arch/arm/dts/stm32mp15-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright : STMicroelectronics 2018
   4  */
   5
   6 / {
   7         aliases {
   8                 gpio0 = &gpioa;
   9                 gpio1 = &gpiob;
  10                 gpio2 = &gpioc;
  11                 gpio3 = &gpiod;
  12                 gpio4 = &gpioe;
  13                 gpio5 = &gpiof;
  14                 gpio6 = &gpiog;
  15                 gpio7 = &gpioh;
  16                 gpio8 = &gpioi;
  17                 gpio9 = &gpioj;
  18                 gpio10 = &gpiok;
  19                 gpio25 = &gpioz;
  20                 pinctrl0 = &pinctrl;
  21                 pinctrl1 = &pinctrl_z;
  22         };
  23
  24         clocks {
  25                 u-boot,dm-pre-reloc;
  26         };
  27
  28         /* need PSCI for sysreset during board_f */
  29         psci {
  30                 u-boot,dm-pre-proper;
  31         };
  32
  33         reboot {
  34                 u-boot,dm-pre-reloc;
  35         };
  36
  37         soc {
  38                 u-boot,dm-pre-reloc;
  39
  40                 ddr: ddr@5a003000 {
  41                         u-boot,dm-pre-reloc;
  42
  43                         compatible = "st,stm32mp1-ddr";
  44
  45                         reg = <0x5A003000 0x550
  46                                0x5A004000 0x234>;
  47
  48                         clocks = <&rcc AXIDCG>,
  49                                  <&rcc DDRC1>,
  50                                  <&rcc DDRC2>,
  51                                  <&rcc DDRPHYC>,
  52                                  <&rcc DDRCAPB>,
  53                                  <&rcc DDRPHYCAPB>;
  54
  55                         clock-names = "axidcg",
  56                                       "ddrc1",
  57                                       "ddrc2",
  58                                       "ddrphyc",
  59                                       "ddrcapb",
  60                                       "ddrphycapb";
  61
  62                         status = "okay";
  63                 };
  64         };
  65 };
  66
  67 &bsec {
  68         u-boot,dm-pre-proper;
  69 };
  70
  71 &clk_csi {
  72         u-boot,dm-pre-reloc;
  73 };
  74
  75 &clk_hsi {
  76         u-boot,dm-pre-reloc;
  77 };
  78
  79 &clk_hse {
  80         u-boot,dm-pre-reloc;
  81 };
  82
  83 &clk_lsi {
  84         u-boot,dm-pre-reloc;
  85 };
  86
  87 &clk_lse {
  88         u-boot,dm-pre-reloc;
  89 };
  90
  91 &gpioa {
  92         u-boot,dm-pre-reloc;
  93 };
  94
  95 &gpiob {
  96         u-boot,dm-pre-reloc;
  97 };
  98
  99 &gpioc {
 100         u-boot,dm-pre-reloc;
 101 };
 102
 103 &gpiod {
 104         u-boot,dm-pre-reloc;
 105 };
 106
 107 &gpioe {
 108         u-boot,dm-pre-reloc;
 109 };
 110
 111 &gpiof {
 112         u-boot,dm-pre-reloc;
 113 };
 114
 115 &gpiog {
 116         u-boot,dm-pre-reloc;
 117 };
 118
 119 &gpioh {
 120         u-boot,dm-pre-reloc;
 121 };
 122
 123 &gpioi {
 124         u-boot,dm-pre-reloc;
 125 };
 126
 127 &gpioj {
 128         u-boot,dm-pre-reloc;
 129 };
 130
 131 &gpiok {
 132         u-boot,dm-pre-reloc;
 133 };
 134
 135 &gpioz {
 136         u-boot,dm-pre-reloc;
 137 };
 138
 139 &iwdg2 {
 140         u-boot,dm-pre-reloc;
 141 };
 142
 143 /* pre-reloc probe = reserve video frame buffer in video_reserve() */
 144 &ltdc {
 145         u-boot,dm-pre-proper;
 146 };
 147
 148 &pinctrl {
 149         u-boot,dm-pre-reloc;
 150 };
 151
 152 &pinctrl_z {
 153         u-boot,dm-pre-reloc;
 154 };
 155
 156 &pwr_regulators {
 157         u-boot,dm-pre-reloc;
 158 };
 159
 160 &rcc {
 161         u-boot,dm-pre-reloc;
 162         #address-cells = <1>;
 163         #size-cells = <0>;
 164 };
 165
 166 &sdmmc1 {
 167         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 168 };
 169
 170 &sdmmc2 {
 171         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 172 };
 173
 174 &sdmmc3 {
 175         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
 176 };
 177
 178 &usbotg_hs {
 179         compatible = "st,stm32mp1-hsotg", "snps,dwc2";
 180 };