arch/arm/dts/sama5d2.dtsi

   1 #include "skeleton.dtsi"
   2
   3 / {
   4         model = "Atmel SAMA5D2 family SoC";
   5         compatible = "atmel,sama5d2";
   6
   7         aliases {
   8                 spi0 = &spi0;
   9                 spi1 = &qspi0;
  10                 i2c0 = &i2c0;
  11                 i2c1 = &i2c1;
  12         };
  13
  14         clocks {
  15                 slow_xtal: slow_xtal {
  16                         compatible = "fixed-clock";
  17                         #clock-cells = <0>;
  18                         clock-frequency = <0>;
  19                 };
  20
  21                 main_xtal: main_xtal {
  22                         compatible = "fixed-clock";
  23                         #clock-cells = <0>;
  24                         clock-frequency = <0>;
  25                 };
  26         };
  27
  28         ahb {
  29                 compatible = "simple-bus";
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 u-boot,dm-pre-reloc;
  33
  34                 usb1: ohci@00400000 {
  35                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  36                         reg = <0x00400000 0x100000>;
  37                         clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
  38                         clock-names = "ohci_clk", "hclk", "uhpck";
  39                         status = "disabled";
  40                 };
  41
  42                 usb2: ehci@00500000 {
  43                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  44                         reg = <0x00500000 0x100000>;
  45                         clocks = <&utmi>, <&uhphs_clk>;
  46                         clock-names = "usb_clk", "ehci_clk";
  47                         status = "disabled";
  48                 };
  49
  50                 sdmmc0: sdio-host@a0000000 {
  51                         compatible = "atmel,sama5d2-sdhci";
  52                         reg = <0xa0000000 0x300>;
  53                         clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
  54                         clock-names = "hclock", "multclk", "baseclk";
  55                         status = "disabled";
  56                 };
  57
  58                 sdmmc1: sdio-host@b0000000 {
  59                         compatible = "atmel,sama5d2-sdhci";
  60                         reg = <0xb0000000 0x300>;
  61                         clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
  62                         clock-names = "hclock", "multclk", "baseclk";
  63                         status = "disabled";
  64                 };
  65
  66                 apb {
  67                         compatible = "simple-bus";
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         u-boot,dm-pre-reloc;
  71
  72                         pmc: pmc@f0014000 {
  73                                 compatible = "atmel,sama5d2-pmc", "syscon";
  74                                 reg = <0xf0014000 0x160>;
  75                                 #address-cells = <1>;
  76                                 #size-cells = <0>;
  77                                 #interrupt-cells = <1>;
  78                                 u-boot,dm-pre-reloc;
  79
  80                                 main: mainck {
  81                                         compatible = "atmel,at91sam9x5-clk-main";
  82                                         #clock-cells = <0>;
  83                                         u-boot,dm-pre-reloc;
  84                                 };
  85
  86                                 plla: pllack@0 {
  87                                         compatible = "atmel,sama5d3-clk-pll";
  88                                         #clock-cells = <0>;
  89                                         clocks = <&main>;
  90                                         reg = <0>;
  91                                         atmel,clk-input-range = <12000000 12000000>;
  92                                         #atmel,pll-clk-output-range-cells = <4>;
  93                                         atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
  94                                         u-boot,dm-pre-reloc;
  95                                 };
  96
  97                                 plladiv: plladivck {
  98                                         compatible = "atmel,at91sam9x5-clk-plldiv";
  99                                         #clock-cells = <0>;
 100                                         clocks = <&plla>;
 101                                 };
 102
 103                                 audio_pll_frac: audiopll_fracck {
 104                                         compatible = "atmel,sama5d2-clk-audio-pll-frac";
 105                                         #clock-cells = <0>;
 106                                         clocks = <&main>;
 107                                 };
 108
 109                                 audio_pll_pad: audiopll_padck {
 110                                         compatible = "atmel,sama5d2-clk-audio-pll-pad";
 111                                         #clock-cells = <0>;
 112                                         clocks = <&audio_pll_frac>;
 113                                 };
 114
 115                                 audio_pll_pmc: audiopll_pmcck {
 116                                         compatible = "atmel,sama5d2-clk-audio-pll-pmc";
 117                                         #clock-cells = <0>;
 118                                         clocks = <&audio_pll_frac>;
 119                                 };
 120
 121                                 utmi: utmick {
 122                                         compatible = "atmel,at91sam9x5-clk-utmi";
 123                                         #clock-cells = <0>;
 124                                         clocks = <&main>;
 125                                         regmap-sfr = <&sfr>;
 126                                         u-boot,dm-pre-reloc;
 127                                 };
 128
 129                                 mck: masterck {
 130                                         compatible = "atmel,at91sam9x5-clk-master";
 131                                         #clock-cells = <0>;
 132                                         clocks = <&main>, <&plladiv>, <&utmi>;
 133                                         atmel,clk-output-range = <124000000 166000000>;
 134                                         atmel,clk-divisors = <1 2 4 3>;
 135                                         u-boot,dm-pre-reloc;
 136                                 };
 137
 138                                 h32ck: h32mxck {
 139                                         #clock-cells = <0>;
 140                                         compatible = "atmel,sama5d4-clk-h32mx";
 141                                         clocks = <&mck>;
 142                                         u-boot,dm-pre-reloc;
 143                                 };
 144
 145                                 usb: usbck {
 146                                         compatible = "atmel,at91sam9x5-clk-usb";
 147                                         #clock-cells = <0>;
 148                                         clocks = <&plladiv>, <&utmi>;
 149                                 };
 150
 151                                 prog: progck {
 152                                         compatible = "atmel,at91sam9x5-clk-programmable";
 153                                         #address-cells = <1>;
 154                                         #size-cells = <0>;
 155                                         interrupt-parent = <&pmc>;
 156                                         clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
 157
 158                                         prog0: prog@0 {
 159                                                 #clock-cells = <0>;
 160                                                 reg = <0>;
 161                                         };
 162
 163                                         prog1: prog@1 {
 164                                                 #clock-cells = <0>;
 165                                                 reg = <1>;
 166                                         };
 167
 168                                         prog2: prog@2 {
 169                                                 #clock-cells = <0>;
 170                                                 reg = <2>;
 171                                         };
 172                                 };
 173
 174                                 systemck {
 175                                         compatible = "atmel,at91rm9200-clk-system";
 176                                         #address-cells = <1>;
 177                                         #size-cells = <0>;
 178
 179                                         ddrck: ddrck@2 {
 180                                                 #clock-cells = <0>;
 181                                                 reg = <2>;
 182                                                 clocks = <&mck>;
 183                                         };
 184
 185                                         lcdck: lcdck@3 {
 186                                                 #clock-cells = <0>;
 187                                                 reg = <3>;
 188                                                 clocks = <&mck>;
 189                                         };
 190
 191                                         uhpck: uhpck@6 {
 192                                                 #clock-cells = <0>;
 193                                                 reg = <6>;
 194                                                 clocks = <&usb>;
 195                                         };
 196
 197                                         udpck: udpck@7 {
 198                                                 #clock-cells = <0>;
 199                                                 reg = <7>;
 200                                                 clocks = <&usb>;
 201                                         };
 202
 203                                         pck0: pck0@8 {
 204                                                 #clock-cells = <0>;
 205                                                 reg = <8>;
 206                                                 clocks = <&prog0>;
 207                                         };
 208
 209                                         pck1: pck1@9 {
 210                                                 #clock-cells = <0>;
 211                                                 reg = <9>;
 212                                                 clocks = <&prog1>;
 213                                         };
 214
 215                                         pck2: pck2@10 {
 216                                                 #clock-cells = <0>;
 217                                                 reg = <10>;
 218                                                 clocks = <&prog2>;
 219                                         };
 220
 221                                         iscck: iscck@18 {
 222                                                 #clock-cells = <0>;
 223                                                 reg = <18>;
 224                                                 clocks = <&mck>;
 225                                         };
 226                                 };
 227
 228                                 periph32ck {
 229                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 230                                         #address-cells = <1>;
 231                                         #size-cells = <0>;
 232                                         clocks = <&h32ck>;
 233                                         u-boot,dm-pre-reloc;
 234
 235                                         macb0_clk: macb0_clk@5 {
 236                                                 #clock-cells = <0>;
 237                                                 reg = <5>;
 238                                                 atmel,clk-output-range = <0 83000000>;
 239                                         };
 240
 241                                         tdes_clk: tdes_clk@11 {
 242                                                 #clock-cells = <0>;
 243                                                 reg = <11>;
 244                                                 atmel,clk-output-range = <0 83000000>;
 245                                         };
 246
 247                                         matrix1_clk: matrix1_clk@14 {
 248                                                 #clock-cells = <0>;
 249                                                 reg = <14>;
 250                                         };
 251
 252                                         hsmc_clk: hsmc_clk@17 {
 253                                                 #clock-cells = <0>;
 254                                                 reg = <17>;
 255                                         };
 256
 257                                         pioA_clk: pioA_clk@18 {
 258                                                 #clock-cells = <0>;
 259                                                 reg = <18>;
 260                                                 atmel,clk-output-range = <0 83000000>;
 261                                                 u-boot,dm-pre-reloc;
 262                                         };
 263
 264                                         flx0_clk: flx0_clk@19 {
 265                                                 #clock-cells = <0>;
 266                                                 reg = <19>;
 267                                                 atmel,clk-output-range = <0 83000000>;
 268                                         };
 269
 270                                         flx1_clk: flx1_clk@20 {
 271                                                 #clock-cells = <0>;
 272                                                 reg = <20>;
 273                                                 atmel,clk-output-range = <0 83000000>;
 274                                         };
 275
 276                                         flx2_clk: flx2_clk@21 {
 277                                                 #clock-cells = <0>;
 278                                                 reg = <21>;
 279                                                 atmel,clk-output-range = <0 83000000>;
 280                                         };
 281
 282                                         flx3_clk: flx3_clk@22 {
 283                                                 #clock-cells = <0>;
 284                                                 reg = <22>;
 285                                                 atmel,clk-output-range = <0 83000000>;
 286                                         };
 287
 288                                         flx4_clk: flx4_clk@23 {
 289                                                 #clock-cells = <0>;
 290                                                 reg = <23>;
 291                                                 atmel,clk-output-range = <0 83000000>;
 292                                         };
 293
 294                                         uart0_clk: uart0_clk@24 {
 295                                                 #clock-cells = <0>;
 296                                                 reg = <24>;
 297                                                 atmel,clk-output-range = <0 83000000>;
 298                                         };
 299
 300                                         uart1_clk: uart1_clk@25 {
 301                                                 #clock-cells = <0>;
 302                                                 reg = <25>;
 303                                                 atmel,clk-output-range = <0 83000000>;
 304                                                 u-boot,dm-pre-reloc;
 305                                         };
 306
 307                                         uart2_clk: uart2_clk@26 {
 308                                                 #clock-cells = <0>;
 309                                                 reg = <26>;
 310                                                 atmel,clk-output-range = <0 83000000>;
 311                                         };
 312
 313                                         uart3_clk: uart3_clk@27 {
 314                                                 #clock-cells = <0>;
 315                                                 reg = <27>;
 316                                                 atmel,clk-output-range = <0 83000000>;
 317                                         };
 318
 319                                         uart4_clk: uart4_clk@28 {
 320                                                 #clock-cells = <0>;
 321                                                 reg = <28>;
 322                                                 atmel,clk-output-range = <0 83000000>;
 323                                         };
 324
 325                                         twi0_clk: twi0_clk@29 {
 326                                                 reg = <29>;
 327                                                 #clock-cells = <0>;
 328                                                 atmel,clk-output-range = <0 83000000>;
 329                                         };
 330
 331                                         twi1_clk: twi1_clk@30 {
 332                                                 #clock-cells = <0>;
 333                                                 reg = <30>;
 334                                                 atmel,clk-output-range = <0 83000000>;
 335                                         };
 336
 337                                         spi0_clk: spi0_clk@33 {
 338                                                 #clock-cells = <0>;
 339                                                 reg = <33>;
 340                                                 atmel,clk-output-range = <0 83000000>;
 341                                                 u-boot,dm-pre-reloc;
 342                                         };
 343
 344                                         spi1_clk: spi1_clk@34 {
 345                                                 #clock-cells = <0>;
 346                                                 reg = <34>;
 347                                                 atmel,clk-output-range = <0 83000000>;
 348                                         };
 349
 350                                         tcb0_clk: tcb0_clk@35 {
 351                                                 #clock-cells = <0>;
 352                                                 reg = <35>;
 353                                                 atmel,clk-output-range = <0 83000000>;
 354                                         };
 355
 356                                         tcb1_clk: tcb1_clk@36 {
 357                                                 #clock-cells = <0>;
 358                                                 reg = <36>;
 359                                                 atmel,clk-output-range = <0 83000000>;
 360                                         };
 361
 362                                         pwm_clk: pwm_clk@38 {
 363                                                 #clock-cells = <0>;
 364                                                 reg = <38>;
 365                                                 atmel,clk-output-range = <0 83000000>;
 366                                         };
 367
 368                                         adc_clk: adc_clk@40 {
 369                                                 #clock-cells = <0>;
 370                                                 reg = <40>;
 371                                                 atmel,clk-output-range = <0 83000000>;
 372                                         };
 373
 374                                         uhphs_clk: uhphs_clk@41 {
 375                                                 #clock-cells = <0>;
 376                                                 reg = <41>;
 377                                                 atmel,clk-output-range = <0 83000000>;
 378                                         };
 379
 380                                         udphs_clk: udphs_clk@42 {
 381                                                 #clock-cells = <0>;
 382                                                 reg = <42>;
 383                                                 atmel,clk-output-range = <0 83000000>;
 384                                         };
 385
 386                                         ssc0_clk: ssc0_clk@43 {
 387                                                 #clock-cells = <0>;
 388                                                 reg = <43>;
 389                                                 atmel,clk-output-range = <0 83000000>;
 390                                         };
 391
 392                                         ssc1_clk: ssc1_clk@44 {
 393                                                 #clock-cells = <0>;
 394                                                 reg = <44>;
 395                                                 atmel,clk-output-range = <0 83000000>;
 396                                         };
 397
 398                                         trng_clk: trng_clk@47 {
 399                                                 #clock-cells = <0>;
 400                                                 reg = <47>;
 401                                                 atmel,clk-output-range = <0 83000000>;
 402                                         };
 403
 404                                         pdmic_clk: pdmic_clk@48 {
 405                                                 #clock-cells = <0>;
 406                                                 reg = <48>;
 407                                                 atmel,clk-output-range = <0 83000000>;
 408                                         };
 409
 410                                         i2s0_clk: i2s0_clk@54 {
 411                                                 #clock-cells = <0>;
 412                                                 reg = <54>;
 413                                                 atmel,clk-output-range = <0 83000000>;
 414                                         };
 415
 416                                         i2s1_clk: i2s1_clk@55 {
 417                                                 #clock-cells = <0>;
 418                                                 reg = <55>;
 419                                                 atmel,clk-output-range = <0 83000000>;
 420                                         };
 421
 422                                         can0_clk: can0_clk@56 {
 423                                                 #clock-cells = <0>;
 424                                                 reg = <56>;
 425                                                 atmel,clk-output-range = <0 83000000>;
 426                                         };
 427
 428                                         can1_clk: can1_clk@57 {
 429                                                 #clock-cells = <0>;
 430                                                 reg = <57>;
 431                                                 atmel,clk-output-range = <0 83000000>;
 432                                         };
 433
 434                                         classd_clk: classd_clk@59 {
 435                                                 #clock-cells = <0>;
 436                                                 reg = <59>;
 437                                                 atmel,clk-output-range = <0 83000000>;
 438                                         };
 439                                 };
 440
 441                                 periph64ck {
 442                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 443                                         #address-cells = <1>;
 444                                         #size-cells = <0>;
 445                                         clocks = <&mck>;
 446                                         u-boot,dm-pre-reloc;
 447
 448                                         dma0_clk: dma0_clk@6 {
 449                                                 #clock-cells = <0>;
 450                                                 reg = <6>;
 451                                         };
 452
 453                                         dma1_clk: dma1_clk@7 {
 454                                                 #clock-cells = <0>;
 455                                                 reg = <7>;
 456                                         };
 457
 458                                         aes_clk: aes_clk@9 {
 459                                                 #clock-cells = <0>;
 460                                                 reg = <9>;
 461                                         };
 462
 463                                         aesb_clk: aesb_clk@10 {
 464                                                 #clock-cells = <0>;
 465                                                 reg = <10>;
 466                                         };
 467
 468                                         sha_clk: sha_clk@12 {
 469                                                 #clock-cells = <0>;
 470                                                 reg = <12>;
 471                                         };
 472
 473                                         mpddr_clk: mpddr_clk@13 {
 474                                                 #clock-cells = <0>;
 475                                                 reg = <13>;
 476                                         };
 477
 478                                         matrix0_clk: matrix0_clk@15 {
 479                                                 #clock-cells = <0>;
 480                                                 reg = <15>;
 481                                         };
 482
 483                                         sdmmc0_hclk: sdmmc0_hclk@31 {
 484                                                 #clock-cells = <0>;
 485                                                 reg = <31>;
 486                                                 u-boot,dm-pre-reloc;
 487                                         };
 488
 489                                         sdmmc1_hclk: sdmmc1_hclk@32 {
 490                                                 #clock-cells = <0>;
 491                                                 reg = <32>;
 492                                                 u-boot,dm-pre-reloc;
 493                                         };
 494
 495                                         lcdc_clk: lcdc_clk@45 {
 496                                                 #clock-cells = <0>;
 497                                                 reg = <45>;
 498                                         };
 499
 500                                         isc_clk: isc_clk@46 {
 501                                                 #clock-cells = <0>;
 502                                                 reg = <46>;
 503                                         };
 504
 505                                         qspi0_clk: qspi0_clk@52 {
 506                                                 #clock-cells = <0>;
 507                                                 reg = <52>;
 508                                         };
 509
 510                                         qspi1_clk: qspi1_clk@53 {
 511                                                 #clock-cells = <0>;
 512                                                 reg = <53>;
 513                                         };
 514                                 };
 515
 516                                 gck {
 517                                         compatible = "atmel,sama5d2-clk-generated";
 518                                         #address-cells = <1>;
 519                                         #size-cells = <0>;
 520                                         interrupt-parent = <&pmc>;
 521                                         clocks = <&main>, <&plla>, <&utmi>, <&mck>;
 522                                         u-boot,dm-pre-reloc;
 523
 524                                         sdmmc0_gclk: sdmmc0_gclk@31 {
 525                                                 #clock-cells = <0>;
 526                                                 reg = <31>;
 527                                                 u-boot,dm-pre-reloc;
 528                                         };
 529
 530                                         sdmmc1_gclk: sdmmc1_gclk@32 {
 531                                                 #clock-cells = <0>;
 532                                                 reg = <32>;
 533                                                 u-boot,dm-pre-reloc;
 534                                         };
 535
 536                                         tcb0_gclk: tcb0_gclk@35 {
 537                                                 #clock-cells = <0>;
 538                                                 reg = <35>;
 539                                                 atmel,clk-output-range = <0 83000000>;
 540                                         };
 541
 542                                         tcb1_gclk: tcb1_gclk@36 {
 543                                                 #clock-cells = <0>;
 544                                                 reg = <36>;
 545                                                 atmel,clk-output-range = <0 83000000>;
 546                                         };
 547
 548                                         pwm_gclk: pwm_gclk@38 {
 549                                                 #clock-cells = <0>;
 550                                                 reg = <38>;
 551                                                 atmel,clk-output-range = <0 83000000>;
 552                                         };
 553
 554                                         pdmic_gclk: pdmic_gclk@48 {
 555                                                 #clock-cells = <0>;
 556                                                 reg = <48>;
 557                                         };
 558
 559                                         i2s0_gclk: i2s0_gclk@54 {
 560                                                 #clock-cells = <0>;
 561                                                 reg = <54>;
 562                                         };
 563
 564                                         i2s1_gclk: i2s1_gclk@55 {
 565                                                 #clock-cells = <0>;
 566                                                 reg = <55>;
 567                                         };
 568
 569                                         can0_gclk: can0_gclk@56 {
 570                                                 #clock-cells = <0>;
 571                                                 reg = <56>;
 572                                                 atmel,clk-output-range = <0 80000000>;
 573                                         };
 574
 575                                         can1_gclk: can1_gclk@57 {
 576                                                 #clock-cells = <0>;
 577                                                 reg = <57>;
 578                                                 atmel,clk-output-range = <0 80000000>;
 579                                         };
 580
 581                                         classd_gclk: classd_gclk@59 {
 582                                                 #clock-cells = <0>;
 583                                                 reg = <59>;
 584                                                 atmel,clk-output-range = <0 100000000>;
 585                                         };
 586                                 };
 587                         };
 588
 589                         qspi0: spi@f0020000 {
 590                                 compatible = "atmel,sama5d2-qspi";
 591                                 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
 592                                 reg-names = "qspi_base", "qspi_mmap";
 593                                 #address-cells = <1>;
 594                                 #size-cells = <0>;
 595                                 clocks = <&qspi0_clk>;
 596                                 status = "disabled";
 597                         };
 598
 599                         spi0: spi@f8000000 {
 600                                 compatible = "atmel,at91rm9200-spi";
 601                                 reg = <0xf8000000 0x100>;
 602                                 clocks = <&spi0_clk>;
 603                                 clock-names = "spi_clk";
 604                                 #address-cells = <1>;
 605                                 #size-cells = <0>;
 606                                 status = "disabled";
 607                         };
 608
 609                         macb0: ethernet@f8008000 {
 610                                 compatible = "cdns,macb";
 611                                 reg = <0xf8008000 0x1000>;
 612                                 #address-cells = <1>;
 613                                 #size-cells = <0>;
 614                                 clocks = <&macb0_clk>, <&macb0_clk>;
 615                                 clock-names = "hclk", "pclk";
 616                                 status = "disabled";
 617                         };
 618
 619                         uart1: serial@f8020000 {
 620                                 compatible = "atmel,at91sam9260-usart";
 621                                 reg = <0xf8020000 0x100>;
 622                                 clocks = <&uart1_clk>;
 623                                 clock-names = "usart";
 624                                 status = "disabled";
 625                         };
 626
 627                         i2c0: i2c@f8028000 {
 628                                 compatible = "atmel,sama5d2-i2c";
 629                                 reg = <0xf8028000 0x100>;
 630                                 #address-cells = <1>;
 631                                 #size-cells = <0>;
 632                                 clocks = <&twi0_clk>;
 633                                 status = "disabled";
 634                         };
 635
 636                         rstc@f8048000 {
 637                                 compatible = "atmel,sama5d3-rstc";
 638                                 reg = <0xf8048000 0x10>;
 639                                 clocks = <&clk32k>;
 640                         };
 641
 642                         shdwc@f8048010 {
 643                                 compatible = "atmel,sama5d2-shdwc";
 644                                 reg = <0xf8048010 0x10>;
 645                                 clocks = <&clk32k>;
 646                                 #address-cells = <1>;
 647                                 #size-cells = <0>;
 648                                 atmel,wakeup-rtc-timer;
 649                         };
 650
 651                         pit: timer@f8048030 {
 652                                 compatible = "atmel,at91sam9260-pit";
 653                                 reg = <0xf8048030 0x10>;
 654                                 clocks = <&h32ck>;
 655                         };
 656
 657                         watchdog@f8048040 {
 658                                 compatible = "atmel,sama5d4-wdt";
 659                                 reg = <0xf8048040 0x10>;
 660                                 clocks = <&clk32k>;
 661                                 status = "disabled";
 662                         };
 663
 664                         sfr: sfr@f8030000 {
 665                                 compatible = "atmel,sama5d2-sfr", "syscon";
 666                                 reg = <0xf8030000 0x98>;
 667                         };
 668
 669                         sckc@f8048050 {
 670                                 compatible = "atmel,at91sam9x5-sckc";
 671                                 reg = <0xf8048050 0x4>;
 672
 673                                 slow_rc_osc: slow_rc_osc {
 674                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
 675                                         #clock-cells = <0>;
 676                                         clock-frequency = <32768>;
 677                                         clock-accuracy = <250000000>;
 678                                         atmel,startup-time-usec = <75>;
 679                                 };
 680
 681                                 slow_osc: slow_osc {
 682                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
 683                                         #clock-cells = <0>;
 684                                         clocks = <&slow_xtal>;
 685                                         atmel,startup-time-usec = <1200000>;
 686                                 };
 687
 688                                 clk32k: slowck {
 689                                         compatible = "atmel,at91sam9x5-clk-slow";
 690                                         #clock-cells = <0>;
 691                                         clocks = <&slow_rc_osc &slow_osc>;
 692                                 };
 693                         };
 694
 695                         spi1: spi@fc000000 {
 696                                 compatible = "atmel,at91rm9200-spi";
 697                                 reg = <0xfc000000 0x100>;
 698                                 #address-cells = <1>;
 699                                 #size-cells = <0>;
 700                                 status = "disabled";
 701                         };
 702
 703                         i2c1: i2c@fc028000 {
 704                                 compatible = "atmel,sama5d2-i2c";
 705                                 reg = <0xfc028000 0x100>;
 706                                 #address-cells = <1>;
 707                                 #size-cells = <0>;
 708                                 clocks = <&twi1_clk>;
 709                                 status = "disabled";
 710                         };
 711
 712                         pioA: gpio@fc038000 {
 713                                 compatible = "atmel,sama5d2-gpio";
 714                                 reg = <0xfc038000 0x600>;
 715                                 clocks = <&pioA_clk>;
 716                                 gpio-controller;
 717                                 #gpio-cells = <2>;
 718                                 u-boot,dm-pre-reloc;
 719
 720                                 pinctrl {
 721                                         compatible = "atmel,sama5d2-pinctrl";
 722                                         u-boot,dm-pre-reloc;
 723                                 };
 724                         };
 725                 };
 726         };
 727 };