arch/arm/dts/sama5d2.dtsi

   1 #include "skeleton.dtsi"
   2
   3 / {
   4         model = "Atmel SAMA5D2 family SoC";
   5         compatible = "atmel,sama5d2";
   6
   7         aliases {
   8                 spi0 = &spi0;
   9                 spi1 = &qspi0;
  10                 i2c0 = &i2c0;
  11                 i2c1 = &i2c1;
  12         };
  13
  14         clocks {
  15                 slow_xtal: slow_xtal {
  16                         compatible = "fixed-clock";
  17                         #clock-cells = <0>;
  18                         clock-frequency = <0>;
  19                 };
  20
  21                 main_xtal: main_xtal {
  22                         compatible = "fixed-clock";
  23                         #clock-cells = <0>;
  24                         clock-frequency = <0>;
  25                 };
  26         };
  27
  28         ahb {
  29                 compatible = "simple-bus";
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 u-boot,dm-pre-reloc;
  33
  34                 usb1: ohci@00400000 {
  35                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  36                         reg = <0x00400000 0x100000>;
  37                         clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
  38                         clock-names = "ohci_clk", "hclk", "uhpck";
  39                         status = "disabled";
  40                 };
  41
  42                 usb2: ehci@00500000 {
  43                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  44                         reg = <0x00500000 0x100000>;
  45                         clocks = <&utmi>, <&uhphs_clk>;
  46                         clock-names = "usb_clk", "ehci_clk";
  47                         status = "disabled";
  48                 };
  49
  50                 sdmmc0: sdio-host@a0000000 {
  51                         compatible = "atmel,sama5d2-sdhci";
  52                         reg = <0xa0000000 0x300>;
  53                         clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
  54                         clock-names = "hclock", "multclk", "baseclk";
  55                         status = "disabled";
  56                 };
  57
  58                 sdmmc1: sdio-host@b0000000 {
  59                         compatible = "atmel,sama5d2-sdhci";
  60                         reg = <0xb0000000 0x300>;
  61                         clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
  62                         clock-names = "hclock", "multclk", "baseclk";
  63                         status = "disabled";
  64                 };
  65
  66                 apb {
  67                         compatible = "simple-bus";
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         u-boot,dm-pre-reloc;
  71
  72                         pmc: pmc@f0014000 {
  73                                 compatible = "atmel,sama5d2-pmc", "syscon";
  74                                 reg = <0xf0014000 0x160>;
  75                                 #address-cells = <1>;
  76                                 #size-cells = <0>;
  77                                 #interrupt-cells = <1>;
  78                                 u-boot,dm-pre-reloc;
  79
  80                                 main: mainck {
  81                                         compatible = "atmel,at91sam9x5-clk-main";
  82                                         #clock-cells = <0>;
  83                                         u-boot,dm-pre-reloc;
  84                                 };
  85
  86                                 plla: pllack@0 {
  87                                         compatible = "atmel,sama5d3-clk-pll";
  88                                         #clock-cells = <0>;
  89                                         clocks = <&main>;
  90                                         reg = <0>;
  91                                         atmel,clk-input-range = <12000000 12000000>;
  92                                         #atmel,pll-clk-output-range-cells = <4>;
  93                                         atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
  94                                         u-boot,dm-pre-reloc;
  95                                 };
  96
  97                                 plladiv: plladivck {
  98                                         compatible = "atmel,at91sam9x5-clk-plldiv";
  99                                         #clock-cells = <0>;
 100                                         clocks = <&plla>;
 101                                 };
 102
 103                                 audio_pll_frac: audiopll_fracck {
 104                                         compatible = "atmel,sama5d2-clk-audio-pll-frac";
 105                                         #clock-cells = <0>;
 106                                         clocks = <&main>;
 107                                 };
 108
 109                                 audio_pll_pad: audiopll_padck {
 110                                         compatible = "atmel,sama5d2-clk-audio-pll-pad";
 111                                         #clock-cells = <0>;
 112                                         clocks = <&audio_pll_frac>;
 113                                 };
 114
 115                                 audio_pll_pmc: audiopll_pmcck {
 116                                         compatible = "atmel,sama5d2-clk-audio-pll-pmc";
 117                                         #clock-cells = <0>;
 118                                         clocks = <&audio_pll_frac>;
 119                                 };
 120
 121                                 utmi: utmick {
 122                                         compatible = "atmel,at91sam9x5-clk-utmi";
 123                                         #clock-cells = <0>;
 124                                         clocks = <&main>;
 125                                         u-boot,dm-pre-reloc;
 126                                 };
 127
 128                                 mck: masterck {
 129                                         compatible = "atmel,at91sam9x5-clk-master";
 130                                         #clock-cells = <0>;
 131                                         clocks = <&main>, <&plladiv>, <&utmi>;
 132                                         atmel,clk-output-range = <124000000 166000000>;
 133                                         atmel,clk-divisors = <1 2 4 3>;
 134                                         u-boot,dm-pre-reloc;
 135                                 };
 136
 137                                 h32ck: h32mxck {
 138                                         #clock-cells = <0>;
 139                                         compatible = "atmel,sama5d4-clk-h32mx";
 140                                         clocks = <&mck>;
 141                                         u-boot,dm-pre-reloc;
 142                                 };
 143
 144                                 usb: usbck {
 145                                         compatible = "atmel,at91sam9x5-clk-usb";
 146                                         #clock-cells = <0>;
 147                                         clocks = <&plladiv>, <&utmi>;
 148                                 };
 149
 150                                 prog: progck {
 151                                         compatible = "atmel,at91sam9x5-clk-programmable";
 152                                         #address-cells = <1>;
 153                                         #size-cells = <0>;
 154                                         interrupt-parent = <&pmc>;
 155                                         clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
 156
 157                                         prog0: prog@0 {
 158                                                 #clock-cells = <0>;
 159                                                 reg = <0>;
 160                                         };
 161
 162                                         prog1: prog@1 {
 163                                                 #clock-cells = <0>;
 164                                                 reg = <1>;
 165                                         };
 166
 167                                         prog2: prog@2 {
 168                                                 #clock-cells = <0>;
 169                                                 reg = <2>;
 170                                         };
 171                                 };
 172
 173                                 systemck {
 174                                         compatible = "atmel,at91rm9200-clk-system";
 175                                         #address-cells = <1>;
 176                                         #size-cells = <0>;
 177
 178                                         ddrck: ddrck@2 {
 179                                                 #clock-cells = <0>;
 180                                                 reg = <2>;
 181                                                 clocks = <&mck>;
 182                                         };
 183
 184                                         lcdck: lcdck@3 {
 185                                                 #clock-cells = <0>;
 186                                                 reg = <3>;
 187                                                 clocks = <&mck>;
 188                                         };
 189
 190                                         uhpck: uhpck@6 {
 191                                                 #clock-cells = <0>;
 192                                                 reg = <6>;
 193                                                 clocks = <&usb>;
 194                                         };
 195
 196                                         udpck: udpck@7 {
 197                                                 #clock-cells = <0>;
 198                                                 reg = <7>;
 199                                                 clocks = <&usb>;
 200                                         };
 201
 202                                         pck0: pck0@8 {
 203                                                 #clock-cells = <0>;
 204                                                 reg = <8>;
 205                                                 clocks = <&prog0>;
 206                                         };
 207
 208                                         pck1: pck1@9 {
 209                                                 #clock-cells = <0>;
 210                                                 reg = <9>;
 211                                                 clocks = <&prog1>;
 212                                         };
 213
 214                                         pck2: pck2@10 {
 215                                                 #clock-cells = <0>;
 216                                                 reg = <10>;
 217                                                 clocks = <&prog2>;
 218                                         };
 219
 220                                         iscck: iscck@18 {
 221                                                 #clock-cells = <0>;
 222                                                 reg = <18>;
 223                                                 clocks = <&mck>;
 224                                         };
 225                                 };
 226
 227                                 periph32ck {
 228                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 229                                         #address-cells = <1>;
 230                                         #size-cells = <0>;
 231                                         clocks = <&h32ck>;
 232                                         u-boot,dm-pre-reloc;
 233
 234                                         macb0_clk: macb0_clk@5 {
 235                                                 #clock-cells = <0>;
 236                                                 reg = <5>;
 237                                                 atmel,clk-output-range = <0 83000000>;
 238                                         };
 239
 240                                         tdes_clk: tdes_clk@11 {
 241                                                 #clock-cells = <0>;
 242                                                 reg = <11>;
 243                                                 atmel,clk-output-range = <0 83000000>;
 244                                         };
 245
 246                                         matrix1_clk: matrix1_clk@14 {
 247                                                 #clock-cells = <0>;
 248                                                 reg = <14>;
 249                                         };
 250
 251                                         hsmc_clk: hsmc_clk@17 {
 252                                                 #clock-cells = <0>;
 253                                                 reg = <17>;
 254                                         };
 255
 256                                         pioA_clk: pioA_clk@18 {
 257                                                 #clock-cells = <0>;
 258                                                 reg = <18>;
 259                                                 atmel,clk-output-range = <0 83000000>;
 260                                                 u-boot,dm-pre-reloc;
 261                                         };
 262
 263                                         flx0_clk: flx0_clk@19 {
 264                                                 #clock-cells = <0>;
 265                                                 reg = <19>;
 266                                                 atmel,clk-output-range = <0 83000000>;
 267                                         };
 268
 269                                         flx1_clk: flx1_clk@20 {
 270                                                 #clock-cells = <0>;
 271                                                 reg = <20>;
 272                                                 atmel,clk-output-range = <0 83000000>;
 273                                         };
 274
 275                                         flx2_clk: flx2_clk@21 {
 276                                                 #clock-cells = <0>;
 277                                                 reg = <21>;
 278                                                 atmel,clk-output-range = <0 83000000>;
 279                                         };
 280
 281                                         flx3_clk: flx3_clk@22 {
 282                                                 #clock-cells = <0>;
 283                                                 reg = <22>;
 284                                                 atmel,clk-output-range = <0 83000000>;
 285                                         };
 286
 287                                         flx4_clk: flx4_clk@23 {
 288                                                 #clock-cells = <0>;
 289                                                 reg = <23>;
 290                                                 atmel,clk-output-range = <0 83000000>;
 291                                         };
 292
 293                                         uart0_clk: uart0_clk@24 {
 294                                                 #clock-cells = <0>;
 295                                                 reg = <24>;
 296                                                 atmel,clk-output-range = <0 83000000>;
 297                                         };
 298
 299                                         uart1_clk: uart1_clk@25 {
 300                                                 #clock-cells = <0>;
 301                                                 reg = <25>;
 302                                                 atmel,clk-output-range = <0 83000000>;
 303                                                 u-boot,dm-pre-reloc;
 304                                         };
 305
 306                                         uart2_clk: uart2_clk@26 {
 307                                                 #clock-cells = <0>;
 308                                                 reg = <26>;
 309                                                 atmel,clk-output-range = <0 83000000>;
 310                                         };
 311
 312                                         uart3_clk: uart3_clk@27 {
 313                                                 #clock-cells = <0>;
 314                                                 reg = <27>;
 315                                                 atmel,clk-output-range = <0 83000000>;
 316                                         };
 317
 318                                         uart4_clk: uart4_clk@28 {
 319                                                 #clock-cells = <0>;
 320                                                 reg = <28>;
 321                                                 atmel,clk-output-range = <0 83000000>;
 322                                         };
 323
 324                                         twi0_clk: twi0_clk@29 {
 325                                                 reg = <29>;
 326                                                 #clock-cells = <0>;
 327                                                 atmel,clk-output-range = <0 83000000>;
 328                                         };
 329
 330                                         twi1_clk: twi1_clk@30 {
 331                                                 #clock-cells = <0>;
 332                                                 reg = <30>;
 333                                                 atmel,clk-output-range = <0 83000000>;
 334                                         };
 335
 336                                         spi0_clk: spi0_clk@33 {
 337                                                 #clock-cells = <0>;
 338                                                 reg = <33>;
 339                                                 atmel,clk-output-range = <0 83000000>;
 340                                                 u-boot,dm-pre-reloc;
 341                                         };
 342
 343                                         spi1_clk: spi1_clk@34 {
 344                                                 #clock-cells = <0>;
 345                                                 reg = <34>;
 346                                                 atmel,clk-output-range = <0 83000000>;
 347                                         };
 348
 349                                         tcb0_clk: tcb0_clk@35 {
 350                                                 #clock-cells = <0>;
 351                                                 reg = <35>;
 352                                                 atmel,clk-output-range = <0 83000000>;
 353                                         };
 354
 355                                         tcb1_clk: tcb1_clk@36 {
 356                                                 #clock-cells = <0>;
 357                                                 reg = <36>;
 358                                                 atmel,clk-output-range = <0 83000000>;
 359                                         };
 360
 361                                         pwm_clk: pwm_clk@38 {
 362                                                 #clock-cells = <0>;
 363                                                 reg = <38>;
 364                                                 atmel,clk-output-range = <0 83000000>;
 365                                         };
 366
 367                                         adc_clk: adc_clk@40 {
 368                                                 #clock-cells = <0>;
 369                                                 reg = <40>;
 370                                                 atmel,clk-output-range = <0 83000000>;
 371                                         };
 372
 373                                         uhphs_clk: uhphs_clk@41 {
 374                                                 #clock-cells = <0>;
 375                                                 reg = <41>;
 376                                                 atmel,clk-output-range = <0 83000000>;
 377                                         };
 378
 379                                         udphs_clk: udphs_clk@42 {
 380                                                 #clock-cells = <0>;
 381                                                 reg = <42>;
 382                                                 atmel,clk-output-range = <0 83000000>;
 383                                         };
 384
 385                                         ssc0_clk: ssc0_clk@43 {
 386                                                 #clock-cells = <0>;
 387                                                 reg = <43>;
 388                                                 atmel,clk-output-range = <0 83000000>;
 389                                         };
 390
 391                                         ssc1_clk: ssc1_clk@44 {
 392                                                 #clock-cells = <0>;
 393                                                 reg = <44>;
 394                                                 atmel,clk-output-range = <0 83000000>;
 395                                         };
 396
 397                                         trng_clk: trng_clk@47 {
 398                                                 #clock-cells = <0>;
 399                                                 reg = <47>;
 400                                                 atmel,clk-output-range = <0 83000000>;
 401                                         };
 402
 403                                         pdmic_clk: pdmic_clk@48 {
 404                                                 #clock-cells = <0>;
 405                                                 reg = <48>;
 406                                                 atmel,clk-output-range = <0 83000000>;
 407                                         };
 408
 409                                         i2s0_clk: i2s0_clk@54 {
 410                                                 #clock-cells = <0>;
 411                                                 reg = <54>;
 412                                                 atmel,clk-output-range = <0 83000000>;
 413                                         };
 414
 415                                         i2s1_clk: i2s1_clk@55 {
 416                                                 #clock-cells = <0>;
 417                                                 reg = <55>;
 418                                                 atmel,clk-output-range = <0 83000000>;
 419                                         };
 420
 421                                         can0_clk: can0_clk@56 {
 422                                                 #clock-cells = <0>;
 423                                                 reg = <56>;
 424                                                 atmel,clk-output-range = <0 83000000>;
 425                                         };
 426
 427                                         can1_clk: can1_clk@57 {
 428                                                 #clock-cells = <0>;
 429                                                 reg = <57>;
 430                                                 atmel,clk-output-range = <0 83000000>;
 431                                         };
 432
 433                                         classd_clk: classd_clk@59 {
 434                                                 #clock-cells = <0>;
 435                                                 reg = <59>;
 436                                                 atmel,clk-output-range = <0 83000000>;
 437                                         };
 438                                 };
 439
 440                                 periph64ck {
 441                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 442                                         #address-cells = <1>;
 443                                         #size-cells = <0>;
 444                                         clocks = <&mck>;
 445                                         u-boot,dm-pre-reloc;
 446
 447                                         dma0_clk: dma0_clk@6 {
 448                                                 #clock-cells = <0>;
 449                                                 reg = <6>;
 450                                         };
 451
 452                                         dma1_clk: dma1_clk@7 {
 453                                                 #clock-cells = <0>;
 454                                                 reg = <7>;
 455                                         };
 456
 457                                         aes_clk: aes_clk@9 {
 458                                                 #clock-cells = <0>;
 459                                                 reg = <9>;
 460                                         };
 461
 462                                         aesb_clk: aesb_clk@10 {
 463                                                 #clock-cells = <0>;
 464                                                 reg = <10>;
 465                                         };
 466
 467                                         sha_clk: sha_clk@12 {
 468                                                 #clock-cells = <0>;
 469                                                 reg = <12>;
 470                                         };
 471
 472                                         mpddr_clk: mpddr_clk@13 {
 473                                                 #clock-cells = <0>;
 474                                                 reg = <13>;
 475                                         };
 476
 477                                         matrix0_clk: matrix0_clk@15 {
 478                                                 #clock-cells = <0>;
 479                                                 reg = <15>;
 480                                         };
 481
 482                                         sdmmc0_hclk: sdmmc0_hclk@31 {
 483                                                 #clock-cells = <0>;
 484                                                 reg = <31>;
 485                                                 u-boot,dm-pre-reloc;
 486                                         };
 487
 488                                         sdmmc1_hclk: sdmmc1_hclk@32 {
 489                                                 #clock-cells = <0>;
 490                                                 reg = <32>;
 491                                                 u-boot,dm-pre-reloc;
 492                                         };
 493
 494                                         lcdc_clk: lcdc_clk@45 {
 495                                                 #clock-cells = <0>;
 496                                                 reg = <45>;
 497                                         };
 498
 499                                         isc_clk: isc_clk@46 {
 500                                                 #clock-cells = <0>;
 501                                                 reg = <46>;
 502                                         };
 503
 504                                         qspi0_clk: qspi0_clk@52 {
 505                                                 #clock-cells = <0>;
 506                                                 reg = <52>;
 507                                         };
 508
 509                                         qspi1_clk: qspi1_clk@53 {
 510                                                 #clock-cells = <0>;
 511                                                 reg = <53>;
 512                                         };
 513                                 };
 514
 515                                 gck {
 516                                         compatible = "atmel,sama5d2-clk-generated";
 517                                         #address-cells = <1>;
 518                                         #size-cells = <0>;
 519                                         interrupt-parent = <&pmc>;
 520                                         clocks = <&main>, <&plla>, <&utmi>, <&mck>;
 521                                         u-boot,dm-pre-reloc;
 522
 523                                         sdmmc0_gclk: sdmmc0_gclk@31 {
 524                                                 #clock-cells = <0>;
 525                                                 reg = <31>;
 526                                                 u-boot,dm-pre-reloc;
 527                                         };
 528
 529                                         sdmmc1_gclk: sdmmc1_gclk@32 {
 530                                                 #clock-cells = <0>;
 531                                                 reg = <32>;
 532                                                 u-boot,dm-pre-reloc;
 533                                         };
 534
 535                                         tcb0_gclk: tcb0_gclk@35 {
 536                                                 #clock-cells = <0>;
 537                                                 reg = <35>;
 538                                                 atmel,clk-output-range = <0 83000000>;
 539                                         };
 540
 541                                         tcb1_gclk: tcb1_gclk@36 {
 542                                                 #clock-cells = <0>;
 543                                                 reg = <36>;
 544                                                 atmel,clk-output-range = <0 83000000>;
 545                                         };
 546
 547                                         pwm_gclk: pwm_gclk@38 {
 548                                                 #clock-cells = <0>;
 549                                                 reg = <38>;
 550                                                 atmel,clk-output-range = <0 83000000>;
 551                                         };
 552
 553                                         pdmic_gclk: pdmic_gclk@48 {
 554                                                 #clock-cells = <0>;
 555                                                 reg = <48>;
 556                                         };
 557
 558                                         i2s0_gclk: i2s0_gclk@54 {
 559                                                 #clock-cells = <0>;
 560                                                 reg = <54>;
 561                                         };
 562
 563                                         i2s1_gclk: i2s1_gclk@55 {
 564                                                 #clock-cells = <0>;
 565                                                 reg = <55>;
 566                                         };
 567
 568                                         can0_gclk: can0_gclk@56 {
 569                                                 #clock-cells = <0>;
 570                                                 reg = <56>;
 571                                                 atmel,clk-output-range = <0 80000000>;
 572                                         };
 573
 574                                         can1_gclk: can1_gclk@57 {
 575                                                 #clock-cells = <0>;
 576                                                 reg = <57>;
 577                                                 atmel,clk-output-range = <0 80000000>;
 578                                         };
 579
 580                                         classd_gclk: classd_gclk@59 {
 581                                                 #clock-cells = <0>;
 582                                                 reg = <59>;
 583                                                 atmel,clk-output-range = <0 100000000>;
 584                                         };
 585                                 };
 586                         };
 587
 588                         qspi0: spi@f0020000 {
 589                                 compatible = "atmel,sama5d2-qspi";
 590                                 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
 591                                 reg-names = "qspi_base", "qspi_mmap";
 592                                 #address-cells = <1>;
 593                                 #size-cells = <0>;
 594                                 clocks = <&qspi0_clk>;
 595                                 status = "disabled";
 596                         };
 597
 598                         spi0: spi@f8000000 {
 599                                 compatible = "atmel,at91rm9200-spi";
 600                                 reg = <0xf8000000 0x100>;
 601                                 clocks = <&spi0_clk>;
 602                                 clock-names = "spi_clk";
 603                                 #address-cells = <1>;
 604                                 #size-cells = <0>;
 605                                 status = "disabled";
 606                         };
 607
 608                         macb0: ethernet@f8008000 {
 609                                 compatible = "cdns,macb";
 610                                 reg = <0xf8008000 0x1000>;
 611                                 #address-cells = <1>;
 612                                 #size-cells = <0>;
 613                                 clocks = <&macb0_clk>, <&macb0_clk>;
 614                                 clock-names = "hclk", "pclk";
 615                                 status = "disabled";
 616                         };
 617
 618                         uart1: serial@f8020000 {
 619                                 compatible = "atmel,at91sam9260-usart";
 620                                 reg = <0xf8020000 0x100>;
 621                                 clocks = <&uart1_clk>;
 622                                 clock-names = "usart";
 623                                 status = "disabled";
 624                         };
 625
 626                         i2c0: i2c@f8028000 {
 627                                 compatible = "atmel,sama5d2-i2c";
 628                                 reg = <0xf8028000 0x100>;
 629                                 #address-cells = <1>;
 630                                 #size-cells = <0>;
 631                                 clocks = <&twi0_clk>;
 632                                 status = "disabled";
 633                         };
 634
 635                         sckc@f8048050 {
 636                                 compatible = "atmel,at91sam9x5-sckc";
 637                                 reg = <0xf8048050 0x4>;
 638
 639                                 slow_rc_osc: slow_rc_osc {
 640                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
 641                                         #clock-cells = <0>;
 642                                         clock-frequency = <32768>;
 643                                         clock-accuracy = <250000000>;
 644                                         atmel,startup-time-usec = <75>;
 645                                 };
 646
 647                                 slow_osc: slow_osc {
 648                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
 649                                         #clock-cells = <0>;
 650                                         clocks = <&slow_xtal>;
 651                                         atmel,startup-time-usec = <1200000>;
 652                                 };
 653
 654                                 clk32k: slowck {
 655                                         compatible = "atmel,at91sam9x5-clk-slow";
 656                                         #clock-cells = <0>;
 657                                         clocks = <&slow_rc_osc &slow_osc>;
 658                                 };
 659                         };
 660
 661                         spi1: spi@fc000000 {
 662                                 compatible = "atmel,at91rm9200-spi";
 663                                 reg = <0xfc000000 0x100>;
 664                                 #address-cells = <1>;
 665                                 #size-cells = <0>;
 666                                 status = "disabled";
 667                         };
 668
 669                         i2c1: i2c@fc028000 {
 670                                 compatible = "atmel,sama5d2-i2c";
 671                                 reg = <0xfc028000 0x100>;
 672                                 #address-cells = <1>;
 673                                 #size-cells = <0>;
 674                                 clocks = <&twi1_clk>;
 675                                 status = "disabled";
 676                         };
 677
 678                         pioA: gpio@fc038000 {
 679                                 compatible = "atmel,sama5d2-gpio";
 680                                 reg = <0xfc038000 0x600>;
 681                                 clocks = <&pioA_clk>;
 682                                 gpio-controller;
 683                                 #gpio-cells = <2>;
 684                                 u-boot,dm-pre-reloc;
 685
 686                                 pinctrl {
 687                                         compatible = "atmel,sama5d2-pinctrl";
 688                                         u-boot,dm-pre-reloc;
 689                                 };
 690                         };
 691                 };
 692         };
 693 };