arch/arm/dts/px30-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 / {
   7         aliases {
   8                 mmc0 = &emmc;
   9                 mmc1 = &sdmmc;
  10         };
  11
  12         chosen {
  13                 u-boot,spl-boot-order = &emmc, &sdmmc;
  14         };
  15
  16         rng: rng@ff0b0000 {
  17                 compatible = "rockchip,cryptov2-rng";
  18                 reg = <0x0 0xff0b0000 0x0 0x4000>;
  19                 status = "disabled";
  20         };
  21 };
  22
  23 &dmc {
  24         u-boot,dm-pre-reloc;
  25 };
  26
  27 &uart2 {
  28         clock-frequency = <24000000>;
  29         u-boot,dm-pre-reloc;
  30 };
  31
  32 &uart5 {
  33         clock-frequency = <24000000>;
  34         u-boot,dm-pre-reloc;
  35 };
  36
  37 &sdmmc {
  38         u-boot,dm-pre-reloc;
  39
  40         /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
  41         u-boot,spl-fifo-mode;
  42 };
  43
  44 &emmc {
  45         u-boot,dm-pre-reloc;
  46
  47         /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
  48         u-boot,spl-fifo-mode;
  49 };
  50
  51 &grf {
  52         u-boot,dm-pre-reloc;
  53 };
  54
  55 &pmugrf {
  56         u-boot,dm-pre-reloc;
  57 };
  58
  59 &xin24m {
  60         u-boot,dm-pre-reloc;
  61 };
  62
  63 &cru {
  64         u-boot,dm-pre-reloc;
  65 };
  66
  67 &pmucru {
  68         u-boot,dm-pre-reloc;
  69 };
  70
  71 &saradc {
  72         u-boot,dm-pre-reloc;
  73         status = "okay";
  74 };
  75
  76 &gpio0 {
  77         u-boot,dm-pre-reloc;
  78 };
  79
  80 &gpio1 {
  81         u-boot,dm-pre-reloc;
  82 };
  83
  84 &gpio2 {
  85         u-boot,dm-pre-reloc;
  86 };
  87
  88 &gpio3 {
  89         u-boot,dm-pre-reloc;
  90 };