arch/arm/dts/ls1021a-twr.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale ls1021a TWR board common device tree source
   4  *
   5  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include "ls1021a.dtsi"
   9
  10 / {
  11         model = "LS1021A TWR Board";
  12
  13         aliases {
  14                 enet2-rgmii-phy = &rgmii_phy1;
  15                 enet0-sgmii-phy = &sgmii_phy2;
  16                 enet1-sgmii-phy = &sgmii_phy0;
  17                 spi0 = &qspi;
  18                 spi1 = &dspi1;
  19         };
  20
  21         chosen {
  22                 stdout-path = &uart0;
  23         };
  24 };
  25
  26 &qspi {
  27         status = "okay";
  28
  29         n25q128a130: flash@0 {
  30                 #address-cells = <1>;
  31                 #size-cells = <1>;
  32                 compatible = "jedec,spi-nor";
  33                 spi-max-frequency = <50000000>;
  34                 reg = <0>;
  35         };
  36 };
  37
  38 &dspi1 {
  39         bus-num = <0>;
  40         status = "okay";
  41
  42         dspiflash: at26df081a@0 {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 compatible = "jedec,spi-nor";
  46                 spi-max-frequency = <16000000>;
  47                 spi-cpol;
  48                 spi-cpha;
  49                 reg = <0>;
  50         };
  51 };
  52
  53 &enet0 {
  54         tbi-handle = <&tbi0>;
  55         phy-handle = <&sgmii_phy2>;
  56         phy-connection-type = "sgmii";
  57         status = "okay";
  58 };
  59
  60 &enet1 {
  61         tbi-handle = <&tbi1>;
  62         phy-handle = <&sgmii_phy0>;
  63         phy-connection-type = "sgmii";
  64         status = "okay";
  65 };
  66
  67 &enet2 {
  68         phy-handle = <&rgmii_phy1>;
  69         phy-connection-type = "rgmii-id";
  70         status = "okay";
  71 };
  72
  73 &i2c0 {
  74         status = "okay";
  75 };
  76
  77 &i2c1 {
  78         status = "okay";
  79 };
  80
  81 &ifc {
  82         #address-cells = <2>;
  83         #size-cells = <1>;
  84         /* NOR Flash on board */
  85         ranges = <0x0 0x0 0x60000000 0x08000000>;
  86         status = "okay";
  87
  88         nor@0,0 {
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 compatible = "cfi-flash";
  92                 reg = <0x0 0x0 0x8000000>;
  93                 bank-width = <2>;
  94                 device-width = <1>;
  95         };
  96 };
  97
  98 &lpuart0 {
  99         status = "okay";
 100 };
 101
 102 &mdio0 {
 103         sgmii_phy0: ethernet-phy@0 {
 104                 reg = <0x0>;
 105         };
 106
 107         rgmii_phy1: ethernet-phy@1 {
 108                 reg = <0x1>;
 109         };
 110
 111         sgmii_phy2: ethernet-phy@2 {
 112                 reg = <0x2>;
 113         };
 114
 115         /* SGMII PCS for enet0 */
 116         tbi0: tbi-phy@1f {
 117                 reg = <0x1f>;
 118                 device_type = "tbi-phy";
 119         };
 120 };
 121
 122 &mdio1 {
 123         /* SGMII PCS for enet1 */
 124         tbi1: tbi-phy@1f {
 125                 reg = <0x1f>;
 126                 device_type = "tbi-phy";
 127         };
 128 };
 129
 130 &uart0 {
 131         status = "okay";
 132 };
 133
 134 &uart1 {
 135         status = "okay";
 136 };
 137
 138 &sata {
 139         status = "okay";
 140 };