arch/arm/dts/imx8mm-beacon-som.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright 2020 Compass Electronics Group, LLC
   4  */
   5
   6 / {
   7         usdhc1_pwrseq: usdhc1_pwrseq {
   8                 compatible = "mmc-pwrseq-simple";
   9                 pinctrl-names = "default";
  10                 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
  11                 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  12                 clocks = <&osc_32k>;
  13                 clock-names = "ext_clock";
  14                 post-power-on-delay-ms = <80>;
  15         };
  16
  17         memory@40000000 {
  18                 device_type = "memory";
  19                 reg = <0x0 0x40000000 0 0x80000000>;
  20         };
  21 };
  22
  23 &A53_0 {
  24         cpu-supply = <&buck2_reg>;
  25 };
  26
  27 &fec1 {
  28         pinctrl-names = "default";
  29         pinctrl-0 = <&pinctrl_fec1>;
  30         phy-mode = "rgmii-id";
  31         phy-handle = <&ethphy0>;
  32         fsl,magic-packet;
  33         status = "okay";
  34
  35         mdio {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 ethphy0: ethernet-phy@0 {
  40                         compatible = "ethernet-phy-ieee802.3-c22";
  41                         reg = <0>;
  42                 };
  43         };
  44 };
  45
  46 &i2c1 {
  47         clock-frequency = <400000>;
  48         pinctrl-names = "default";
  49         pinctrl-0 = <&pinctrl_i2c1>;
  50         status = "okay";
  51
  52         pmic@4b {
  53                 compatible = "rohm,bd71847";
  54                 reg = <0x4b>;
  55                 pinctrl-0 = <&pinctrl_pmic>;
  56                 interrupt-parent = <&gpio1>;
  57                 interrupts = <3 GPIO_ACTIVE_LOW>;
  58                 rohm,reset-snvs-powered;
  59
  60                 regulators {
  61                         buck1_reg: BUCK1 {
  62                                 regulator-name = "buck1";
  63                                 regulator-min-microvolt = <700000>;
  64                                 regulator-max-microvolt = <1300000>;
  65                                 regulator-boot-on;
  66                                 regulator-always-on;
  67                                 regulator-ramp-delay = <1250>;
  68                         };
  69
  70                         buck2_reg: BUCK2 {
  71                                 regulator-name = "buck2";
  72                                 regulator-min-microvolt = <700000>;
  73                                 regulator-max-microvolt = <1300000>;
  74                                 regulator-boot-on;
  75                                 regulator-always-on;
  76                                 regulator-ramp-delay = <1250>;
  77                                 rohm,dvs-run-voltage = <1000000>;
  78                                 rohm,dvs-idle-voltage = <900000>;
  79                         };
  80
  81                         buck3_reg: BUCK3 {
  82                                 // BUCK5 in datasheet
  83                                 regulator-name = "buck3";
  84                                 regulator-min-microvolt = <700000>;
  85                                 regulator-max-microvolt = <1350000>;
  86                                 regulator-boot-on;
  87                                 regulator-always-on;
  88                         };
  89
  90                         buck4_reg: BUCK4 {
  91                                 // BUCK6 in datasheet
  92                                 regulator-name = "buck4";
  93                                 regulator-min-microvolt = <3000000>;
  94                                 regulator-max-microvolt = <3300000>;
  95                                 regulator-boot-on;
  96                                 regulator-always-on;
  97                         };
  98
  99                         buck5_reg: BUCK5 {
 100                                 // BUCK7 in datasheet
 101                                 regulator-name = "buck5";
 102                                 regulator-min-microvolt = <1605000>;
 103                                 regulator-max-microvolt = <1995000>;
 104                                 regulator-boot-on;
 105                                 regulator-always-on;
 106                         };
 107
 108                         buck6_reg: BUCK6 {
 109                                 // BUCK8 in datasheet
 110                                 regulator-name = "buck6";
 111                                 regulator-min-microvolt = <800000>;
 112                                 regulator-max-microvolt = <1400000>;
 113                                 regulator-boot-on;
 114                                 regulator-always-on;
 115                         };
 116
 117                         ldo1_reg: LDO1 {
 118                                 regulator-name = "ldo1";
 119                                 regulator-min-microvolt = <3000000>;
 120                                 regulator-max-microvolt = <3300000>;
 121                                 regulator-boot-on;
 122                                 regulator-always-on;
 123                         };
 124
 125                         ldo2_reg: LDO2 {
 126                                 regulator-name = "ldo2";
 127                                 regulator-min-microvolt = <900000>;
 128                                 regulator-max-microvolt = <900000>;
 129                                 regulator-boot-on;
 130                                 regulator-always-on;
 131                         };
 132
 133                         ldo3_reg: LDO3 {
 134                                 regulator-name = "ldo3";
 135                                 regulator-min-microvolt = <1800000>;
 136                                 regulator-max-microvolt = <3300000>;
 137                                 regulator-boot-on;
 138                                 regulator-always-on;
 139                         };
 140
 141                         ldo4_reg: LDO4 {
 142                                 regulator-name = "ldo4";
 143                                 regulator-min-microvolt = <900000>;
 144                                 regulator-max-microvolt = <1800000>;
 145                                 regulator-boot-on;
 146                                 regulator-always-on;
 147                         };
 148
 149                         ldo6_reg: LDO6 {
 150                                 regulator-name = "ldo6";
 151                                 regulator-min-microvolt = <900000>;
 152                                 regulator-max-microvolt = <1800000>;
 153                                 regulator-boot-on;
 154                                 regulator-always-on;
 155                         };
 156                 };
 157         };
 158 };
 159
 160 &i2c3 {
 161         clock-frequency = <400000>;
 162         pinctrl-names = "default";
 163         pinctrl-0 = <&pinctrl_i2c3>;
 164         status = "okay";
 165
 166         eeprom@50 {
 167                 compatible = "microchip, at24c64d", "atmel,24c64";
 168                 pagesize = <32>;
 169                 read-only;      /* Manufacturing EEPROM programmed at factory */
 170                 reg = <0x50>;
 171         };
 172
 173         rtc@51 {
 174                 compatible = "nxp,pcf85263";
 175                 reg = <0x51>;
 176         };
 177 };
 178
 179 &uart1 {
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_uart1>;
 182         assigned-clocks = <&clk IMX8MM_CLK_UART1>;
 183         assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
 184         uart-has-rtscts;
 185         status = "okay";
 186
 187         bluetooth {
 188                 compatible = "brcm,bcm43438-bt";
 189                 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
 190                 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
 191                 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
 192                 clocks = <&osc_32k>;
 193                 clock-names = "extclk";
 194         };
 195 };
 196
 197 &usdhc1 {
 198         #address-cells = <1>;
 199         #size-cells = <0>;
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&pinctrl_usdhc1>;
 202         bus-width = <4>;
 203         non-removable;
 204         cap-power-off-card;
 205         pm-ignore-notify;
 206         keep-power-in-suspend;
 207         mmc-pwrseq = <&usdhc1_pwrseq>;
 208         status = "okay";
 209
 210         brcmf: bcrmf@1 {
 211                 reg = <1>;
 212                 compatible = "brcm,bcm4329-fmac";
 213                 pinctrl-names = "default";
 214                 pinctrl-0 = <&pinctrl_wlan>;
 215                 interrupt-parent = <&gpio2>;
 216                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
 217                 interrupt-names = "host-wake";
 218         };
 219 };
 220
 221 &usdhc3 {
 222         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 223         pinctrl-0 = <&pinctrl_usdhc3>;
 224         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 225         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 226         bus-width = <8>;
 227         non-removable;
 228         status = "okay";
 229 };
 230
 231 &wdog1 {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_wdog>;
 234         fsl,ext-reset-output;
 235         status = "okay";
 236 };
 237
 238 &iomuxc {
 239                 pinctrl_fec1: fec1grp {
 240                         fsl,pins = <
 241                                 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC         0x3
 242                                 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
 243                                 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
 244                                 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
 245                                 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
 246                                 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
 247                                 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
 248                                 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
 249                                 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
 250                                 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
 251                                 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
 252                                 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
 253                                 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 254                                 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 255                                 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
 256                         >;
 257                 };
 258
 259                 pinctrl_i2c1: i2c1grp {
 260                         fsl,pins = <
 261                                 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
 262                                 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
 263                         >;
 264                 };
 265
 266                 pinctrl_i2c3: i2c3grp {
 267                         fsl,pins = <
 268                                 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
 269                                 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
 270                         >;
 271                 };
 272
 273                 pinctrl_pmic: pmicirq {
 274                         fsl,pins = <
 275                                 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x41
 276                         >;
 277                 };
 278
 279                 pinctrl_uart1: uart1grp {
 280                         fsl,pins = <
 281                                 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 282                                 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 283                                 MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
 284                                 MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
 285                                 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6        0x19
 286                                 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7        0x19
 287                                 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x19
 288                                 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x141
 289                         >;
 290                 };
 291
 292                 pinctrl_usdhc1_gpio: usdhc1grpgpio {
 293                         fsl,pins = <
 294                                 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x41
 295                         >;
 296                 };
 297
 298                 pinctrl_usdhc1: usdhc1grp {
 299                         fsl,pins = <
 300                                 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
 301                                 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
 302                                 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
 303                                 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
 304                                 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
 305                                 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
 306                         >;
 307                 };
 308
 309                 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 310                         fsl,pins = <
 311                                 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
 312                                 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
 313                                 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
 314                                 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
 315                                 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
 316                                 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
 317                         >;
 318                 };
 319
 320                 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 321                         fsl,pins = <
 322                                 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
 323                                 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
 324                                 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
 325                                 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
 326                                 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
 327                                 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
 328                         >;
 329                 };
 330
 331                 pinctrl_usdhc3: usdhc3grp {
 332                         fsl,pins = <
 333                                 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
 334                                 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 335                                 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 336                                 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 337                                 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 338                                 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 339                                 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 340                                 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 341                                 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 342                                 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 343                                 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 344                         >;
 345                 };
 346
 347                 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 348                         fsl,pins = <
 349                                 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
 350                                 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 351                                 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 352                                 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 353                                 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 354                                 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 355                                 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 356                                 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 357                                 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 358                                 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 359                                 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 360                         >;
 361                 };
 362
 363                 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 364                         fsl,pins = <
 365                                 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
 366                                 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 367                                 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 368                                 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 369                                 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 370                                 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 371                                 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 372                                 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 373                                 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 374                                 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 375                                 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 376                         >;
 377                 };
 378
 379                 pinctrl_wdog: wdoggrp {
 380                         fsl,pins = <
 381                                 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 382                         >;
 383                 };
 384
 385                 pinctrl_wlan: wlangrp {
 386                         fsl,pins = <
 387                                 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                0x111
 388                         >;
 389                 };
 390 };