arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP LX2160AQDS device tree source for the SERDES block #2 - protocol 11
   4  *
   5  * Some assumptions are made:
   6  *    * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8
   7  *       (sgmii for DPMAC 12, 13, 14, 16, 17, 18)
   8  *
   9  * Copyright 2020 NXP
  10  *
  11  */
  12 #include "fsl-lx2160a-qds.dtsi"
  13
  14 &dpmac12 {
  15         status = "okay";
  16         phy-handle = <&sgmii_phy7_2>;
  17         phy-connection-type = "sgmii";
  18 };
  19
  20 &dpmac17 {
  21         status = "okay";
  22         phy-handle = <&sgmii_phy7_3>;
  23         phy-connection-type = "sgmii";
  24 };
  25
  26 &dpmac18 {
  27         status = "okay";
  28         phy-handle = <&sgmii_phy7_4>;
  29         phy-connection-type = "sgmii";
  30 };
  31
  32 &dpmac16 {
  33         status = "okay";
  34         phy-handle = <&sgmii_phy8_2>;
  35         phy-connection-type = "sgmii";
  36 };
  37
  38 &dpmac13 {
  39         status = "okay";
  40         phy-handle = <&sgmii_phy8_3>;
  41         phy-connection-type = "sgmii";
  42 };
  43
  44 &dpmac14 {
  45         status = "okay";
  46         phy-handle = <&sgmii_phy8_4>;
  47         phy-connection-type = "sgmii";
  48 };
  49
  50 &emdio1_slot7 {
  51         sgmii_phy7_2: ethernet-phy@1d {
  52                 reg = <0x1d>;
  53         };
  54
  55         sgmii_phy7_3: ethernet-phy@1e {
  56                 reg = <0x1e>;
  57         };
  58
  59         sgmii_phy7_4: ethernet-phy@1f {
  60                 reg = <0x1f>;
  61         };
  62 };
  63
  64 &emdio1_slot8 {
  65         sgmii_phy8_2: ethernet-phy@1d {
  66                 reg = <0x1d>;
  67         };
  68
  69         sgmii_phy8_3: ethernet-phy@1e {
  70                 reg = <0x1e>;
  71         };
  72
  73         sgmii_phy8_4: ethernet-phy@1f {
  74                 reg = <0x1f>;
  75         };
  76 };