arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 3
   4  *
   5  * Some assumptions are made:
   6  *    * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6)
   7  *
   8  * Copyright 2020 NXP
   9  *
  10  */
  11
  12 #include "fsl-lx2160a-qds.dtsi"
  13
  14 &dpmac3 {
  15         status = "okay";
  16         phy-handle = <&aquantia_phy1>;
  17         phy-connection-type = "usxgmii";
  18 };
  19
  20 &dpmac4 {
  21         status = "okay";
  22         phy-handle = <&aquantia_phy2>;
  23         phy-connection-type = "usxgmii";
  24 };
  25
  26 &dpmac5 {
  27         status = "okay";
  28         phy-handle = <&aquantia_phy3>;
  29         phy-connection-type = "usxgmii";
  30 };
  31
  32 &dpmac6 {
  33         status = "okay";
  34         phy-handle = <&aquantia_phy4>;
  35         phy-connection-type = "usxgmii";
  36 };
  37
  38 &emdio1_slot1 {
  39         aquantia_phy1: ethernet-phy@4 {
  40                 compatible = "ethernet-phy-ieee802.3-c45";
  41                 reg = <0x0>;
  42         };
  43         aquantia_phy2: ethernet-phy@5 {
  44                 compatible = "ethernet-phy-ieee802.3-c45";
  45                 reg = <0x1>;
  46         };
  47         aquantia_phy3: ethernet-phy@6 {
  48                 compatible = "ethernet-phy-ieee802.3-c45";
  49                 reg = <0x2>;
  50         };
  51         aquantia_phy4: ethernet-phy@7 {
  52                 compatible = "ethernet-phy-ieee802.3-c45";
  53                 reg = <0x3>;
  54         };
  55 };