arch/arm/dts/fsl-ls1088a.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * NXP ls1088a SOC common device tree source
   4  *
   5  * Copyright 2017 NXP
   6  */
   7
   8 / {
   9         compatible = "fsl,ls1088a";
  10         interrupt-parent = <&gic>;
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13
  14         memory@80000000 {
  15                 device_type = "memory";
  16                 reg = <0x00000000 0x80000000 0 0x80000000>;
  17                       /* DRAM space - 1, size : 2 GB DRAM */
  18         };
  19
  20         gic: interrupt-controller@6000000 {
  21                 compatible = "arm,gic-v3";
  22                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  23                       <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  24                 #interrupt-cells = <3>;
  25                 interrupt-controller;
  26                 interrupts = <1 9 0x4>;
  27         };
  28
  29         timer {
  30                 compatible = "arm,armv8-timer";
  31                 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  32                              <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  33                              <1 11 0x8>, /* Virtual PPI, active-low */
  34                              <1 10 0x8>; /* Hypervisor PPI, active-low */
  35         };
  36
  37         i2c0: i2c@2000000 {
  38                 compatible = "fsl,vf610-i2c";
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41                 reg = <0x0 0x2000000 0x0 0x10000>;
  42                 interrupts = <0 34 4>;
  43         };
  44
  45         i2c1: i2c@2010000 {
  46                 compatible = "fsl,vf610-i2c";
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49                 reg = <0x0 0x2010000 0x0 0x10000>;
  50                 interrupts = <0 34 4>;
  51         };
  52
  53         i2c2: i2c@2020000 {
  54                 compatible = "fsl,vf610-i2c";
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57                 reg = <0x0 0x2020000 0x0 0x10000>;
  58                 interrupts = <0 35 4>;
  59         };
  60
  61         i2c3: i2c@2030000 {
  62                 compatible = "fsl,vf610-i2c";
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65                 reg = <0x0 0x2030000 0x0 0x10000>;
  66                 interrupts = <0 35 4>;
  67         };
  68
  69         serial0: serial@21c0500 {
  70                 device_type = "serial";
  71                 compatible = "fsl,ns16550", "ns16550a";
  72                 reg = <0x0 0x21c0500 0x0 0x100>;
  73                 clock-frequency = <0>;  /* Updated by bootloader */
  74                 interrupts = <0 32 0x1>; /* edge triggered */
  75         };
  76
  77         serial1: serial@21c0600 {
  78                 device_type = "serial";
  79                 compatible = "fsl,ns16550", "ns16550a";
  80                 reg = <0x0 0x21c0600 0x0 0x100>;
  81                 clock-frequency = <0>;  /* Updated by bootloader */
  82                 interrupts = <0 32 0x1>; /* edge triggered */
  83         };
  84
  85         dspi: dspi@2100000 {
  86                 compatible = "fsl,vf610-dspi";
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 reg = <0x0 0x2100000 0x0 0x10000>;
  90                 interrupts = <0 26 0x4>; /* Level high type */
  91                 num-cs = <6>;
  92         };
  93
  94         qspi: quadspi@1550000 {
  95                 compatible = "fsl,ls1088a-qspi";
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98                 reg = <0x0 0x20c0000 0x0 0x10000>,
  99                         <0x0 0x20000000 0x0 0x10000000>;
 100                 reg-names = "QuadSPI", "QuadSPI-memory";
 101                 num-cs = <4>;
 102         };
 103
 104         esdhc: esdhc@2140000 {
 105                 compatible = "fsl,esdhc";
 106                 reg = <0x0 0x2140000 0x0 0x10000>;
 107                 interrupts = <0 28 0x4>; /* Level high type */
 108                 little-endian;
 109                 bus-width = <4>;
 110         };
 111
 112         ifc: ifc@1530000 {
 113                 compatible = "fsl,ifc", "simple-bus";
 114                 reg = <0x0 0x2240000 0x0 0x20000>;
 115                 interrupts = <0 21 0x4>; /* Level high type */
 116         };
 117
 118         usb0: usb3@3100000 {
 119                 compatible = "fsl,layerscape-dwc3";
 120                 reg = <0x0 0x3100000 0x0 0x10000>;
 121                 interrupts = <0 80 0x4>; /* Level high type */
 122                 dr_mode = "host";
 123         };
 124
 125         usb1: usb3@3110000 {
 126                 compatible = "fsl,layerscape-dwc3";
 127                 reg = <0x0 0x3110000 0x0 0x10000>;
 128                 interrupts = <0 81 0x4>; /* Level high type */
 129                 dr_mode = "host";
 130         };
 131
 132         pcie@3400000 {
 133                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 134                 reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 135                        0x00 0x03480000 0x0 0x80000   /* lut registers */
 136                        0x00 0x034c0000 0x0 0x40000   /* pf controls registers */
 137                        0x20 0x00000000 0x0 0x20000>; /* configuration space */
 138                 reg-names = "dbi", "lut", "ctrl", "config";
 139                 #address-cells = <3>;
 140                 #size-cells = <2>;
 141                 device_type = "pci";
 142                 num-lanes = <4>;
 143                 bus-range = <0x0 0xff>;
 144                 ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000   /* downstream I/O */
 145                           0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 146         };
 147
 148         pcie@3500000 {
 149                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 150                 reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 151                        0x00 0x03580000 0x0 0x80000   /* lut registers */
 152                        0x00 0x035c0000 0x0 0x40000   /* pf controls registers */
 153                        0x28 0x00000000 0x0 0x20000>; /* configuration space */
 154                 reg-names = "dbi", "lut", "ctrl", "config";
 155                 #address-cells = <3>;
 156                 #size-cells = <2>;
 157                 device_type = "pci";
 158                 num-lanes = <4>;
 159                 bus-range = <0x0 0xff>;
 160                 ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000   /* downstream I/O */
 161                           0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 162         };
 163
 164         pcie@3600000 {
 165                 compatible = "fsl,ls-pcie", "snps,dw-pcie";
 166                 reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 167                        0x00 0x03680000 0x0 0x80000   /* lut registers */
 168                        0x00 0x036c0000 0x0 0x40000   /* pf controls registers */
 169                        0x30 0x00000000 0x0 0x20000>; /* configuration space */
 170                 reg-names = "dbi", "lut", "ctrl", "config";
 171                 #address-cells = <3>;
 172                 #size-cells = <2>;
 173                 device_type = "pci";
 174                 num-lanes = <8>;
 175                 bus-range = <0x0 0xff>;
 176                 ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000   /* downstream I/O */
 177                           0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 178         };
 179
 180         sata: sata@3200000 {
 181                 compatible = "fsl,ls1088a-ahci";
 182                 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
 183                        0x7 0x100520  0x0 0x4>;   /* ecc sata addr*/
 184                 reg-names = "sata-base", "ecc-addr";
 185                 interrupts = <0 133 4>;
 186                 status = "disabled";
 187         };
 188
 189         psci {
 190                 compatible = "arm,psci-0.2";
 191                 method = "smc";
 192         };
 193
 194         fsl_mc: fsl-mc@80c000000 {
 195                 compatible = "fsl,qoriq-mc", "simple-mfd";
 196                 reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 197                       <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 198                 #address-cells = <3>;
 199                 #size-cells = <1>;
 200
 201                 /*
 202                  * Region type 0x0 - MC portals
 203                  * Region type 0x1 - QBMAN portals
 204                  */
 205                 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 206                           0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 207
 208                 dpmacs {
 209                         compatible = "simple-mfd";
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212
 213                         dpmac1: dpmac@1 {
 214                                 compatible = "fsl,qoriq-mc-dpmac";
 215                                 reg = <0x1>;
 216                                 status = "disabled";
 217                         };
 218
 219                         dpmac2: dpmac@2 {
 220                                 compatible = "fsl,qoriq-mc-dpmac";
 221                                 reg = <0x2>;
 222                                 status = "disabled";
 223                         };
 224
 225                         dpmac3: dpmac@3 {
 226                                 compatible = "fsl,qoriq-mc-dpmac";
 227                                 reg = <0x3>;
 228                                 status = "disabled";
 229                         };
 230
 231                         dpmac4: dpmac@4 {
 232                                 compatible = "fsl,qoriq-mc-dpmac";
 233                                 reg = <0x4>;
 234                                 status = "disabled";
 235                         };
 236
 237                         dpmac5: dpmac@5 {
 238                                 compatible = "fsl,qoriq-mc-dpmac";
 239                                 reg = <0x5>;
 240                                 status = "disabled";
 241                         };
 242
 243                         dpmac6: dpmac@6 {
 244                                 compatible = "fsl,qoriq-mc-dpmac";
 245                                 reg = <0x6>;
 246                                 status = "disabled";
 247                         };
 248
 249                         dpmac7: dpmac@7 {
 250                                 compatible = "fsl,qoriq-mc-dpmac";
 251                                 reg = <0x7>;
 252                                 status = "disabled";
 253                         };
 254
 255                         dpmac8: dpmac@8 {
 256                                 compatible = "fsl,qoriq-mc-dpmac";
 257                                 reg = <0x8>;
 258                                 status = "disabled";
 259                         };
 260
 261                         dpmac9: dpmac@9 {
 262                                 compatible = "fsl,qoriq-mc-dpmac";
 263                                 reg = <0x9>;
 264                                 status = "disabled";
 265                         };
 266
 267                         dpmac10: dpmac@a {
 268                                 compatible = "fsl,qoriq-mc-dpmac";
 269                                 reg = <0xa>;
 270                                 status = "disabled";
 271                         };
 272                 };
 273         };
 274
 275         emdio1: mdio@8B96000 {
 276                 compatible = "fsl,ls-mdio";
 277                 reg = <0x0 0x8B96000 0x0 0x1000>;
 278                 #address-cells = <1>;
 279                 #size-cells = <0>;
 280                 status = "disabled";
 281         };
 282
 283         emdio2: mdio@8B97000 {
 284                 compatible = "fsl,ls-mdio";
 285                 reg = <0x0 0x8B97000 0x0 0x1000>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 status = "disabled";
 289         };
 290 };