arch/arm/cpu/armv8/hisilicon/pinmux.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Linaro.
   4  * Peter Griffin <peter.griffin@linaro.org>
   5  */
   6
   7 #include <common.h>
   8 #include <fdtdec.h>
   9 #include <log.h>
  10 #include <asm/gpio.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/pinmux.h>
  13 #include <linux/bitops.h>
  14
  15 struct hi6220_pinmux0_regs *pmx0 =
  16         (struct hi6220_pinmux0_regs *)HI6220_PINMUX0_BASE;
  17
  18 struct hi6220_pinmux1_regs *pmx1 =
  19         (struct hi6220_pinmux1_regs *)HI6220_PINMUX1_BASE;
  20
  21 static void hi6220_uart_config(int peripheral)
  22 {
  23         switch (peripheral) {
  24         case PERIPH_ID_UART0:
  25                 writel(MUX_M0, &pmx0->iomg[48]); /* UART0_RXD */
  26                 writel(MUX_M0, &pmx0->iomg[49]); /* UART0_TXD */
  27
  28                 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[49]); /* UART0_RXD */
  29                 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[50]); /* UART0_TXD */
  30                 break;
  31
  32         case PERIPH_ID_UART1:
  33                 writel(MUX_M0, &pmx0->iomg[50]); /* UART1_CTS_N */
  34                 writel(MUX_M0, &pmx0->iomg[51]); /* UART1_RTS_N */
  35                 writel(MUX_M0, &pmx0->iomg[52]); /* UART1_RXD */
  36                 writel(MUX_M0, &pmx0->iomg[53]); /* UART1_TXD */
  37
  38                 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[51]); /*UART1_CTS_N*/
  39                 writel(DRIVE1_02MA | PULL_UP, &pmx1->iocfg[53]); /* UART1_RXD */
  40                 writel(DRIVE1_02MA, &pmx1->iocfg[52]); /* UART1_RTS_N */
  41                 writel(DRIVE1_02MA, &pmx1->iocfg[54]); /* UART1_TXD */
  42                 break;
  43
  44         case PERIPH_ID_UART2:
  45                 writel(MUX_M0, &pmx0->iomg[54]); /* UART2_CTS_N */
  46                 writel(MUX_M0, &pmx0->iomg[55]); /* UART2_RTS_N */
  47                 writel(MUX_M0, &pmx0->iomg[56]); /* UART2_RXD */
  48                 writel(MUX_M0, &pmx0->iomg[57]); /* UART2_TXD */
  49
  50                 writel(DRIVE1_02MA, &pmx1->iocfg[55]); /* UART2_CTS_N */
  51                 writel(DRIVE1_02MA, &pmx1->iocfg[56]); /* UART2_RTS_N */
  52                 writel(DRIVE1_02MA, &pmx1->iocfg[57]); /* UART2_RXD */
  53                 writel(DRIVE1_02MA, &pmx1->iocfg[58]); /* UART2_TXD */
  54                 break;
  55
  56         case PERIPH_ID_UART3:
  57                 writel(MUX_M1, &pmx0->iomg[96]); /* UART3_CTS_N */
  58                 writel(MUX_M1, &pmx0->iomg[97]); /* UART3_RTS_N */
  59                 writel(MUX_M1, &pmx0->iomg[98]); /* UART3_RXD */
  60                 writel(MUX_M1, &pmx0->iomg[99]); /* UART3_TXD */
  61
  62                 /* UART3_TXD */
  63                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[100]);
  64                 /* UART3_RTS_N */
  65                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[101]);
  66                 /* UART3_RXD */
  67                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[102]);
  68                 /* UART3_TXD */
  69                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[103]);
  70                 break;
  71
  72         case PERIPH_ID_UART4:
  73                 writel(MUX_M1, &pmx0->iomg[116]); /* UART4_CTS_N */
  74                 writel(MUX_M1, &pmx0->iomg[117]); /* UART4_RTS_N */
  75                 writel(MUX_M1, &pmx0->iomg[118]); /* UART4_RXD */
  76                 writel(MUX_M1, &pmx0->iomg[119]); /* UART4_TXD */
  77
  78                 /* UART4_CTS_N */
  79                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[120]);
  80                 /* UART4_RTS_N */
  81                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[121]);
  82                 /* UART4_RXD */
  83                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[122]);
  84                 /* UART4_TXD */
  85                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[123]);
  86                 break;
  87         case PERIPH_ID_UART5:
  88                 writel(MUX_M1, &pmx0->iomg[114]); /* UART5_RXD */
  89                 writel(MUX_M1, &pmx0->iomg[115]); /* UART5_TXD */
  90
  91                 /* UART5_RXD */
  92                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[118]);
  93                 /* UART5_TXD */
  94                 writel(DRIVE1_02MA | PULL_DOWN, &pmx1->iocfg[119]);
  95
  96                 break;
  97
  98         default:
  99                 debug("%s: invalid peripheral %d", __func__, peripheral);
 100                 return;
 101         }
 102 }
 103
 104 static int hi6220_mmc_config(int peripheral)
 105 {
 106         u32 tmp;
 107
 108         switch (peripheral) {
 109         case PERIPH_ID_SDMMC0:
 110
 111                 /* eMMC pinmux config */
 112                 writel(MUX_M0, &pmx0->iomg[64]); /* EMMC_CLK */
 113                 writel(MUX_M0, &pmx0->iomg[65]); /* EMMC_CMD */
 114                 writel(MUX_M0, &pmx0->iomg[66]); /* EMMC_DATA0 */
 115                 writel(MUX_M0, &pmx0->iomg[67]); /* EMMC_DATA1 */
 116                 writel(MUX_M0, &pmx0->iomg[68]); /* EMMC_DATA2 */
 117                 writel(MUX_M0, &pmx0->iomg[69]); /* EMMC_DATA3 */
 118                 writel(MUX_M0, &pmx0->iomg[70]); /* EMMC_DATA4 */
 119                 writel(MUX_M0, &pmx0->iomg[71]); /* EMMC_DATA5 */
 120                 writel(MUX_M0, &pmx0->iomg[72]); /* EMMC_DATA6 */
 121                 writel(MUX_M0, &pmx0->iomg[73]); /* EMMC_DATA7 */
 122
 123                 /*eMMC configure up/down/drive */
 124                 writel(DRIVE1_08MA, &pmx1->iocfg[65]); /* EMMC_CLK */
 125
 126                 tmp = DRIVE1_04MA | PULL_UP;
 127                 writel(tmp, &pmx1->iocfg[65]); /* EMMC_CMD */
 128                 writel(tmp, &pmx1->iocfg[66]); /* EMMC_DATA0 */
 129                 writel(tmp, &pmx1->iocfg[67]); /* EMMC_DATA1 */
 130                 writel(tmp, &pmx1->iocfg[68]); /* EMMC_DATA2 */
 131                 writel(tmp, &pmx1->iocfg[69]); /* EMMC_DATA3 */
 132                 writel(tmp, &pmx1->iocfg[70]); /* EMMC_DATA4 */
 133                 writel(tmp, &pmx1->iocfg[71]); /* EMMC_DATA5 */
 134                 writel(tmp, &pmx1->iocfg[72]); /* EMMC_DATA6 */
 135                 writel(tmp, &pmx1->iocfg[73]); /* EMMC_DATA7 */
 136
 137                 writel(DRIVE1_04MA, &pmx1->iocfg[73]); /* EMMC_RST_N */
 138                 break;
 139
 140         case PERIPH_ID_SDMMC1:
 141
 142                 writel(MUX_M0, &pmx0->iomg[3]); /* SD_CLK */
 143                 writel(MUX_M0, &pmx0->iomg[4]); /* SD_CMD */
 144                 writel(MUX_M0, &pmx0->iomg[5]); /* SD_DATA0 */
 145                 writel(MUX_M0, &pmx0->iomg[6]); /* SD_DATA1 */
 146                 writel(MUX_M0, &pmx0->iomg[7]); /* SD_DATA2 */
 147                 writel(MUX_M0, &pmx0->iomg[8]); /* SD_DATA3 */
 148
 149                 writel(DRIVE1_10MA | BIT(2), &pmx1->iocfg[3]); /*SD_CLK*/
 150                 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[4]); /*SD_CMD*/
 151                 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[5]); /*SD_DATA0*/
 152                 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[6]); /*SD_DATA1*/
 153                 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[7]); /*SD_DATA2*/
 154                 writel(DRIVE1_08MA | BIT(2), &pmx1->iocfg[8]); /*SD_DATA3*/
 155                 break;
 156
 157         default:
 158                 debug("%s: invalid peripheral %d", __func__, peripheral);
 159                 return -1;
 160         }
 161
 162         return 0;
 163 }
 164
 165 int hi6220_pinmux_config(int peripheral)
 166 {
 167         switch (peripheral) {
 168         case PERIPH_ID_UART0:
 169         case PERIPH_ID_UART1:
 170         case PERIPH_ID_UART2:
 171         case PERIPH_ID_UART3:
 172                 hi6220_uart_config(peripheral);
 173                 break;
 174         case PERIPH_ID_SDMMC0:
 175         case PERIPH_ID_SDMMC1:
 176                 return hi6220_mmc_config(peripheral);
 177         default:
 178                 debug("%s: invalid peripheral %d", __func__, peripheral);
 179                 return -1;
 180         }
 181
 182         return 0;
 183 }
 184
 185