1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 DENX Software Engineering
4 * Author: John Rigby <jrigby@gmail.com>
6 * Based on mx27/generic.c:
7 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
8 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
12 #include <clock_legacy.h>
19 #include <asm/arch-imx/cpu.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/clock.h>
23 #ifdef CONFIG_FSL_ESDHC_IMX
24 #include <fsl_esdhc_imx.h>
26 DECLARE_GLOBAL_DATA_PTR;
30 * get the system pll clock in Hz
32 * mfi + mfn / (mfd +1)
33 * f = 2 * f_ref * --------------------
36 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
38 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
40 int mfn = (pll >> CCM_PLL_MFN_SHIFT)
42 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
44 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
47 mfi = mfi <= 5 ? 5 : mfi;
48 mfn = mfn >= 512 ? mfn - 1024 : mfn;
52 return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
56 static ulong imx_get_mpllclk(void)
58 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
59 ulong fref = MXC_HCLK;
61 return imx_decode_pll(readl(&ccm->mpctl), fref);
64 static ulong imx_get_upllclk(void)
66 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
67 ulong fref = MXC_HCLK;
69 return imx_decode_pll(readl(&ccm->upctl), fref);
72 static ulong imx_get_armclk(void)
74 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
75 ulong cctl = readl(&ccm->cctl);
76 ulong fref = imx_get_mpllclk();
79 if (cctl & CCM_CCTL_ARM_SRC)
80 fref = lldiv((u64) fref * 3, 4);
82 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
83 & CCM_CCTL_ARM_DIV_MASK) + 1;
88 static ulong imx_get_ahbclk(void)
90 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
91 ulong cctl = readl(&ccm->cctl);
92 ulong fref = imx_get_armclk();
95 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
96 & CCM_CCTL_AHB_DIV_MASK) + 1;
101 static ulong imx_get_ipgclk(void)
103 return imx_get_ahbclk() / 2;
106 static ulong imx_get_perclk(int clk)
108 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
109 ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
113 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
114 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
119 int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
121 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
122 ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
123 ulong div = (fref + freq - 1) / freq;
125 if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
128 clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
129 CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
130 div << CCM_PERCLK_SHIFT(clk));
132 setbits_le32(&ccm->mcr, 1 << clk);
134 clrbits_le32(&ccm->mcr, 1 << clk);
138 unsigned int mxc_get_clock(enum mxc_clock clk)
140 if (clk >= MXC_CLK_NUM)
144 return imx_get_armclk();
146 return imx_get_ahbclk();
150 return imx_get_ipgclk();
152 return imx_get_perclk(clk);
156 u32 get_cpu_rev(void)
159 u32 system_rev = 0x25000;
161 /* read SREV register from IIM module */
162 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
163 srev = readl(&iim->iim_srev);
167 system_rev |= CHIP_REV_1_0;
170 system_rev |= CHIP_REV_1_1;
173 system_rev |= CHIP_REV_1_2;
176 system_rev |= 0x8000;
183 #if defined(CONFIG_DISPLAY_CPUINFO)
184 static char *get_reset_cause(void)
186 /* read RCSR register from CCM module */
187 struct ccm_regs *ccm =
188 (struct ccm_regs *)IMX_CCM_BASE;
190 u32 cause = readl(&ccm->rcsr) & 0x0f;
196 else if ((cause & 2) == 2)
198 else if ((cause & 4) == 4)
200 else if ((cause & 8) == 8)
203 return "unknown reset";
207 int print_cpuinfo(void)
210 u32 cpurev = get_cpu_rev();
212 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
213 (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
214 ((cpurev & 0x8000) ? " unknown" : ""),
215 strmhz(buf, imx_get_armclk()));
216 printf("Reset cause: %s\n", get_reset_cause());
221 #if defined(CONFIG_FEC_MXC)
223 * Initializes on-chip ethernet controllers.
224 * to override, implement board_eth_init()
226 int cpu_eth_init(bd_t *bis)
228 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
231 val = readl(&ccm->cgr0);
233 writel(val, &ccm->cgr0);
234 return fecmxc_initialize(bis);
240 #ifdef CONFIG_FSL_ESDHC_IMX
241 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
242 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
244 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
250 #ifdef CONFIG_FSL_ESDHC_IMX
252 * Initializes on-chip MMC controllers.
253 * to override, implement board_mmc_init()
255 int cpu_mmc_init(bd_t *bis)
257 return fsl_esdhc_mmc_init(bis);
261 #ifdef CONFIG_FEC_MXC
262 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
265 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
266 struct fuse_bank *bank = &iim->bank[0];
267 struct fuse_bank0_regs *fuse =
268 (struct fuse_bank0_regs *)bank->fuse_regs;
270 for (i = 0; i < 6; i++)
271 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
273 #endif /* CONFIG_FEC_MXC */