#include "if_athvar.h"
#include "ah_desc.h"
#include "ah.h"
+#include "ratectrl.h"
+#include "ah_internal.h"
static a_int32_t ath_numrxbufs = -1;
static a_int32_t ath_numrxdescs = -1;
void owl_tgt_tx_tasklet(TQUEUE_ARG data);
static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
+static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
extern void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
-/*************/
-/* Utilities */
-/*************/
-
-#undef adf_os_cpu_to_le16
-
-static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
-{
- return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
-}
-
/*
- * Extend a 32 bit TSF to 64 bit, taking wrapping into account.
+ * Extend a 32 bit TSF to nearest 64 bit TSF value.
+ * When the adapter is a STATION, its local TSF is periodically modified by
+ * the hardware to match the BSS TSF (as received in beacon packets), and
+ * rstamp may appear to be from the future or from the past (with reference
+ * to the current local TSF) because of jitter. This is mostly noticable in
+ * highly congested channels. The code uses signed modulo arithmetic to
+ * handle both past/future cases and signed-extension to avoid branches.
+ * Test cases:
+ * extend(0x0000001200000004, 0x00000006) == 0x0000001200000006
+ * extend(0x0000001200000004, 0x00000002) == 0x0000001200000002
+ * extend(0x0000001200000004, 0xfffffffe) == 0x00000011fffffffe ! tsfhigh--
+ * extend(0x000000127ffffffe, 0x80000002) == 0x0000001280000002
+ * extend(0x0000001280000002, 0x7ffffffe) == 0x000000127ffffffe
+ * extend(0x00000012fffffffc, 0xfffffffe) == 0x00000012fffffffe
+ * extend(0x00000012fffffffc, 0xfffffffa) == 0x00000012fffffffa
+ * extend(0x00000012fffffffc, 0x00000002) == 0x0000001300000002 ! tsfhigh++
*/
static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
{
+ struct ath_hal *ah = sc->sc_ah;
u_int64_t tsf;
u_int32_t tsf_low;
- u_int64_t tsf64;
+ a_int64_t tsf_delta; /* signed int64 */
- tsf = ath_hal_gettsf64(sc->sc_ah);
- tsf_low = tsf & 0xffffffff;
- tsf64 = (tsf & ~0xffffffffULL) | rstamp;
+ tsf = ah->ah_getTsf64(ah);
+ tsf_low = tsf & 0xffffffffUL;
- if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000))
- tsf64 -= 0x100000000ULL;
+ tsf_delta = (a_int32_t)((rstamp - tsf_low) & 0xffffffffUL);
- if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000))
- tsf64 += 0x100000000ULL;
-
- return tsf64;
+ return (tsf + (u_int64_t)tsf_delta);
}
static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode)
ds->ds_link = 0;
adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
- ath_hal_setuprxdesc(ah, ds,
- adf_nbuf_tailroom(ds->ds_nbuf),
- 0);
+ ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
if (sc->sc_rxlink == NULL) {
- ath_hal_putrxbuf(ah, ds->ds_daddr);
+ ah->ah_setRxDP(ah, ds->ds_daddr);
}
else {
*sc->sc_rxlink = ds->ds_daddr;
}
sc->sc_rxlink = &ds->ds_link;
- ath_hal_rxena(ah);
+ ah->ah_enableReceive(ah);
return 0;
}
a_int32_t retval;
a_uint32_t cnt = 0;
a_uint16_t frame_len = 0;
- a_uint64_t tsf;
#define PA2DESC(_sc, _pa) \
((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
- tsf = ath_hal_gettsf64(ah);
bf = asf_tailq_first(&sc->sc_rxbuf);
ds = asf_tailq_first(&sc->sc_rxdesc);
continue;
}
- retval = ath_hal_rxprocdescfast(ah, ds, ds->ds_daddr,
+ retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr,
PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
if (HAL_EINPROGRESS == retval) {
break;
}
ds = asf_tailq_first(&sc->sc_rxdesc);
- ath_hal_putrxbuf(ah, ds->ds_daddr);
+ ah->ah_setRxDP(ah, ds->ds_daddr);
return 0;
}
} while(1);
sc->sc_imask |= HAL_INT_RX;
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
}
/*******************/
rt = sc->sc_currates;
rate = rt->info[rix].rateCode;
- ath_hal_setuptxdesc(ah, ds
+ ah->ah_setupTxDesc(ds
, adf_nbuf_len(skb) + IEEE80211_CRC_LEN
, sizeof(struct ieee80211_frame)
, HAL_PKT_TYPE_BEACON
, MAX_RATE_POWER
, rate, 1
, HAL_TXKEYIX_INVALID
- , 0
, flags
, 0
- , 0
- , 0
- , 0
- , ATH_COMP_PROC_NO_COMP_NO_CCS);
+ , 0);
- ath_hal_filltxdesc(ah, ds
+ ah->ah_fillTxDesc(ds
, asf_roundup(adf_nbuf_len(skb), 4)
, AH_TRUE
, AH_TRUE
series[0].Rate = rate;
series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
series[0].RateFlags = 0;
- ath_hal_set11n_ratescenario(ah, ds, 0, 0, 0, series, 4, 0);
+ ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0);
}
static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
struct ath_tx_buf *bf;
a_uint8_t vap_index, *anbdata;
ath_beacon_hdr_t *bhdr;
- struct ieee80211vap_target *vap;
a_uint32_t anblen;
- struct ieee80211_frame *wh;
if (!bc_hdr) {
adf_nbuf_peek_header(nbuf, &anbdata, &anblen);
vap_index = bhdr->vap_index;
adf_os_assert(vap_index < TARGET_VAP_MAX);
- vap = &sc->sc_vap[vap_index].av_vap;
- wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf,
- sizeof(ath_beacon_hdr_t));
+ adf_nbuf_pull_head(nbuf, sizeof(ath_beacon_hdr_t));
bf = sc->sc_vap[vap_index].av_bcbuf;
adf_os_assert(bf);
a_uint32_t tmp;
#ifdef ATH_ENABLE_CABQ
- tsf = ath_hal_gettsf64(ah);
+ tsf = ah->ah_getTsf64(ah);
tmp = tsf - sc->sc_swba_tsf;
if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
ath_bufhead *head, a_int32_t dir)
{
struct ath_buf *bf;
- struct ieee80211_node_target *ni;
asf_tailq_foreach(bf, head, bf_list) {
if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap);
- ni = bf->bf_node;
bf->bf_node = NULL;
}
if (sc->sc_invalid)
return ADF_OS_IRQ_NONE;
- if (!ath_hal_intrpend(ah))
+ if (!ah->ah_isInterruptPending(ah))
return ADF_OS_IRQ_NONE;
- ath_hal_getisr(ah, &status);
+ ah->ah_getPendingInterrupts(ah, &status);
status &= sc->sc_imask;
if (status & HAL_INT_FATAL) {
- ath_hal_intrset(ah, 0);
+ ah->ah_setInterrupts(ah, 0);
ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
} else {
if (status & HAL_INT_SWBA) {
WMI_SWBA_EVENT swbaEvt;
struct ath_txq *txq = ATH_TXQ(sc, 8);
- swbaEvt.tsf = ath_hal_gettsf64(ah);
+ swbaEvt.tsf = ah->ah_getTsf64(ah);
swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq);
- sc->sc_swba_tsf = ath_hal_gettsf64(ah);
+ sc->sc_swba_tsf = ah->ah_getTsf64(ah);
wmi_event(sc->tgt_wmi_handle,
WMI_SWBA_EVENTID,
ath_uapsd_processtriggers(sc);
sc->sc_imask &= ~HAL_INT_RX;
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
}
{
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
struct ath_hal *ah = sc->sc_ah;
- a_uint32_t intr;
+ a_uint32_t intr = 0;
- if (data)
+ if (datalen == 4)
intr = (*(a_uint32_t *)data);
intr = adf_os_ntohl(intr);
sc->sc_imask |= HAL_INT_BMISS;
}
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
}
sc->sc_imask |= HAL_INT_GTT;
- if (ath_hal_htsupported(ah))
+ if (ath_hal_getcapability(ah, HAL_CAP_HT))
sc->sc_imask |= HAL_INT_CST;
adf_os_setup_intr(sc->sc_dev, ath_intr);
- ath_hal_intrset(ah, sc->sc_imask);
+ ah->ah_setInterrupts(ah, sc->sc_imask);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
+static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr)
+{
+ if ((addr & 0xffffe000) == 0x2000) {
+ /* SEEPROM registers */
+ ioread32_mac(addr);
+ if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0))
+ adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
+
+ return ioread32_mac(0x407c) & 0x0000ffff;
+ } else if (addr > 0xffff)
+ /* SoC registers */
+ return ioread32(addr);
+ else
+ /* MAC registers */
+ return ioread32_mac(addr);
+}
+
static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
{
addr = *(a_uint32_t *)(data + i);
addr = adf_os_ntohl(addr);
- if ((addr & 0xffffe000) == 0x2000) {
- /* SEEPROM */
- ath_hal_reg_read_target(ah, addr);
- if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) {
- adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
- }
- val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
- } else if (addr > 0xffff) {
- val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr;
- } else
- val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr);
-
- val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]);
+ val[i/sizeof(a_int32_t)] =
+ adf_os_ntohl(ath_reg_read_filter(ah, addr));
}
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
}
+static void ath_pll_reset_ones(struct ath_hal *ah)
+{
+ static uint8_t reset_pll = 0;
+
+ if(reset_pll == 0) {
+#if defined(PROJECT_K2)
+ /* here we write to core register */
+ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
+ /* and here to mac register */
+ iowrite32_mac(0x786c,
+ ioread32_mac(0x786c) | 0x6000000);
+ iowrite32_mac(0x786c,
+ ioread32_mac(0x786c) & (~0x6000000));
+
+ iowrite32(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
+
+#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
+ iowrite32_mac(0x7890,
+ ioread32_mac(0x7890) | 0x1800000);
+ iowrite32_mac(0x7890,
+ ioread32_mac(0x7890) & (~0x1800000));
+#endif
+ reset_pll = 1;
+ }
+}
+
+static void ath_hal_reg_write_filter(struct ath_hal *ah,
+ a_uint32_t reg, a_uint32_t val)
+{
+ if(reg > 0xffff) {
+ iowrite32(reg, val);
+#if defined(PROJECT_K2)
+ if(reg == 0x50040) {
+ static uint8_t flg=0;
+
+ if(flg == 0) {
+ /* reinit clock and uart.
+ * TODO: Independent on what host will
+ * here set. We do our own decision. Why? */
+ A_CLOCK_INIT(117);
+ A_UART_HWINIT(117*1000*1000, 19200);
+ flg = 1;
+ }
+ }
+#endif
+ } else {
+ if(reg == 0x7014)
+ ath_pll_reset_ones(ah);
+
+ iowrite32_mac(reg, val);
+ }
+}
+
static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
{
for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
t = (struct registerWrite *)(data+i);
- if( t->reg > 0xffff ) {
- a_uint32_t *pReg = (a_uint32_t *)t->reg;
+ ath_hal_reg_write_filter(ah, t->reg, t->val);
+ }
- *pReg = t->val;
+ wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
+}
-#if defined(PROJECT_K2)
- if( t->reg == 0x50040 ) {
- static uint8_t flg=0;
+static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command,
+ A_UINT16 SeqNo, A_UINT8 *data,
+ a_int32_t datalen)
+{
+ struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
+ struct ath_hal *ah = sc->sc_ah;
+ struct register_rmw *buf = (struct register_rmw *)data;
+ int i;
- if( flg == 0 ) {
- A_CLOCK_INIT(117);
- A_UART_HWINIT(117*1000*1000, 19200);
- flg = 1;
- }
- }
-#endif
- } else {
-#if defined(PROJECT_K2)
- if( t->reg == 0x7014 ) {
- static uint8_t resetPLL = 0;
- a_uint32_t *pReg;
-
- if( resetPLL == 0 ) {
- t->reg = 0x50044;
- pReg = (a_uint32_t *)t->reg;
- *pReg = 0;
- ath_hal_reg_write_target(ah, 0x786c,
- ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
- ath_hal_reg_write_target(ah, 0x786c,
- ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
- *pReg = 0x20;
- resetPLL = 1;
- }
- t->reg = 0x7014;
- }
-#elif defined(PROJECT_MAGPIE) && !defined (FPGA)
- if( t->reg == 0x7014 ){
- static uint8_t resetPLL = 0;
-
- if( resetPLL == 0 ) {
- ath_hal_reg_write_target(ah, 0x7890,
- ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
- ath_hal_reg_write_target(ah, 0x7890,
- ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
- resetPLL = 1;
- }
- }
-#endif
- ath_hal_reg_write_target(ah,t->reg,t->val);
- }
- }
+ for (i = 0; i < datalen;
+ i += sizeof(struct register_rmw)) {
+ a_uint32_t val;
+ buf = (struct register_rmw *)(data + i);
+ val = ath_reg_read_filter(ah, buf->reg);
+ val &= ~buf->clr;
+ val |= buf->set;
+ ath_hal_reg_write_filter(ah, buf->reg, val);
+ }
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
struct ath_hal *ah = sc->sc_ah;
- ath_hal_intrset(ah, 0);
+ ah->ah_setInterrupts(ah, 0);
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
}
struct ath_hal *ah = sc->sc_ah;
a_uint32_t q;
- if (data)
- q = *(a_uint32_t *)data;
+ if (!datalen)
+ goto done;
+
+ q = *(a_uint32_t *)data;
q = adf_os_ntohl(q);
ah->ah_stopTxDma(ah, q);
+done:
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
}
struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
struct ath_hal *ah = sc->sc_ah;
- ath_hal_stoppcurecv(ah);
- ath_hal_setrxfilter(ah, 0);
- ath_hal_stopdmarecv(ah);
+ ah->ah_stopPcuReceive(ah);
+ ah->ah_setRxFilter(ah, 0);
+ ah->ah_stopDmaReceive(ah);
sc->sc_rxlink = NULL;
wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
{ath_tx_stats_tgt, WMI_TX_STATS_CMDID, 0},
{ath_rx_stats_tgt, WMI_RX_STATS_CMDID, 0},
{ath_rc_mask_tgt, WMI_BITRATE_MASK_CMDID, 0},
+ {ath_hal_reg_rmw_tgt, WMI_REG_RMW_CMDID, 0},
};
/*****************/
ath_tgt_txq_setup(sc);
sc->sc_imask =0;
- ath_hal_intrset(ah,0);
+ ah->ah_setInterrupts(ah, 0);
return 0;
bad:
projects / librecmc / open-ath9k-htc-firmware.git / blobdiff