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arm: socfpga: set the mpuclk divider in the Altera group register
2017-02-08 Dinh Nguyenarm: socfpga: set the mpuclk divider in the Altera...
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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2016-12-06 Dinh NguyenMAINTAINERS: socfpga: update email address for Dinh...
...socfpga: update email address for Dinh Nguyen
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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2016-05-10 Dinh Nguyenarm: socfpga: Update iomux and pll for c5 socdk RevE
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2016-04-25 Dinh Nguyencmd: Kconfig: Add a Kconfig options for a few CMD
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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2016-03-05 Dinh Nguyenusb: dwc2: disable erroneous overcurrent condition
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2016-02-04 Dinh NguyenRevert "arm: socfpga: set the fpga global bit to disable...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2016-01-28 Dinh Nguyennet: phy: micrel: fix divisor value for KSZ9031 phy...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2016-01-28 Dinh Nguyennet: phy: micrel: add documentation for Micrel KSZ90x1...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2016-01-16 Dinh Nguyenarm: socfpga: set the fpga global bit to disable HPS...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-12-20 Dinh Nguyenarm: socfpga: fix trivial header preprocessor for socfpga_co...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-12-20 Dinh Nguyenarm: socfpga: fix up a questionable macro for SDMMC
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-12-20 Dinh Nguyenarm: socfpga: remove building scan manager
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-12-20 Dinh Nguyenarm: socfpga: introduce TARGET_SOCFPGA_GEN5 config...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-12-20 Dinh Nguyenarm: socfpga: remove note to add CONFIG_USB_DWC2_REG_ADDR
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-11-30 Dinh NguyenARM: socfpga: rename the cyclone5 and arria5 base address...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-11-30 Dinh NguyenARM: socfpga: arria10: add base address map for Arria10
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-11-03 Dinh Nguyenarm: socfpga: reset: correct dma, qspi, and sdmmc reset...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-10-16 Dinh Nguyenarm: dts: socfpga: add "u-boot,dm-pre-reloc" to socfpga_cycl...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-10-16 Dinh Nguyenarm: socfpga: enable data/inst prefetch and shared...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-09-24 Dinh Nguyenarm: socfpga: Enable saveenv for SD/MMC
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-09-23 Dinh Nguyenarm: socfpga: update MAINTAINERS' file for cyclone5_socdk...
the same time, update the email for Dinh Nguyen.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-09-23 Dinh Nguyenarm: socfpga: rename socfpga_cyclone5 and socfpga_arria5...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-09-04 Dinh Nguyenarm: socfpga: Add support for the Terasic DE-0 Atlas...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-08-08 Dinh Nguyenarm: socfpga: misc: Add support for printing FPGA type
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-08-08 Dinh Nguyenarm: socfpga: scan: Add code to get FPGA ID
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-08-08 Dinh Nguyenddr: altera: sequencer: add RW_MGR_MEM_NUMBER_OF_RANKS
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-08-08 Dinh Nguyenarm: socfpga: enable the Altera SDRAM controller driver
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-08-08 Dinh Nguyendriver/ddr/altera: Add the sdram calibration portion
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-08-08 Dinh Nguyendriver/ddr/altera: Add DDR driver for Altera's SDRAM...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-05-07 Dinh Nguyengit-mailrc: add Dinh Nguyen as a contact for SoCFPGA
git-mailrc: add Dinh Nguyen as a contact for SoCFPGA
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: update peripheral pll for dev kit
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: add board_init_f to SPL
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Add s_init stub
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: fix uart0 pin mux configuration
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Add SDRAM check
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Adjust the SYS_INIT_RAM_SIZE to...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: add CONFIG_SPL_STACK to socfpga_common.h
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Use common lowlevel_init
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: printout sdram size
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: add sdram init and calibration
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: allow bootrom to enable IOs after...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Add call to timer_init
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: enable sdram, timer and uart
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: add functions to bring sdram, timer,...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2015-04-21 Dinh Nguyenarm: socfpga: spl: Add CONFIG_SPL_MAX_SIZE to be 64KB
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2014-12-06 Dinh Nguyensocfpga: correctly increment freeze_controller_base...
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2014-12-06 Dinh Nguyensocfpga: add missing struct member fifo_triple_byte
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2014-12-06 Dinh Nguyenarm: socfpga: set skew settings for ethernet phy
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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2014-07-29 Dinh Nguyenboards.cfg : Add maintainers entries for SOCFPGA
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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2013-07-25 Dinh Nguyensocfpga: Move board/socfpga_cyclone5 to board/socfpga
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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2012-10-04 Dinh NguyenARM: Add Altera SOCFPGA Cyclone5
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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2012-10-03 Dinh NguyenARM: kirkwood/orion5x: Use reset_cpu definition in...
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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2012-07-11 Dinh Nguyennet/designware: Consecutive writes to the same register...
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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