From 8804cc94e3b66550797279f540b960d18a78421f Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Fri, 8 Mar 2013 14:45:06 -0800 Subject: [PATCH 1/1] Initial cut of the open ath9k htc firmware. --- LICENCE.TXT | 21 + Makefile | 89 + NOTICE.TXT | 149 + build | 22 + .../build/include/xtensa/config/core-isa.h | 424 + .../build/include/xtensa/config/core-matmap.h | 301 + .../build/include/xtensa/config/specreg.h | 84 + .../build/include/xtensa/config/tie.h | 54 + .../build/k2_1_0/image/k2_ram/Makefile | 80 + .../image/k2_ram/builds_fusion_vista.ram | 45 + .../build/k2_1_0/image/k2_ram/rom.addrs.ld | 69 + .../build/k2_1_0/image/k2_ram/target.ram.ld | 264 + .../k2_1_0/image/k2_ram/target.ram_debug.ld | 264 + .../build/k2_1_0/lib/ram/dummy.txt | 0 .../build/k2_1_0/ram/adf/Makefile | 61 + .../build/k2_1_0/ram/adf/Makefile.ss | 48 + .../build/k2_1_0/ram/buf_pool/Makefile | 59 + .../build/k2_1_0/ram/buf_pool/Makefile.ss | 44 + .../build/k2_1_0/ram/carrier_apd/Makefile | 59 + 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a/LICENCE.TXT b/LICENCE.TXT new file mode 100644 index 0000000..ee2738e --- /dev/null +++ b/LICENCE.TXT @@ -0,0 +1,21 @@ +Files with a Qualcomm Atheros / Atheros licence fall under the following +licence. Please see NOTICES.TXT for information about other files in this +repository. + +---- + +Copyright (c) 2013 Qualcomm Atheros, Inc. + +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH +REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, +INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM +LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR +OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR +PERFORMANCE OF THIS SOFTWARE. + +---- diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..81f4500 --- /dev/null +++ b/Makefile @@ -0,0 +1,89 @@ +GMP_VER=5.0.5 +GMP_URL=http://ftp.gnu.org/gnu/gmp/gmp-$(GMP_VER).tar.bz2 +GMP_TAR=gmp-$(GMP_VER).tar.bz2 + +MPFR_VER=3.1.1 +MPFR_URL=http://ftp.gnu.org/gnu/mpfr/mpfr-$(MPFR_VER).tar.bz2 +MPFR_TAR=mpfr-$(MPFR_VER).tar.bz2 + +MPC_VER=1.0.1 +MPC_URL=http://ftp.gnu.org/gnu/mpc/mpc-$(MPC_VER).tar.gz +MPC_TAR=mpc-$(MPC_VER).tar.gz + +BINUTILS_VER=2.23.1 +BINUTILS_URL=http://ftp.gnu.org/gnu/binutils/binutils-$(BINUTILS_VER).tar.bz2 +BINUTILS_TAR=binutils-$(BINUTILS_VER).tar.bz2 + +GCC_VER=4.7.2 +GCC_URL=http://ftp.gnu.org/gnu/gcc/gcc-$(GCC_VER)/gcc-$(GCC_VER).tar.bz2 +GCC_TAR=gcc-$(GCC_VER).tar.bz2 + +BASEDIR=$(shell pwd) +TOOLCHAIN_DIR=$(BASEDIR)/toolchain +TARGET=xtensa-elf + +all: toolchain + +gmp-$(GMP_VER): + wget -N -P $(TOOLCHAIN_DIR)/dl $(GMP_URL) + tar -C $(TOOLCHAIN_DIR)/dl -xjf $(TOOLCHAIN_DIR)/dl/$(GMP_TAR) + +gmp: gmp-$(GMP_VER) + mkdir -p $(TOOLCHAIN_DIR)/build/gmp + cd $(TOOLCHAIN_DIR)/build/gmp; \ + $(TOOLCHAIN_DIR)/dl/$, which includes this file, for more details. + */ + +/* + * Xtensa processor core configuration information. + * + * Customer ID=4748; Build=0x2230f; Copyright (c) 1999-2008 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 1 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ +#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* floating point pkg */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ + +#define XCHAL_CORE_ID "Magpie_P0" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x0002230F /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC280DBFF /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x0D02230F /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX2.1.0" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2210 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 0 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 221000 /* major*100+minor */ +#define XCHAL_HW_REL_LX2 1 +#define XCHAL_HW_REL_LX2_1 1 +#define XCHAL_HW_REL_LX2_1_0 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2210 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 0 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 221000 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2210 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 0 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 221000 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 0 +#define XCHAL_DCACHE_SETWIDTH 0 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 1 +#define XCHAL_DCACHE_WAYS 1 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 0 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Number of encoded cache attr bits (see for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x00800000 +#define XCHAL_INSTRAM0_PADDR 0x00800000 +#define XCHAL_INSTRAM0_SIZE 4194304 +#define XCHAL_INSTRAM0_ECC_PARITY 0 + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x00400000 +#define XCHAL_DATARAM0_PADDR 0x00400000 +#define XCHAL_DATARAM0_SIZE 4194304 +#define XCHAL_DATARAM0_ECC_PARITY 0 + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 1 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 19 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x00000001 +#define XCHAL_INTLEVEL2_MASK 0x00007FFE +#define XCHAL_INTLEVEL3_MASK 0x00038000 +#define XCHAL_INTLEVEL4_MASK 0x00000000 +#define XCHAL_INTLEVEL5_MASK 0x00040000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00000000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00000001 +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00007FFF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x0003FFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x0003FFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x0007FFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x0007FFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x0007FFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 2 +#define XCHAL_INT2_LEVEL 2 +#define XCHAL_INT3_LEVEL 2 +#define XCHAL_INT4_LEVEL 2 +#define XCHAL_INT5_LEVEL 2 +#define XCHAL_INT6_LEVEL 2 +#define XCHAL_INT7_LEVEL 2 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 2 +#define XCHAL_INT10_LEVEL 2 +#define XCHAL_INT11_LEVEL 2 +#define XCHAL_INT12_LEVEL 2 +#define XCHAL_INT13_LEVEL 2 +#define XCHAL_INT14_LEVEL 2 +#define XCHAL_INT15_LEVEL 3 +#define XCHAL_INT16_LEVEL 3 +#define XCHAL_INT17_LEVEL 3 +#define XCHAL_INT18_LEVEL 5 +#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 5 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_NMI + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFF80000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000001 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0003FFFC +#define XCHAL_INTTYPE_MASK_TIMER 0x00000002 +#define XCHAL_INTTYPE_MASK_NMI 0x00040000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 1 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 18 /* non-maskable interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL1_NUM 0 +#define XCHAL_INTLEVEL5_NUM 18 +/* (There are many interrupts each at level(s) 2, 3.) */ + + +/* + * External interrupt vectors/levels. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ +#define XCHAL_EXTINT0_NUM 2 /* (intlevel 2) */ +#define XCHAL_EXTINT1_NUM 3 /* (intlevel 2) */ +#define XCHAL_EXTINT2_NUM 4 /* (intlevel 2) */ +#define XCHAL_EXTINT3_NUM 5 /* (intlevel 2) */ +#define XCHAL_EXTINT4_NUM 6 /* (intlevel 2) */ +#define XCHAL_EXTINT5_NUM 7 /* (intlevel 2) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 2) */ +#define XCHAL_EXTINT8_NUM 10 /* (intlevel 2) */ +#define XCHAL_EXTINT9_NUM 11 /* (intlevel 2) */ +#define XCHAL_EXTINT10_NUM 12 /* (intlevel 2) */ +#define XCHAL_EXTINT11_NUM 13 /* (intlevel 2) */ +#define XCHAL_EXTINT12_NUM 14 /* (intlevel 2) */ +#define XCHAL_EXTINT13_NUM 15 /* (intlevel 3) */ +#define XCHAL_EXTINT14_NUM 16 /* (intlevel 3) */ +#define XCHAL_EXTINT15_NUM 17 /* (intlevel 3) */ +#define XCHAL_EXTINT16_NUM 18 /* (intlevel 5) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x008E0800 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x008E0800 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x008E0000 +#define XCHAL_RESET_VECTOR0_PADDR 0x008E0000 +#define XCHAL_RESET_VECTOR1_VADDR 0x0F000000 +#define XCHAL_RESET_VECTOR1_PADDR 0x0F000000 +#define XCHAL_RESET_VECTOR_VADDR 0x008E0000 +#define XCHAL_RESET_VECTOR_PADDR 0x008E0000 +#define XCHAL_USER_VECOFS 0x00000620 +#define XCHAL_USER_VECTOR_VADDR 0x008E0E20 +#define XCHAL_USER_VECTOR_PADDR 0x008E0E20 +#define XCHAL_KERNEL_VECOFS 0x00000540 +#define XCHAL_KERNEL_VECTOR_VADDR 0x008E0D40 +#define XCHAL_KERNEL_VECTOR_PADDR 0x008E0D40 +#define XCHAL_DOUBLEEXC_VECOFS 0x00000720 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x008E0F20 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x008E0F20 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x008E0800 +#define XCHAL_WINDOW_VECTORS_PADDR 0x008E0800 +#define XCHAL_INTLEVEL2_VECOFS 0x00000220 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x008E0A20 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x008E0A20 +#define XCHAL_INTLEVEL3_VECOFS 0x00000320 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x008E0B20 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x008E0B20 +#define XCHAL_INTLEVEL4_VECOFS 0x00000420 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x008E0C20 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x008E0C20 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000004E4 +#define XCHAL_NMI_VECTOR_VADDR 0x008E0CE4 +#define XCHAL_NMI_VECTOR_PADDR 0x008E0CE4 +#define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ diff --git a/target_firmware/magpie_fw_dev/build/include/xtensa/config/core-matmap.h b/target_firmware/magpie_fw_dev/build/include/xtensa/config/core-matmap.h new file mode 100644 index 0000000..f0acaca --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/include/xtensa/config/core-matmap.h @@ -0,0 +1,301 @@ +/* + * xtensa/config/core-matmap.h -- Memory access and translation mapping + * parameters (CHAL) of the Xtensa processor core configuration. + * + * If you are using Xtensa Tools, see (which includes + * this file) for more details. + * + * In the Xtensa processor products released to date, all parameters + * defined in this file are derivable (at least in theory) from + * information contained in the core-isa.h header file. + * In particular, the following core configuration parameters are relevant: + * XCHAL_HAVE_CACHEATTR + * XCHAL_HAVE_MIMIC_CACHEATTR + * XCHAL_HAVE_XLT_CACHEATTR + * XCHAL_HAVE_PTP_MMU + * XCHAL_ITLB_ARF_ENTRIES_LOG2 + * XCHAL_DTLB_ARF_ENTRIES_LOG2 + * XCHAL_DCACHE_IS_WRITEBACK + * XCHAL_ICACHE_SIZE (presence of I-cache) + * XCHAL_DCACHE_SIZE (presence of D-cache) + * XCHAL_HW_VERSION_MAJOR + * XCHAL_HW_VERSION_MINOR + */ + +/* + * Customer ID=4748; Build=0x2230f; Copyright (c) 1999-2008 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + + +#ifndef XTENSA_CONFIG_CORE_MATMAP_H +#define XTENSA_CONFIG_CORE_MATMAP_H + + +/*---------------------------------------------------------------------- + CACHE (MEMORY ACCESS) ATTRIBUTES + ----------------------------------------------------------------------*/ + + +/* Cache Attribute encodings -- lists of access modes for each cache attribute: */ +#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_BYPASS XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION XCHAL_SEP \ + XTHAL_FAM_EXCEPTION +#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_EXCEPTION XCHAL_SEP \ + XTHAL_LAM_BYPASSG XCHAL_SEP \ + XTHAL_LAM_EXCEPTION +#define XCHAL_SCA_LIST XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_EXCEPTION XCHAL_SEP \ + XTHAL_SAM_BYPASS XCHAL_SEP \ + XTHAL_SAM_EXCEPTION + + +/* + * Specific encoded cache attribute values of general interest. + * If a specific cache mode is not available, the closest available + * one is returned instead (eg. writethru instead of writeback, + * bypass instead of writethru). + */ +#define XCHAL_CA_BYPASS 2 /* cache disabled (bypassed) mode */ +#define XCHAL_CA_WRITETHRU 2 /* cache enabled (write-through) mode */ +#define XCHAL_CA_WRITEBACK 2 /* cache enabled (write-back) mode */ +#define XCHAL_CA_BYPASS_RW 0 /* cache disabled (bypassed) mode (no exec) */ +#define XCHAL_CA_WRITETHRU_RW 0 /* cache enabled (write-through) mode (no exec) */ +#define XCHAL_CA_WRITEBACK_RW 0 /* cache enabled (write-back) mode (no exec) */ +#define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */ +#define XCHAL_CA_ISOLATE 0 /* cache isolate (accesses go to cache not memory) mode */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* + * General notes on MMU parameters. + * + * Terminology: + * ASID = address-space ID (acts as an "extension" of virtual addresses) + * VPN = virtual page number + * PPN = physical page number + * CA = encoded cache attribute (access modes) + * TLB = translation look-aside buffer (term is stretched somewhat here) + * I = instruction (fetch accesses) + * D = data (load and store accesses) + * way = each TLB (ITLB and DTLB) consists of a number of "ways" + * that simultaneously match the virtual address of an access; + * a TLB successfully translates a virtual address if exactly + * one way matches the vaddr; if none match, it is a miss; + * if multiple match, one gets a "multihit" exception; + * each way can be independently configured in terms of number of + * entries, page sizes, which fields are writable or constant, etc. + * set = group of contiguous ways with exactly identical parameters + * ARF = auto-refill; hardware services a 1st-level miss by loading a PTE + * from the page table and storing it in one of the auto-refill ways; + * if this PTE load also misses, a miss exception is posted for s/w. + * min-wired = a "min-wired" way can be used to map a single (minimum-sized) + * page arbitrarily under program control; it has a single entry, + * is non-auto-refill (some other way(s) must be auto-refill), + * all its fields (VPN, PPN, ASID, CA) are all writable, and it + * supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current + * restriction is that this be the only page size it supports). + * + * TLB way entries are virtually indexed. + * TLB ways that support multiple page sizes: + * - must have all writable VPN and PPN fields; + * - can only use one page size at any given time (eg. setup at startup), + * selected by the respective ITLBCFG or DTLBCFG special register, + * whose bits n*4+3 .. n*4 index the list of page sizes for way n + * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n); + * this list may be sparse for auto-refill ways because auto-refill + * ways have independent lists of supported page sizes sharing a + * common encoding with PTE entries; the encoding is the index into + * this list; unsupported sizes for a given way are zero in the list; + * selecting unsupported sizes results in undefined hardware behaviour; + * - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition). + */ + +#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */ +#define XCHAL_MMU_ASID_KERNEL 0 /* ASID value indicating kernel (ring 0) address space */ +#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */ +#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */ +#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 29 /* max page size in a PTE structure (log2) */ +#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 29 /* min page size in a PTE structure (log2) */ + + +/*** Instruction TLB: ***/ + +#define XCHAL_ITLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_ITLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_ITLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_ITLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_ITLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* ITLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_ITLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_ITLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_ITLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_ITLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_ITLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_ITLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_ITLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_ITLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_ITLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_ITLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_ITLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_ITLB_SET0_E7_VPN_CONST 0xE0000000 +/* Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero): */ +#define XCHAL_ITLB_SET0_E0_PPN_CONST 0x00000000 +#define XCHAL_ITLB_SET0_E1_PPN_CONST 0x20000000 +#define XCHAL_ITLB_SET0_E2_PPN_CONST 0x40000000 +#define XCHAL_ITLB_SET0_E3_PPN_CONST 0x60000000 +#define XCHAL_ITLB_SET0_E4_PPN_CONST 0x80000000 +#define XCHAL_ITLB_SET0_E5_PPN_CONST 0xA0000000 +#define XCHAL_ITLB_SET0_E6_PPN_CONST 0xC0000000 +#define XCHAL_ITLB_SET0_E7_PPN_CONST 0xE0000000 +/* Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_ITLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_ITLB_SET0_E7_CA_RESET 0x02 + + +/*** Data TLB: ***/ + +#define XCHAL_DTLB_WAY_BITS 0 /* number of bits holding the ways */ +#define XCHAL_DTLB_WAYS 1 /* number of ways (n-way set-associative TLB) */ +#define XCHAL_DTLB_ARF_WAYS 0 /* number of auto-refill ways */ +#define XCHAL_DTLB_SETS 1 /* number of sets (groups of ways with identical settings) */ + +/* Way set to which each way belongs: */ +#define XCHAL_DTLB_WAY0_SET 0 + +/* Ways sets that are used by hardware auto-refill (ARF): */ +#define XCHAL_DTLB_ARF_SETS 0 /* number of auto-refill sets */ + +/* Way sets that are "min-wired" (see terminology comment above): */ +#define XCHAL_DTLB_MINWIRED_SETS 0 /* number of "min-wired" sets */ + + +/* DTLB way set 0 (group of ways 0 thru 0): */ +#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */ +#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */ +#define XCHAL_DTLB_SET0_ENTRIES_LOG2 3 /* log2(number of entries in this way) */ +#define XCHAL_DTLB_SET0_ENTRIES 8 /* number of entries in this way (always a power of 2) */ +#define XCHAL_DTLB_SET0_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */ +#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */ +#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 29 /* log2(minimum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */ +#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 29 /* list of log2(page size)s, separated by XCHAL_SEP; + 2^PAGESZ_BITS entries in list, unsupported entries are zero */ +#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0xE0000000 /* constant PPN bits, including entry index bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */ +#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */ +#define XCHAL_DTLB_SET0_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */ +/* Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero): */ +#define XCHAL_DTLB_SET0_E0_VPN_CONST 0x00000000 +#define XCHAL_DTLB_SET0_E1_VPN_CONST 0x20000000 +#define XCHAL_DTLB_SET0_E2_VPN_CONST 0x40000000 +#define XCHAL_DTLB_SET0_E3_VPN_CONST 0x60000000 +#define XCHAL_DTLB_SET0_E4_VPN_CONST 0x80000000 +#define XCHAL_DTLB_SET0_E5_VPN_CONST 0xA0000000 +#define XCHAL_DTLB_SET0_E6_VPN_CONST 0xC0000000 +#define XCHAL_DTLB_SET0_E7_VPN_CONST 0xE0000000 +/* Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero): */ +#define XCHAL_DTLB_SET0_E0_PPN_CONST 0x00000000 +#define XCHAL_DTLB_SET0_E1_PPN_CONST 0x20000000 +#define XCHAL_DTLB_SET0_E2_PPN_CONST 0x40000000 +#define XCHAL_DTLB_SET0_E3_PPN_CONST 0x60000000 +#define XCHAL_DTLB_SET0_E4_PPN_CONST 0x80000000 +#define XCHAL_DTLB_SET0_E5_PPN_CONST 0xA0000000 +#define XCHAL_DTLB_SET0_E6_PPN_CONST 0xC0000000 +#define XCHAL_DTLB_SET0_E7_PPN_CONST 0xE0000000 +/* Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero): */ +#define XCHAL_DTLB_SET0_E0_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E1_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E2_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E3_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E4_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E5_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E6_CA_RESET 0x02 +#define XCHAL_DTLB_SET0_E7_CA_RESET 0x02 + + + + +#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/ diff --git a/target_firmware/magpie_fw_dev/build/include/xtensa/config/specreg.h b/target_firmware/magpie_fw_dev/build/include/xtensa/config/specreg.h new file mode 100644 index 0000000..f342a9d --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/include/xtensa/config/specreg.h @@ -0,0 +1,84 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* $Id: //depot/rel/BadgerPass/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ + +/* + * Customer ID=4748; Build=0x2230f; Copyright (c) 1998-2002 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef XTENSA_SPECREG_H +#define XTENSA_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include + + +/* Special registers: */ +#define LBEG 0 +#define LEND 1 +#define LCOUNT 2 +#define SAR 3 +#define LITBASE 5 +#define SCOMPARE1 12 +#define WINDOWBASE 72 +#define WINDOWSTART 73 +#define IBREAKENABLE 96 +#define DDR 104 +#define IBREAKA_0 128 +#define IBREAKA_1 129 +#define DBREAKA_0 144 +#define DBREAKA_1 145 +#define DBREAKC_0 160 +#define DBREAKC_1 161 +#define EPC_1 177 +#define EPC_2 178 +#define EPC_3 179 +#define EPC_4 180 +#define EPC_5 181 +#define DEPC 192 +#define EPS_2 194 +#define EPS_3 195 +#define EPS_4 196 +#define EPS_5 197 +#define EXCSAVE_1 209 +#define EXCSAVE_2 210 +#define EXCSAVE_3 211 +#define EXCSAVE_4 212 +#define EXCSAVE_5 213 +#define INTERRUPT 226 +#define INTENABLE 228 +#define PS 230 +#define VECBASE 231 +#define EXCCAUSE 232 +#define DEBUGCAUSE 233 +#define CCOUNT 234 +#define PRID 235 +#define ICOUNT 236 +#define ICOUNTLEVEL 237 +#define EXCVADDR 238 +#define CCOMPARE_0 240 +#define MISC_REG_0 244 +#define MISC_REG_1 245 + +/* Special cases (bases of special register series): */ +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 +#define EPC 176 +#define EPS 192 +#define EXCSAVE 208 +#define CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define INTREAD 226 +#define INTSET 226 +#define INTCLEAR 227 + +#endif /* XTENSA_SPECREG_H */ diff --git a/target_firmware/magpie_fw_dev/build/include/xtensa/config/tie.h b/target_firmware/magpie_fw_dev/build/include/xtensa/config/tie.h new file mode 100644 index 0000000..b53910c --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/include/xtensa/config/tie.h @@ -0,0 +1,54 @@ +/* + * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + */ + +/* + * This header file describes this specific Xtensa processor's TIE extensions + * that extend basic Xtensa core functionality. It is customized to this + * Xtensa processor configuration. + * + * Customer ID=4748; Build=0x2230f; Copyright (C) 1999-2008 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef _XTENSA_CORE_TIE_H +#define _XTENSA_CORE_TIE_H + +#define XCHAL_CP_NUM 0 /* number of coprocessors */ +#define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE 4 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE 16 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_{UREG,SREG,REGF} macros (they + * are not defined here) before expanding the XCHAL_SA_xxx_LIST macros. + * + * XCHAL_SA_SREG(dbnum,offset,size,contentsz,align,name,sregnum,bitmask,x,x) + * XCHAL_SA_UREG(dbnum,offset,size,contentsz,align,name,uregnum,bitmask,x,x) + * XCHAL_SA_REGF(dbnum,offset,size,contentsz,align,name,index,span,x,x, + * basename,regf_name,regf_numentries) + */ + +#define XCHAL_SA_NCP_NUM 1 +#define XCHAL_SA_NCP_LIST \ + XCHAL_SA_SREG(0x020C, 0, 4, 4, 4, scompare1, 12,0xFFFFFFFF,0,0) + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +#endif /*_XTENSA_CORE_TIE_H*/ diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/Makefile b/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/Makefile new file mode 100755 index 0000000..5870104 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/Makefile @@ -0,0 +1,80 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + +DIRS = \ + $(PRJ_ROOT)/$(TARGET)/adf \ + $(PRJ_ROOT)/$(TARGET)/init \ + $(PRJ_ROOT)/$(TARGET)/wmi \ + $(PRJ_ROOT)/$(TARGET)/wlan \ + $(PRJ_ROOT)/$(TARGET)/carrier_apd \ + $(PRJ_ROOT)/$(TARGET)/cmnos \ + $(PRJ_ROOT)/$(TARGET)/htc \ + $(PRJ_ROOT)/$(TARGET)/hif \ + $(PRJ_ROOT)/$(TARGET)/buf_pool + +COMPONENTS_sw.ram = \ + $(LIB_PATH)/libcmnos.a \ + $(LIB_PATH)/libadf.a \ + $(LIB_PATH)/libwmi.a \ + $(LIB_PATH)/libwlan.a \ + $(LIB_PATH)/libcarrier_apd.a \ + $(LIB_PATH)/libbuf_pool.a \ + $(LIB_PATH)/libhif.a \ + $(LIB_PATH)/libhtc.a + + +ifeq ($(debug),1) +LINKFLAGS_sw.ram = \ + -T./target.ram_debug.ld \ + --start-group \ + $(COMPONENTS_sw.ram) \ + --end-group +else +LINKFLAGS_sw.ram = \ + -T./target.ram.ld \ + --start-group \ + $(COMPONENTS_sw.ram) \ + --end-group +endif + +all: util toolchain_prep + @for i in $(DIRS) ; do $(MAKE) -C $$i all CC=$(XCC) LD=$(XLD) AR=$(XAR) || exit ; done + +dep: util toolchain_prep + @for i in $(DIRS) ; do $(MAKE) -C $$i dep CC=$(XCC) LD=$(XLD) AR=$(XAR) || exit ; done + +clean: + find $(PRJ_ROOT)/ram -name "*.o" -exec rm -f {} \; + rm -rf $(PRJ_ROOT)/lib/ram/*.a + @for i in $(DIRS) ; do echo $$i; $(MAKE) -C $$i clean; done + rm -f *.bin *.hex *.objdump *.out *.map *.c *.fw *.fw.back *.c.back + rm -f ../../../utility/athfw2lnx/athfw2lnx + +init: toolchain_prep + for i in $(DIRS) ; do $(MAKE) -C $$i init CC=$(XCC) LD=$(XLD) AR=$(XAR) ; done + +build: binary image + +binary: + $(XLD) $(PRJ_ROOT)/ram/init/obj/app_start.o $(PRJ_ROOT)/ram/init/obj/init.o $(PRJ_ROOT)/ram/init/obj/magpie.o $(LINKFLAGS_sw.ram) -Map $(PRJNAME).map -o $(PRJNAME).out + +toolchain_prep: +ifeq ($(XTENSA_TOOL_INSTALLED),0) + @cd ../../../toolchain && \ + (test -d tools) || tar xvzf toolchain.tgz +endif + +image: + $(XOBJCOPY) \ + --change-section-lma .text-0x400000 \ + --change-section-vma .text-0x400000 \ + -O binary $(PRJNAME).out $(PRJNAME).bin + rm -f ../../../utility/athfw2lnx/athfw2lnx + $(shell cp -f fwu.c fwu.c.back 2> /dev/null) + $(shell cp -f htc_9271.fw htc_9271.fw.back 2> /dev/null) + $(BIN2HEX) $(PRJNAME).bin fwu.c 0 $(MAGPIE_IF) + $(MAKE) -C ../../../utility/athfw2lnx ATH_FW=$(PRJ_ROOT)/image/k2_ram/fwu.c + $(shell ../../../utility/athfw2lnx/athfw2lnx > htc_9271.fw) + +util: + $(MAKE) -C ../../../utility/ clean + $(MAKE) -C ../../../utility/ all diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/builds_fusion_vista.ram b/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/builds_fusion_vista.ram new file mode 100755 index 0000000..35f7fa1 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/builds_fusion_vista.ram @@ -0,0 +1,45 @@ +#!/bin/bash + +MAGPIE_ROOT=`pwd`/../../../../;export MAGPIE_ROOT +PROJECT=k2; export PROJECT +TARGET=ram; export TARGET + +PRJ_ROOT=$MAGPIE_ROOT/build/k2_1_0; export PRJ_ROOT +PRJNAME=ram; export PRJNAME +PRJPATH=$PRJ_ROOT/$PRJNAME; export PRJPATH +PRJ_HPATH=$PRJPATH/inc; export PRJ_HPATH + +XTENSA_TOOLS_INC=$XTENSA_TOOLS_ROOT/xtensa-elf/include +XTENSA_GCC_INC=$XTENSA_TOOLS_ROOT/lib/gcc/xtensa-elf/4.7.2/include + +HPATH=" -I$XTENSA_TOOLS_INC \ + -I$XTENSA_GCC_INC \ + -I$MAGPIE_ROOT/target/inc/k2 \ + -I$MAGPIE_ROOT/target/inc/k2/k2 \ + -I$MAGPIE_ROOT/../wlan/include \ + -I$MAGPIE_ROOT/../wlan/include/k2 \ + -I$MAGPIE_ROOT/../wlan/ \ + -I$MAGPIE_ROOT/target/cmnos/ \ + -I$MAGPIE_ROOT/target/wmi/ \ + -I$MAGPIE_ROOT/target/wlan/ \ + -I$MAGPIE_ROOT/target/buf_pool/ \ + -I$MAGPIE_ROOT/target/htc/ \ + -I$MAGPIE_ROOT/target/inc \ + -I$MAGPIE_ROOT/target/inc/OTUS \ + -I$MAGPIE_ROOT/target/adf/ \ + -I$MAGPIE_ROOT/build/include"; + + +export HPATH + + +LIB_PATH=$PRJ_ROOT/lib/ram; export LIB_PATH +CROSS_COMPILE=$XTENSA_TOOLS_ROOT/bin; export CROSS_COMPILE +TARGET_PREFIX=xt-; export TARGET_PREFIX + +ARCH=""; export ARCH +DEFS=""; export DEFS +CCOPTS=" -g -Os -Wunused-label -Wunused-variable -Wunused-value -Wpointer-arith -Wundef -nostdlib -Wundef"; export CCOPTS +ASOPTS="-Wa, --fatal-warnings"; export ASOPTS +DFLAGS="-D_RAM_ -DPROJECT_K2 -DBIG_ENDIAN -D_BYTE_ORDER=_BIG_ENDIAN -D__XTENSA__ -DFUSION_USB_FW -DRX_SCATTER -DFUSION_USB_ENABLE_TX_STREAM -DFUSION_USB_ENABLE_RX_STREAM -DATH_ENABLE_CABQ"; export DFLAGS +TARGET_LDFLAGS="-g -nostdlib"; export TARGET_LDFLAGS diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/rom.addrs.ld b/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/rom.addrs.ld new file mode 100755 index 0000000..936d4d4 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/rom.addrs.ld @@ -0,0 +1,69 @@ +PROVIDE ( _indir_tbl = 0x00500000 ); +PROVIDE (athos_indirection_table_install = 0x008e1548); +PROVIDE ( memcpy = 0x008e4eb8 ); +PROVIDE ( memset = 0x008e519c ); +PROVIDE ( __divsi3 = 0x008e4cec ); +PROVIDE ( __udivsi3 = 0x008e4da0 ); +PROVIDE ( __umodsi3 = 0x008e4df0 ); +PROVIDE ( __modsi3 = 0x008e4d54 ); +PROVIDE ( athos_interrupt_init = 0x008e1600 ); +PROVIDE ( athos_unblock_all_intrlvl = 0x008e1460 ); +PROVIDE ( athos_interrupt_handler = 0x008e15f0 ); +PROVIDE ( _xtos_set_interrupt_handler = 0x008e1230 ); +PROVIDE ( hif_module_install = 0x008e2bd4 ); +PROVIDE ( strcmp = 0x008e48b4 ); +PROVIDE ( strlen = 0x008e4a64 ); +PROVIDE ( strcpy = 0x008e49cc ); +PROVIDE ( strncpy = 0x008e4b90 ); +PROVIDE ( Xthal_num_ccompare = 0x004e5869 ); +PROVIDE ( cticks = 0x0050088c ); +PROVIDE ( UsbDeviceDescriptor = 0x004e0100 ); +PROVIDE ( String00Descriptor = 0x004e01a0 ); +PROVIDE ( String10Descriptor = 0x004e01b0 ); +PROVIDE ( String20Descriptor = 0x004e01c0 ); +PROVIDE ( String30Descriptor = 0x004e01e0 ); +PROVIDE ( HIFusb_DescTraceDump = 0x008e2c18 ); +PROVIDE ( xthal_get_intenable = 0x008e4cd4 ); +PROVIDE ( xthal_set_intenable = 0x008e4ce4 ); +PROVIDE ( xthal_get_interrupt = 0x008e4cdc ); +PROVIDE ( xthal_get_ccompare = 0x008e4cc4 ); +PROVIDE ( xthal_set_ccompare = 0x008e4cb4 ); +PROVIDE ( xthal_get_ccount = 0x008e4cac ); +PROVIDE ( Xthal_num_ccompare = 0x004e5869 ); +PROVIDE ( zfDmaReclaimPacket = 0x008e4568 ); +PROVIDE ( zfDmaPutPacket = 0x008e45fc ); +PROVIDE ( zfDmaGetPacket = 0x008e452c ); +PROVIDE ( handle_hp_rx_complete_isr = 0x008e2b18 ); +PROVIDE ( handle_mp_rx_complete_isr = 0x008e2b38 ); +PROVIDE ( handle_tx_complete_isr = 0x008e2adc ); +PROVIDE ( u16TxRxCounter = 0x005009e4 ); +PROVIDE ( pu8DescriptorEX = 0x005009e0 ); +PROVIDE ( fwCheckSum = 0x005009dc ); +PROVIDE ( eUsbCxCommand = 0x005009f0 ); +PROVIDE ( ControlCmd = 0x005009c0 ); +PROVIDE ( eUsbCxFinishAction = 0x005009ec ); +PROVIDE ( UsbChirpFinish = 0x005009f4 ); +PROVIDE ( cmnos_allocram_debug = 0x008e1ae8 ); +PROVIDE ( g_hifUSBCtx = 0x00500978 ); +PROVIDE ( _HIFusb_return_recv_buf = 0x008e2a74 ); +PROVIDE ( vdesc_module_install = 0x008e413c ); +PROVIDE ( vbuf_module_install = 0x008e408c ); +PROVIDE ( mUsbFIFOConfig = 0x008e3ca4 ); +PROVIDE ( mUsbEPMxPtSzHigh = 0x008e3cc4 ); +PROVIDE ( mUsbEPMxPtSzLow = 0x008e3cec ); +PROVIDE ( mUsbEPinHighBandSet = 0x008e3d10 ); +PROVIDE ( mUsbFIFOConfig = 0x008e3ca4 ); +PROVIDE ( mUsbFIFOMap = 0x008e3c84 ); +PROVIDE ( mUsbEPMap = 0x008e3c68 ); +PROVIDE ( usbFifoConf = 0x005009cc ); +PROVIDE ( u8UsbInterfaceValue = 0x005009f8 ); +PROVIDE ( u8UsbConfigValue = 0x005009f6 ); +PROVIDE ( u8UsbInterfaceAlternateSetting = 0x005009fa ); +PROVIDE ( ControlCmd = 0x005009c0 ); +PROVIDE ( vUsbFIFO_EPxCfg_HS = 0x008e3d5c ); +PROVIDE ( vUsbClrEPx = 0x008e2d00 ); +PROVIDE ( bSet_configuration = 0x008e2f7c ); +PROVIDE ( _HIFusb_isr_handler = 0x008e2b58 ); +PROVIDE ( bGet_descriptor = 0x008e2ec4 ); +PROVIDE ( u8ConfigDescriptorEX = 0x005009e8 ); +PROVIDE ( bStandardCommand = 0x008e328c ); diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/target.ram.ld b/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/target.ram.ld new file mode 100755 index 0000000..0b2d62e --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/target.ram.ld @@ -0,0 +1,264 @@ + +/* Linker script for Magpie RAM-based applications */ + +/* +Currently, ROM code reserves the first 8KB of RAM for its data/bss. +The next 12KB or RAM is used for RAM software's literals and read-only data. +After that comes 64KB reserved for RAM software's data and bss. +Then 92KB of RAM is reserved for text (code). +The last 8KB of RAM is reserved for ROM patches, customer DataSets, +and RAM software expansion. (There is also some additional RAM between +segments that can be used, if needed.) + ROM reserved: 0x00500000..0x00501fff + Literals: 0x00502000..0x00504fff + Data: 0x00505000..0x00514fff + Text: 0x00915000..0x0092bfff +TBD: May want to use a 2-pass link approach in order to +eliminate fixed boundaries. Support for physical addressing +in Tensilica tools would be helpful, but it's not coming +any time soon. +*/ + +/* dram_seg: 0x504000, see target.rom.ld */ + +/* ***** */ +MEMORY +{ + lit_seg : org = 0x004E5200, len = 0x1DE00 + iram_seg : org = 0x00903000, len = 0x9B40 + dram_seg : org = 0x0050CB40, len = 0x1800 + +} + +PHDRS +{ + lit_phdr PT_LOAD; + dram_phdr PT_LOAD; + iram_phdr PT_LOAD; +} + +/* Default entry point: */ +ENTRY(app_start) + +SECTIONS +{ + /* + * This empty section is used to convince RAM linkage + * to share litbase with ROM code. + */ + .lit4 (NOLOAD) : + { + _rom_literal_start = ABSOLUTE(.); + . += 0x1BE00; /* Reserved virtual space for physical mem gap and ROM */ + _lit4_start = ABSOLUTE(.); + _lit4_end = ABSOLUTE(.); + _rom_literal_end = ABSOLUTE(.); + } >lit_seg :NONE + + .dport0.rodata : + { + _dport0_rodata_start = ABSOLUTE(.); /* 0x505000 */ + *(.dport0.rodata) + *(.dport.rodata) + _dport0_rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dport0.literal : + { + _dport0_literal_start = ABSOLUTE(.); + *(.dport0.literal) + *(.dport.literal) + _dport0_literal_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dram0.rodata : + { + _dram0_rodata_start = ABSOLUTE(.); + *(.dram0.rodata) + *(.dram.rodata) + _dram0_rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .rodata : + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = ALIGN(4); /* this table MUST be 4-byte aligned */ + _bss_table_start = ABSOLUTE(.); + LONG(_dport0_bss_start) + LONG(_dport0_bss_end) + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .literals : + { + _literals_start = ABSOLUTE(.); + *(*.lit4) + *(.gnu.linkonce.lit4.*) + _literals_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dram0.literal : + { + _dram0_literal_start = ABSOLUTE(.); + *(.dram0.literal) + *(.dram.literal) + _dram0_literal_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dport0.data : + { + _dport0_data_start = ABSOLUTE(.); + *(.dport0.data) + *(.dport.data) + _dport0_data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .dport0.bss : + { + . = ALIGN (8); + _dport0_bss_start = ABSOLUTE(.); + *(.dport0.bss) + . = ALIGN (8); + _dport0_bss_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .dram0.data : + { + _dram0_data_start = ABSOLUTE(.); + *(.dram0.data) + *(.dram.data) + _dram0_data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .data : + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.eh_frame) + /* C++ constructor and destructor tables, properly ordered: */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .bss : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + *(.dram0.bss) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + _end = ALIGN(0x8); + PROVIDE(end = ALIGN(0x8)); + _fw_image_end = ABSOLUTE(.); + /*_stack_sentry = ALIGN(0x8);*/ + } >dram_seg :dram_phdr + + .text : + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.entry.text) + *(.init.literal) + *(.init) + *(.literal .text .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.fini.literal) + *(.fini) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + } >iram_seg :iram_phdr + + .iram0.text : + { + _iram0_text_start = ABSOLUTE(.); + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + _iram0_text_end = ABSOLUTE(.); + } >iram_seg :iram_phdr + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.gnu.linkonce.p.*)) + } +} + +INCLUDE "rom.addrs.ld" + diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/target.ram_debug.ld b/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/target.ram_debug.ld new file mode 100755 index 0000000..72b293f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/image/k2_ram/target.ram_debug.ld @@ -0,0 +1,264 @@ + +/* Linker script for Magpie RAM-based applications */ + +/* +Currently, ROM code reserves the first 8KB of RAM for its data/bss. +The next 12KB or RAM is used for RAM software's literals and read-only data. +After that comes 64KB reserved for RAM software's data and bss. +Then 92KB of RAM is reserved for text (code). +The last 8KB of RAM is reserved for ROM patches, customer DataSets, +and RAM software expansion. (There is also some additional RAM between +segments that can be used, if needed.) + ROM reserved: 0x00500000..0x00501fff + Literals: 0x00502000..0x00504fff + Data: 0x00505000..0x00514fff + Text: 0x00915000..0x0092bfff +TBD: May want to use a 2-pass link approach in order to +eliminate fixed boundaries. Support for physical addressing +in Tensilica tools would be helpful, but it's not coming +any time soon. +*/ + +/* dram_seg: 0x504000, see target.rom.ld */ + +/* ***** */ +MEMORY +{ + lit_seg : org = 0x004E5200, len = 0x1EE00 + iram_seg : org = 0x00904000, len = 0xA800 + dram_seg : org = 0x0050E800, len = 0x1800 + +} + +PHDRS +{ + lit_phdr PT_LOAD; + dram_phdr PT_LOAD; + iram_phdr PT_LOAD; +} + +/* Default entry point: */ +ENTRY(app_start) + +SECTIONS +{ + /* + * This empty section is used to convince RAM linkage + * to share litbase with ROM code. + */ + .lit4 (NOLOAD) : + { + _rom_literal_start = ABSOLUTE(.); + . += 0x1BE00; /* Reserved virtual space for physical mem gap and ROM */ + _lit4_start = ABSOLUTE(.); + _lit4_end = ABSOLUTE(.); + _rom_literal_end = ABSOLUTE(.); + } >lit_seg :NONE + + .dport0.rodata : + { + _dport0_rodata_start = ABSOLUTE(.); /* 0x505000 */ + *(.dport0.rodata) + *(.dport.rodata) + _dport0_rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dport0.literal : + { + _dport0_literal_start = ABSOLUTE(.); + *(.dport0.literal) + *(.dport.literal) + _dport0_literal_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dram0.rodata : + { + _dram0_rodata_start = ABSOLUTE(.); + *(.dram0.rodata) + *(.dram.rodata) + _dram0_rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .rodata : + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = ALIGN(4); /* this table MUST be 4-byte aligned */ + _bss_table_start = ABSOLUTE(.); + LONG(_dport0_bss_start) + LONG(_dport0_bss_end) + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .literals : + { + _literals_start = ABSOLUTE(.); + *(*.lit4) + *(.gnu.linkonce.lit4.*) + _literals_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dram0.literal : + { + _dram0_literal_start = ABSOLUTE(.); + *(.dram0.literal) + *(.dram.literal) + _dram0_literal_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dport0.data : + { + _dport0_data_start = ABSOLUTE(.); + *(.dport0.data) + *(.dport.data) + _dport0_data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .dport0.bss : + { + . = ALIGN (8); + _dport0_bss_start = ABSOLUTE(.); + *(.dport0.bss) + . = ALIGN (8); + _dport0_bss_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .dram0.data : + { + _dram0_data_start = ABSOLUTE(.); + *(.dram0.data) + *(.dram.data) + _dram0_data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .data : + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.eh_frame) + /* C++ constructor and destructor tables, properly ordered: */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .bss : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + *(.dram0.bss) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + _end = ALIGN(0x8); + PROVIDE(end = ALIGN(0x8)); + _fw_image_end = ABSOLUTE(.); + /*_stack_sentry = ALIGN(0x8);*/ + } >dram_seg :dram_phdr + + .text : + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.entry.text) + *(.init.literal) + *(.init) + *(.literal .text .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.fini.literal) + *(.fini) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + } >iram_seg :iram_phdr + + .iram0.text : + { + _iram0_text_start = ABSOLUTE(.); + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + _iram0_text_end = ABSOLUTE(.); + } >iram_seg :iram_phdr + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.gnu.linkonce.p.*)) + } +} + +INCLUDE "rom.addrs.ld" + diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/lib/ram/dummy.txt b/target_firmware/magpie_fw_dev/build/k2_1_0/lib/ram/dummy.txt new file mode 100755 index 0000000..e69de29 diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/adf/Makefile b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/adf/Makefile new file mode 100755 index 0000000..eee2bb6 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/adf/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = adf + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(LAYERNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +# export SSOBJPATH = $(PRJ_ROOT)/build/$(TARGET)/$(LAYERNAME)/obj + + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/obj + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . +#DIRS = net os nbuf + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libadf.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/adf/Makefile.ss b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/adf/Makefile.ss new file mode 100755 index 0000000..8611c2a --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/adf/Makefile.ss @@ -0,0 +1,48 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/adf_nbuf.o \ + $(SSOBJPATH)/adf_net.o \ + $(SSOBJPATH)/adf_os_defer_pvt.o \ + $(SSOBJPATH)/adf_os_dma.o \ + $(SSOBJPATH)/adf_os_irq_pvt.o \ + $(SSOBJPATH)/adf_os_timer.o + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/buf_pool/Makefile b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/buf_pool/Makefile new file mode 100755 index 0000000..2eeb0ba --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/buf_pool/Makefile @@ -0,0 +1,59 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export SSNAME = buf_pool + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libbuf_pool.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/buf_pool/Makefile.ss b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/buf_pool/Makefile.ss new file mode 100755 index 0000000..1fe76f9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/buf_pool/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/buf_pool_static.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/carrier_apd/Makefile b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/carrier_apd/Makefile new file mode 100755 index 0000000..d9b80f7 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/carrier_apd/Makefile @@ -0,0 +1,59 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = carrier_apd +export SLAYERNAME = ../wlan + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/$(SLAYERNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +# export SSOBJPATH = $(PRJ_ROOT)/build/$(TARGET)/$(LAYERNAME)/usb/obj + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SLAYERNAME)/$(SSNAME)/obj + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcarrier_apd.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/carrier_apd/Makefile.ss b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/carrier_apd/Makefile.ss new file mode 100755 index 0000000..bef6db9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/carrier_apd/Makefile.ss @@ -0,0 +1,53 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/ah.o \ + $(SSOBJPATH)/ar5416_hw.o \ + $(SSOBJPATH)/ar5416_phy.o \ + $(SSOBJPATH)/ah_osdep.o \ + $(SSOBJPATH)/if_ath.o \ + $(SSOBJPATH)/if_ath_pci.o \ + $(SSOBJPATH)/if_owl.o \ + $(SSOBJPATH)/ieee80211_output.o \ + $(SSOBJPATH)/ar5416Phy.o \ + $(SSOBJPATH)/ratectrl_11n_ln.o + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/cmnos/Makefile b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/cmnos/Makefile new file mode 100755 index 0000000..5fbf26b --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/cmnos/Makefile @@ -0,0 +1,57 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = cmnos + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(LAYERNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +# export SSOBJPATH = $(PRJ_ROOT)/build/$(TARGET)/$(LAYERNAME)/obj +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/obj + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . +#DIRS = dbg printf sflash clock + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/cmnos/Makefile.ss b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/cmnos/Makefile.ss new file mode 100755 index 0000000..74f66c2 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/cmnos/Makefile.ss @@ -0,0 +1,48 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/k2_cmnos_clock_patch.o \ + $(SSOBJPATH)/dbg_api.o \ + $(SSOBJPATH)/k2_fw_cmnos_printf.o \ + $(SSOBJPATH)/cmnos_sflash.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/hif/Makefile b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/hif/Makefile new file mode 100755 index 0000000..52c578f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/hif/Makefile @@ -0,0 +1,59 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = hif + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(LAYERNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +# export SSOBJPATH = $(PRJ_ROOT)/build/$(TARGET)/$(LAYERNAME)/obj +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/obj + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +#DIRS = usb +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libhif.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/hif/Makefile.ss b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/hif/Makefile.ss new file mode 100755 index 0000000..2a17993 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/hif/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/k2_fw_usb_api.o \ + $(SSOBJPATH)/k2_HIF_usb_patch.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/htc/Makefile b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/htc/Makefile new file mode 100755 index 0000000..d1159ac --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/htc/Makefile @@ -0,0 +1,60 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export SSNAME = htc + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libhtc.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/htc/Makefile.ss b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/htc/Makefile.ss new file mode 100755 index 0000000..ae26c92 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/htc/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/htc.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/init/Makefile b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/init/Makefile new file mode 100755 index 0000000..81da922 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/init/Makefile @@ -0,0 +1,60 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = ram +export SSNAME = init + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libinit.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/init/Makefile.ss b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/init/Makefile.ss new file mode 100755 index 0000000..642be84 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/init/Makefile.ss @@ -0,0 +1,46 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/app_start.o \ + $(SSOBJPATH)/init.o \ + $(SSOBJPATH)/magpie.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wlan/Makefile b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wlan/Makefile new file mode 100755 index 0000000..c05e4e9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wlan/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = ram +export SSNAME = wlan + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libwlan.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wlan/Makefile.ss b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wlan/Makefile.ss new file mode 100755 index 0000000..aab1446 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wlan/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/wlan_pci.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wmi/Makefile b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wmi/Makefile new file mode 100755 index 0000000..6a3704f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wmi/Makefile @@ -0,0 +1,59 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export SSNAME = wmi + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libwmi.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wmi/Makefile.ss b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wmi/Makefile.ss new file mode 100755 index 0000000..dd4a587 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/k2_1_0/ram/wmi/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/wmi_svc.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/Makefile new file mode 100755 index 0000000..6193b99 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/Makefile @@ -0,0 +1,83 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + +ifeq ($(TGT_BUILD),) + TGT_BUILD=asic +endif + +DIRS = \ + $(PRJ_ROOT)/$(TARGET)/adf \ + $(PRJ_ROOT)/$(TARGET)/init \ + $(PRJ_ROOT)/$(TARGET)/wmi \ + $(PRJ_ROOT)/$(TARGET)/wlan \ + $(PRJ_ROOT)/$(TARGET)/carrier_apd \ + $(PRJ_ROOT)/$(TARGET)/cmnos \ + $(PRJ_ROOT)/$(TARGET)/rompatch + +COMPONENTS_sw.ram = \ + $(LIB_PATH)/libcmnos.a \ + $(LIB_PATH)/libadf.a \ + $(LIB_PATH)/libwmi.a \ + $(LIB_PATH)/libwlan.a \ + $(LIB_PATH)/libcarrier_apd.a \ + $(LIB_PATH)/librompatch.a + + +LINKFLAGS_sw.ram = \ + -T./target.ram.ld \ + --start-group \ + $(COMPONENTS_sw.ram) \ + --end-group + +FW_LOAD_ADDR=`$(XREADELF) -l ram.out | grep LOAD | awk '/LOAD/ { if (NR==1) print $$3 }'` +FW_EXEC_ADDR=`$(XREADELF) -l ram.out | grep 'Entry point' | awk '{ print $$3 }'` + +all: util toolchain_prep + @for i in $(DIRS) ; do $(MAKE) -C $$i all CC=$(XCC) LD=$(XLD) AR=$(XAR) || exit ; done + +dep: util toolchain_prep + for i in $(DIRS) ; do $(MAKE) -C $$i dep CC=$(XCC) LD=$(XLD) AR=$(XAR) || exit ; done + +clean: util_clean + find $(PRJ_ROOT)/ram -name "*.o" -exec rm -f {} \; + find $(PRJ_ROOT)/lib -name "*.a" -exec rm -f {} \; +# for i in $(DIRS) ; do $(MAKE) -C $$i clean; done + rm -f *.bin *.objdump *.out *.map *.c rom.addrs.ld *.fw *.fw.back *.c.back + rm -f ../../../utility/athfw2lnx/athfw2lnx + +init: toolchain_prep + for i in $(DIRS) ; do $(MAKE) -C $$i init CC=$(XCC) LD=$(XLD) AR=$(XAR) ; done + +build: binary image + +binary: + if [ -d $(OUTPUT_DIR)/$(TGT_BUILD) ]; \ + then cp -vf $(OUTPUT_DIR)/$(TGT_BUILD)/rom.$(TGT_BUILD).addrs.ld rom.addrs.ld; \ + fi + + $(XLD) $(PRJ_ROOT)/ram/init/obj/app_start.o $(PRJ_ROOT)/ram/init/obj/init.o $(PRJ_ROOT)/ram/init/obj/magpie.o $(LINKFLAGS_sw.ram) -Map $(PRJNAME).map -o $(PRJNAME).out + +toolchain_prep: +ifeq ($(XTENSA_TOOL_INSTALLED),0) + @cd ../../../toolchain && \ + (test -d tools) || tar xvzf toolchain.tgz + +endif + +image: + $(XOBJCOPY) \ + --change-section-lma .text-0x400000 \ + --change-section-vma .text-0x400000 \ + -O binary $(PRJNAME).out $(PRJNAME).bin + $(XOBJDUMP) -Dlxs $(PRJNAME).out > $(PRJNAME).objdump + rm -f ../../../utility/athfw2lnx/athfw2lnx + $(shell cp -f fwu.c fwu.c.back 2> /dev/null) + $(shell cp -f htc_7010.fw htc_7010.fw.back 2> /dev/null) + $(BIN2HEX) $(PRJNAME).bin fwu.c 0 usb + $(MAKE) -C ../../../utility/athfw2lnx ATH_FW=$(PRJ_ROOT)/image/magpie_ram/fwu.c + $(shell ../../../utility/athfw2lnx/athfw2lnx > htc_7010.fw) + +util: + @cd ../../../utility && $(MAKE) all + +util_clean: + @cd ../../../utility && $(MAKE) clean diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/merlin_fusion.ram b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/merlin_fusion.ram new file mode 100755 index 0000000..07bde75 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/merlin_fusion.ram @@ -0,0 +1,39 @@ +#!/bin/bash + +MAGPIE_ROOT=`pwd`/../../../../;export MAGPIE_ROOT +PROJECT=magpie; export PROJECT +TARGET=ram; export TARGET + +PRJ_ROOT=$MAGPIE_ROOT/build/magpie_1_1; export PRJ_ROOT +PRJNAME=ram; export PRJNAME +PRJPATH=$PRJ_ROOT/$PRJNAME; export PRJPATH +PRJ_HPATH=$PRJPATH/inc; export PRJ_HPATH +OUTPUT_DIR=$PRJ_ROOT/image/output; export OUTPUT_DIR + +XTENSA_TOOLS_INC=$XTENSA_TOOLS_ROOT/xtensa-elf/include + +HPATH=" -I$XTENSA_TOOLS_INC \ + -I$PRJ_ROOT/inc \ + -I$PRJ_ROOT/inc/$PROJECT \ + -I$MAGPIE_ROOT/../wlan/include \ + -I$MAGPIE_ROOT/../wlan/include/magpie \ + -I$MAGPIE_ROOT/../wlan/ \ + -I$MAGPIE_ROOT/target/cmnos/ \ + -I$MAGPIE_ROOT/target/wmi/ \ + -I$MAGPIE_ROOT/target/wlan/ \ + -I$MAGPIE_ROOT/target/inc \ + -I$MAGPIE_ROOT/target/inc/OTUS \ + -I$MAGPIE_ROOT/target/adf/ \ + -I$MAGPIE_ROOT/build/include"; + +export HPATH + +LIB_PATH=$PRJ_ROOT/lib/ram; export LIB_PATH +CROSS_COMPILE=$XTENSA_TOOLS_ROOT/bin; export CROSS_COMPILE +TARGET_PREFIX=xt-; export TARGET_PREFIX + +ARCH=""; export ARCH +DEFS=""; export DEFS +CCOPTS=" -g -Os -Wunused-label -Wunused-variable -Wunused-value -Wpointer-arith -Wundef -nostdlib -Wundef"; export CCOPTS +ASOPTS="-Wa, --fatal-warnings"; export ASOPTS +DFLAGS="-DROM_VER_1_1 -D_ROM_1_1_ -D_RAM_ -DPROJECT_MAGPIE -DBIG_ENDIAN -D_BYTE_ORDER=_BIG_ENDIAN -DATH_STATS_ENABLE -D__XTENSA__ -DFUSION_USB_FW -DMAGPIE_MERLIN -DRX_SCATTER -DFUSION_USB_ENABLE_TX_STREAM -DFUSION_USB_ENABLE_RX_STREAM -DATH_ENABLE_CABQ"; export DFLAGS diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/target.ram.ld b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/target.ram.ld new file mode 100755 index 0000000..0da8315 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/target.ram.ld @@ -0,0 +1,264 @@ + +/* Linker script for Magpie RAM-based applications */ + +/* +Currently, ROM code reserves the first 8KB of RAM for its data/bss. +The next 12KB or RAM is used for RAM software's literals and read-only data. +After that comes 64KB reserved for RAM software's data and bss. +Then 92KB of RAM is reserved for text (code). +The last 8KB of RAM is reserved for ROM patches, customer DataSets, +and RAM software expansion. (There is also some additional RAM between +segments that can be used, if needed.) + ROM reserved: 0x00500000..0x00501fff + Literals: 0x00502000..0x00504fff + Data: 0x00505000..0x00514fff + Text: 0x00915000..0x0092bfff +TBD: May want to use a 2-pass link approach in order to +eliminate fixed boundaries. Support for physical addressing +in Tensilica tools would be helpful, but it's not coming +any time soon. +*/ + +/* dram_seg: 0x504000, see target.rom.ld */ + +/* ***** */ +MEMORY +{ + lit_seg : org = 0x004E8000, len = 0x1f600 + iram_seg : org = 0x00906000, len = 0xad00 + dram_seg : org = 0x00510d00, len = 0x6000 + +} + +PHDRS +{ + lit_phdr PT_LOAD; + dram_phdr PT_LOAD; + iram_phdr PT_LOAD; +} + +/* Default entry point: */ +ENTRY(app_start) + +SECTIONS +{ + /* + * This empty section is used to convince RAM linkage + * to share litbase with ROM code. + */ + .lit4 (NOLOAD) : + { + _rom_literal_start = ABSOLUTE(.); + . += 0x19000; /* Reserved virtual space for physical mem gap and ROM */ + _lit4_start = ABSOLUTE(.); + _lit4_end = ABSOLUTE(.); + _rom_literal_end = ABSOLUTE(.); + } >lit_seg :NONE + + .dport0.rodata : + { + _dport0_rodata_start = ABSOLUTE(.); /* 0x505000 */ + *(.dport0.rodata) + *(.dport.rodata) + _dport0_rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dport0.literal : + { + _dport0_literal_start = ABSOLUTE(.); + *(.dport0.literal) + *(.dport.literal) + _dport0_literal_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dram0.rodata : + { + _dram0_rodata_start = ABSOLUTE(.); + *(.dram0.rodata) + *(.dram.rodata) + _dram0_rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .rodata : + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = ALIGN(4); /* this table MUST be 4-byte aligned */ + _bss_table_start = ABSOLUTE(.); + LONG(_dport0_bss_start) + LONG(_dport0_bss_end) + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .literals : + { + _literals_start = ABSOLUTE(.); + *(*.lit4) + *(.gnu.linkonce.lit4.*) + _literals_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dram0.literal : + { + _dram0_literal_start = ABSOLUTE(.); + *(.dram0.literal) + *(.dram.literal) + _dram0_literal_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dport0.data : + { + _dport0_data_start = ABSOLUTE(.); + *(.dport0.data) + *(.dport.data) + _dport0_data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .dport0.bss : + { + . = ALIGN (8); + _dport0_bss_start = ABSOLUTE(.); + *(.dport0.bss) + . = ALIGN (8); + _dport0_bss_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .dram0.data : + { + _dram0_data_start = ABSOLUTE(.); + *(.dram0.data) + *(.dram.data) + _dram0_data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .data : + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.eh_frame) + /* C++ constructor and destructor tables, properly ordered: */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .bss : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + *(.dram0.bss) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + _end = ALIGN(0x8); + PROVIDE(end = ALIGN(0x8)); + _fw_image_end = ABSOLUTE(.); + /*_stack_sentry = ALIGN(0x8);*/ + } >dram_seg :dram_phdr + + .text : + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.entry.text) + *(.init.literal) + *(.init) + *(.literal .text .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.fini.literal) + *(.fini) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + } >iram_seg :iram_phdr + + .iram0.text : + { + _iram0_text_start = ABSOLUTE(.); + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + _iram0_text_end = ABSOLUTE(.); + } >iram_seg :iram_phdr + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.gnu.linkonce.p.*)) + } +} + +INCLUDE "rom.addrs.ld" + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/target_gmac.ram.ld b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/target_gmac.ram.ld new file mode 100755 index 0000000..43a5d97 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/magpie_ram/target_gmac.ram.ld @@ -0,0 +1,267 @@ + +/* Linker script for Magpie RAM-based applications */ + +/* +Currently, ROM code reserves the first 8KB of RAM for its data/bss. +The next 12KB or RAM is used for RAM software's literals and read-only data. +After that comes 64KB reserved for RAM software's data and bss. +Then 92KB of RAM is reserved for text (code). +The last 8KB of RAM is reserved for ROM patches, customer DataSets, +and RAM software expansion. (There is also some additional RAM between +segments that can be used, if needed.) + ROM reserved: 0x00500000..0x00501fff + Literals: 0x00502000..0x00504fff + Data: 0x00505000..0x00514fff + Text: 0x00915000..0x0092bfff +TBD: May want to use a 2-pass link approach in order to +eliminate fixed boundaries. Support for physical addressing +in Tensilica tools would be helpful, but it's not coming +any time soon. +*/ + +/* dram_seg: 0x504000, see target.rom.ld */ + +/* ***** */ + /*lit_seg : org = 0x00508000, len = 0x9000 + iram_seg : org = 0x00911000, len = 0xb000 + dram_seg : org = 0x0051c000, len = 0x6000 */ +MEMORY +{ + lit_seg : org = 0x004E8000, len = 0x1E600 + iram_seg : org = 0x00906600, len = 0x9500 + dram_seg : org = 0x0050FB00, len = 0x6000 + +} + +PHDRS +{ + lit_phdr PT_LOAD; + dram_phdr PT_LOAD; + iram_phdr PT_LOAD; +} + +/* Default entry point: */ +ENTRY(app_start) + +SECTIONS +{ + /* + * This empty section is used to convince RAM linkage + * to share litbase with ROM code. + */ + .lit4 (NOLOAD) : + { + _rom_literal_start = ABSOLUTE(.); + . += 0x1a600; /* Reserved virtual space for physical mem gap and ROM */ + _lit4_start = ABSOLUTE(.); + _lit4_end = ABSOLUTE(.); + _rom_literal_end = ABSOLUTE(.); + } >lit_seg :NONE + + .dport0.rodata : + { + _dport0_rodata_start = ABSOLUTE(.); /* 0x505000 */ + *(.dport0.rodata) + *(.dport.rodata) + _dport0_rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dport0.literal : + { + _dport0_literal_start = ABSOLUTE(.); + *(.dport0.literal) + *(.dport.literal) + _dport0_literal_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dram0.rodata : + { + _dram0_rodata_start = ABSOLUTE(.); + *(.dram0.rodata) + *(.dram.rodata) + _dram0_rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .rodata : + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = ALIGN(4); /* this table MUST be 4-byte aligned */ + _bss_table_start = ABSOLUTE(.); + LONG(_dport0_bss_start) + LONG(_dport0_bss_end) + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .literals : + { + _literals_start = ABSOLUTE(.); + *(*.lit4) + *(.gnu.linkonce.lit4.*) + _literals_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dram0.literal : + { + _dram0_literal_start = ABSOLUTE(.); + *(.dram0.literal) + *(.dram.literal) + _dram0_literal_end = ABSOLUTE(.); + } >lit_seg :lit_phdr + + .dport0.data : + { + _dport0_data_start = ABSOLUTE(.); + *(.dport0.data) + *(.dport.data) + _dport0_data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .dport0.bss : + { + . = ALIGN (8); + _dport0_bss_start = ABSOLUTE(.); + *(.dport0.bss) + . = ALIGN (8); + _dport0_bss_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .dram0.data : + { + _dram0_data_start = ABSOLUTE(.); + *(.dram0.data) + *(.dram.data) + _dram0_data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .data : + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.eh_frame) + /* C++ constructor and destructor tables, properly ordered: */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _data_end = ABSOLUTE(.); + } >dram_seg :dram_phdr + + .bss : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + *(.dram0.bss) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + _end = ALIGN(0x8); + PROVIDE(end = ALIGN(0x8)); + _fw_image_end = ABSOLUTE(.); + /*_stack_sentry = ALIGN(0x8);*/ + } >dram_seg :dram_phdr + + .text : + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.entry.text) + *(.init.literal) + *(.init) + *(.literal .text .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.fini.literal) + *(.fini) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + } >iram_seg :iram_phdr + + .iram0.text : + { + _iram0_text_start = ABSOLUTE(.); + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + _iram0_text_end = ABSOLUTE(.); + } >iram_seg :iram_phdr + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.gnu.linkonce.p.*)) + } +} + +INCLUDE "rom.addrs.ld" + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/image/output/asic/rom.asic.addrs.ld b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/output/asic/rom.asic.addrs.ld new file mode 100755 index 0000000..a54a98e --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/output/asic/rom.asic.addrs.ld @@ -0,0 +1,74 @@ +PROVIDE ( _indir_tbl = 0x00500000 ); +PROVIDE ( memcpy = 0x008e6b64 ); +PROVIDE ( memset = 0x008e6e48 ); +PROVIDE ( __divsi3 = 0x008e6998 ); +PROVIDE ( __udivsi3 = 0x008e6a4c ); +PROVIDE ( __umodsi3 = 0x008e6a9c ); +PROVIDE ( __modsi3 = 0x008e6a00 ); +PROVIDE ( athos_interrupt_init = 0x008e1614 ); +PROVIDE ( athos_unblock_all_intrlvl = 0x008e1460 ); +PROVIDE ( athos_interrupt_handler = 0x008e1604 ); +PROVIDE ( _xtos_set_interrupt_handler = 0x008e1230 ); +PROVIDE ( generic_hif_module_install = 0x008e1548 ); +PROVIDE ( htc_module_install = 0x008e54a8 ); +PROVIDE ( buf_pool_module_install = 0x008e6264 ); +PROVIDE ( vbuf_module_install = 0x008e4f60 ); +PROVIDE ( vdesc_module_install = 0x008e5010 ); +PROVIDE ( strcmp = 0x008e6560 ); +PROVIDE ( strlen = 0x008e6710 ); +PROVIDE ( strcpy = 0x008e6678 ); +PROVIDE ( strncpy = 0x008e683c ); +PROVIDE ( Xthal_num_ccompare = 0x004e87f9 ); +PROVIDE ( cticks = 0x0050095c ); +PROVIDE ( UsbDeviceDescriptor = 0x004e0100 ); +PROVIDE ( String00Descriptor = 0x004e01a0 ); +PROVIDE ( String10Descriptor = 0x004e01b0 ); +PROVIDE ( String20Descriptor = 0x004e01c0 ); +PROVIDE ( String30Descriptor = 0x004e01e0 ); +PROVIDE ( HIFusb_DescTraceDump = 0x008e37e8 ); +PROVIDE ( xthal_get_intenable = 0x008e6980 ); +PROVIDE ( xthal_set_intenable = 0x008e6990 ); +PROVIDE ( xthal_get_interrupt = 0x008e6988 ); +PROVIDE ( xthal_get_ccompare = 0x008e6970 ); +PROVIDE ( xthal_set_ccompare = 0x008e6960 ); +PROVIDE ( xthal_get_ccount = 0x008e6958 ); +PROVIDE ( Xthal_num_ccompare = 0x004e87f9 ); +PROVIDE ( zfDmaReclaimPacket = 0x008e5d2c ); +PROVIDE ( zfDmaPutPacket = 0x008e5dc0 ); +PROVIDE ( zfDmaGetPacket = 0x008e5cf0 ); +PROVIDE ( fwd_init = 0x008e5e78 ); +PROVIDE ( usbFifoConf = 0x00500aa4 ); +PROVIDE ( _HIFusb_isr_handler = 0x008e36e4 ); +PROVIDE ( mUsbFIFOConfig = 0x008e4934 ); +PROVIDE ( mUsbEPMxPtSzHigh = 0x008e4954 ); +PROVIDE ( mUsbEPMxPtSzLow = 0x008e497c ); +PROVIDE ( mUsbEPinHighBandSet = 0x008e49a0 ); +PROVIDE ( mUsbFIFOConfig = 0x008e4934 ); +PROVIDE ( mUsbFIFOMap = 0x008e4914 ); +PROVIDE ( mUsbEPMap = 0x008e48f8 ); +PROVIDE ( u8UsbInterfaceValue = 0x00500ad0 ); +PROVIDE ( u8UsbConfigValue = 0x00500ace ); +PROVIDE ( u8UsbInterfaceAlternateSetting = 0x00500ad2 ); +PROVIDE ( ControlCmd = 0x00500a98 ); +PROVIDE ( vUsbFIFO_EPxCfg_HS = 0x008e49ec ); +PROVIDE ( vUsbClrEPx = 0x008e38d0 ); +PROVIDE ( bSet_configuration = 0x008e3b54 ); +PROVIDE ( eUsbCxFinishAction = 0x00500ac4 ); +PROVIDE ( pci_sc = 0x00500708 ); +PROVIDE ( __pci_reap_recv = 0x008e31e8 ); +PROVIDE ( __pci_reap_xmitted = 0x008e31bc ); +PROVIDE ( _HIFusb_start = 0x008e34a0 ); +PROVIDE ( g_hifUSBCtx = 0x00500a54 ); +PROVIDE ( _HIFusb_return_recv_buf = 0x008e367c ); +PROVIDE ( athos_indirection_table_install = 0x008e1574 ); +PROVIDE ( u8ConfigDescriptorEX = 0x00500ac0 ); +PROVIDE ( bStandardCommand = 0x008e3e64 ); +PROVIDE ( u16TxRxCounter = 0x00500abc ); +PROVIDE ( pu8DescriptorEX = 0x00500ab8 ); +PROVIDE ( bGet_descriptor = 0x008e3a9c ); +PROVIDE ( _xtos_set_exception_handler = 0x008e6348 ); +PROVIDE (HTCMsgRecvHandler = 0x008e581c); +PROVIDE (HTCControlSvcProcessMsg = 0x008e56f4); +PROVIDE (HTCFreeMsgBuffer = 0x008e54ec); +PROVIDE ( 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/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) (xthal_get_interrupt) +/opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(int_asm--set_intenable.o) + /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) (xthal_set_intenable) +/opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(interrupts--intlevel.o) + /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-sethandler.o) (Xthal_intlevel) +/opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib/xcc//libgcc.a(_divsi3.o) + (__divsi3) +/opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib/xcc//libgcc.a(_modsi3.o) + (__modsi3) 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+/opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strcmp.o) + (strcmp) +/opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strcpy.o) + (strcpy) +/opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strlen.o) + (strlen) +/opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strncmp.o) + /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_string.o) (strncmp) +/opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strncpy.o) + /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_string.o) (strncpy) + +Memory Configuration + +Name Origin Length Attributes +ResetVector_text_seg 0x008e0000 0x00000800 +WindowVectors_text_seg 0x008e0800 0x00000200 +Level2InterruptVector_lit_seg 0x008e0a00 0x00000020 +Level2InterruptVector_text_seg 0x008e0a20 0x000000e0 +Level3InterruptVector_lit_seg 0x008e0b00 0x00000020 +Level3InterruptVector_text_seg 0x008e0b20 0x000000e0 +DebugExceptionVector_lit_seg 0x008e0c00 0x00000020 +DebugExceptionVector_text_seg 0x008e0c20 0x000000e0 +NMIExceptionVector_lit_seg 0x008e0ce0 0x00000004 +NMIExceptionVector_text_seg 0x008e0ce4 0x0000001c +KernelExceptionVector_lit_seg 0x008e0d00 0x00000040 +KernelExceptionVector_text_seg 0x008e0d40 0x000000c0 +UserExceptionVector_lit_seg 0x008e0e00 0x00000020 +UserExceptionVector_text_seg 0x008e0e20 0x000000e0 +DoubleExceptionVector_lit_seg 0x008e0f00 0x00000020 +DoubleExceptionVector_text_seg 0x008e0f20 0x000000e0 +irom_seg 0x008e1000 0x00007000 +drom_seg 0x004e8000 0x00001800 +dram_seg 0x00500000 0x00001000 +dram1_seg 0x0053f7f0 0x00000800 +dram2_seg 0x004e0100 0x00000400 +*default* 0x00000000 0xffffffff + +Linker script and memory map + + 0x008e0800 PROVIDE (_memmap_vecbase_reset, 0x8e0800) + 0x00021001 _memmap_cacheattr_wb_base = 0x21001 + 0x00021001 _memmap_cacheattr_wt_base = 0x21001 + 0x00022002 _memmap_cacheattr_bp_base = 0x22002 + 0xfff00ff0 _memmap_cacheattr_unused_mask = 0xfff00ff0 + 0x22221221 _memmap_cacheattr_wb_trapnull = 0x22221221 + 0x22221221 _memmap_cacheattr_wt_trapnull = 0x22221221 + 0x22222222 _memmap_cacheattr_bp_trapnull = 0x22222222 + 0xfff21ff1 _memmap_cacheattr_wb_strict = 0xfff21ff1 + 0xfff21ff1 _memmap_cacheattr_wt_strict = 0xfff21ff1 + 0xfff22ff2 _memmap_cacheattr_bp_strict = 0xfff22ff2 + 0x22221221 _memmap_cacheattr_wb_allvalid = 0x22221221 + 0x22221221 _memmap_cacheattr_wt_allvalid = 0x22221221 + 0x22222222 _memmap_cacheattr_bp_allvalid = 0x22222222 + 0x22221221 PROVIDE (_memmap_cacheattr_reset, _memmap_cacheattr_wb_trapnull) + +.lit4 0x004e8000 0x718 + 0x004e8000 _lit4_start = (.) + *(*.lit4) + .lit4 0x004e8000 0x10 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/crt1-tiny.o + .ResetVector.lit4 + 0x004e8010 0x8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(reset-vector-unpack.o) + .UserExceptionVector.lit4 + 0x004e8018 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(user-vector.o) + .lit4 0x004e801c 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-alloca-handler.o) + .lit4 0x004e8020 0x8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-syscall-handler.o) + .lit4 0x004e8028 0xc /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-lowpri-dispatcher.o) + .lit4 0x004e8034 0xc /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-sethandler.o) + .lit4 0x004e8040 0x8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-handler-level2.o) + .lit4 0x004e8048 0x8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-handler-level3.o) + .lit4 0x004e8050 0x110 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + .lit4 0x004e8160 0x1c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_allocram.o) + .lit4 0x004e817c 0x38 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_clock.o) + .lit4 0x004e81b4 0x54 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_eeprom.o) + .lit4 0x004e8208 0x2c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_intr.o) + .lit4 0x004e8234 0x14 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_mem.o) + .lit4 0x004e8248 0x50 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_misc.o) + .lit4 0x004e8298 0x1c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_printf.o) + .lit4 0x004e82b4 0x34 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_rompatch.o) + .lit4 0x004e82e8 0x18 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_string.o) + .lit4 0x004e8300 0x18 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_tasklet.o) + .lit4 0x004e8318 0x1c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_timer.o) + .lit4 0x004e8334 0x2c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_wdt.o) + .lit4 0x004e8360 0x34 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(uart_api.o) + .lit4 0x004e8394 0x7c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(hif_pci.o) + .lit4 0x004e8410 0x88 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(HIF_usb.o) + .lit4 0x004e8498 0xfc /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_api.o) + .lit4 0x004e8594 0xc /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_fifo.o) + .lit4 0x004e85a0 0x34 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(dma_lib.o) + .lit4 0x004e85d4 0x10 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvbuf.a(vbuf.o) + .lit4 0x004e85e4 0x14 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvdesc.a(vdesc.o) + .lit4 0x004e85f8 0x30 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhtc.a(htc.o) + .lit4 0x004e8628 0x50 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libdma.a(dma_engine.o) + .lit4 0x004e8678 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libdma.a(desc.o) + .lit4 0x004e867c 0x54 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libfwd.a(fwd.o) + .lit4 0x004e86d0 0x1c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libbuf_pool.a(buf_pool_static.o) + .lit4 0x004e86ec 0x10 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-sethandler.o) + .lit4 0x004e86fc 0x4 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(windowspill_asm.o) + .lit4 0x004e8700 0x10 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strcmp.o) + .lit4 0x004e8710 0x8 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strncmp.o) + *(.gnu.linkonce.lit4.*) + 0x004e8718 _lit4_end = (.) + +.ResetVector.literal + 0x004e8718 0x0 + 0x004e8718 _ResetVector_literal_start = (.) + *(.ResetVector.literal) + 0x004e8718 _ResetVector_literal_end = (.) + +.dport0.stack 0x0053f7f0 0x800 + 0x0053f7f0 _reserved_stack_start = . + 0x0053f7f0 _stack_sentry = ALIGN (0x8) + 0x0053fff0 . = (. + 0x800) + *fill* 0x0053f7f0 0x800 00 + *fill* 0x0053fff0 0x0 00 + *fill* 0x0053fff0 0x0 00 + *fill* 0x0053fff0 0x0 00 + *fill* 0x0053fff0 0x0 00 + 0x0053fff0 __stack = . + 0x0053fff0 _reserved_stack_end = . + +.dport0.usb_in_rom + 0x004e0100 0xec + 0x004e0100 _reserved_rom_data_start = . + 0x004e0100 _reserved_rom_data_end = . + 0x004e0260 _data_start_in_rom = 0x160 + .dport0.usb_in_rom + 0x004e0100 0xec /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_table.o) + 0x004e0100 UsbDeviceDescriptor + 0x004e01c0 String20Descriptor + 0x004e01b0 String10Descriptor + 0x004e0120 u8HSConfigDescriptor01 + 0x004e0160 u8FSConfigDescriptor01 + 0x004e01a0 String00Descriptor + 0x004e01e0 String30Descriptor + +.dport0.data 0x00500000 0x400 + 0x00500000 _reserved_data_start = 0x0 + 0x00500000 _indir_tbl = 0x0 + 0x00500400 . = 0x400 + *fill* 0x00500000 0x400 00 + *fill* 0x00500400 0x0 00 + *fill* 0x00500400 0x0 00 + *fill* 0x00500400 0x0 00 + *fill* 0x00500400 0x0 00 + 0x00500400 _reserved_data_end = . + 0x00500400 _dport0_data_start = (.) + *(.dport0.data) + *(.dport.data) + 0x00500400 _dport0_data_end = (.) + +.dport0.bss 0x00500400 0x0 + 0x00500400 . = ALIGN (0x8) + 0x00500400 _dport0_bss_start = (.) + *(.dport0.bss) + 0x00500400 . = ALIGN (0x8) + 0x00500400 _dport0_bss_end = (.) + +.dram0.rodata 0x004e8718 0x0 + 0x004e8718 _dram0_rodata_start = (.) + *(.dram0.rodata) + *(.dram.rodata) + 0x004e8718 _dram0_rodata_end = (.) + +.rodata 0x004e8720 0x934 + 0x004e8720 _rodata_start = (.) + *(.rodata) + .rodata 0x004e8720 0x30 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + 0x004e8720 _rom_store_table + .rodata 0x004e8750 0x50 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_clock.o) + 0x004e8750 cmnos_clocking_table + .rodata 0x004e87a0 0x98 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(misc.o) + 0x004e87b4 Xthal_have_loops + 0x004e87e6 Xthal_have_mimic_cacheattr + 0x004e87e8 Xthal_mmu_rings + 0x004e87b3 Xthal_have_density + 0x004e87a8 Xthal_rev_no + 0x004e87b1 Xthal_memory_order + 0x004e8834 Xthal_xlmi_size + 0x004e87bc Xthal_have_highlevel_interrupts + 0x004e87dc Xthal_hw_min_version_major + 0x004e87b9 Xthal_have_exceptions + 0x004e87d4 Xthal_hw_release_major + 0x004e87fc Xthal_instrom_vaddr + 0x004e8804 Xthal_instrom_size + 0x004e8830 Xthal_xlmi_paddr + 0x004e87e9 Xthal_mmu_ca_bits + 0x004e87e7 Xthal_have_tlbs + 0x004e8800 Xthal_instrom_paddr + 0x004e87b2 Xthal_have_windowed + 0x004e87f9 Xthal_num_ccompare + 0x004e87b0 Xthal_num_aregs_log2 + 0x004e8828 Xthal_dataram_size + 0x004e8824 Xthal_dataram_paddr + 0x004e87a0 Xthal_release_major + 0x004e8820 Xthal_dataram_vaddr + 0x004e87e0 Xthal_hw_max_version_major + 0x004e87f6 Xthal_num_instram + 0x004e87f5 Xthal_dtlb_ways + 0x004e87e4 Xthal_have_spanning_way + 0x004e881c Xthal_datarom_size + 0x004e87b8 Xthal_have_mul16 + 0x004e87c0 Xthal_have_s32c1i + 0x004e87f4 Xthal_itlb_ways + 0x004e87d0 Xthal_hw_configid1 + 0x004e87bb Xthal_have_interrupts + 0x004e87bf Xthal_have_release_sync + 0x004e87d8 Xthal_hw_release_name + 0x004e880c Xthal_instram_paddr + 0x004e87c2 Xthal_have_pif + 0x004e87b6 Xthal_have_minmax + 0x004e87ac Xthal_num_aregs + 0x004e87bd Xthal_have_nmi + 0x004e87c8 Xthal_build_unique_id + 0x004e8814 Xthal_datarom_vaddr + 0x004e8818 Xthal_datarom_paddr + 0x004e87e5 Xthal_have_identity_map + 0x004e87ba Xthal_xea_version + 0x004e87ec Xthal_mmu_max_pte_page_size + 0x004e87be Xthal_have_prid + 0x004e87f0 Xthal_mmu_min_pte_page_size + 0x004e8810 Xthal_instram_size + 0x004e882c Xthal_xlmi_vaddr + 0x004e87b5 Xthal_have_nsa + 0x004e87f8 Xthal_have_ccount + 0x004e87cc Xthal_hw_configid0 + 0x004e87c4 Xthal_num_writebuffer_entries + 0x004e87a4 Xthal_release_name + 0x004e8808 Xthal_instram_vaddr + 0x004e87f7 Xthal_num_dataram + 0x004e87c1 Xthal_have_threadptr + 0x004e87b7 Xthal_have_sext + *fill* 0x004e8838 0x8 00 + .rodata 0x004e8840 0x20 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(interrupts--intlevel.o) + 0x004e8840 Xthal_intlevel + *(.rodata.*) + .rodata.str1.4 + 0x004e8860 0x22a /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + *fill* 0x004e8a8a 0x2 00 + .rodata.str1.4 + 0x004e8a8c 0x5d /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_allocram.o) + *fill* 0x004e8ae9 0x3 00 + .rodata.str1.4 + 0x004e8aec 0x1e /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_eeprom.o) + *fill* 0x004e8b0a 0x2 00 + .rodata.str1.4 + 0x004e8b0c 0x98 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_misc.o) + 0x9c (size before relaxing) + .rodata.str1.4 + 0x004e8ba4 0x3b /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_printf.o) + *fill* 0x004e8bdf 0x1 00 + .rodata.str1.4 + 0x004e8be0 0x82 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_rompatch.o) + *fill* 0x004e8c62 0x2 00 + .rodata.str1.4 + 0x004e8c64 0x71 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(hif_pci.o) + *fill* 0x004e8cd5 0x3 00 + .rodata.str1.4 + 0x004e8cd8 0xc2 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+ *(.gnu.version_r) + 0x004e9044 . = ALIGN (0x4) + 0x004e9044 _bss_table_start = (.) + 0x004e9044 0x4 LONG 0x500400 _dport0_bss_start + 0x004e9048 0x4 LONG 0x500400 _dport0_bss_end + 0x004e904c 0x4 LONG 0x500950 _bss_start + 0x004e9050 0x4 LONG 0x500b78 _bss_end + 0x004e9054 _bss_table_end = (.) + 0x004e9054 _rodata_end = (.) + +.dram0.literal 0x004e9054 0x0 + 0x004e9054 _dram0_literal_start = (.) + *(.dram0.literal) + *(.dram.literal) + 0x004e9054 _dram0_literal_end = (.) + +.dram0.data 0x00500400 0x0 + 0x00500400 _dram0_data_start = (.) + *(.dram0.data) + *(.dram.data) + 0x00500400 _dram0_data_end = (.) + +.data 0x00500400 0x550 + 0x00500400 _data_start = (.) + *(.data) + .data 0x00500400 0x100 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(user-vector.o) + 0x00500400 _xtos_exc_handler_table + .data 0x00500500 0x138 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(interrupt-table.o) + 0x00500500 _xtos_enabled + 0x00500500 _xtos_intstruct + 0x00500508 _xtos_interrupt_table + 0x005005a0 _xtos_interrupt_mask_table + 0x00500504 _xtos_vpri_enabled + *fill* 0x00500638 0x8 00 + .data 0x00500640 0xb8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + 0x00500640 basic_ROM_module_table + .data 0x005006f8 0x8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_misc.o) + 0x005006fc assprint + 0x005006f8 assloop + .data 0x00500700 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_printf.o) + 0x00500700 _putc + .data 0x00500704 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_rompatch.o) + 0x00500704 patch_addr + .data 0x00500708 0xc /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(hif_pci.o) + 0x00500708 pci_sc + *fill* 0x00500714 0xc 00 + .data 0x00500720 0x44 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_api.o) + 0x00500720 TestPatn0 + 0x00500730 TestPatn1 + *fill* 0x00500764 0xc 00 + .data 0x00500770 0x4c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_table.o) + 0x00500780 u8OtherSpeedConfigDescriptorEX + 0x00500770 u8DeviceQualifierDescriptorEX + *fill* 0x005007bc 0x4 00 + .data 0x005007c0 0x90 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(dma_lib.o) + 0x005007c0 eng_q + .data 0x00500850 0x100 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-table.o) + 0x00500850 _xtos_c_handler_table + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.eh_frame) + *crtbegin.o(.ctors) + *(EXCLUDE_FILE(*crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *(EXCLUDE_FILE(*crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + 0x00500950 __XT_EXCEPTION_DESCS__ = (.) + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + 0x00500950 __XT_EXCEPTION_DESCS_END__ = (.) + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + 0x00500950 _data_end = (.) + +.bss 0x00500950 0x2a8 + 0x00500950 . = ALIGN (0x8) + 0x00500950 _bss_start = (.) + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + .bss 0x00500950 0x2 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + *fill* 0x00500952 0x2 00 + .bss 0x00500954 0x8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_allocram.o) + 0x00500954 allocram_current_addr + 0x00500958 allocram_remaining_bytes + .bss 0x0050095c 0x1c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_clock.o) + 0x00500970 pll_ctrl_setting_5ghz + 0x0050096c pll_ctrl_setting_24ghz + 0x00500964 clock_info + 0x0050095c cticks + 0x00500968 cmnos_skip_pll_init + 0x00500960 curr_band + .bss 0x00500978 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_eeprom.o) + 0x00500978 eep_state + 0x0050097a eep_exist + *fill* 0x0050097c 0x4 00 + .bss 0x00500980 0xa8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_intr.o) + 0x00500980 cmnos_enabled_interrupts + 0x00500990 cmnos_isr_info + .bss 0x00500a28 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_misc.o) + 0x00500a28 current_dump + .bss 0x00500a2c 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_rompatch.o) + 0x00500a2c patch_start + .bss 0x00500a30 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_tasklet.o) + .bss 0x00500a34 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_timer.o) + 0x00500a34 timer_list + .bss 0x00500a38 0xc /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_wdt.o) + 0x00500a38 wdt_ctrl + .bss 0x00500a44 0x10 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(uart_api.o) + .bss 0x00500a54 0x44 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(HIF_usb.o) + 0x00500a54 g_hifUSBCtx + .bss 0x00500a98 0x5e /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_api.o) + 0x00500abc u16TxRxCounter + 0x00500ad0 u8UsbInterfaceValue + 0x00500ae0 u8String10Descriptor + 0x00500ad4 u16FirmwareComplete + 0x00500ad8 u8UsbDeviceDescriptor + 0x00500ad2 u8UsbInterfaceAlternateSetting + 0x00500aa4 usbFifoConf + 0x00500ab8 pu8DescriptorEX + 0x00500ac8 eUsbCxCommand + 0x00500af0 UsbStatus + 0x00500a98 ControlCmd + 0x00500ace u8UsbConfigValue + 0x00500ae4 u8String20Descriptor + 0x00500ae8 u8String30Descriptor + 0x00500ac4 eUsbCxFinishAction + 0x00500ac0 u8ConfigDescriptorEX + 0x00500acc UsbChirpFinish + 0x00500ab4 fwCheckSum + 0x00500adc u8String00Descriptor + *fill* 0x00500af6 0x2 00 + .bss 0x00500af8 0xc /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvbuf.a(vbuf.o) + 0x00500af8 g_vbufCtx + .bss 0x00500b04 0x8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvdesc.a(vdesc.o) + 0x00500b04 g_vdescCtx + .bss 0x00500b0c 0xc /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libfwd.a(fwd.o) + 0x00500b0c fwd_sc + .bss 0x00500b18 0x2c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libbuf_pool.a(buf_pool_static.o) + 0x00500b18 g_poolCtx + .bss 0x00500b44 0x2d /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(misc.o) + 0x00500b4d Xthal_have_clamps + 0x00500b70 Xthal_num_xlmi + 0x00500b48 Xthal_release_internal + 0x00500b6a Xthal_itlb_way_bits + 0x00500b6b Xthal_itlb_arf_ways + 0x00500b44 Xthal_release_minor + 0x00500b64 Xthal_have_xlt_cacheattr + 0x00500b50 Xthal_have_speculation + 0x00500b67 Xthal_mmu_asid_kernel + 0x00500b69 Xthal_mmu_sr_bits + 0x00500b65 Xthal_have_cacheattr + 0x00500b6d Xthal_dtlb_arf_ways + 0x00500b6c Xthal_dtlb_way_bits + 0x00500b60 Xthal_hw_release_internal + 0x00500b58 Xthal_hw_min_version_minor + 0x00500b4f Xthal_have_fp + 0x00500b68 Xthal_mmu_ring_bits + 0x00500b4e Xthal_have_mac16 + 0x00500b4c Xthal_have_booleans + 0x00500b66 Xthal_mmu_asid_bits + 0x00500b6e Xthal_num_instrom + 0x00500b54 Xthal_hw_release_minor + 0x00500b5c Xthal_hw_max_version_minor + 0x00500b6f Xthal_num_datarom + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + *(.dram0.bss) + 0x00500b78 . = ALIGN (0x8) + *fill* 0x00500b71 0x7 00 + *fill* 0x00500b78 0x0 00 + *fill* 0x00500b78 0x0 00 + *fill* 0x00500b78 0x0 00 + *fill* 0x00500b78 0x0 00 + 0x00500b78 _bss_end = (.) + 0x00500bf8 . = (. + 0x80) + *fill* 0x00500b78 0x80 00 + *fill* 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0x008e08c0 _WindowUnderflow8 + 0x008e096a _WindowVectors_text_end = (.) + +.KernelExceptionVector.literal + 0x008e0d00 0x0 + 0x008e0d00 _KernelExceptionVector_literal_start = (.) + *(.KernelExceptionVector.literal) + 0x008e0d00 _KernelExceptionVector_literal_end = (.) + +.KernelExceptionVector.text + 0x008e0d40 0x6 + 0x008e0d40 _KernelExceptionVector_text_start = (.) + *(.KernelExceptionVector.text) + .KernelExceptionVector.text + 0x008e0d40 0x6 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(kernel-vector.o) + 0x008e0d40 _KernelExceptionVector + 0x008e0d46 _KernelExceptionVector_text_end = (.) + +.UserExceptionVector.literal + 0x008e0e00 0x0 + 0x008e0e00 _UserExceptionVector_literal_start = (.) + *(.UserExceptionVector.literal) + 0x008e0e00 _UserExceptionVector_literal_end = (.) + +.UserExceptionVector.text + 0x008e0e20 0x17 + 0x008e0e20 _UserExceptionVector_text_start = (.) + *(.UserExceptionVector.text) + .UserExceptionVector.text + 0x008e0e20 0x17 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(user-vector.o) + 0x008e0e20 _UserExceptionVector + 0x008e0e37 _UserExceptionVector_text_end = (.) + +.DoubleExceptionVector.literal + 0x008e0f00 0x0 + 0x008e0f00 _DoubleExceptionVector_literal_start = (.) + *(.DoubleExceptionVector.literal) + 0x008e0f00 _DoubleExceptionVector_literal_end = (.) + +.DoubleExceptionVector.text + 0x008e0f20 0x6 + 0x008e0f20 _DoubleExceptionVector_text_start = (.) + *(.DoubleExceptionVector.text) + .DoubleExceptionVector.text + 0x008e0f20 0x6 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(double-vector.o) + 0x008e0f20 _DoubleExceptionVector + 0x008e0f26 _DoubleExceptionVector_text_end = (.) + +.Level2InterruptVector.literal + 0x008e0a00 0x0 + 0x008e0a00 _Level2InterruptVector_literal_start = (.) + *(.Level2InterruptVector.literal) + 0x008e0a00 _Level2InterruptVector_literal_end = (.) + +.Level2InterruptVector.text + 0x008e0a20 0x6 + 0x008e0a20 _Level2InterruptVector_text_start = (.) + *(.Level2InterruptVector.text) + .Level2InterruptVector.text + 0x008e0a20 0x6 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-vector-level2.o) + 0x008e0a20 _Level2Vector + 0x008e0a26 _Level2InterruptVector_text_end = (.) + +.Level3InterruptVector.literal + 0x008e0b00 0x0 + 0x008e0b00 _Level3InterruptVector_literal_start = (.) + *(.Level3InterruptVector.literal) + 0x008e0b00 _Level3InterruptVector_literal_end = (.) + +.Level3InterruptVector.text + 0x008e0b20 0x6 + 0x008e0b20 _Level3InterruptVector_text_start = (.) + *(.Level3InterruptVector.text) + .Level3InterruptVector.text + 0x008e0b20 0x6 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-vector-level3.o) + 0x008e0b20 _Level3Vector + 0x008e0b26 _Level3InterruptVector_text_end = (.) + +.DebugExceptionVector.literal + 0x008e0c00 0x0 + 0x008e0c00 _DebugExceptionVector_literal_start = (.) + *(.DebugExceptionVector.literal) + 0x008e0c00 _DebugExceptionVector_literal_end = (.) + +.DebugExceptionVector.text + 0x008e0c20 0x6 + 0x008e0c20 _DebugExceptionVector_text_start = (.) + *(.DebugExceptionVector.text) + .DebugExceptionVector.text + 0x008e0c20 0x6 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(debug-vector.o) + 0x008e0c20 _DebugExceptionVector + 0x008e0c26 _DebugExceptionVector_text_end = (.) + +.NMIExceptionVector.literal + 0x008e0ce0 0x0 + 0x008e0ce0 _NMIExceptionVector_literal_start = (.) + *(.NMIExceptionVector.literal) + 0x008e0ce0 _NMIExceptionVector_literal_end = (.) + +.NMIExceptionVector.text + 0x008e0ce4 0x3 + 0x008e0ce4 _NMIExceptionVector_text_start = (.) + *(.NMIExceptionVector.text) + .NMIExceptionVector.text + 0x008e0ce4 0x3 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(nmi-vector.o) + 0x008e0ce4 _NMIExceptionVector + 0x008e0ce7 _NMIExceptionVector_text_end = (.) + +.iram0.text 0x008e1000 0x0 + 0x008e1000 _iram0_text_start = (.) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + 0x008e1000 _iram0_text_end = (.) + +.text 0x008e1000 0x5e94 + 0x008e1000 _stext = . + 0x008e1000 _text_start = (.) + *(.entry.text) + *(.init) + *(.init) + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + .text 0x008e1000 0x2a /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/crt1-tiny.o + 0x008e1000 _start + *fill* 0x008e102a 0x2 00 + .text 0x008e102c 0xd7 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-alloca-handler.o) + 0x008e102c _xtos_alloca_handler + *fill* 0x008e1103 0x1 00 + .text 0x008e1104 0x6f /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-syscall-handler.o) + 0x008e1104 _xtos_syscall_handler + 0x008e1143 _SyscallException + *fill* 0x008e1173 0x1 00 + .text 0x008e1174 0x6e /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-lowpri-dispatcher.o) + 0x008e1174 _xtos_l1int_handler + 0x008e1192 _LevelOneInterrupt + *fill* 0x008e11e2 0x2 00 + .text 0x008e11e4 0x5c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-sethandler.o) + 0x008e11e4 _xtos_set_interrupt_handler_arg + 0x008e1230 _xtos_set_interrupt_handler + .text 0x008e1240 0xb1 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-handler-level2.o) + 0x008e1240 _Level2FromVector + 0x008e12f1 _Level2HandlerLabel + *fill* 0x008e12f1 0x3 00 + .text 0x008e12f4 0xae /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-handler-level3.o) + 0x008e12f4 _Level3FromVector + 0x008e13a2 _Level3HandlerLabel + *fill* 0x008e13a2 0x2 00 + .text 0x008e13a4 0x88e /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + 0x008e1604 athos_interrupt_handler + 0x008e18c8 turn_off_rc + 0x008e167c athos_init + 0x008e16e8 read_usb_conf + 0x008e178c set_pci_conf + 0x008e1614 athos_interrupt_init + 0x008e1548 generic_hif_module_install + 0x008e16b0 _read_usb_desc + 0x008e13f8 Magpie_fatal_exception_handler + 0x008e1468 athos_restore_intrlvl + 0x008e18fc bootentry + 0x008e1c14 main + 0x008e189c pci_gmac_bootload + 0x008e1574 athos_indirection_table_install + 0x008e1860 bootload + 0x008e13a4 post + 0x008e1454 athos_block_all_intrlvl + 0x008e1460 athos_unblock_all_intrlvl + *fill* 0x008e1c32 0x2 00 + .text 0x008e1c34 0x78 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_allocram.o) + 0x008e1c98 cmnos_allocram_module_install + 0x008e1c44 cmnos_allocram + 0x008e1c74 cmnos_allocram_debug + 0x008e1c34 cmnos_allocram_init + .text 0x008e1cac 0xf2 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_clock.o) + 0x008e1cdc cmnos_refclk_speed_get + 0x008e1ce8 cmnos_uart_frequency + 0x008e1cf0 cmnos_sysclk_change + 0x008e1d00 cmnos_wlan_band_set + 0x008e1d44 cmnos_tick + 0x008e1d08 cmnos_pll_init + 0x008e1cac cmnos_delay_us + 0x008e1cf8 cmnos_clockregs_init + 0x008e1ccc cmnos_milliseconds + 0x008e1d6c cmnos_clock_module_install + 0x008e1d10 cmnos_clock_init + *fill* 0x008e1d9e 0x2 00 + .text 0x008e1da0 0x3e5 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_eeprom.o) + 0x008e1e24 cmnos_eep_is_exist + 0x008e1da0 cmnos_eeprom_write_hword + 0x008e216c cmnos_eep_module_install + 0x008e1df8 cmnos_eeprom_read_hword + 0x008e1ebc cmnos_eep_read + 0x008e1f04 cmnos_eep_init + 0x008e1e5c cmnos_eep_write + *fill* 0x008e2185 0x3 00 + .text 0x008e2188 0x18e /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_intr.o) + 0x008e21b8 cmnos_intr_mask_inum + 0x008e2298 cmnos_intr_invoke_isr + 0x008e22f8 cmnos_intr_module_install + 0x008e2188 cmnos_intr_dummy + 0x008e21f8 cmnos_intr_unmask_inum + 0x008e2190 cmnos_intr_init + 0x008e2234 cmnos_intr_attach_isr + *fill* 0x008e2316 0x2 00 + .text 0x008e2318 0x26 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_mem.o) + 0x008e2318 cmnos_mem_init + 0x008e2320 cmnos_mem_module_install + *fill* 0x008e233e 0x2 00 + .text 0x008e2340 0x175 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_misc.o) + 0x008e235c cmnos_misaligned_load_handler + 0x008e247c cmnos_rom_version_get + 0x008e2354 cmnos_mac_reset + 0x008e2340 cmnos_system_reset + 0x008e245c cmnos_is_host_present + 0x008e242c cmnos_get_kbhit + 0x008e2488 cmnos_misc_module_install + 0x008e23b0 cmnos_assfail + 0x008e241c cmnos_report_failure_to_host + 0x008e2424 cmnos_target_id_get + *fill* 0x008e24b5 0x3 00 + .text 0x008e24b8 0x513 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_printf.o) + 0x008e29bc cmnos_printf_module_install + 0x008e24b8 cmnos_write_char + 0x008e2980 cmnos_printf + 0x008e29b4 cmnos_printf_init + *fill* 0x008e29cb 0x1 00 + .text 0x008e29cc 0x155 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_rompatch.o) + 0x008e2a50 cmnos_romp_decode + 0x008e2b08 cmnos_romp_module_install + 0x008e2a9c cmnos_romp_download + 0x008e2b00 cmnos_romp_init + 0x008e29e4 _read_rom_patch + 0x008e29cc _patch_dump + 0x008e2a8c cmnos_romp_install + *fill* 0x008e2b21 0x3 00 + .text 0x008e2b24 0x2b /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_string.o) + 0x008e2b2c cmnos_string_module_install + 0x008e2b24 cmnos_string_init + *fill* 0x008e2b4f 0x1 00 + .text 0x008e2b50 0xb2 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_tasklet.o) + 0x008e2b50 cmnos_tasklet_init + 0x008e2b88 cmnos_tasklet_disable + 0x008e2b6c cmnos_tasklet_schedule + 0x008e2be4 cmnos_tasklet_module_install + 0x008e2bbc cmnos_tasklet_run + 0x008e2b5c cmnos_tasklet_init_task + *fill* 0x008e2c02 0x2 00 + .text 0x008e2c04 0xde /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_timer.o) + 0x008e2c04 cmnos_timer_setfn + 0x008e2c58 cmnos_timer_disarm + 0x008e2c14 cmnos_timer_arm + 0x008e2cc4 cmnos_timer_module_install + 0x008e2c94 cmnos_timer_handler + 0x008e2c88 cmnos_timer_init + *fill* 0x008e2ce2 0x2 00 + .text 0x008e2ce4 0x114 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_wdt.o) + 0x008e2d90 cmnos_wdt_init + 0x008e2d74 cmnos_wdt_disable + 0x008e2dd0 cmnos_wdt_module_install + 0x008e2ce4 cmnos_wdt_last_boot + 0x008e2db8 cmnos_wdt_task + 0x008e2d2c cmnos_wdt_set + 0x008e2d10 cmnos_wdt_reset + 0x008e2d54 cmnos_wdt_enable + .text 0x008e2df8 0x19b /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(uart_api.o) + 0x008e2e74 _uart_char_put_nowait + 0x008e2ed4 _uart_str_out + 0x008e2e40 _uart_char_get_nothing + 0x008e2e48 _uart_char_put + 0x008e2ec0 _uart_task + 0x008e2ec8 _uart_status + 0x008e2df8 _uart_init + 0x008e2f5c cmnos_uart_module_install + 0x008e2ea0 _uart_char_get + 0x008e2e38 _uart_char_put_nothing + 0x008e2ef4 _uart_config + *fill* 0x008e2f93 0x1 00 + .text 0x008e2f94 0x41a /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(hif_pci.o) + 0x008e337c hif_pci_api_install + 0x008e31e8 __pci_reap_recv + 0x008e2fd4 __pci_get_tx_eng + 0x008e300c __pci_enable + 0x008e32f8 __pci_is_pipe_supported + 0x008e2fe8 __pci_get_rx_eng + 0x008e2fa0 __pci_reg_write + 0x008e3308 __pci_get_max_msg_len + 0x008e3210 __pci_isr_handler + 0x008e32b0 __pci_xmit_buf + 0x008e3110 __pci_init + 0x008e3328 __pci_get_def_pipe + 0x008e31a8 __pci_reg_callback + 0x008e3338 hif_pci_module_install + 0x008e3164 __pci_cfg_pipe + 0x008e2fac __pci_get_pipe + 0x008e3318 __pci_get_reserved_headroom + 0x008e30d8 __pci_boot_init + 0x008e31bc __pci_reap_xmitted + 0x008e32dc __pci_return_recv + 0x008e3320 __pci_shutdown + 0x008e2f94 __pci_reg_read + 0x008e31a0 __pci_start + 0x008e3024 __pci_reset + *fill* 0x008e33ae 0x2 00 + .text 0x008e33b0 0x4d4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(HIF_usb.o) + 0x008e37e8 HIFusb_DescTraceDump + 0x008e367c _HIFusb_return_recv_buf + 0x008e36c0 _HIFusb_is_pipe_supported + 0x008e3430 _HIFusb_init + 0x008e36e4 _HIFusb_isr_handler + 0x008e36d0 _HIFusb_get_max_msg_len + 0x008e36b0 _HIFusb_pause_recv + 0x008e3570 _HIFusb_config_pipe + 0x008e36a8 _HIFusb_set_recv_bufsz + 0x008e37a4 hif_usb_module_install + 0x008e348c _HIFusb_register_callback + 0x008e3484 _HIFusb_shutdown + 0x008e3794 _HIFusb_get_default_pipe + 0x008e34a0 _HIFusb_start + 0x008e361c _HIFusb_send_buffer + 0x008e36b8 _HIFusb_resume_recv + .text 0x008e3884 0x1071 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_api.o) + 0x008e4848 usbfifo_module_install + 0x008e4858 cmnos_usb_module_install + 0x008e476c _usb_init + *fill* 0x008e48f5 0x3 00 + .text 0x008e48f8 0x3b3 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_fifo.o) + 0x008e4934 mUsbFIFOConfig + 0x008e497c mUsbEPMxPtSzLow + 0x008e48f8 mUsbEPMap + 0x008e4b7c vUsbFIFO_EPxCfg_FS + 0x008e4954 mUsbEPMxPtSzHigh + 0x008e49ec vUsbFIFO_EPxCfg_HS + 0x008e4914 mUsbFIFOMap + 0x008e49a0 mUsbEPinHighBandSet + *fill* 0x008e4cab 0x1 00 + .text 0x008e4cac 0x243 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(dma_lib.o) + 0x008e4d7c __dma_lib_rx_init + 0x008e4eb8 dma_lib_module_install + 0x008e4e50 __dma_reap_recv + 0x008e4cb8 __dma_reg_write + 0x008e4da8 __dma_hard_xmit + 0x008e4e28 __dma_xmit_done + 0x008e4cc4 __dma_set_base + 0x008e4d2c __dma_lib_rx_config + 0x008e4ce4 __dma_lib_tx_init + 0x008e4e6c __dma_return_recv + 0x008e4cac __dma_reg_read + 0x008e4dd0 __dma_reap_xmitted + 0x008e4dec __dma_flush_xmit + 0x008e4e94 __dma_recv_pkt + *fill* 0x008e4eef 0x1 00 + .text 0x008e4ef0 0x84 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvbuf.a(vbuf.o) + 0x008e4f4c _vbuf_free_vbuf + 0x008e4f60 vbuf_module_install + 0x008e4f2c _vbuf_alloc_vbuf + 0x008e4ef0 _vbuf_init + .text 0x008e4f74 0xb5 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvdesc.a(vdesc.o) + 0x008e4fb0 _vdesc_alloc_desc + 0x008e4fc8 _vdesc_get_hw_desc + 0x008e5010 vdesc_module_install + 0x008e4f74 _vdesc_init + 0x008e4fd0 _vdesc_swap_vdesc + *fill* 0x008e5029 0x3 00 + .text 0x008e502c 0x8ef /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhtc.a(htc.o) + 0x008e56f4 HTCControlSvcProcessMsg + 0x008e57e4 AdjustCreditThreshold + 0x008e5114 _HTC_Init + 0x008e520c _HTC_Ready + 0x008e5260 ReturnBuffers + 0x008e5328 _HTC_SendMsg + 0x008e567c HTCProcessConfigPipeMsg + 0x008e5494 _HTC_GetReservedHeadroom + 0x008e57bc HTCSendDoneHandler + 0x008e5524 HTCCheckAndSendCreditReport + 0x008e5484 _HTC_PauseRecv + 0x008e51f4 _HTC_Shutdown + 0x008e54ec HTCFreeMsgBuffer + 0x008e5318 _HTC_ReturnBuffers + 0x008e581c HTCMsgRecvHandler + 0x008e54a8 htc_module_install + 0x008e577c HTCControlSvcProcessSendComplete + 0x008e5504 HTCAllocMsgBuffer + 0x008e51fc _HTC_RegisterService + 0x008e5584 HTCProcessConnectMsg + 0x008e50fc HTC_AssembleBuffers + 0x008e548c _HTC_ResumeRecv + 0x008e52e0 _HTC_ReturnBuffersList + 0x008e5814 RedistributeCredit + *fill* 0x008e591b 0x1 00 + .text 0x008e591c 0x3d3 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libdma.a(dma_engine.o) + 0x008e5964 _DMAengine_init_tx_queue + 0x008e5924 _DMAengine_init_rx_queue + 0x008e591c _DMAengine_init + 0x008e5a50 _DMAengine_config_rx_queue + 0x008e5c58 dma_engine_module_install + 0x008e5b70 _DMAengine_has_compl_packets + 0x008e5b68 _DMAengine_flush_xmit + 0x008e5b90 _DMAengine_reap_recv_buf + 0x008e5bc0 _DMAengine_reap_xmited_buf + 0x008e5bf8 _DMAengine_desc_dump + 0x008e59c0 _DMAengine_return_recv_buf + 0x008e5aa8 _DMAengine_xmit_buf + *fill* 0x008e5cef 0x1 00 + .text 0x008e5cf0 0x16f /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libdma.a(desc.o) + 0x008e5d2c zfDmaReclaimPacket + 0x008e5cf0 zfDmaGetPacket + 0x008e5dc0 zfDmaPutPacket + *fill* 0x008e5e5f 0x1 00 + .text 0x008e5e60 0x404 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libfwd.a(fwd.o) + 0x008e5eb0 fwd_retbuf_handler + 0x008e615c magpie_mdio_copy_bytes + 0x008e5ffc magpie_mdio_boot_init + 0x008e619c fw_compute_cksum + 0x008e61bc mdio_get_fw_image + 0x008e5ec8 fwd_tgt_process_last + 0x008e5ef8 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0x00004b84 0x108 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strcpy.o) + .xt.prop 0x00004c8c 0xb4 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strlen.o) + .xt.prop 0x00004d40 0xe4 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strncmp.o) + .xt.prop 0x00004e24 0x198 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strncpy.o) + *(.xt.prop.*) + *(.gnu.linkonce.prop.*) + +.xt.lit 0x00000000 0x8 + *(.xt.lit) + .xt.lit 0x00000000 0x8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(reset-vector-unpack.o) + *(.xt.lit.*) + *(.gnu.linkonce.p.*) + +.xt.profile_range + *(.xt.profile_range) + *(.gnu.linkonce.profile_range.*) + +.xt.profile_ranges + *(.xt.profile_ranges) + *(.gnu.linkonce.xt.profile_ranges.*) + +.xt.profile_files + *(.xt.profile_files) + *(.gnu.linkonce.xt.profile_files.*) +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/_vectors.o +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/crt1-tiny.o +START GROUP +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvbuf.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvdesc.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhtc.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libdma.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libfwd.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libbuf_pool.a +END GROUP +LOAD /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a +LOAD /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib/xcc//libgcc.a +LOAD /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a +OUTPUT(rom.asic.out elf32-xtensa-be) + +.xtensa.info 0x00000000 0x1b4 + .xtensa.info 0x00000000 0x1b4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/_vectors.o diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/image/output/asic/rom.asic.objdump b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/output/asic/rom.asic.objdump new file mode 100755 index 0000000..001831c --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/output/asic/rom.asic.objdump @@ -0,0 +1,107884 @@ + +rom.asic.out: file format elf32-xtensa-be +rom.asic.out +architecture: xtensa, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x008e0000 + +Xtensa header: + +Machine = Base +Insn tables = true +Literal tables = true + +Program Header: + LOAD off 0x00000200 vaddr 0x008e0000 paddr 0x008e0000 align 2**0 + filesz 0x000000de memsz 0x000000de flags r-x + LOAD off 0x000002de vaddr 0x008e0800 paddr 0x008e0800 align 2**0 + filesz 0x0000016a memsz 0x0000016a flags r-x + LOAD off 0x00000448 vaddr 0x008e0a20 paddr 0x008e0a20 align 2**0 + filesz 0x00000006 memsz 0x00000006 flags r-x + LOAD off 0x00000450 vaddr 0x008e0b20 paddr 0x008e0b20 align 2**0 + filesz 0x00000006 memsz 0x00000006 flags r-x + LOAD off 0x00000458 vaddr 0x008e0c20 paddr 0x008e0c20 align 2**0 + filesz 0x00000006 memsz 0x00000006 flags r-x + LOAD off 0x00000460 vaddr 0x008e0ce4 paddr 0x008e0ce4 align 2**0 + filesz 0x00000003 memsz 0x00000003 flags r-x + LOAD off 0x00000464 vaddr 0x008e0d40 paddr 0x008e0d40 align 2**0 + filesz 0x00000006 memsz 0x00000006 flags r-x + LOAD off 0x0000046c vaddr 0x008e0e20 paddr 0x008e0e20 align 2**0 + filesz 0x00000017 memsz 0x00000017 flags r-x + LOAD off 0x00000484 vaddr 0x008e0f20 paddr 0x008e0f20 align 2**0 + filesz 0x00000006 memsz 0x00000006 flags r-x + LOAD off 0x0000048c vaddr 0x008e1000 paddr 0x008e1000 align 2**0 + filesz 0x00005e94 memsz 0x00005e94 flags r-x + LOAD off 0x00006320 vaddr 0x004e8000 paddr 0x004e8000 align 2**0 + filesz 0x00001054 memsz 0x00001054 flags r-x + LOAD off 0x00007370 vaddr 0x00500000 paddr 0x00500000 align 2**0 + filesz 0x00000950 memsz 0x00000ff8 flags rw- + LOAD off 0x00007cc4 vaddr 0x0053f7f0 paddr 0x0053f7f0 align 2**0 + filesz 0x00000000 memsz 0x00000800 flags rw- + LOAD off 0x00007cd0 vaddr 0x004e0100 paddr 0x004e0100 align 2**0 + filesz 0x000000ec memsz 0x000000ec flags r-- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .lit4 00000718 004e8000 004e8000 00006320 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .ResetVector.literal 00000000 004e8718 004e8718 00006a38 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .dport0.stack 00000800 0053f7f0 0053f7f0 00007cc4 2**0 + ALLOC + 3 .dport0.usb_in_rom 000000ec 004e0100 004e0100 00007cd0 2**4 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .dport0.data 00000400 00500000 00500004 00007374 2**0 + CONTENTS, ALLOC, LOAD, DATA + 5 .dport0.bss 00000000 00500400 00500400 00007dbc 2**0 + + 6 .dram0.rodata 00000000 004e8718 004e8718 00007dbc 2**0 + CONTENTS + 7 .rodata 00000934 004e8720 004e8720 00006a40 2**4 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .dram0.literal 00000000 004e9054 004e9054 00007dbc 2**0 + CONTENTS + 9 .dram0.data 00000000 00500400 00500400 00007dbc 2**0 + CONTENTS + 10 .data 00000550 00500400 00500400 00007774 2**4 + CONTENTS, ALLOC, LOAD, DATA + 11 .bss 000002a8 00500950 00500950 00007cc4 2**4 + ALLOC + 12 .ResetVector.text 000000de 008e0000 008e0000 00000200 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 13 .WindowVectors.text 0000016a 008e0800 008e0800 000002de 2**0 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 14 .KernelExceptionVector.literal 00000000 008e0d00 008e0d00 00007dbc 2**0 + CONTENTS + 15 .KernelExceptionVector.text 00000006 008e0d40 008e0d40 00000464 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 16 .UserExceptionVector.literal 00000000 008e0e00 008e0e00 00007dbc 2**0 + CONTENTS + 17 .UserExceptionVector.text 00000017 008e0e20 008e0e20 0000046c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 18 .DoubleExceptionVector.literal 00000000 008e0f00 008e0f00 00007dbc 2**0 + CONTENTS + 19 .DoubleExceptionVector.text 00000006 008e0f20 008e0f20 00000484 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 20 .Level2InterruptVector.literal 00000000 008e0a00 008e0a00 00007dbc 2**0 + CONTENTS + 21 .Level2InterruptVector.text 00000006 008e0a20 008e0a20 00000448 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 22 .Level3InterruptVector.literal 00000000 008e0b00 008e0b00 00007dbc 2**0 + CONTENTS + 23 .Level3InterruptVector.text 00000006 008e0b20 008e0b20 00000450 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 24 .DebugExceptionVector.literal 00000000 008e0c00 008e0c00 00007dbc 2**0 + CONTENTS + 25 .DebugExceptionVector.text 00000006 008e0c20 008e0c20 00000458 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 26 .NMIExceptionVector.literal 00000000 008e0ce0 008e0ce0 00007dbc 2**0 + CONTENTS + 27 .NMIExceptionVector.text 00000003 008e0ce4 008e0ce4 00000460 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 28 .iram0.text 00000000 008e1000 008e1000 00007dbc 2**0 + CONTENTS + 29 .text 00005e94 008e1000 008e1000 0000048c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 30 .debug_aranges 00000840 00000000 00000000 00007dc0 2**3 + CONTENTS, READONLY, DEBUGGING + 31 .debug_pubnames 000024ff 00000000 00000000 00008600 2**0 + CONTENTS, READONLY, DEBUGGING + 32 .debug_info 000806eb 00000000 00000000 0000aaff 2**0 + CONTENTS, READONLY, DEBUGGING + 33 .debug_abbrev 0000321a 00000000 00000000 0008b1ea 2**0 + CONTENTS, READONLY, DEBUGGING + 34 .debug_line 0001e431 00000000 00000000 0008e404 2**0 + CONTENTS, READONLY, DEBUGGING + 35 .xt.prop 00004fbc 00000000 00000000 000ac835 2**0 + CONTENTS, READONLY + 36 .xt.lit 00000008 00000000 00000000 000b17f1 2**0 + CONTENTS, READONLY + 37 .xtensa.info 000001b4 00000000 00000000 000b17f9 2**0 + CONTENTS, READONLY +SYMBOL TABLE: +004e8000 l d .lit4 00000000 .lit4 +004e8718 l d .ResetVector.literal 00000000 .ResetVector.literal +0053f7f0 l d .dport0.stack 00000000 .dport0.stack +004e0100 l d .dport0.usb_in_rom 00000000 .dport0.usb_in_rom +00500000 l d .dport0.data 00000000 .dport0.data +00500400 l d .dport0.bss 00000000 .dport0.bss +004e8718 l d .dram0.rodata 00000000 .dram0.rodata +004e8720 l d .rodata 00000000 .rodata +004e9054 l d .dram0.literal 00000000 .dram0.literal +00500400 l d .dram0.data 00000000 .dram0.data +00500400 l d .data 00000000 .data +00500950 l d .bss 00000000 .bss +008e0000 l d .ResetVector.text 00000000 .ResetVector.text +008e0800 l d .WindowVectors.text 00000000 .WindowVectors.text +008e0d00 l d .KernelExceptionVector.literal 00000000 .KernelExceptionVector.literal +008e0d40 l d .KernelExceptionVector.text 00000000 .KernelExceptionVector.text +008e0e00 l d .UserExceptionVector.literal 00000000 .UserExceptionVector.literal +008e0e20 l d .UserExceptionVector.text 00000000 .UserExceptionVector.text +008e0f00 l d .DoubleExceptionVector.literal 00000000 .DoubleExceptionVector.literal +008e0f20 l d .DoubleExceptionVector.text 00000000 .DoubleExceptionVector.text +008e0a00 l d .Level2InterruptVector.literal 00000000 .Level2InterruptVector.literal +008e0a20 l d .Level2InterruptVector.text 00000000 .Level2InterruptVector.text +008e0b00 l d .Level3InterruptVector.literal 00000000 .Level3InterruptVector.literal +008e0b20 l d .Level3InterruptVector.text 00000000 .Level3InterruptVector.text +008e0c00 l d .DebugExceptionVector.literal 00000000 .DebugExceptionVector.literal +008e0c20 l d .DebugExceptionVector.text 00000000 .DebugExceptionVector.text +008e0ce0 l d .NMIExceptionVector.literal 00000000 .NMIExceptionVector.literal +008e0ce4 l d .NMIExceptionVector.text 00000000 .NMIExceptionVector.text +008e1000 l d .iram0.text 00000000 .iram0.text +008e1000 l d .text 00000000 .text +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_pubnames 00000000 .debug_pubnames +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .xt.prop 00000000 .xt.prop +00000000 l d .xt.lit 00000000 .xt.lit +00000000 l d .xtensa.info 00000000 .xtensa.info +00000000 l d *ABS* 00000000 .shstrtab +00000000 l d *ABS* 00000000 .symtab +00000000 l d *ABS* 00000000 .strtab +00000000 l df *ABS* 00000000 crt1-tiny.S +00000000 l df *ABS* 00000000 reset-vector.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +008e00b6 l .ResetVector.text 00000000 unpackdone +008e0094 l .ResetVector.text 00000000 unpack +008e00b0 l .ResetVector.text 00000000 upnext +008e00a0 l .ResetVector.text 00000000 uploop +00000000 l df *ABS* 00000000 user-vector.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 exc-alloca-handler.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 exc-syscall-handler.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000007 l *ABS* 00000000 .Ldelta_done +00000000 l df *ABS* 00000000 int-lowpri-dispatcher.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +008e11ce l .text 00000000 spurious_int +00000000 l df *ABS* 00000000 int-handler.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +008e12d4 l .text 00000000 spurious2int +008e12e8 l .text 00000000 return2from_exc +00000000 l df *ABS* 00000000 int-handler.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +008e1388 l .text 00000000 spurious3int +008e1399 l .text 00000000 return3from_exc +004e8740 l O .rodata 00000010 pattern.init_91_2 +008e1428 l F .text 00000029 athos_linkage_check +008e1474 l F .text 0000005e AR6002_misaligned_load_handler +008e14d4 l F .text 00000071 AR6002_fatal_exception_handler +00500950 l O .bss 00000002 i.1_140_4 +00500974 l O .bss 00000004 last_tick.1_93_1 +008e24e4 l F .text 00000054 _cvt +008e2538 l F .text 00000445 cmnos_vprintf +00500a30 l O .bss 00000004 g_tasklet_ctx_121 +00500a44 l O .bss 00000010 uart_ctl_blk_122 +008e2f1c l F .text 00000040 _uart_hwinit +008e33b0 l F .text 00000012 usbfifo_get_command_buf +008e33c4 l F .text 00000036 usbfifo_recv_command +008e33fc l F .text 0000001e usbfifo_get_event_buf +008e341c l F .text 00000011 usbfifo_send_event_done +008e351c l F .text 00000007 _HIFusb_get_reserved_headroom +008e3524 l F .text 0000002b enable_rx +008e3550 l F .text 0000001e get_queue_from_pipe +008e3884 l F .text 00000028 vUsb_ep0tx +008e38ac l F .text 00000022 vUsb_ep0rx +008e38d0 l F .text 00000081 vUsbClrEPx +008e3954 l F .text 00000034 bGet_status +008e3988 l F .text 00000023 bClear_feature +008e39ac l F .text 000000d0 bSet_feature +008e3a7c l F .text 0000001f bSet_address +008e3a9c l F .text 0000008f bGet_descriptor +008e3b2c l F .text 00000026 bGet_configuration +008e3b54 l F .text 000000a5 bSet_configuration +008e3bfc l F .text 00000045 bGet_interface +008e3c44 l F .text 0000008d bSet_interface +008e3cd4 l F .text 000000b6 vUsbEP0TxData +008e3d8c l F .text 0000007c vUsbEP0RxData +008e3e08 l F .text 0000005b vUsb_SetupDescriptor +008e3e64 l F .text 000000fd bStandardCommand +008e3f64 l F .text 000000f2 VendorCommand +008e4058 l F .text 00000176 vUsb_ep0setup +008e41d0 l F .text 00000081 cFUSB200Init +008e4254 l F .text 0000001a _usbfifo_enable_event_isr +008e4270 l F .text 00000018 _usbfifo_init +008e4288 l F .text 00000068 vUsb_Reg_Out +008e42f0 l F .text 000000a2 vUsb_Status_In +008e4394 l F .text 00000011 zfResetUSBFIFO +008e43a8 l F .text 00000072 zfTurnOffPower +008e441c l F .text 00000042 zfGenWatchDogEvent +008e4460 l F .text 00000008 zfJumpToBootCode +008e4468 l F .text 000000c6 _usb_rom_task +008e4530 l F .text 00000135 _usb_fw_task +008e4668 l F .text 00000104 _usb_clk_init +008e502c l F .text 00000021 adf_nbuf_tailroom +008e5050 l F .text 00000029 adf_nbuf_push_head +008e507c l F .text 0000002b adf_nbuf_put_tail +008e50a8 l F .text 0000002a adf_nbuf_pull_head +008e50d4 l F .text 00000008 adf_nbuf_len +008e50dc l F .text 00000015 adf_nbuf_peek_header +008e50f4 l F .text 00000007 adf_nbuf_get_priv +008e5974 l F .text 0000004b swapData +008e59d8 l F .text 00000078 config_queue +008e5ca8 l F .text 00000047 relinkUSBDescToVdesc +008e5e60 l F .text 00000015 mii_reg_write_32 +00000000 l df *ABS* 00000000 exc-c-wrapper-handler.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/windowspill_asm.S +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/strcmp.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/strcpy.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/strlen.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/strncpy.S +008e6804 l .text 00000000 __strncpy_aux +00000000 l df *ABS* 00000000 _vectors.S +00000000 l df *ABS* 00000000 debug-vector.S +00000000 l df *ABS* 00000000 double-vector.S +00000000 l df *ABS* 00000000 kernel-vector.S +00000000 l df *ABS* 00000000 nmi-vector.S +00000000 l df *ABS* 00000000 window-vectors.S +00000000 l df *ABS* 00000000 int-vector.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 int-vector.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 interrupt-table.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 exc-unhandled.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 exc-return.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 exc-table.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/clock.S +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/cache_asm.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/cache_asm.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/cache_asm.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/cache_asm.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/int_asm.S +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/int_asm.S +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/int_asm.S +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memcpy.S +008e6b24 l .text 00000000 __memcpy_aux +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S +008e6e20 l .text 00000000 __memset_aux +00500abc g O .bss 00000002 u16TxRxCounter +008e1cdc g F .text 0000000c cmnos_refclk_speed_get +00000000 *UND* 00000000 _write_usb_desc_to_eeprom +008e235c g F .text 00000051 cmnos_misaligned_load_handler +008e37e8 g F .text 0000009c HIFusb_DescTraceDump +004e87b4 g O .rodata 00000001 Xthal_have_loops +008e6678 g F .text 00000000 strcpy +008e5964 g F .text 00000010 _DMAengine_init_tx_queue +008e1604 g F .text 00000010 athos_interrupt_handler +008e337c g F .text 00000032 hif_pci_api_install +008e6990 g F .text 00000000 xthal_set_intenable +004e87e6 g O .rodata 00000001 Xthal_have_mimic_cacheattr +004e87e8 g O .rodata 00000001 Xthal_mmu_rings +004e87b3 g O .rodata 00000001 Xthal_have_density +00500b4d g O .bss 00000001 Xthal_have_clamps +008e1ce8 g F .text 00000005 cmnos_uart_frequency +00500ad0 g O .bss 00000002 u8UsbInterfaceValue +008e31e8 g F .text 00000028 __pci_reap_recv +008e29bc g F .text 0000000f cmnos_printf_module_install +008e2fd4 g F .text 00000014 __pci_get_tx_eng +008e21b8 g F .text 0000003e cmnos_intr_mask_inum +004e9054 g *ABS* 00000000 _bss_table_end +00000000 *UND* 00000000 __adf_net_register_drv +008e0000 g .ResetVector.text 00000000 _ResetVector +fff00ff0 g *ABS* 00000000 _memmap_cacheattr_unused_mask +008e56f4 g F .text 00000086 HTCControlSvcProcessMsg +008e0b26 g *ABS* 00000000 _Level3InterruptVector_text_end +004e8720 g O .rodata 00000018 _rom_store_table +00500b70 g O .bss 00000001 Xthal_num_xlmi +008e2298 g F .text 0000005f cmnos_intr_invoke_isr +004e87a8 g O .rodata 00000004 Xthal_rev_no +004e87b1 g O .rodata 00000001 Xthal_memory_order +008e2a50 g F .text 0000003c cmnos_romp_decode +00500000 g .dport0.data 00000000 _indir_tbl +008e1e24 g F .text 00000037 cmnos_eep_is_exist +00500b48 g O .bss 00000004 Xthal_release_internal +004e8834 g O .rodata 00000004 Xthal_xlmi_size +008e4f4c g F .text 00000014 _vbuf_free_vbuf +008e6264 g F .text 00000023 buf_pool_module_install +00500b6a g O .bss 00000001 Xthal_itlb_way_bits +004e8718 g *ABS* 00000000 _lit4_end +00500a2c g O .bss 00000004 patch_start +008e1cf0 g F .text 00000005 cmnos_sysclk_change +00021001 g *ABS* 00000000 _memmap_cacheattr_wt_base +008e24b8 g F .text 0000002a cmnos_write_char +008e0c00 g *ABS* 00000000 _DebugExceptionVector_literal_end +00500ae0 g O .bss 00000004 u8String10Descriptor +008e6c5c g F .text 000001c2 memmove +008e6e94 g *ABS* 00000000 _text_end +004e87bc g O .rodata 00000001 Xthal_have_highlevel_interrupts +008e367c g F .text 0000002a _HIFusb_return_recv_buf +008e4d7c g F .text 00000029 __dma_lib_rx_init +008e18c8 g F .text 00000033 turn_off_rc +008e0f26 g *ABS* 00000000 _DoubleExceptionVector_text_end +004e87dc g O .rodata 00000004 Xthal_hw_min_version_major +008e36c0 g F .text 00000010 _HIFusb_is_pipe_supported +004e8000 g *ABS* 00000000 _lit4_start +00500b6b g O .bss 00000001 Xthal_itlb_arf_ways +004e9054 g *ABS* 00000000 _dram0_literal_end +004e8840 g O .rodata 00000020 Xthal_intlevel +00500ad4 g O .bss 00000002 u16FirmwareComplete +00000000 g *ABS* 00000000 _xtos_vectors_ref_ +008e167c g F .text 00000032 athos_init +008e57e4 g F .text 0000002d AdjustCreditThreshold +00500700 g O .data 00000004 _putc +008e247c g F .text 0000000b cmnos_rom_version_get +004e9054 g *ABS* 00000000 _dram0_literal_start +00500a38 g O .bss 0000000c wdt_ctrl +008e2354 g F .text 00000005 cmnos_mac_reset +004e87b9 g O .rodata 00000001 Xthal_have_exceptions +008e6e94 g .text 00000000 _etext +008e4f60 g F .text 00000014 vbuf_module_install +00000000 *UND* 00000000 wlan_pci_register_drv +004e87d4 g O .rodata 00000004 Xthal_hw_release_major +008e2d90 g F .text 00000028 cmnos_wdt_init +00500b44 g O .bss 00000004 Xthal_release_minor +004e87fc g O .rodata 00000004 Xthal_instrom_vaddr +00500708 g O .data 0000000c pci_sc +004e8804 g O .rodata 00000004 Xthal_instrom_size +008e4848 g F .text 0000000f usbfifo_module_install +008e300c g F .text 00000016 __pci_enable +008e5114 g F .text 000000e0 _HTC_Init +008e0ce4 g *ABS* 00000000 _NMIExceptionVector_text_start +004e8830 g O .rodata 00000004 Xthal_xlmi_paddr +008e3430 g F .text 00000053 _HIFusb_init +004e0100 g O .dport0.usb_in_rom 00000012 UsbDeviceDescriptor +00500954 g O .bss 00000004 allocram_current_addr +008e2d74 g F .text 0000001c cmnos_wdt_disable +008e6b64 g F .text 00000000 memcpy +008e5eb0 g F .text 00000018 fwd_retbuf_handler +00000000 *UND* 00000000 _need_user_vector_ +008e0e37 g *ABS* 00000000 _UserExceptionVector_text_end +008e6920 g F .text 00000000 _xtos_unhandled_interrupt +004e87e9 g O .rodata 00000001 Xthal_mmu_ca_bits +00500b64 g O .bss 00000001 Xthal_have_xlt_cacheattr +004e9054 g *ABS* 00000000 _rodata_end +00500b50 g O .bss 00000001 Xthal_have_speculation +008e4f2c g F .text 0000001e _vbuf_alloc_vbuf +008e2b50 g F .text 0000000c cmnos_tasklet_init +008e5924 g F .text 00000040 _DMAengine_init_rx_queue +00500b04 g O .bss 00000008 g_vdescCtx +008e32f8 g F .text 0000000e __pci_is_pipe_supported +008e615c g F .text 0000003d magpie_mdio_copy_bytes +004e87e7 g O .rodata 00000001 Xthal_have_tlbs +008e0ce7 g *ABS* 00000000 _NMIExceptionVector_text_end +00500ad8 g O .bss 00000004 u8UsbDeviceDescriptor +008e0900 g .WindowVectors.text 00000000 _WindowOverflow12 +008e0c20 g *ABS* 00000000 _DebugExceptionVector_text_start +00500970 g O .bss 00000004 pll_ctrl_setting_5ghz +008e6960 g F .text 00000000 xthal_set_ccompare +008e2fe8 g F .text 00000023 __pci_get_rx_eng +008e6a4c g F .text 00000050 __udivsi3 +008e2e74 g F .text 0000002c _uart_char_put_nowait +004e8800 g O .rodata 00000004 Xthal_instrom_paddr +008e2fa0 g F .text 0000000a __pci_reg_write +008e16e8 g F .text 000000a3 read_usb_conf +008e0800 g *ABS* 00000000 _WindowVectors_text_start +008e520c g F .text 00000052 _HTC_Ready +008e2c04 g F .text 0000000f cmnos_timer_setfn +008e2dd0 g F .text 00000028 cmnos_wdt_module_install +008e4858 g F .text 0000009d cmnos_usb_module_install +00500950 g *ABS* 00000000 _bss_start +008e6928 g .text 00000000 _xtos_unhandled_exception +00500400 g *ABS* 00000000 _dram0_data_end +00500b67 g O .bss 00000001 Xthal_mmu_asid_kernel +008e5260 g F .text 0000007d ReturnBuffers +008e63ac g .text 00000000 _xtos_cause3_handler +00500780 g O .data 0000003c u8OtherSpeedConfigDescriptorEX +004e87b2 g O .rodata 00000001 Xthal_have_windowed +00500ad2 g O .bss 00000002 u8UsbInterfaceAlternateSetting +00500950 g *ABS* 00000000 __XT_EXCEPTION_DESCS__ +008e22f8 g F .text 0000001e cmnos_intr_module_install +008e2188 g F .text 00000005 cmnos_intr_dummy +008e2ed4 g F .text 0000001d _uart_str_out +22221221 g *ABS* 00000000 _memmap_cacheattr_wb_allvalid +00500a54 g O .bss 00000044 g_hifUSBCtx +008e2c58 g F .text 00000030 cmnos_timer_disarm +008e1c98 g F .text 00000014 cmnos_allocram_module_install +008e2b88 g F .text 00000031 cmnos_tasklet_disable +008e178c g F .text 000000d2 set_pci_conf +008e3308 g F .text 0000000e __pci_get_max_msg_len +00000000 *UND* 00000000 send_buffer_via_dma +008e1000 g *ABS* 00000000 _text_start +00500958 g O .bss 00000004 allocram_remaining_bytes +008e4eb8 g F .text 00000037 dma_lib_module_install +008e1614 g F .text 00000066 athos_interrupt_init +008e2e40 g F .text 00000007 _uart_char_get_nothing +008e2340 g F .text 00000011 cmnos_system_reset +00021001 g *ABS* 00000000 _memmap_cacheattr_wb_base +008e5328 g F .text 0000015a _HTC_SendMsg +008e0b20 g *ABS* 00000000 _Level3InterruptVector_text_start +008e4fb0 g F .text 00000018 _vdesc_alloc_desc +008e2b08 g F .text 00000019 cmnos_romp_module_install +00500b69 g O .bss 00000001 Xthal_mmu_sr_bits +008e2ce4 g F .text 0000002b cmnos_wdt_last_boot +008e4e50 g F .text 0000001b __dma_reap_recv +008e2a9c g F .text 00000061 cmnos_romp_download +005007c0 g O .data 00000090 eng_q +004e87f9 g O .rodata 00000001 Xthal_num_ccompare +008e0ce0 g *ABS* 00000000 _NMIExceptionVector_literal_end +008e1548 g F .text 0000002b generic_hif_module_install +fff22ff2 g *ABS* 00000000 _memmap_cacheattr_bp_strict +0050096c g O .bss 00000004 pll_ctrl_setting_24ghz +008e591c g F .text 00000005 _DMAengine_init +008e3210 g F .text 0000009f __pci_isr_handler +008e4934 g F .text 0000001e mUsbFIFOConfig +008e5d2c g F .text 00000092 zfDmaReclaimPacket +22221221 g *ABS* 00000000 _memmap_cacheattr_wt_trapnull +008e36e4 g F .text 000000ad _HIFusb_isr_handler +008e62a8 g F .text 00000055 _buf_pool_static_create_pool +008e0d40 g .KernelExceptionVector.text 00000000 _KernelExceptionVector +00500964 g O .bss 00000004 clock_info +008e2b00 g F .text 00000005 cmnos_romp_init +008e0e00 g *ABS* 00000000 _UserExceptionVector_literal_start +008e16b0 g F .text 00000036 _read_usb_desc +008e0800 g .WindowVectors.text 00000000 _WindowOverflow4 +008e4cb8 g F .text 0000000a __dma_reg_write +00000000 g *ABS* 00000000 xthals_release_minor +008e32b0 g F .text 0000002a __pci_xmit_buf +00500400 g .data 00000000 _xtos_exc_handler_table +008e0d40 g *ABS* 00000000 _KernelExceptionVector_text_start +008e3110 g F .text 00000053 __pci_init +00500640 g O .data 000000b8 basic_ROM_module_table +008e5ffc g F .text 000000c2 magpie_mdio_boot_init +008e2e48 g F .text 0000002c _uart_char_put +00500b78 g *ABS* 00000000 _bss_end +008e13f8 g F .text 00000030 Magpie_fatal_exception_handler +008e6428 g .text 00000000 xthal_window_spill_nw +008e1240 g .text 00000000 _Level2FromVector +008e62a0 g F .text 00000005 _buf_pool_static_shutdown +00500b18 g O .bss 0000002c g_poolCtx +008e0840 g .WindowVectors.text 00000000 _WindowUnderflow4 +00500978 g O .bss 00000002 eep_state +004e87b0 g O .rodata 00000001 Xthal_num_aregs_log2 +008e4da8 g F .text 00000028 __dma_hard_xmit +00500500 g O .data 00000004 _xtos_enabled +00500500 g .data 00000000 _xtos_intstruct +004e8828 g O .rodata 00000004 Xthal_dataram_size +008e567c g F .text 00000075 HTCProcessConfigPipeMsg +008e6300 g F .text 00000022 _buf_pool_static_alloc_buf +008e096a g *ABS* 00000000 _WindowVectors_text_end +00500aa4 g O .bss 00000010 usbFifoConf +004e8824 g O .rodata 00000004 Xthal_dataram_paddr +00500ab8 g O .bss 00000004 pu8DescriptorEX +00500400 g *ABS* 00000000 _dram0_data_start +008e2ec0 g F .text 00000005 _uart_task +004e0100 g .dport0.usb_in_rom 00000000 _reserved_rom_data_end +004e87a0 g O .rodata 00000004 Xthal_release_major +008e0940 g .WindowVectors.text 00000000 _WindowUnderflow12 +008e3328 g F .text 0000000d __pci_get_def_pipe +22222222 g *ABS* 00000000 _memmap_cacheattr_bp_allvalid +008e1174 g .text 00000000 _xtos_l1int_handler +004e8820 g O .rodata 00000004 Xthal_dataram_vaddr +004e87e0 g O .rodata 00000004 Xthal_hw_max_version_major +004e87f6 g O .rodata 00000001 Xthal_num_instram +22221221 g *ABS* 00000000 _memmap_cacheattr_wt_allvalid +008e6970 g F .text 00000000 xthal_get_ccompare +008e5494 g F .text 00000013 _HTC_GetReservedHeadroom +004e01c0 g O .dport0.usb_in_rom 00000018 String20Descriptor +008e1da0 g F .text 00000057 cmnos_eeprom_write_hword +00500950 g *ABS* 00000000 __XT_EXCEPTION_DESCS_END__ +00500b65 g O .bss 00000001 Xthal_have_cacheattr +004e87f5 g O .rodata 00000001 Xthal_dtlb_ways +008e21f8 g F .text 00000039 cmnos_intr_unmask_inum +00500704 g O .data 00000004 patch_addr +008e1d00 g F .text 00000005 cmnos_wlan_band_set +00500ac8 g O .bss 00000004 eUsbCxCommand +00000000 *UND* 00000000 WMI_service_module_install +008e6324 g F .text 00000010 _buf_pool_static_alloc_buf_align +008e6a9c g F .text 0000003d __umodsi3 +00500b6d g O .bss 00000001 Xthal_dtlb_arf_ways +004e01b0 g O .dport0.usb_in_rom 00000010 String10Descriptor +00500400 g *ABS* 00000000 _dport0_data_start +008e29e4 g F .text 00000069 _read_rom_patch +008e5a50 g F .text 00000057 _DMAengine_config_rx_queue +00500af0 g O .bss 00000006 UsbStatus +004e0120 g O .dport0.usb_in_rom 0000003c u8HSConfigDescriptor01 +008e6958 g F .text 00000000 xthal_get_ccount +008e6e94 g .text 00000000 _text_end_magic +008e2318 g F .text 00000005 cmnos_mem_init +0053f7f0 g .dport0.stack 00000000 _stack_sentry +008e2c14 g F .text 00000042 cmnos_timer_arm +008e5c58 g F .text 00000050 dma_engine_module_install +008e63d4 g .text 00000000 _GeneralException +008e2980 g F .text 00000033 cmnos_printf +008e619c g F .text 0000001f fw_compute_cksum +008e216c g F .text 00000019 cmnos_eep_module_install +0d02230f g *ABS* 00000000 xthals_hw_configid1 +008e6428 g .text 00000000 xthal_spill_registers_into_stack_nw +00000000 *UND* 00000000 hif_module_install +00500b6c g O .bss 00000001 Xthal_dtlb_way_bits +008e57bc g F .text 00000027 HTCSendDoneHandler +008e5b70 g F .text 0000001e _DMAengine_has_compl_packets +008e31a8 g F .text 00000014 __pci_reg_callback +008e497c g F .text 00000024 mUsbEPMxPtSzLow +004e87e4 g O .rodata 00000001 Xthal_have_spanning_way +008e5524 g F .text 0000005e HTCCheckAndSendCreditReport +008e1000 g .text 00000000 _start +008e00de g *ABS* 00000000 _ResetVector_text_end +00500a98 g O .bss 0000000c ControlCmd +00500400 g *ABS* 00000000 _data_start +008e6950 g F .text 00000000 _xtos_p_none +00500ace g O .bss 00000002 u8UsbConfigValue +00500980 g O .bss 00000004 cmnos_enabled_interrupts +008e2ec8 g F .text 0000000a _uart_status +008e2db8 g F .text 00000018 cmnos_wdt_task +008e5484 g F .text 00000005 _HTC_PauseRecv +008e1d44 g F .text 00000026 cmnos_tick +008e245c g F .text 0000001f cmnos_is_host_present +004e881c g O .rodata 00000004 Xthal_datarom_size +004e87b8 g O .rodata 00000001 Xthal_have_mul16 +008e1df8 g F .text 0000002b cmnos_eeprom_read_hword +008e48f8 g F .text 0000001c mUsbEPMap +00500b60 g O .bss 00000004 Xthal_hw_release_internal +00000000 *UND* 00000000 __adf_os_setup_intr +004e87c0 g O .rodata 00000001 Xthal_have_s32c1i +008e4fc8 g F .text 00000008 _vdesc_get_hw_desc +008e6774 g F .text 0000008e strncmp +008e0b00 g *ABS* 00000000 _Level3InterruptVector_literal_end +004e87f4 g O .rodata 00000001 Xthal_itlb_ways +008e1d08 g F .text 00000005 cmnos_pll_init +008e2b2c g F .text 00000023 cmnos_string_module_install +008e2d2c g F .text 00000028 cmnos_wdt_set +008e0d00 g *ABS* 00000000 _KernelExceptionVector_literal_end +008e1ebc g F .text 00000045 cmnos_eep_read +004e87d0 g O .rodata 00000004 Xthal_hw_configid1 +008e683c g F .text 00000000 strncpy +008e0800 g *ABS* 00000000 _memmap_vecbase_reset +008e0a20 g .Level2InterruptVector.text 00000000 _Level2Vector +008e1cac g F .text 00000020 cmnos_delay_us +004e87bb g O .rodata 00000001 Xthal_have_interrupts +00500b0c g O .bss 0000000c fwd_sc +008e1cf8 g F .text 00000005 cmnos_clockregs_init +008e0f20 g *ABS* 00000000 _DoubleExceptionVector_text_start +008e6334 g F .text 00000013 _buf_pool_static_free_buf +008e1468 g F .text 0000000a athos_restore_intrlvl +fff21ff1 g *ABS* 00000000 _memmap_cacheattr_wb_strict +008e18fc g F .text 00000318 bootentry +008e12f4 g .text 00000000 _Level3FromVector +004e87bf g O .rodata 00000001 Xthal_have_release_sync +008e6348 g F .text 00000061 _xtos_set_exception_handler +004e87d8 g O .rodata 00000004 Xthal_hw_release_name +005006fc g O .data 00000004 assprint +0050095c g O .bss 00000004 cticks +008e2b6c g F .text 00000019 cmnos_tasklet_schedule +008e2df8 g F .text 0000003e _uart_init +00500400 g .dport0.data 00000000 _reserved_data_end +008e5010 g F .text 00000019 vdesc_module_install +008e0f00 g *ABS* 00000000 _DoubleExceptionVector_literal_start +008e1ccc g F .text 0000000d cmnos_milliseconds +008e3338 g F .text 00000041 hif_pci_module_install +008e6adc g F .text 00000045 memcmp +008e2f5c g F .text 00000037 cmnos_uart_module_install +008e2ea0 g F .text 00000020 _uart_char_get +00500b58 g O .bss 00000004 Xthal_hw_min_version_minor +00500950 g *ABS* 00000000 _data_end +008e4e28 g F .text 00000026 __dma_xmit_done +008e102c g .text 00000000 _xtos_alloca_handler +008e1000 g *ABS* 00000000 _iram0_text_end +004e880c g O .rodata 00000004 Xthal_instram_paddr +004e8718 g *ABS* 00000000 _ResetVector_literal_end +008e5b68 g F .text 00000005 _DMAengine_flush_xmit +008e2cc4 g F .text 0000001e cmnos_timer_module_install +004e9044 g *ABS* 00000000 __XT_EXCEPTION_TABLE__ +008e11e4 g F .text 0000004c _xtos_set_interrupt_handler_arg +004e87c2 g O .rodata 00000001 Xthal_have_pif +004e87b6 g O .rodata 00000001 Xthal_have_minmax +008e5b90 g F .text 0000002f _DMAengine_reap_recv_buf +008e5cf0 g F .text 00000039 zfDmaGetPacket +008e3164 g F .text 0000003a __pci_cfg_pipe +008e4b7c g F .text 0000012f vUsbFIFO_EPxCfg_FS +00500ae4 g O .bss 00000004 u8String20Descriptor +00500508 g .data 00000000 _xtos_interrupt_table +00500b4f g O .bss 00000001 Xthal_have_fp +008e61bc g F .text 000000a8 mdio_get_fw_image +008e2be4 g F .text 0000001e cmnos_tasklet_module_install +008e2bbc g F .text 00000028 cmnos_tasklet_run +008e6288 g F .text 00000016 _buf_pool_static_init +008e5ec8 g F .text 0000002e fwd_tgt_process_last +008e0020 g .ResetVector.text 00000000 _ResetHandler +fff21ff1 g *ABS* 00000000 _memmap_cacheattr_wt_strict +008e6e48 g F .text 00000000 memset +008e63b4 g .text 00000000 _xtos_c_wrapper_handler +008e1c14 g F .text 0000001e main +00500b68 g O .bss 00000001 Xthal_mmu_ring_bits +008e5ef8 g F .text 000000df fwd_tgt_recv +008e5bc0 g F .text 00000036 _DMAengine_reap_xmited_buf +008e5bf8 g F .text 0000005e _DMAengine_desc_dump +008e51f4 g F .text 00000005 _HTC_Shutdown +004e0100 g .dport0.usb_in_rom 00000000 _reserved_rom_data_start +008e4cc4 g F .text 00000020 __dma_set_base +005005a0 g .data 00000000 _xtos_interrupt_mask_table +008e242c g F .text 0000002d cmnos_get_kbhit +008e0a20 g *ABS* 00000000 _Level2InterruptVector_text_start +008e0c20 g .DebugExceptionVector.text 00000000 _DebugExceptionVector +00500ae8 g O .bss 00000004 u8String30Descriptor +008e1d6c g F .text 00000032 cmnos_clock_module_install +008e6114 g F .text 00000045 mdio_read_block +008e0ce4 g .NMIExceptionVector.text 00000000 _NMIExceptionVector +008e2fac g F .text 00000027 __pci_get_pipe +00500ac4 g O .bss 00000004 eUsbCxFinishAction +004e87ac g O .rodata 00000004 Xthal_num_aregs +004e87bd g O .rodata 00000001 Xthal_have_nmi +008e5dc0 g F .text 0000009f zfDmaPutPacket +008e3318 g F .text 00000007 __pci_get_reserved_headroom +008e54ec g F .text 00000015 HTCFreeMsgBuffer +008e4d2c g F .text 0000004d __dma_lib_rx_config +004e87c8 g O .rodata 00000004 Xthal_build_unique_id +004e8814 g O .rodata 00000004 Xthal_datarom_vaddr +00500850 g .data 00000000 _xtos_c_handler_table +008e189c g F .text 0000002c pci_gmac_bootload +00500504 g O .data 00000004 _xtos_vpri_enabled +008e0b20 g .Level3InterruptVector.text 00000000 _Level3Vector +008e0d46 g *ABS* 00000000 _KernelExceptionVector_text_end +008e6998 g F .text 00000068 __divsi3 +008e0f00 g *ABS* 00000000 _DoubleExceptionVector_literal_end +008e1104 g .text 00000000 _xtos_syscall_handler +008e1192 g .text 00000000 _LevelOneInterrupt +008e36d0 g F .text 00000012 _HIFusb_get_max_msg_len +008e6560 g F .text 00000000 strcmp +0053f7f0 g .dport0.stack 00000000 _reserved_stack_start +004e8818 g O .rodata 00000004 Xthal_datarom_paddr +008e2c94 g F .text 0000002d cmnos_timer_handler +004e8718 g *ABS* 00000000 _dram0_rodata_start +004e87e5 g O .rodata 00000001 Xthal_have_identity_map +008e36b0 g F .text 00000005 _HIFusb_pause_recv +0053fff0 g .dport0.stack 00000000 _reserved_stack_end +008e30d8 g F .text 00000035 __pci_boot_init +008e3570 g F .text 000000ab _HIFusb_config_pipe +008e31bc g F .text 0000002c __pci_reap_xmitted +004e8718 g *ABS* 00000000 _ResetVector_literal_start +008e2d10 g F .text 0000001a cmnos_wdt_reset +008e36a8 g F .text 00000005 _HIFusb_set_recv_bufsz +00500b4e g O .bss 00000001 Xthal_have_mac16 +008e2488 g F .text 0000002d cmnos_misc_module_install +008e0e00 g *ABS* 00000000 _UserExceptionVector_literal_end +004e0260 g .dport0.usb_in_rom 00000000 _data_start_in_rom +008e5318 g F .text 00000010 _HTC_ReturnBuffers +008e1574 g F .text 0000008f athos_indirection_table_install +005006f8 g O .data 00000004 assloop +008e6980 g F .text 00000000 xthal_get_intenable +004e87ba g O .rodata 00000001 Xthal_xea_version +00500a28 g O .bss 00000004 current_dump +008e4ce4 g F .text 00000048 __dma_lib_tx_init +004e87ec g O .rodata 00000004 Xthal_mmu_max_pte_page_size +008e32dc g F .text 0000001b __pci_return_recv +008e2b5c g F .text 0000000f cmnos_tasklet_init_task +008e0c00 g *ABS* 00000000 _DebugExceptionVector_literal_start +00500990 g O .bss 00000098 cmnos_isr_info +008e4954 g F .text 00000027 mUsbEPMxPtSzHigh +008e49ec g F .text 00000190 vUsbFIFO_EPxCfg_HS +008e0ce0 g *ABS* 00000000 _NMIExceptionVector_literal_start +008e1f04 g F .text 00000268 cmnos_eep_init +00500ac0 g O .bss 00000004 u8ConfigDescriptorEX +004e8750 g O .rodata 00000050 cmnos_clocking_table +008e0e20 g *ABS* 00000000 _UserExceptionVector_text_start +00500acc g O .bss 00000002 UsbChirpFinish +008e581c g F .text 000000ff HTCMsgRecvHandler +008e37a4 g F .text 00000041 hif_usb_module_install +00500b4c g O .bss 00000001 Xthal_have_booleans +008e1860 g F .text 0000003b bootload +00500000 g .dport0.data 00000000 _reserved_data_start +008e3320 g F .text 00000005 __pci_shutdown +22221221 g *ABS* 00000000 _memmap_cacheattr_wb_trapnull +008e348c g F .text 00000014 _HIFusb_register_callback +008e6938 g .text 00000000 _xtos_return_from_exc +008e4e6c g F .text 00000028 __dma_return_recv +008e4914 g F .text 0000001e mUsbFIFOMap +004e9044 g *ABS* 00000000 _bss_table_start +008e0a00 g *ABS* 00000000 _Level2InterruptVector_literal_end +00500b66 g O .bss 00000001 Xthal_mmu_asid_bits +008e12f1 g .text 00000000 _Level2HandlerLabel +008e23b0 g F .text 0000006c cmnos_assfail +008e29cc g F .text 00000018 _patch_dump +004e87be g O .rodata 00000001 Xthal_have_prid +008e4cac g F .text 0000000a __dma_reg_read +004e87f0 g O .rodata 00000004 Xthal_mmu_min_pte_page_size +008e13a2 g .text 00000000 _Level3HandlerLabel +008e3484 g F .text 00000005 _HIFusb_shutdown +008e2c88 g F .text 0000000c cmnos_timer_init +008e4dd0 g F .text 0000001b __dma_reap_xmitted +008e2a8c g F .text 0000000d cmnos_romp_install +008e3794 g F .text 0000000f _HIFusb_get_default_pipe +004e8810 g O .rodata 00000004 Xthal_instram_size +00500b6e g O .bss 00000001 Xthal_num_instrom +c280dbff g *ABS* 00000000 xthals_hw_configid0 +008e54a8 g F .text 00000041 htc_module_install +00500400 g *ABS* 00000000 _dport0_data_end +0053fff0 g .dport0.stack 00000000 __stack +008e241c g F .text 00000005 cmnos_report_failure_to_host +008e2190 g F .text 00000026 cmnos_intr_init +008e0b00 g *ABS* 00000000 _Level3InterruptVector_literal_start +00500af8 g O .bss 0000000c g_vbufCtx +008e2f94 g F .text 0000000a __pci_reg_read +008e0000 g *ABS* 00000000 _ResetVector_text_start +004e8720 g *ABS* 00000000 _rodata_start +008e0f20 g .DoubleExceptionVector.text 00000000 _DoubleExceptionVector +008e60c0 g F .text 00000039 magpie_mdio_wait_for_lock +00500bf8 g .bss 00000000 _end +008e34a0 g F .text 0000007a _HIFusb_start +008e2424 g F .text 00000005 cmnos_target_id_get +00500720 g O .data 00000006 TestPatn0 +008e13a4 g F .text 00000053 post +008e4dec g F .text 00000039 __dma_flush_xmit +008e4f74 g F .text 0000003b _vdesc_init +00500b54 g O .bss 00000004 Xthal_hw_release_minor +008e5fd8 g F .text 00000022 magpie_mdio_module_install +008e1000 g *ABS* 00000000 _iram0_text_start +008e5e78 g F .text 00000038 fwd_init +008e577c g F .text 0000003f HTCControlSvcProcessSendComplete +008e1c44 g F .text 00000030 cmnos_allocram +008e0880 g .WindowVectors.text 00000000 _WindowOverflow8 +008e1230 g F .text 00000010 _xtos_set_interrupt_handler +008e59c0 g F .text 00000017 _DMAengine_return_recv_buf +008e5504 g F .text 0000001f HTCAllocMsgBuffer +008e51fc g F .text 0000000d _HTC_RegisterService +004e882c g O .rodata 00000004 Xthal_xlmi_vaddr +008e361c g F .text 0000005e _HIFusb_send_buffer +00500ab4 g O .bss 00000004 fwCheckSum +008e29b4 g F .text 00000005 cmnos_printf_init +008e5584 g F .text 000000f8 HTCProcessConnectMsg +008e6988 g F .text 00000000 xthal_get_interrupt +008e2320 g F .text 0000001e cmnos_mem_module_install +008e2234 g F .text 00000064 cmnos_intr_attach_isr +004e87b5 g O .rodata 00000001 Xthal_have_nsa +008e653c g F .text 00000000 xthal_window_spill +00500b5c g O .bss 00000004 Xthal_hw_max_version_minor +004e87f8 g O .rodata 00000001 Xthal_have_ccount +004e87cc g O .rodata 00000004 Xthal_hw_configid0 +008e6a00 g F .text 00000049 __modsi3 +008e1c74 g F .text 00000021 cmnos_allocram_debug +004e87c4 g O .rodata 00000002 Xthal_num_writebuffer_entries +008e36b8 g F .text 00000005 _HIFusb_resume_recv +0050097a g O .bss 00000002 eep_exist +004e0160 g O .dport0.usb_in_rom 0000003c u8FSConfigDescriptor01 +22221221 g *ABS* 00000000 _memmap_cacheattr_reset +00000000 *UND* 00000000 download_write_flag +004e87a4 g O .rodata 00000004 Xthal_release_name +22222222 g *ABS* 00000000 _memmap_cacheattr_bp_trapnull +008e0c26 g *ABS* 00000000 _DebugExceptionVector_text_end +008e08c0 g .WindowVectors.text 00000000 _WindowUnderflow8 +008e0a26 g *ABS* 00000000 _Level2InterruptVector_text_end +008e50fc g F .text 00000017 HTC_AssembleBuffers +008e1c34 g F .text 00000010 cmnos_allocram_init +008e548c g F .text 00000005 _HTC_ResumeRecv +008e6988 g F .text 00000000 xthal_get_intread +008e0e20 g .UserExceptionVector.text 00000000 _UserExceptionVector +008e31a0 g F .text 00000005 __pci_start +00500b6f g O .bss 00000001 Xthal_num_datarom +008e1000 g .text 00000000 _stext +008e1d10 g F .text 00000033 cmnos_clock_init +008e6710 g F .text 00000000 strlen +008e5aa8 g F .text 000000be _DMAengine_xmit_buf +008e4ef0 g F .text 0000003b _vbuf_init +00500968 g O .bss 00000004 cmnos_skip_pll_init +008e2b24 g F .text 00000005 cmnos_string_init +008e60fc g F .text 00000016 magpie_mdio_release_lock +00500adc g O .bss 00000004 u8String00Descriptor +008e1454 g F .text 0000000b athos_block_all_intrlvl +008e52e0 g F .text 00000037 _HTC_ReturnBuffersList +00500a34 g O .bss 00000004 timer_list +00022002 g *ABS* 00000000 _memmap_cacheattr_bp_base +008e476c g F .text 000000d9 _usb_init +008e49a0 g F .text 0000004a mUsbEPinHighBandSet +004e01a0 g O .dport0.usb_in_rom 00000004 String00Descriptor +008e0d00 g *ABS* 00000000 _KernelExceptionVector_literal_start +004e8718 g *ABS* 00000000 _dram0_rodata_end +00500400 g *ABS* 00000000 _dport0_bss_start +004e8808 g O .rodata 00000004 Xthal_instram_vaddr +008e3024 g F .text 000000b4 __pci_reset +008e1460 g F .text 00000008 athos_unblock_all_intrlvl +008e5814 g F .text 00000005 RedistributeCredit +00500400 g *ABS* 00000000 _dport0_bss_end +004e87f7 g O .rodata 00000001 Xthal_num_dataram +00500730 g O .data 00000034 TestPatn1 +008e1e5c g F .text 00000060 cmnos_eep_write +008e0a00 g *ABS* 00000000 _Level2InterruptVector_literal_start +00500960 g O .bss 00000004 curr_band +00001b62 g *ABS* 00000000 xthals_release_major +008e2d54 g F .text 0000001e cmnos_wdt_enable +004e01e0 g O .dport0.usb_in_rom 0000000c String30Descriptor +008e4e94 g F .text 00000023 __dma_recv_pkt +008e1143 g .text 00000000 _SyscallException +008e2e38 g F .text 00000005 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00000000 ...@....@....... + 4e01a0 03040409 00000000 00000000 00000000 ................ + 4e01b0 03100041 00540048 00450052 004f0053 ...A.T.H.E.R.O.S + 4e01c0 03180055 00530042 0032002e 00300020 ...U.S.B.2...0. + 4e01d0 0057004c 0041004e 00000000 00000000 .W.L.A.N........ + 4e01e0 030c0031 00320033 00340035 ...1.2.3.4.5 +Contents of section .dport0.data: + 500000 00000000 00000000 00000000 00000000 ................ + 500010 00000000 00000000 00000000 00000000 ................ + 500020 00000000 00000000 00000000 00000000 ................ + 500030 00000000 00000000 00000000 00000000 ................ + 500040 00000000 00000000 00000000 00000000 ................ + 500050 00000000 00000000 00000000 00000000 ................ + 500060 00000000 00000000 00000000 00000000 ................ + 500070 00000000 00000000 00000000 00000000 ................ + 500080 00000000 00000000 00000000 00000000 ................ + 500090 00000000 00000000 00000000 00000000 ................ + 5000a0 00000000 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00000000 00000000 ................ + 5001b0 00000000 00000000 00000000 00000000 ................ + 5001c0 00000000 00000000 00000000 00000000 ................ + 5001d0 00000000 00000000 00000000 00000000 ................ + 5001e0 00000000 00000000 00000000 00000000 ................ + 5001f0 00000000 00000000 00000000 00000000 ................ + 500200 00000000 00000000 00000000 00000000 ................ + 500210 00000000 00000000 00000000 00000000 ................ + 500220 00000000 00000000 00000000 00000000 ................ + 500230 00000000 00000000 00000000 00000000 ................ + 500240 00000000 00000000 00000000 00000000 ................ + 500250 00000000 00000000 00000000 00000000 ................ + 500260 00000000 00000000 00000000 00000000 ................ + 500270 00000000 00000000 00000000 00000000 ................ + 500280 00000000 00000000 00000000 00000000 ................ + 500290 00000000 00000000 00000000 00000000 ................ + 5002a0 00000000 00000000 00000000 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................ + 5003b0 00000000 00000000 00000000 00000000 ................ + 5003c0 00000000 00000000 00000000 00000000 ................ + 5003d0 00000000 00000000 00000000 00000000 ................ + 5003e0 00000000 00000000 00000000 00000000 ................ + 5003f0 00000000 00000000 00000000 00000000 ................ +Contents of section .rodata: + 4e8720 00500400 00500950 004e0260 00000000 .P...P.P.N.`.... + 4e8730 00000000 00000000 00000000 00000000 ................ + 4e8740 55aa55aa aa55aa55 ffffffff 00000000 U.U..U.U........ + 4e8750 00000000 00989680 00000000 00000000 ................ + 4e8760 00000000 00000001 01312d00 00000000 .........1-..... + 4e8770 00000000 00000000 00000002 02625a00 .............bZ. + 4e8780 00000000 00000000 00000000 ffffffff ................ + 4e8790 00000000 00000000 00000000 00000000 ................ + 4e87a0 00001b62 004e9034 1b620000 00000020 ...b.N.4.b..... + 4e87b0 05010101 01010101 01010201 01010101 ................ + 4e87c0 01010100 00040000 0002230f c280dbff ..........#..... + 4e87d0 0d02230f 000008a2 004e903c 000008a2 ..#......N.<.... + 4e87e0 000008a2 01010101 01040000 0000001d ................ + 4e87f0 0000001d 01010101 01010000 00000000 ................ + 4e8800 00000000 00000000 00800000 00800000 ................ + 4e8810 00400000 00000000 00000000 00000000 .@.............. + 4e8820 00400000 00400000 00400000 00000000 .@...@...@...... + 4e8830 00000000 00000000 00000000 00000000 ................ + 4e8840 01020202 02020202 02020202 02020203 ................ + 4e8850 03030500 00000000 00000000 00000000 ................ + 4e8860 52414d20 6661696c 0a0d0000 46617461 RAM fail....Fata + 4e8870 6c206578 63657074 696f6e20 28256429 l exception (%d) + 4e8880 3a207063 3d307825 78206261 64766164 : pc=0x%x badvad + 4e8890 64723d30 78257820 64756d70 20617265 dr=0x%x dump are + 4e88a0 613d3078 25780a00 2d41312d 0a0d0000 a=0x%x..-A1-.... + 4e88b0 6d697361 6c69676e 65645f6c 6f61640a misaligned_load. + 4e88c0 0d000000 46617461 6c206578 63657074 ....Fatal except + 4e88d0 696f6e20 28256429 3a200970 633d3078 ion (%d): .pc=0x + 4e88e0 2578200a 0d096261 64766164 64723d30 %x ...badvaddr=0 + 4e88f0 78257820 0a0d0964 756d7020 61726561 x%x ...dump area + 4e8900 3d307825 780a0000 09657063 313d3078 =0x%x....epc1=0x + 4e8910 25782c20 65706332 3d307825 782c2065 %x, epc2=0x%x, e + 4e8920 7063333d 30782578 2c206570 63343d30 pc3=0x%x, epc4=0 + 4e8930 7825780a 00000000 30782530 38782c20 x%x.....0x%08x, + 4e8940 30782530 38782c20 30782530 38782c20 0x%08x, 0x%08x, + 4e8950 0a0d0000 202d2025 735f7665 723a2025 .... - %s_ver: % + 4e8960 78202d20 0a0a0d00 61736963 00000000 x - ....asic.... + 4e8970 64696476 69642066 726f6d20 6f776c20 didvid from owl + 4e8980 0a000000 64656661 756c7420 64696476 ....default didv + 4e8990 6964200a 00000000 382e2077 61697420 id .....8. wait + 4e89a0 666f7220 646f776e 6c6f6164 2e2e2e2e for download.... + 4e89b0 200a0d00 32000000 33000000 20332e31 ...2...3... 3.1 + 4e89c0 206e6f20 70617463 680a0d00 20332e31 no patch... 3.1 + 4e89d0 206e6f20 65657020 6f722063 6f727275 no eep or corru + 4e89e0 70740a0d 00000000 20332e31 20534e53 pt...... 3.1 SNS + 4e89f0 543a2065 65702069 6e697420 6661696c T: eep init fail + 4e8a00 6564210a 0d000000 342e2077 64742073 ed!.....4. wdt s + 4e8a10 74617274 0a0d0000 342e2077 61726d20 tart....4. warm + 4e8a20 73746172 740a0d00 342e2063 6f6c6420 start...4. cold + 4e8a30 73746172 740a0d00 352e2068 69662028 start...5. hif ( + 4e8a40 2564290a 00000000 53544152 542e2e2e %d).....START... + 4e8a50 2e0a0000 524f4d3e 3a6d6469 6f20646f ....ROM>:mdio do + 4e8a60 776e6c6f 61642072 65616479 0a000000 wnload ready.... + 4e8a70 362e2053 4e53543a 20686f73 74696620 6. SNST: hostif + 4e8a80 636f7272 7570740a 0d000000 52414d20 corrupt.....RAM + 4e8a90 616c6c6f 63617469 6f6e2028 25642062 allocation (%d b + 4e8aa0 79746573 29206661 696c6564 210a0000 ytes) failed!... + 4e8ab0 414c4c4f 4352414d 20437572 72656e74 ALLOCRAM Current + 4e8ac0 20416464 72203078 25780a00 414c4c4f Addr 0x%x..ALLO + 4e8ad0 4352414d 2052656d 61696e69 6e672042 CRAM Remaining B + 4e8ae0 79746573 2025640a 00000000 2d453132 ytes %d.....-E12 + 4e8af0 2d000000 2d453130 2d000000 2d453131 -...-E10-...-E11 + 4e8b00 2d000000 2d453133 2d000000 4d697361 -...-E13-...Misa + 4e8b10 6c69676e 6564206c 6f61643a 2070633d ligned load: pc= + 4e8b20 30782578 20626164 76616464 723d3078 0x%x badvaddr=0x + 4e8b30 25782064 756d7020 61726561 3d307825 %x dump area=0x% + 4e8b40 780a0000 61737365 7274696f 6e206661 x...assertion fa + 4e8b50 696c6564 3f207063 3d307825 782c206c iled? pc=0x%x, l + 4e8b60 696e653d 25642c20 64756d70 20617265 ine=%d, dump are + 4e8b70 613d3078 25780a00 54617267 65742049 a=0x%x..Target I + 4e8b80 443a2030 78257820 28256429 0a000000 D: 0x%x (%d).... + 4e8b90 44656275 6720496e 666f3a00 30782530 Debug Info:.0x%0 + 4e8ba0 38782000 30313233 34353637 38390000 8x .0123456789.. + 4e8bb0 30313233 34353637 38396162 63646566 0123456789abcdef + 4e8bc0 00000000 30313233 34353637 38394142 ....0123456789AB + 4e8bd0 43444546 00000000 3c6e756c 6c3e0000 CDEF...... + 4e8be0 09737a3a 2025642c 206c643a 2025702c .sz: %d, ld: %p, + 4e8bf0 20666e3a 2025700d 00000000 21696e76 fn: %p.....!inv + 4e8c00 616c6964 2064706f 72742061 64647265 alid dport addre + 4e8c10 73732c20 30782530 38780a0d 00000000 ss, 0x%08x...... + 4e8c20 63702025 64206279 74657320 66726f6d cp %d bytes from + 4e8c30 20307825 30387820 746f2030 78253038 0x%08x to 0x%08 + 4e8c40 78000000 702e6f66 743a2030 78253034 x...p.oft: 0x%04 + 4e8c50 782c2070 2e737a20 3a203078 25303478 x, p.sz : 0x%04x + 4e8c60 0a000000 57616974 696e6720 666f7220 ....Waiting for + 4e8c70 686f7374 20726573 65742e2e 00000000 host reset...... + 4e8c80 72656365 69766564 2e0a0000 42616420 received....Bad + 4e8c90 456e6769 6e65206e 756d6265 720a0000 Engine number... + 4e8ca0 456d7074 79205258 20526561 700a0000 Empty RX Reap... + 4e8cb0 456d7074 79205458 20526561 70200a00 Empty TX Reap .. + 4e8cc0 496e7661 6c696420 50697065 206e756d Invalid Pipe num + 4e8cd0 6265720a 00000000 0a0d093d 3e5b646e ber........=>[dn + 4e8ce0 515d2030 78253038 78200a5b 00000000 Q] 0x%08x .[.... + 4e8cf0 093d3e5b 7570515d 20307825 30387820 .=>[upQ] 0x%08x + 4e8d00 0a5b0000 093d3e5b 68702064 6e515d20 .[...=>[hp dnQ] + 4e8d10 30782530 3878200a 5b000000 093d3e5b 0x%08x .[....=>[ + 4e8d20 6d702064 6e515d20 30782530 3878200a mp dnQ] 0x%08x . + 4e8d30 5b000000 0a0d5b68 7020646e 515d2030 [.....[hp dnQ] 0 + 4e8d40 78253038 782c2000 444d4120 54524143 x%08x, .DMA TRAC + 4e8d50 45203078 25303878 0a0d2020 20205b00 E 0x%08x.. [. + 4e8d60 0a0d5b6d 7020646e 515d2030 78253038 ..[mp dnQ] 0x%08 + 4e8d70 782c2000 0a0d5b64 6e515d20 30782530 x, ...[dnQ] 0x%0 + 4e8d80 38782c20 00000000 0a0a0d5b 7570515d 8x, .......[upQ] + 4e8d90 20307825 3038782c 20000000 2d206375 0x%08x, ...- cu + 4e8da0 73746f6d 20757362 20636f6e 6669670a stom usb config. + 4e8db0 00000000 095b6355 53425f52 45515f44 .....[cUSB_REQ_D + 4e8dc0 4f574e4c 4f41445d 3a203078 25303878 OWNLOAD]: 0x%08x + 4e8dd0 2c202530 32780a0d 00000000 090a0d3d , %02x.........= + 4e8de0 3d3e5b63 5553425f 5245515f 434f4d50 =>[cUSB_REQ_COMP + 4e8df0 5d3a2030 78253038 780a0d00 636b7375 ]: 0x%08x...cksu + 4e8e00 6d3d2578 00000000 56656e64 6f72436d m=%x....VendorCm + 4e8e10 643a2044 6f776e6c 6f616443 6f6d706c d: DownloadCompl + 4e8e20 65746521 0a000000 7a665265 73657455 ete!....zfResetU + 4e8e30 53424649 464f0a0d 00000000 7a665475 SBFIFO......zfTu + 4e8e40 726e4f66 66506f77 65720a0d 00000000 rnOffPower...... + 4e8e50 47656e65 72617465 20457665 6e740a00 Generate Event.. + 4e8e60 215b534f 55524345 5f305d20 62697437 ![SOURCE_0] bit7 + 4e8e70 206f6e0a 0d000000 21555342 20726573 on.....!USB res + 4e8e80 65740a0d 00000000 21555342 20737573 et......!USB sus + 4e8e90 70656e64 0a0d0000 21555342 20726573 pend....!USB res + 4e8ea0 756d650a 0d000000 362e2075 73625f68 ume.....6. usb_h + 4e8eb0 636c6b20 7264790a 0d000000 30782530 clk rdy.....0x%0 + 4e8ec0 38782854 295d0000 30782530 38782825 8x(T)]..0x%08x(% + 4e8ed0 63292d3e 00000000 0a0d2020 20000000 c)->...... ... + 4e8ee0 6d69692d 6d64696f 202d2072 65736574 mii-mdio - reset + 4e8ef0 202d2073 74617274 200a0000 6d69692d - start ...mii- + 4e8f00 6d64696f 202d2072 65736574 202d2065 mdio - reset - e + 4e8f10 6e64200a 00000000 73746172 74656420 nd .....started + 4e8f20 72656365 6976696e 67206279 74657320 receiving bytes + 4e8f30 746f2025 78206c65 6e677468 2025640a to %x length %d. + 4e8f40 00000000 636f6d70 6c657465 64207265 ....completed re + 4e8f50 63656976 696e6720 62797465 7320746f ceiving bytes to + 4e8f60 20257820 6c656e67 74682025 640a0000 %x length %d... + 4e8f70 4669726d 77617265 20446f77 6e6c6f61 Firmware Downloa + 4e8f80 64206c65 6e677468 20307825 780a0000 d length 0x%x... + 4e8f90 4669726d 77617265 20457865 63204164 Firmware Exec Ad + 4e8fa0 64726573 73203078 25780a00 4669726d dress 0x%x..Firm + 4e8fb0 77617265 20636865 636b7375 6d203078 ware checksum 0x + 4e8fc0 25780a00 4669726d 77617265 20636865 %x..Firmware che + 4e8fd0 636b7375 6d206661 696c6564 202d2072 cksum failed - r + 4e8fe0 65206e65 676f7469 6174696e 67200a00 e negotiating .. + 4e8ff0 4669726d 77617265 20446f77 6e6c6f61 Firmware Downloa + 4e9000 64206973 20676f6f 64200a00 434f4d4d d is good ..COMM + 4e9010 414e4420 544f2053 54415254 20464952 AND TO START FIR + 4e9020 4d574152 45205245 43454956 4544200a MWARE RECEIVED . + 4e9030 00000000 372e312e 30000000 4c58322e ....7.1.0...LX2. + 4e9040 312e3000 00500400 00500400 00500950 1.0..P...P...P.P + 4e9050 00500b78 .P.x +Contents of section .data: + 500400 008e6928 008e1104 008e6928 008e6928 ..i(......i(..i( + 500410 008e1174 008e102c 008e6928 008e6928 ...t...,..i(..i( + 500420 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500430 008e63ac 008e63ac 008e63ac 008e63ac ..c...c...c...c. + 500440 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500450 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500460 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500470 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500480 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500490 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004a0 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004b0 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004c0 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004d0 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004e0 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004f0 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500500 00000000 ffffffff 008e6920 00000012 ..........i .... + 500510 008e6920 00000011 008e6920 00000010 ..i ......i .... + 500520 008e6920 0000000f 008e6920 0000000e ..i ......i .... + 500530 008e6920 0000000d 008e6920 0000000c ..i ......i .... + 500540 008e6920 0000000b 008e6920 0000000a ..i ......i .... + 500550 008e6920 00000009 008e6920 00000008 ..i ......i .... + 500560 008e6920 00000007 008e6920 00000006 ..i ......i .... + 500570 008e6920 00000005 008e6920 00000004 ..i ......i .... + 500580 008e6920 00000003 008e6920 00000002 ..i ......i .... + 500590 008e6920 00000001 008e6920 00000000 ..i ......i .... + 5005a0 fffffffe 00040000 fffffffe 00020000 ................ + 5005b0 fffffffe 00010000 fffffffe 00008000 ................ + 5005c0 fffffffe 00004000 fffffffe 00002000 ......@....... . + 5005d0 fffffffe 00001000 fffffffe 00000800 ................ + 5005e0 fffffffe 00000400 fffffffe 00000200 ................ + 5005f0 fffffffe 00000100 fffffffe 00000080 ................ + 500600 fffffffe 00000040 fffffffe 00000020 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..$............. + 500710 00000000 00000000 00000000 00000000 ................ + 500720 00020004 00080000 00000000 00000000 ................ + 500730 00000000 00000000 aa00aa00 aaaaaaaa ................ + 500740 eeaaaaaa eeeeeeee feeeeeee ffffffff ................ + 500750 ffffffff 7fffffff f7efdfbf 7efcfdfb ............~... + 500760 fdfbdfbf 00000000 00000000 00000000 ................ + 500770 00000000 00000000 00000000 00000000 ................ + 500780 07090000 00000000 00000000 00000000 ................ + 500790 00000000 00000000 00000000 00000000 ................ + 5007a0 00000000 00000000 00000000 00000000 ................ + 5007b0 00000000 00000000 00000000 00000000 ................ + 5007c0 00053000 00000800 00000000 00000000 ..0............. + 5007d0 00000000 00000000 00053000 00000900 ..........0..... + 5007e0 00000000 00000000 00000000 00000000 ................ + 5007f0 00053000 00000a00 00000000 00000000 ..0............. + 500800 00000000 00000000 00053000 00000b00 ..........0..... + 500810 00000000 00000000 00000000 00000000 ................ + 500820 00053000 00000c00 00000000 00000000 ..0............. + 500830 00000000 00000000 00053000 00000d00 ..........0..... + 500840 00000000 00000000 00000000 00000000 ................ + 500850 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500860 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500870 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500880 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500890 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008a0 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008b0 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008c0 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008d0 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008e0 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008f0 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500900 008e6950 008e6950 008e6950 008e6950 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039f9004 ................ + 8e08d0 78900579 90067a90 077b9000 53000000 x..y..z..{..S... + 8e08e0 00000000 00000000 00000000 00000000 ................ + 8e08f0 00000000 00000000 00000000 00000000 ................ + 8e0900 00dc9400 1d9001dd 9402de94 03df9404 ................ + 8e0910 04940505 94060694 07079408 08940909 ................ + 8e0920 940a0a94 0b0b9400 43000000 00000000 ........C....... + 8e0930 00000000 00000000 00000000 00000000 ................ + 8e0940 00dc9001 dd9002de 900b1d90 03df9004 ................ + 8e0950 b49005b5 9006b690 07b79008 b89009b9 ................ + 8e0960 900aba90 0bbb9000 5300 ........S. +Contents of section .KernelExceptionVector.text: + 8e0d40 00140063 fff9 ...c.. +Contents of section .UserExceptionVector.text: + 8e0e20 211c9092 14931513 000602e8 3003230a !...........0.#. + 8e0e30 83309416 0a3000 .0...0. +Contents of section .DoubleExceptionVector.text: + 8e0f20 04140063 fff9 ...c.. +Contents of section .Level2InterruptVector.text: + 8e0a20 02d2160a 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00020007 d7ee0400 00000000 ................ + 0690 008e6990 00000008 00000000 00000000 ..i............. + 06a0 0000001c 00020007 dae20400 00000000 ................ + 06b0 008e6998 00000068 00000000 00000000 ..i....h........ + 06c0 0000001c 00020007 dbd60400 00000000 ................ + 06d0 008e6a00 00000049 00000000 00000000 ..j....I........ + 06e0 0000001c 00020007 dcca0400 00000000 ................ + 06f0 008e6a4c 00000050 00000000 00000000 ..jL...P........ + 0700 0000001c 00020007 ddbe0400 00000000 ................ + 0710 008e6a9c 0000003d 00000000 00000000 ..j....=........ + 0720 0000001c 00020007 deb20400 00000000 ................ + 0730 008e6adc 00000045 00000000 00000000 ..j....E........ + 0740 0000001c 00020007 e9f20400 00000000 ................ + 0750 008e6b24 00000135 00000000 00000000 ..k$...5........ + 0760 0000001c 00020007 eaff0400 00000000 ................ + 0770 008e6c5c 000001c2 00000000 00000000 ..l\............ + 0780 0000001c 00020007 f6800400 00000000 ................ + 0790 008e6e20 00000074 00000000 00000000 ..n ...t........ + 07a0 0000001c 00020007 f78d0400 00000000 ................ + 07b0 008e6560 00000118 00000000 00000000 ..e`............ + 07c0 0000001c 00020007 f89a0400 00000000 ................ + 07d0 008e6678 00000098 00000000 00000000 ..fx............ + 07e0 0000001c 00020007 f9a70400 00000000 ................ + 07f0 008e6710 00000063 00000000 00000000 ..g....c........ + 0800 0000001c 00020007 fab40400 00000000 ................ + 0810 008e6774 0000008e 00000000 00000000 ..gt............ + 0820 0000001c 00020008 05dd0400 00000000 ................ + 0830 008e6804 0000011b 00000000 00000000 ..h............. +Contents of section .debug_pubnames: + 0000 00000052 00020000 065c0000 00000000 ...R.....\...... + 0010 02f15f78 746f735f 7365745f 696e7465 .._xtos_set_inte + 0020 72727570 745f6861 6e646c65 725f6172 rrupt_handler_ar + 0030 67000000 03655f78 746f735f 7365745f g....e_xtos_set_ + 0040 696e7465 72727570 745f6861 6e646c65 interrupt_handle + 0050 72000000 00000000 01c50002 00000c8e r............... + 0060 00000000 000049bc 5f726f6d 5f73746f ......I._rom_sto + 0070 72655f74 61626c65 0000004a ca626173 re_table...J.bas + 0080 69635f52 4f4d5f6d 6f64756c 655f7461 ic_ROM_module_ta + 0090 626c6500 00004d32 706f7374 0000004d ble...M2post...M + 00a0 704d6167 7069655f 66617461 6c5f6578 pMagpie_fatal_ex + 00b0 63657074 696f6e5f 68616e64 6c657200 ception_handler. + 00c0 00004e1a 6174686f 735f626c 6f636b5f ..N.athos_block_ + 00d0 616c6c5f 696e7472 6c766c00 00004e58 all_intrlvl...NX + 00e0 6174686f 735f756e 626c6f63 6b5f616c athos_unblock_al + 00f0 6c5f696e 74726c76 6c000000 4e946174 l_intrlvl...N.at + 0100 686f735f 72657374 6f72655f 696e7472 hos_restore_intr + 0110 6c766c00 00004fd8 67656e65 7269635f lvl...O.generic_ + 0120 6869665f 6d6f6475 6c655f69 6e737461 hif_module_insta + 0130 6c6c0000 00502861 74686f73 5f696e64 ll...P(athos_ind + 0140 69726563 74696f6e 5f746162 6c655f69 irection_table_i + 0150 6e737461 6c6c0000 00507261 74686f73 nstall...Prathos + 0160 5f696e74 65727275 70745f68 616e646c _interrupt_handl + 0170 65720000 0050cd61 74686f73 5f696e74 er...P.athos_int + 0180 65727275 70745f69 6e697400 00005103 errupt_init...Q. + 0190 6174686f 735f696e 69740000 0051365f athos_init...Q6_ + 01a0 72656164 5f757362 5f646573 63000000 read_usb_desc... + 01b0 51ab7265 61645f75 73625f63 6f6e6600 Q.read_usb_conf. + 01c0 000051e5 7365745f 7063695f 636f6e66 ..Q.set_pci_conf + 01d0 00000052 4e626f6f 746c6f61 64000000 ...RNbootload... + 01e0 526b7063 695f676d 61635f62 6f6f746c Rkpci_gmac_bootl + 01f0 6f616400 00005291 7475726e 5f6f6666 oad...R.turn_off + 0200 5f726300 000052b1 626f6f74 656e7472 _rc...R.bootentr + 0210 79000000 535b6d61 696e0000 00000000 y...S[main...... + 0220 0000ab00 02000060 0a000000 00000046 .......`.......F + 0230 c3616c6c 6f637261 6d5f6375 7272656e .allocram_curren + 0240 745f6164 64720000 0046e561 6c6c6f63 t_addr...F.alloc + 0250 72616d5f 72656d61 696e696e 675f6279 ram_remaining_by + 0260 74657300 0000474f 636d6e6f 735f616c tes...GOcmnos_al + 0270 6c6f6372 616d5f69 6e697400 000047b3 locram_init...G. + 0280 636d6e6f 735f616c 6c6f6372 616d0000 cmnos_allocram.. + 0290 00480d63 6d6e6f73 5f616c6c 6f637261 .H.cmnos_allocra + 02a0 6d5f6465 62756700 00004836 636d6e6f m_debug...H6cmno + 02b0 735f616c 6c6f6372 616d5f6d 6f64756c s_allocram_modul + 02c0 655f696e 7374616c 6c000000 00000000 e_install....... + 02d0 01990002 0000a882 00000000 000046ba ..............F. + 02e0 63746963 6b730000 0046cd63 7572725f cticks...F.curr_ + 02f0 62616e64 00000048 17636d6e 6f735f63 band...H.cmnos_c + 0300 6c6f636b 696e675f 7461626c 65000000 locking_table... + 0310 483f636c 6f636b5f 696e666f 00000048 H?clock_info...H + 0320 56636d6e 6f735f73 6b69705f 706c6c5f Vcmnos_skip_pll_ + 0330 696e6974 00000048 76706c6c 5f637472 init...Hvpll_ctr + 0340 6c5f7365 7474696e 675f3234 67687a00 l_setting_24ghz. + 0350 00004899 706c6c5f 6374726c 5f736574 ..H.pll_ctrl_set + 0360 74696e67 5f356768 7a000000 48d0636d ting_5ghz...H.cm + 0370 6e6f735f 64656c61 795f7573 00000049 nos_delay_us...I + 0380 30636d6e 6f735f6d 696c6c69 7365636f 0cmnos_milliseco + 0390 6e647300 0000495b 636d6e6f 735f7265 nds...I[cmnos_re + 03a0 66636c6b 5f737065 65645f67 65740000 fclk_speed_get.. + 03b0 00498a63 6d6e6f73 5f756172 745f6672 .I.cmnos_uart_fr + 03c0 65717565 6e637900 000049b7 636d6e6f equency...I.cmno + 03d0 735f7379 73636c6b 5f636861 6e676500 s_sysclk_change. + 03e0 000049df 636d6e6f 735f636c 6f636b72 ..I.cmnos_clockr + 03f0 6567735f 696e6974 0000004a 08636d6e egs_init...J.cmn + 0400 6f735f77 6c616e5f 62616e64 5f736574 os_wlan_band_set + 0410 0000004a 49636d6e 6f735f70 6c6c5f69 ...JIcmnos_pll_i + 0420 6e697400 00004a6c 636d6e6f 735f636c nit...Jlcmnos_cl + 0430 6f636b5f 696e6974 0000004a c1636d6e ock_init...J.cmn + 0440 6f735f74 69636b00 00004b1c 636d6e6f os_tick...K.cmno + 0450 735f636c 6f636b5f 6d6f6475 6c655f69 s_clock_module_i + 0460 6e737461 6c6c0000 00000000 0000d100 nstall.......... + 0470 020000f3 df000000 00000046 d0656570 ...........F.eep + 0480 5f737461 74650000 0046e665 65705f65 _state...F.eep_e + 0490 78697374 00000047 48636d6e 6f735f65 xist...GHcmnos_e + 04a0 6570726f 6d5f7772 6974655f 68776f72 eprom_write_hwor + 04b0 64000000 479c636d 6e6f735f 65657072 d...G.cmnos_eepr + 04c0 6f6d5f72 6561645f 68776f72 64000000 om_read_hword... + 04d0 47fe636d 6e6f735f 6565705f 69735f65 G.cmnos_eep_is_e + 04e0 78697374 00000048 39636d6e 6f735f65 xist...H9cmnos_e + 04f0 65705f77 72697465 00000048 dc636d6e ep_write...H.cmn + 0500 6f735f65 65705f72 65616400 00004977 os_eep_read...Iw + 0510 636d6e6f 735f6565 705f696e 69740000 cmnos_eep_init.. + 0520 0049c963 6d6e6f73 5f656570 5f6d6f64 .I.cmnos_eep_mod + 0530 756c655f 696e7374 616c6c00 00000000 ule_install..... + 0540 000000ed 00020001 3de70000 00000000 ........=....... + 0550 487a636d 6e6f735f 6973725f 696e666f Hzcmnos_isr_info + 0560 00000048 95636d6e 6f735f65 6e61626c ...H.cmnos_enabl + 0570 65645f69 6e746572 72757074 73000000 ed_interrupts... + 0580 48d4636d 6e6f735f 696e7472 5f64756d H.cmnos_intr_dum + 0590 6d790000 00491163 6d6e6f73 5f696e74 my...I.cmnos_int + 05a0 725f696e 69740000 00494163 6d6e6f73 r_init...IAcmnos + 05b0 5f696e74 725f6d61 736b5f69 6e756d00 _intr_mask_inum. + 05c0 000049a1 636d6e6f 735f696e 74725f75 ..I.cmnos_intr_u + 05d0 6e6d6173 6b5f696e 756d0000 004a0563 nmask_inum...J.c + 05e0 6d6e6f73 5f696e74 725f6174 74616368 mnos_intr_attach + 05f0 5f697372 0000004a 6a636d6e 6f735f69 _isr...Jjcmnos_i + 0600 6e74725f 696e766f 6b655f69 73720000 ntr_invoke_isr.. + 0610 004aab63 6d6e6f73 5f696e74 725f6d6f .J.cmnos_intr_mo + 0620 64756c65 5f696e73 74616c6c 00000000 dule_install.... + 0630 00000000 3e000200 0188d000 00000000 ....>........... + 0640 0046ed63 6d6e6f73 5f6d656d 5f696e69 .F.cmnos_mem_ini + 0650 74000000 4710636d 6e6f735f 6d656d5f t...G.cmnos_mem_ + 0660 6d6f6475 6c655f69 6e737461 6c6c0000 module_install.. + 0670 00000000 00013600 020001d0 1d000000 ......6......... + 0680 00000048 56617373 6c6f6f70 00000048 ...HVassloop...H + 0690 6a617373 7072696e 74000000 48936375 jassprint...H.cu + 06a0 7272656e 745f6475 6d700000 00493663 rrent_dump...I6c + 06b0 6d6e6f73 5f737973 74656d5f 72657365 mnos_system_rese + 06c0 74000000 495d636d 6e6f735f 6d61635f t...I]cmnos_mac_ + 06d0 72657365 74000000 4981636d 6e6f735f reset...I.cmnos_ + 06e0 6d697361 6c69676e 65645f6c 6f61645f misaligned_load_ + 06f0 68616e64 6c657200 000049c6 636d6e6f handler...I.cmno + 0700 735f6173 73666169 6c000000 4a11636d s_assfail...J.cm + 0710 6e6f735f 7265706f 72745f66 61696c75 nos_report_failu + 0720 72655f74 6f5f686f 73740000 004a6263 re_to_host...Jbc + 0730 6d6e6f73 5f746172 6765745f 69645f67 mnos_target_id_g + 0740 65740000 004a8e63 6d6e6f73 5f676574 et...J.cmnos_get + 0750 5f6b6268 69740000 004ae963 6d6e6f73 _kbhit...J.cmnos + 0760 5f69735f 686f7374 5f707265 73656e74 _is_host_present + 0770 0000004b 31636d6e 6f735f72 6f6d5f76 ...K1cmnos_rom_v + 0780 65727369 6f6e5f67 65740000 004b5f63 ersion_get...K_c + 0790 6d6e6f73 5f6d6973 635f6d6f 64756c65 mnos_misc_module + 07a0 5f696e73 74616c6c 00000000 00000000 _install........ + 07b0 74000200 021bba00 00000000 0046c65f t............F._ + 07c0 70757463 00000047 78636d6e 6f735f77 putc...Gxcmnos_w + 07d0 72697465 5f636861 72000000 49b3636d rite_char...I.cm + 07e0 6e6f735f 7072696e 74660000 0049fe63 nos_printf...I.c + 07f0 6d6e6f73 5f707269 6e74665f 696e6974 mnos_printf_init + 0800 0000004a 25636d6e 6f735f70 72696e74 ...J%cmnos_print + 0810 665f6d6f 64756c65 5f696e73 74616c6c f_module_install + 0820 00000000 00000000 c8000200 02662100 .............f!. + 0830 00000000 0046c370 61746368 5f737461 .....F.patch_sta + 0840 72740000 0046db70 61746368 5f616464 rt...F.patch_add + 0850 72000000 476c5f70 61746368 5f64756d r...Gl_patch_dum + 0860 70000000 47a45f72 6561645f 726f6d5f p...G._read_rom_ + 0870 70617463 68000000 4806636d 6e6f735f patch...H.cmnos_ + 0880 726f6d70 5f646563 6f646500 00004889 romp_decode...H. + 0890 636d6e6f 735f726f 6d705f69 6e737461 cmnos_romp_insta + 08a0 6c6c0000 0048b463 6d6e6f73 5f726f6d ll...H.cmnos_rom + 08b0 705f646f 776e6c6f 61640000 00493363 p_download...I3c + 08c0 6d6e6f73 5f726f6d 705f696e 69740000 mnos_romp_init.. + 08d0 00495763 6d6e6f73 5f726f6d 705f6d6f .IWcmnos_romp_mo + 08e0 64756c65 5f696e73 74616c6c 00000000 dule_install.... + 08f0 00000000 44000200 02afb600 00000000 ....D........... + 0900 0046c663 6d6e6f73 5f737472 696e675f .F.cmnos_string_ + 0910 696e6974 00000046 ec636d6e 6f735f73 init...F.cmnos_s + 0920 7472696e 675f6d6f 64756c65 5f696e73 tring_module_ins + 0930 74616c6c 00000000 00000000 ad000200 tall............ + 0940 02f6e200 00000000 00472663 6d6e6f73 .........G&cmnos + 0950 5f746173 6b6c6574 5f696e69 74000000 _tasklet_init... + 0960 474d636d 6e6f735f 7461736b 6c65745f GMcmnos_tasklet_ + 0970 696e6974 5f746173 6b000000 47a8636d init_task...G.cm + 0980 6e6f735f 7461736b 6c65745f 73636865 nos_tasklet_sche + 0990 64756c65 00000047 e9636d6e 6f735f74 dule...G.cmnos_t + 09a0 61736b6c 65745f64 69736162 6c650000 asklet_disable.. + 09b0 00483c63 6d6e6f73 5f746173 6b6c6574 .H__pci_get + 0cd0 5f72785f 656e6700 0000487a 5f5f7063 _rx_eng...Hz__pc + 0ce0 695f656e 61626c65 00000048 ac5f5f70 i_enable...H.__p + 0cf0 63695f72 65736574 00000048 e05f5f70 ci_reset...H.__p + 0d00 63695f62 6f6f745f 696e6974 00000049 ci_boot_init...I + 0d10 045f5f70 63695f69 6e697400 0000493d .__pci_init...I= + 0d20 5f5f7063 695f6366 675f7069 70650000 __pci_cfg_pipe.. + 0d30 0049a95f 5f706369 5f737461 72740000 .I.__pci_start.. + 0d40 0049dd5f 5f706369 5f726567 5f63616c .I.__pci_reg_cal + 0d50 6c626163 6b000000 4a2d5f5f 7063695f lback...J-__pci_ + 0d60 72656170 5f786d69 74746564 0000004a reap_xmitted...J + 0d70 8c5f5f70 63695f72 6561705f 72656376 .__pci_reap_recv + 0d80 0000004a de5f5f70 63695f69 73725f68 ...J.__pci_isr_h + 0d90 616e646c 65720000 004b2a5f 5f706369 andler...K*__pci + 0da0 5f786d69 745f6275 66000000 4b8c5f5f _xmit_buf...K.__ + 0db0 7063695f 72657475 726e5f72 65637600 pci_return_recv. + 0dc0 00004bec 5f5f7063 695f6973 5f706970 ..K.__pci_is_pip + 0dd0 655f7375 70706f72 74656400 00004c3f e_supported...L? + 0de0 5f5f7063 695f6765 745f6d61 785f6d73 __pci_get_max_ms + 0df0 675f6c65 6e000000 4c905f5f 7063695f g_len...L.__pci_ + 0e00 6765745f 72657365 72766564 5f686561 get_reserved_hea + 0e10 64726f6f 6d000000 4cd85f5f 7063695f droom...L.__pci_ + 0e20 73687574 646f776e 0000004d 0f5f5f70 shutdown...M.__p + 0e30 63695f67 65745f64 65665f70 69706500 ci_get_def_pipe. + 0e40 00004d71 6869665f 7063695f 6d6f6475 ..Mqhif_pci_modu + 0e50 6c655f69 6e737461 6c6c0000 004db168 le_install...M.h + 0e60 69665f70 63695f61 70695f69 6e737461 if_pci_api_insta + 0e70 6c6c0000 00000000 0001ad00 02000469 ll.............i + 0e80 e2000000 00000047 6e675f68 69665553 .......Gng_hifUS + 0e90 42437478 00000049 7d5f4849 46757362 BCtx...I}_HIFusb + 0ea0 5f696e69 74000000 49c85f48 49467573 _init...I._HIFus + 0eb0 625f7368 7574646f 776e0000 004a025f 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6f72655f 696e7472 6c766c00 01010392 ore_intrlvl..... + 05b40 01200290 00008e14 68008e14 7200004e . ......h...r..N + 05b50 d7240101 066f6c64 5f696e74 72000000 .$...old_intr... + 05b60 01a50152 00250101 10415236 3030325f ...R.%...AR6002_ + 05b70 6d697361 6c69676e 65645f6c 6f61645f misaligned_load_ + 05b80 68616e64 6c657200 01049201 b0010290 handler......... + 05b90 00008e14 74008e14 d200004f 45240101 ....t......OE$.. + 05ba0 10657863 5f667261 6d650000 004a0b01 .exc_frame...J.. + 05bb0 521e6475 6d700000 0004a203 91d07e1f R.dump........~. + 05bc0 73746b70 74720000 004a501f 69000000 stkptr...JP.i... + 05bd0 01080025 01013b41 52363030 325f6661 ...%..;AR6002_fa + 05be0 74616c5f 65786365 7074696f 6e5f6861 tal_exception_ha + 05bf0 6e646c65 72000104 9201b001 02900000 ndler........... + 05c00 8e14d400 8e154500 004fd824 01013b65 ......E..O.$..;e + 05c10 78635f66 72616d65 0000004a 0b01521f xc_frame...J..R. + 05c20 72657365 745f6675 6e630000 0001011e reset_func...... + 05c30 64756d70 00000004 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ction_table_t... + 184f0 45ee1110 0000473e 08613000 000001af E.....G>.a0..... + 18500 02230008 61310000 0001af02 23040861 .#..a1......#..a + 18510 32000000 01af0223 08086133 00000001 2......#..a3.... + 18520 af02230c 000e0000 470b5000 00474b0f ..#.....G.P..GK. + 18530 04000758 54656e73 615f6578 63657074 ...XTensa_except + 18540 696f6e5f 6672616d 655f7300 80000048 ion_frame_s....H + 18550 2f087874 5f706300 000001af 02230008 /.xt_pc......#.. + 18560 78745f70 73000000 01af0223 04087874 xt_ps......#..xt + 18570 5f736172 00000001 af022308 0878745f _sar......#..xt_ + 18580 76707269 00000001 af02230c 0878745f vpri......#..xt_ + 18590 61320000 0001af02 23100878 745f6133 a2......#..xt_a3 + 185a0 00000001 af022314 0878745f 61340000 ......#..xt_a4.. + 185b0 0001af02 23180878 745f6135 00000001 ....#..xt_a5.... + 185c0 af02231c 0878745f 65786363 61757365 ..#..xt_exccause + 185d0 00000001 af022320 0878745f 6c636f75 ......# .xt_lcou + 185e0 6e740000 0001af02 23240878 745f6c62 nt......#$.xt_lb + 185f0 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745f636f 6e666967 .#.._uart_config + 1d2c0 00000003 65022318 085f7561 72745f68 ....e.#.._uart_h + 1d2d0 77696e69 74000000 036e0223 1c000300 winit....n.#.... + 1d2e0 00020804 00077561 72745f62 6c6b0010 ......uart_blk.. + 1d2f0 00000312 08646562 75675f6d 6f646500 .....debug_mode. + 1d300 0000018c 02230008 62617564 00000001 .....#..baud.... + 1d310 8c022302 085f7561 72740000 0002c102 ..#.._uart...... + 1d320 2304085f 74780000 0001bd02 23080006 #.._tx......#... + 1d330 000001af 01030000 03120400 04756e73 .............uns + 1d340 69676e65 64206368 61720007 01097569 igned char....ui + 1d350 6e74385f 74000000 031f0201 03000003 nt8_t........... + 1d360 3d040003 00000330 04000600 00018c01 =......0........ + 1d370 03000003 4d040002 01030000 035a0400 ....M........Z.. + 1d380 02010300 00036304 00020103 0000036c ......c........l + 1d390 04000300 00011904 00060000 01120103 ................ + 1d3a0 0000037c 04000744 425f434f 4d4d414e ...|...DB_COMMAN + 1d3b0 445f5354 52554354 000c0000 03d40863 D_STRUCT.......c + 1d3c0 6d645f73 74720000 00037502 23000868 md_str....u.#..h + 1d3d0 656c705f 73747200 00000375 02230408 elp_str....u.#.. + 1d3e0 636d645f 66756e63 00000003 82022308 cmd_func......#. + 1d3f0 00076462 675f6170 69000800 00040708 ..dbg_api....... + 1d400 5f646267 5f696e69 74000000 010b0223 _dbg_init......# + 1d410 00085f64 62675f74 61736b00 0000010b .._dbg_task..... + 1d420 02230400 0a040004 756e7369 676e6564 .#......unsigned + 1d430 20696e74 00070406 00000407 01030000 int............ + 1d440 041a0400 0b0b0300 00042804 00060000 ..........(..... + 1d450 04070103 00000430 04000600 00011201 .......0........ + 1d460 03000004 3d040007 6d656d5f 61706900 ....=...mem_api. + 1d470 14000004 ac085f6d 656d5f69 6e697400 ......_mem_init. + 1d480 0000010b 02230008 5f6d656d 73657400 .....#.._memset. + 1d490 00000420 02230408 5f6d656d 63707900 ... .#.._memcpy. + 1d4a0 00000436 02230808 5f6d656d 6d6f7665 ...6.#.._memmove + 1d4b0 00000004 3602230c 085f6d65 6d636d70 ....6.#.._memcmp + 1d4c0 00000004 43022310 00077265 67697374 ....C.#...regist + 1d4d0 65725f64 756d705f 73009000 00051308 er_dump_s....... + 1d4e0 74617267 65745f69 64000000 01af0223 target_id......# + 1d4f0 00086173 736c696e 65000000 01af0223 ..assline......# + 1d500 04087063 00000001 af022308 08626164 ..pc......#..bad + 1d510 76616464 72000000 01af0223 0c086578 vaddr......#..ex + 1d520 635f6672 616d6500 0000482f 02231000 c_frame...H/.#.. + 1d530 03000004 ac040002 01030000 051a0400 ................ + 1d540 02010300 00052304 00060000 01120103 ......#......... + 1d550 0000052c 04000c68 6f737469 665f7300 ...,...hostif_s. + 1d560 04000005 880d4849 465f5553 4200000d ......HIF_USB... + 1d570 4849465f 50434945 00010d48 49465f47 HIF_PCIE...HIF_G + 1d580 4d414300 020d4849 465f5043 4900030d MAC...HIF_PCI... + 1d590 4849465f 4e554d00 040d4849 465f4e4f HIF_NUM...HIF_NO + 1d5a0 4e450005 0009415f 484f5354 49460000 NE....A_HOSTIF.. + 1d5b0 00053906 00000588 01030000 05960400 ..9............. + 1d5c0 06000003 30010300 0005a304 00060000 ....0........... + 1d5d0 018c0103 000005b0 0400076d 6973635f ...........misc_ + 1d5e0 61706900 24000006 a0085f73 79737465 api.$....._syste + 1d5f0 6d5f7265 73657400 0000010b 02230008 m_reset......#.. + 1d600 5f6d6163 5f726573 65740000 00010b02 _mac_reset...... + 1d610 2304085f 61737366 61696c00 0000051c #.._assfail..... + 1d620 02230808 5f6d6973 616c6967 6e65645f .#.._misaligned_ + 1d630 6c6f6164 5f68616e 646c6572 00000005 load_handler.... + 1d640 1c02230c 085f7265 706f7274 5f666169 ..#.._report_fai + 1d650 6c757265 5f746f5f 686f7374 00000005 lure_to_host.... + 1d660 25022310 085f7461 72676574 5f69645f %.#.._target_id_ + 1d670 67657400 00000532 02231408 5f69735f get....2.#.._is_ + 1d680 686f7374 5f707265 73656e74 00000005 host_present.... + 1d690 9c022318 085f6b62 68697400 000005a9 ..#.._kbhit..... + 1d6a0 02231c08 5f726f6d 5f766572 73696f6e .#.._rom_version + 1d6b0 5f676574 00000005 b6022320 00060000 _get......# .... + 1d6c0 03750103 000006a0 04000600 00037501 .u............u. + 1d6d0 03000006 ad040006 00000112 01030000 ................ + 1d6e0 06ba0400 06000001 12010300 0006c704 ................ + 1d6f0 00060000 01120103 000006d4 04000773 ...............s + 1d700 7472696e 675f6170 69001800 00075a08 tring_api.....Z. + 1d710 5f737472 696e675f 696e6974 00000001 _string_init.... + 1d720 0b022300 085f7374 72637079 00000006 ..#.._strcpy.... + 1d730 a6022304 085f7374 726e6370 79000000 ..#.._strncpy... + 1d740 06b30223 08085f73 74726c65 6e000000 ...#.._strlen... + 1d750 06c00223 0c085f73 7472636d 70000000 ...#.._strcmp... + 1d760 06cd0223 10085f73 74726e63 6d700000 ...#.._strncmp.. + 1d770 0006da02 2314000e 0000040a 14000007 ....#........... + 1d780 670f0400 095f415f 54494d45 525f5350 g...._A_TIMER_SP + 1d790 41434500 0000075a 09415f74 696d6572 ACE....Z.A_timer + 1d7a0 5f740000 00076703 0000077b 04000201 _t....g....{.... + 1d7b0 03000007 91040002 01030000 079a0400 ................ + 1d7c0 09415f48 414e444c 45000000 040a0201 .A_HANDLE....... + 1d7d0 09415f54 494d4552 5f46554e 43000000 .A_TIMER_FUNC... + 1d7e0 07b10300 0007b304 00020103 000007cc ................ + 1d7f0 04000774 696d6572 5f617069 00140000 ...timer_api.... + 1d800 084b085f 74696d65 725f696e 69740000 .K._timer_init.. + 1d810 00010b02 2300085f 74696d65 725f6172 ....#.._timer_ar + 1d820 6d000000 07930223 04085f74 696d6572 m......#.._timer + 1d830 5f646973 61726d00 0000079c 02230808 _disarm......#.. + 1d840 5f74696d 65725f73 6574666e 00000007 _timer_setfn.... + 1d850 ce02230c 085f7469 6d65725f 72756e00 ..#.._timer_run. + 1d860 0000010b 02231000 09424f4f 4c45414e .....#...BOOLEAN + 1d870 00000001 8c060000 084b0103 00000858 .........K.....X + 1d880 04000600 00084b01 03000008 65040006 ......K.....e... + 1d890 0000084b 01030000 08720400 07726f6d ...K.....r...rom + 1d8a0 705f6170 69001000 0008e408 5f726f6d p_api......._rom + 1d8b0 705f696e 69740000 00010b02 2300085f p_init......#.._ + 1d8c0 726f6d70 5f646f77 6e6c6f61 64000000 romp_download... + 1d8d0 085e0223 04085f72 6f6d705f 696e7374 .^.#.._romp_inst + 1d8e0 616c6c00 0000086b 02230808 5f726f6d all....k.#.._rom + 1d8f0 705f6465 636f6465 00000008 7802230c p_decode....x.#. + 1d900 0007726f 6d5f7061 7463685f 73740010 ..rom_patch_st.. + 1d910 00000940 08637263 31360000 00018c02 ...@.crc16...... + 1d920 2300086c 656e0000 00018c02 2302086c #..len......#..l + 1d930 645f6164 64720000 0001af02 23040866 d_addr......#..f + 1d940 756e5f61 64647200 000001af 02230808 un_addr......#.. + 1d950 7066756e 00000003 4602230c 00076565 pfun....F.#...ee + 1d960 705f7265 6469725f 61646472 00040000 p_redir_addr.... + 1d970 0972086f 66667365 74000000 018c0223 .r.offset......# + 1d980 00087369 7a650000 00018c02 23020009 ..size......#... + 1d990 415f5549 4e543332 00000004 0a060000 A_UINT32........ + 1d9a0 04070103 00000980 04000761 6c6c6f63 ...........alloc + 1d9b0 72616d5f 61706900 0c000009 f108636d ram_api.......cm + 1d9c0 6e6f735f 616c6c6f 6372616d 5f696e69 nos_allocram_ini + 1d9d0 74000000 09860223 0008636d 6e6f735f t......#..cmnos_ + 1d9e0 616c6c6f 6372616d 00000009 86022304 allocram......#. + 1d9f0 08636d6e 6f735f61 6c6c6f63 72616d5f .cmnos_allocram_ + 1da00 64656275 67000000 010b0223 08000201 debug......#.... + 1da10 03000009 f1040009 415f5441 534b4c45 ........A_TASKLE + 1da20 545f4655 4e430000 0009f307 5f746173 T_FUNC......_tas + 1da30 6b6c6574 00100000 0a520866 756e6300 klet.....R.func. + 1da40 000009fa 02230008 61726700 00000407 .....#..arg..... + 1da50 02230408 73746174 65000000 01120223 .#..state......# + 1da60 08086e65 78740000 000a5202 230c0003 ..next....R.#... + 1da70 00000a0e 04000300 000a0e04 0009415f ..............A_ + 1da80 7461736b 6c65745f 74000000 0a0e0300 tasklet_t....... + 1da90 000a6004 00020103 00000a78 04000201 ..`........x.... + 1daa0 0300000a 81040007 7461736b 6c65745f ........tasklet_ + 1dab0 61706900 1400000b 16085f74 61736b6c api......._taskl + 1dac0 65745f69 6e697400 0000010b 02230008 et_init......#.. + 1dad0 5f746173 6b6c6574 5f696e69 745f7461 _tasklet_init_ta + 1dae0 736b0000 000a7a02 2304085f 7461736b sk....z.#.._task + 1daf0 6c65745f 64697361 626c6500 00000a83 let_disable..... + 1db00 02230808 5f746173 6b6c6574 5f736368 .#.._tasklet_sch + 1db10 6564756c 65000000 0a830223 0c085f74 edule......#.._t + 1db20 61736b6c 65745f72 756e0000 00010b02 asklet_run...... + 1db30 23100002 01030000 0b160400 06000009 #............... + 1db40 72010300 000b1f04 00020103 00000b2c r.............., + 1db50 04000763 6c6f636b 5f617069 00240000 ...clock_api.$.. + 1db60 0c0e085f 636c6f63 6b5f696e 69740000 ..._clock_init.. + 1db70 000b1802 2300085f 636c6f63 6b726567 ....#.._clockreg + 1db80 735f696e 69740000 00010b02 2304085f s_init......#.._ + 1db90 75617274 5f667265 7175656e 63790000 uart_frequency.. + 1dba0 000b2502 2308085f 64656c61 795f7573 ..%.#.._delay_us + 1dbb0 0000000b 2e02230c 085f776c 616e5f62 ......#.._wlan_b + 1dbc0 616e645f 73657400 00000b2e 02231008 and_set......#.. + 1dbd0 5f726566 636c6b5f 73706565 645f6765 _refclk_speed_ge + 1dbe0 74000000 0b250223 14085f6d 696c6c69 t....%.#.._milli + 1dbf0 7365636f 6e647300 00000b25 02231808 seconds....%.#.. + 1dc00 5f737973 636c6b5f 6368616e 67650000 _sysclk_change.. + 1dc10 00010b02 231c085f 636c6f63 6b5f7469 ....#.._clock_ti + 1dc20 636b0000 00010b02 23200006 000001af ck......# ...... + 1dc30 01030000 0c0e0400 09415f6f 6c645f69 .........A_old_i + 1dc40 6e74725f 74000000 01af0600 000c1b01 ntr_t........... + 1dc50 0300000c 2d040002 01030000 0c3a0400 ....-........:.. + 1dc60 02010300 000c4304 00060000 01af0103 ......C......... + 1dc70 00000c4c 04000941 5f697372 5f740000 ...L...A_isr_t.. + 1dc80 000c5202 01030000 0c660400 06000004 ..R......f...... + 1dc90 0a010300 000c6f04 00020103 00000c7c ......o........| + 1dca0 04000769 6e74725f 61706900 2c00000d ...intr_api.,... + 1dcb0 9e085f69 6e74725f 696e6974 00000001 .._intr_init.... + 1dcc0 0b022300 085f696e 74725f69 6e766f6b ..#.._intr_invok + 1dcd0 655f6973 72000000 0c140223 04085f69 e_isr......#.._i + 1dce0 6e74725f 64697361 626c6500 00000c33 ntr_disable....3 + 1dcf0 02230808 5f696e74 725f7265 73746f72 .#.._intr_restor + 1dd00 65000000 0c3c0223 0c085f69 6e74725f e....<.#.._intr_ + 1dd10 6d61736b 5f696e75 6d000000 0c450223 mask_inum....E.# + 1dd20 10085f69 6e74725f 756e6d61 736b5f69 .._intr_unmask_i + 1dd30 6e756d00 00000c45 02231408 5f696e74 num....E.#.._int + 1dd40 725f6174 74616368 5f697372 0000000c r_attach_isr.... + 1dd50 68022318 085f6765 745f696e 7472656e h.#.._get_intren + 1dd60 61626c65 0000000c 7502231c 085f7365 able....u.#.._se + 1dd70 745f696e 7472656e 61626c65 0000000c t_intrenable.... + 1dd80 7e022320 085f6765 745f696e 74727065 ~.# ._get_intrpe + 1dd90 6e64696e 67000000 0c750223 24085f75 nding....u.#$._u + 1dda0 6e626c6f 636b5f61 6c6c5f69 6e74726c nblock_all_intrl + 1ddb0 766c0000 00010b02 23280010 0400000d vl......#(...... + 1ddc0 c4087469 6d656f75 74000000 01af0223 ..timeout......# + 1ddd0 00086163 74696f6e 00000001 af022300 ..action......#. + 1dde0 00110800 000ddf08 636d6400 000001af ........cmd..... + 1ddf0 02230012 00000d9e 02230400 09545f57 .#.......#...T_W + 1de00 44545f43 4d440000 000dc402 01030000 DT_CMD.......... + 1de10 0dee0400 13040000 0e440d45 4e554d5f .........D.ENUM_ + 1de20 5744545f 424f4f54 00010d45 4e554d5f WDT_BOOT...ENUM_ + 1de30 434f4c44 5f424f4f 5400020d 454e554d COLD_BOOT...ENUM + 1de40 5f535553 505f424f 4f540003 0d454e55 _SUSP_BOOT...ENU + 1de50 4d5f554e 4b4e4f57 4e5f424f 4f540004 M_UNKNOWN_BOOT.. + 1de60 0009545f 424f4f54 5f545950 45000000 ..T_BOOT_TYPE... + 1de70 0df70600 000e4401 0300000e 55040007 ......D.....U... + 1de80 7764745f 61706900 1c00000e f9085f77 wdt_api......._w + 1de90 64745f69 6e697400 0000010b 02230008 dt_init......#.. + 1dea0 5f776474 5f656e61 626c6500 0000010b _wdt_enable..... + 1deb0 02230408 5f776474 5f646973 61626c65 .#.._wdt_disable + 1dec0 00000001 0b022308 085f7764 745f7365 ......#.._wdt_se + 1ded0 74000000 0df00223 0c085f77 64745f74 t......#.._wdt_t + 1dee0 61736b00 0000010b 02231008 5f776474 ask......#.._wdt + 1def0 5f726573 65740000 00010b02 2314085f _reset......#.._ + 1df00 7764745f 6c617374 5f626f6f 74000000 wdt_last_boot... + 1df10 0e5b0223 18001304 00000f60 0d524554 .[.#.......`.RET + 1df20 5f535543 43455353 00000d52 45545f4e _SUCCESS...RET_N + 1df30 4f545f49 4e495400 010d5245 545f4e4f OT_INIT...RET_NO + 1df40 545f4558 49535400 020d5245 545f4545 T_EXIST...RET_EE + 1df50 505f434f 52525550 5400030d 5245545f P_CORRUPT...RET_ + 1df60 4545505f 4f564552 464c4f57 00040d52 EEP_OVERFLOW...R + 1df70 45545f55 4e4b4e4f 574e0005 0009545f ET_UNKNOWN....T_ + 1df80 4545505f 52455400 00000ef9 03000001 EEP_RET......... + 1df90 8c040006 00000f60 01030000 0f760400 .......`.....v.. + 1dfa0 0600000f 60010300 000f8304 00076565 ....`.........ee + 1dfb0 705f6170 69001000 000fec08 5f656570 p_api......._eep + 1dfc0 5f696e69 74000000 010b0223 00085f65 _init......#.._e + 1dfd0 65705f72 65616400 00000f7c 02230408 ep_read....|.#.. + 1dfe0 5f656570 5f777269 74650000 000f7c02 _eep_write....|. + 1dff0 2308085f 6565705f 69735f65 78697374 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arm....T.#.._tim + 26e00 65725f73 6574666e 00000007 8602230c er_setfn......#. + 26e10 085f7469 6d65725f 72756e00 00000117 ._timer_run..... + 26e20 02231000 09424f4f 4c45414e 00000001 .#...BOOLEAN.... + 26e30 98060000 08030103 00000810 04000600 ................ + 26e40 00080301 03000008 1d040006 00000803 ................ + 26e50 01030000 082a0400 07726f6d 705f6170 .....*...romp_ap + 26e60 69001000 00089c08 5f726f6d 705f696e i......._romp_in + 26e70 69740000 00011702 2300085f 726f6d70 it......#.._romp + 26e80 5f646f77 6e6c6f61 64000000 08160223 _download......# + 26e90 04085f72 6f6d705f 696e7374 616c6c00 .._romp_install. + 26ea0 00000823 02230808 5f726f6d 705f6465 ...#.#.._romp_de + 26eb0 636f6465 00000008 3002230c 0007726f code....0.#...ro + 26ec0 6d5f7061 7463685f 73740010 000008f8 m_patch_st...... + 26ed0 08637263 31360000 00019802 2300086c .crc16......#..l + 26ee0 656e0000 00019802 2302086c 645f6164 en......#..ld_ad + 26ef0 64720000 0001bb02 23040866 756e5f61 dr......#..fun_a + 26f00 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...............c + 27110 6c6f636b 5f617069 00240000 0bc6085f lock_api.$....._ + 27120 636c6f63 6b5f696e 69740000 000ad002 clock_init...... + 27130 2300085f 636c6f63 6b726567 735f696e #.._clockregs_in + 27140 69740000 00011702 2304085f 75617274 it......#.._uart + 27150 5f667265 7175656e 63790000 000add02 _frequency...... + 27160 2308085f 64656c61 795f7573 0000000a #.._delay_us.... + 27170 e602230c 085f776c 616e5f62 616e645f ..#.._wlan_band_ + 27180 73657400 00000ae6 02231008 5f726566 set......#.._ref + 27190 636c6b5f 73706565 645f6765 74000000 clk_speed_get... + 271a0 0add0223 14085f6d 696c6c69 7365636f ...#.._milliseco + 271b0 6e647300 00000add 02231808 5f737973 nds......#.._sys + 271c0 636c6b5f 6368616e 67650000 00011702 clk_change...... + 271d0 231c085f 636c6f63 6b5f7469 636b0000 #.._clock_tick.. + 271e0 00011702 23200006 000001bb 01030000 ....# .......... + 271f0 0bc60400 09415f6f 6c645f69 6e74725f .....A_old_intr_ + 27200 74000000 01bb0600 000bd301 0300000b t............... + 27210 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7472656e 61626c65 ._get_intrenable + 27320 0000000c 2d02231c 085f7365 745f696e ....-.#.._set_in + 27330 7472656e 61626c65 0000000c 36022320 trenable....6.# + 27340 085f6765 745f696e 74727065 6e64696e ._get_intrpendin + 27350 67000000 0c2d0223 24085f75 6e626c6f g....-.#$._unblo + 27360 636b5f61 6c6c5f69 6e74726c 766c0000 ck_all_intrlvl.. + 27370 00011702 23280011 0400000d 7c087469 ....#(......|.ti + 27380 6d656f75 74000000 01bb0223 00086163 meout......#..ac + 27390 74696f6e 00000001 bb022300 00120800 tion......#..... + 273a0 000d9708 636d6400 000001bb 02230013 ....cmd......#.. + 273b0 00000d56 02230400 09545f57 44545f43 ...V.#...T_WDT_C + 273c0 4d440000 000d7c02 01030000 0da60400 MD....|......... + 273d0 14040000 0dfc0e45 4e554d5f 5744545f .......ENUM_WDT_ + 273e0 424f4f54 00010e45 4e554d5f 434f4c44 BOOT...ENUM_COLD + 273f0 5f424f4f 5400020e 454e554d 5f535553 _BOOT...ENUM_SUS + 27400 505f424f 4f540003 0e454e55 4d5f554e P_BOOT...ENUM_UN + 27410 4b4e4f57 4e5f424f 4f540004 0009545f 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00285b02 2324085f andler...([.#$._ + 2a200 4854435f 436f6e74 726f6c53 76635072 HTC_ControlSvcPr + 2a210 6f636573 734d7367 00000039 5b022328 ocessMsg...9[.#( + 2a220 085f4854 435f436f 6e74726f 6c537663 ._HTC_ControlSvc + 2a230 50726f63 65737353 656e6443 6f6d706c ProcessSendCompl + 2a240 65746500 00003964 02232c08 70526573 ete...9d.#,.pRes + 2a250 65727665 64000000 04130223 30000768 erved......#0..h + 2a260 6f73745f 6170705f 61726561 5f730004 ost_app_area_s.. + 2a270 00003c6d 08776d69 5f70726f 746f636f ...# + 2b130 04000473 686f7274 20756e73 69676e65 ...short unsigne + 2b140 6420696e 74000702 0975696e 7431365f d int....uint16_ + 2b150 74000000 017c046c 6f6e6720 756e7369 t....|.long unsi + 2b160 676e6564 20696e74 00070409 75696e74 gned int....uint + 2b170 33325f74 00000001 a0077561 72745f66 32_t......uart_f + 2b180 69666f00 08000002 0e087374 6172745f ifo.......start_ + 2b190 696e6465 78000000 01920223 0008656e index......#..en + 2b1a0 645f696e 64657800 00000192 02230208 d_index......#.. + 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74000000 02c70223 .#.._uart......# + 2b2c0 04085f74 78000000 01c30223 08000600 .._tx......#.... + 2b2d0 0001b501 03000003 18040004 756e7369 ............unsi + 2b2e0 676e6564 20636861 72000701 0975696e gned char....uin + 2b2f0 74385f74 00000003 25020103 00000343 t8_t....%......C + 2b300 04000300 00033604 00060000 01920103 ......6......... + 2b310 00000353 04000201 03000003 60040002 ...S........`... + 2b320 01030000 03690400 02010300 00037204 .....i........r. + 2b330 00030000 011f0400 06000001 18010300 ................ + 2b340 00038204 00074442 5f434f4d 4d414e44 ......DB_COMMAND + 2b350 5f535452 55435400 0c000003 da08636d _STRUCT.......cm + 2b360 645f7374 72000000 037b0223 00086865 d_str....{.#..he + 2b370 6c705f73 74720000 00037b02 23040863 lp_str....{.#..c + 2b380 6d645f66 756e6300 00000388 02230800 md_func......#.. + 2b390 07646267 5f617069 00080000 040d085f .dbg_api......._ + 2b3a0 6462675f 696e6974 00000001 11022300 dbg_init......#. + 2b3b0 085f6462 675f7461 736b0000 00011102 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5f55494e 54363400 0000174e 095f5f61 _UINT64....N.__a + 2c730 5f75696e 7436345f 74000000 17680961 _uint64_t....h.a + 2c740 5f75696e 7436345f 74000000 17761404 _uint64_t....v.. + 2c750 000017d4 0e414446 5f4f535f 5245534f .....ADF_OS_RESO + 2c760 55524345 5f545950 455f4d45 4d00000e URCE_TYPE_MEM... + 2c770 4144465f 4f535f52 45534f55 5243455f ADF_OS_RESOURCE_ + 2c780 54595045 5f494f00 01000961 64665f6f TYPE_IO....adf_o + 2c790 735f7265 736f7572 63655f74 7970655f s_resource_type_ + 2c7a0 74000000 17981218 0000181e 08737461 t............sta + 2c7b0 72740000 00178802 23000865 6e640000 rt......#..end.. + 2c7c0 00178802 23080874 79706500 000017d4 ....#..type..... + 2c7d0 02231000 09616466 5f6f735f 7063695f .#...adf_os_pci_ + 2c7e0 6465765f 69645f74 00000017 05030000 dev_id_t........ + 2c7f0 181e0400 11040000 185d0870 63690000 .........].pci.. + 2c800 00183702 23000872 61770000 00040d02 ..7.#..raw...... + 2c810 23000011 10000018 7c087063 69000000 #.......|.pci... + 2c820 181e0223 00087261 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00041014 0400001a 970e415f 46414c53 ..........A_FALS + 2ca40 4500000e 415f5452 55450001 0009615f E...A_TRUE....a_ + 2ca50 626f6f6c 5f740000 001a7d03 00001505 bool_t....}..... + 2ca60 0400095f 5f616466 5f6f735f 646d615f ...__adf_os_dma_ + 2ca70 6d61705f 74000000 1aa50201 0d616466 map_t........adf + 2ca80 5f6f735f 63616368 655f7379 6e630004 _os_cache_sync.. + 2ca90 00001b2f 0e414446 5f53594e 435f5052 .../.ADF_SYNC_PR + 2caa0 45524541 4400000e 4144465f 53594e43 EREAD...ADF_SYNC + 2cab0 5f505245 57524954 4500020e 4144465f _PREWRITE...ADF_ + 2cac0 53594e43 5f504f53 54524541 4400010e SYNC_POSTREAD... + 2cad0 4144465f 53594e43 5f504f53 54575249 ADF_SYNC_POSTWRI + 2cae0 54450003 00096164 665f6f73 5f636163 TE....adf_os_cac + 2caf0 68655f73 796e635f 74000000 1ac60201 he_sync_t....... + 2cb00 09616466 5f6f735f 73697a65 5f740000 .adf_os_size_t.. + 2cb10 001a6806 00001b4a 01096164 665f6f73 ..h....J..adf_os + 2cb20 5f646d61 5f6d6170 5f740000 001aac03 _dma_map_t...... + 2cb30 00001b63 04000600 00040d01 0300001a ...c............ + 2cb40 ac040006 0000040d 01020106 00001598 ................ + 2cb50 01020104 73686f72 7420696e 74000502 ....short int... + 2cb60 09415f49 4e543136 0000001b 9d095f5f .A_INT16......__ + 2cb70 615f696e 7431365f 74000000 1baa0961 a_int16_t......a + 2cb80 5f696e74 31365f74 0000001b b7047369 _int16_t......si + 2cb90 676e6564 20636861 72000501 09415f49 gned char....A_I + 2cba0 4e543800 00001bd7 095f5f61 5f696e74 NT8......__a_int + 2cbb0 385f7400 00001be6 09615f69 6e74385f 8_t......a_int8_ + 2cbc0 74000000 1bf2120c 00001c69 08737570 t..........i.sup + 2cbd0 706f7274 65640000 00161d02 23000861 ported......#..a + 2cbe0 64766572 74697a65 64000000 161d0223 dvertized......# + 2cbf0 04087370 65656400 00001bc8 02230808 ..speed......#.. + 2cc00 6475706c 65780000 001c0202 230a0861 duplex......#..a + 2cc10 75746f6e 65670000 00168402 230b000f utoneg......#... + 2cc20 00001684 0600001c 76100500 07616466 ........v....adf + 2cc30 5f6e6574 5f657468 61646472 00060000 _net_ethaddr.... + 2cc40 1c9a0861 64647200 00001c69 02230000 ...addr....i.#.. + 2cc50 095f5f61 5f75696e 7431365f 74000000 .__a_uint16_t... + 2cc60 12f20961 5f75696e 7431365f 74000000 ...a_uint16_t... + 2cc70 1c9a120e 00001cfe 08657468 65725f64 .........ether_d + 2cc80 686f7374 0000001c 69022300 08657468 host....i.#..eth + 2cc90 65725f73 686f7374 0000001c 69022306 er_shost....i.#. + 2cca0 08657468 65725f74 79706500 00001cac .ether_type..... + 2ccb0 02230c00 12140000 1dbf1569 705f7665 .#.........ip_ve + 2ccc0 7273696f 6e000000 16840100 04022300 rsion.........#. + 2ccd0 1569705f 686c0000 00168401 04040223 .ip_hl.........# + 2cce0 00086970 5f746f73 00000016 84022301 ..ip_tos......#. + 2ccf0 0869705f 6c656e00 00001cac 02230208 .ip_len......#.. + 2cd00 69705f69 64000000 1cac0223 04086970 ip_id......#..ip + 2cd10 5f667261 675f6f66 66000000 1cac0223 _frag_off......# + 2cd20 06086970 5f74746c 00000016 84022308 ..ip_ttl......#. + 2cd30 0869705f 70726f74 6f000000 16840223 .ip_proto......# + 2cd40 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....WMI_EVT_CLAS + 41220 535f434d 445f4556 454e5400 000e574d S_CMD_EVENT...WM + 41230 495f4556 545f434c 4153535f 434d445f I_EVT_CLASS_CMD_ + 41240 5245504c 5900010e 574d495f 4556545f REPLY...WMI_EVT_ + 41250 434c4153 535f4d41 58000200 09574d49 CLASS_MAX....WMI + 41260 5f455654 5f434c41 53530000 003f9e07 _EVT_CLASS...?.. + 41270 5f574d49 5f425546 5f434f4e 54455854 _WMI_BUF_CONTEXT + 41280 000c0000 40710848 74634275 66437478 ....@q.HtcBufCtx + 41290 0000003f 89022300 08457665 6e74436c ...?..#..EventCl + 412a0 61737300 00004013 02230408 466c6167 ass...@..#..Flag + 412b0 73000000 12ea0223 08000977 6d695f68 s......#...wmi_h + 412c0 616e646c 655f7400 00000405 09574d49 andle_t......WMI + 412d0 5f535643 5f434f4e 46494700 00003e29 _SVC_CONFIG...>) + 412e0 03000040 83040006 00004071 01030000 ...@......@q.... + 412f0 409e0400 09574d49 5f444953 50415443 @....WMI_DISPATC + 41300 485f5441 424c4500 00003efb 03000040 H_TABLE...>....@ + 41310 ab040002 01030000 40ca0400 06000026 ........@......& + 41320 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696e6f72 al_release_minor + 7ca90 00000000 f2050300 500b4401 02636861 ........P.D..cha + 7caa0 72000701 03000001 37030000 01370500 r.......7....7.. + 7cab0 00014404 00030000 01490300 00013705 ..D......I....7. + 7cac0 00000155 04000458 7468616c 5f72656c ...U...Xthal_rel + 7cad0 65617365 5f6e616d 65000000 01500503 ease_name....P.. + 7cae0 004e87a4 01060000 01370600 00018d07 .N.......7...... + 7caf0 05000458 7468616c 5f72656c 65617365 ...Xthal_release + 7cb00 5f696e74 65726e61 6c000000 01500503 _internal....P.. + 7cb10 00500b48 01045874 68616c5f 7265765f .P.H..Xthal_rev_ + 7cb20 6e6f0000 0000f205 03004e87 a8010458 no........N....X + 7cb30 7468616c 5f6e756d 5f617265 67730000 thal_num_aregs.. + 7cb40 0000f205 03004e87 ac010275 6e736967 ......N....unsig + 7cb50 6e656420 63686172 00070103 000001e5 ned char........ + 7cb60 04587468 616c5f6e 756d5f61 72656773 .Xthal_num_aregs + 7cb70 5f6c6f67 32000000 01f60503 004e87b0 _log2........N.. + 7cb80 01045874 68616c5f 6d656d6f 72795f6f ..Xthal_memory_o + 7cb90 72646572 00000001 f6050300 4e87b101 rder........N... + 7cba0 04587468 616c5f68 6176655f 77696e64 .Xthal_have_wind + 7cbb0 6f776564 00000001 f6050300 4e87b201 owed........N... + 7cbc0 04587468 616c5f68 6176655f 64656e73 .Xthal_have_dens + 7cbd0 69747900 000001f6 0503004e 87b30104 ity........N.... + 7cbe0 58746861 6c5f6861 76655f62 6f6f6c65 Xthal_have_boole + 7cbf0 616e7300 000001f6 05030050 0b4c0104 ans........P.L.. + 7cc00 58746861 6c5f6861 76655f6c 6f6f7073 Xthal_have_loops + 7cc10 00000001 f6050300 4e87b401 04587468 ........N....Xth + 7cc20 616c5f68 6176655f 6e736100 000001f6 al_have_nsa..... + 7cc30 0503004e 87b50104 58746861 6c5f6861 ...N....Xthal_ha + 7cc40 76655f6d 696e6d61 78000000 01f60503 ve_minmax....... + 7cc50 004e87b6 01045874 68616c5f 68617665 .N....Xthal_have + 7cc60 5f736578 74000000 01f60503 004e87b7 _sext........N.. + 7cc70 01045874 68616c5f 68617665 5f636c61 ..Xthal_have_cla + 7cc80 6d707300 000001f6 05030050 0b4d0104 mps........P.M.. + 7cc90 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616c5f68 6176655f N....Xthal_have_ + 7cda0 6e6d6900 000001f6 0503004e 87bd0104 nmi........N.... + 7cdb0 58746861 6c5f6861 76655f70 72696400 Xthal_have_prid. + 7cdc0 000001f6 0503004e 87be0104 58746861 .......N....Xtha + 7cdd0 6c5f6861 76655f72 656c6561 73655f73 l_have_release_s + 7cde0 796e6300 000001f6 0503004e 87bf0104 ync........N.... + 7cdf0 58746861 6c5f6861 76655f73 33326331 Xthal_have_s32c1 + 7ce00 69000000 01f60503 004e87c0 01045874 i........N....Xt + 7ce10 68616c5f 68617665 5f746872 65616470 hal_have_threadp + 7ce20 74720000 0001f605 03004e87 c1010458 tr........N....X + 7ce30 7468616c 5f686176 655f7069 66000000 thal_have_pif... + 7ce40 01f60503 004e87c2 01027368 6f727420 .....N....short + 7ce50 756e7369 676e6564 20696e74 00070203 unsigned int.... + 7ce60 000004e4 04587468 616c5f6e 756d5f77 .....Xthal_num_w + 7ce70 72697465 62756666 65725f65 6e747269 ritebuffer_entri + 7ce80 65730000 0004fa05 03004e87 c4010458 es........N....X + 7ce90 7468616c 5f627569 6c645f75 6e697175 thal_build_uniqu + 7cea0 655f6964 00000000 f2050300 4e87c801 e_id........N... + 7ceb0 04587468 616c5f68 775f636f 6e666967 .Xthal_hw_config + 7cec0 69643000 000000f2 0503004e 87cc0104 id0........N.... + 7ced0 58746861 6c5f6877 5f636f6e 66696769 Xthal_hw_configi + 7cee0 64310000 0000f205 03004e87 d0010458 d1........N....X + 7cef0 7468616c 5f68775f 72656c65 6173655f thal_hw_release_ + 7cf00 6d616a6f 72000000 00f20503 004e87d4 major........N.. + 7cf10 01045874 68616c5f 68775f72 656c6561 ..Xthal_hw_relea + 7cf20 73655f6d 696e6f72 00000000 f2050300 se_minor........ + 7cf30 500b5401 04587468 616c5f68 775f7265 P.T..Xthal_hw_re + 7cf40 6c656173 655f6e61 6d650000 00015005 lease_name....P. + 7cf50 03004e87 d8010600 00013708 000005fe ..N.......7..... + 7cf60 07070004 58746861 6c5f6877 5f6d696e ....Xthal_hw_min + 7cf70 5f766572 73696f6e 5f6d616a 6f720000 _version_major.. + 7cf80 0000f205 03004e87 dc010458 7468616c ......N....Xthal + 7cf90 5f68775f 6d696e5f 76657273 696f6e5f _hw_min_version_ + 7cfa0 6d696e6f 72000000 00f20503 00500b58 minor........P.X + 7cfb0 01045874 68616c5f 68775f6d 61785f76 ..Xthal_hw_max_v + 7cfc0 65727369 6f6e5f6d 616a6f72 00000000 ersion_major.... + 7cfd0 f2050300 4e87e001 04587468 616c5f68 ....N....Xthal_h + 7cfe0 775f6d61 785f7665 7273696f 6e5f6d69 w_max_version_mi + 7cff0 6e6f7200 000000f2 05030050 0b5c0104 nor........P.\.. + 7d000 58746861 6c5f6877 5f72656c 65617365 Xthal_hw_release + 7d010 5f696e74 65726e61 6c000000 01500503 _internal....P.. + 7d020 00500b60 01045874 68616c5f 68617665 .P.`..Xthal_have + 7d030 5f737061 6e6e696e 675f7761 79000000 _spanning_way... + 7d040 01f60503 004e87e4 01045874 68616c5f .....N....Xthal_ + 7d050 68617665 5f696465 6e746974 795f6d61 have_identity_ma + 7d060 70000000 01f60503 004e87e5 01045874 p........N....Xt + 7d070 68616c5f 68617665 5f6d696d 69635f63 hal_have_mimic_c + 7d080 61636865 61747472 00000001 f6050300 acheattr........ + 7d090 4e87e601 04587468 616c5f68 6176655f N....Xthal_have_ + 7d0a0 786c745f 63616368 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04090003 01030209 00030109 00020001 ................ + 1e430 01 . +Contents of section .xt.prop: + 0000 008e1000 0000001a 00020082 008e101a ................ + 0010 00000007 000200a2 008e1021 00000009 ...........!.... + 0020 000200a2 008e102a 00000000 00000008 .......*........ + 0030 004e8000 00000010 00002804 008e0c20 .N........(.... + 0040 00000006 00020082 008e0c26 00000000 ...........&.... + 0050 00000008 008e0f20 00000006 00020082 ....... ........ + 0060 008e0f26 00000000 00000008 008e0d40 ...&...........@ + 0070 00000006 00020082 008e0d46 00000000 ...........F.... + 0080 00000008 008e0000 00000003 00020082 ................ + 0090 008e0003 00000000 00002808 008e0004 ..........(..... + 00a0 00000018 00002801 008e0020 00000021 ......(.... ...! + 00b0 00000082 008e0041 00000000 00004808 .......A......H. + 00c0 008e0050 00000008 000001a2 008e0058 ...P...........X + 00d0 00000005 00000082 008e005d 00000015 ...........].... + 00e0 000000a2 008e0072 0000000a 000000a2 .......r........ + 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4a70 008e6e92 00000002 000200a2 008e6e94 ..n...........n. + 4a80 00000000 00000008 008e6560 0000004a ..........e`...J + 4a90 00020082 008e65aa 00000000 00002808 ......e.......(. + 4aa0 008e65ac 00000002 000201a2 008e65ae ..e...........e. + 4ab0 00000013 00020082 008e65c1 00000005 ..........e..... + 4ac0 000200b2 008e65c6 00000000 00002808 ......e.......(. + 4ad0 008e65c8 00000033 000201a2 008e65fb ..e....3......e. + 4ae0 00000027 000201b2 008e6622 00000015 ...'......f".... + 4af0 00020082 008e6637 00000004 000200b2 ......f7........ + 4b00 008e663b 00000001 00000008 008e663c ..f;..........f< + 4b10 0000000d 000200a2 008e6649 00000000 ..........fI.... + 4b20 00000008 008e6649 00000004 000200a2 ......fI........ + 4b30 008e664d 00000000 00000008 008e664d ..fM..........fM + 4b40 0000001b 000200a2 008e6668 00000005 ..........fh.... + 4b50 000200a2 008e666d 00000000 00000008 ......fm........ + 4b60 008e666d 0000000b 000200a2 008e6678 ..fm..........fx + 4b70 00000000 00000008 004e8700 00000010 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00000000 00002804 008e6710 .N........(...g. + 4c90 0000001b 00020082 008e672b 00000001 ..........g+.... + 4ca0 00000008 008e672c 0000000a 000200a2 ......g,........ + 4cb0 008e6736 00000011 000200a2 008e6747 ..g6..........gG + 4cc0 00000000 00002808 008e6748 00000002 ......(...gH.... + 4cd0 000201a2 008e674a 00000013 00020082 ......gJ........ + 4ce0 008e675d 00000002 000200b2 008e675f ..g]..........g_ + 4cf0 00000005 000200a2 008e6764 00000000 ..........gd.... + 4d00 00000008 008e6764 00000007 000200a2 ......gd........ + 4d10 008e676b 00000001 00000008 008e676c ..gk..........gl + 4d20 00000007 000200a2 008e6773 00000000 ..........gs.... + 4d30 00000008 004e8710 00000000 00002804 .....N........(. + 4d40 008e6774 0000000f 00020082 008e6783 ..gt..........g. + 4d50 00000028 000200a2 008e67ab 00000003 ...(......g..... + 4d60 00020092 008e67ae 00000000 00000008 ......g......... + 4d70 008e67ae 00000004 000200a2 008e67b2 ..g...........g. + 4d80 00000002 00000008 008e67b4 00000005 ..........g..... + 4d90 00020082 008e67b9 00000000 00000008 ......g......... + 4da0 008e67b9 0000000b 000200a2 008e67c4 ..g...........g. + 4db0 00000000 00000008 008e67c4 00000015 ..........g..... + 4dc0 000200a2 008e67d9 00000000 00000008 ......g......... + 4dd0 008e67d9 00000021 000200a2 008e67fa ..g....!......g. + 4de0 00000000 00000008 008e67fa 00000004 ..........g..... + 4df0 000200a2 008e67fe 00000000 00000008 ......g......... + 4e00 008e67fe 00000004 000200a2 008e6802 ..g...........h. + 4e10 00000000 00000008 004e8710 00000004 .........N...... + 4e20 00002804 008e6804 00000014 000200a2 ..(...h......... + 4e30 008e6818 00000021 000200a2 008e6839 ..h....!......h9 + 4e40 00000000 00000008 008e6839 00000002 ..........h9.... + 4e50 000200a2 008e683b 00000000 00002808 ......h;......(. + 4e60 008e683c 0000001a 00020082 008e6856 ..h<..........hV + 4e70 00000008 000200a2 008e685e 00000000 ..........h^.... + 4e80 00000008 008e685e 00000008 000200a2 ......h^........ + 4e90 008e6866 0000000f 000200a2 008e6875 ..hf..........hu + 4ea0 00000008 00020092 008e687d 0000000b ..........h}.... + 4eb0 000200a2 008e6888 00000002 000200a2 ......h......... + 4ec0 008e688a 00000002 00000008 008e688c ..h...........h. + 4ed0 0000000d 000200a2 008e6899 00000015 ..........h..... + 4ee0 000200a2 008e68ae 00000000 00002808 ......h.......(. + 4ef0 008e68b0 00000002 000201a2 008e68b2 ..h...........h. + 4f00 0000001d 00020082 008e68cf 00000003 ..........h..... + 4f10 00020092 008e68d2 00000000 00000008 ......h......... + 4f20 008e68d2 0000000c 000200a2 008e68de ..h...........h. + 4f30 00000002 00000008 008e68e0 0000000e ..........h..... + 4f40 000200a2 008e68ee 00000002 00000008 ......h......... + 4f50 008e68f0 00000013 000200a2 008e6903 ..h...........i. + 4f60 00000000 00002808 008e6904 00000002 ......(...i..... + 4f70 000201a2 008e6906 00000014 00020082 ......i......... + 4f80 008e691a 00000003 000200b2 008e691d ..i...........i. + 4f90 00000000 00000008 008e691d 00000002 ..........i..... + 4fa0 000200a2 008e691f 00000000 00000008 ......i......... + 4fb0 004e8718 00000000 00002804 .N........(. +Contents of section .xt.lit: + 0000 008e0004 00000018 ........ +Contents of section .xtensa.info: + 0000 0000000c 0000019c 00000001 5874656e ............Xten + 0010 73615f49 6e666f00 48575f43 4f4e4649 sa_Info.HW_CONFI + 0020 47494430 3d307863 32383064 6266660a GID0=0xc280dbff. + 0030 48575f43 4f4e4649 47494431 3d307830 HW_CONFIGID1=0x0 + 0040 64303232 3330660a 4255494c 445f554e d02230f.BUILD_UN + 0050 49515545 5f49443d 30783030 30323233 IQUE_ID=0x000223 + 0060 30660a41 42493d30 0a555345 5f414253 0f.ABI=0.USE_ABS + 0070 4f4c5554 455f4c49 54455241 4c533d31 OLUTE_LITERALS=1 + 0080 0a48575f 56455253 494f4e3d 224c5832 .HW_VERSION="LX2 + 0090 2e312e30 220a4857 5f4d494e 5f564552 .1.0".HW_MIN_VER + 00a0 53494f4e 5f4d414a 4f523d32 3231300a SION_MAJOR=2210. + 00b0 48575f4d 494e5f56 45525349 4f4e5f4d HW_MIN_VERSION_M + 00c0 494e4f52 3d300a48 575f4d41 585f5645 INOR=0.HW_MAX_VE + 00d0 5253494f 4e5f4d41 4a4f523d 32323130 RSION_MAJOR=2210 + 00e0 0a48575f 4d41585f 56455253 494f4e5f .HW_MAX_VERSION_ + 00f0 4d494e4f 523d300a 52454c45 4153455f MINOR=0.RELEASE_ + 0100 4e414d45 3d225242 2d323030 372e3222 NAME="RB-2007.2" + 0110 0a52454c 45415345 5f564552 53494f4e .RELEASE_VERSION + 0120 3d22372e 312e3022 0a52454c 45415345 ="7.1.0".RELEASE + 0130 5f4d414a 4f523d37 3031300a 52454c45 _MAJOR=7010.RELE + 0140 4153455f 4d494e4f 523d300a 434f5245 ASE_MINOR=0.CORE + 0150 5f4e414d 453d224d 61677069 655f5030 _NAME="Magpie_P0 + 0160 220a5449 455f4348 45434b53 554d5f30 ".TIE_CHECKSUM_0 + 0170 3d300a54 49455f43 4845434b 53554d5f =0.TIE_CHECKSUM_ + 0180 313d300a 5449455f 43484543 4b53554d 1=0.TIE_CHECKSUM + 0190 5f323d30 0a544945 5f434845 434b5355 _2=0.TIE_CHECKSU + 01a0 4d5f333d 300a5444 4b5f5041 54483d22 M_3=0.TDK_PATH=" + 01b0 220a0000 "... +Disassembly of section .lit4: + +004e8000 <.lit4>: + 4e8000: 0053fff0 00040020 00500950 00500b78 .S..... .P.P.P.x + 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00500b7c 00500b9c ATHR.....P.|.P.. + 4e80d0: 00500ba8 00500bc0 00500be0 0004fe00 .P...P...P...... + 4e80e0: 0005be00 00051e00 fffeefef 004e8970 .............N.p + 4e80f0: 13fffe00 a55a0000 00036000 00000b7c .....Z....`....| + 4e8100: 004e8984 008e1860 004e8998 008e189c .N.....`.N...... + 4e8110: 00500978 008e18fc fffeefff 004e89b4 .P.x.........N.. + 4e8120: 004e89b8 00500950 20000000 004e89e8 .N...P.P ....N.. + 4e8130: 004e8a08 004e8a18 004e8a28 004e8a38 .N...N...N.(.N.8 + 4e8140: 00530000 00010000 004e8a48 004e8a54 .S.......N.H.N.T + 4e8150: 004e8a70 004e89cc 004e89bc 008e1c14 .N.p.N...N...... + +004e8160 <.lit4+0x160>: + 4e8160: 00500954 004e8a8c 004e8ab0 004e8acc .P.T.N...N...N.. + 4e8170: 008e1c34 008e1c44 ...4...D + +004e8178 <.lit4+0x178>: + 4e8178: 008e1c74 ...t + +004e817c <.lit4+0x17c>: + 4e817c: 0050095c 000c3500 fff3cb00 004e8750 .P.\..5......N.P + 4e818c: 00500974 008e1d10 008e1cf8 008e1cac .P.t............ + 4e819c: 008e1d00 008e1cdc 008e1ccc 008e1ce8 ................ + 4e81ac: 008e1cf0 .... + +004e81b0 <.lit4+0x1b0>: + 4e81b0: 008e1d44 ...D + +004e81b4 <.lit4+0x1b4>: + 4e81b4: 00020000 10ff3e00 10ff2000 00000fff ......>... ..... + 4e81c4: 004e8afc 004e8aec 004e8af4 004e8b04 .N...N...N...N.. + 4e81d4: 00055e00 0003fe00 fffaffff 0001fe00 ..^............. + 4e81e4: 0000ffc1 10ff0000 10ff1e00 000c0000 ................ + 4e81f4: 04000000 008e1f04 008e1ebc 008e1e5c ...............\ + +004e8204 <.lit4+0x204>: + 4e8204: 008e1e24 ...$ + +004e8208 <.lit4+0x208>: + 4e8208: 00500980 008e2188 004e0600 004e0601 .P....!..N...N.. + 4e8218: 00500990 004e0771 008e2190 008e2298 .P...N.q..!...". + 4e8228: 008e2234 008e21b8 .."4..!. + +004e8230 <.lit4+0x230>: + 4e8230: 008e21f8 ..!. + +004e8234 <.lit4+0x234>: + 4e8234: 008e2318 008e6e48 008e6b64 008e6c5c ..#...nH..kd..l\ + +004e8244 <.lit4+0x244>: + 4e8244: 008e6adc ..j. + +004e8248 <.lit4+0x248>: + 4e8248: 01000000 fffe000f 004e0001 004e8b0c .........N...N.. + 4e8258: 00500a28 005006f8 004e8b44 004e8b78 .P.(.P...N.D.N.x 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..+. + +004e8318 <.lit4+0x318>: + 4e8318: 00500a34 00009c40 008e2c88 008e2c14 .P.4...@..,...,. + 4e8328: 008e2c58 008e2c04 ..,X..,. + +004e8330 <.lit4+0x330>: + 4e8330: 008e2c94 ..,. + +004e8334 <.lit4+0x334>: + 4e8334: 5f574454 5f535553 00500a38 07270e00 _WDT_SUS.P.8.'.. + 4e8344: 008e2d90 008e2d54 008e2d74 008e2d2c ..-...-T..-t..-, + 4e8354: 008e2db8 008e2d10 ..-...-. + +004e835c <.lit4+0x35c>: + 4e835c: 008e2ce4 ..,. + +004e8360 <.lit4+0x360>: + 4e8360: 00050e00 0001c200 00500a44 00002710 .........P.D..'. + 4e8370: 008e2e38 008e2e48 008e2df8 008e2ea0 ...8...H..-..... + 4e8380: 008e2ed4 008e2ec0 008e2ef4 008e2ec8 ................ + +004e8390 <.lit4+0x390>: + 4e8390: 008e2f1c ../. + +004e8394 <.lit4+0x394>: + 4e8394: 00050018 004e8c64 00050010 004e8c80 .....N.d.....N.. + 4e83a4: ffffdfff 00002000 00500708 004e8c8c ...... ..P...N.. + 4e83b4: 004e8ca0 004e8cb0 004e8cc0 008e3110 .N...N...N....1. + 4e83c4: 008e31a0 008e3164 008e3210 008e32b0 ..1...1d..2...2. + 4e83d4: 008e32dc 008e32f8 008e3308 008e31a8 ..2...2...3...1. + 4e83e4: 008e3320 008e3318 008e3328 008e30d8 ..3 ..3...3(..0. + 4e83f4: 008e300c 008e31e8 008e31bc 008e3024 ..0...1...1...0$ + 4e8404: 008e2fac 008e2fe8 ../.../. + +004e840c <.lit4+0x40c>: + 4e840c: 008e2fd4 ../. + +004e8410 <.lit4+0x410>: + 4e8410: 00500a54 008e33b0 008e33c4 008e33fc .P.T..3...3...3. + 4e8420: 008e341c 00500a60 00500a68 00500a78 ..4..P.`.P.h.P.x + 4e8430: 00500a80 004e8cd8 004e8cf0 00055a00 .P...N...N....Z. + 4e8440: 00055600 004e8d04 004e8d1c 00054e00 ..V..N...N....N. + 4e8450: 00010007 008e3430 008e34a0 008e3570 ......40..4...5p + 4e8460: 008e36e4 008e361c 008e367c 008e36c0 ..6...6...6|..6. + 4e8470: 008e36d0 008e348c 008e3484 008e351c ..6...4...4...5. + 4e8480: 008e3794 004e8d34 004e8d48 004e8d60 ..7..N.4.N.H.N.` + 4e8490: 004e8d74 004e8d88 .N.t.N.. + +004e8498 <.lit4+0x498>: + 4e8498: 00500a98 0000ff80 0000fe00 00500620 .P...........P. + 4e84a8: 00500730 007efdfb 00500780 00500770 .P.0.~...P...P.p + 4e84b8: 004e8d9c 004e01a0 004e01b0 004e01c0 .N...N...N...N.. + 4e84c8: 004e01e0 008e3f64 004e8ddc 004e8dfc .N....?d.N...N.. + 4e84d8: 08000000 004e8db4 004e8e08 f7ffffff .....N...N...... + 4e84e8: 004e0160 004e0120 00010080 004e8e28 .N.`.N. .....N.( + 4e84f8: 004e8e3c 00010001 0000c600 004e8e50 .N.<.........N.P + 4e8508: 004e8e60 004e8e78 004e8e88 004e8e98 .N.`.N.x.N...N.. + 4e8518: 00001010 004e8ea8 008e4270 008e4254 .....N....Bp..BT + 4e8528: 008e476c 008e4468 008e4530 008e41d0 ..Gl..Dh..E0..A. + 4e8538: 008e4058 008e3cd4 008e3d8c 008e3b2c ..@X..<...=...;, + 4e8548: 008e3b54 008e3bfc 008e3c44 008e3e64 ..;T..;...d + 4e8558: 008e4394 008e43a8 008e441c 008e4460 ..C...C...D...D` + 4e8568: 008e3a9c 008e3a7c 008e39ac 008e3988 ..:...:|..9...9. + 4e8578: 008e3954 008e3e08 008e4288 008e42f0 ..9T..>...B...B. + 4e8588: 008e3884 008e38ac ..8...8. + +004e8590 <.lit4+0x590>: + 4e8590: 008e4668 ..Fh + +004e8594 <.lit4+0x594>: + 4e8594: 00500ace 00500ad0 00500ad2 .P...P...P.. + +004e85a0 <.lit4+0x5a0>: + 4e85a0: 005007c0 00053000 00054000 008e4ce4 .P....0...@...L. + 4e85b0: 008e4d7c 008e4d2c 008e4da8 008e4dec ..M|..M,..M...M. + 4e85c0: 008e4e28 008e4e50 008e4dd0 008e4e6c ..N(..NP..M...Nl + +004e85d0 <.lit4+0x5d0>: + 4e85d0: 008e4e94 ..N. + +004e85d4 <.lit4+0x5d4>: + 4e85d4: 00500af8 008e4ef0 008e4f2c .P....N...O, + +004e85e0 <.lit4+0x5e0>: + 4e85e0: 008e4f4c ..OL + +004e85e4 <.lit4+0x5e4>: + 4e85e4: 00500b04 008e4f74 008e4fb0 008e4fc8 .P....Ot..O...O. + +004e85f4 <.lit4+0x5f4>: + 4e85f4: 008e4fd0 ..O. + +004e85f8 <.lit4+0x5f8>: + 4e85f8: 008e5114 008e5318 008e52e0 008e520c ..Q...S...R...R. + 4e8608: 008e51fc 008e5328 008e51f4 008e5494 ..Q...S(..Q...T. + 4e8618: 008e581c 008e57bc 008e56f4 008e577c ..X...W...V...W| + +004e8628 <.lit4+0x628>: + 4e8628: 0000ff00 004e8ebc 004e8950 004e8ec8 .....N...N.P.N.. + 4e8638: 004e8ed8 008e591c 008e5a50 008e5aa8 .N....Y...ZP..Z. + 4e8648: 008e5b68 008e5b90 008e59c0 008e5bc0 ..[h..[...Y...[. + 4e8658: 008e5974 008e5b70 008e5924 008e5964 ..Yt..[p..Y$..Yd + 4e8668: 008e5bf8 008e5cf0 008e5d2c ..[...\...], + +004e8674 <.lit4+0x674>: + 4e8674: 008e5dc0 ..]. + +004e8678 <.lit4+0x678>: + 4e8678: 0000fffc .... + +004e867c <.lit4+0x67c>: + 4e867c: 008e5eb0 008e5ef8 00500b0c 00500b14 ..^...^..P...P.. + 4e868c: 008e5ffc 004e8ee0 00001a00 ffffe5ff .._..N.......... + 4e869c: 00054100 00060000 004e8efc 00054200 ..A......N....B. + 4e86ac: 00054204 004e8f18 004e8f44 004e8f70 ..B..N...N.D.N.p + 4e86bc: 004e8f90 004e8fac 004e8fc4 004e8ff0 .N...N...N...N.. + 4e86cc: 004e900c .N.. + +004e86d0 <.lit4+0x6d0>: + 4e86d0: 008e6288 008e62a8 008e6300 008e6324 ..b...b...c...c$ + 4e86e0: 008e6334 008e62a0 00500b18 ..c4..b..P.. + +004e86ec <.lit4+0x6ec>: + 4e86ec: 008e6950 00500850 008e63b4 008e6928 ..iP.P.P..c...i( + +004e86fc <.lit4+0x6fc>: + 4e86fc: fffbfff0 .... + +004e8700 <.lit4+0x700>: + 4e8700: ff000000 00ff0000 000000ff 40404040 ............@@@@ + +004e8710 <.lit4+0x710>: + 4e8710: fefefeff .... + +004e8714 <.lit4+0x714>: + 4e8714: 80808080 .... +Disassembly of section .dport0.stack: + +0053f7f0 <_reserved_stack_start>: + ... +Disassembly of section .dport0.usb_in_rom: + +004e0100 : +_reserved_rom_data_start(): + 4e0100: 01120200 ffff40ff 0cf37010 02022010 ......@...p... . + 4e0110: 01300000 00000000 00000000 00000000 .0.............. + +004e0120 : + 4e0120: 0209003c 01018000 09fa0004 060000ff ...<............ + 4e0130: 00000507 02010200 07008205 00020002 ................ + 4e0140: 05070383 00400701 04054003 01000507 .....@....@..... + 4e0150: 02050200 07000605 00020002 00000000 ................ + +004e0160 : + 4e0160: 0209003c 01018000 09fa0004 060000ff ...<............ + 4e0170: 00000507 02010040 07008205 40020000 .......@....@... + 4e0180: 05070383 00400701 04054002 00000507 .....@....@..... + 4e0190: 02050040 07000605 40020000 00000000 ...@....@....... + +004e01a0 : + 4e01a0: 03040409 00000000 00000000 00000000 ................ + +004e01b0 : + 4e01b0: 03100041 00540048 00450052 004f0053 ...A.T.H.E.R.O.S + +004e01c0 : + 4e01c0: 03180055 00530042 0032002e 00300020 ...U.S.B.2...0. + 4e01d0: 0057004c 0041004e 00000000 00000000 .W.L.A.N........ + +004e01e0 : + 4e01e0: 030c0031 00320033 00340035 ...1.2.3.4.5 +Disassembly of section .dport0.data: + +00500000 <_indir_tbl>: + ... +Disassembly of section .rodata: + +004e8720 <_rom_store_table>: + 4e8720: 00500400 00500950 004e0260 00000000 .P...P.P.N.`.... + ... + +004e8740 : + 4e8740: 55aa55aa aa55aa55 ffffffff 00000000 U.U..U.U........ + +004e8750 : + 4e8750: 00000000 00989680 00000000 00000000 ................ + 4e8760: 00000000 00000001 01312d00 00000000 .........1-..... + ... + 4e8778: 00000002 02625a00 00000000 00000000 .....bZ......... + 4e8788: 00000000 ffffffff 00000000 00000000 ................ + ... + +004e87a0 : + 4e87a0: 00001b62 ...b + +004e87a4 : + 4e87a4: 004e9034 .N.4 + +004e87a8 : + 4e87a8: 1b620000 .b.. + +004e87ac : + 4e87ac: 00000020 ... + +004e87b0 : + 4e87b0: 05 . + +004e87b1 : + 4e87b1: 01 . + +004e87b2 : + 4e87b2: 01 . + +004e87b3 : + 4e87b3: 01 . + +004e87b4 : + 4e87b4: 01 . + +004e87b5 : + 4e87b5: 01 . + +004e87b6 : + 4e87b6: 01 . + +004e87b7 : + 4e87b7: 01 . + +004e87b8 : + 4e87b8: 01 . + +004e87b9 : + 4e87b9: 01 . + +004e87ba : + 4e87ba: 02 . + +004e87bb : + 4e87bb: 01 . + +004e87bc : + 4e87bc: 01 . + +004e87bd : + 4e87bd: 01 . + +004e87be : + 4e87be: 01 . + +004e87bf : + 4e87bf: 01 . + +004e87c0 : + 4e87c0: 01 . + +004e87c1 : + 4e87c1: 01 . + +004e87c2 : + 4e87c2: 0100 .. + +004e87c4 : + 4e87c4: 00040000 .... + +004e87c8 : + 4e87c8: 0002230f ..#. + +004e87cc : + 4e87cc: c280dbff .... + +004e87d0 : + 4e87d0: 0d02230f ..#. + +004e87d4 : + 4e87d4: 000008a2 .... + +004e87d8 : + 4e87d8: 004e903c .N.< + +004e87dc : + 4e87dc: 000008a2 .... + +004e87e0 : + 4e87e0: 000008a2 .... + +004e87e4 : + 4e87e4: 01 . + +004e87e5 : + 4e87e5: 01 . + +004e87e6 : + 4e87e6: 01 . + +004e87e7 : + 4e87e7: 01 . + +004e87e8 : + 4e87e8: 01 . + +004e87e9 : + 4e87e9: 040000 ... + +004e87ec : + 4e87ec: 0000001d .... + +004e87f0 : + 4e87f0: 0000001d .... + +004e87f4 : + 4e87f4: 01 . + +004e87f5 : + 4e87f5: 01 . + +004e87f6 : + 4e87f6: 01 . + +004e87f7 : + 4e87f7: 01 . + +004e87f8 : + 4e87f8: 01 . + +004e87f9 : + 4e87f9: 010000 ... + +004e87fc : + 4e87fc: 00000000 .... + +004e8800 : + 4e8800: 00000000 .... + +004e8804 : + 4e8804: 00000000 .... + +004e8808 : + 4e8808: 00800000 .... + +004e880c : + 4e880c: 00800000 .... + +004e8810 : + 4e8810: 00400000 .@.. + +004e8814 : + 4e8814: 00000000 .... + +004e8818 : + 4e8818: 00000000 .... + +004e881c : + 4e881c: 00000000 .... + +004e8820 : + 4e8820: 00400000 .@.. + +004e8824 : + 4e8824: 00400000 .@.. + +004e8828 : + 4e8828: 00400000 .@.. + +004e882c : + 4e882c: 00000000 .... + +004e8830 : + 4e8830: 00000000 .... + +004e8834 : + ... + +004e8840 : + 4e8840: 01020202 02020202 02020202 02020203 ................ + 4e8850: 03030500 00000000 00000000 00000000 ................ + 4e8860: 52414d20 6661696c 0a0d0000 46617461 RAM fail....Fata + 4e8870: 6c206578 63657074 696f6e20 28256429 l exception (%d) + 4e8880: 3a207063 3d307825 78206261 64766164 : pc=0x%x badvad + 4e8890: 64723d30 78257820 64756d70 20617265 dr=0x%x dump are + 4e88a0: 613d3078 25780a00 2d41312d 0a0d0000 a=0x%x..-A1-.... + 4e88b0: 6d697361 6c69676e 65645f6c 6f61640a misaligned_load. + 4e88c0: 0d000000 46617461 6c206578 63657074 ....Fatal except + 4e88d0: 696f6e20 28256429 3a200970 633d3078 ion (%d): .pc=0x + 4e88e0: 2578200a 0d096261 64766164 64723d30 %x ...badvaddr=0 + 4e88f0: 78257820 0a0d0964 756d7020 61726561 x%x ...dump area + 4e8900: 3d307825 780a0000 09657063 313d3078 =0x%x....epc1=0x + 4e8910: 25782c20 65706332 3d307825 782c2065 %x, epc2=0x%x, e + 4e8920: 7063333d 30782578 2c206570 63343d30 pc3=0x%x, epc4=0 + 4e8930: 7825780a 00000000 30782530 38782c20 x%x.....0x%08x, + 4e8940: 30782530 38782c20 30782530 38782c20 0x%08x, 0x%08x, + 4e8950: 0a0d0000 202d2025 735f7665 723a2025 .... - %s_ver: % + 4e8960: 78202d20 0a0a0d00 61736963 00000000 x - ....asic.... + 4e8970: 64696476 69642066 726f6d20 6f776c20 didvid from owl + 4e8980: 0a000000 64656661 756c7420 64696476 ....default didv + 4e8990: 6964200a 00000000 382e2077 61697420 id .....8. wait + 4e89a0: 666f7220 646f776e 6c6f6164 2e2e2e2e for download.... + 4e89b0: 200a0d00 32000000 33000000 20332e31 ...2...3... 3.1 + 4e89c0: 206e6f20 70617463 680a0d00 20332e31 no patch... 3.1 + 4e89d0: 206e6f20 65657020 6f722063 6f727275 no eep or corru + 4e89e0: 70740a0d 00000000 20332e31 20534e53 pt...... 3.1 SNS + 4e89f0: 543a2065 65702069 6e697420 6661696c T: eep init fail + 4e8a00: 6564210a 0d000000 342e2077 64742073 ed!.....4. wdt s + 4e8a10: 74617274 0a0d0000 342e2077 61726d20 tart....4. warm + 4e8a20: 73746172 740a0d00 342e2063 6f6c6420 start...4. cold + 4e8a30: 73746172 740a0d00 352e2068 69662028 start...5. hif ( + 4e8a40: 2564290a 00000000 53544152 542e2e2e %d).....START... + 4e8a50: 2e0a0000 524f4d3e 3a6d6469 6f20646f ....ROM>:mdio do + 4e8a60: 776e6c6f 61642072 65616479 0a000000 wnload ready.... + 4e8a70: 362e2053 4e53543a 20686f73 74696620 6. SNST: hostif + 4e8a80: 636f7272 7570740a 0d000000 52414d20 corrupt.....RAM + 4e8a90: 616c6c6f 63617469 6f6e2028 25642062 allocation (%d b + 4e8aa0: 79746573 29206661 696c6564 210a0000 ytes) failed!... + 4e8ab0: 414c4c4f 4352414d 20437572 72656e74 ALLOCRAM Current + 4e8ac0: 20416464 72203078 25780a00 414c4c4f Addr 0x%x..ALLO + 4e8ad0: 4352414d 2052656d 61696e69 6e672042 CRAM Remaining B + 4e8ae0: 79746573 2025640a 00000000 2d453132 ytes %d.....-E12 + 4e8af0: 2d000000 2d453130 2d000000 2d453131 -...-E10-...-E11 + 4e8b00: 2d000000 2d453133 2d000000 4d697361 -...-E13-...Misa + 4e8b10: 6c69676e 6564206c 6f61643a 2070633d ligned load: pc= + 4e8b20: 30782578 20626164 76616464 723d3078 0x%x badvaddr=0x + 4e8b30: 25782064 756d7020 61726561 3d307825 %x dump area=0x% + 4e8b40: 780a0000 61737365 7274696f 6e206661 x...assertion fa + 4e8b50: 696c6564 3f207063 3d307825 782c206c iled? pc=0x%x, l + 4e8b60: 696e653d 25642c20 64756d70 20617265 ine=%d, dump are + 4e8b70: 613d3078 25780a00 54617267 65742049 a=0x%x..Target I + 4e8b80: 443a2030 78257820 28256429 0a000000 D: 0x%x (%d).... + 4e8b90: 44656275 6720496e 666f3a00 30782530 Debug Info:.0x%0 + 4e8ba0: 38782000 30313233 34353637 38390000 8x .0123456789.. + 4e8bb0: 30313233 34353637 38396162 63646566 0123456789abcdef + 4e8bc0: 00000000 30313233 34353637 38394142 ....0123456789AB + 4e8bd0: 43444546 00000000 3c6e756c 6c3e0000 CDEF...... + 4e8be0: 09737a3a 2025642c 206c643a 2025702c .sz: %d, ld: %p, + 4e8bf0: 20666e3a 2025700d 00000000 21696e76 fn: %p.....!inv + 4e8c00: 616c6964 2064706f 72742061 64647265 alid dport addre + 4e8c10: 73732c20 30782530 38780a0d 00000000 ss, 0x%08x...... + 4e8c20: 63702025 64206279 74657320 66726f6d cp %d bytes from + 4e8c30: 20307825 30387820 746f2030 78253038 0x%08x to 0x%08 + 4e8c40: 78000000 702e6f66 743a2030 78253034 x...p.oft: 0x%04 + 4e8c50: 782c2070 2e737a20 3a203078 25303478 x, p.sz : 0x%04x + 4e8c60: 0a000000 57616974 696e6720 666f7220 ....Waiting for + 4e8c70: 686f7374 20726573 65742e2e 00000000 host reset...... + 4e8c80: 72656365 69766564 2e0a0000 42616420 received....Bad + 4e8c90: 456e6769 6e65206e 756d6265 720a0000 Engine number... + 4e8ca0: 456d7074 79205258 20526561 700a0000 Empty RX Reap... + 4e8cb0: 456d7074 79205458 20526561 70200a00 Empty TX Reap .. + 4e8cc0: 496e7661 6c696420 50697065 206e756d Invalid Pipe num + 4e8cd0: 6265720a 00000000 0a0d093d 3e5b646e ber........=>[dn + 4e8ce0: 515d2030 78253038 78200a5b 00000000 Q] 0x%08x .[.... + 4e8cf0: 093d3e5b 7570515d 20307825 30387820 .=>[upQ] 0x%08x + 4e8d00: 0a5b0000 093d3e5b 68702064 6e515d20 .[...=>[hp dnQ] + 4e8d10: 30782530 3878200a 5b000000 093d3e5b 0x%08x .[....=>[ + 4e8d20: 6d702064 6e515d20 30782530 3878200a mp dnQ] 0x%08x . + 4e8d30: 5b000000 0a0d5b68 7020646e 515d2030 [.....[hp dnQ] 0 + 4e8d40: 78253038 782c2000 444d4120 54524143 x%08x, .DMA TRAC + 4e8d50: 45203078 25303878 0a0d2020 20205b00 E 0x%08x.. [. + 4e8d60: 0a0d5b6d 7020646e 515d2030 78253038 ..[mp dnQ] 0x%08 + 4e8d70: 782c2000 0a0d5b64 6e515d20 30782530 x, ...[dnQ] 0x%0 + 4e8d80: 38782c20 00000000 0a0a0d5b 7570515d 8x, .......[upQ] + 4e8d90: 20307825 3038782c 20000000 2d206375 0x%08x, ...- cu + 4e8da0: 73746f6d 20757362 20636f6e 6669670a stom usb config. + 4e8db0: 00000000 095b6355 53425f52 45515f44 .....[cUSB_REQ_D + 4e8dc0: 4f574e4c 4f41445d 3a203078 25303878 OWNLOAD]: 0x%08x + 4e8dd0: 2c202530 32780a0d 00000000 090a0d3d , %02x.........= + 4e8de0: 3d3e5b63 5553425f 5245515f 434f4d50 =>[cUSB_REQ_COMP + 4e8df0: 5d3a2030 78253038 780a0d00 636b7375 ]: 0x%08x...cksu + 4e8e00: 6d3d2578 00000000 56656e64 6f72436d m=%x....VendorCm + 4e8e10: 643a2044 6f776e6c 6f616443 6f6d706c d: DownloadCompl + 4e8e20: 65746521 0a000000 7a665265 73657455 ete!....zfResetU + 4e8e30: 53424649 464f0a0d 00000000 7a665475 SBFIFO......zfTu + 4e8e40: 726e4f66 66506f77 65720a0d 00000000 rnOffPower...... + 4e8e50: 47656e65 72617465 20457665 6e740a00 Generate Event.. + 4e8e60: 215b534f 55524345 5f305d20 62697437 ![SOURCE_0] bit7 + 4e8e70: 206f6e0a 0d000000 21555342 20726573 on.....!USB res + 4e8e80: 65740a0d 00000000 21555342 20737573 et......!USB sus + 4e8e90: 70656e64 0a0d0000 21555342 20726573 pend....!USB res + 4e8ea0: 756d650a 0d000000 362e2075 73625f68 ume.....6. usb_h + 4e8eb0: 636c6b20 7264790a 0d000000 30782530 clk rdy.....0x%0 + 4e8ec0: 38782854 295d0000 30782530 38782825 8x(T)]..0x%08x(% + 4e8ed0: 63292d3e 00000000 0a0d2020 20000000 c)->...... ... + 4e8ee0: 6d69692d 6d64696f 202d2072 65736574 mii-mdio - reset + 4e8ef0: 202d2073 74617274 200a0000 6d69692d - start ...mii- + 4e8f00: 6d64696f 202d2072 65736574 202d2065 mdio - reset - e + 4e8f10: 6e64200a 00000000 73746172 74656420 nd .....started + 4e8f20: 72656365 6976696e 67206279 74657320 receiving bytes + 4e8f30: 746f2025 78206c65 6e677468 2025640a to %x length %d. + 4e8f40: 00000000 636f6d70 6c657465 64207265 ....completed re + 4e8f50: 63656976 696e6720 62797465 7320746f ceiving bytes to + 4e8f60: 20257820 6c656e67 74682025 640a0000 %x length %d... + 4e8f70: 4669726d 77617265 20446f77 6e6c6f61 Firmware Downloa + 4e8f80: 64206c65 6e677468 20307825 780a0000 d length 0x%x... + 4e8f90: 4669726d 77617265 20457865 63204164 Firmware Exec Ad + 4e8fa0: 64726573 73203078 25780a00 4669726d dress 0x%x..Firm + 4e8fb0: 77617265 20636865 636b7375 6d203078 ware checksum 0x + 4e8fc0: 25780a00 4669726d 77617265 20636865 %x..Firmware che + 4e8fd0: 636b7375 6d206661 696c6564 202d2072 cksum failed - r + 4e8fe0: 65206e65 676f7469 6174696e 67200a00 e negotiating .. + 4e8ff0: 4669726d 77617265 20446f77 6e6c6f61 Firmware Downloa + 4e9000: 64206973 20676f6f 64200a00 434f4d4d d is good ..COMM + 4e9010: 414e4420 544f2053 54415254 20464952 AND TO START FIR + 4e9020: 4d574152 45205245 43454956 4544200a MWARE RECEIVED . + 4e9030: 00000000 372e312e 30000000 4c58322e ....7.1.0...LX2. + 4e9040: 312e3000 00500400 00500400 00500950 1.0..P...P...P.P + 4e9050: 00500b78 .P.x +Disassembly of section .data: + +00500400 <_xtos_exc_handler_table>: +_xtos_exc_handler_table(): + 500400: 008e6928 008e1104 008e6928 008e6928 ..i(......i(..i( + 500410: 008e1174 008e102c 008e6928 008e6928 ...t...,..i(..i( + 500420: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500430: 008e63ac 008e63ac 008e63ac 008e63ac ..c...c...c...c. + 500440: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500450: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500460: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500470: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500480: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 500490: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004a0: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004b0: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004c0: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004d0: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004e0: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + 5004f0: 008e6928 008e6928 008e6928 008e6928 ..i(..i(..i(..i( + +00500500 <_xtos_enabled>: +_xtos_intstruct(): + 500500: 00000000 .... + +00500504 <_xtos_vpri_enabled>: + 500504: ffffffff .... + +00500508 <_xtos_interrupt_table>: +_xtos_interrupt_table(): + 500508: 008e6920 00000012 008e6920 00000011 ..i ......i .... + 500518: 008e6920 00000010 008e6920 0000000f ..i ......i .... + 500528: 008e6920 0000000e 008e6920 0000000d ..i ......i .... + 500538: 008e6920 0000000c 008e6920 0000000b ..i ......i .... + 500548: 008e6920 0000000a 008e6920 00000009 ..i ......i .... + 500558: 008e6920 00000008 008e6920 00000007 ..i ......i .... + 500568: 008e6920 00000006 008e6920 00000005 ..i ......i .... + 500578: 008e6920 00000004 008e6920 00000003 ..i ......i .... + 500588: 008e6920 00000002 008e6920 00000001 ..i ......i .... + 500598: 008e6920 00000000 ..i .... + +005005a0 <_xtos_interrupt_mask_table>: +_xtos_interrupt_mask_table(): + 5005a0: fffffffe 00040000 fffffffe 00020000 ................ + 5005b0: fffffffe 00010000 fffffffe 00008000 ................ + 5005c0: fffffffe 00004000 fffffffe 00002000 ......@....... . + 5005d0: fffffffe 00001000 fffffffe 00000800 ................ + 5005e0: fffffffe 00000400 fffffffe 00000200 ................ + 5005f0: fffffffe 00000100 fffffffe 00000080 ................ + 500600: fffffffe 00000040 fffffffe 00000020 .......@....... + 500610: fffffffe 00000010 fffffffe 00000008 ................ + 500620: fffffffe 00000004 fffffffe 00000002 ................ + 500630: fffffffe 00000001 00000000 00000000 ................ + +00500640 : + 500640: 008e2320 0050000c 008e2488 00500020 ..# .P....$..P. + 500650: 008e29bc 00500044 008e2f5c 0050004c ..)..P.D../\.P.L + 500660: 008e4858 00500070 008e22f8 00500118 ..HX.P.p.."..P.. + 500670: 008e2cc4 00500104 008e1d6c 005000e0 ..,..P.....l.P.. + 500680: 008e1c98 00500144 008e2b08 00500150 .....P.D..+..P.P + 500690: 008e2dd0 00500160 008e216c 0050017c ..-..P.`..!l.P.| + 5006a0: 00000000 0050006c 008e2b2c 0050018c .....P.l..+,.P.. + 5006b0: 008e2be4 005001a4 008e5010 00500294 ..+..P....P..P.. + 5006c0: 008e4f60 00500280 008e1548 005001c0 ..O`.P.....H.P.. + 5006d0: 008e337c 00500328 008e4eb8 005002f4 ..3|.P.(..N..P.. + 5006e0: 008e6264 00500264 008e4848 00500258 ..bd.P.d..HH.P.X + 5006f0: 008e5c58 005002b4 ..\X.P.. + +005006f8 : + 5006f8: 00000001 .... + +005006fc : + 5006fc: 00000001 .... + +00500700 <_putc>: + 500700: 008e24b8 ..$. + +00500704 : + 500704: 00000000 .... + +00500708 : + ... + +00500720 : + 500720: 00020004 00080000 00000000 00000000 ................ + +00500730 : + ... + 500738: aa00aa00 aaaaaaaa eeaaaaaa eeeeeeee ................ + 500748: feeeeeee ffffffff ffffffff 7fffffff ................ + 500758: f7efdfbf 7efcfdfb fdfbdfbf 00000000 ....~........... + ... + +00500770 : + ... + +00500780 : + 500780: 07090000 00000000 00000000 00000000 ................ + ... + +005007c0 : + 5007c0: 00053000 00000800 00000000 00000000 ..0............. + ... + 5007d8: 00053000 00000900 00000000 00000000 ..0............. + ... + 5007f0: 00053000 00000a00 00000000 00000000 ..0............. + ... + 500808: 00053000 00000b00 00000000 00000000 ..0............. + ... + 500820: 00053000 00000c00 00000000 00000000 ..0............. + ... + 500838: 00053000 00000d00 00000000 00000000 ..0............. + ... + +00500850 <_xtos_c_handler_table>: +_xtos_c_handler_table(): + 500850: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500860: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500870: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500880: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500890: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008a0: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008b0: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008c0: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008d0: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008e0: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 5008f0: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500900: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500910: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500920: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500930: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP + 500940: 008e6950 008e6950 008e6950 008e6950 ..iP..iP..iP..iP +Disassembly of section .bss: + +00500950 : + 500950: 00000000 .... + +00500954 : + 500954: 00000000 .... + +00500958 : + 500958: 00000000 .... + +0050095c : + 50095c: 00000000 .... + +00500960 : + 500960: 00000000 .... + +00500964 : + 500964: 00000000 .... + +00500968 : + 500968: 00000000 .... + +0050096c : + 50096c: 00000000 .... + +00500970 : + 500970: 00000000 .... + +00500974 : + 500974: 00000000 .... + +00500978 : + ... + +0050097a : + 50097a: 00000000 00000000 ...... + +00500980 : + ... + +00500990 : + ... + +00500a28 : + 500a28: 00000000 .... + +00500a2c : + 500a2c: 00000000 .... + +00500a30 : + 500a30: 00000000 .... + +00500a34 : + 500a34: 00000000 .... + +00500a38 : + ... + +00500a44 : + ... + +00500a54 : + ... + +00500a98 : + ... + +00500aa4 : + ... + +00500ab4 : + 500ab4: 00000000 .... + +00500ab8 : + 500ab8: 00000000 .... + +00500abc : + 500abc: 00000000 .... + +00500ac0 : + 500ac0: 00000000 .... + +00500ac4 : + 500ac4: 00000000 .... + +00500ac8 : + 500ac8: 00000000 .... + +00500acc : + ... + +00500ace : + ... + +00500ad0 : + ... + +00500ad2 : + ... + +00500ad4 : + 500ad4: 00000000 .... + +00500ad8 : + 500ad8: 00000000 .... + +00500adc : + 500adc: 00000000 .... + +00500ae0 : + 500ae0: 00000000 .... + +00500ae4 : + 500ae4: 00000000 .... + +00500ae8 : + ... + +00500af0 : + ... + +00500af8 : + ... + +00500b04 : + ... + +00500b0c : + ... + +00500b18 : + ... + +00500b44 : + 500b44: 00000000 .... + +00500b48 : + 500b48: 00000000 .... + +00500b4c : + ... + +00500b4d : + ... + +00500b4e : + ... + +00500b4f : + ... + +00500b50 : + 500b50: 00000000 .... + +00500b54 : + 500b54: 00000000 .... + +00500b58 : + 500b58: 00000000 .... + +00500b5c : + 500b5c: 00000000 .... + +00500b60 : + 500b60: 00000000 .... + +00500b64 : + ... + +00500b65 : + ... + +00500b66 : + ... + +00500b67 : + ... + +00500b68 : + ... + +00500b69 : + ... + +00500b6a : + ... + +00500b6b : + ... + +00500b6c : + ... + +00500b6d : + ... + +00500b6e : + ... + +00500b6f : + ... + +00500b70 : + ... +Disassembly of section .ResetVector.text: + +008e0000 <_ResetVector>: +_ResetVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:56 + 8e0000: 60001c j 8e0020 <_ResetHandler> + +008e0003 <_ResetVector+0x3>: + ... + +008e0004 <_ResetVector+0x4>: + 8e0004: 008e0800 22221221 e0000000 008e0063 ...."".!.......c + 8e0014: 004e8720 00528001 .N. .R.. + +008e001c <_ResetVector+0x1c>: + 8e001c: 00000000 .... + +008e0020 <_ResetHandler>: +_ResetHandler(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:73 + 8e0020: c000 movi.n a0, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:76 + 8e0022: 00e431 wsr.intenable a0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:128 + 8e0025: 12fff7 l32r a2, 8e0004 <_ResetVector_text_start+0x4> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:129 + 8e0028: 02e731 wsr.vecbase a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:133 + 8e002b: 021600 rsil a2, 1 +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:161 + 8e002e: 12fff6 l32r a2, 8e0008 <_ResetVector_text_start+0x8> +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:396 + 8e0031: 15fff6 l32r a5, 8e000c <_ResetVector_text_start+0xc> + 8e0034: 16fff7 l32r a6, 8e0010 <_ResetVector_text_start+0x10> + 8e0037: c030 movi.n a3, 0 + 8e0039: d720 mov.n a7, a2 + 8e003b: 056601 and a6, a6, a5 + 8e003e: 600021 j 8e0063 <_ResetHandler+0x43> + +008e0041 <_ResetHandler+0x21>: + ... + +008e0050 <_ResetHandler+0x30>: +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:281 + 8e0050: 043605 witlb a4, a3 + 8e0053: 000200 isync + 8e0056: d30f nop.n + +008e0058 <_ResetHandler+0x38>: + 8e0058: d30f nop.n + 8e005a: 753114 beq a3, a5, 8e0072 <_ResetHandler+0x52> + +008e005d <_ResetHandler+0x3d>: + 8e005d: 074714 srli a7, a7, 4 + 8e0060: 05330c sub a3, a3, a5 +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:304 + 8e0063: 070443 extui a4, a7, 0, 4 + 8e0066: 7631e6 beq a3, a6, 8e0050 <_ResetHandler+0x30> + 8e0069: 043605 witlb a4, a3 + 8e006c: 7539ed bne a3, a5, 8e005d <_ResetHandler+0x3d> + 8e006f: 000200 isync + +008e0072 <_ResetHandler+0x52>: +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:396 + 8e0072: 15ffe6 l32r a5, 8e000c <_ResetVector_text_start+0xc> + 8e0075: c030 movi.n a3, 0 + 8e0077: d720 mov.n a7, a2 + 8e0079: 600006 j 8e0083 <_ResetHandler+0x63> + +008e007c <_ResetHandler+0x5c>: + ... + +008e007d <_ResetHandler+0x5d>: + 8e007d: 074714 srli a7, a7, 4 + 8e0080: 05330c sub a3, a3, a5 +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:343 + 8e0083: 070443 extui a4, a7, 0, 4 + 8e0086: 043e05 wdtlb a4, a3 + 8e0089: 7539f0 bne a3, a5, 8e007d <_ResetHandler+0x5d> + 8e008c: 030200 dsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:172 + 8e008f: 12ffe1 l32r a2, 8e0014 <_ResetVector_text_start+0x14> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:173 + 8e0092: ca20 beqz.n a2, 8e00b6 + +008e0094 : +unpack(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:174 + 8e0094: 8320 l32i.n a3, a2, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:175 + 8e0096: 8421 l32i.n a4, a2, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:176 + 8e0098: 8522 l32i.n a5, a2, 8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:177 + 8e009a: 222c0c addi a2, a2, 12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:178 + 8e009d: 743b0f bgeu a3, a4, 8e00b0 + +008e00a0 : +uploop(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:179 + 8e00a0: 8650 l32i.n a6, a5, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:180 + 8e00a2: b455 addi.n a5, a5, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:181 + 8e00a4: 9630 s32i.n a6, a3, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:182 + 8e00a6: b433 addi.n a3, a3, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:183 + 8e00a8: 7433f4 bltu a3, a4, 8e00a0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:184 + 8e00ab: 63ffe5 j 8e0094 + +008e00ae : + ... + +008e00b0 : +upnext(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:185 + 8e00b0: 653fe0 bnez a3, 8e0094 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:186 + 8e00b3: 655fdd bnez a5, 8e0094 + +008e00b6 : +unpackdone(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:254 + 8e00b6: 12ffd8 l32r a2, 8e0018 <_ResetVector_text_start+0x18> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:255 + 8e00b9: 020531 wsr.litbase a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:256 + 8e00bc: 010200 rsync + +008e00bf : +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:266 + 8e00bf: 000200 isync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:281 + 8e00c2: c011 movi.n a1, 1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:282 + 8e00c4: 014931 wsr.windowstart a1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:286 + 8e00c7: 004831 wsr.windowbase a0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:287 + 8e00ca: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:288 + 8e00cd: c000 movi.n a0, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:353 + 8e00cf: 140004 l32r a4, 4e8010 <_lit4_start+0x10> + 8e00d2: 04d231 wsr.excsave2 a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:354 + 8e00d5: 140005 l32r a4, 4e8014 <_lit4_start+0x14> + 8e00d8: 04d331 wsr.excsave3 a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:372 + 8e00db: 5003c9 call0 8e1000 <_iram0_text_end> +Disassembly of section .WindowVectors.text: + +008e0800 <_WindowOverflow4>: +_WindowOverflow4(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:105 + 8e0800: 005c94 s32e a0, a5, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:106 + 8e0803: 015d94 s32e a1, a5, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:107 + 8e0806: 025e94 s32e a2, a5, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:108 + 8e0809: 035f94 s32e a3, a5, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:110 + 8e080c: 004300 rfwo + +008e080f <_WindowOverflow4+0xf>: + ... + +008e0840 <_WindowUnderflow4>: +_WindowUnderflow4(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:133 + 8e0840: 005c90 l32e a0, a5, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:134 + 8e0843: 015d90 l32e a1, a5, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:135 + 8e0846: 025e90 l32e a2, a5, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:136 + 8e0849: 035f90 l32e a3, a5, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:138 + 8e084c: 005300 rfwu + +008e084f <_WindowUnderflow4+0xf>: + ... + +008e0880 <_WindowOverflow8>: +_WindowOverflow8(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:169 + 8e0880: 009c94 s32e a0, a9, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:170 + 8e0883: 001d90 l32e a0, a1, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:171 + 8e0886: 019d94 s32e a1, a9, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:172 + 8e0889: 029e94 s32e a2, a9, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:173 + 8e088c: 039f94 s32e a3, a9, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:174 + 8e088f: 040894 s32e a4, a0, -32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:175 + 8e0892: 050994 s32e a5, a0, -28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:176 + 8e0895: 060a94 s32e a6, a0, -24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:177 + 8e0898: 070b94 s32e a7, a0, -20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:179 + 8e089b: 004300 rfwo + +008e089e <_WindowOverflow8+0x1e>: + ... + +008e08c0 <_WindowUnderflow8>: +_WindowUnderflow8(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:210 + 8e08c0: 009c90 l32e a0, a9, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:211 + 8e08c3: 019d90 l32e a1, a9, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:212 + 8e08c6: 029e90 l32e a2, a9, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:213 + 8e08c9: 071d90 l32e a7, a1, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:214 + 8e08cc: 039f90 l32e a3, a9, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:215 + 8e08cf: 047890 l32e a4, a7, -32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:216 + 8e08d2: 057990 l32e a5, a7, -28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:217 + 8e08d5: 067a90 l32e a6, a7, -24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:218 + 8e08d8: 077b90 l32e a7, a7, -20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:220 + 8e08db: 005300 rfwu + +008e08de <_WindowUnderflow8+0x1e>: + ... + +008e0900 <_WindowOverflow12>: +_WindowOverflow12(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:255 + 8e0900: 00dc94 s32e a0, a13, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:256 + 8e0903: 001d90 l32e a0, a1, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:257 + 8e0906: 01dd94 s32e a1, a13, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:258 + 8e0909: 02de94 s32e a2, a13, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:259 + 8e090c: 03df94 s32e a3, a13, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:260 + 8e090f: 040494 s32e a4, a0, -48 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:261 + 8e0912: 050594 s32e a5, a0, -44 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:262 + 8e0915: 060694 s32e a6, a0, -40 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:263 + 8e0918: 070794 s32e a7, a0, -36 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:264 + 8e091b: 080894 s32e a8, a0, -32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:265 + 8e091e: 090994 s32e a9, a0, -28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:266 + 8e0921: 0a0a94 s32e a10, a0, -24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:267 + 8e0924: 0b0b94 s32e a11, a0, -20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:269 + 8e0927: 004300 rfwo + +008e092a <_WindowOverflow12+0x2a>: + ... + +008e0940 <_WindowUnderflow12>: +_WindowUnderflow12(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:304 + 8e0940: 00dc90 l32e a0, a13, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:305 + 8e0943: 01dd90 l32e a1, a13, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:306 + 8e0946: 02de90 l32e a2, a13, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:307 + 8e0949: 0b1d90 l32e a11, a1, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:308 + 8e094c: 03df90 l32e a3, a13, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:309 + 8e094f: 04b490 l32e a4, a11, -48 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:310 + 8e0952: 05b590 l32e a5, a11, -44 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:311 + 8e0955: 06b690 l32e a6, a11, -40 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:312 + 8e0958: 07b790 l32e a7, a11, -36 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:313 + 8e095b: 08b890 l32e a8, a11, -32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:314 + 8e095e: 09b990 l32e a9, a11, -28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:315 + 8e0961: 0aba90 l32e a10, a11, -24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:316 + 8e0964: 0bbb90 l32e a11, a11, -20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:318 + 8e0967: 005300 rfwu +Disassembly of section .KernelExceptionVector.text: + +008e0d40 <_KernelExceptionVector>: +_KernelExceptionVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/kernel-vector.S:43 + 8e0d40: 001400 break 1, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/kernel-vector.S:51 + 8e0d43: 63fff9 j 8e0d40 <_KernelExceptionVector_text_start> +Disassembly of section .UserExceptionVector.text: + +008e0e20 <_UserExceptionVector>: +_UserExceptionVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:25 + 8e0e20: 211c90 addi a1, a1, -112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:26 + 8e0e23: 9214 s32i.n a2, a1, 16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:27 + 8e0e25: 9315 s32i.n a3, a1, 20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:28 + 8e0e27: 130006 l32r a3, 4e8018 <_lit4_start+0x18> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:29 + 8e0e2a: 02e830 rsr.exccause a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:31 + 8e0e2d: 03230a addx4 a3, a2, a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:32 + 8e0e30: 8330 l32i.n a3, a3, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:33 + 8e0e32: 9416 s32i.n a4, a1, 24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:34 + 8e0e34: 0a3000 jx a3 +Disassembly of section .DoubleExceptionVector.text: + +008e0f20 <_DoubleExceptionVector>: +_DoubleExceptionVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/double-vector.S:47 + 8e0f20: 041400 break 1, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/double-vector.S:55 + 8e0f23: 63fff9 j 8e0f20 <_DoubleExceptionVector_text_start> +Disassembly of section .Level2InterruptVector.text: + +008e0a20 <_Level2Vector>: +_Level2Vector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-vector.S:37 + 8e0a20: 02d216 xsr.excsave2 a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-vector.S:38 + 8e0a23: 0a2000 jx a2 +Disassembly of section .Level3InterruptVector.text: + +008e0b20 <_Level3Vector>: +_Level3Vector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-vector.S:37 + 8e0b20: 02d316 xsr.excsave3 a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-vector.S:38 + 8e0b23: 0a2000 jx a2 +Disassembly of section .DebugExceptionVector.text: + +008e0c20 <_DebugExceptionVector>: +_DebugExceptionVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/debug-vector.S:42 + 8e0c20: 004700 waiti 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/debug-vector.S:44 + 8e0c23: 63fff9 j 8e0c20 <_DebugExceptionVector_text_start> +Disassembly of section .NMIExceptionVector.text: + +008e0ce4 <_NMIExceptionVector>: +_NMIExceptionVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/nmi-vector.S:40 + 8e0ce4: 015300 rfi 5 +Disassembly of section .text: + +008e1000 <_start>: +_stext(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:49 + 8e1000: 200a00 movi a0, 0 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+/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:71 + 8e101a: 9060 s32i.n a0, a6, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:72 + 8e101c: b466 addi.n a6, a6, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:73 + 8e101e: 7763f8 bltu a6, a7, 8e101a <_iram0_text_end+0x1a> + +008e1021 <_start+0x21>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:80 + 8e1021: 5402fc call4 8e1c14
+/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:90 + 8e1024: 0f1400 break 1, 15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:92 + 8e1027: 63fff9 j 8e1024 <_iram0_text_end+0x24> + +008e102a <_start+0x2a>: + ... + +008e102c <_xtos_alloca_handler>: +_xtos_alloca_handler(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:101 + 8e102c: 03b130 rsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:102 + 8e102f: 9517 s32i.n a5, a1, 28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:103 + 8e1031: b332 addi.n a2, a3, 3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:110 + 8e1033: 040130 rsr.lend a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:111 + 8e1036: 050230 rsr.lcount a5 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:112 + 8e1039: 72490b bne a4, a2, 8e1048 <_xtos_alloca_handler+0x1c> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:113 + 8e103c: 645008 beqz a5, 8e1048 <_xtos_alloca_handler+0x1c> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:114 + 8e103f: 255cff addi a5, a5, -1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:115 + 8e1042: 050231 wsr.lcount a5 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:116 + 8e1045: 020030 rsr.lbeg a2 + +008e1048 <_xtos_alloca_handler+0x1c>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:118 + 8e1048: 02b131 wsr.epc1 a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:126 + 8e104b: b133 addi.n a3, a3, 1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:127 + 8e104d: 030241 extui a2, a3, 0, 2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:128 + 8e1050: 02330c sub a3, a3, a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:129 + 8e1053: 8330 l32i.n a3, a3, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:130 + 8e1055: 040330 rsr.sar a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:133 + 8e1058: 002304 ssa8b a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:134 + 8e105b: 00331a sll a3, a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:135 + 8e105e: 03c353 extui a3, a3, 28, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:141 + 8e1061: 040331 wsr.sar a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:144 + 8e1064: 140007 l32r a4, 4e801c <_lit4_start+0x1c> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:145 + 8e1067: d510 mov.n a5, a1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:146 + 8e1069: 211c70 addi a1, a1, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:149 + 8e106c: 04340a addx4 a4, a3, a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:162 + 8e106f: 0a4000 jx a4 + +008e1072 <_xtos_alloca_handler+0x46>: + ... + +008e1074 <_xtos_alloca_handler+0x48>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:165 + 8e1074: d100 mov.n a1, a0 + 8e1076: cf48 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:166 + 8e1078: cf46 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> + +008e107a <_xtos_alloca_handler+0x4e>: + ... + +008e107c <_xtos_alloca_handler+0x50>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:167 + 8e107c: 8154 l32i.n a1, a5, 16 + 8e107e: cf40 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:168 + 8e1080: 8155 l32i.n a1, a5, 20 + 8e1082: ce4c bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:169 + 8e1084: 8156 l32i.n a1, a5, 24 + 8e1086: ce48 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:170 + 8e1088: 8157 l32i.n a1, a5, 28 + 8e108a: ce44 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:171 + 8e108c: d160 mov.n a1, a6 + 8e108e: ce40 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:172 + 8e1090: d170 mov.n a1, a7 + 8e1092: cd4c bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:173 + 8e1094: d180 mov.n a1, a8 + 8e1096: cd48 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:174 + 8e1098: d190 mov.n a1, a9 + 8e109a: cd44 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:175 + 8e109c: d1a0 mov.n a1, a10 + 8e109e: cd40 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:176 + 8e10a0: d1b0 mov.n a1, a11 + 8e10a2: cc4c bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:177 + 8e10a4: d1c0 mov.n a1, a12 + 8e10a6: cc48 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:178 + 8e10a8: d1d0 mov.n a1, a13 + 8e10aa: cc44 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:179 + 8e10ac: d1e0 mov.n a1, a14 + 8e10ae: cc40 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> + +008e10b0 <_xtos_alloca_handler+0x84>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:180 + 8e10b0: d1f0 mov.n a1, a15 + +008e10b2 <_xtos_alloca_handler+0x86>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:187 + 8e10b2: 010341 extui a3, a1, 0, 2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:188 + 8e10b5: c834 beqz.n a3, 8e10bd <_xtos_alloca_handler+0x91> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:193 + 8e10b7: 0f1400 break 1, 15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:195 + 8e10ba: 03110c sub a1, a1, a3 + +008e10bd <_xtos_alloca_handler+0x91>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:200 + 8e10bd: 225c70 addi a2, a5, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:205 + 8e10c0: 240a70 movi a4, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:206 + 8e10c3: 05130c sub a3, a1, a5 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:207 + 8e10c6: 743b16 bgeu a3, a4, 8e10e0 <_xtos_alloca_handler+0xb4> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:210 + 8e10c9: 04550c sub a5, a5, a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:211 + 8e10cc: 235220 l32i a3, a5, 128 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:212 + 8e10cf: 245221 l32i a4, a5, 132 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:213 + 8e10d2: 9354 s32i.n a3, a5, 16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:214 + 8e10d4: 9455 s32i.n a4, a5, 20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:215 + 8e10d6: 235222 l32i a3, a5, 136 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:216 + 8e10d9: 245223 l32i a4, a5, 140 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:217 + 8e10dc: 9356 s32i.n a3, a5, 24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:218 + 8e10de: 9457 s32i.n a4, a5, 28 + +008e10e0 <_xtos_alloca_handler+0xb4>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:223 + 8e10e0: 032c90 l32e a3, a2, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:224 + 8e10e3: 042d90 l32e a4, a2, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:225 + 8e10e6: 031c94 s32e a3, a1, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:226 + 8e10e9: 041d94 s32e a4, a1, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:227 + 8e10ec: 032e90 l32e a3, a2, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:228 + 8e10ef: 042f90 l32e a4, a2, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:229 + 8e10f2: 031e94 s32e a3, a1, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:230 + 8e10f5: 041f94 s32e a4, a1, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:246 + 8e10f8: 8254 l32i.n a2, a5, 16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:247 + 8e10fa: 8355 l32i.n a3, a5, 20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:248 + 8e10fc: 8456 l32i.n a4, a5, 24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:249 + 8e10fe: 8557 l32i.n a5, a5, 28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:250 + 8e1100: 000300 rfe + +008e1103 <_xtos_alloca_handler+0xd7>: + ... + +008e1104 <_xtos_syscall_handler>: +_xtos_syscall_handler(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:74 + 8e1104: 03b130 rsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:80 + 8e1107: 020130 rsr.lend a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:81 + 8e110a: b333 addi.n a3, a3, 3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:82 + 8e110c: 73290c bne a2, a3, 8e111c <_xtos_syscall_handler+0x18> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:83 + 8e110f: 020230 rsr.lcount a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:84 + 8e1112: c826 beqz.n a2, 8e111c <_xtos_syscall_handler+0x18> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:85 + 8e1114: b022 addi.n a2, a2, -1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:86 + 8e1116: 020231 wsr.lcount a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:87 + 8e1119: 030030 rsr.lbeg a3 + +008e111c <_xtos_syscall_handler+0x18>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:88 + 8e111c: 8214 l32i.n a2, a1, 16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:94 + 8e111e: 03b131 wsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:95 + 8e1121: 8315 l32i.n a3, a1, 20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:99 + 8e1123: 652044 bnez a2, 8e116b <_SyscallException+0x28> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:106 + 8e1126: 231615 s32i a3, a1, 84 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:107 + 8e1129: 241616 s32i a4, a1, 88 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:108 + 8e112c: 251617 s32i a5, a1, 92 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:110 + 8e112f: 130008 l32r a3, 4e8020 <_lit4_start+0x20> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:111 + 8e1132: 02e630 rsr.ps a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:112 + 8e1135: 03e631 wsr.ps a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:114 + 8e1138: 03b130 rsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:115 + 8e113b: 211c70 addi a1, a1, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:116 + 8e113e: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:123 + 8e1141: c040 movi.n a4, 0 + +008e1143 <_SyscallException>: +_SyscallException(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:129 + 8e1143: 6c1008 entry a1, 64 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:131 + 8e1146: 5c0007 call12 8e1164 <_SyscallException+0x21> + +008e1149 <_SyscallException+0x6>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:132 + 8e1149: 1e0009 l32r a14, 4e8024 <_lit4_start+0x24> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:133 + 8e114c: aec0 add.n a0, a12, a14 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:134 + 8e114e: d10f retw.n + +008e1150 <_SyscallException+0xd>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:137 + 8e1150: 02e631 wsr.ps a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:138 + 8e1153: c020 movi.n a2, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:139 + 8e1155: 845a l32i.n a4, a5, 40 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:140 + 8e1157: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:141 + 8e115a: 03b131 wsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:142 + 8e115d: 8359 l32i.n a3, a5, 36 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:143 + 8e115f: 855b l32i.n a5, a5, 44 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:144 + 8e1161: 000300 rfe + +008e1164 <_SyscallException+0x21>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:150 + 8e1164: 6c1006 entry a1, 48 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:152 + 8e1167: dff0 mov.n a15, a15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:163 + 8e1169: d10f retw.n + +008e116b <_SyscallException+0x28>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:168 + 8e116b: c72f movi.n a2, -1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:169 + 8e116d: 211c70 addi a1, a1, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:170 + 8e1170: 000300 rfe + +008e1173 <_SyscallException+0x30>: + ... + +008e1174 <_xtos_l1int_handler>: +_xtos_l1int_handler(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:69 + 8e1174: 9517 s32i.n a5, a1, 28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:85 + 8e1176: 120008 l32r a2, 4e8020 <_lit4_start+0x20> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:87 + 8e1179: 03b130 rsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:88 + 8e117c: 02e616 xsr.ps a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:98 + 8e117f: 9310 s32i.n a3, a1, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:99 + 8e1181: 9211 s32i.n a2, a1, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:170 + 8e1183: 211c70 addi a1, a1, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:172 + 8e1186: 12000a l32r a2, 4e8028 <_lit4_start+0x28> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:174 + 8e1189: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:257 + 8e118c: 032402 or a4, a2, a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:258 + 8e118f: 042409 addx2 a4, a2, a4 + +008e1192 <_LevelOneInterrupt>: +_LevelOneInterrupt(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:266 + 8e1192: 6c100e entry a1, 112 + +008e1195 <_LevelOneInterrupt+0x3>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:315 + 8e1195: 0f1600 rsil a15, 1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:345 + 8e1198: c0d1 movi.n a13, 1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:348 + 8e119a: 1c000b l32r a12, 4e802c <_lit4_start+0x2c> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:350 + 8e119d: 0de331 wsr.intclear a13 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:554 + 8e11a0: 0d0230 rsr.lcount a13 + 8e11a3: 0f0030 rsr.lbeg a15 + 8e11a6: 9d19 s32i.n a13, a1, 36 + 8e11a8: 0d0130 rsr.lend a13 + 8e11ab: 9f1a s32i.n a15, a1, 40 + 8e11ad: 9d1b s32i.n a13, a1, 44 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:556 + 8e11af: 0f0330 rsr.sar a15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:561 + 8e11b2: 8dc0 l32i.n a13, a12, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:562 + 8e11b4: 9f12 s32i.n a15, a1, 8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:570 + 8e11b6: df10 mov.n a15, a1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:571 + 8e11b8: 8ec1 l32i.n a14, a12, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:572 + 8e11ba: 0fd000 callx12 a13 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:576 + 8e11bd: 8d19 l32i.n a13, a1, 36 + 8e11bf: 8e1a l32i.n a14, a1, 40 + 8e11c1: 8f1b l32i.n a15, a1, 44 + 8e11c3: 0d0231 wsr.lcount a13 + 8e11c6: 0e0031 wsr.lbeg a14 + 8e11c9: 0f0131 wsr.lend a15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:578 + 8e11cc: 8c12 l32i.n a12, a1, 8 + +008e11ce : +spurious_int(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:684 + 8e11ce: 10000c l32r a0, 4e8030 <_lit4_start+0x30> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:692 + 8e11d1: 1d000a l32r a13, 4e8028 <_lit4_start+0x28> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:693 + 8e11d4: 0c0331 wsr.sar a12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:694 + 8e11d7: 0d0002 or a0, a0, a13 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:695 + 8e11da: 00d009 addx2 a0, a13, a0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:698 + 8e11dd: 0d3600 rsil a13, 3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:701 + 8e11e0: d10f retw.n + +008e11e2 : + ... + +008e11e4 <_xtos_set_interrupt_handler_arg>: +_xtos_set_interrupt_handler_arg(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:31 + 8e11e4: 6c1004 entry a1, 32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:36 + 8e11e7: c152 movi.n a5, 18 + 8e11e9: 72533b bltu a5, a2, 8e1228 <_xtos_set_interrupt_handler_arg+0x44> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:38 + 8e11ec: 18000d l32r a8, 4e8034 <_lit4_start+0x34> + 8e11ef: a828 add.n a8, a2, a8 + 8e11f1: 288000 l8ui a8, a8, 0 + 8e11f4: 17000e l32r a7, 4e8038 <_lit4_start+0x38> + 8e11f7: 6f8531 bgeui a8, 5, 8e122c <_xtos_set_interrupt_handler_arg+0x48> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:41 + 8e11fa: 0d2811 slli a8, a2, 3 + 8e11fd: 08770c sub a7, a7, a8 + 8e1200: 18000f l32r a8, 4e803c <_lit4_start+0x3c> + 8e1203: 267224 l32i a6, a7, 144 + 8e1206: c83e beqz.n a3, 8e1218 <_xtos_set_interrupt_handler_arg+0x34> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:49 + 8e1208: 237624 s32i a3, a7, 144 + 8e120b: 247625 s32i a4, a7, 148 + 8e120e: c020 movi.n a2, 0 + 8e1210: 08690c sub a9, a6, a8 + 8e1213: 096239 movnez a2, a6, a9 + 8e1216: d10f retw.n + +008e1218 <_xtos_set_interrupt_handler_arg+0x34>: + 8e1218: 287624 s32i a8, a7, 144 + 8e121b: 227625 s32i a2, a7, 148 + 8e121e: 086a0c sub a10, a6, a8 + 8e1221: c020 movi.n a2, 0 + 8e1223: 0a6239 movnez a2, a6, a10 + 8e1226: d10f retw.n + +008e1228 <_xtos_set_interrupt_handler_arg+0x44>: + 8e1228: c020 movi.n a2, 0 + 8e122a: d10f retw.n + +008e122c <_xtos_set_interrupt_handler_arg+0x48>: + 8e122c: c020 movi.n a2, 0 + 8e122e: d10f retw.n + +008e1230 <_xtos_set_interrupt_handler>: +_xtos_set_interrupt_handler(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:57 + 8e1230: 6c1004 entry a1, 32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:58 + 8e1233: da20 mov.n a10, a2 + 8e1235: db30 mov.n a11, a3 + 8e1237: dc20 mov.n a12, a2 + 8e1239: 5bffea call8 8e11e4 <_xtos_set_interrupt_handler_arg> + 8e123c: d2a0 mov.n a2, a10 + 8e123e: d10f retw.n + +008e1240 <_Level2FromVector>: +_Level2FromVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:53 + 8e1240: 02d216 xsr.excsave2 a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:57 + 8e1243: 211c90 addi a1, a1, -112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:58 + 8e1246: 9214 s32i.n a2, a1, 16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:62 + 8e1248: 120008 l32r a2, 4e8020 <_lit4_start+0x20> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:64 + 8e124b: 9416 s32i.n a4, a1, 24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:65 + 8e124d: 9517 s32i.n a5, a1, 28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:66 + 8e124f: 02e631 wsr.ps a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:67 + 8e1252: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:84 + 8e1255: c040 movi.n a4, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:85 + 8e1257: 211c70 addi a1, a1, 112 + +008e125a <_Level2FromVector+0x1a>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:86 + 8e125a: 6c100e entry a1, 112 + +008e125d <_Level2FromVector+0x1d>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:93 + 8e125d: 0f2600 rsil a15, 2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:129 + 8e1260: 0fe230 rsr.interrupt a15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:130 + 8e1263: 0ce430 rsr.intenable a12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:131 + 8e1266: 1d0010 l32r a13, 4e8040 <_lit4_start+0x40> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:132 + 8e1269: 0cff01 and a15, a15, a12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:133 + 8e126c: 0dff01 and a15, a15, a13 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:134 + 8e126f: 0e0330 rsr.sar a14 + +008e1272 <_Level2FromVector+0x32>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:135 + 8e1272: 64f05e beqz a15, 8e12d4 + +008e1275 <_Level2FromVector+0x35>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:136 + 8e1275: 9e12 s32i.n a14, a1, 8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:137 + 8e1277: 0d0230 rsr.lcount a13 + 8e127a: 0e0030 rsr.lbeg a14 + 8e127d: 9d19 s32i.n a13, a1, 36 + 8e127f: 0d0130 rsr.lend a13 + 8e1282: 2e160a s32i a14, a1, 40 + 8e1285: 2d160b s32i a13, a1, 44 + +008e1288 <_Level2FromVector+0x48>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:142 + 8e1288: 0f0c06 neg a12, a15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:143 + 8e128b: 0fcc01 and a12, a12, a15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:144 + 8e128e: 0ce331 wsr.intclear a12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:145 + 8e1291: 1d000e l32r a13, 4e8038 <_lit4_start+0x38> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:146 + 8e1294: c1ef movi.n a14, 31 + 8e1296: 0ccf04 nsau a12, a12 + 8e1299: 0cef0c sub a15, a14, a12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:147 + 8e129c: 0f0f06 neg a15, a15 + 8e129f: 2ffc12 addi a15, a15, 18 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:148 + 8e12a2: 0dfc0b addx8 a12, a15, a13 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:149 + 8e12a5: 8dc0 l32i.n a13, a12, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:155 + 8e12a7: 2ec201 l32i a14, a12, 4 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8e158b: b199 addi.n a9, a9, 1 + +008e158d : + 8e158d: 140021 l32r a4, 4e8084 <_lit4_start+0x84> + +008e1590 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:492 + 8e1590: 8b20 l32i.n a11, a2, 0 + 8e1592: c8b3 beqz.n a11, 8e1599 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:493 + 8e1594: 8a21 l32i.n a10, a2, 4 + +008e1596 : + 8e1596: 0bb000 callx8 a11 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:494 + 8e1599: b822 addi.n a2, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:491 + 8e159b: 7429f1 bne a2, a4, 8e1590 + 8e159e: 1c0027 l32r a12, 4e809c <_lit4_start+0x9c> + 8e15a1: 1a0028 l32r a10, 4e80a0 <_lit4_start+0xa0> + 8e15a4: 1d0026 l32r a13, 4e8098 <_lit4_start+0x98> + 8e15a7: 1e0025 l32r a14, 4e8094 <_lit4_start+0x94> + 8e15aa: 1f0024 l32r a15, 4e8090 <_lit4_start+0x90> + 8e15ad: 1b0022 l32r a11, 4e8088 <_lit4_start+0x88> + 8e15b0: 180023 l32r a8, 4e808c <_lit4_start+0x8c> + 8e15b3: 190029 l32r a9, 4e80a4 <_lit4_start+0xa4> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:503 + 8e15b6: 9930 s32i.n a9, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:509 + 8e15b8: 98bd s32i.n a8, a11, 52 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:510 + 8e15ba: 9fbe s32i.n a15, a11, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:511 + 8e15bc: 9ebf s32i.n a14, a11, 60 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:512 + 8e15be: 2db610 s32i a13, a11, 64 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:514 + 8e15c1: 9ab9 s32i.n a10, a11, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:513 + 8e15c3: 9cb8 s32i.n a12, a11, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:518 + 8e15c5: c0a9 movi.n a10, 9 + 8e15c7: 1b002a l32r a11, 4e80a8 <_lit4_start+0xa8> + 8e15ca: 58135f call8 8e6348 <_xtos_set_exception_handler> + 8e15cd: 12002b l32r a2, 4e80ac <_lit4_start+0xac> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:519 + 8e15d0: c0a3 movi.n a10, 3 + 8e15d2: db20 mov.n a11, a2 + 8e15d4: 58135c call8 8e6348 <_xtos_set_exception_handler> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:520 + 8e15d7: c0a0 movi.n a10, 0 + 8e15d9: db20 mov.n a11, a2 + 8e15db: 58135b call8 8e6348 <_xtos_set_exception_handler> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:521 + 8e15de: c0a2 movi.n a10, 2 + 8e15e0: db20 mov.n a11, a2 + 8e15e2: 581359 call8 8e6348 <_xtos_set_exception_handler> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:522 + 8e15e5: c0a8 movi.n a10, 8 + 8e15e7: db20 mov.n a11, a2 + 8e15e9: 581357 call8 8e6348 <_xtos_set_exception_handler> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:523 + 8e15ec: c0ac movi.n a10, 12 + 8e15ee: db20 mov.n a11, a2 + 8e15f0: 581355 call8 8e6348 <_xtos_set_exception_handler> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:524 + 8e15f3: c0ad movi.n a10, 13 + 8e15f5: db20 mov.n a11, a2 + 8e15f7: 581354 call8 8e6348 <_xtos_set_exception_handler> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:525 + 8e15fa: db20 mov.n a11, a2 + 8e15fc: c0a6 movi.n a10, 6 + 8e15fe: 581352 call8 8e6348 <_xtos_set_exception_handler> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:526 + 8e1601: d10f retw.n + +008e1603 : + ... + +008e1604 : +athos_interrupt_handler(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:540 + 8e1604: 6c1004 entry a1, 32 + 8e1607: 180018 l32r a8, 4e8060 <_lit4_start+0x60> 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:547 + 8e161c: 26fa00 movi a6, 0xffffff00 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:550 + 8e161f: 0c0200 memw + 8e1622: 22527d l32i a2, a5, 0x1f4 + 8e1625: 062201 and a2, a2, a6 + 8e1628: 032202 or a2, a2, a3 + 8e162b: 0c0200 memw +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:552 + 8e162e: c133 movi.n a3, 19 + 8e1630: 14002c l32r a4, 4e80b0 <_lit4_start+0xb0> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:550 + 8e1633: 22567d s32i a2, a5, 0x1f4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:552 + 8e1636: c020 movi.n a2, 0 + +008e1638 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:553 + 8e1638: db40 mov.n a11, a4 + 8e163a: da20 mov.n a10, a2 + 8e163c: 5bfefc call8 8e1230 <_xtos_set_interrupt_handler> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:554 + 8e163f: b122 addi.n a2, a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:552 + 8e1641: 7329f3 bne a2, a3, 8e1638 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:556 + 8e1644: c2a1 movi.n a10, 33 + 8e1646: 0c0200 memw + 8e1649: 29527d l32i a9, a5, 0x1f4 + 8e164c: 069901 and a9, a9, a6 + 8e164f: 0a9902 or a9, a9, a10 + 8e1652: 0c0200 memw + 8e1655: 180018 l32r a8, 4e8060 <_lit4_start+0x60> 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8e1697: 1a002e l32r a10, 4e80b8 <_lit4_start+0xb8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:941 + 8e169a: 282212 l32i a8, a2, 72 + 8e169d: 1b002f l32r a11, 4e80bc <_lit4_start+0xbc> + 8e16a0: 2c2a02 movi a12, 0x202 + 8e16a3: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:943 + 8e16a6: 28225f l32i a8, a2, 0x17c + 8e16a9: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:945 + 8e16ac: d10f retw.n + +008e16ae : + ... + +008e16b0 <_read_usb_desc>: +_read_usb_desc(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:949 + 8e16b0: 6c1006 entry a1, 48 + 8e16b3: 150018 l32r a5, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:954 + 8e16b6: da30 mov.n a10, a3 + 8e16b8: 285260 l32i a8, a5, 0x180 + 8e16bb: c0b1 movi.n a11, 1 + 8e16bd: dc10 mov.n a12, a1 + 8e16bf: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:962 + 8e16c2: da30 mov.n a10, a3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:959 + 8e16c4: 2b1100 l16ui a11, a1, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:962 + 8e16c7: dc20 mov.n a12, a2 + 8e16c9: 285260 l32i a8, a5, 0x180 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:959 + 8e16cc: 0b1b46 extui a11, a11, 1, 7 + 8e16cf: 0b4b36 minu a11, a4, a11 + 8e16d2: 0b0b4f extui a11, a11, 0, 16 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<_lit4_start+0x54> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:968 + 8e16f2: 23fa00 movi a3, 0xffffff00 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:971 + 8e16f5: c0ac movi.n a10, 12 + 8e16f7: 0c0200 memw + 8e16fa: 29227d l32i a9, a2, 0x1f4 + 8e16fd: 039901 and a9, a9, a3 + 8e1700: 0a9902 or a9, a9, a10 + 8e1703: 0c0200 memw + 8e1706: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e1709: 29267d s32i a9, a2, 0x1f4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:972 + 8e170c: 2a0a80 movi a10, 128 + 8e170f: 288260 l32i a8, a8, 0x180 + 8e1712: c0b2 movi.n a11, 2 + 8e1714: dc10 mov.n a12, a1 + 8e1716: 0b8000 callx8 a8 + 8e1719: 1c0030 l32r a12, 4e80c0 <_lit4_start+0xc0> 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+ 8e1c95: 000000 ... + +008e1c98 : +cmnos_allocram_module_install(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/allocram/src/cmnos_allocram.c:99 + 8e1c98: 6c1004 entry a1, 32 + 8e1c9b: 18005d l32r a8, 4e8174 <_lit4_start+0x174> + 8e1c9e: 19005c l32r a9, 4e8170 <_lit4_start+0x170> + 8e1ca1: 13005e l32r a3, 4e8178 <_lit4_start+0x178> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/allocram/src/cmnos_allocram.c:102 + 8e1ca4: 9322 s32i.n a3, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/allocram/src/cmnos_allocram.c:101 + 8e1ca6: 9821 s32i.n a8, a2, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/allocram/src/cmnos_allocram.c:100 + 8e1ca8: 9920 s32i.n a9, a2, 0 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8e1cc1: 581325 call8 8e6958 + 8e1cc4: 03a80c sub a8, a10, a3 + 8e1cc7: 7283f6 bltu a8, a2, 8e1cc1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:120 + 8e1cca: d10f retw.n + +008e1ccc : +cmnos_milliseconds(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:129 + 8e1ccc: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:143 + 8e1ccf: 58001d call8 8e1d44 + 8e1cd2: 12005f l32r a2, 4e817c <_lit4_start+0x17c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:145 + 8e1cd5: 8220 l32i.n a2, a2, 0 + 8e1cd7: d10f retw.n + +008e1cd9 : + 8e1cd9: 000000 ... + +008e1cdc : +cmnos_refclk_speed_get(): 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:208 + 8e1d08: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:211 + 8e1d0b: d10f retw.n + +008e1d0d : + 8e1d0d: 000000 ... + +008e1d10 : +cmnos_clock_init(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:215 + 8e1d10: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:222 + 8e1d13: c060 movi.n a6, 0 + 8e1d15: 190060 l32r a9, 4e8180 <_lit4_start+0x180> + 8e1d18: 1a0062 l32r a10, 4e8188 <_lit4_start+0x188> + 8e1d1b: 170061 l32r a7, 4e8184 <_lit4_start+0x184> + 8e1d1e: c033 movi.n a3, 3 + 8e1d20: d5a0 mov.n a5, a10 + 8e1d22: 6d3a10 loopgtz a3, 8e1d36 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a8, 4e817c <_lit4_start+0x17c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:234 + 8e1d3f: 9582 s32i.n a5, a8, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:238 + 8e1d41: d10f retw.n + +008e1d43 : + ... + +008e1d44 : +cmnos_tick(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:244 + 8e1d44: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:253 + 8e1d47: 581304 call8 8e6958 + 8e1d4a: 150063 l32r a5, 4e818c <_lit4_start+0x18c> + 8e1d4d: 2b3ae8 movi a11, 0x3e8 + 8e1d50: 8250 l32i.n a2, a5, 0 + 8e1d52: d3a0 mov.n a3, a10 + 8e1d54: 245ce8 addi a4, a5, -24 + 8e1d57: 02aa0c sub a10, a10, a2 + 8e1d5a: 58133c call8 8e6a4c <__udivsi3> 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+008e2185 : + 8e2185: 000000 ... + +008e2188 : +cmnos_intr_dummy(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/intr/src/cmnos_intr.c:30 + 8e2188: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/intr/src/cmnos_intr.c:32 + 8e218b: d10f retw.n + +008e218d : + 8e218d: 000000 ... + +008e2190 : +cmnos_intr_init(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/intr/src/cmnos_intr.c:42 + 8e2190: 6c1004 entry a1, 32 + 8e2193: 190082 l32r a9, 4e8208 <_lit4_start+0x208> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/intr/src/cmnos_intr.c:46 + 8e2196: c0a0 movi.n a10, 0 + 8e2198: c183 movi.n a8, 19 + 8e219a: 9a90 s32i.n a10, a9, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/intr/src/cmnos_intr.c:49 + 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<_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/intr/src/cmnos_intr.c:65 + 8e21be: 283248 l32i a8, a3, 0x120 + 8e21c1: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/intr/src/cmnos_intr.c:66 + 8e21c4: 28324d l32i a8, a3, 0x134 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/intr/src/cmnos_intr.c:65 + 8e21c7: d4a0 mov.n a4, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/intr/src/cmnos_intr.c:66 + 8e21c9: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/intr/src/cmnos_intr.c:69 + 8e21cc: 28324e l32i a8, a3, 0x138 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/intr/src/cmnos_intr.c:67 + 8e21cf: c7df movi.n a13, -1 + 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/misc/src/cmnos_misc.c:240 + 8e24a9: 9a24 s32i.n a10, a2, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/misc/src/cmnos_misc.c:239 + 8e24ab: 9b23 s32i.n a11, a2, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/misc/src/cmnos_misc.c:238 + 8e24ad: 9c22 s32i.n a12, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/misc/src/cmnos_misc.c:237 + 8e24af: 9d21 s32i.n a13, a2, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/misc/src/cmnos_misc.c:236 + 8e24b1: 9e20 s32i.n a14, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/misc/src/cmnos_misc.c:245 + 8e24b3: d10f retw.n + +008e24b5 : + 8e24b5: 000000 ... + +008e24b8 : +cmnos_write_char(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:59 + 8e24b8: 6c1004 entry a1, 32 + 8e24bb: 130018 l32r a3, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:60 + 8e24be: 692911 bnei a2, 10, 8e24d3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:61 + 8e24c1: 283214 l32i a8, a3, 80 + 8e24c4: c0ad movi.n a10, 13 + 8e24c6: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:62 + 8e24c9: 283214 l32i a8, a3, 80 + 8e24cc: c0aa movi.n a10, 10 + 8e24ce: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:67 + 8e24d1: d10f retw.n + +008e24d3 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:63 + 8e24d3: c09d movi.n a9, 13 + 8e24d5: 792107 beq a2, a9, 8e24e0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:65 + 8e24d8: 283214 l32i a8, a3, 80 + 8e24db: da20 mov.n a10, a2 + +008e24dd : + 8e24dd: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:67 + 8e24e0: d10f retw.n + +008e24e2 : + ... + +008e24e4 <_cvt>: +_cvt(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:72 + 8e24e4: 6c100e entry a1, 112 + 8e24e7: cc2a bnez.n a2, 8e24f5 <_cvt+0x11> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:79 + 8e24e9: d810 mov.n a8, a1 + 8e24eb: c360 movi.n a6, 48 + 8e24ed: 268400 s8i a6, a8, 0 + 8e24f0: b116 addi.n a6, a1, 1 + 8e24f2: 60001e j 8e2514 <_cvt+0x30> + +008e24f5 <_cvt+0x11>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:81 + 8e24f5: d610 mov.n a6, a1 + +008e24f7 <_cvt+0x13>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:82 + 8e24f7: da20 mov.n a10, a2 + 8e24f9: db40 mov.n a11, a4 + 8e24fb: 581168 call8 8e6a9c <__umodsi3> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:83 + 8e24fe: db40 mov.n a11, a4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:82 + 8e2500: aa59 add.n a9, a5, a10 + 8e2502: 299000 l8ui a9, a9, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:83 + 8e2505: da20 mov.n a10, a2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:82 + 8e2507: 296400 s8i a9, a6, 0 + 8e250a: b166 addi.n a6, a6, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:83 + 8e250c: 58114f call8 8e6a4c <__udivsi3> + 8e250f: d2a0 mov.n a2, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:81 + 8e2511: 65afe2 bnez a10, 8e24f7 <_cvt+0x13> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:90 + 8e2514: c0d0 movi.n a13, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:81 + 8e2516: da10 mov.n a10, a1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:86 + 8e2518: 7a6115 beq a6, a10, 8e2531 <_cvt+0x4d> + 8e251b: 0a6b0c sub a11, a6, a10 + 8e251e: 0bb202 or a2, a11, a11 + 8e2521: 6db909 loopnez a11, 8e252e <_cvt+0x4a> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:87 + 8e2524: b066 addi.n a6, a6, -1 + 8e2526: 2c6000 l8ui a12, a6, 0 + 8e2529: 2c3400 s8i a12, a3, 0 + 8e252c: b133 addi.n a3, a3, 1 + +008e252e <_cvt+0x4a>: + 8e252e: 600001 j 8e2533 <_cvt+0x4f> + +008e2531 <_cvt+0x4d>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:86 + 8e2531: c020 movi.n a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:90 + 8e2533: 2d3400 s8i a13, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:91 + 8e2536: d10f retw.n + +008e2538 : +cmnos_vprintf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:96 + 8e2538: 6c100e entry a1, 112 + 8e253b: d950 mov.n a9, a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:102 + 8e253d: dd10 mov.n a13, a1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:96 + 8e253f: da40 mov.n a10, a4 + 8e2541: 261611 s32i a6, a1, 68 + 8e2544: 221613 s32i a2, a1, 76 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:102 + 8e2547: c060 movi.n a6, 0 + 8e2549: c020 movi.n a2, 0 + 8e254b: c040 movi.n a4, 0 + 8e254d: 9d18 s32i.n a13, a1, 32 + 8e254f: 9a1b s32i.n a10, a1, 44 + 8e2551: 991a s32i.n a9, a1, 40 + +008e2553 : + 8e2553: 251213 l32i a5, a1, 76 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:104 + 8e2556: b133 addi.n a3, a3, 1 + 8e2558: 273dff addmi a7, a3, 0xffffff00 + 8e255b: 2770ff l8ui a7, a7, 255 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:105 + 8e255e: c285 movi.n a8, 37 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:104 + 8e2560: 6473c4 beqz a7, 8e2928 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:105 + 8e2563: 787915 bne a7, a8, 8e257c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:106 + 8e2566: 273000 l8ui a7, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:108 + 8e2569: c29d movi.n a9, 45 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:106 + 8e256b: b133 addi.n a3, a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:108 + 8e256d: 797932 bne a7, a9, 8e25a3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:109 + 8e2570: 273000 l8ui a7, a3, 0 + 8e2573: c0a1 movi.n a10, 1 + 8e2575: b133 addi.n a3, a3, 1 + 8e2577: 9a1d s32i.n a10, a1, 52 + 8e2579: 60002a j 8e25a7 + +008e257c : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:284 + 8e257c: da70 mov.n a10, a7 + 8e257e: 0b5000 callx8 a5 + 8e2581: 600019 j 8e259e + +008e2584 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:220 + 8e2584: c1c8 movi.n a12, 24 + 8e2586: 7bc204 blt a12, a11, 8e258e + 8e2589: c2d4 movi.n a13, 36 + +008e258b : + 8e258b: 2d1611 s32i a13, a1, 68 + 8e258e: 8b1b l32i.n a11, a1, 44 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:221 + 8e2590: 2a1211 l32i a10, a1, 68 + 8e2593: abaa add.n a10, a10, a11 + 8e2595: 2aadff addmi a10, a10, 0xffffff00 + 8e2598: 2aa0ff l8ui a10, a10, 255 + 8e259b: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:222 + 8e259e: b122 addi.n a2, a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:223 + 8e25a0: 63ffb2 j 8e2556 + +008e25a3 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:109 + 8e25a3: c0b0 movi.n a11, 0 + 8e25a5: 9b1d s32i.n a11, a1, 52 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:112 + 8e25a7: c3c0 movi.n a12, 48 + 8e25a9: 7c790b bne a7, a12, 8e25b8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:114 + 8e25ac: 273000 l8ui a7, a3, 0 + 8e25af: c0d1 movi.n a13, 1 + 8e25b1: b133 addi.n a3, a3, 1 + 8e25b3: 9d1e s32i.n a13, a1, 56 + 8e25b5: 600003 j 8e25bc + +008e25b8 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:116 + 8e25b8: c0e0 movi.n a14, 0 + 8e25ba: 9e1e s32i.n a14, a1, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:118 + 8e25bc: 2f7cd0 addi a15, a7, -48 + 8e25bf: 0f0f47 extui a15, a15, 0, 8 + 8e25c2: 6ff923 bgeui a15, 10, 8e25e9 + 8e25c5: c080 movi.n a8, 0 + 8e25c7: 981c s32i.n a8, a1, 48 + +008e25c9 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:119 + 8e25c9: 891c l32i.n a9, a1, 48 + 8e25cb: 099b0a addx4 a11, a9, a9 + 8e25ce: 07bb09 addx2 a11, a11, a7 + 8e25d1: 29bcd0 addi a9, a11, -48 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:120 + 8e25d4: 273000 l8ui a7, a3, 0 + 8e25d7: b133 addi.n a3, a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:119 + 8e25d9: 991c s32i.n a9, a1, 48 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:118 + 8e25db: 2a7cd0 addi a10, a7, -48 + 8e25de: 0a0a47 extui a10, a10, 0, 8 + 8e25e1: 6ea9e4 bltui a10, 10, 8e25c9 + 8e25e4: 991c s32i.n a9, a1, 48 + 8e25e6: 600003 j 8e25ed + +008e25e9 : + 8e25e9: c0c0 movi.n a12, 0 + 8e25eb: 9c1c s32i.n a12, a1, 48 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:133 + 8e25ed: 290a6c movi a9, 108 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:122 + 8e25f0: c2de movi.n a13, 46 + 8e25f2: 7d7921 bne a7, a13, 8e2617 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:123 + 8e25f5: 273000 l8ui a7, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:124 + 8e25f8: 8f1e l32i.n a15, a1, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:123 + 8e25fa: b133 addi.n a3, a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:125 + 8e25fc: 2e7cd0 addi a14, a7, -48 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:124 + 8e25ff: b1ff addi.n a15, a15, 1 + 8e2601: 9f1e s32i.n a15, a1, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:125 + 8e2603: 0e0e47 extui a14, a14, 0, 8 + 8e2606: 6fe90d bgeui a14, 10, 8e2617 + +008e2609 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:127 + 8e2609: 273000 l8ui a7, a3, 0 + 8e260c: b133 addi.n a3, a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:125 + 8e260e: 287cd0 addi a8, a7, -48 + 8e2611: 080847 extui a8, a8, 0, 8 + 8e2614: 6e89f1 bltui a8, 10, 8e2609 + +008e2617 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:178 + 8e2617: c4c2 movi.n a12, 66 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:133 + 8e2619: 797916 bne a7, a9, 8e2633 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:135 + 8e261c: 273000 l8ui a7, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:139 + 8e261f: c0b1 movi.n a11, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:135 + 8e2621: b133 addi.n a3, a3, 1 + 8e2623: 2a7c94 addi a10, a7, -108 + 8e2626: 65a205 bnez a10, 8e282f +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:139 + 8e2629: 273000 l8ui a7, a3, 0 + 8e262c: c0a1 movi.n a10, 1 + 8e262e: b133 addi.n a3, a3, 1 + 8e2630: 6001fd j 8e2831 + +008e2633 : + 8e2633: c0a0 movi.n a10, 0 + 8e2635: c0b0 movi.n a11, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:178 + 8e2637: 7c7902 bne a7, a12, 8e263d + 8e263a: 6000ef j 8e272d + 8e263d: c4d4 movi.n a13, 68 + 8e263f: 7d7902 bne a7, a13, 8e2645 + 8e2642: 6000e7 j 8e272d + 8e2645: c5e5 movi.n a14, 85 + 8e2647: 7e7902 bne a7, a14, 8e264d + 8e264a: 6000df j 8e272d + 8e264d: c5f8 movi.n a15, 88 + 8e264f: 7f7902 bne a7, a15, 8e2655 + 8e2652: 6000d7 j 8e272d + 8e2655: 280a62 movi a8, 98 + 8e2658: 787902 bne a7, a8, 8e265e + 8e265b: 6000ce j 8e272d + 8e265e: 290a64 movi a9, 100 + 8e2661: 797902 bne a7, a9, 8e2667 + 8e2664: 6000c5 j 8e272d + 8e2667: 2c0a70 movi a12, 112 + 8e266a: 7c7902 bne a7, a12, 8e2670 + 8e266d: 6000ba j 8e272b + 8e2670: 2d0a75 movi a13, 117 + 8e2673: 7d7902 bne a7, a13, 8e2679 + 8e2676: 6000b3 j 8e272d + 8e2679: 2e0a78 movi a14, 120 + 8e267c: 7e7902 bne a7, a14, 8e2682 + 8e267f: 6000aa j 8e272d + +008e2682 : + 8e2682: c0f0 movi.n a15, 0 + 8e2684: 2f1610 s32i a15, a1, 64 + 8e2687: 60002c j 8e26b7 + +008e268a : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:156 + 8e268a: c188 movi.n a8, 24 + 8e268c: 7a8204 blt a8, a10, 8e2694 + 8e268f: c294 movi.n a9, 36 + +008e2691 : + 8e2691: 291611 s32i a9, a1, 68 + 8e2694: 8a1b l32i.n a10, a1, 44 + 8e2696: 241211 l32i a4, a1, 68 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:162 + 8e2699: c484 movi.n a8, 68 + 8e269b: 2b0a64 movi a11, 100 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:156 + 8e269e: aa44 add.n a4, a4, a10 + 8e26a0: 244dff addmi a4, a4, 0xffffff00 + 8e26a3: 24423f l32i a4, a4, 252 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:162 + 8e26a6: 7b7102 beq a7, a11, 8e26ac + 8e26a9: 7879d5 bne a7, a8, 8e2682 + +008e26ac : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:163 + 8e26ac: 674fd2 bgez a4, 8e2682 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:165 + 8e26af: 040406 neg a4, a4 + 8e26b2: c29d movi.n a9, 45 + 8e26b4: 291610 s32i a9, a1, 64 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:247 + 8e26b7: 2a0a62 movi a10, 98 + 8e26ba: 7a7a02 bge a7, a10, 8e26c0 + 8e26bd: 600086 j 8e2747 + 8e26c0: 2b0a62 movi a11, 98 + 8e26c3: 77b202 blt a11, a7, 8e26c9 + 8e26c6: 6000ad j 8e2777 + 8e26c9: 2c0a73 movi a12, 115 + 8e26cc: 7c7a02 bge a7, a12, 8e26d2 + 8e26cf: 60017a j 8e284d + 8e26d2: 2d0a73 movi a13, 115 + 8e26d5: 77d202 blt a13, a7, 8e26db + 8e26d8: 6001a1 j 8e287d + 8e26db: 2e0a78 movi a14, 120 + 8e26de: 7e7a02 bge a7, a14, 8e26e4 + 8e26e1: 600256 j 8e293b + 8e26e4: 2f0a78 movi a15, 120 + 8e26e7: 77fa02 bge a15, a7, 8e26ed + 8e26ea: 6001a9 j 8e2897 + +008e26ed : + 8e26ed: 287cbc addi a8, a7, -68 + 8e26f0: 648236 beqz a8, 8e292a + 8e26f3: 297cab addi a9, a7, -85 + 8e26f6: 649230 beqz a9, 8e292a + 8e26f9: 2a7ca8 addi a10, a7, -88 + 8e26fc: 64a267 beqz a10, 8e2967 + 8e26ff: 2b7c9c addi a11, a7, -100 + 8e2702: 64b224 beqz a11, 8e292a +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:206 + 8e2705: 2c0a70 movi a12, 112 + 8e2708: 7c710e beq a7, a12, 8e271a + 8e270b: 2d7c8b addi a13, a7, -117 + 8e270e: 64d218 beqz a13, 8e292a + 8e2711: 2e0a78 movi a14, 120 + 8e2714: 7e7102 beq a7, a14, 8e271a + 8e2717: 60008a j 8e27a5 + +008e271a : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:201 + 8e271a: da40 mov.n a10, a4 + 8e271c: db10 mov.n a11, a1 + 8e271e: c1c0 movi.n a12, 16 + 8e2720: 1d00a6 l32r a13, 4e8298 <_lit4_start+0x298> + 8e2723: 5bff70 call8 8e24e4 <_cvt> + 8e2726: d6a0 mov.n a6, a10 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8e27b8: 9b1f s32i.n a11, a1, 60 + 8e27ba: c9a4 beqz.n a10, 8e27d2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:254 + 8e27bc: 2c1210 l32i a12, a1, 64 + 8e27bf: c8ca beqz.n a12, 8e27cd + 8e27c1: dac0 mov.n a10, a12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:255 + 8e27c3: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:256 + 8e27c6: b122 addi.n a2, a2, 1 + 8e27c8: c0d0 movi.n a13, 0 + +008e27ca : + 8e27ca: 2d1610 s32i a13, a1, 64 + 8e27cd: c370 movi.n a7, 48 + 8e27cf: 600001 j 8e27d4 + +008e27d2 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:260 + 8e27d2: c270 movi.n a7, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:262 + 8e27d4: 8e1d l32i.n a14, a1, 52 + 8e27d6: 891f l32i.n a9, a1, 60 + 8e27d8: cde9 bnez.n a14, 8e27f5 + 8e27da: b199 addi.n a9, a9, 1 + 8e27dc: 600008 j 8e27e8 + +008e27df : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:264 + 8e27df: da70 mov.n a10, a7 + 8e27e1: 0b5000 callx8 a5 + 8e27e4: 8919 l32i.n a9, a1, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:265 + 8e27e6: b122 addi.n a2, a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:263 + 8e27e8: 8a1f l32i.n a10, a1, 60 + 8e27ea: b099 addi.n a9, a9, -1 + 8e27ec: 9919 s32i.n a9, a1, 36 + 8e27ee: b0aa addi.n a10, a10, -1 + 8e27f0: 9a1f s32i.n a10, a1, 60 + 8e27f2: 6b91e9 bgei a9, 1, 8e27df + +008e27f5 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:268 + 8e27f5: 2b1210 l32i a11, a1, 64 + 8e27f8: 8718 l32i.n a7, a1, 32 + 8e27fa: c8b5 beqz.n a11, 8e2803 + 8e27fc: dab0 mov.n a10, a11 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:269 + 8e27fe: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:270 + 8e2801: b122 addi.n a2, a2, 1 + +008e2803 : + 8e2803: b169 addi.n a9, a6, 1 + 8e2805: 60000c j 8e2815 + +008e2808 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:273 + 8e2808: 2a7000 l8ui a10, a7, 0 + 8e280b: b177 addi.n a7, a7, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:274 + 8e280d: 0b5000 callx8 a5 + 8e2810: 291212 l32i a9, a1, 72 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:275 + 8e2813: b122 addi.n a2, a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:272 + 8e2815: b066 addi.n a6, a6, -1 + 8e2817: b099 addi.n a9, a9, -1 + 8e2819: 291612 s32i a9, a1, 72 + 8e281c: 6b91e8 bgei a9, 1, 8e2808 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:277 + 8e281f: 8c1d l32i.n a12, a1, 52 + 8e2821: 9718 s32i.n a7, a1, 32 + 8e2823: 64cd2f beqz a12, 8e2556 + 8e2826: 8d1f l32i.n a13, a1, 60 + 8e2828: b1dd addi.n a13, a13, 1 + 8e282a: 9d19 s32i.n a13, a1, 36 + 8e282c: 60008a j 8e28ba + +008e282f : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:139 + 8e282f: c0a0 movi.n a10, 0 + 8e2831: 63fe02 j 8e2637 + +008e2834 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:157 + 8e2834: 64b10c beqz a11, 8e2944 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:158 + 8e2837: 2f1211 l32i a15, a1, 68 + 8e283a: c1b8 movi.n a11, 24 + 8e283c: c1e8 movi.n a14, 24 + 8e283e: daf0 mov.n a10, a15 + 8e2840: b4ff addi.n a15, a15, 4 + 8e2842: 2f1611 s32i a15, a1, 68 + 8e2845: 7fe27d blt a14, a15, 8e28c6 + 8e2848: 8a1a l32i.n a10, a1, 40 + 8e284a: 63fe48 j 8e2696 + +008e284d : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:247 + 8e284d: 280a64 movi a8, 100 + 8e2850: 78723d blt a7, a8, 8e2891 + 8e2853: 290a64 movi a9, 100 + 8e2856: 779202 blt a9, a7, 8e285c + 8e2859: 63fe90 j 8e26ed + 8e285c: 2a0a70 movi a10, 112 + 8e285f: 7a7934 bne a7, a10, 8e2897 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:182 + 8e2862: c3a0 movi.n a10, 48 + 8e2864: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:183 + 8e2867: 2a0a78 movi a10, 120 + 8e286a: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:185 + 8e286d: c0b8 movi.n a11, 8 + 8e286f: c0c1 movi.n a12, 1 + 8e2871: 9c1e s32i.n a12, a1, 56 + 8e2873: 9b1c s32i.n a11, a1, 48 + 8e2875: 63fe74 j 8e26ed + +008e2878 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:247 + 8e2878: c5d3 movi.n a13, 83 + 8e287a: 7d7919 bne a7, a13, 8e2897 + +008e287d : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:211 + 8e287d: 2f1211 l32i a15, a1, 68 + 8e2880: c1e8 movi.n a14, 24 + 8e2882: dbf0 mov.n a11, a15 + 8e2884: b4ff addi.n a15, a15, 4 + 8e2886: 2f1611 s32i a15, a1, 68 + 8e2889: 7fe246 blt a14, a15, 8e28d3 + 8e288c: 891a l32i.n a9, a1, 40 + 8e288e: 60004d j 8e28df + +008e2891 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:247 + 8e2891: 280a63 movi a8, 99 + 8e2894: 787179 beq a7, a8, 8e2911 + +008e2897 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:244 + 8e2897: c2a5 movi.n a10, 37 + 8e2899: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:245 + 8e289c: da70 mov.n a10, a7 + 8e289e: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:246 + 8e28a1: b222 addi.n a2, a2, 2 + 8e28a3: 63ff02 j 8e27a9 + +008e28a6 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:247 + 8e28a6: c295 movi.n a9, 37 + 8e28a8: 7979eb bne a7, a9, 8e2897 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:241 + 8e28ab: c2a5 movi.n a10, 37 + 8e28ad: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:242 + 8e28b0: 63fef5 j 8e27a9 + +008e28b3 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:279 + 8e28b3: c2a0 movi.n a10, 32 + 8e28b5: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:280 + 8e28b8: b122 addi.n a2, a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:278 + 8e28ba: 8a19 l32i.n a10, a1, 36 + 8e28bc: b0aa addi.n a10, a10, -1 + 8e28be: 9a19 s32i.n a10, a1, 36 + 8e28c0: 6ba1ef bgei a10, 1, 8e28b3 + 8e28c3: 63fc8f j 8e2556 + +008e28c6 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:158 + 8e28c6: 7ab204 blt a11, a10, 8e28ce + 8e28c9: c2c4 movi.n a12, 36 + +008e28cb : + 8e28cb: 2c1611 s32i a12, a1, 68 + 8e28ce: 8a1b l32i.n a10, a1, 44 + 8e28d0: 63fdc2 j 8e2696 + +008e28d3 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:211 + 8e28d3: c1d8 movi.n a13, 24 + 8e28d5: 7bd204 blt a13, a11, 8e28dd + 8e28d8: c2e4 movi.n a14, 36 + +008e28da : + 8e28da: 2e1611 s32i a14, a1, 68 + 8e28dd: 891b l32i.n a9, a1, 44 + 8e28df: 2f1211 l32i a15, a1, 68 + 8e28e2: a9ff add.n a15, a15, a9 + 8e28e4: 2ffdff addmi a15, a15, 0xffffff00 + 8e28e7: 2ff23f l32i a15, a15, 252 + 8e28ea: 9f18 s32i.n a15, a1, 32 + 8e28ec: ccf3 bnez.n a15, 8e28f3 + 8e28ee: 1800a7 l32r a8, 4e829c <_lit4_start+0x29c> + 8e28f1: 9818 s32i.n a8, a1, 32 + +008e28f3 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:216 + 8e28f3: 8918 l32i.n a9, a1, 32 + 8e28f5: 299000 l8ui a9, a9, 0 + 8e28f8: c060 movi.n a6, 0 + 8e28fa: 64907a beqz a9, 8e2978 + 8e28fd: 8918 l32i.n a9, a1, 32 + +008e28ff : + 8e28ff: 2a9001 l8ui a10, a9, 1 + 8e2902: b166 addi.n a6, a6, 1 + 8e2904: b199 addi.n a9, a9, 1 + 8e2906: 65aff5 bnez a10, 8e28ff + 8e2909: 63fe9c j 8e27a9 + +008e290c : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:247 + 8e290c: c4b3 movi.n a11, 67 + 8e290e: 7b7985 bne a7, a11, 8e2897 + +008e2911 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:220 + 8e2911: 2d1211 l32i a13, a1, 68 + 8e2914: c1c8 movi.n a12, 24 + 8e2916: dbd0 mov.n a11, a13 + 8e2918: b4dd addi.n a13, a13, 4 + 8e291a: 2d1611 s32i a13, a1, 68 + 8e291d: 7dca02 bge a12, a13, 8e2923 + 8e2920: 63fc60 j 8e2584 + 8e2923: 8b1a l32i.n a11, a1, 40 + 8e2925: 63fc67 j 8e2590 + +008e2928 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:288 + 8e2928: d10f retw.n + +008e292a : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:197 + 8e292a: da40 mov.n a10, a4 + 8e292c: db10 mov.n a11, a1 + 8e292e: c0ca movi.n a12, 10 + 8e2930: 1d00a8 l32r a13, 4e82a0 <_lit4_start+0x2a0> + 8e2933: 5bfeec call8 8e24e4 <_cvt> + 8e2936: d6a0 mov.n a6, a10 + 8e2938: 63fe69 j 8e27a5 + +008e293b : + 8e293b: 2e7c8b addi a14, a7, -117 + 8e293e: 65ef55 bnez a14, 8e2897 + 8e2941: 63fda8 j 8e26ed + +008e2944 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:160 + 8e2944: 281211 l32i a8, a1, 68 + 8e2947: c1f8 movi.n a15, 24 + 8e2949: da80 mov.n a10, a8 + 8e294b: b488 addi.n a8, a8, 4 + 8e294d: 281611 s32i a8, a1, 68 + 8e2950: 78f204 blt a15, a8, 8e2958 + 8e2953: 8a1a l32i.n a10, a1, 40 + 8e2955: 63fd3d j 8e2696 + +008e2958 : + 8e2958: c198 movi.n a9, 24 + 8e295a: 7a9204 blt a9, a10, 8e2962 + 8e295d: c2a4 movi.n a10, 36 + +008e295f : + 8e295f: 2a1611 s32i a10, a1, 68 + 8e2962: 8a1b l32i.n a10, a1, 44 + 8e2964: 63fd2e j 8e2696 + +008e2967 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:204 + 8e2967: da40 mov.n a10, a4 + 8e2969: db10 mov.n a11, a1 + 8e296b: c1c0 movi.n a12, 16 + 8e296d: 1d00a9 l32r a13, 4e82a4 <_lit4_start+0x2a4> + 8e2970: 5bfedc call8 8e24e4 <_cvt> + 8e2973: d6a0 mov.n a6, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:205 + 8e2975: 63fe2c j 8e27a5 + +008e2978 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:216 + 8e2978: c060 movi.n a6, 0 + 8e297a: 63fe2b j 8e27a9 + +008e297d : + 8e297d: 000000 ... + +008e2980 : +cmnos_printf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:292 + 8e2980: 6c100a entry a1, 80 + 8e2983: db20 mov.n a11, a2 + 8e2985: 9214 s32i.n a2, a1, 16 + 8e2987: 9416 s32i.n a4, a1, 24 + 8e2989: 9517 s32i.n a5, a1, 28 + 8e298b: 9618 s32i.n a6, a1, 32 + 8e298d: 9719 s32i.n a7, a1, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:300 + 8e298f: de10 mov.n a14, a1 + 8e2991: 1a00aa l32r a10, 4e82a8 <_lit4_start+0x2a8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:292 + 8e2994: 9315 s32i.n a3, a1, 20 + 8e2996: 2f1c30 addi a15, a1, 48 + 8e2999: 2d1c10 addi a13, a1, 16 + 8e299c: 9d11 s32i.n a13, a1, 4 + 8e299e: 9f10 s32i.n a15, a1, 0 + 8e29a0: c034 movi.n a3, 4 + 8e29a2: 9312 s32i.n a3, a1, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:300 + 8e29a4: 8aa0 l32i.n a10, a10, 0 + 8e29a6: 8ce0 l32i.n a12, a14, 0 + 8e29a8: 8de1 l32i.n a13, a14, 4 + 8e29aa: 8ee2 l32i.n a14, a14, 8 + 8e29ac: 5bfee2 call8 8e2538 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:307 + 8e29af: d2a0 mov.n a2, a10 + 8e29b1: d10f retw.n + +008e29b3 : + ... + +008e29b4 : +cmnos_printf_init(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:312 + 8e29b4: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:313 + 8e29b7: d10f retw.n + +008e29b9 : + 8e29b9: 000000 ... + +008e29bc : +cmnos_printf_module_install(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:316 + 8e29bc: 6c1004 entry a1, 32 + 8e29bf: 1800ab l32r a8, 4e82ac <_lit4_start+0x2ac> + 8e29c2: 1300ac l32r a3, 4e82b0 <_lit4_start+0x2b0> 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8e29da: 8d22 l32i.n a13, a2, 8 + 8e29dc: 1a00ad l32r a10, 4e82b4 <_lit4_start+0x2b4> + 8e29df: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:43 + 8e29e2: d10f retw.n + +008e29e4 <_read_rom_patch>: +_read_rom_patch(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:49 + 8e29e4: 6c1004 entry a1, 32 + 8e29e7: 1900ae l32r a9, 4e82b8 <_lit4_start+0x2b8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:60 + 8e29ea: 8321 l32i.n a3, a2, 4 + 8e29ec: 1800af l32r a8, 4e82bc <_lit4_start+0x2bc> + 8e29ef: 140018 l32r a4, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:61 + 8e29f2: a939 add.n a9, a3, a9 + 8e29f4: 798b0e bgeu a8, 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:99 + 8e2ffd: d10f retw.n + +008e2fff <__pci_get_rx_eng+0x17>: + 8e2fff: c020 movi.n a2, 0 + 8e3001: d10f retw.n + +008e3003 <__pci_get_rx_eng+0x1b>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:102 + 8e3003: c021 movi.n a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:99 + 8e3005: d10f retw.n + +008e3007 <__pci_get_rx_eng+0x1f>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:105 + 8e3007: c022 movi.n a2, 2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:99 + 8e3009: d10f retw.n + +008e300b <__pci_get_rx_eng+0x23>: + ... + +008e300c <__pci_enable>: +__pci_enable(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:118 + 8e300c: 6c1004 entry a1, 32 + 8e300f: 1a00e5 l32r a10, 4e8394 <_lit4_start+0x394> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:124 + 8e3012: 5bffe0 call8 8e2f94 <__pci_reg_read> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:126 + 8e3015: c0b8 movi.n a11, 8 + 8e3017: 0bab02 or a11, a10, a11 + 8e301a: 1a00e5 l32r a10, 4e8394 <_lit4_start+0x394> + 8e301d: 5bffe0 call8 8e2fa0 <__pci_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:127 + 8e3020: d10f retw.n + +008e3022 <__pci_enable+0x16>: + ... + +008e3024 <__pci_reset>: +__pci_reset(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:135 + 8e3024: 6c1006 entry a1, 48 + 8e3027: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:141 + 8e302a: 282212 l32i a8, a2, 72 + 8e302d: 1a00e6 l32r a10, 4e8398 <_lit4_start+0x398> + +008e3030 <__pci_reset+0xc>: + 8e3030: 0b8000 callx8 a8 + 8e3033: 1a00e7 l32r a10, 4e839c <_lit4_start+0x39c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:143 + 8e3036: 5bffd7 call8 8e2f94 <__pci_reg_read> + 8e3039: 0c0200 memw + 8e303c: 9a10 s32i.n a10, a1, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:145 + 8e303e: 0c0200 memw + 8e3041: 8910 l32i.n a9, a1, 0 + 8e3043: 7197ec bbci a9, 17, 8e3033 <__pci_reset+0xf> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:148 + 8e3046: 282212 l32i a8, a2, 72 + 8e3049: 1a00e8 l32r a10, 4e83a0 <_lit4_start+0x3a0> + 8e304c: 0b8000 callx8 a8 + 8e304f: 1a00e7 l32r a10, 4e839c <_lit4_start+0x39c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:154 + 8e3052: 5bffd0 call8 8e2f94 <__pci_reg_read> + 8e3055: 1300e9 l32r a3, 4e83a4 <_lit4_start+0x3a4> + 8e3058: 0c0200 memw + 8e305b: 9a10 s32i.n a10, a1, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:155 + 8e305d: 0c0200 memw + 8e3060: 8910 l32i.n a9, a1, 0 + 8e3062: 039901 and a9, a9, a3 + 8e3065: 0c0200 memw + 8e3068: 9910 s32i.n a9, a1, 0 + 8e306a: 1a00e7 l32r a10, 4e839c <_lit4_start+0x39c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:156 + 8e306d: 0c0200 memw + 8e3070: 8b10 l32i.n a11, a1, 0 + 8e3072: 5bffcb call8 8e2fa0 <__pci_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:158 + 8e3075: 28223b l32i a8, a2, 236 + 8e3078: c0aa movi.n a10, 10 + 8e307a: 0b8000 callx8 a8 + 8e307d: 1a00e7 l32r a10, 4e839c <_lit4_start+0x39c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:164 + 8e3080: 5bffc4 call8 8e2f94 <__pci_reg_read> + 8e3083: 0c0200 memw + 8e3086: 9a10 s32i.n a10, a1, 0 + 8e3088: 1a00ea l32r a10, 4e83a8 <_lit4_start+0x3a8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:165 + 8e308b: 0c0200 memw + 8e308e: 8910 l32i.n a9, a1, 0 + 8e3090: 0a9902 or a9, a9, a10 + 8e3093: 0c0200 memw + 8e3096: 9910 s32i.n a9, a1, 0 + 8e3098: 1a00e7 l32r a10, 4e839c <_lit4_start+0x39c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:166 + 8e309b: 0c0200 memw + 8e309e: 8b10 l32i.n a11, a1, 0 + 8e30a0: 5bffbf call8 8e2fa0 <__pci_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:168 + 8e30a3: 28223b l32i a8, a2, 236 + 8e30a6: c0aa movi.n a10, 10 + 8e30a8: 0b8000 callx8 a8 + 8e30ab: 1a00e7 l32r a10, 4e839c <_lit4_start+0x39c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:174 + 8e30ae: 5bffb9 call8 8e2f94 <__pci_reg_read> + 8e30b1: 0c0200 memw + 8e30b4: 9a10 s32i.n a10, a1, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:175 + 8e30b6: 0c0200 memw + 8e30b9: 8910 l32i.n a9, a1, 0 + 8e30bb: 039901 and a9, a9, a3 + 8e30be: 0c0200 memw + 8e30c1: 9910 s32i.n a9, a1, 0 + 8e30c3: 1a00e7 l32r a10, 4e839c <_lit4_start+0x39c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:176 + 8e30c6: 0c0200 memw + 8e30c9: 8b10 l32i.n a11, a1, 0 + 8e30cb: 5bffb5 call8 8e2fa0 <__pci_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:178 + 8e30ce: 28223b l32i a8, a2, 236 + 8e30d1: c0aa movi.n a10, 10 + 8e30d3: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:179 + 8e30d6: d10f retw.n + +008e30d8 <__pci_boot_init>: +__pci_boot_init(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:185 + 8e30d8: 6c1004 entry a1, 32 + 8e30db: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:186 + 8e30de: 2822cc l32i a8, a2, 0x330 + 8e30e1: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:187 + 8e30e4: 2822cd l32i a8, a2, 0x334 + 8e30e7: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:189 + 8e30ea: 2822bd l32i a8, a2, 0x2f4 + 8e30ed: c0a4 movi.n a10, 4 + 8e30ef: c0b1 movi.n a11, 1 + 8e30f1: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:190 + 8e30f4: 2822bf l32i a8, a2, 0x2fc + 8e30f7: c0a0 movi.n a10, 0 + 8e30f9: c0b1 movi.n a11, 1 + 8e30fb: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:192 + 8e30fe: c0a0 movi.n a10, 0 + 8e3100: 2822c0 l32i a8, a2, 0x300 + 8e3103: c0b2 movi.n a11, 2 + 8e3105: 2c6a80 movi a12, 0x680 + 8e3108: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:195 + 8e310b: d10f retw.n + +008e310d <__pci_boot_init+0x35>: + 8e310d: 000000 ... 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8e312f: c0a5 movi.n a10, 5 + 8e3131: c0b1 movi.n a11, 1 + 8e3133: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:218 + 8e3136: 2822bf l32i a8, a2, 0x2fc + 8e3139: c0a0 movi.n a10, 0 + 8e313b: c0b1 movi.n a11, 1 + 8e313d: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:219 + 8e3140: 2822bf l32i a8, a2, 0x2fc + 8e3143: c0a1 movi.n a10, 1 + 8e3145: c0b1 movi.n a11, 1 + 8e3147: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:220 + 8e314a: 2822bf l32i a8, a2, 0x2fc + 8e314d: c0a2 movi.n a10, 2 + 8e314f: c0b1 movi.n a11, 1 + 8e3151: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:221 + 8e3154: 2822bf l32i a8, a2, 0x2fc + 8e3157: c0a3 movi.n a10, 3 + 8e3159: c0b1 movi.n a11, 1 + 8e315b: 0b8000 callx8 a8 + 8e315e: 1200eb l32r a2, 4e83ac <_lit4_start+0x3ac> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:223 + 8e3161: d10f retw.n + +008e3163 <__pci_init+0x53>: + ... + +008e3164 <__pci_cfg_pipe>: +__pci_cfg_pipe(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:234 + 8e3164: 6c1004 entry a1, 32 + 8e3167: 160018 l32r a6, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:238 + 8e316a: 2862d2 l32i a8, a6, 0x348 + 8e316d: da30 mov.n a10, a3 + 8e316f: 0b8000 callx8 a8 + 8e3172: d5a0 mov.n a5, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:240 + 8e3174: 69a60a bnei a10, 6, 8e3182 <__pci_cfg_pipe+0x1e> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:241 + 8e3177: 286212 l32i a8, a6, 72 + 8e317a: 1a00ec l32r a10, 4e83b0 <_lit4_start+0x3b0> + 8e317d: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:248 + 8e3180: d10f retw.n + +008e3182 <__pci_cfg_pipe+0x1e>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:245 + 8e3182: 286279 l32i a8, a6, 0x1e4 + 8e3185: db30 mov.n a11, a3 + 8e3187: da20 mov.n a10, a2 + 8e3189: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:247 + 8e318c: 040b4f extui a11, a4, 0, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:245 + 8e318f: dca0 mov.n a12, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:247 + 8e3191: 2862c0 l32i a8, a6, 0x300 + 8e3194: da50 mov.n a10, a5 + 8e3196: 0c0c4f extui a12, a12, 0, 16 + 8e3199: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:248 + 8e319c: d10f retw.n + +008e319e <__pci_cfg_pipe+0x3a>: + ... + +008e31a0 <__pci_start>: +__pci_start(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:256 + 8e31a0: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:257 + 8e31a3: d10f retw.n + +008e31a5 <__pci_start+0x5>: + 8e31a5: 000000 ... + +008e31a8 <__pci_reg_callback>: +__pci_reg_callback(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:267 + 8e31a8: 6c1004 entry a1, 32 + 8e31ab: 1400eb l32r a4, 4e83ac <_lit4_start+0x3ac> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:270 + 8e31ae: 8932 l32i.n a9, a3, 8 + 8e31b0: 9942 s32i.n a9, a4, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:271 + 8e31b2: 8831 l32i.n a8, a3, 4 + 8e31b4: 9841 s32i.n a8, a4, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:272 + 8e31b6: 8230 l32i.n a2, a3, 0 + 8e31b8: 9240 s32i.n a2, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:273 + 8e31ba: d10f retw.n + +008e31bc <__pci_reap_xmitted>: +__pci_reap_xmitted(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:283 + 8e31bc: 6c1004 entry a1, 32 + 8e31bf: 140018 l32r a4, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:287 + 8e31c2: 2842d0 l32i a8, a4, 0x340 + 8e31c5: da30 mov.n a10, a3 + 8e31c7: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:289 + 8e31ca: 2842c6 l32i a8, a4, 0x318 + 8e31cd: da30 mov.n a10, a3 + 8e31cf: 0b8000 callx8 a8 + 8e31d2: c8a7 beqz.n a10, 8e31dd <__pci_reap_xmitted+0x21> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:292 + 8e31d4: 8820 l32i.n a8, a2, 0 + 8e31d6: 8b22 l32i.n a11, a2, 8 + 8e31d8: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:297 + 8e31db: d10f retw.n + +008e31dd <__pci_reap_xmitted+0x21>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:294 + 8e31dd: 284212 l32i a8, a4, 72 + 8e31e0: 1a00ed l32r a10, 4e83b4 <_lit4_start+0x3b4> + 8e31e3: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:297 + 8e31e6: d10f retw.n + +008e31e8 <__pci_reap_recv>: +__pci_reap_recv(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:308 + 8e31e8: 6c1004 entry a1, 32 + 8e31eb: da30 mov.n a10, a3 + 8e31ed: 130018 l32r a3, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:311 + 8e31f0: 2832c7 l32i a8, a3, 0x31c + 8e31f3: 0b8000 callx8 a8 + 8e31f6: dba0 mov.n a11, a10 + 8e31f8: c8a9 beqz.n a10, 8e3205 <__pci_reap_recv+0x1d> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:314 + 8e31fa: 8821 l32i.n a8, a2, 4 + 8e31fc: 8c22 l32i.n a12, a2, 8 + 8e31fe: c0a0 movi.n a10, 0 + 8e3200: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:317 + 8e3203: d10f retw.n + +008e3205 <__pci_reap_recv+0x1d>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:316 + 8e3205: 283212 l32i a8, a3, 72 + 8e3208: 1a00ee l32r a10, 4e83b8 <_lit4_start+0x3b8> + 8e320b: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:317 + 8e320e: d10f retw.n + +008e3210 <__pci_isr_handler>: +__pci_isr_handler(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:325 + 8e3210: 6c1004 entry a1, 32 + 8e3213: 1300eb l32r a3, 4e83ac <_lit4_start+0x3ac> + 8e3216: 120018 l32r a2, 4e8060 <_lit4_start+0x60> + 8e3219: 600009 j 8e3226 <__pci_isr_handler+0x16> + +008e321c <__pci_isr_handler+0xc>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:330 + 8e321c: 2822cf l32i a8, a2, 0x33c + 8e321f: da30 mov.n a10, a3 + 8e3221: c0b3 movi.n a11, 3 + 8e3223: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:329 + 8e3226: 2822c9 l32i a8, a2, 0x324 + 8e3229: c0a3 movi.n a10, 3 + 8e322b: 0b8000 callx8 a8 + 8e322e: 65afea bnez a10, 8e321c <__pci_isr_handler+0xc> + 8e3231: 600009 j 8e323e <__pci_isr_handler+0x2e> + +008e3234 <__pci_isr_handler+0x24>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:333 + 8e3234: 2822cf l32i a8, a2, 0x33c + 8e3237: da30 mov.n a10, a3 + 8e3239: c0b2 movi.n a11, 2 + 8e323b: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:332 + 8e323e: 2822c9 l32i a8, a2, 0x324 + 8e3241: c0a2 movi.n a10, 2 + 8e3243: 0b8000 callx8 a8 + 8e3246: 65afea bnez a10, 8e3234 <__pci_isr_handler+0x24> + 8e3249: 600009 j 8e3256 <__pci_isr_handler+0x46> + +008e324c <__pci_isr_handler+0x3c>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:336 + 8e324c: 2822cf l32i a8, a2, 0x33c + 8e324f: da30 mov.n a10, a3 + 8e3251: c0b1 movi.n a11, 1 + 8e3253: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:335 + 8e3256: 2822c9 l32i a8, a2, 0x324 + 8e3259: c0a1 movi.n a10, 1 + 8e325b: 0b8000 callx8 a8 + 8e325e: 65afea bnez a10, 8e324c <__pci_isr_handler+0x3c> + 8e3261: 600009 j 8e326e <__pci_isr_handler+0x5e> + +008e3264 <__pci_isr_handler+0x54>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:339 + 8e3264: 2822ce l32i a8, a2, 0x338 + 8e3267: da30 mov.n a10, a3 + 8e3269: c0b5 movi.n a11, 5 + 8e326b: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:338 + 8e326e: 2822c5 l32i a8, a2, 0x314 + 8e3271: c0a5 movi.n a10, 5 + 8e3273: 0b8000 callx8 a8 + 8e3276: 65afea bnez a10, 8e3264 <__pci_isr_handler+0x54> + +008e3279 <__pci_isr_handler+0x69>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:345 + 8e3279: 2822c5 l32i a8, a2, 0x314 + 8e327c: c0a4 movi.n a10, 4 + 8e327e: 0b8000 callx8 a8 + 8e3281: c8ad beqz.n a10, 8e3292 <__pci_isr_handler+0x82> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:346 + 8e3283: 2822ce l32i a8, a2, 0x338 + 8e3286: da30 mov.n a10, a3 + 8e3288: c0b4 movi.n a11, 4 + 8e328a: 0b8000 callx8 a8 + 8e328d: c041 movi.n a4, 1 + 8e328f: 600001 j 8e3294 <__pci_isr_handler+0x84> + +008e3292 <__pci_isr_handler+0x82>: + 8e3292: c040 movi.n a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:350 + 8e3294: 2822c9 l32i a8, a2, 0x324 + 8e3297: c0a0 movi.n a10, 0 + 8e3299: 0b8000 callx8 a8 + 8e329c: c8aa beqz.n a10, 8e32aa <__pci_isr_handler+0x9a> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:351 + 8e329e: 2822cf l32i a8, a2, 0x33c + 8e32a1: da30 mov.n a10, a3 + 8e32a3: c0b0 movi.n a11, 0 + 8e32a5: 0b8000 callx8 a8 + 8e32a8: c041 movi.n a4, 1 + +008e32aa <__pci_isr_handler+0x9a>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:355 + 8e32aa: 654fcb bnez a4, 8e3279 <__pci_isr_handler+0x69> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:357 + 8e32ad: d10f retw.n + +008e32af <__pci_isr_handler+0x9f>: + ... + +008e32b0 <__pci_xmit_buf>: +__pci_xmit_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:369 + 8e32b0: 6c1004 entry a1, 32 + 8e32b3: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:372 + 8e32b6: 2822d1 l32i a8, a2, 0x344 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:369 + 8e32b9: da30 mov.n a10, a3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:372 + 8e32bb: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:374 + 8e32be: 69a60c bnei a10, 6, 8e32ce <__pci_xmit_buf+0x1e> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:375 + 8e32c1: 282212 l32i a8, a2, 72 + 8e32c4: 1a00ef l32r a10, 4e83bc <_lit4_start+0x3bc> + 8e32c7: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:376 + 8e32ca: c72f movi.n a2, -1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:379 + 8e32cc: d10f retw.n + +008e32ce <__pci_xmit_buf+0x1e>: + 8e32ce: 2822c3 l32i a8, a2, 0x30c + 8e32d1: db40 mov.n a11, a4 + 8e32d3: 0b8000 callx8 a8 + 8e32d6: d2a0 mov.n a2, a10 + 8e32d8: d10f retw.n + +008e32da <__pci_xmit_buf+0x2a>: + ... + +008e32dc <__pci_return_recv>: +__pci_return_recv(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:390 + 8e32dc: 6c1004 entry a1, 32 + 8e32df: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:393 + 8e32e2: 2822d2 l32i a8, a2, 0x348 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:390 + 8e32e5: da30 mov.n a10, a3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:393 + 8e32e7: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:395 + 8e32ea: 68a607 beqi a10, 6, 8e32f5 <__pci_return_recv+0x19> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:398 + 8e32ed: 2822c8 l32i a8, a2, 0x320 + 8e32f0: db40 mov.n a11, a4 + +008e32f2 <__pci_return_recv+0x16>: + 8e32f2: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:399 + 8e32f5: d10f retw.n + +008e32f7 <__pci_return_recv+0x1b>: + ... + +008e32f8 <__pci_is_pipe_supported>: +__pci_is_pipe_supported(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:410 + 8e32f8: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:411 + 8e32fb: 6f3503 bgeui a3, 5, 8e3302 <__pci_is_pipe_supported+0xa> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:412 + 8e32fe: c021 movi.n a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:414 + 8e3300: d10f retw.n + +008e3302 <__pci_is_pipe_supported+0xa>: + 8e3302: c020 movi.n a2, 0 + 8e3304: d10f retw.n + +008e3306 <__pci_is_pipe_supported+0xe>: + ... + +008e3308 <__pci_get_max_msg_len>: +__pci_get_max_msg_len(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:426 + 8e3308: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:430 + 8e330b: 246a80 movi a4, 0x680 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:428 + 8e330e: 222a00 movi a2, 0x200 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:427 + 8e3311: 034239 movnez a2, a4, a3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:430 + 8e3314: d10f retw.n + +008e3316 <__pci_get_max_msg_len+0xe>: + ... + +008e3318 <__pci_get_reserved_headroom>: +__pci_get_reserved_headroom(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:441 + 8e3318: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:442 + 8e331b: c020 movi.n a2, 0 + 8e331d: d10f retw.n + +008e331f <__pci_get_reserved_headroom+0x7>: + ... + +008e3320 <__pci_shutdown>: +__pci_shutdown(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:451 + 8e3320: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:452 + 8e3323: d10f retw.n + +008e3325 <__pci_shutdown+0x5>: + 8e3325: 000000 ... + +008e3328 <__pci_get_def_pipe>: +__pci_get_def_pipe(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:457 + 8e3328: 6c1004 entry a1, 32 + 8e332b: c020 movi.n a2, 0 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mov.n a11, a3 + 8e35bc: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/target/adf/os/inc/adf_os_mem_pvt.h:10 + 8e35bf: 286252 l32i a8, a6, 0x148 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:280 + 8e35c2: dba0 mov.n a11, a10 +/root/Workspace/0412_v202/tgt/target/adf/os/inc/adf_os_mem_pvt.h:10 + 8e35c4: c0a0 movi.n a10, 0 + 8e35c6: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:280 + 8e35c9: 9a51 s32i.n a10, a5, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:281 + 8e35cb: 286279 l32i a8, a6, 0x1e4 + 8e35ce: db30 mov.n a11, a3 + 8e35d0: da20 mov.n a10, a2 + 8e35d2: 0b8000 callx8 a8 + 8e35d5: 2a5504 s16i a10, a5, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:274 + 8e35d8: 8b10 l32i.n a11, a1, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:296 + 8e35da: b144 addi.n a4, a4, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:282 + 8e35dc: c0c0 movi.n a12, 0 + 8e35de: 9c50 s32i.n a12, a5, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:283 + 8e35e0: 2c5505 s16i a12, a5, 10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:284 + 8e35e3: 2c5506 s16i a12, a5, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:285 + 8e35e6: 2c5507 s16i a12, a5, 14 + 8e35e9: c870 beqz.n a7, 8e35ed <_HIFusb_config_pipe+0x7d> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:293 + 8e35eb: 9750 s32i.n a7, a5, 0 + +008e35ed <_HIFusb_config_pipe+0x7d>: + 8e35ed: d750 mov.n a7, a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:274 + 8e35ef: 74b9b5 bne a11, a4, 8e35a8 <_HIFusb_config_pipe+0x38> + 8e35f2: 600001 j 8e35f7 <_HIFusb_config_pipe+0x87> + +008e35f5 <_HIFusb_config_pipe+0x85>: + 8e35f5: d7c0 mov.n a7, a12 + 8e35f7: c97e beqz.n a7, 8e3619 <_HIFusb_config_pipe+0xa9> + 8e35f9: 120104 l32r a2, 4e8410 <_lit4_start+0x410> + +008e35fc <_HIFusb_config_pipe+0x8c>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:196 + 8e35fc: 2862a1 l32i a8, a6, 0x284 + 8e35ff: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:200 + 8e3602: c0b0 movi.n a11, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:198 + 8e3604: 97a0 s32i.n a7, a10, 0 + 8e3606: dc70 mov.n a12, a7 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:202 + 8e3608: 892d l32i.n a9, a2, 52 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:199 + 8e360a: 8770 l32i.n a7, a7, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:200 + 8e360c: 9bc0 s32i.n a11, a12, 0 + 8e360e: c890 beqz.n a9, 8e3612 <_HIFusb_config_pipe+0xa2> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:205 + 8e3610: 99a1 s32i.n a9, a10, 4 + +008e3612 <_HIFusb_config_pipe+0xa2>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:206 + 8e3612: 9a2d s32i.n a10, a2, 52 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:195 + 8e3614: 657fe4 bnez a7, 8e35fc <_HIFusb_config_pipe+0x8c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:299 + 8e3617: d10f retw.n + +008e3619 <_HIFusb_config_pipe+0xa9>: + 8e3619: d10f retw.n + +008e361b <_HIFusb_config_pipe+0xab>: + ... + +008e361c <_HIFusb_send_buffer>: +_HIFusb_send_buffer(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:335 + 8e361c: 6c1004 entry a1, 32 + 8e361f: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:336 + 8e3622: 693335 bnei a3, 3, 8e365b <_HIFusb_send_buffer+0x3f> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:315 + 8e3625: 8a40 l32i.n a10, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:317 + 8e3627: 2da106 l16ui a13, a10, 12 + 8e362a: 0c0200 memw +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:318 + 8e362d: 8ca1 l32i.n a12, a10, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:317 + 8e362f: 2da50b s16i a13, a10, 22 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:318 + 8e3632: 2ba105 l16ui a11, a10, 10 + 8e3635: acbb add.n a11, a11, a12 + 8e3637: 0c0200 memw +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:320 + 8e363a: 2822b6 l32i a8, a2, 0x2d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:318 + 8e363d: 9ba7 s32i.n a11, a10, 28 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:320 + 8e363f: 2aac10 addi a10, a10, 16 + 8e3642: 0b8000 callx8 a8 + 8e3645: 1a0104 l32r a10, 4e8410 <_lit4_start+0x410> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:323 + 8e3648: 8eae l32i.n a14, a10, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:327 + 8e364a: 8baf l32i.n a11, a10, 60 + 8e364c: cee5 bnez.n a14, 8e3675 <_HIFusb_send_buffer+0x59> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:324 + 8e364e: 94ae s32i.n a4, a10, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:331 + 8e3650: 282297 l32i a8, a2, 0x25c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:328 + 8e3653: 94af s32i.n a4, a10, 60 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:331 + 8e3655: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:337 + 8e3658: 600015 j 8e3671 <_HIFusb_send_buffer+0x55> + +008e365b <_HIFusb_send_buffer+0x3f>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:339 + 8e365b: 2822b1 l32i a8, a2, 0x2c4 + 8e365e: db40 mov.n a11, a4 + 8e3660: 1a010a l32r a10, 4e8428 <_lit4_start+0x428> + 8e3663: 0b8000 callx8 a8 + 8e3666: 1a010f l32r a10, 4e843c <_lit4_start+0x43c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:343 + 8e3669: c091 movi.n a9, 1 + 8e366b: 0c0200 memw + 8e366e: 29a681 s32i a9, a10, 0x204 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:347 + 8e3671: c020 movi.n a2, 0 + 8e3673: d10f retw.n + +008e3675 <_HIFusb_send_buffer+0x59>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:327 + 8e3675: 94b1 s32i.n a4, a11, 4 + 8e3677: 63ffd5 j 8e3650 <_HIFusb_send_buffer+0x34> + +008e367a <_HIFusb_send_buffer+0x5e>: + ... + +008e367c <_HIFusb_return_recv_buf>: +_HIFusb_return_recv_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:352 + 8e367c: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:355 + 8e367f: 69340c bnei a3, 4, 8e368f <_HIFusb_return_recv_buf+0x13> + 8e3682: 1a0104 l32r a10, 4e8410 <_lit4_start+0x410> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:356 + 8e3685: 89ad l32i.n a9, a10, 52 + 8e3687: c890 beqz.n a9, 8e368b <_HIFusb_return_recv_buf+0xf> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:359 + 8e3689: 9941 s32i.n a9, a4, 4 + +008e368b <_HIFusb_return_recv_buf+0xf>: + 8e368b: 94ad s32i.n a4, a10, 52 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:367 + 8e368d: d10f retw.n + +008e368f <_HIFusb_return_recv_buf+0x13>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:363 + 8e368f: da30 mov.n a10, a3 + 8e3691: 5bffaf call8 8e3550 + 8e3694: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:364 + 8e3697: 2882b4 l32i a8, a8, 0x2d0 + 8e369a: db40 mov.n a11, a4 + 8e369c: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:365 + 8e369f: da30 mov.n a10, a3 + 8e36a1: 5bffa0 call8 8e3524 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:367 + 8e36a4: d10f retw.n + +008e36a6 <_HIFusb_return_recv_buf+0x2a>: + ... + +008e36a8 <_HIFusb_set_recv_bufsz>: +_HIFusb_set_recv_bufsz(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:370 + 8e36a8: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:373 + 8e36ab: d10f retw.n + +008e36ad <_HIFusb_set_recv_bufsz+0x5>: + 8e36ad: 000000 ... + +008e36b0 <_HIFusb_pause_recv>: +_HIFusb_pause_recv(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:376 + 8e36b0: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:378 + 8e36b3: d10f retw.n + +008e36b5 <_HIFusb_pause_recv+0x5>: + 8e36b5: 000000 ... + +008e36b8 <_HIFusb_resume_recv>: +_HIFusb_resume_recv(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:381 + 8e36b8: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:383 + 8e36bb: d10f retw.n + +008e36bd <_HIFusb_resume_recv+0x5>: + 8e36bd: 000000 ... + +008e36c0 <_HIFusb_is_pipe_supported>: +_HIFusb_is_pipe_supported(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:386 + 8e36c0: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:387 + 8e36c3: b034 addi.n a4, a3, -1 + 8e36c5: 6e4603 bltui a4, 6, 8e36cc <_HIFusb_is_pipe_supported+0xc> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:388 + 8e36c8: c020 movi.n a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:390 + 8e36ca: d10f retw.n + +008e36cc <_HIFusb_is_pipe_supported+0xc>: + 8e36cc: c021 movi.n a2, 1 + 8e36ce: d10f retw.n + +008e36d0 <_HIFusb_get_max_msg_len>: +_HIFusb_get_max_msg_len(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:395 + 8e36d0: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:403 + 8e36d3: 6b3506 bgei a3, 5, 8e36dd <_HIFusb_get_max_msg_len+0xd> + 8e36d6: 6a3303 blti a3, 3, 8e36dd <_HIFusb_get_max_msg_len+0xd> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:399 + 8e36d9: c420 movi.n a2, 64 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:402 + 8e36db: d10f retw.n + +008e36dd <_HIFusb_get_max_msg_len+0xd>: + 8e36dd: 226a40 movi a2, 0x640 + 8e36e0: d10f retw.n + +008e36e2 <_HIFusb_get_max_msg_len+0x12>: + ... + +008e36e4 <_HIFusb_isr_handler>: +_HIFusb_isr_handler(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:518 + 8e36e4: 6c1004 entry a1, 32 + 8e36e7: 190113 l32r a9, 4e844c <_lit4_start+0x44c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:525 + 8e36ea: 0c0200 memw + 8e36ed: 180114 l32r a8, 4e8450 <_lit4_start+0x450> + 8e36f0: 299280 l32i a9, a9, 0x200 + 8e36f3: 14010b l32r a4, 4e842c <_lit4_start+0x42c> + 8e36f6: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:532 + 8e36f9: 798802 bany a8, a9, 8e36ff <_HIFusb_isr_handler+0x1b> + 8e36fc: 60008f j 8e378f <_HIFusb_isr_handler+0xab> + 8e36ff: 234cdc addi a3, a4, -36 + 8e3702: 600012 j 8e3718 <_HIFusb_isr_handler+0x34> + +008e3705 <_HIFusb_isr_handler+0x21>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:488 + 8e3705: 2822b3 l32i a8, a2, 0x2cc + 8e3708: da40 mov.n a10, a4 + 8e370a: 0b8000 callx8 a8 + 8e370d: dba0 mov.n a11, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:489 + 8e370f: 8831 l32i.n a8, a3, 4 + 8e3711: 8c32 l32i.n a12, a3, 8 + 8e3713: c0a0 movi.n a10, 0 + 8e3715: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:538 + 8e3718: 2822b7 l32i a8, a2, 0x2dc + 8e371b: da40 mov.n a10, a4 + 8e371d: 0b8000 callx8 a8 + 8e3720: 65afe1 bnez a10, 8e3705 <_HIFusb_isr_handler+0x21> + 8e3723: 14010c l32r a4, 4e8430 <_lit4_start+0x430> + 8e3726: 600012 j 8e373c <_HIFusb_isr_handler+0x58> + +008e3729 <_HIFusb_isr_handler+0x45>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:511 + 8e3729: 2822b3 l32i a8, a2, 0x2cc + 8e372c: da40 mov.n a10, a4 + 8e372e: 0b8000 callx8 a8 + 8e3731: dba0 mov.n a11, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:512 + 8e3733: 8831 l32i.n a8, a3, 4 + 8e3735: 8c32 l32i.n a12, a3, 8 + 8e3737: c0a0 movi.n a10, 0 + 8e3739: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:553 + 8e373c: 2822b7 l32i a8, a2, 0x2dc + 8e373f: da40 mov.n a10, a4 + 8e3741: 0b8000 callx8 a8 + 8e3744: 65afe1 bnez a10, 8e3729 <_HIFusb_isr_handler+0x45> + 8e3747: 16010a l32r a6, 4e8428 <_lit4_start+0x428> + +008e374a <_HIFusb_isr_handler+0x66>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:555 + 8e374a: 246cf8 addi a4, a6, -8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:570 + 8e374d: 2822b7 l32i a8, a2, 0x2dc + 8e3750: da60 mov.n a10, a6 + 8e3752: 0b8000 callx8 a8 + 8e3755: c9a2 beqz.n a10, 8e376b <_HIFusb_isr_handler+0x87> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:439 + 8e3757: 2822b5 l32i a8, a2, 0x2d4 + 8e375a: da60 mov.n a10, a6 + 8e375c: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:440 + 8e375f: 8830 l32i.n a8, a3, 0 + 8e3761: 8b32 l32i.n a11, a3, 8 + 8e3763: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:572 + 8e3766: c051 movi.n a5, 1 + 8e3768: 600001 j 8e376d <_HIFusb_isr_handler+0x89> + +008e376b <_HIFusb_isr_handler+0x87>: + 8e376b: c050 movi.n a5, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:577 + 8e376d: 2822b7 l32i a8, a2, 0x2dc + 8e3770: da40 mov.n a10, a4 + 8e3772: 0b8000 callx8 a8 + 8e3775: c9a3 beqz.n a10, 8e378c <_HIFusb_isr_handler+0xa8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:466 + 8e3777: 2822b3 l32i a8, a2, 0x2cc + 8e377a: da40 mov.n a10, a4 + 8e377c: 0b8000 callx8 a8 + 8e377f: dba0 mov.n a11, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:467 + 8e3781: 8831 l32i.n a8, a3, 4 + 8e3783: 8c32 l32i.n a12, a3, 8 + 8e3785: c0a0 movi.n a10, 0 + 8e3787: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:579 + 8e378a: c051 movi.n a5, 1 + +008e378c <_HIFusb_isr_handler+0xa8>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:583 + 8e378c: 655fbd bnez a5, 8e374d <_HIFusb_isr_handler+0x69> + +008e378f <_HIFusb_isr_handler+0xab>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:590 + 8e378f: d10f retw.n + +008e3791 <_HIFusb_isr_handler+0xad>: + 8e3791: 000000 ... + +008e3794 <_HIFusb_get_default_pipe>: +_HIFusb_get_default_pipe(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:593 + 8e3794: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:595 + 8e3797: c023 movi.n a2, 3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:594 + 8e3799: c084 movi.n a8, 4 + 8e379b: 283400 s8i a8, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:595 + 8e379e: 224400 s8i a2, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:596 + 8e37a1: d10f retw.n + +008e37a3 <_HIFusb_get_default_pipe+0xf>: + ... + +008e37a4 : +hif_usb_module_install(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:601 + 8e37a4: 6c1004 entry a1, 32 + 8e37a7: 190115 l32r a9, 4e8454 <_lit4_start+0x454> + 8e37aa: 130117 l32r a3, 4e845c <_lit4_start+0x45c> + 8e37ad: 1a011d l32r a10, 4e8474 <_lit4_start+0x474> + 8e37b0: 1b011c l32r a11, 4e8470 <_lit4_start+0x470> + 8e37b3: 1c011b l32r a12, 4e846c <_lit4_start+0x46c> + 8e37b6: 1d011a l32r a13, 4e8468 <_lit4_start+0x468> + 8e37b9: 1e0119 l32r a14, 4e8464 <_lit4_start+0x464> + 8e37bc: 1f0118 l32r a15, 4e8460 <_lit4_start+0x460> + 8e37bf: 180116 l32r a8, 4e8458 <_lit4_start+0x458> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:604 + 8e37c2: 9824 s32i.n a8, a2, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:611 + 8e37c4: 9a22 s32i.n a10, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:610 + 8e37c6: 9b29 s32i.n a11, a2, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:609 + 8e37c8: 9c28 s32i.n a12, a2, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:608 + 8e37ca: 9d27 s32i.n a13, a2, 28 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:607 + 8e37cc: 9e26 s32i.n a14, a2, 24 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:606 + 8e37ce: 9f2b s32i.n a15, a2, 44 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:603 + 8e37d0: 9920 s32i.n a9, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:605 + 8e37d2: 9325 s32i.n a3, a2, 20 + 8e37d4: 18011f l32r a8, 4e847c <_lit4_start+0x47c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:613 + 8e37d7: 982a s32i.n a8, a2, 40 + 8e37d9: 130120 l32r a3, 4e8480 <_lit4_start+0x480> + 8e37dc: 19011e l32r a9, 4e8478 <_lit4_start+0x478> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:612 + 8e37df: 9921 s32i.n a9, a2, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:614 + 8e37e1: 932c s32i.n a3, a2, 48 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:618 + 8e37e3: d10f retw.n + +008e37e5 : + 8e37e5: 000000 ... + +008e37e8 : +HIFusb_DescTraceDump(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:621 + 8e37e8: 6c1004 entry a1, 32 + 8e37eb: 120018 l32r a2, 4e8060 <_lit4_start+0x60> + 8e37ee: 130104 l32r a3, 4e8410 <_lit4_start+0x410> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:623 + 8e37f1: 282212 l32i a8, a2, 72 + 8e37f4: 1a0121 l32r a10, 4e8484 <_lit4_start+0x484> + 8e37f7: 8b39 l32i.n a11, a3, 36 + 8e37f9: 0b8000 callx8 a8 + 8e37fc: 1a0122 l32r a10, 4e8488 <_lit4_start+0x488> + 8e37ff: 150110 l32r a5, 4e8440 <_lit4_start+0x440> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:624 + 8e3802: 0c0200 memw + 8e3805: 282212 l32i a8, a2, 72 + 8e3808: 2b52c6 l32i a11, a5, 0x318 + 8e380b: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:626 + 8e380e: 2822b8 l32i a8, a2, 0x2e0 + 8e3811: 1a010b l32r a10, 4e842c <_lit4_start+0x42c> + 8e3814: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:630 + 8e3817: 282212 l32i a8, a2, 72 + 8e381a: 1a0123 l32r a10, 4e848c <_lit4_start+0x48c> + 8e381d: 8b3b l32i.n a11, a3, 44 + 8e381f: 0b8000 callx8 a8 + 8e3822: 1a0122 l32r a10, 4e8488 <_lit4_start+0x488> + 8e3825: 14010f l32r a4, 4e843c <_lit4_start+0x43c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:631 + 8e3828: 0c0200 memw + 8e382b: 282212 l32i a8, a2, 72 + 8e382e: 8b46 l32i.n a11, a4, 24 + 8e3830: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:633 + 8e3833: 2822b8 l32i a8, a2, 0x2e0 + 8e3836: 1a010c l32r a10, 4e8430 <_lit4_start+0x430> + 8e3839: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:636 + 8e383c: 282212 l32i a8, a2, 72 + 8e383f: 1a0124 l32r a10, 4e8490 <_lit4_start+0x490> + 8e3842: 8b33 l32i.n a11, a3, 12 + 8e3844: 0b8000 callx8 a8 + 8e3847: 1a0122 l32r a10, 4e8488 <_lit4_start+0x488> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:637 + 8e384a: 0c0200 memw + 8e384d: 282212 l32i a8, a2, 72 + 8e3850: 2b5286 l32i a11, a5, 0x218 + 8e3853: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:638 + 8e3856: 2822b8 l32i a8, a2, 0x2e0 + 8e3859: 1a0109 l32r a10, 4e8424 <_lit4_start+0x424> + 8e385c: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:640 + 8e385f: 282212 l32i a8, a2, 72 + 8e3862: 8b35 l32i.n a11, a3, 20 + 8e3864: 1a0125 l32r a10, 4e8494 <_lit4_start+0x494> + 8e3867: 0b8000 callx8 a8 + 8e386a: 1a0122 l32r a10, 4e8488 <_lit4_start+0x488> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:641 + 8e386d: 0c0200 memw + 8e3870: 282212 l32i a8, a2, 72 + 8e3873: 2b4285 l32i a11, a4, 0x214 + 8e3876: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:642 + 8e3879: 2822b8 l32i a8, a2, 0x2e0 + 8e387c: 1a010a l32r a10, 4e8428 <_lit4_start+0x428> + 8e387f: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:643 + 8e3882: d10f retw.n + +008e3884 : +vUsb_ep0tx(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:319 + 8e3884: 6c1004 entry a1, 32 + 8e3887: 120126 l32r a2, 4e8498 <_lit4_start+0x498> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:331 + 8e388a: 882c l32i.n a8, a2, 48 + 8e388c: 1a0127 l32r a10, 4e849c <_lit4_start+0x49c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:328 + 8e388f: c490 movi.n a9, 64 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:331 + 8e3891: 688108 beqi a8, 1, 8e389d +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:328 + 8e3894: 0c0200 memw + 8e3897: 29a488 s8i a9, a10, 136 + 8e389a: 600008 j 8e38a6 + +008e389d : + 8e389d: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:323 + 8e38a0: 288235 l32i a8, a8, 212 + 8e38a3: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:333 + 8e38a6: c090 movi.n a9, 0 + 8e38a8: 992b s32i.n a9, a2, 44 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:334 + 8e38aa: d10f retw.n + +008e38ac : +vUsb_ep0rx(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:345 + 8e38ac: 6c1004 entry a1, 32 + 8e38af: 120126 l32r a2, 4e8498 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8e3a74: 2b2488 s8i a11, a2, 136 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:558 + 8e3a77: 865b l32i.n a6, a5, 44 + 8e3a79: 63ff77 j 8e39f4 + +008e3a7c : +bSet_address(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:584 + 8e3a7c: 6c1004 entry a1, 32 + 8e3a7f: 140126 l32r a4, 4e8498 <_lit4_start+0x498> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:588 + 8e3a82: 224103 l16ui a2, a4, 6 + 8e3a85: 130127 l32r a3, 4e849c <_lit4_start+0x49c> + 8e3a88: 6e2f03 bltui a2, 0x100, 8e3a8f +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:589 + 8e3a8b: c020 movi.n a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:597 + 8e3a8d: d10f retw.n + +008e3a8f : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:594 + 8e3a8f: 0c0200 memw + 8e3a92: 223482 s8i a2, a3, 130 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:596 + 8e3a95: c021 movi.n a2, 1 + 8e3a97: 924b s32i.n a2, a4, 44 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:597 + 8e3a99: d10f retw.n + +008e3a9b : + ... + +008e3a9c : +bGet_descriptor(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:610 + 8e3a9c: 6c1004 entry a1, 32 + 8e3a9f: 1a0126 l32r a10, 4e8498 <_lit4_start+0x498> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:694 + 8e3aa2: 2ba103 l16ui a11, a10, 6 + 8e3aa5: 0b8947 extui a9, a11, 8, 8 + 8e3aa8: 689132 beqi a9, 1, 8e3ade + 8e3aab: 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minu a9, a9, a11 + 8e3acb: 29a512 s16i a9, a10, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:700 + 8e3ace: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:701 + 8e3ad1: c021 movi.n a2, 1 + 8e3ad3: d10f retw.n + +008e3ad5 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:643 + 8e3ad5: 0b0947 extui a9, a11, 0, 8 + 8e3ad8: cb93 beqz.n a9, 8e3b0f + +008e3ada : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:693 + 8e3ada: c020 movi.n a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:701 + 8e3adc: d10f retw.n + +008e3ade : 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a1, 32 + 8e3d8f: 190126 l32r a9, 4e8498 <_lit4_start+0x498> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1005 + 8e3d92: c031 movi.n a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1002 + 8e3d94: c460 movi.n a6, 64 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1005 + 8e3d96: 259112 l16ui a5, a9, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1010 + 8e3d99: d760 mov.n a7, a6 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1015 + 8e3d9b: 8498 l32i.n a4, a9, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1005 + 8e3d9d: 050847 extui a8, a5, 0, 8 + 8e3da0: 6e5d01 bltui a5, 64, 8e3da5 + 8e3da3: c030 movi.n a3, 0 + +008e3da5 : + 8e3da5: 038639 movnez a6, a8, a3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1010 + 8e3da8: 038739 movnez a7, a8, a3 + 8e3dab: 07550c sub a5, a5, a7 + 8e3dae: 05054f extui a5, a5, 0, 16 + 8e3db1: 259512 s16i a5, a9, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1017 + 8e3db4: b367 addi.n a7, a6, 3 + 8e3db6: 072712 srai a7, a7, 2 + 8e3db9: 6a7138 blti a7, 1, 8e3df5 + 8e3dbc: 160128 l32r a6, 4e84a0 <_lit4_start+0x4a0> + 8e3dbf: c030 movi.n a3, 0 + 8e3dc1: 6d7a28 loopgtz a7, 8e3ded +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1021 + 8e3dc4: 0c0200 memw + 8e3dc7: 2b6283 l32i a11, a6, 0x20c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1033 + 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8e3f5c: 29a6c2 s32i a9, a10, 0x308 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1100 + 8e3f5f: d10f retw.n + +008e3f61 : + 8e3f61: 000000 ... + +008e3f64 : +VendorCommand(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1239 + 8e3f64: 6c1004 entry a1, 32 + 8e3f67: 190133 l32r a9, 4e84cc <_lit4_start+0x4cc> + 8e3f6a: 160015 l32r a6, 4e8054 <_lit4_start+0x54> + 8e3f6d: 120126 l32r a2, 4e8498 <_lit4_start+0x498> + 8e3f70: 130018 l32r a3, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1248 + 8e3f73: 0c0200 memw +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1306 + 8e3f76: 2a2102 l16ui a10, a2, 4 + 8e3f79: c380 movi.n a8, 48 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s32i a13, a5, 0x300 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1283 + 8e400a: 0c0200 memw + 8e400d: 2c5683 s32i a12, a5, 0x20c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1284 + 8e4010: 0c0200 memw + 8e4013: 2e56c0 s32i a14, a5, 0x300 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1285 + 8e4016: 0c0200 memw + 8e4019: 2d4488 s8i a13, a4, 136 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1287 + 8e401c: 283212 l32i a8, a3, 72 + 8e401f: 1a0138 l32r a10, 4e84e0 <_lit4_start+0x4e0> + 8e4022: 0b8000 callx8 a8 + 8e4025: 1d0139 l32r a13, 4e84e4 <_lit4_start+0x4e4> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1289 + 8e4028: 0c0200 memw + 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2924ab s8i a9, a2, 171 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1929 + 8e461e: 285212 l32i a8, a5, 72 + 8e4621: 1a0144 l32r a10, 4e8510 <_lit4_start+0x510> + 8e4624: 0b8000 callx8 a8 + 8e4627: 1900ce l32r a9, 4e8338 <_lit4_start+0x338> + 8e462a: 1a0015 l32r a10, 4e8054 <_lit4_start+0x54> + +008e462d <_usb_fw_task+0xfd>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1933 + 8e462d: 0c0200 memw +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1939 + 8e4630: 28522a l32i a8, a5, 168 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1933 + 8e4633: 29a67f s32i a9, a10, 0x1fc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1939 + 8e4636: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1942 + 8e4639: 285229 l32i a8, a5, 164 + 8e463c: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1947 + 8e463f: 28522c l32i a8, a5, 176 + 8e4642: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1951 + 8e4645: 7c371a bbci a3, 28, 8e4663 <_usb_fw_task+0x133> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1953 + 8e4648: 2a0af7 movi a10, 247 + 8e464b: 0c0200 memw + 8e464e: 2920ab l8ui a9, a2, 171 + 8e4651: 0a9901 and a9, a9, a10 + 8e4654: 0c0200 memw + 8e4657: 2924ab s8i a9, a2, 171 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1954 + 8e465a: 285212 l32i a8, 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000000 ... + +008e48f8 : +mUsbEPMap(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:20 + 8e48f8: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:26 + 8e48fb: c053 movi.n a5, 3 + 8e48fd: 242c2f addi a4, a2, 47 + 8e4900: 054403 xor a4, a4, a5 + 8e4903: 150051 l32r a5, 4e8144 <_lit4_start+0x144> + 8e4906: 040447 extui a4, a4, 0, 8 + 8e4909: 054402 or a4, a4, a5 + 8e490c: 0c0200 memw + 8e490f: 234400 s8i a3, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:33 + 8e4912: d10f retw.n + +008e4914 : +mUsbFIFOMap(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:36 + 8e4914: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:45 + 8e4917: c053 movi.n a5, 3 + 8e4919: 240a80 movi a4, 128 + 8e491c: a424 add.n a4, a2, a4 + 8e491e: 054403 xor a4, a4, a5 + 8e4921: 150051 l32r a5, 4e8144 <_lit4_start+0x144> + 8e4924: 040447 extui a4, a4, 0, 8 + 8e4927: 054402 or a4, a4, a5 + 8e492a: 0c0200 memw + 8e492d: 234400 s8i a3, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:51 + 8e4930: d10f retw.n + +008e4932 : + ... + +008e4934 : +mUsbFIFOConfig(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:54 + 8e4934: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:60 + 8e4937: c053 movi.n a5, 3 + 8e4939: 240a90 movi a4, 144 + 8e493c: a424 add.n a4, a2, a4 + 8e493e: 054403 xor a4, a4, a5 + 8e4941: 150051 l32r a5, 4e8144 <_lit4_start+0x144> + 8e4944: 040447 extui a4, a4, 0, 8 + 8e4947: 054402 or a4, a4, a5 + 8e494a: 0c0200 memw + 8e494d: 234400 s8i a3, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:66 + 8e4950: d10f retw.n + +008e4952 : + ... + +008e4954 : +mUsbEPMxPtSzHigh(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:69 + 8e4954: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:75 + 8e4957: 0f2711 slli a7, a2, 1 + 8e495a: 0b3611 slli a6, a3, 5 + 8e495d: 048514 srli a5, a4, 8 + 8e4960: a766 add.n a6, a6, a7 + 8e4962: c073 movi.n a7, 3 + 8e4964: 266c3f addi a6, a6, 63 + 8e4967: 076603 xor a6, a6, a7 + 8e496a: 170051 l32r a7, 4e8144 <_lit4_start+0x144> + 8e496d: 060647 extui a6, a6, 0, 8 + 8e4970: 076602 or a6, a6, a7 + 8e4973: 0c0200 memw + 8e4976: 256400 s8i a5, a6, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:79 + 8e4979: d10f retw.n + +008e497b : + ... + +008e497c : +mUsbEPMxPtSzLow(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:82 + 8e497c: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:88 + 8e497f: 0f2611 slli a6, a2, 1 + 8e4982: 0b3511 slli a5, a3, 5 + 8e4985: a655 add.n a5, a5, a6 + 8e4987: c063 movi.n a6, 3 + 8e4989: 255c3e addi a5, a5, 62 + 8e498c: 065503 xor a5, a5, a6 + 8e498f: 160051 l32r a6, 4e8144 <_lit4_start+0x144> + 8e4992: 050547 extui a5, a5, 0, 8 + 8e4995: 065502 or a5, a5, a6 + 8e4998: 0c0200 memw + 8e499b: 245400 s8i a4, a5, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:91 + 8e499e: d10f retw.n + +008e49a0 : +mUsbEPinHighBandSet(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:94 + 8e49a0: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:106 + 8e49a3: 2a0a9f movi a10, 159 + 8e49a6: c073 movi.n a7, 3 + 8e49a8: 0f2611 slli a6, a2, 1 + 8e49ab: 266c3f addi a6, a6, 63 + 8e49ae: 076603 xor a6, a6, a7 + 8e49b1: 170051 l32r a7, 4e8144 <_lit4_start+0x144> + 8e49b4: 060647 extui a6, a6, 0, 8 + 8e49b7: 076602 or a6, a6, a7 + 8e49ba: 0c0200 memw + 8e49bd: 296000 l8ui a9, a6, 0 + 8e49c0: 0a9901 and a9, a9, a10 + 8e49c3: 0c0200 memw + 8e49c6: 296400 s8i a9, a6, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:107 + 8e49c9: c081 movi.n a8, 1 + 8e49cb: 04b714 srli a7, a4, 11 + 8e49ce: b177 addi.n a7, a7, 1 + 8e49d0: 03880c sub a8, a8, a3 + 8e49d3: 0b7711 slli a7, a7, 5 + 8e49d6: 08771d mul16s a7, a7, a8 + 8e49d9: 0c0200 memw + 8e49dc: 256000 l8ui a5, a6, 0 + 8e49df: 075502 or a5, a5, a7 + 8e49e2: 0c0200 memw + 8e49e5: 256400 s8i a5, a6, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:111 + 8e49e8: d10f retw.n + +008e49ea : + ... + +008e49ec : +vUsbFIFO_EPxCfg_HS(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:143 + 8e49ec: 6c1004 entry a1, 32 + 8e49ef: 180165 l32r a8, 4e8594 <_lit4_start+0x594> + 8e49f2: 190166 l32r a9, 4e8598 <_lit4_start+0x598> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:302 + 8e49f5: 288100 l16ui a8, a8, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:297 + 8e49f8: 299100 l16ui a9, a9, 0 + 8e49fb: b088 addi.n a8, a8, -1 + 8e49fd: 658179 bnez a8, 8e4b7a + 8e4a00: 659176 bnez a9, 8e4b7a + 8e4a03: 1a0167 l32r a10, 4e859c <_lit4_start+0x59c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:292 + 8e4a06: 2aa100 l16ui a10, a10, 0 + 8e4a09: 65a16d bnez a10, 8e4b7a +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:164 + 8e4a0c: c0a1 movi.n a10, 1 + 8e4a0e: c0bf movi.n a11, 15 + 8e4a10: 5bffb9 call8 8e48f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:165 + 8e4a13: c0a0 movi.n a10, 0 + 8e4a15: c0b1 movi.n a11, 1 + 8e4a17: 5bffbf call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:167 + 8e4a1a: c0a1 movi.n a10, 1 + 8e4a1c: c0b1 movi.n a11, 1 + 8e4a1e: 5bffbd call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:169 + 8e4a21: c0a0 movi.n a10, 0 + 8e4a23: 2b0a86 movi a11, 134 + 8e4a26: 5bffc3 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:175 + 8e4a29: c0a1 movi.n a10, 1 + 8e4a2b: c0b6 movi.n a11, 6 + 8e4a2d: 5bffc1 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:178 + 8e4a30: c0a1 movi.n a10, 1 + 8e4a32: c0b1 movi.n a11, 1 + 8e4a34: 2c2a00 movi a12, 0x200 + 8e4a37: 5bffc7 call8 8e4954 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:179 + 8e4a3a: c0a1 movi.n a10, 1 + 8e4a3c: c0b1 movi.n a11, 1 + 8e4a3e: 2c2a00 movi a12, 0x200 + 8e4a41: 5bffce call8 8e497c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:180 + 8e4a44: c0a1 movi.n a10, 1 + 8e4a46: c0b1 movi.n a11, 1 + 8e4a48: 2c2a00 movi a12, 0x200 + 8e4a4b: 5bffd5 call8 8e49a0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:185 + 8e4a4e: c0a2 movi.n a10, 2 + 8e4a50: 2b0af2 movi a11, 242 + 8e4a53: 5bffa9 call8 8e48f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:186 + 8e4a56: c0a2 movi.n a10, 2 + 8e4a58: c1b2 movi.n a11, 18 + 8e4a5a: 5bffae call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:188 + 8e4a5d: c0a3 movi.n a10, 3 + 8e4a5f: c1b2 movi.n a11, 18 + 8e4a61: 5bffac call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:190 + 8e4a64: c0a2 movi.n a10, 2 + 8e4a66: 2b0a86 movi a11, 134 + 8e4a69: 5bffb2 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:196 + 8e4a6c: c0a3 movi.n a10, 3 + 8e4a6e: c0b6 movi.n a11, 6 + 8e4a70: 5bffb0 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:199 + 8e4a73: c0a2 movi.n a10, 2 + 8e4a75: c0b0 movi.n a11, 0 + 8e4a77: 2c2a00 movi a12, 0x200 + 8e4a7a: 5bffb6 call8 8e4954 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:200 + 8e4a7d: c0a2 movi.n a10, 2 + 8e4a7f: c0b0 movi.n a11, 0 + 8e4a81: 2c2a00 movi a12, 0x200 + 8e4a84: 5bffbd call8 8e497c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:201 + 8e4a87: c0a2 movi.n a10, 2 + 8e4a89: c0b0 movi.n a11, 0 + 8e4a8b: 2c2a00 movi a12, 0x200 + 8e4a8e: 5bffc4 call8 8e49a0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:206 + 8e4a91: c0a3 movi.n a10, 3 + 8e4a93: 2b0afe movi a11, 254 + 8e4a96: 5bff98 call8 8e48f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:207 + 8e4a99: c0ae movi.n a10, 14 + 8e4a9b: c1b3 movi.n a11, 19 + 8e4a9d: 5bff9d call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:208 + 8e4aa0: c0ae movi.n a10, 14 + 8e4aa2: 2b0a83 movi a11, 131 + 8e4aa5: 5bffa3 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:217 + 8e4aa8: c0a3 movi.n a10, 3 + 8e4aaa: c0b0 movi.n a11, 0 + 8e4aac: c4c0 movi.n a12, 64 + 8e4aae: 5bffa9 call8 8e4954 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:218 + 8e4ab1: c0a3 movi.n a10, 3 + 8e4ab3: c0b0 movi.n a11, 0 + 8e4ab5: c4c0 movi.n a12, 64 + 8e4ab7: 5bffb1 call8 8e497c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:219 + 8e4aba: c0a3 movi.n a10, 3 + 8e4abc: c0b0 movi.n a11, 0 + 8e4abe: c4c0 movi.n a12, 64 + 8e4ac0: 5bffb7 call8 8e49a0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:224 + 8e4ac3: c0a4 movi.n a10, 4 + 8e4ac5: 2b0aff movi a11, 255 + 8e4ac8: 5bff8b call8 8e48f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:225 + 8e4acb: c0af movi.n a10, 15 + 8e4acd: c0b4 movi.n a11, 4 + 8e4acf: 5bff91 call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:226 + 8e4ad2: c0af movi.n a10, 15 + 8e4ad4: 2b0a83 movi a11, 131 + 8e4ad7: 5bff97 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:235 + 8e4ada: c0a4 movi.n a10, 4 + 8e4adc: c0b1 movi.n a11, 1 + 8e4ade: c4c0 movi.n a12, 64 + 8e4ae0: 5bff9c call8 8e4954 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:236 + 8e4ae3: c0a4 movi.n a10, 4 + 8e4ae5: c0b1 movi.n a11, 1 + 8e4ae7: c4c0 movi.n a12, 64 + 8e4ae9: 5bffa4 call8 8e497c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:237 + 8e4aec: c0a4 movi.n a10, 4 + 8e4aee: c0b1 movi.n a11, 1 + 8e4af0: c4c0 movi.n a12, 64 + 8e4af2: 5bffab call8 8e49a0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:244 + 8e4af5: c0a5 movi.n a10, 5 + 8e4af7: c4bf movi.n a11, 79 + 8e4af9: 5bff7f call8 8e48f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:245 + 8e4afc: c0a4 movi.n a10, 4 + 8e4afe: c0b5 movi.n a11, 5 + 8e4b00: 5bff84 call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:247 + 8e4b03: c0a5 movi.n a10, 5 + 8e4b05: c0b5 movi.n a11, 5 + 8e4b07: 5bff83 call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:249 + 8e4b0a: c0a4 movi.n a10, 4 + 8e4b0c: 2b0a86 movi a11, 134 + 8e4b0f: 5bff89 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:255 + 8e4b12: c0a5 movi.n a10, 5 + 8e4b14: c0b6 movi.n a11, 6 + 8e4b16: 5bff87 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:258 + 8e4b19: c0a5 movi.n a10, 5 + 8e4b1b: c0b1 movi.n a11, 1 + 8e4b1d: 2c2a00 movi a12, 0x200 + 8e4b20: 5bff8c call8 8e4954 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:259 + 8e4b23: c0a5 movi.n a10, 5 + 8e4b25: c0b1 movi.n a11, 1 + 8e4b27: 2c2a00 movi a12, 0x200 + 8e4b2a: 5bff94 call8 8e497c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:260 + 8e4b2d: c0a5 movi.n a10, 5 + 8e4b2f: c0b1 movi.n a11, 1 + 8e4b31: 2c2a00 movi a12, 0x200 + 8e4b34: 5bff9a call8 8e49a0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:268 + 8e4b37: c0a6 movi.n a10, 6 + 8e4b39: 2b0a6f movi a11, 111 + 8e4b3c: 5bff6e call8 8e48f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:269 + 8e4b3f: c0a6 movi.n a10, 6 + 8e4b41: c0b6 movi.n a11, 6 + 8e4b43: 5bff74 call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:271 + 8e4b46: c0a7 movi.n a10, 7 + 8e4b48: c0b6 movi.n a11, 6 + 8e4b4a: 5bff72 call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:273 + 8e4b4d: c0a6 movi.n a10, 6 + 8e4b4f: 2b0a86 movi a11, 134 + 8e4b52: 5bff78 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:279 + 8e4b55: c0a7 movi.n a10, 7 + 8e4b57: c0b6 movi.n a11, 6 + 8e4b59: 5bff76 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:282 + 8e4b5c: c0a6 movi.n a10, 6 + 8e4b5e: c0b1 movi.n a11, 1 + 8e4b60: 2c2a00 movi a12, 0x200 + 8e4b63: 5bff7c call8 8e4954 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:283 + 8e4b66: c0a6 movi.n a10, 6 + 8e4b68: c0b1 movi.n a11, 1 + 8e4b6a: 2c2a00 movi a12, 0x200 + 8e4b6d: 5bff83 call8 8e497c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:284 + 8e4b70: c0a6 movi.n a10, 6 + 8e4b72: c0b1 movi.n a11, 1 + 8e4b74: 2c2a00 movi a12, 0x200 + 8e4b77: 5bff8a call8 8e49a0 + +008e4b7a : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:305 + 8e4b7a: d10f retw.n + +008e4b7c : +vUsbFIFO_EPxCfg_FS(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:308 + 8e4b7c: 6c1004 entry a1, 32 + 8e4b7f: 180165 l32r a8, 4e8594 <_lit4_start+0x594> + 8e4b82: 190166 l32r a9, 4e8598 <_lit4_start+0x598> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:431 + 8e4b85: 288100 l16ui a8, a8, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:426 + 8e4b88: 299100 l16ui a9, a9, 0 + 8e4b8b: b088 addi.n a8, a8, -1 + 8e4b8d: 658118 bnez a8, 8e4ca9 + 8e4b90: 659115 bnez a9, 8e4ca9 + 8e4b93: 1a0167 l32r a10, 4e859c <_lit4_start+0x59c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:421 + 8e4b96: 2aa100 l16ui a10, a10, 0 + 8e4b99: 65a10c bnez a10, 8e4ca9 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:329 + 8e4b9c: c0a1 movi.n a10, 1 + 8e4b9e: c0bf movi.n a11, 15 + 8e4ba0: 5bff55 call8 8e48f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:330 + 8e4ba3: c0a0 movi.n a10, 0 + 8e4ba5: c0b1 movi.n a11, 1 + 8e4ba7: 5bff5b call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:331 + 8e4baa: c0a0 movi.n a10, 0 + 8e4bac: 2b0a86 movi a11, 134 + 8e4baf: 5bff61 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:337 + 8e4bb2: c0a1 movi.n a10, 1 + 8e4bb4: c0b6 movi.n a11, 6 + 8e4bb6: 5bff5f call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:340 + 8e4bb9: c0a1 movi.n a10, 1 + 8e4bbb: c0b1 movi.n a11, 1 + 8e4bbd: c4c0 movi.n a12, 64 + 8e4bbf: 5bff65 call8 8e4954 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:341 + 8e4bc2: c0a1 movi.n a10, 1 + 8e4bc4: c0b1 movi.n a11, 1 + 8e4bc6: c4c0 movi.n a12, 64 + 8e4bc8: 5bff6c call8 8e497c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:343 + 8e4bcb: c0a1 movi.n a10, 1 + 8e4bcd: c0b1 movi.n a11, 1 + 8e4bcf: c4c0 movi.n a12, 64 + 8e4bd1: 5bff73 call8 8e49a0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:348 + 8e4bd4: c0a2 movi.n a10, 2 + 8e4bd6: 2b0af2 movi a11, 242 + 8e4bd9: 5bff47 call8 8e48f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:349 + 8e4bdc: c0a2 movi.n a10, 2 + 8e4bde: c1b2 movi.n a11, 18 + 8e4be0: 5bff4c call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:350 + 8e4be3: c0a2 movi.n a10, 2 + 8e4be5: 2b0a86 movi a11, 134 + 8e4be8: 5bff52 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:356 + 8e4beb: c0a3 movi.n a10, 3 + 8e4bed: c0b6 movi.n a11, 6 + 8e4bef: 5bff51 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:359 + 8e4bf2: c0a2 movi.n a10, 2 + 8e4bf4: c0b0 movi.n a11, 0 + 8e4bf6: c4c0 movi.n a12, 64 + 8e4bf8: 5bff56 call8 8e4954 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:360 + 8e4bfb: c0a2 movi.n a10, 2 + 8e4bfd: c0b0 movi.n a11, 0 + 8e4bff: c4c0 movi.n a12, 64 + 8e4c01: 5bff5e call8 8e497c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:361 + 8e4c04: c0a2 movi.n a10, 2 + 8e4c06: c0b0 movi.n a11, 0 + 8e4c08: c4c0 movi.n a12, 64 + 8e4c0a: 5bff65 call8 8e49a0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:366 + 8e4c0d: c0a3 movi.n a10, 3 + 8e4c0f: 2b0afe movi a11, 254 + 8e4c12: 5bff39 call8 8e48f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:367 + 8e4c15: c0ae movi.n a10, 14 + 8e4c17: c1b3 movi.n a11, 19 + 8e4c19: 5bff3e call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:368 + 8e4c1c: c0ae movi.n a10, 14 + 8e4c1e: 2b0a83 movi a11, 131 + 8e4c21: 5bff44 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:377 + 8e4c24: c0a3 movi.n a10, 3 + 8e4c26: c0b0 movi.n a11, 0 + 8e4c28: c4c0 movi.n a12, 64 + 8e4c2a: 5bff4a call8 8e4954 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:378 + 8e4c2d: c0a3 movi.n a10, 3 + 8e4c2f: c0b0 movi.n a11, 0 + 8e4c31: c4c0 movi.n a12, 64 + 8e4c33: 5bff52 call8 8e497c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:379 + 8e4c36: c0a3 movi.n a10, 3 + 8e4c38: c0b0 movi.n a11, 0 + 8e4c3a: c4c0 movi.n a12, 64 + 8e4c3c: 5bff58 call8 8e49a0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:384 + 8e4c3f: c0a4 movi.n a10, 4 + 8e4c41: 2b0aff movi a11, 255 + 8e4c44: 5bff2c call8 8e48f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:385 + 8e4c47: c0af movi.n a10, 15 + 8e4c49: c0b4 movi.n a11, 4 + 8e4c4b: 5bff32 call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:386 + 8e4c4e: c0af movi.n a10, 15 + 8e4c50: 2b0a82 movi a11, 130 + 8e4c53: 5bff38 call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:395 + 8e4c56: c0a4 movi.n a10, 4 + 8e4c58: c0b1 movi.n a11, 1 + 8e4c5a: c4c0 movi.n a12, 64 + 8e4c5c: 5bff3d call8 8e4954 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:396 + 8e4c5f: c0a4 movi.n a10, 4 + 8e4c61: c0b1 movi.n a11, 1 + 8e4c63: c4c0 movi.n a12, 64 + 8e4c65: 5bff45 call8 8e497c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:397 + 8e4c68: c0a4 movi.n a10, 4 + 8e4c6a: c0b1 movi.n a11, 1 + 8e4c6c: c4c0 movi.n a12, 64 + 8e4c6e: 5bff4c call8 8e49a0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:402 + 8e4c71: c0a5 movi.n a10, 5 + 8e4c73: c4bf movi.n a11, 79 + 8e4c75: 5bff20 call8 8e48f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:403 + 8e4c78: c0a4 movi.n a10, 4 + 8e4c7a: c0b5 movi.n a11, 5 + 8e4c7c: 5bff25 call8 8e4914 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:404 + 8e4c7f: c0a4 movi.n a10, 4 + 8e4c81: 2b0a86 movi a11, 134 + 8e4c84: 5bff2b call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:410 + 8e4c87: c0a5 movi.n a10, 5 + 8e4c89: c0b6 movi.n a11, 6 + 8e4c8b: 5bff2a call8 8e4934 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:413 + 8e4c8e: c0a5 movi.n a10, 5 + 8e4c90: c0b1 movi.n a11, 1 + 8e4c92: c4c0 movi.n a12, 64 + 8e4c94: 5bff2f call8 8e4954 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:414 + 8e4c97: c0a5 movi.n a10, 5 + 8e4c99: c0b1 movi.n a11, 1 + 8e4c9b: c4c0 movi.n a12, 64 + 8e4c9d: 5bff37 call8 8e497c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:415 + 8e4ca0: c0a5 movi.n a10, 5 + 8e4ca2: c0b1 movi.n a11, 1 + 8e4ca4: c4c0 movi.n a12, 64 + 8e4ca6: 5bff3e call8 8e49a0 + +008e4ca9 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:433 + 8e4ca9: d10f retw.n + +008e4cab : + ... + +008e4cac <__dma_reg_read>: +__dma_reg_read(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:166 + 8e4cac: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:167 + 8e4caf: 0c0200 memw + 8e4cb2: 8220 l32i.n a2, a2, 0 + 8e4cb4: d10f retw.n + +008e4cb6 <__dma_reg_read+0xa>: + ... + +008e4cb8 <__dma_reg_write>: +__dma_reg_write(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:177 + 8e4cb8: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:178 + 8e4cbb: 0c0200 memw + 8e4cbe: 9320 s32i.n a3, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:179 + 8e4cc0: d10f retw.n + +008e4cc2 <__dma_reg_write+0xa>: + ... + +008e4cc4 <__dma_set_base>: +__dma_set_base(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:188 + 8e4cc4: 6c1004 entry a1, 32 + 8e4cc7: 160168 l32r a6, 4e85a0 <_lit4_start+0x5a0> + 8e4cca: c839 beqz.n a3, 8e4cd7 <__dma_set_base+0x13> + 8e4ccc: 150169 l32r a5, 4e85a4 <_lit4_start+0x5a4> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:201 + 8e4ccf: 683107 beqi a3, 1, 8e4cda <__dma_set_base+0x16> + 8e4cd2: 683204 beqi a3, 2, 8e4cda <__dma_set_base+0x16> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:202 + 8e4cd5: d10f retw.n + +008e4cd7 <__dma_set_base+0x13>: + 8e4cd7: 15016a l32r a5, 4e85a8 <_lit4_start+0x5a8> + +008e4cda <__dma_set_base+0x16>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:197 + 8e4cda: 022409 addx2 a4, a2, a2 + 8e4cdd: 06440b addx8 a4, a4, a6 + 8e4ce0: 9540 s32i.n a5, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:202 + 8e4ce2: d10f retw.n + +008e4ce4 <__dma_lib_tx_init>: +__dma_lib_tx_init(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:213 + 8e4ce4: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:217 + 8e4ce7: 282cfc addi a8, a2, -4 + 8e4cea: 6e8203 bltui a8, 2, 8e4cf1 <__dma_lib_tx_init+0xd> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:218 + 8e4ced: c021 movi.n a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:232 + 8e4cef: d10f retw.n + +008e4cf1 <__dma_lib_tx_init+0xd>: + 8e4cf1: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e4cf4: 190168 l32r a9, 4e85a0 <_lit4_start+0x5a0> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:220 + 8e4cf7: 022409 addx2 a4, a2, a2 + 8e4cfa: 2882af l32i a8, a8, 0x2bc + 8e4cfd: 09440b addx8 a4, a4, a9 + 8e4d00: b84a addi.n a10, a4, 8 + 8e4d02: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:222 + 8e4d05: db30 mov.n a11, a3 + 8e4d07: da20 mov.n a10, a2 + 8e4d09: 5bffee call8 8e4cc4 <__dma_set_base> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:224 + 8e4d0c: 8841 l32i.n a8, a4, 4 + 8e4d0e: 8240 l32i.n a2, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:228 + 8e4d10: 8b42 l32i.n a11, a4, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:224 + 8e4d12: a822 add.n a2, a2, a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:228 + 8e4d14: da20 mov.n a10, a2 + 8e4d16: 5bffe8 call8 8e4cb8 <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:229 + 8e4d19: bc2a addi.n a10, a2, 12 + 8e4d1b: c0b2 movi.n a11, 2 + 8e4d1d: 5bffe6 call8 8e4cb8 <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:230 + 8e4d20: 2a2c18 addi a10, a2, 24 + 8e4d23: c0b1 movi.n a11, 1 + 8e4d25: 5bffe4 call8 8e4cb8 <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:232 + 8e4d28: c020 movi.n a2, 0 + 8e4d2a: d10f retw.n + +008e4d2c <__dma_lib_rx_config>: +__dma_lib_rx_config(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:238 + 8e4d2c: 6c1004 entry a1, 32 + 8e4d2f: dc40 mov.n a12, a4 + 8e4d31: db30 mov.n a11, a3 + 8e4d33: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e4d36: 1a0168 l32r a10, 4e85a0 <_lit4_start+0x5a0> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:246 + 8e4d39: 022909 addx2 a9, a2, a2 + 8e4d3c: 2882b0 l32i a8, a8, 0x2c0 + 8e4d3f: 0a920b addx8 a2, a9, a10 + 8e4d42: b82a addi.n a10, a2, 8 + 8e4d44: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:251 + 8e4d47: c0c2 movi.n a12, 2 + 8e4d49: c031 movi.n a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:249 + 8e4d4b: 8f21 l32i.n a15, a2, 4 + 8e4d4d: 8d20 l32i.n a13, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:257 + 8e4d4f: 8b22 l32i.n a11, a2, 8 + 8e4d51: 1e016a l32r a14, 4e85a8 <_lit4_start+0x5a8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:249 + 8e4d54: afd2 add.n a2, a13, a15 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:257 + 8e4d56: da20 mov.n a10, a2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:251 + 8e4d58: 0edd0c sub a13, a13, a14 + 8e4d5b: 0dc338 moveqz a3, a12, a13 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:257 + 8e4d5e: 5bffd6 call8 8e4cb8 <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:258 + 8e4d61: db30 mov.n a11, a3 + 8e4d63: b82a addi.n a10, a2, 8 + 8e4d65: 5bffd4 call8 8e4cb8 <__dma_reg_write> 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8e4d7f: 6e2403 bltui a2, 4, 8e4d86 <__dma_lib_rx_init+0xa> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:274 + 8e4d82: c021 movi.n a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:284 + 8e4d84: d10f retw.n + +008e4d86 <__dma_lib_rx_init+0xa>: + 8e4d86: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e4d89: 1b0168 l32r a11, 4e85a0 <_lit4_start+0x5a0> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:280 + 8e4d8c: 022a09 addx2 a10, a2, a2 + 8e4d8f: 2882ae l32i a8, a8, 0x2b8 + 8e4d92: 0baa0b addx8 a10, a10, a11 + 8e4d95: b8aa addi.n a10, a10, 8 + 8e4d97: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:282 + 8e4d9a: db30 mov.n a11, a3 + 8e4d9c: da20 mov.n a10, a2 + 8e4d9e: 5bffc9 call8 8e4cc4 <__dma_set_base> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:284 + 8e4da1: c020 movi.n a2, 0 + 8e4da3: d10f retw.n + +008e4da5 <__dma_lib_rx_init+0x29>: + 8e4da5: 000000 ... + +008e4da8 <__dma_hard_xmit>: +__dma_hard_xmit(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:295 + 8e4da8: 6c1004 entry a1, 32 + 8e4dab: db30 mov.n a11, a3 + 8e4dad: 1c0168 l32r a12, 4e85a0 <_lit4_start+0x5a0> + 8e4db0: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:298 + 8e4db3: 022a09 addx2 a10, a2, a2 + 8e4db6: 0caa0b addx8 a10, a10, a12 + 8e4db9: 8ca1 l32i.n a12, a10, 4 + 8e4dbb: 89a0 l32i.n a9, a10, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:300 + 8e4dbd: 2882b1 l32i a8, a8, 0x2c4 + 8e4dc0: b8aa addi.n a10, a10, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:298 + 8e4dc2: ac92 add.n a2, a9, a12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:300 + 8e4dc4: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:304 + 8e4dc7: b42a addi.n a10, a2, 4 + 8e4dc9: c0b1 movi.n a11, 1 + 8e4dcb: 5bffbb call8 8e4cb8 <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:305 + 8e4dce: d10f retw.n + +008e4dd0 <__dma_reap_xmitted>: +__dma_reap_xmitted(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:315 + 8e4dd0: 6c1004 entry a1, 32 + 8e4dd3: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e4dd6: 1b0168 l32r a11, 4e85a0 <_lit4_start+0x5a0> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:316 + 8e4dd9: 022a09 addx2 a10, a2, a2 + 8e4ddc: 2882b5 l32i a8, a8, 0x2d4 + 8e4ddf: 0baa0b addx8 a10, a10, a11 + 8e4de2: b8aa addi.n a10, a10, 8 + 8e4de4: 0b8000 callx8 a8 + 8e4de7: d2a0 mov.n a2, a10 + 8e4de9: d10f retw.n + +008e4deb <__dma_reap_xmitted+0x1b>: + ... + +008e4dec <__dma_flush_xmit>: +__dma_flush_xmit(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:326 + 8e4dec: 6c1004 entry a1, 32 + 8e4def: 140168 l32r a4, 4e85a0 <_lit4_start+0x5a0> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:339 + 8e4df2: c0b0 movi.n a11, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:330 + 8e4df4: 022309 addx2 a3, a2, a2 + 8e4df7: 04330b addx8 a3, a3, a4 + 8e4dfa: 8831 l32i.n a8, a3, 4 + 8e4dfc: 8430 l32i.n a4, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:332 + 8e4dfe: 8232 l32i.n a2, a3, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:333 + 8e4e00: 8333 l32i.n a3, a3, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:330 + 8e4e02: a844 add.n a4, a4, a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:339 + 8e4e04: b44a addi.n a10, a4, 4 + 8e4e06: 5bffac call8 8e4cb8 <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:340 + 8e4e09: da40 mov.n a10, a4 + 8e4e0b: db30 mov.n a11, a3 + 8e4e0d: 5bffaa call8 8e4cb8 <__dma_reg_write> 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8e5211: 5800bc call8 8e5504 + 8e5214: d4a0 mov.n a4, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:206 + 8e5216: c0b8 movi.n a11, 8 + 8e5218: 5bff98 call8 8e507c + 8e521b: 150018 l32r a5, 4e8060 <_lit4_start+0x60> + 8e521e: d3a0 mov.n a3, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:208 + 8e5220: 8854 l32i.n a8, a5, 16 + 8e5222: c0b0 movi.n a11, 0 + 8e5224: c0c8 movi.n a12, 8 + 8e5226: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:217 + 8e5229: dc40 mov.n a12, a4 + 8e522b: da20 mov.n a10, a2 + 8e522d: c0b0 movi.n a11, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:213 + 8e522f: c1e6 movi.n a14, 22 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:209 + 8e5231: c081 movi.n a8, 1 + 8e5233: c0f0 movi.n a15, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:210 + 8e5235: 2922a7 l32i a9, a2, 0x29c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:212 + 8e5238: 2d22aa l32i a13, a2, 0x2a8 + 8e523b: 2d3403 s8i a13, a3, 3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:210 + 8e523e: 293405 s8i a9, a3, 5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:209 + 8e5241: 2f3400 s8i a15, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:210 + 8e5244: 098914 srli a9, a9, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:212 + 8e5247: 0d8d14 srli a13, a13, 8 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retw.n + +008e525e <_HTC_Ready+0x52>: + ... + +008e5260 : +ReturnBuffers(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:222 + 8e5260: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:229 + 8e5263: da40 mov.n a10, a4 + 8e5265: c0b8 movi.n a11, 8 + 8e5267: 5bff7a call8 8e5050 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:233 + 8e526a: 2a22b0 l32i a10, a2, 0x2c0 + 8e526d: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e5270: dc40 mov.n a12, a4 + 8e5272: 03360f subx8 a6, a3, a3 + 8e5275: 288277 l32i a8, a8, 0x1dc + 8e5278: 02660a addx4 a6, a6, a2 + 8e527b: 2b6019 l8ui a11, a6, 25 + 8e527e: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:236 + 8e5281: 2922a8 l32i a9, a2, 0x2a0 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addi.n a8, a8, 1 + 8e556c: 9844 s32i.n a8, a4, 16 + +008e556e : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:567 + 8e556e: 2fa401 s8i a15, a10, 1 + 8e5571: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:573 + 8e5574: dc30 mov.n a12, a3 + 8e5576: 288284 l32i a8, a8, 0x210 + 8e5579: da20 mov.n a10, a2 + 8e557b: c0b0 movi.n a11, 0 + +008e557d : + 8e557d: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:576 + 8e5580: d10f retw.n + +008e5582 : + ... + +008e5584 : +HTCProcessConnectMsg(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:580 + 8e5584: 6c1006 entry a1, 48 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:589 + 8e5587: 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:84 + 8e5990: 743002 bnone a3, a4, 8e5996 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:85 + 8e5993: 266c01 addi a6, a6, 1 + +008e5996 : + 8e5996: 15018a l32r a5, 4e8628 <_lit4_start+0x628> + 8e5999: 6d6a20 loopgtz a6, 8e59bd +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:89 + 8e599c: 8820 l32i.n a8, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:91 + 8e599e: 058a01 and a10, a8, a5 + 8e59a1: 088910 slli a9, a8, 24 + 8e59a4: 08aa11 slli a10, a10, 8 + 8e59a7: 0a9902 or a9, a9, a10 + 8e59aa: 088a57 extui a10, a8, 24, 8 + 8e59ad: 088814 srli a8, a8, 8 + 8e59b0: 058801 and a8, a8, a5 + 8e59b3: 0a8802 or a8, a8, a10 + 8e59b6: 098802 or a8, a8, a9 + 8e59b9: 9820 s32i.n a8, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:92 + 8e59bb: b422 addi.n a2, a2, 4 + +008e59bd : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:93 + 8e59bd: d10f retw.n + +008e59bf : + ... + +008e59c0 <_DMAengine_return_recv_buf>: +_DMAengine_return_recv_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:98 + 8e59c0: 6c1004 entry a1, 32 + 8e59c3: da20 mov.n a10, a2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:102 + 8e59c5: 8b30 l32i.n a11, a3, 0 + 8e59c7: 580004 call8 8e59d8 + 8e59ca: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:103 + 8e59cd: 2882a3 l32i a8, a8, 0x28c + 8e59d0: da30 mov.n a10, a3 + 8e59d2: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:104 + 8e59d5: d10f retw.n + +008e59d7 <_DMAengine_return_recv_buf+0x17>: + ... + +008e59d8 : +config_queue(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:107 + 8e59d8: 6c1004 entry a1, 32 + 8e59db: 150018 l32r a5, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:114 + 8e59de: 64305b beqz a3, 8e5a3d + 8e59e1: c060 movi.n a6, 0 + 8e59e3: c040 movi.n a4, 0 + +008e59e5 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:115 + 8e59e5: 2852a7 l32i a8, a5, 0x29c + 8e59e8: da30 mov.n a10, a3 + 8e59ea: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:40 + 8e59ed: 0c0200 memw + 8e59f0: 26a501 s16i a6, a10, 2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:41 + 8e59f3: 0c0200 memw + 8e59f6: 26a500 s16i a6, a10, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:42 + 8e59f9: 0c0200 memw + 8e59fc: 26a503 s16i a6, a10, 6 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:43 + 8e59ff: 0c0200 memw + 8e5a02: 26a502 s16i a6, a10, 4 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:120 + 8e5a1e: 293104 l16ui a9, a3, 8 + 8e5a21: 0c0200 memw + 8e5a24: 29a503 s16i a9, a10, 6 + 8e5a27: cc43 bnez.n a4, 8e5a2e +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:123 + 8e5a29: d7a0 mov.n a7, a10 + 8e5a2b: 600004 j 8e5a33 + +008e5a2e : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:126 + 8e5a2e: 0c0200 memw + 8e5a31: 9a44 s32i.n a10, a4, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:130 + 8e5a33: 8330 l32i.n a3, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:126 + 8e5a35: d4a0 mov.n a4, a10 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:134 + 8e5a4b: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:136 + 8e5a4e: d10f retw.n + +008e5a50 <_DMAengine_config_rx_queue>: +_DMAengine_config_rx_queue(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:143 + 8e5a50: 6c1006 entry a1, 48 + 8e5a53: da20 mov.n a10, a2 + 8e5a55: 9311 s32i.n a3, a1, 4 + 8e5a57: d230 mov.n a2, a3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:148 + 8e5a59: 6a3141 blti a3, 1, 8e5a9e <_DMAengine_config_rx_queue+0x4e> + 8e5a5c: c050 movi.n a5, 0 + 8e5a5e: 130018 l32r a3, 4e8060 <_lit4_start+0x60> + 8e5a61: c070 movi.n a7, 0 + 8e5a63: 9a10 s32i.n a10, a1, 0 + +008e5a65 <_DMAengine_config_rx_queue+0x15>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:150 + 8e5a65: 2832a6 l32i a8, a3, 0x298 + 8e5a68: 0b8000 callx8 a8 + 8e5a6b: d6a0 mov.n a6, a10 + 8e5a6d: cca1 bnez.n a10, 8e5a72 <_DMAengine_config_rx_queue+0x22> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:152 + 8e5a6f: 63fffc j 8e5a6f <_DMAengine_config_rx_queue+0x1f> + +008e5a72 <_DMAengine_config_rx_queue+0x22>: +/root/Workspace/0412_v202/tgt/target/adf/os/inc/adf_os_mem_pvt.h:10 + 8e5a72: 283252 l32i a8, a3, 0x148 + 8e5a75: c0a0 movi.n a10, 0 + 8e5a77: db40 mov.n a11, a4 + 8e5a79: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:154 + 8e5a7c: 9a61 s32i.n a10, a6, 4 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+008e5aa7 <_DMAengine_config_rx_queue+0x57>: + ... + +008e5aa8 <_DMAengine_xmit_buf>: +_DMAengine_xmit_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:176 + 8e5aa8: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:185 + 8e5aab: 8930 l32i.n a9, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:176 + 8e5aad: da20 mov.n a10, a2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:186 + 8e5aaf: c0c0 movi.n a12, 0 + 8e5ab1: 64907a beqz a9, 8e5b2f <_DMAengine_xmit_buf+0x87> + 8e5ab4: c0f0 movi.n a15, 0 + +008e5ab6 <_DMAengine_xmit_buf+0xe>: + 8e5ab6: 222a00 movi a2, 0x200 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:44 + 8e5ad4: 0c0200 memw + 8e5ad7: 9f96 s32i.n a15, a9, 24 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:45 + 8e5ad9: 0c0200 memw + 8e5adc: 9f97 s32i.n a15, a9, 28 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:46 + 8e5ade: 0c0200 memw + 8e5ae1: 9f98 s32i.n a15, a9, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:191 + 8e5ae3: 289106 l16ui a8, a9, 12 + 8e5ae6: 0c0200 memw +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:192 + 8e5ae9: 8e91 l32i.n a14, a9, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:191 + 8e5aeb: 28950b s16i a8, a9, 22 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:192 + 8e5aee: 289105 l16ui a8, a9, 10 + 8e5af1: ae88 add.n a8, a8, a14 + 8e5af3: 0c0200 memw + 8e5af6: 9897 s32i.n a8, a9, 28 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:193 + 8e5af8: 0c0200 memw + 8e5afb: 2f9508 s16i a15, a9, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:194 + 8e5afe: 0c0200 memw + 8e5b01: 2f9509 s16i a15, a9, 18 + 8e5b04: cdcb bnez.n a12, 8e5b23 <_DMAengine_xmit_buf+0x7b> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:201 + 8e5b06: dbd0 mov.n a11, a13 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:203 + 8e5b08: 0c0200 memw + 8e5b0b: 2e9108 l16ui a14, a9, 16 + 8e5b0e: 02ee02 or a14, a14, a2 + 8e5b11: 0c0200 memw + 8e5b14: 2e9508 s16i a14, a9, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:206 + 8e5b17: 2c3104 l16ui a12, a3, 8 + 8e5b1a: 0c0200 memw + 8e5b1d: 2c950a s16i a12, a9, 20 + 8e5b20: 600004 j 8e5b28 <_DMAengine_xmit_buf+0x80> + +008e5b23 <_DMAengine_xmit_buf+0x7b>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:210 + 8e5b23: 0c0200 memw + 8e5b26: 9dc4 s32i.n a13, a12, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:214 + 8e5b28: 8990 l32i.n a9, a9, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:210 + 8e5b2a: dcd0 mov.n a12, a13 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:186 + 8e5b2c: 659f89 bnez a9, 8e5ab9 <_DMAengine_xmit_buf+0x11> + +008e5b2f <_DMAengine_xmit_buf+0x87>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:217 + 8e5b2f: 291a00 movi a9, 0x100 + 8e5b32: 0c0200 memw + 8e5b35: 28d100 l16ui a8, a13, 0 + 8e5b38: 098802 or a8, a8, a9 + 8e5b3b: 0c0200 memw + 8e5b3e: 28d500 s16i a8, a13, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:218 + 8e5b41: 0c0200 memw +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:220 + 8e5b44: 8fa2 l32i.n a15, a10, 8 + 8e5b46: 89a3 l32i.n a9, a10, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:218 + 8e5b48: 9db2 s32i.n a13, a11, 8 + 8e5b4a: ccf9 bnez.n a15, 8e5b57 <_DMAengine_xmit_buf+0xaf> + 8e5b4c: cc97 bnez.n a9, 8e5b57 <_DMAengine_xmit_buf+0xaf> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:222 + 8e5b4e: 93a3 s32i.n a3, a10, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:221 + 8e5b50: 93a2 s32i.n a3, a10, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:223 + 8e5b52: 9331 s32i.n a3, a3, 4 + 8e5b54: 600003 j 8e5b5b <_DMAengine_xmit_buf+0xb3> + +008e5b57 <_DMAengine_xmit_buf+0xaf>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:226 + 8e5b57: 9391 s32i.n a3, a9, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:227 + 8e5b59: 93a3 s32i.n a3, a10, 12 + 8e5b5b: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:230 + 8e5b5e: 2882bb l32i a8, a8, 0x2ec + 8e5b61: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:231 + 8e5b64: d10f retw.n + +008e5b66 <_DMAengine_xmit_buf+0xbe>: + ... + +008e5b68 <_DMAengine_flush_xmit>: +_DMAengine_flush_xmit(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:234 + 8e5b68: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:235 + 8e5b6b: d10f retw.n + +008e5b6d <_DMAengine_flush_xmit+0x5>: + 8e5b6d: 000000 ... + +008e5b70 <_DMAengine_has_compl_packets>: +_DMAengine_has_compl_packets(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:238 + 8e5b70: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:242 + 8e5b73: 8520 l32i.n a5, a2, 0 + 8e5b75: 8321 l32i.n a3, a2, 4 + 8e5b77: 75310f beq a3, a5, 8e5b8a <_DMAengine_has_compl_packets+0x1a> + 8e5b7a: 0c0200 memw + 8e5b7d: 285101 l16ui a8, a5, 2 + 8e5b80: c021 movi.n a2, 1 + 8e5b82: 080841 extui a8, a8, 0, 2 + 8e5b85: 688101 beqi a8, 1, 8e5b8a <_DMAengine_has_compl_packets+0x1a> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:246 + 8e5b88: d10f retw.n + +008e5b8a <_DMAengine_has_compl_packets+0x1a>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:242 + 8e5b8a: c020 movi.n a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:246 + 8e5b8c: d10f retw.n + +008e5b8e <_DMAengine_has_compl_packets+0x1e>: + ... + +008e5b90 <_DMAengine_reap_recv_buf>: +_DMAengine_reap_recv_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:250 + 8e5b90: 6c1004 entry a1, 32 + 8e5b93: da20 mov.n a10, a2 + 8e5b95: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:256 + 8e5b98: 2822b9 l32i a8, a2, 0x2e4 + 8e5b9b: 0b8000 callx8 a8 + 8e5b9e: d3a0 mov.n a3, a10 + 8e5ba0: cca3 bnez.n a10, 8e5ba7 <_DMAengine_reap_recv_buf+0x17> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:259 + 8e5ba2: c0a0 movi.n a10, 0 + 8e5ba4: 600013 j 8e5bbb <_DMAengine_reap_recv_buf+0x2b> + +008e5ba7 <_DMAengine_reap_recv_buf+0x17>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:265 + 8e5ba7: 2822a1 l32i a8, a2, 0x284 + 8e5baa: 0b8000 callx8 a8 + 8e5bad: d2a0 mov.n a2, a10 + 8e5baf: cca1 bnez.n a10, 8e5bb4 <_DMAengine_reap_recv_buf+0x24> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:266 + 8e5bb1: 63fffc j 8e5bb1 <_DMAengine_reap_recv_buf+0x21> + +008e5bb4 <_DMAengine_reap_recv_buf+0x24>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:268 + 8e5bb4: db30 mov.n a11, a3 + 8e5bb6: 58003c call8 8e5ca8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:269 + 8e5bb9: da20 mov.n a10, a2 + 8e5bbb: d2a0 mov.n a2, a10 + 8e5bbd: d10f retw.n + +008e5bbf <_DMAengine_reap_recv_buf+0x2f>: + ... + +008e5bc0 <_DMAengine_reap_xmited_buf>: +_DMAengine_reap_xmited_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:273 + 8e5bc0: 6c1004 entry a1, 32 + 8e5bc3: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:277 + 8e5bc6: 2882b9 l32i a8, a8, 0x2e4 + 8e5bc9: da20 mov.n a10, a2 + 8e5bcb: 0b8000 callx8 a8 + 8e5bce: dba0 mov.n a11, a10 + 8e5bd0: cca3 bnez.n a10, 8e5bd7 <_DMAengine_reap_xmited_buf+0x17> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:280 + 8e5bd2: c030 movi.n a3, 0 + 8e5bd4: 60001a j 8e5bf2 <_DMAengine_reap_xmited_buf+0x32> + +008e5bd7 <_DMAengine_reap_xmited_buf+0x17>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:284 + 8e5bd7: 8322 l32i.n a3, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:285 + 8e5bd9: 8923 l32i.n a9, a2, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:284 + 8e5bdb: c0c0 movi.n a12, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:285 + 8e5bdd: 739906 bne a9, a3, 8e5be7 <_DMAengine_reap_xmited_buf+0x27> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:286 + 8e5be0: 9c22 s32i.n a12, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:287 + 8e5be2: 9c23 s32i.n a12, a2, 12 + 8e5be4: 600003 j 8e5beb <_DMAengine_reap_xmited_buf+0x2b> + +008e5be7 <_DMAengine_reap_xmited_buf+0x27>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:289 + 8e5be7: 8a31 l32i.n a10, a3, 4 + 8e5be9: 9a22 s32i.n a10, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:292 + 8e5beb: 9c31 s32i.n a12, a3, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:293 + 8e5bed: da30 mov.n a10, a3 + 8e5bef: 58002e call8 8e5ca8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:294 + 8e5bf2: d230 mov.n a2, a3 + 8e5bf4: d10f retw.n + +008e5bf6 <_DMAengine_reap_xmited_buf+0x36>: + ... + +008e5bf8 <_DMAengine_desc_dump>: +_DMAengine_desc_dump(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:298 + 8e5bf8: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:302 + 8e5bfb: 8320 l32i.n a3, a2, 0 + 8e5bfd: c040 movi.n a4, 0 + 8e5bff: c478 movi.n a7, 72 + 8e5c01: c563 movi.n a6, 83 + 8e5c03: 150018 l32r a5, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:305 + 8e5c06: 8821 l32i.n a8, a2, 4 + 8e5c08: 738915 bne a8, a3, 8e5c21 <_DMAengine_desc_dump+0x29> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:310 + 8e5c0b: 285212 l32i a8, a5, 72 + 8e5c0e: db30 mov.n a11, a3 + 8e5c10: 1a018b l32r a10, 4e862c <_lit4_start+0x62c> + 8e5c13: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:328 + 8e5c16: 285212 l32i a8, a5, 72 + 8e5c19: 1a018c l32r a10, 4e8630 <_lit4_start+0x630> + 8e5c1c: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:329 + 8e5c1f: d10f retw.n + +008e5c21 <_DMAengine_desc_dump+0x29>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:318 + 8e5c21: dc60 mov.n a12, a6 + 8e5c23: 0c0200 memw + 8e5c26: 1a018d l32r a10, 4e8634 <_lit4_start+0x634> + 8e5c29: 293101 l16ui a9, a3, 2 + 8e5c2c: db30 mov.n a11, a3 + 8e5c2e: 285212 l32i a8, a5, 72 + 8e5c31: 090940 extui a9, a9, 0, 1 + 8e5c34: 097c39 movnez a12, a7, a9 + 8e5c37: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:321 + 8e5c3a: c0b5 movi.n a11, 5 + 8e5c3c: b144 addi.n a4, a4, 1 + 8e5c3e: da40 mov.n a10, a4 + 8e5c40: 580396 call8 8e6a9c <__umodsi3> + 8e5c43: cca7 bnez.n a10, 8e5c4e <_DMAengine_desc_dump+0x56> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:323 + 8e5c45: 285212 l32i a8, a5, 72 + 8e5c48: 1a018e l32r a10, 4e8638 <_lit4_start+0x638> + +008e5c4b <_DMAengine_desc_dump+0x53>: + 8e5c4b: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:326 + 8e5c4e: 0c0200 memw + 8e5c51: 8334 l32i.n a3, a3, 16 + 8e5c53: 63ffaf j 8e5c06 <_DMAengine_desc_dump+0xe> + +008e5c56 <_DMAengine_desc_dump+0x5e>: + ... + +008e5c58 : +dma_engine_module_install(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:334 + 8e5c58: 6c1004 entry a1, 32 + 8e5c5b: 190192 l32r a9, 4e8648 <_lit4_start+0x648> + 8e5c5e: 130194 l32r a3, 4e8650 <_lit4_start+0x650> + 8e5c61: 1a0191 l32r a10, 4e8644 <_lit4_start+0x644> + 8e5c64: 1b0190 l32r a11, 4e8640 <_lit4_start+0x640> + 8e5c67: 1c018f l32r a12, 4e863c <_lit4_start+0x63c> + 8e5c6a: 1d0197 l32r a13, 4e865c <_lit4_start+0x65c> + 8e5c6d: 1e0196 l32r a14, 4e8658 <_lit4_start+0x658> + 8e5c70: 1f0195 l32r a15, 4e8654 <_lit4_start+0x654> + 8e5c73: 180193 l32r a8, 4e864c <_lit4_start+0x64c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:340 + 8e5c76: 9826 s32i.n a8, a2, 24 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8e5fb9 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:119 + 8e5f8f: c081 movi.n a8, 1 + 8e5f91: 0c0200 memw + 8e5f94: 9870 s32i.n a8, a7, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:120 + 8e5f96: 600006 j 8e5fa0 + +008e5f99 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:132 + 8e5f99: c093 movi.n a9, 3 + 8e5f9b: 0c0200 memw + 8e5f9e: 9970 s32i.n a9, a7, 0 + 8e5fa0: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:136 + 8e5fa3: dc30 mov.n a12, a3 + 8e5fa5: 288276 l32i a8, a8, 0x1d8 + 8e5fa8: 8a61 l32i.n a10, a6, 4 + 8e5faa: 2b6009 l8ui a11, a6, 9 + 8e5fad: 0b8000 callx8 a8 + 8e5fb0: cc43 bnez.n a4, 8e5fb7 + 8e5fb2: cc51 bnez.n a5, 8e5fb7 + +008e5fb4 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:140 + 8e5fb4: 0b2000 callx8 a2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:142 + 8e5fb7: d10f retw.n + +008e5fb9 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:123 + 8e5fb9: adca add.n a10, a12, a13 + 8e5fbb: 0c0200 memw + 8e5fbe: 8b20 l32i.n a11, a2, 0 + 8e5fc0: 5bffc1 call8 8e5ec8 + 8e5fc3: d5a0 mov.n a5, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:127 + 8e5fc5: 0c0200 memw + 8e5fc8: 8221 l32i.n a2, a2, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:129 + 8e5fca: 65afcb bnez a10, 8e5f99 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:130 + 8e5fcd: c092 movi.n a9, 2 + 8e5fcf: 0c0200 memw + 8e5fd2: 9970 s32i.n a9, a7, 0 + 8e5fd4: 63ffc8 j 8e5fa0 + +008e5fd7 : + ... + +008e5fd8 : +magpie_mdio_module_install(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:146 + 8e5fd8: 6c1004 entry a1, 32 + 8e5fdb: c080 movi.n a8, 0 + 8e5fdd: 1301a3 l32r a3, 4e868c <_lit4_start+0x68c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:148 + 8e5fe0: 9320 s32i.n a3, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:149 + 8e5fe2: 9824 s32i.n a8, a2, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:150 + 8e5fe4: 9825 s32i.n a8, a2, 20 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:151 + 8e5fe6: 982b s32i.n a8, a2, 44 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4e839c <_lit4_start+0x39c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:171 + 8e6017: 2c2a00 movi a12, 0x200 + 8e601a: 0cbb02 or a11, a11, a12 + 8e601d: 0b0b4f extui a11, a11, 0, 16 + 8e6020: 5bff8f call8 8e5e60 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:173 + 8e6023: 28323b l32i a8, a3, 236 + 8e6026: 2a3ae8 movi a10, 0x3e8 + 8e6029: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:176 + 8e602c: 0c0200 memw + 8e602f: 2b2284 l32i a11, a2, 0x210 + 8e6032: 1a00e7 l32r a10, 4e839c <_lit4_start+0x39c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:178 + 8e6035: 2cdaff movi a12, 0xfffffdff + 8e6038: 0cbb01 and a11, a11, a12 + 8e603b: 0b0b4f extui a11, a11, 0, 16 + 8e603e: 5bff88 call8 8e5e60 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l32i.n a7, a6, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:238 + 8e6136: a23a add.n a10, a3, a2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:242 + 8e6138: b466 addi.n a6, a6, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:232 + 8e613a: 07074f extui a7, a7, 0, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:234 + 8e613d: 738901 bne a8, a3, 8e6142 + 8e6140: cc9a bnez.n a9, 8e614e + +008e6142 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:239 + 8e6142: 27a401 s8i a7, a10, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:238 + 8e6145: 078b14 srli a11, a7, 8 + 8e6148: 2ba400 s8i a11, a10, 0 + 8e614b: 600004 j 8e6153 + +008e614e : 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mov.n a12, a3 + 8e616c: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:254 + 8e616f: 6a3117 blti a3, 1, 8e618a + 8e6172: c040 movi.n a4, 0 + +008e6174 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:255 + 8e6174: 5bffd2 call8 8e60c0 + 8e6177: d5a0 mov.n a5, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:257 + 8e6179: a24a add.n a10, a4, a2 + 8e617b: db50 mov.n a11, a5 + 8e617d: 5bffe5 call8 8e6114 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:258 + 8e6180: a454 add.n a4, a5, a4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:259 + 8e6182: c0a0 movi.n a10, 0 + 8e6184: 5bffdd call8 8e60fc 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<_buf_pool_static_init>: +_buf_pool_static_init(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:44 + 8e6288: 6c1004 entry a1, 32 + 8e628b: 1201ba l32r a2, 4e86e8 <_lit4_start+0x6e8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:48 + 8e628e: c050 movi.n a5, 0 + 8e6290: c03a movi.n a3, 10 + 8e6292: 022402 or a4, a2, a2 + 8e6295: 6d3a03 loopgtz a3, 8e629c <_buf_pool_static_init+0x14> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:49 + 8e6298: 9540 s32i.n a5, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:50 + 8e629a: b444 addi.n a4, a4, 4 + +008e629c <_buf_pool_static_init+0x14>: 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:79 + 8e62c6: 0b8000 callx8 a8 + 8e62c9: d4a0 mov.n a4, a10 +/root/Workspace/0412_v202/tgt/target/adf/os/inc/adf_os_mem_pvt.h:10 + 8e62cb: 286252 l32i a8, a6, 0x148 + 8e62ce: db50 mov.n a11, a5 + 8e62d0: c0a0 movi.n a10, 0 + 8e62d2: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:77 + 8e62d5: 8c10 l32i.n a12, a1, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:95 + 8e62d7: b177 addi.n a7, a7, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:82 + 8e62d9: 254504 s16i a5, a4, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:81 + 8e62dc: 9a41 s32i.n a10, a4, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:84 + 8e62de: c0b0 movi.n a11, 0 + 8e62e0: 2b4506 s16i a11, a4, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:83 + 8e62e3: 2b4505 s16i a11, a4, 10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:89 + 8e62e6: 8930 l32i.n a9, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:87 + 8e62e8: 9420 s32i.n a4, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:86 + 8e62ea: 2b2504 s16i a11, a2, 8 + 8e62ed: cc95 bnez.n a9, 8e62f6 <_buf_pool_static_create_pool+0x4e> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:90 + 8e62ef: 9230 s32i.n a2, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:77 + 8e62f1: 77c9c6 bne a12, a7, 8e62bb <_buf_pool_static_create_pool+0x13> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:96 + 8e62f4: d10f retw.n + +008e62f6 <_buf_pool_static_create_pool+0x4e>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:92 + 8e62f6: 9921 s32i.n a9, a2, 4 + 8e62f8: 63fff3 j 8e62ef <_buf_pool_static_create_pool+0x47> + +008e62fb <_buf_pool_static_create_pool+0x53>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:96 + 8e62fb: d10f retw.n + +008e62fd <_buf_pool_static_create_pool+0x55>: + 8e62fd: 000000 ... + +008e6300 <_buf_pool_static_alloc_buf>: +_buf_pool_static_alloc_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:99 + 8e6300: 6c1004 entry a1, 32 + 8e6303: 1201ba l32r a2, 4e86e8 <_lit4_start+0x6e8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:102 + 8e6306: 02330a addx4 a3, a3, a2 + 8e6309: 8230 l32i.n a2, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:104 + 8e630b: c050 movi.n a5, 0 + 8e630d: c82f beqz.n a2, 8e6320 <_buf_pool_static_alloc_buf+0x20> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:107 + 8e630f: 8620 l32i.n a6, a2, 0 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a1, 32 + 8e6337: 1201ba l32r a2, 4e86e8 <_lit4_start+0x6e8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:122 + 8e633a: 02330a addx4 a3, a3, a2 + 8e633d: 8530 l32i.n a5, a3, 0 + 8e633f: c850 beqz.n a5, 8e6343 <_buf_pool_static_free_buf+0xf> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:125 + 8e6341: 9541 s32i.n a5, a4, 4 + +008e6343 <_buf_pool_static_free_buf+0xf>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:123 + 8e6343: 9430 s32i.n a4, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:128 + 8e6345: d10f retw.n + +008e6347 <_buf_pool_static_free_buf+0x13>: + ... + +008e6348 <_xtos_set_exception_handler>: +_xtos_set_exception_handler(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-sethandler.c:33 + 8e6348: 6c1004 entry a1, 32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-sethandler.c:36 + 8e634b: 6f2d2d bgeui a2, 64, 8e637c <_xtos_set_exception_handler+0x34> + 8e634e: 1901bb l32r a9, 4e86ec <_lit4_start+0x6ec> + 8e6351: ca3b beqz.n a3, 8e6380 <_xtos_set_exception_handler+0x38> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-sethandler.c:48 + 8e6353: c0a0 movi.n a10, 0 + 8e6355: 1601bd l32r a6, 4e86f4 <_lit4_start+0x6f4> + 8e6358: 1401be l32r a4, 4e86f8 <_lit4_start+0x6f8> + 8e635b: 180006 l32r a8, 4e8018 <_lit4_start+0x18> + 8e635e: 1c01bc l32r a12, 4e86f0 <_lit4_start+0x6f0> + 8e6361: 0e2511 slli a5, a2, 2 + 8e6364: 09370c sub a7, a3, a9 + 8e6367: ac5c add.n a12, a5, a12 + 8e6369: a855 add.n a5, a5, a8 + 8e636b: 82c0 l32i.n a2, a12, 0 + 8e636d: 93c0 s32i.n a3, a12, 0 + 8e636f: 076439 movnez a4, a6, a7 + 8e6372: 9450 s32i.n a4, a5, 0 + 8e6374: 092b0c sub a11, a2, a9 + 8e6377: 0ba238 moveqz a2, a10, a11 + 8e637a: d10f retw.n + +008e637c <_xtos_set_exception_handler+0x34>: + 8e637c: c020 movi.n a2, 0 + 8e637e: d10f retw.n + +008e6380 <_xtos_set_exception_handler+0x38>: + 8e6380: c0a0 movi.n a10, 0 + 8e6382: 09970c sub a7, a9, a9 + 8e6385: 1601bd l32r a6, 4e86f4 <_lit4_start+0x6f4> + 8e6388: 180006 l32r a8, 4e8018 <_lit4_start+0x18> + 8e638b: 1c01bc l32r a12, 4e86f0 <_lit4_start+0x6f0> + 8e638e: 0e2511 slli a5, a2, 2 + 8e6391: 1401be l32r a4, 4e86f8 <_lit4_start+0x6f8> + 8e6394: ac5c add.n a12, a5, a12 + 8e6396: a855 add.n a5, a5, a8 + 8e6398: 82c0 l32i.n a2, a12, 0 + 8e639a: 99c0 s32i.n a9, a12, 0 + 8e639c: 076439 movnez a4, a6, a7 + 8e639f: 9450 s32i.n a4, a5, 0 + 8e63a1: 092b0c sub a11, a2, a9 + 8e63a4: 0ba238 moveqz a2, a10, a11 + 8e63a7: d10f retw.n + +008e63a9 <_xtos_set_exception_handler+0x61>: + 8e63a9: 000000 ... + +008e63ac <_xtos_cause3_handler>: +_xtos_cause3_handler(): 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+/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-c-wrapper-handler.S:97 + 8e63be: 02e616 xsr.ps a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-c-wrapper-handler.S:104 + 8e63c1: 9310 s32i.n a3, a1, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-c-wrapper-handler.S:105 + 8e63c3: 9211 s32i.n a2, a1, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-c-wrapper-handler.S:126 + 8e63c5: 211c70 addi a1, a1, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-c-wrapper-handler.S:128 + 8e63c8: 12000a l32r a2, 4e8028 <_lit4_start+0x28> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-c-wrapper-handler.S:130 + 8e63cb: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-c-wrapper-handler.S:213 + 8e63ce: 032402 or a4, a2, a3 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<__udivsi3+0x43>: + ... + +008e6a91 <__udivsi3+0x45>: +/home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm:570 + 8e6a91: 000000 ill + +008e6a94 <__udivsi3+0x48>: + 8e6a94: 44495630 DIV0 + +008e6a98 <__udivsi3+0x4c>: +/home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm:574 + 8e6a98: c020 movi.n a2, 0 +/home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm:576 + 8e6a9a: d10f retw.n + +008e6a9c <__umodsi3>: +__umodsi3(): +/home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm:673 + 8e6a9c: 6c1002 entry a1, 16 +/home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm:677 + 8e6a9f: 6e3229 bltui a3, 2, 8e6acc <__umodsi3+0x30> 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+/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memcpy.S:292 + 8e6c42: b233 addi.n a3, a3, 2 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memcpy.S:293 + 8e6c44: 265400 s8i a6, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memcpy.S:294 + 8e6c47: 275401 s8i a7, a5, 1 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memcpy.S:295 + 8e6c4a: b255 addi.n a5, a5, 2 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memcpy.S:296 + 8e6c4c: 7f4f01 bbsi a4, 31, 8e6c51 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memcpy.S:297 + 8e6c4f: d10f retw.n + +008e6c51 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memcpy.S:300 + 8e6c51: 263000 l8ui a6, a3, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memcpy.S:301 + 8e6c54: 265400 s8i a6, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memcpy.S:302 + 8e6c57: d10f retw.n + +008e6c59 : + 8e6c59: 000000 ... + +008e6c5c : +memmove(): +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:62 + 8e6c5c: 6c1004 entry a1, 32 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:93 + 8e6c5f: d820 mov.n a8, a2 + 8e6c61: d940 mov.n a9, a4 + 8e6c63: da40 mov.n a10, a4 + 8e6c65: d730 mov.n a7, a3 + 8e6c67: d320 mov.n a3, a2 + 8e6c69: 727b1b bgeu a7, a2, 8e6c88 + 8e6c6c: a742 add.n a2, a4, a7 + 8e6c6e: 723b16 bgeu a3, a2, 8e6c88 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:97 + 8e6c71: a843 add.n a3, a4, a8 + 8e6c73: 6440a3 beqz a4, 8e6d1a + 8e6c76: 6d4909 loopnez a4, 8e6c83 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:100 + 8e6c79: b022 addi.n a2, a2, -1 + 8e6c7b: b033 addi.n a3, a3, -1 + 8e6c7d: 242000 l8ui a4, a2, 0 + 8e6c80: 243400 s8i a4, a3, 0 + +008e6c83 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:141 + 8e6c83: d280 mov.n a2, a8 + 8e6c85: d10f retw.n + +008e6c87 : + ... + +008e6c88 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:108 + 8e6c88: 6e9b08 bltui a9, 16, 8e6c94 + 8e6c8b: 087b02 or a11, a7, a8 + 8e6c8e: 0b0b41 extui a11, a11, 0, 2 + 8e6c91: 64b089 beqz a11, 8e6d1e + +008e6c94 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:135 + 8e6c94: b0ac addi.n a12, a10, -1 + 8e6c96: 69c002 bnei a12, -1, 8e6c9c + 8e6c99: 60007d j 8e6d1a + 8e6c9c: 0a4212 srai a2, a10, 4 + 8e6c9f: 0a0d43 extui a13, a10, 0, 4 + 8e6ca2: 6dda09 loopgtz a13, 8e6caf +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:137 + 8e6ca5: 2e7000 l8ui a14, a7, 0 + 8e6ca8: 2e3400 s8i a14, a3, 0 + 8e6cab: b177 addi.n a7, a7, 1 + 8e6cad: b133 addi.n a3, a3, 1 + +008e6caf : + 8e6caf: d430 mov.n a4, a3 + 8e6cb1: 6d2a65 loopgtz a2, 8e6d1a + 8e6cb4: 227000 l8ui a2, a7, 0 + 8e6cb7: 224400 s8i a2, a4, 0 + 8e6cba: 227001 l8ui a2, a7, 1 + 8e6cbd: 224401 s8i a2, a4, 1 + 8e6cc0: 227002 l8ui a2, a7, 2 + 8e6cc3: 224402 s8i a2, a4, 2 + 8e6cc6: 227003 l8ui a2, a7, 3 + 8e6cc9: 224403 s8i a2, a4, 3 + 8e6ccc: 227004 l8ui a2, a7, 4 + 8e6ccf: 224404 s8i a2, a4, 4 + 8e6cd2: 227005 l8ui a2, a7, 5 + 8e6cd5: 224405 s8i a2, a4, 5 + 8e6cd8: 227006 l8ui a2, a7, 6 + 8e6cdb: 224406 s8i a2, a4, 6 + 8e6cde: 227007 l8ui a2, a7, 7 + 8e6ce1: 224407 s8i a2, a4, 7 + 8e6ce4: 227008 l8ui a2, a7, 8 + 8e6ce7: 224408 s8i a2, a4, 8 + 8e6cea: 227009 l8ui a2, a7, 9 + 8e6ced: 224409 s8i a2, a4, 9 + 8e6cf0: 22700a l8ui a2, a7, 10 + 8e6cf3: 22440a s8i a2, a4, 10 + 8e6cf6: 22700b l8ui a2, a7, 11 + 8e6cf9: 22440b s8i a2, a4, 11 + 8e6cfc: 22700c l8ui a2, a7, 12 + 8e6cff: 22440c s8i a2, a4, 12 + 8e6d02: 22700d l8ui a2, a7, 13 + 8e6d05: 22440d s8i a2, a4, 13 + 8e6d08: 22700e l8ui a2, a7, 14 + 8e6d0b: 22440e s8i a2, a4, 14 + 8e6d0e: 22700f l8ui a2, a7, 15 + 8e6d11: 22440f s8i a2, a4, 15 + 8e6d14: 277c10 addi a7, a7, 16 + 8e6d17: 244c10 addi a4, a4, 16 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:141 + 8e6d1a: d280 mov.n a2, a8 + 8e6d1c: d10f retw.n + +008e6d1e : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:114 + 8e6d1e: d380 mov.n a3, a8 + 8e6d20: 6f9b02 bgeui a9, 16, 8e6d26 + 8e6d23: 600082 j 8e6da9 + 8e6d26: c0a1 movi.n a10, 1 + 8e6d28: 269c0f addi a6, a9, 15 + 8e6d2b: 09963b movgez a6, a9, a9 + 8e6d2e: 064612 srai a6, a6, 4 + 8e6d31: 0a6635 max a6, a6, a10 + 8e6d34: 060f41 extui a15, a6, 0, 2 + 8e6d37: 066402 or a4, a6, a6 + 8e6d3a: 042212 srai a2, a4, 2 + 8e6d3d: 6dfa15 loopgtz a15, 8e6d56 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:119 + 8e6d40: 8d70 l32i.n a13, a7, 0 + 8e6d42: 9d30 s32i.n a13, a3, 0 + 8e6d44: 8c71 l32i.n a12, a7, 4 + 8e6d46: 9c31 s32i.n a12, a3, 4 + 8e6d48: 8b72 l32i.n a11, a7, 8 + 8e6d4a: 9b32 s32i.n a11, a3, 8 + 8e6d4c: 8a73 l32i.n a10, a7, 12 + 8e6d4e: 9a33 s32i.n a10, a3, 12 + 8e6d50: 277c10 addi a7, a7, 16 + 8e6d53: 233c10 addi a3, a3, 16 + +008e6d56 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:114 + 8e6d56: d430 mov.n a4, a3 + 8e6d58: 0c6a11 slli a10, a6, 4 + 8e6d5b: 0a9a0c sub a10, a9, a10 + 8e6d5e: 6d2a45 loopgtz a2, 8e6da7 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:119 + 8e6d61: 8270 l32i.n a2, a7, 0 + 8e6d63: 9240 s32i.n a2, a4, 0 + 8e6d65: 8271 l32i.n a2, a7, 4 + 8e6d67: 9241 s32i.n a2, a4, 4 + 8e6d69: 8272 l32i.n a2, a7, 8 + 8e6d6b: 9242 s32i.n a2, a4, 8 + 8e6d6d: 8273 l32i.n a2, a7, 12 + 8e6d6f: 9243 s32i.n a2, a4, 12 + 8e6d71: 8274 l32i.n a2, a7, 16 + 8e6d73: 9244 s32i.n a2, a4, 16 + 8e6d75: 8275 l32i.n a2, a7, 20 + 8e6d77: 9245 s32i.n a2, a4, 20 + 8e6d79: 8276 l32i.n a2, a7, 24 + 8e6d7b: 9246 s32i.n a2, a4, 24 + 8e6d7d: 8277 l32i.n a2, a7, 28 + 8e6d7f: 9247 s32i.n a2, a4, 28 + 8e6d81: 8278 l32i.n a2, a7, 32 + 8e6d83: 9248 s32i.n a2, a4, 32 + 8e6d85: 8279 l32i.n a2, a7, 36 + 8e6d87: 9249 s32i.n a2, a4, 36 + 8e6d89: 827a l32i.n a2, a7, 40 + 8e6d8b: 924a s32i.n a2, a4, 40 + 8e6d8d: 827b l32i.n a2, a7, 44 + 8e6d8f: 924b s32i.n a2, a4, 44 + 8e6d91: 827c l32i.n a2, a7, 48 + 8e6d93: 924c s32i.n a2, a4, 48 + 8e6d95: 827d l32i.n a2, a7, 52 + 8e6d97: 924d s32i.n a2, a4, 52 + 8e6d99: 827e l32i.n a2, a7, 56 + 8e6d9b: 924e s32i.n a2, a4, 56 + 8e6d9d: 827f l32i.n a2, a7, 60 + 8e6d9f: 924f s32i.n a2, a4, 60 + 8e6da1: 277c40 addi a7, a7, 64 + 8e6da4: 244c40 addi a4, a4, 64 + +008e6da7 : + 8e6da7: d340 mov.n a3, a4 + +008e6da9 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:124 + 8e6da9: d6a0 mov.n a6, a10 + 8e6dab: 6fa402 bgeui a10, 4, 8e6db1 + 8e6dae: 63fee2 j 8e6c94 + 8e6db1: 0a2b43 extui a11, a10, 2, 4 + 8e6db4: 0a2914 srli a9, a10, 2 + 8e6db7: d490 mov.n a4, a9 + 8e6db9: 6db907 loopnez a11, 8e6dc4 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:126 + 8e6dbc: 8c70 l32i.n a12, a7, 0 + 8e6dbe: 9c30 s32i.n a12, a3, 0 + 8e6dc0: b477 addi.n a7, a7, 4 + 8e6dc2: b433 addi.n a3, a3, 4 + +008e6dc4 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:124 + 8e6dc4: 0e9a11 slli a10, a9, 2 + 8e6dc7: 044214 srli a2, a4, 4 + 8e6dca: 033402 or a4, a3, a3 + 8e6dcd: 6d2945 loopnez a2, 8e6e16 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:126 + 8e6dd0: 8270 l32i.n a2, a7, 0 + 8e6dd2: 9240 s32i.n a2, a4, 0 + 8e6dd4: 8271 l32i.n a2, a7, 4 + 8e6dd6: 9241 s32i.n a2, a4, 4 + 8e6dd8: 8272 l32i.n a2, a7, 8 + 8e6dda: 9242 s32i.n a2, a4, 8 + 8e6ddc: 8273 l32i.n a2, a7, 12 + 8e6dde: 9243 s32i.n a2, a4, 12 + 8e6de0: 8274 l32i.n a2, a7, 16 + 8e6de2: 9244 s32i.n a2, a4, 16 + 8e6de4: 8275 l32i.n a2, a7, 20 + 8e6de6: 9245 s32i.n a2, a4, 20 + 8e6de8: 8276 l32i.n a2, a7, 24 + 8e6dea: 9246 s32i.n a2, a4, 24 + 8e6dec: 8277 l32i.n a2, a7, 28 + 8e6dee: 9247 s32i.n a2, a4, 28 + 8e6df0: 8278 l32i.n a2, a7, 32 + 8e6df2: 9248 s32i.n a2, a4, 32 + 8e6df4: 8279 l32i.n a2, a7, 36 + 8e6df6: 9249 s32i.n a2, a4, 36 + 8e6df8: 827a l32i.n a2, a7, 40 + 8e6dfa: 924a s32i.n a2, a4, 40 + 8e6dfc: 827b l32i.n a2, a7, 44 + 8e6dfe: 924b s32i.n a2, a4, 44 + 8e6e00: 827c l32i.n a2, a7, 48 + 8e6e02: 924c s32i.n a2, a4, 48 + 8e6e04: 827d l32i.n a2, a7, 52 + 8e6e06: 924d s32i.n a2, a4, 52 + 8e6e08: 827e l32i.n a2, a7, 56 + 8e6e0a: 924e s32i.n a2, a4, 56 + 8e6e0c: 827f l32i.n a2, a7, 60 + 8e6e0e: 924f s32i.n a2, a4, 60 + 8e6e10: 277c40 addi a7, a7, 64 + 8e6e13: 244c40 addi a4, a4, 64 + +008e6e16 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:124 + 8e6e16: 0a6a0c sub a10, a6, a10 + 8e6e19: d340 mov.n a3, a4 + 8e6e1b: 63fe75 j 8e6c94 + +008e6e1e : + ... + +008e6e20 <__memset_aux>: + ... + +008e6e21 <__memset_aux+0x1>: +__memset_aux(): +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:59 + 8e6e21: 6d4904 loopnez a4, 8e6e29 <__memset_aux+0x9> +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:64 + 8e6e24: 235400 s8i a3, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:65 + 8e6e27: b155 addi.n a5, a5, 1 + +008e6e29 <__memset_aux+0x9>: +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:69 + 8e6e29: d10f retw.n + +008e6e2b <__memset_aux+0xb>: + ... + +008e6e2c <__memset_aux+0xc>: +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:79 + 8e6e2c: 6e48f1 bltui a4, 8, 8e6e21 <__memset_aux+0x1> +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:82 + 8e6e2f: 235400 s8i a3, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:83 + 8e6e32: b155 addi.n a5, a5, 1 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:84 + 8e6e34: b044 addi.n a4, a4, -1 + +008e6e36 <__memset_aux+0x16>: +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:87 + 8e6e36: 7e5728 bbci a5, 30, 8e6e62 + +008e6e39 <__memset_aux+0x19>: +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:92 + 8e6e39: 6e48e4 bltui a4, 8, 8e6e21 <__memset_aux+0x1> +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:95 + 8e6e3c: 235500 s16i a3, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:96 + 8e6e3f: b255 addi.n a5, a5, 2 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:97 + 8e6e41: 244cfe addi a4, a4, -2 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:100 + 8e6e44: 60001a j 8e6e62 + +008e6e47 <__memset_aux+0x27>: + ... + +008e6e48 : +memset(): +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:107 + 8e6e48: 6c1002 entry a1, 16 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:111 + 8e6e4b: 030347 extui a3, a3, 0, 8 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:112 + 8e6e4e: 083711 slli a7, a3, 8 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:113 + 8e6e51: 073302 or a3, a3, a7 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:114 + 8e6e54: 003711 slli a7, a3, 16 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:115 + 8e6e57: 073302 or a3, a3, a7 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:117 + 8e6e5a: d520 mov.n a5, a2 + +008e6e5c : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:120 + 8e6e5c: 7f2fcc bbsi a2, 31, 8e6e2c <__memset_aux+0xc> +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:121 + 8e6e5f: 7e2fd6 bbsi a2, 30, 8e6e39 <__memset_aux+0x19> + +008e6e62 : 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................ + 230: 008e6928 0000000d 00000000 00000000 ..i(............ + 240: 0000001c 00020000 0c140400 00000000 ................ + 250: 008e6938 00000018 00000000 00000000 ..i8............ + 260: 0000001c 00020000 0c8e0400 00000000 ................ + 270: 008e13a4 0000088e 00000000 00000000 ................ + 280: 0000001c 00020000 600a0400 00000000 ........`....... + 290: 008e1c34 00000078 00000000 00000000 ...4...x........ + 2a0: 0000001c 00020000 a8820400 00000000 ................ + 2b0: 008e1cac 000000f2 00000000 00000000 ................ + 2c0: 0000001c 00020000 f3df0400 00000000 ................ + 2d0: 008e1da0 000003e5 00000000 00000000 ................ + 2e0: 0000001c 00020001 3de70400 00000000 ........=....... + 2f0: 008e2188 0000018e 00000000 00000000 ..!............. + 300: 0000001c 00020001 88d00400 00000000 ................ + 310: 008e2318 00000026 00000000 00000000 ..#....&........ + 320: 0000001c 00020001 d01d0400 00000000 ................ + 330: 008e2340 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../............. + 440: 0000001c 00020004 69e20400 00000000 ........i....... + 450: 008e33b0 000004d4 00000000 00000000 ..3............. + 460: 0000001c 00020004 b9550400 00000000 .........U...... + 470: 008e3884 00001071 00000000 00000000 ..8....q........ + 480: 0000001c 00020005 10430400 00000000 .........C...... + 490: 008e48f8 000003b3 00000000 00000000 ..H............. + 4a0: 0000001c 00020005 59d90400 00000000 ........Y....... + 4b0: 008e4cac 00000243 00000000 00000000 ..L....C........ + 4c0: 0000001c 00020005 a7030400 00000000 ................ + 4d0: 008e4ef0 00000084 00000000 00000000 ..N............. + 4e0: 0000001c 00020005 eee00400 00000000 ................ + 4f0: 008e4f74 000000b5 00000000 00000000 ..Ot............ + 500: 0000001c 00020006 37230400 00000000 ........7#...... + 510: 008e502c 000008ef 00000000 00000000 ..P,............ + 520: 0000001c 00020006 8fc30400 00000000 ................ + 530: 008e591c 000003d3 00000000 00000000 ..Y............. + 540: 0000001c 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.........X...... + 650: 008e6980 00000008 00000000 00000000 ..i............. + 660: 0000001c 00020007 d7230400 00000000 .........#...... + 670: 008e6988 00000008 00000000 00000000 ..i............. + 680: 0000001c 00020007 d7ee0400 00000000 ................ + 690: 008e6990 00000008 00000000 00000000 ..i............. + 6a0: 0000001c 00020007 dae20400 00000000 ................ + 6b0: 008e6998 00000068 00000000 00000000 ..i....h........ + 6c0: 0000001c 00020007 dbd60400 00000000 ................ + 6d0: 008e6a00 00000049 00000000 00000000 ..j....I........ + 6e0: 0000001c 00020007 dcca0400 00000000 ................ + 6f0: 008e6a4c 00000050 00000000 00000000 ..jL...P........ + 700: 0000001c 00020007 ddbe0400 00000000 ................ + 710: 008e6a9c 0000003d 00000000 00000000 ..j....=........ + 720: 0000001c 00020007 deb20400 00000000 ................ + 730: 008e6adc 00000045 00000000 00000000 ..j....E........ + 740: 0000001c 00020007 e9f20400 00000000 ................ + 750: 008e6b24 00000135 00000000 00000000 ..k$...5........ + 760: 0000001c 00020007 eaff0400 00000000 ................ + 770: 008e6c5c 000001c2 00000000 00000000 ..l\............ + 780: 0000001c 00020007 f6800400 00000000 ................ + 790: 008e6e20 00000074 00000000 00000000 ..n ...t........ + 7a0: 0000001c 00020007 f78d0400 00000000 ................ + 7b0: 008e6560 00000118 00000000 00000000 ..e`............ + 7c0: 0000001c 00020007 f89a0400 00000000 ................ + 7d0: 008e6678 00000098 00000000 00000000 ..fx............ + 7e0: 0000001c 00020007 f9a70400 00000000 ................ + 7f0: 008e6710 00000063 00000000 00000000 ..g....c........ + 800: 0000001c 00020007 fab40400 00000000 ................ + 810: 008e6774 0000008e 00000000 00000000 ..gt............ + 820: 0000001c 00020008 05dd0400 00000000 ................ + 830: 008e6804 0000011b 00000000 00000000 ..h............. +Disassembly of section .debug_pubnames: + +00000000 <.debug_pubnames>: + 0: 00000052 00020000 065c0000 00000000 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Vcmnos_skip_pll_ + 330: 696e6974 00000048 76706c6c 5f637472 init...Hvpll_ctr + 340: 6c5f7365 7474696e 675f3234 67687a00 l_setting_24ghz. + 350: 00004899 706c6c5f 6374726c 5f736574 ..H.pll_ctrl_set + 360: 74696e67 5f356768 7a000000 48d0636d ting_5ghz...H.cm + 370: 6e6f735f 64656c61 795f7573 00000049 nos_delay_us...I + 380: 30636d6e 6f735f6d 696c6c69 7365636f 0cmnos_milliseco + 390: 6e647300 0000495b 636d6e6f 735f7265 nds...I[cmnos_re + 3a0: 66636c6b 5f737065 65645f67 65740000 fclk_speed_get.. + 3b0: 00498a63 6d6e6f73 5f756172 745f6672 .I.cmnos_uart_fr + 3c0: 65717565 6e637900 000049b7 636d6e6f equency...I.cmno + 3d0: 735f7379 73636c6b 5f636861 6e676500 s_sysclk_change. + 3e0: 000049df 636d6e6f 735f636c 6f636b72 ..I.cmnos_clockr + 3f0: 6567735f 696e6974 0000004a 08636d6e egs_init...J.cmn + 400: 6f735f77 6c616e5f 62616e64 5f736574 os_wlan_band_set + 410: 0000004a 49636d6e 6f735f70 6c6c5f69 ...JIcmnos_pll_i + 420: 6e697400 00004a6c 636d6e6f 735f636c nit...Jlcmnos_cl + 430: 6f636b5f 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0400001e 17087470 69640000 001cb202 ......tpid...... + 7df0: 23001570 72696f00 0000168a 01000302 #..prio......... + 7e00: 23021563 66690000 00168a01 03010223 #..cfi.........# + 7e10: 02157669 64000000 1cb20204 0c022302 ..vid.........#. + 7e20: 00076164 665f6e65 745f7669 64000200 ..adf_net_vid... + 7e30: 001e4815 72657300 0000168a 01000402 ..H.res......... + 7e40: 23001576 616c0000 001cb202 040c0223 #..val.........# + 7e50: 0000120c 00001e84 0872785f 62756673 .........rx_bufs + 7e60: 697a6500 00001623 02230008 72785f6e ize....#.#..rx_n + 7e70: 64657363 00000016 23022304 0874785f desc....#.#..tx_ + 7e80: 6e646573 63000000 16230223 08001208 ndesc....#.#.... + 7e90: 00001eaa 08706f6c 6c656400 00001a9d .....polled..... + 7ea0: 02230008 706f6c6c 5f777400 00001623 .#..poll_wt....# + 7eb0: 02230400 0f000016 8a400000 1eb7103f .#.......@.....? + 7ec0: 00124600 001edf08 69665f6e 616d6500 ..F.....if_name. + 7ed0: 00001eaa 02230008 6465765f 61646472 .....#..dev_addr + 7ee0: 0000001c 6f022340 00140400 001f160e ....o.#@........ + 7ef0: 4144465f 4f535f44 4d415f4d 41534b5f ADF_OS_DMA_MASK_ + 7f00: 33324249 5400000e 4144465f 4f535f44 32BIT...ADF_OS_D + 7f10: 4d415f4d 41534b5f 36344249 54000100 MA_MASK_64BIT... + 7f20: 09616466 5f6f735f 646d615f 6d61736b .adf_os_dma_mask + 7f30: 5f740000 001edf07 6164665f 646d615f _t......adf_dma_ + 7f40: 696e666f 00080000 1f630864 6d615f6d info.....c.dma_m + 7f50: 61736b00 00001f16 02230008 73675f6e ask......#..sg_n + 7f60: 73656773 00000016 23022304 00140400 segs....#.#..... + 7f70: 001fb90e 4144465f 4e45545f 434b5355 ....ADF_NET_CKSU + 7f80: 4d5f4e4f 4e450000 0e414446 5f4e4554 M_NONE...ADF_NET + 7f90: 5f434b53 554d5f54 43505f55 44505f49 _CKSUM_TCP_UDP_I + 7fa0: 50763400 010e4144 465f4e45 545f434b Pv4...ADF_NET_CK + 7fb0: 53554d5f 5443505f 5544505f 49507636 SUM_TCP_UDP_IPv6 + 7fc0: 00020009 6164665f 6e65745f 636b7375 ....adf_net_cksu + 7fd0: 6d5f7479 70655f74 0000001f 63120800 m_type_t....c... + 7fe0: 001ffc08 74785f63 6b73756d 0000001f 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U.ADF_NET_T + 8030: 534f5f4e 4f4e4500 000e4144 465f4e45 SO_NONE...ADF_NE + 8040: 545f5453 4f5f4950 56340001 0e414446 T_TSO_IPV4...ADF + 8050: 5f4e4554 5f54534f 5f414c4c 00020009 _NET_TSO_ALL.... + 8060: 6164665f 6e65745f 74736f5f 74797065 adf_net_tso_type + 8070: 5f740000 00201612 10000020 a908636b _t... ..... ..ck + 8080: 73756d5f 63617000 00001ffc 02230008 sum_cap......#.. + 8090: 74736f00 00002055 02230808 766c616e tso... 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085f7374 72637079 ......#.._strcpy + faa0: 00000006 58022304 085f7374 726e6370 ....X.#.._strncp + fab0: 79000000 06650223 08085f73 74726c65 y....e.#.._strle + fac0: 6e000000 06720223 0c085f73 7472636d n....r.#.._strcm + fad0: 70000000 067f0223 10085f73 74726e63 p......#.._strnc + fae0: 6d700000 00068c02 2314000f 00000410 mp......#....... + faf0: 14000007 19100400 095f415f 54494d45 ........._A_TIME + fb00: 525f5350 41434500 0000070c 09415f74 R_SPACE......A_t + fb10: 696d6572 5f740000 00071903 0000072d imer_t.........- + fb20: 04000201 03000007 43040002 01030000 ........C....... + fb30: 074c0400 09415f48 414e444c 45000000 .L...A_HANDLE... + fb40: 04100201 09415f54 494d4552 5f46554e .....A_TIMER_FUN + fb50: 43000000 07630300 00076504 00020103 C....c....e..... + fb60: 0000077e 04000774 696d6572 5f617069 ...~...timer_api + fb70: 00140000 07fd085f 74696d65 725f696e ......._timer_in + fb80: 69740000 00011102 2300085f 74696d65 it......#.._time + fb90: 725f6172 6d000000 07450223 04085f74 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....#........... + feb0: 06000009 24010300 000ad104 00020103 ....$........... + fec0: 00000ade 04000763 6c6f636b 5f617069 .......clock_api + fed0: 00240000 0bc0085f 636c6f63 6b5f696e .$....._clock_in + fee0: 69740000 000aca02 2300085f 636c6f63 it......#.._cloc + fef0: 6b726567 735f696e 69740000 00011102 kregs_init...... + ff00: 2304085f 75617274 5f667265 7175656e #.._uart_frequen + ff10: 63790000 000ad702 2308085f 64656c61 cy......#.._dela + ff20: 795f7573 0000000a e002230c 085f776c y_us......#.._wl + ff30: 616e5f62 616e645f 73657400 00000ae0 an_band_set..... + ff40: 02231008 5f726566 636c6b5f 73706565 .#.._refclk_spee + ff50: 645f6765 74000000 0ad70223 14085f6d d_get......#.._m + ff60: 696c6c69 7365636f 6e647300 00000ad7 illiseconds..... + ff70: 02231808 5f737973 636c6b5f 6368616e .#.._sysclk_chan + ff80: 67650000 00011102 231c085f 636c6f63 ge......#.._cloc + ff90: 6b5f7469 636b0000 00011102 23200006 k_tick......# .. + ffa0: 000001b5 01030000 0bc00400 09415f6f .............A_o + ffb0: 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D....@.#..Flags. + 17d30: 00001340 02230600 075f574d 495f4449 ...@.#..._WMI_DI + 17d40: 53504154 43485f54 41424c45 00100000 SPATCH_TABLE.... + 17d50: 3fb20870 4e657874 0000003f b2022300 ?..pNext...?..#. + 17d60: 0870436f 6e746578 74000000 04070223 .pContext......# + 17d70: 04084e75 6d626572 4f66456e 74726965 ..NumberOfEntrie + 17d80: 73000000 01120223 08087054 61626c65 s......#..pTable + 17d90: 0000003f d102230c 00030000 3f510400 ...?..#.....?Q.. + 17da0: 09574d49 5f444953 50415443 485f454e .WMI_DISPATCH_EN + 17db0: 54525900 00003f06 0300003f b9040003 TRY...?....?.... + 17dc0: 00003f51 04000948 54435f42 55465f43 ..?Q...HTC_BUF_C + 17dd0: 4f4e5445 58540000 003a3f0c 574d495f ONTEXT...:?.WMI_ + 17de0: 4556545f 434c4153 53000400 00406918 EVT_CLASS....@i. + 17df0: 574d495f 4556545f 434c4153 535f4e4f WMI_EVT_CLASS_NO + 17e00: 4e4500ff ffffff0d 574d495f 4556545f NE......WMI_EVT_ + 17e10: 434c4153 535f434d 445f4556 454e5400 CLASS_CMD_EVENT. + 17e20: 000d574d 495f4556 545f434c 4153535f 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_WMI_Shutdown... + 18030: 414e0223 1c085f57 4d495f52 6563764d AN.#.._WMI_RecvM + 18040: 65737361 67654861 6e646c65 72000000 essageHandler... + 18050: 39a30223 20085f57 4d495f53 65727669 9..# ._WMI_Servi + 18060: 6365436f 6e6e6563 74000000 415b0223 ceConnect...A[.# + 18070: 24087052 65736572 76656400 00000407 $.pReserved..... + 18080: 02232800 077a7344 6d614465 73630014 .#(..zsDmaDesc.. + 18090: 0000431f 08637472 6c000000 01760223 ..C..ctrl....v.# + 180a0: 00087374 61747573 00000001 76022302 ..status....v.#. + 180b0: 08746f74 616c4c65 6e000000 01760223 .totalLen....v.# + 180c0: 04086461 74615369 7a650000 00017602 ..dataSize....v. + 180d0: 2306086c 61737441 64647200 0000431f #..lastAddr...C. + 180e0: 02230808 64617461 41646472 00000001 .#..dataAddr.... + 180f0: 9a02230c 086e6578 74416464 72000000 ..#..nextAddr... + 18100: 431f0223 10000300 00429d04 00030000 C..#.....B...... + 18110: 429d0400 077a7344 6d615175 65756500 B....zsDmaQueue. + 18120: 08000043 5f086865 61640000 00432602 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ndler...>..#..Cm + 1c7b0: 64494400 000012e9 02230408 466c6167 dID......#..Flag + 1c7c0: 73000000 12e90223 0600075f 574d495f s......#..._WMI_ + 1c7d0: 44495350 41544348 5f544142 4c450010 DISPATCH_TABLE.. + 1c7e0: 00003f5b 08704e65 78740000 003f5b02 ..?[.pNext...?[. + 1c7f0: 23000870 436f6e74 65787400 00000404 #..pContext..... + 1c800: 02230408 4e756d62 65724f66 456e7472 .#..NumberOfEntr + 1c810: 69657300 0000010f 02230808 70546162 ies......#..pTab + 1c820: 6c650000 003f7a02 230c0003 00003efa le...?z.#.....>. + 1c830: 04000957 4d495f44 49535041 5443485f ...WMI_DISPATCH_ + 1c840: 454e5452 59000000 3eaf0300 003f6204 ENTRY...>....?b. + 1c850: 00030000 3efa0400 09485443 5f425546 ....>....HTC_BUF + 1c860: 5f434f4e 54455854 00000039 e80d574d _CONTEXT...9..WM + 1c870: 495f4556 545f434c 41535300 04000040 I_EVT_CLASS....@ + 1c880: 1219574d 495f4556 545f434c 4153535f ..WMI_EVT_CLASS_ + 1c890: 4e4f4e45 00ffffff ff0e574d 495f4556 NONE......WMI_EV + 1c8a0: 545f434c 4153535f 434d445f 4556454e T_CLASS_CMD_EVEN + 1c8b0: 5400000e 574d495f 4556545f 434c4153 T...WMI_EVT_CLAS + 1c8c0: 535f434d 445f5245 504c5900 010e574d S_CMD_REPLY...WM + 1c8d0: 495f4556 545f434c 4153535f 4d415800 I_EVT_CLASS_MAX. + 1c8e0: 02000957 4d495f45 56545f43 4c415353 ...WMI_EVT_CLASS + 1c8f0: 0000003f 9d075f57 4d495f42 55465f43 ...?.._WMI_BUF_C + 1c900: 4f4e5445 5854000c 00004070 08487463 ONTEXT....@p.Htc + 1c910: 42756643 74780000 003f8802 23000845 BufCtx...?..#..E + 1c920: 76656e74 436c6173 73000000 40120223 ventClass...@..# + 1c930: 0408466c 61677300 000012e9 02230800 ..Flags......#.. + 1c940: 09776d69 5f68616e 646c655f 74000000 .wmi_handle_t... + 1c950: 04040957 4d495f53 56435f43 4f4e4649 ...WMI_SVC_CONFI + 1c960: 47000000 3e280300 00408204 00060000 G...>(...@...... + 1c970: 40700103 0000409d 04000957 4d495f44 @p....@....WMI_D + 1c980: 49535041 5443485f 5441424c 45000000 ISPATCH_TABLE... + 1c990: 3efa0300 0040aa04 00020103 000040c9 >....@........@. + 1c9a0: 04000600 00264001 03000040 d2040002 .....&@....@.... + 1c9b0: 01030000 40df0400 06000001 0f010300 ....@........... + 1c9c0: 0040e804 00020103 000040f5 04000600 .@........@..... + 1c9d0: 0012d501 03000040 fe040007 5f776d69 .......@...._wmi + 1c9e0: 5f737663 5f617069 73002c00 00424608 _svc_apis.,..BF. + 1c9f0: 5f574d49 5f496e69 74000000 40a30223 _WMI_Init...@..# + 1ca00: 00085f57 4d495f52 65676973 74657244 .._WMI_RegisterD + 1ca10: 69737061 74636854 61626c65 00000040 ispatchTable...@ + 1ca20: cb022304 085f574d 495f416c 6c6f6345 ..#.._WMI_AllocE + 1ca30: 76656e74 00000040 d8022308 085f574d vent...@..#.._WM + 1ca40: 495f5365 6e644576 656e7400 000040e1 I_SendEvent...@. + 1ca50: 02230c08 5f574d49 5f476574 50656e64 .#.._WMI_GetPend + 1ca60: 696e6745 76656e74 73436f75 6e740000 ingEventsCount.. + 1ca70: 0040ee02 2310085f 574d495f 53656e64 .@..#.._WMI_Send + 1ca80: 436f6d70 6c657465 48616e64 6c657200 CompleteHandler. + 1ca90: 00003955 02231408 5f574d49 5f476574 ..9U.#.._WMI_Get + 1caa0: 436f6e74 726f6c45 70000000 40ee0223 ControlEp...@..# + 1cab0: 18085f57 4d495f53 68757464 6f776e00 .._WMI_Shutdown. + 1cac0: 000040f7 02231c08 5f574d49 5f526563 ..@..#.._WMI_Rec + 1cad0: 764d6573 73616765 48616e64 6c657200 vMessageHandler. + 1cae0: 0000394c 02232008 5f574d49 5f536572 ..9L.# ._WMI_Ser + 1caf0: 76696365 436f6e6e 65637400 00004104 viceConnect...A. + 1cb00: 02232408 70526573 65727665 64000000 .#$.pReserved... + 1cb10: 04040223 2800077a 73446d61 44657363 ...#(..zsDmaDesc + 1cb20: 00140000 42c80863 74726c00 00000173 ....B..ctrl....s + 1cb30: 02230008 73746174 75730000 00017302 .#..status....s. + 1cb40: 23020874 6f74616c 4c656e00 00000173 #..totalLen....s + 1cb50: 02230408 64617461 53697a65 00000001 .#..dataSize.... + 1cb60: 73022306 086c6173 74416464 72000000 s.#..lastAddr... + 1cb70: 42c80223 08086461 74614164 64720000 B..#..dataAddr.. + 1cb80: 00019702 230c086e 65787441 64647200 ....#..nextAddr. + 1cb90: 000042c8 02231000 03000042 46040003 ..B..#.....BF... + 1cba0: 00004246 0400077a 73446d61 51756575 ..BF...zsDmaQueu + 1cbb0: 65000800 00430808 68656164 00000042 e....C..head...B + 1cbc0: cf022300 08746572 6d696e61 746f7200 ..#..terminator. + 1cbd0: 000042cf 02230400 077a7354 78446d61 ..B..#...zsTxDma + 1cbe0: 51756575 65001000 00436c08 68656164 Queue....Cl.head + 1cbf0: 00000042 cf022300 08746572 6d696e61 ...B..#..termina + 1cc00: 746f7200 000042cf 02230408 786d6974 tor...B..#..xmit + 1cc10: 65645f62 75665f68 65616400 00001434 ed_buf_head....4 + 1cc20: 02230808 786d6974 65645f62 75665f74 .#..xmited_buf_t + 1cc30: 61696c00 00001434 02230c00 02010300 ail....4.#...... + 1cc40: 00436c04 00030000 42d60400 02010300 .Cl.....B....... + 1cc50: 00437c04 00030000 43080400 02010300 .C|.....C....... + 1cc60: 00438c04 00020103 00004395 04000201 .C........C..... + 1cc70: 03000043 9e040006 00001434 01030000 ...C.......4.... + 1cc80: 43a70400 02010300 0043b404 00060000 C........C...... + 1cc90: 14340103 000043bd 04000201 03000043 .4....C........C + 1cca0: ca040006 0000010f 01030000 43d30400 ............C... + 1ccb0: 06000042 cf010300 0043e004 00020103 ...B.....C...... + 1ccc0: 000043ed 04000764 6d615f65 6e67696e ..C....dma_engin + 1ccd0: 655f6170 69004000 00456308 5f696e69 e_api.@..Ec._ini + 1cce0: 74000000 436e0223 00085f69 6e69745f t...Cn.#.._init_ + 1ccf0: 72785f71 75657565 00000043 7e022304 rx_queue...C~.#. + 1cd00: 085f696e 69745f74 785f7175 65756500 ._init_tx_queue. + 1cd10: 0000438e 02230808 5f636f6e 6669675f ..C..#.._config_ + 1cd20: 72785f71 75657565 00000043 9702230c rx_queue...C..#. + 1cd30: 085f786d 69745f62 75660000 0043a002 ._xmit_buf...C.. + 1cd40: 2310085f 666c7573 685f786d 69740000 #.._flush_xmit.. + 1cd50: 00437e02 2314085f 72656170 5f726563 .C~.#.._reap_rec + 1cd60: 765f6275 66000000 43ad0223 18085f72 v_buf...C..#.._r + 1cd70: 65747572 6e5f7265 63765f62 75660000 eturn_recv_buf.. + 1cd80: 0043b602 231c085f 72656170 5f786d69 .C..#.._reap_xmi + 1cd90: 7465645f 62756600 000043c3 02232008 ted_buf...C..# . + 1cda0: 5f737761 705f6461 74610000 0043cc02 _swap_data...C.. + 1cdb0: 2324085f 6861735f 636f6d70 6c5f7061 #$._has_compl_pa + 1cdc0: 636b6574 73000000 43d90223 28085f64 ckets...C..#(._d + 1cdd0: 6573635f 64756d70 00000043 7e02232c esc_dump...C~.#, + 1cde0: 085f6765 745f7061 636b6574 00000043 ._get_packet...C + 1cdf0: e6022330 085f7265 636c6169 6d5f7061 ..#0._reclaim_pa + 1ce00: 636b6574 00000043 ef022334 085f7075 cket...C..#4._pu + 1ce10: 745f7061 636b6574 00000043 ef022338 t_packet...C..#8 + 1ce20: 08705265 73657276 65640000 00040402 .pReserved...... + 1ce30: 233c0009 5f415f63 6d6e6f73 5f696e64 #<.._A_cmnos_ind + 1ce40: 69726563 74696f6e 5f746162 6c655f74 irection_table_t + 1ce50: 00000030 a209574d 495f5356 435f4150 ...0..WMI_SVC_AP + 1ce60: 49530000 00410b17 5f415f6d 61677069 IS...A.._A_magpi + 1ce70: 655f696e 64697265 6374696f 6e5f7461 e_indirection_ta + 1ce80: 626c6500 034c0000 46910863 6d6e6f73 ble..L..F..cmnos + 1ce90: 00000045 63022300 08646267 00000003 ...Ec.#..dbg.... + 1cea0: d10323b8 03086869 66000000 294b0323 ..#...hif...)K.# + 1ceb0: c0030868 74630000 003abe03 23f80308 ...htc...:..#... + 1cec0: 776d695f 7376635f 61706900 00004585 wmi_svc_api...E. + 1ced0: 0323ac04 08757362 6669666f 5f617069 .#...usbfifo_api + 1cee0: 00000032 760323d8 04086275 665f706f ...2v.#...buf_po + 1cef0: 6f6c0000 00371f03 23e40408 76627566 ol...7..#...vbuf + 1cf00: 00000014 5e032380 05087664 65736300 ....^.#...vdesc. + 1cf10: 00001340 03239405 08616c6c 6f637261 ...@.#...allocra + 1cf20: 6d000000 09360323 a8050864 6d615f65 m....6.#...dma_e + 1cf30: 6e67696e 65000000 43f60323 b4050864 ngine...C..#...d + 1cf40: 6d615f6c 69620000 002bdf03 23f40508 ma_lib...+..#... + 1cf50: 6869665f 70636900 00002e3f 0323a806 hif_pci....?.#.. + 1cf60: 00095f41 5f6d6167 7069655f 696e6469 .._A_magpie_indi + 1cf70: 72656374 696f6e5f 7461626c 655f7400 rection_table_t. + 1cf80: 00004597 03000004 47040002 01060000 ..E.....G....... + 1cf90: 04040103 000046bd 04000b0b 03000046 ......F........F + 1cfa0: cb040006 00000404 01030000 46d30400 ............F... + 1cfb0: 06000001 0f010300 0046e004 001a010a .........F...... + 1cfc0: 636d6e6f 735f6d65 6d5f696e 69740001 cmnos_mem_init.. + 1cfd0: 01039201 20029000 008e2318 008e231d .... .....#...#. + 1cfe0: 1b011663 6d6e6f73 5f6d656d 5f6d6f64 ...cmnos_mem_mod + 1cff0: 756c655f 696e7374 616c6c00 01010392 ule_install..... + 1d000: 01200290 00008e23 20008e23 3e1c0116 . .....# ..#>... + 1d010: 74626c00 000046b4 01520000 0000004b tbl...F..R.....K + 1d020: 99000200 000b7c04 012f726f 6f742f57 ......|../root/W + 1d030: 6f726b73 70616365 2f303431 325f7632 orkspace/0412_v2 + 1d040: 30322f74 67742f62 75696c64 2f6d6167 02/tgt/build/mag + 1d050: 7069655f 315f312f 696d6167 652f6d61 pie_1_1/image/ma + 1d060: 67706965 2f2e2e2f 2e2e2f2e 2e2f2e2e gpie/../../../.. + 1d070: 2f2f6275 696c642f 6d616770 69655f31 //build/magpie_1 + 1d080: 5f312f72 6f6d2f63 6d6e6f73 2f6d6973 _1/rom/cmnos/mis + 1d090: 632f7372 632f636d 6e6f735f 6d697363 c/src/cmnos_misc + 1d0a0: 2e63002f 726f6f74 2f576f72 6b737061 .c./root/Workspa + 1d0b0: 63652f30 3431325f 76323032 2f746774 ce/0412_v202/tgt + 1d0c0: 2f627569 6c642f6d 61677069 655f315f /build/magpie_1_ + 1d0d0: 312f726f 6d2f636d 6e6f732f 6d697363 1/rom/cmnos/misc + 1d0e0: 0078742d 78636320 666f7220 372e312e .xt-xcc for 7.1. + 1d0f0: 30202d4f 50543a61 6c69676e 5f696e73 0 -OPT:align_ins + 1d100: 74727563 74696f6e 733d3332 202d4f32 tructions=32 -O2 + 1d110: 202d6733 202d4f50 543a7370 61636500 -g3 -OPT:space. + 1d120: 01000000 6d830201 03000001 09040004 ....m........... + 1d130: 696e7400 05040463 68617200 07010500 int....char..... + 1d140: 00011905 00000119 03000001 26040006 ............&... + 1d150: 00000112 01030000 01320400 07707269 .........2...pri + 1d160: 6e74665f 61706900 08000001 76085f70 ntf_api.....v._p + 1d170: 72696e74 665f696e 69740000 00010b02 rintf_init...... + 1d180: 2300085f 7072696e 74660000 00013802 #.._printf....8. + 1d190: 23040004 73686f72 7420756e 7369676e #...short unsign + 1d1a0: 65642069 6e740007 02097569 6e743136 ed int....uint16 + 1d1b0: 5f740000 00017604 6c6f6e67 20756e73 _t....v.long uns + 1d1c0: 69676e65 6420696e 74000704 0975696e igned int....uin + 1d1d0: 7433325f 74000000 019a0775 6172745f t32_t......uart_ + 1d1e0: 6669666f 00080000 02080873 74617274 fifo.......start + 1d1f0: 5f696e64 65780000 00018c02 23000865 _index......#..e + 1d200: 6e645f69 6e646578 00000001 8c022302 nd_index......#. + 1d210: 086f7665 7272756e 5f657272 00000001 .overrun_err.... + 1d220: af022304 00077561 72745f61 70690020 ..#...uart_api. + 1d230: 000002c1 085f7561 72745f69 6e697400 ....._uart_init. + 1d240: 00000318 02230008 5f756172 745f6368 .....#.._uart_ch + 1d250: 61725f70 75740000 00033f02 2304085f ar_put....?.#.._ + 1d260: 75617274 5f636861 725f6765 74000000 uart_char_get... + 1d270: 03530223 08085f75 6172745f 7374725f .S.#.._uart_str_ + 1d280: 6f757400 0000035c 02230c08 5f756172 out....\.#.._uar + 1d290: 745f7461 736b0000 00010b02 2310085f t_task......#.._ + 1d2a0: 75617274 5f737461 74757300 00000318 uart_status..... + 1d2b0: 02231408 5f756172 745f636f 6e666967 .#.._uart_config + 1d2c0: 00000003 65022318 085f7561 72745f68 ....e.#.._uart_h + 1d2d0: 77696e69 74000000 036e0223 1c000300 winit....n.#.... + 1d2e0: 00020804 00077561 72745f62 6c6b0010 ......uart_blk.. + 1d2f0: 00000312 08646562 75675f6d 6f646500 .....debug_mode. + 1d300: 0000018c 02230008 62617564 00000001 .....#..baud.... + 1d310: 8c022302 085f7561 72740000 0002c102 ..#.._uart...... + 1d320: 2304085f 74780000 0001bd02 23080006 #.._tx......#... + 1d330: 000001af 01030000 03120400 04756e73 .............uns + 1d340: 69676e65 64206368 61720007 01097569 igned char....ui + 1d350: 6e74385f 74000000 031f0201 03000003 nt8_t........... + 1d360: 3d040003 00000330 04000600 00018c01 =......0........ + 1d370: 03000003 4d040002 01030000 035a0400 ....M........Z.. + 1d380: 02010300 00036304 00020103 0000036c ......c........l + 1d390: 04000300 00011904 00060000 01120103 ................ + 1d3a0: 0000037c 04000744 425f434f 4d4d414e ...|...DB_COMMAN + 1d3b0: 445f5354 52554354 000c0000 03d40863 D_STRUCT.......c + 1d3c0: 6d645f73 74720000 00037502 23000868 md_str....u.#..h + 1d3d0: 656c705f 73747200 00000375 02230408 elp_str....u.#.. + 1d3e0: 636d645f 66756e63 00000003 82022308 cmd_func......#. + 1d3f0: 00076462 675f6170 69000800 00040708 ..dbg_api....... + 1d400: 5f646267 5f696e69 74000000 010b0223 _dbg_init......# + 1d410: 00085f64 62675f74 61736b00 0000010b .._dbg_task..... + 1d420: 02230400 0a040004 756e7369 676e6564 .#......unsigned + 1d430: 20696e74 00070406 00000407 01030000 int............ + 1d440: 041a0400 0b0b0300 00042804 00060000 ..........(..... + 1d450: 04070103 00000430 04000600 00011201 .......0........ + 1d460: 03000004 3d040007 6d656d5f 61706900 ....=...mem_api. + 1d470: 14000004 ac085f6d 656d5f69 6e697400 ......_mem_init. + 1d480: 0000010b 02230008 5f6d656d 73657400 .....#.._memset. + 1d490: 00000420 02230408 5f6d656d 63707900 ... .#.._memcpy. + 1d4a0: 00000436 02230808 5f6d656d 6d6f7665 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#............... + 26d40: 095f415f 54494d45 525f5350 41434500 ._A_TIMER_SPACE. + 26d50: 00000712 09415f74 696d6572 5f740000 .....A_timer_t.. + 26d60: 00071f03 00000733 04000201 03000007 .......3........ + 26d70: 49040002 01030000 07520400 09415f48 I........R...A_H + 26d80: 414e444c 45000000 04160201 09415f54 ANDLE........A_T + 26d90: 494d4552 5f46554e 43000000 07690300 IMER_FUNC....i.. + 26da0: 00076b04 00020103 00000784 04000774 ..k............t + 26db0: 696d6572 5f617069 00140000 0803085f imer_api......._ + 26dc0: 74696d65 725f696e 69740000 00011702 timer_init...... + 26dd0: 2300085f 74696d65 725f6172 6d000000 #.._timer_arm... + 26de0: 074b0223 04085f74 696d6572 5f646973 .K.#.._timer_dis + 26df0: 61726d00 00000754 02230808 5f74696d arm....T.#.._tim + 26e00: 65725f73 6574666e 00000007 8602230c er_setfn......#. + 26e10: 085f7469 6d65725f 72756e00 00000117 ._timer_run..... + 26e20: 02231000 09424f4f 4c45414e 00000001 .#...BOOLEAN.... + 26e30: 98060000 08030103 00000810 04000600 ................ + 26e40: 00080301 03000008 1d040006 00000803 ................ + 26e50: 01030000 082a0400 07726f6d 705f6170 .....*...romp_ap + 26e60: 69001000 00089c08 5f726f6d 705f696e i......._romp_in + 26e70: 69740000 00011702 2300085f 726f6d70 it......#.._romp + 26e80: 5f646f77 6e6c6f61 64000000 08160223 _download......# + 26e90: 04085f72 6f6d705f 696e7374 616c6c00 .._romp_install. + 26ea0: 00000823 02230808 5f726f6d 705f6465 ...#.#.._romp_de + 26eb0: 636f6465 00000008 3002230c 0007726f code....0.#...ro + 26ec0: 6d5f7061 7463685f 73740010 000008f8 m_patch_st...... + 26ed0: 08637263 31360000 00019802 2300086c .crc16......#..l + 26ee0: 656e0000 00019802 2302086c 645f6164 en......#..ld_ad + 26ef0: 64720000 0001bb02 23040866 756e5f61 dr......#..fun_a + 26f00: 64647200 000001bb 02230808 7066756e ddr......#..pfun + 26f10: 00000003 5202230c 00076565 705f7265 ....R.#...eep_re + 26f20: 6469725f 61646472 00040000 092a086f dir_addr.....*.o + 26f30: 66667365 74000000 01980223 00087369 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NKNOWN....T_EEP_ + 27540: 52455400 00000eb1 03000001 98040006 RET............. + 27550: 00000f18 01030000 0f2e0400 0600000f ................ + 27560: 18010300 000f3b04 00076565 705f6170 ......;...eep_ap + 27570: 69001000 000fa408 5f656570 5f696e69 i......._eep_ini + 27580: 74000000 01170223 00085f65 65705f72 t......#.._eep_r + 27590: 65616400 00000f34 02230408 5f656570 ead....4.#.._eep + 275a0: 5f777269 74650000 000f3402 2308085f _write....4.#.._ + 275b0: 6565705f 69735f65 78697374 0000000f eep_is_exist.... + 275c0: 4102230c 00077573 625f6170 69007000 A.#...usb_api.p. + 275d0: 00125108 5f757362 5f696e69 74000000 ..Q._usb_init... + 275e0: 01170223 00085f75 73625f72 6f6d5f74 ...#.._usb_rom_t + 275f0: 61736b00 00000117 02230408 5f757362 ask......#.._usb + 27600: 5f66775f 7461736b 00000001 17022308 _fw_task......#. + 27610: 085f7573 625f696e 69745f70 68790000 ._usb_init_phy.. + 27620: 00011702 230c085f 7573625f 6570305f ....#.._usb_ep0_ + 27630: 73657475 70000000 01170223 10085f75 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........Q...VDES + 27940: 43000000 12510300 00131a04 00060000 C....Q.......... + 27950: 13250103 0000132c 04000600 0012f101 .%.....,........ + 27960: 03000013 39040002 01030000 13460400 ....9........F.. + 27970: 07766465 73635f61 70690014 000013be .vdesc_api...... + 27980: 085f696e 69740000 000ae602 2300085f ._init......#.._ + 27990: 616c6c6f 635f7664 65736300 00001332 alloc_vdesc....2 + 279a0: 02230408 5f676574 5f68775f 64657363 .#.._get_hw_desc + 279b0: 00000013 3f022308 085f7377 61705f76 ....?.#.._swap_v + 279c0: 64657363 00000013 4802230c 08705265 desc....H.#..pRe + 279d0: 73657276 65640000 00041302 23100007 served......#... + 279e0: 5f564255 46002000 00141e08 64657363 _VBUF. .....desc + 279f0: 5f6c6973 74000000 13250223 00086e65 _list....%.#..ne + 27a00: 78745f62 75660000 00141e02 23040862 xt_buf......#..b + 27a10: 75665f6c 656e6774 68000000 12f80223 uf_length......# + 27a20: 08087265 73657276 65640000 00142502 ..reserved....%. + 27a30: 230a0863 74780000 00130602 230c0003 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ID......#......3 + 29990: cd084d65 73736167 65494400 00001cb2 ..MessageID..... + 299a0: 02230008 43726564 6974436f 756e7400 .#..CreditCount. + 299b0: 00001cb2 02230208 43726564 69745369 .....#..CreditSi + 299c0: 7a650000 001cb202 2304084d 6178456e ze......#..MaxEn + 299d0: 64706f69 6e747300 0000168a 02230608 dpoints......#.. + 299e0: 5f506164 31000000 168a0223 0700120a _Pad1......#.... + 299f0: 00003464 084d6573 73616765 49440000 ..4d.MessageID.. + 29a00: 001cb202 23000853 65727669 63654944 ....#..ServiceID + 29a10: 0000001c b2022302 08436f6e 6e656374 ......#..Connect + 29a20: 696f6e46 6c616773 0000001c b2022304 ionFlags......#. + 29a30: 08446f77 6e4c696e 6b506970 65494400 .DownLinkPipeID. + 29a40: 0000168a 02230608 55704c69 6e6b5069 .....#..UpLinkPi + 29a50: 70654944 00000016 8a022307 08536572 peID......#..Ser + 29a60: 76696365 4d657461 4c656e67 74680000 viceMetaLength.. + 29a70: 00168a02 2308085f 50616431 00000016 ....#.._Pad1.... + 29a80: 8a022309 00120a00 0034ec08 4d657373 ..#......4..Mess + 29a90: 61676549 44000000 1cb20223 00085365 ageID......#..Se + 29aa0: 72766963 65494400 00001cb2 02230208 rviceID......#.. + 29ab0: 53746174 75730000 00168a02 23040845 Status......#..E + 29ac0: 6e64706f 696e7449 44000000 168a0223 ndpointID......# + 29ad0: 05084d61 784d7367 53697a65 0000001c ..MaxMsgSize.... + 29ae0: b2022306 08536572 76696365 4d657461 ..#..ServiceMeta + 29af0: 4c656e67 74680000 00168a02 2308085f Length......#.._ + 29b00: 50616431 00000016 8a022309 00120200 Pad1......#..... + 29b10: 00350508 4d657373 61676549 44000000 .5..MessageID... + 29b20: 1cb20223 00001204 00003541 084d6573 ...#......5A.Mes + 29b30: 73616765 49440000 001cb202 23000850 sageID......#..P + 29b40: 69706549 44000000 168a0223 02084372 ipeID......#..Cr + 29b50: 65646974 436f756e 74000000 168a0223 editCount......# + 29b60: 03001204 00003578 084d6573 73616765 ......5x.Message + 29b70: 49440000 001cb202 23000850 69706549 ID......#..PipeI + 29b80: 44000000 168a0223 02085374 61747573 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#.._create_pool. + 29d90: 00003704 02230808 5f616c6c 6f635f62 ..7..#.._alloc_b + 29da0: 75660000 00371102 230c085f 616c6c6f uf...7..#.._allo + 29db0: 635f6275 665f616c 69676e00 0000371e c_buf_align...7. + 29dc0: 02231008 5f667265 655f6275 66000000 .#.._free_buf... + 29dd0: 37270223 14087052 65736572 76656400 7'.#..pReserved. + 29de0: 00000413 02231800 075f4854 435f5345 .....#..._HTC_SE + 29df0: 52564943 45001c00 0038a608 704e6578 RVICE....8..pNex + 29e00: 74000000 38a60223 00085072 6f636573 t...8..#..Proces + 29e10: 73526563 764d7367 00000039 5b022304 sRecvMsg...9[.#. + 29e20: 0850726f 63657373 53656e64 42756666 .ProcessSendBuff + 29e30: 6572436f 6d706c65 74650000 00396402 erComplete...9d. + 29e40: 23080850 726f6365 7373436f 6e6e6563 #..ProcessConnec + 29e50: 74000000 39780223 0c085365 72766963 t...9x.#..Servic + 29e60: 65494400 000012f8 02231008 53657276 eID......#..Serv + 29e70: 69636546 6c616773 00000012 f8022312 iceFlags......#. + 29e80: 084d6178 5376634d 73675369 7a650000 .MaxSvcMsgSize.. + 29e90: 0012f802 23140854 7261696c 65725370 ....#..TrailerSp + 29ea0: 63436865 636b4c69 6d697400 000012f8 cCheckLimit..... + 29eb0: 02231608 53657276 69636543 74780000 .#..ServiceCtx.. + 29ec0: 00041302 23180003 000037c7 04001404 ....#.....7..... + 29ed0: 00003944 19454e44 504f494e 545f554e ..9D.ENDPOINT_UN + 29ee0: 55534544 00ffffff ff0e454e 44504f49 USED......ENDPOI + 29ef0: 4e543000 000e454e 44504f49 4e543100 NT0...ENDPOINT1. + 29f00: 010e454e 44504f49 4e543200 020e454e ..ENDPOINT2...EN + 29f10: 44504f49 4e543300 030e454e 44504f49 DPOINT3...ENDPOI + 29f20: 4e543400 040e454e 44504f49 4e543500 NT4...ENDPOINT5. + 29f30: 050e454e 44504f49 4e543600 060e454e ..ENDPOINT6...EN + 29f40: 44504f49 4e543700 070e454e 44504f49 DPOINT7...ENDPOI + 29f50: 4e543800 080e454e 44504f49 4e545f4d NT8...ENDPOINT_M + 29f60: 41580016 00094854 435f454e 44504f49 AX....HTC_ENDPOI + 29f70: 4e545f49 44000000 38ad0201 03000039 NT_ID...8......9 + 29f80: 59040002 01030000 39620400 03000001 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ersList...:..#.. + 2a190: 5f485443 5f53656e 644d7367 0000003a _HTC_SendMsg...: + 2a1a0: b0022318 085f4854 435f4765 74526573 ..#.._HTC_GetRes + 2a1b0: 65727665 64486561 64726f6f 6d000000 ervedHeadroom... + 2a1c0: 3ac60223 1c085f48 54435f4d 73675265 :..#.._HTC_MsgRe + 2a1d0: 63764861 6e646c65 72000000 28640223 cvHandler...(d.# + 2a1e0: 20085f48 54435f53 656e6444 6f6e6548 ._HTC_SendDoneH + 2a1f0: 616e646c 65720000 00285b02 2324085f andler...([.#$._ + 2a200: 4854435f 436f6e74 726f6c53 76635072 HTC_ControlSvcPr + 2a210: 6f636573 734d7367 00000039 5b022328 ocessMsg...9[.#( + 2a220: 085f4854 435f436f 6e74726f 6c537663 ._HTC_ControlSvc + 2a230: 50726f63 65737353 656e6443 6f6d706c ProcessSendCompl + 2a240: 65746500 00003964 02232c08 70526573 ete...9d.#,.pRes + 2a250: 65727665 64000000 04130223 30000768 erved......#0..h + 2a260: 6f73745f 6170705f 61726561 5f730004 ost_app_area_s.. + 2a270: 00003c6d 08776d69 5f70726f 746f636f ...# + 2b130: 04000473 686f7274 20756e73 69676e65 ...short unsigne + 2b140: 6420696e 74000702 0975696e 7431365f d int....uint16_ + 2b150: 74000000 017c046c 6f6e6720 756e7369 t....|.long unsi + 2b160: 676e6564 20696e74 00070409 75696e74 gned int....uint + 2b170: 33325f74 00000001 a0077561 72745f66 32_t......uart_f + 2b180: 69666f00 08000002 0e087374 6172745f ifo.......start_ + 2b190: 696e6465 78000000 01920223 0008656e index......#..en + 2b1a0: 645f696e 64657800 00000192 02230208 d_index......#.. + 2b1b0: 6f766572 72756e5f 65727200 000001b5 overrun_err..... + 2b1c0: 02230400 07756172 745f6170 69002000 .#...uart_api. . + 2b1d0: 0002c708 5f756172 745f696e 69740000 ...._uart_init.. + 2b1e0: 00031e02 2300085f 75617274 5f636861 ....#.._uart_cha + 2b1f0: 725f7075 74000000 03450223 04085f75 r_put....E.#.._u + 2b200: 6172745f 63686172 5f676574 00000003 art_char_get.... + 2b210: 59022308 085f7561 72745f73 74725f6f Y.#.._uart_str_o + 2b220: 75740000 00036202 230c085f 75617274 ut....b.#.._uart + 2b230: 5f746173 6b000000 01110223 10085f75 _task......#.._u + 2b240: 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_uint64_t....v.. + 2c750: 000017d4 0e414446 5f4f535f 5245534f .....ADF_OS_RESO + 2c760: 55524345 5f545950 455f4d45 4d00000e URCE_TYPE_MEM... + 2c770: 4144465f 4f535f52 45534f55 5243455f ADF_OS_RESOURCE_ + 2c780: 54595045 5f494f00 01000961 64665f6f TYPE_IO....adf_o + 2c790: 735f7265 736f7572 63655f74 7970655f s_resource_type_ + 2c7a0: 74000000 17981218 0000181e 08737461 t............sta + 2c7b0: 72740000 00178802 23000865 6e640000 rt......#..end.. + 2c7c0: 00178802 23080874 79706500 000017d4 ....#..type..... + 2c7d0: 02231000 09616466 5f6f735f 7063695f .#...adf_os_pci_ + 2c7e0: 6465765f 69645f74 00000017 05030000 dev_id_t........ + 2c7f0: 181e0400 11040000 185d0870 63690000 .........].pci.. + 2c800: 00183702 23000872 61770000 00040d02 ..7.#..raw...... + 2c810: 23000011 10000018 7c087063 69000000 #.......|.pci... + 2c820: 181e0223 00087261 77000000 040d0223 ...#..raw......# + 2c830: 00000961 64665f64 72765f68 616e646c ...adf_drv_handl + 2c840: 655f7400 0000040d 09616466 5f6f735f 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E...A_TRUE....a_ + 2ca50: 626f6f6c 5f740000 001a7d03 00001505 bool_t....}..... + 2ca60: 0400095f 5f616466 5f6f735f 646d615f ...__adf_os_dma_ + 2ca70: 6d61705f 74000000 1aa50201 0d616466 map_t........adf + 2ca80: 5f6f735f 63616368 655f7379 6e630004 _os_cache_sync.. + 2ca90: 00001b2f 0e414446 5f53594e 435f5052 .../.ADF_SYNC_PR + 2caa0: 45524541 4400000e 4144465f 53594e43 EREAD...ADF_SYNC + 2cab0: 5f505245 57524954 4500020e 4144465f _PREWRITE...ADF_ + 2cac0: 53594e43 5f504f53 54524541 4400010e SYNC_POSTREAD... + 2cad0: 4144465f 53594e43 5f504f53 54575249 ADF_SYNC_POSTWRI + 2cae0: 54450003 00096164 665f6f73 5f636163 TE....adf_os_cac + 2caf0: 68655f73 796e635f 74000000 1ac60201 he_sync_t....... + 2cb00: 09616466 5f6f735f 73697a65 5f740000 .adf_os_size_t.. + 2cb10: 001a6806 00001b4a 01096164 665f6f73 ..h....J..adf_os + 2cb20: 5f646d61 5f6d6170 5f740000 001aac03 _dma_map_t...... + 2cb30: 00001b63 04000600 00040d01 0300001a ...c............ + 2cb40: ac040006 0000040d 01020106 00001598 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...addr....i.#.. + 2cc50: 095f5f61 5f75696e 7431365f 74000000 .__a_uint16_t... + 2cc60: 12f20961 5f75696e 7431365f 74000000 ...a_uint16_t... + 2cc70: 1c9a120e 00001cfe 08657468 65725f64 .........ether_d + 2cc80: 686f7374 0000001c 69022300 08657468 host....i.#..eth + 2cc90: 65725f73 686f7374 0000001c 69022306 er_shost....i.#. + 2cca0: 08657468 65725f74 79706500 00001cac .ether_type..... + 2ccb0: 02230c00 12140000 1dbf1569 705f7665 .#.........ip_ve + 2ccc0: 7273696f 6e000000 16840100 04022300 rsion.........#. + 2ccd0: 1569705f 686c0000 00168401 04040223 .ip_hl.........# + 2cce0: 00086970 5f746f73 00000016 84022301 ..ip_tos......#. + 2ccf0: 0869705f 6c656e00 00001cac 02230208 .ip_len......#.. + 2cd00: 69705f69 64000000 1cac0223 04086970 ip_id......#..ip + 2cd10: 5f667261 675f6f66 66000000 1cac0223 _frag_off......# + 2cd20: 06086970 5f74746c 00000016 84022308 ..ip_ttl......#. + 2cd30: 0869705f 70726f74 6f000000 16840223 .ip_proto......# + 2cd40: 09086970 5f636865 636b0000 001cac02 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ap_t........adf_ + 311b0: 6f735f63 61636865 5f73796e 63000400 os_cache_sync... + 311c0: 001b320e 4144465f 53594e43 5f505245 ..2.ADF_SYNC_PRE + 311d0: 52454144 00000e41 44465f53 594e435f READ...ADF_SYNC_ + 311e0: 50524557 52495445 00020e41 44465f53 PREWRITE...ADF_S + 311f0: 594e435f 504f5354 52454144 00010e41 YNC_POSTREAD...A + 31200: 44465f53 594e435f 504f5354 57524954 DF_SYNC_POSTWRIT + 31210: 45000300 09616466 5f6f735f 63616368 E....adf_os_cach + 31220: 655f7379 6e635f74 0000001a c9020109 e_sync_t........ + 31230: 6164665f 6f735f73 697a655f 74000000 adf_os_size_t... + 31240: 1a6b0600 001b4d01 09616466 5f6f735f .k....M..adf_os_ + 31250: 646d615f 6d61705f 74000000 1aaf0300 dma_map_t....... + 31260: 001b6604 00060000 04100103 00001aaf ..f............. + 31270: 04000600 00041001 02010600 00159b01 ................ + 31280: 02010473 686f7274 20696e74 00050209 ...short int.... + 31290: 415f494e 54313600 00001ba0 095f5f61 A_INT16......__a + 312a0: 5f696e74 31365f74 0000001b ad09615f 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.#...adf_net_vla + 314b0: 6e686472 00040000 1e140874 70696400 nhdr.......tpid. + 314c0: 00001caf 02230015 7072696f 00000016 .....#..prio.... + 314d0: 87010003 02230215 63666900 00001687 .....#..cfi..... + 314e0: 01030102 23021576 69640000 001caf02 ....#..vid...... + 314f0: 040c0223 02000761 64665f6e 65745f76 ...#...adf_net_v + 31500: 69640002 00001e45 15726573 00000016 id.....E.res.... + 31510: 87010004 02230015 76616c00 00001caf .....#..val..... + 31520: 02040c02 23000012 0c00001e 81087278 ....#.........rx + 31530: 5f627566 73697a65 00000016 20022300 _bufsize.... .#. + 31540: 0872785f 6e646573 63000000 16200223 .rx_ndesc.... .# + 31550: 04087478 5f6e6465 73630000 00162002 ..tx_ndesc.... . + 31560: 23080012 0800001e a708706f 6c6c6564 #.........polled + 31570: 0000001a 9a022300 08706f6c 6c5f7774 ......#..poll_wt + 31580: 00000016 20022304 000f0000 16874000 .... .#.......@. + 31590: 001eb410 3f001246 00001edc 0869665f ....?..F.....if_ + 315a0: 6e616d65 0000001e a7022300 08646576 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_cksum_type_t... + 316b0: 1f601208 00001ff9 0874785f 636b7375 .`.......tx_cksu + 316c0: 6d000000 1fb60223 00087278 5f636b73 m......#..rx_cks + 316d0: 756d0000 001fb602 23040009 6164665f um......#...adf_ + 316e0: 6e65745f 636b7375 6d5f696e 666f5f74 net_cksum_info_t + 316f0: 0000001f d0140400 0020520e 4144465f ......... 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zsDmaQueue....C. + 38280: 08686561 64000000 42d50223 00087465 .head...B..#..te + 38290: 726d696e 61746f72 00000042 d5022304 rminator...B..#. + 382a0: 00077a73 5478446d 61517565 75650010 ..zsTxDmaQueue.. + 382b0: 00004372 08686561 64000000 42d50223 ..Cr.head...B..# + 382c0: 00087465 726d696e 61746f72 00000042 ..terminator...B + 382d0: d5022304 08786d69 7465645f 6275665f ..#..xmited_buf_ + 382e0: 68656164 00000014 3a022308 08786d69 head....:.#..xmi + 382f0: 7465645f 6275665f 7461696c 00000014 ted_buf_tail.... + 38300: 3a02230c 00020103 00004372 04000300 :.#.......Cr.... + 38310: 0042dc04 00020103 00004382 04000300 .B........C..... + 38320: 00430e04 00020103 00004392 04000201 .C........C..... + 38330: 03000043 9b040002 01030000 43a40400 ...C........C... + 38340: 06000014 3a010300 0043ad04 00020103 ....:....C...... + 38350: 000043ba 04000600 00143a01 03000043 ..C.......:....C + 38360: c3040002 01030000 43d00400 06000001 ........C....... + 38370: 15010300 0043d904 00060000 42d50103 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.....i.......... + 38c80: 0000010f 01030000 03790400 0744425f .........y...DB_ + 38c90: 434f4d4d 414e445f 53545255 4354000c COMMAND_STRUCT.. + 38ca0: 000003d1 08636d64 5f737472 00000003 .....cmd_str.... + 38cb0: 72022300 0868656c 705f7374 72000000 r.#..help_str... + 38cc0: 03720223 0408636d 645f6675 6e630000 .r.#..cmd_func.. + 38cd0: 00037f02 23080007 6462675f 61706900 ....#...dbg_api. + 38ce0: 08000004 04085f64 62675f69 6e697400 ......_dbg_init. + 38cf0: 00000108 02230008 5f646267 5f746173 .....#.._dbg_tas + 38d00: 6b000000 01080223 04000a04 0004756e k......#......un + 38d10: 7369676e 65642069 6e740007 04060000 signed int...... + 38d20: 04040103 00000417 04000b0b 03000004 ................ + 38d30: 25040006 00000404 01030000 042d0400 %............-.. + 38d40: 06000001 0f010300 00043a04 00076d65 ..........:...me + 38d50: 6d5f6170 69001400 0004a908 5f6d656d m_api......._mem + 38d60: 5f696e69 74000000 01080223 00085f6d _init......#.._m + 38d70: 656d7365 74000000 041d0223 04085f6d emset......#.._m + 38d80: 656d6370 79000000 04330223 08085f6d emcpy....3.#.._m + 38d90: 656d6d6f 76650000 00043302 230c085f emmove....3.#.._ + 38da0: 6d656d63 6d700000 00044002 2310000c memcmp....@.#... + 38db0: 72656769 73746572 5f64756d 705f7300 register_dump_s. + 38dc0: 00010300 0004a904 00020103 000004c3 ................ + 38dd0: 04000201 03000004 cc040006 0000010f ................ + 38de0: 01030000 04d50400 0d686f73 7469665f .........hostif_ + 38df0: 73000400 0005310e 4849465f 55534200 s.....1.HIF_USB. + 38e00: 000e4849 465f5043 49450001 0e484946 ..HIF_PCIE...HIF + 38e10: 5f474d41 4300020e 4849465f 50434900 _GMAC...HIF_PCI. + 38e20: 030e4849 465f4e55 4d00040e 4849465f ..HIF_NUM...HIF_ + 38e30: 4e4f4e45 00050009 415f484f 53544946 NONE....A_HOSTIF + 38e40: 00000004 e2060000 05310103 0000053f .........1.....? + 38e50: 04000600 00032d01 03000005 4c040006 ......-.....L... + 38e60: 00000189 01030000 05590400 076d6973 .........Y...mis + 38e70: 635f6170 69002400 00064908 5f737973 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0001f602 230c035f 776c616e us......#.._wlan + 43f90: 5f62616e 645f7365 74000000 01f60223 _band_set......# + 43fa0: 10035f72 6566636c 6b5f7370 6565645f .._refclk_speed_ + 43fb0: 67657400 00002327 02231403 5f6d696c get...#'.#.._mil + 43fc0: 6c697365 636f6e64 73000000 23270223 liseconds...#'.# + 43fd0: 18035f73 7973636c 6b5f6368 616e6765 .._sysclk_change + 43fe0: 00000019 bf02231c 035f636c 6f636b5f ......#.._clock_ + 43ff0: 7469636b 00000019 bf022320 000a0000 tick......# .... + 44000: 1a3e0104 00002407 04000641 5f6f6c64 .>....$....A_old + 44010: 5f696e74 725f7400 00001a3e 0a000024 _intr_t....>...$ + 44020: 14010400 00242604 00090104 00002433 .....$&.......$3 + 44030: 04000901 04000024 3c04000a 00001a3e .......$<......> + 44040: 01040000 24450400 06415f69 73725f74 ....$E...A_isr_t + 44050: 00000024 4b090104 0000245f 04000a00 ...$K.....$_.... + 44060: 0003ea01 04000024 68040009 01040000 .......$h....... + 44070: 24750400 02696e74 725f6170 69002c00 $u...intr_api.,. + 44080: 00259703 5f696e74 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...#.._wdt_disab + 44290: 6c650000 0019bf02 2308035f 7764745f le......#.._wdt_ + 442a0: 73657400 000025e9 02230c03 5f776474 set...%..#.._wdt + 442b0: 5f746173 6b000000 19bf0223 10035f77 _task......#.._w + 442c0: 64745f72 65736574 00000019 bf022314 dt_reset......#. + 442d0: 035f7764 745f6c61 73745f62 6f6f7400 ._wdt_last_boot. + 442e0: 00002654 02231800 0d040000 27590e52 ..&T.#......'Y.R + 442f0: 45545f53 55434345 53530000 0e524554 ET_SUCCESS...RET + 44300: 5f4e4f54 5f494e49 5400010e 5245545f _NOT_INIT...RET_ + 44310: 4e4f545f 45584953 5400020e 5245545f NOT_EXIST...RET_ + 44320: 4545505f 434f5252 55505400 030e5245 EEP_CORRUPT...RE + 44330: 545f4545 505f4f56 4552464c 4f570004 T_EEP_OVERFLOW.. + 44340: 0e524554 5f554e4b 4e4f574e 00050006 .RET_UNKNOWN.... + 44350: 545f4545 505f5245 54000000 26f20400 T_EEP_RET...&... + 44360: 001a1b04 000a0000 27590104 0000276f ........'Y....'o + 44370: 04000a00 00275901 04000027 7c040002 .....'Y....'|... + 44380: 6565705f 61706900 10000027 e5035f65 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.....#..ip_ttl.. + 57a60: 00199702 23080369 705f7072 6f746f00 ....#..ip_proto. + 57a70: 00001997 02230903 69705f63 6865636b .....#..ip_check + 57a80: 0000001f bf02230a 0369705f 73616464 ......#..ip_sadd + 57a90: 72000000 19300223 0c036970 5f646164 r....0.#..ip_dad + 57aa0: 64720000 00193002 23100002 6164665f dr....0.#...adf_ + 57ab0: 6e65745f 766c616e 68647200 04000021 net_vlanhdr....! + 57ac0: 24037470 69640000 001fbf02 23001570 $.tpid......#..p + 57ad0: 72696f00 00001997 01000302 23021563 rio.........#..c + 57ae0: 66690000 00199701 03010223 02157669 fi.........#..vi + 57af0: 64000000 1fbf0204 0c022302 00026164 d.........#...ad + 57b00: 665f6e65 745f7669 64000200 00215515 f_net_vid....!U. + 57b10: 72657300 00001997 01000402 23001576 res.........#..v + 57b20: 616c0000 001fbf02 040c0223 0000120c al.........#.... + 57b30: 00002191 0372785f 62756673 697a6500 ..!..rx_bufsize. + 57b40: 00001930 02230003 72785f6e 64657363 ...0.#..rx_ndesc + 57b50: 00000019 30022304 0374785f 6e646573 ....0.#..tx_ndes + 57b60: 63000000 19300223 08001208 000021b7 c....0.#......!. + 57b70: 03706f6c 6c656400 00001daa 02230003 .polled......#.. + 57b80: 706f6c6c 5f777400 00001930 02230400 poll_wt....0.#.. + 57b90: 07000019 97400000 21c4083f 00124600 .....@..!..?..F. + 57ba0: 0021ec03 69665f6e 616d6500 000021b7 .!..if_name...!. + 57bb0: 02230003 6465765f 61646472 0000001f .#..dev_addr.... + 57bc0: 7c022340 00140400 00222310 4144465f |.#@....."#.ADF_ + 57bd0: 4f535f44 4d415f4d 41534b5f 33324249 OS_DMA_MASK_32BI + 57be0: 54000010 4144465f 4f535f44 4d415f4d T...ADF_OS_DMA_M + 57bf0: 41534b5f 36344249 54000100 06616466 ASK_64BIT....adf + 57c00: 5f6f735f 646d615f 6d61736b 5f740000 _os_dma_mask_t.. + 57c10: 0021ec02 6164665f 646d615f 696e666f .!..adf_dma_info + 57c20: 00080000 22700364 6d615f6d 61736b00 ...."p.dma_mask. + 57c30: 00002223 02230003 73675f6e 73656773 .."#.#..sg_nsegs + 57c40: 00000019 30022304 00140400 0022c610 ....0.#......".. + 57c50: 4144465f 4e45545f 434b5355 4d5f4e4f ADF_NET_CKSUM_NO + 57c60: 4e450000 10414446 5f4e4554 5f434b53 NE...ADF_NET_CKS + 57c70: 554d5f54 43505f55 44505f49 50763400 UM_TCP_UDP_IPv4. + 57c80: 01104144 465f4e45 545f434b 53554d5f ..ADF_NET_CKSUM_ + 57c90: 5443505f 5544505f 49507636 00020006 TCP_UDP_IPv6.... + 57ca0: 6164665f 6e65745f 636b7375 6d5f7479 adf_net_cksum_ty + 57cb0: 70655f74 00000022 70120800 00230903 pe_t..."p....#.. + 57cc0: 74785f63 6b73756d 00000022 c6022300 tx_cksum..."..#. + 57cd0: 0372785f 636b7375 6d000000 22c60223 .rx_cksum..."..# + 57ce0: 04000661 64665f6e 65745f63 6b73756d ...adf_net_cksum + 57cf0: 5f696e66 6f5f7400 000022e0 14040000 _info_t..."..... + 57d00: 23621041 44465f4e 45545f54 534f5f4e #b.ADF_NET_TSO_N + 57d10: 4f4e4500 00104144 465f4e45 545f5453 ONE...ADF_NET_TS + 57d20: 4f5f4950 56340001 10414446 5f4e4554 O_IPV4...ADF_NET + 57d30: 5f54534f 5f414c4c 00020006 6164665f _TSO_ALL....adf_ + 57d40: 6e65745f 74736f5f 74797065 5f740000 net_tso_type_t.. + 57d50: 00232312 10000023 b603636b 73756d5f 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f_net_cmd_mcaddr + 57e60: 00030400 0024ab03 6e656c65 6d000000 .....$..nelem... + 57e70: 19300223 00036d63 61737400 00002466 .0.#..mcast...$f + 57e80: 02230400 06616466 5f6e6574 5f636d64 .#...adf_net_cmd + 57e90: 5f6c696e 6b5f696e 666f5f74 0000001f _link_info_t.... + 57ea0: 23066164 665f6e65 745f636d 645f706f #.adf_net_cmd_po + 57eb0: 6c6c5f69 6e666f5f 74000000 21910661 ll_info_t...!..a + 57ec0: 64665f6e 65745f63 6d645f63 6b73756d df_net_cmd_cksum + 57ed0: 5f696e66 6f5f7400 00002309 06616466 _info_t...#..adf + 57ee0: 5f6e6574 5f636d64 5f72696e 675f696e _net_cmd_ring_in + 57ef0: 666f5f74 00000021 55066164 665f6e65 fo_t...!U.adf_ne + 57f00: 745f636d 645f646d 615f696e 666f5f74 t_cmd_dma_info_t + 57f10: 00000022 3a066164 665f6e65 745f636d ...":.adf_net_cm + 57f20: 645f7669 645f7400 00001fbf 06616466 d_vid_t......adf + 57f30: 5f6e6574 5f636d64 5f6f6666 6c6f6164 _net_cmd_offload + 57f40: 5f636170 5f740000 00237a06 6164665f _cap_t...#z.adf_ + 57f50: 6e65745f 636d645f 73746174 735f7400 net_cmd_stats_t. + 57f60: 000023b6 06616466 5f6e6574 5f636d64 ..#..adf_net_cmd + 57f70: 5f6d6361 6464725f 74000000 24740f61 _mcaddr_t...$t.a + 57f80: 64665f6e 65745f63 6d645f6d 63617374 df_net_cmd_mcast + 57f90: 5f636170 00040000 25ed1041 44465f4e _cap....%..ADF_N + 57fa0: 45545f4d 43415354 5f535550 00001041 ET_MCAST_SUP...A + 57fb0: 44465f4e 45545f4d 43415354 5f4e4f54 DF_NET_MCAST_NOT + 57fc0: 53555000 01000661 64665f6e 65745f63 SUP....adf_net_c + 57fd0: 6d645f6d 63617374 5f636170 5f740000 md_mcast_cap_t.. + 57fe0: 0025a518 03040000 26bf036c 696e6b5f .%......&..link_ + 57ff0: 696e666f 00000024 ab022300 03706f6c info...$..#..pol + 58000: 6c5f696e 666f0000 0024c802 23000363 l_info...$..#..c + 58010: 6b73756d 5f696e66 6f000000 24e50223 ksum_info...$..# + 58020: 00037269 6e675f69 6e666f00 00002503 ..ring_info...%. + 58030: 02230003 646d615f 696e666f 00000025 .#..dma_info...% + 58040: 20022300 03766964 00000025 3c022300 .#..vid...%<.#. + 58050: 036f6666 6c6f6164 5f636170 00000025 .offload_cap...% + 58060: 53022300 03737461 74730000 00257202 S.#..stats...%r. + 58070: 2300036d 63617374 5f696e66 6f000000 #..mcast_info... + 58080: 258b0223 00036d63 6173745f 63617000 %..#..mcast_cap. + 58090: 000025ed 02230000 14040000 27161041 ..%..#......'..A + 580a0: 44465f4e 4255465f 52585f43 4b53554d DF_NBUF_RX_CKSUM + 580b0: 5f4e4f4e 45000010 4144465f 4e425546 _NONE...ADF_NBUF + 580c0: 5f52585f 434b5355 4d5f4857 00011041 _RX_CKSUM_HW...A + 580d0: 44465f4e 4255465f 52585f43 4b53554d DF_NBUF_RX_CKSUM + 580e0: 5f554e4e 45434553 53415259 00020006 _UNNECESSARY.... + 580f0: 6164665f 6e627566 5f72785f 636b7375 adf_nbuf_rx_cksu + 58100: 6d5f7479 70655f74 00000026 bf120800 m_type_t...&.... + 58110: 00275603 72657375 6c740000 00271602 .'V.result...'.. + 58120: 23000376 616c0000 00193002 23040012 #..val....0.#... + 58130: 08000027 86037479 70650000 00236202 ...'..type...#b. + 58140: 2300036d 73730000 001fbf02 23040368 #..mss......#..h + 58150: 64725f6f 66660000 00199702 23060002 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S_ENOENT...A_STA + 58260: 5455535f 454e4f4d 454d0003 10415f53 TUS_ENOMEM...A_S + 58270: 54415455 535f4549 4e56414c 00041041 TATUS_EINVAL...A + 58280: 5f535441 5455535f 45494e50 524f4752 _STATUS_EINPROGR + 58290: 45535300 0510415f 53544154 55535f45 ESS...A_STATUS_E + 582a0: 4e4f5453 55505000 0610415f 53544154 NOTSUPP...A_STAT + 582b0: 55535f45 42555359 00071041 5f535441 US_EBUSY...A_STA + 582c0: 5455535f 45324249 47000810 415f5354 TUS_E2BIG...A_ST + 582d0: 41545553 5f454144 44524e4f 54415641 ATUS_EADDRNOTAVA + 582e0: 494c0009 10415f53 54415455 535f454e IL...A_STATUS_EN + 582f0: 58494f00 0a10415f 53544154 55535f45 XIO...A_STATUS_E + 58300: 4641554c 54000b10 415f5354 41545553 FAULT...A_STATUS + 58310: 5f45494f 000c0006 615f7374 61747573 _EIO....a_status + 58320: 5f740000 0028490a 0000293e 010a0000 _t...(I...)>.... + 58330: 01f50109 01066164 665f6e62 75665f74 ......adf_nbuf_t + 58340: 00000027 c5140400 0029a310 4144465f ...'.....)..ADF_ + 58350: 4f535f44 4d415f54 4f5f4445 56494345 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te_page_size.... + 7d1d0: f2050300 4e87ec01 04587468 616c5f6d ....N....Xthal_m + 7d1e0: 6d755f6d 696e5f70 74655f70 6167655f mu_min_pte_page_ + 7d1f0: 73697a65 00000000 f2050300 4e87f001 size........N... + 7d200: 04587468 616c5f69 746c625f 7761795f .Xthal_itlb_way_ + 7d210: 62697473 00000001 f6050300 500b6a01 bits........P.j. + 7d220: 04587468 616c5f69 746c625f 77617973 .Xthal_itlb_ways + 7d230: 00000001 f6050300 4e87f401 04587468 ........N....Xth + 7d240: 616c5f69 746c625f 6172665f 77617973 al_itlb_arf_ways + 7d250: 00000001 f6050300 500b6b01 04587468 ........P.k..Xth + 7d260: 616c5f64 746c625f 7761795f 62697473 al_dtlb_way_bits + 7d270: 00000001 f6050300 500b6c01 04587468 ........P.l..Xth + 7d280: 616c5f64 746c625f 77617973 00000001 al_dtlb_ways.... + 7d290: f6050300 4e87f501 04587468 616c5f64 ....N....Xthal_d + 7d2a0: 746c625f 6172665f 77617973 00000001 tlb_arf_ways.... + 7d2b0: f6050300 500b6d01 04587468 616c5f6e ....P.m..Xthal_n + 7d2c0: 756d5f69 6e737472 6f6d0000 0001f605 um_instrom...... + 7d2d0: 0300500b 6e010458 7468616c 5f6e756d ..P.n..Xthal_num + 7d2e0: 5f696e73 7472616d 00000001 f6050300 _instram........ + 7d2f0: 4e87f601 04587468 616c5f6e 756d5f64 N....Xthal_num_d + 7d300: 61746172 6f6d0000 0001f605 0300500b atarom........P. + 7d310: 6f010458 7468616c 5f6e756d 5f646174 o..Xthal_num_dat + 7d320: 6172616d 00000001 f6050300 4e87f701 aram........N... + 7d330: 04587468 616c5f6e 756d5f78 6c6d6900 .Xthal_num_xlmi. + 7d340: 000001f6 05030050 0b700103 000000e2 .......P.p...... + 7d350: 06000009 e6040000 09f80700 00030000 ................ + 7d360: 09eb0300 0000e206 000009fd 0400000a ................ + 7d370: 0f070000 04587468 616c5f69 6e737472 .....Xthal_instr + 7d380: 6f6d5f76 61646472 00000009 f8050300 om_vaddr........ + 7d390: 4e87fc01 04587468 616c5f69 6e737472 N....Xthal_instr + 7d3a0: 6f6d5f70 61646472 00000009 f8050300 om_paddr........ + 7d3b0: 4e880001 04587468 616c5f69 6e737472 N....Xthal_instr + 7d3c0: 6f6d5f73 697a6500 000009f8 0503004e om_size........N + 7d3d0: 88040104 58746861 6c5f696e 73747261 ....Xthal_instra + 7d3e0: 6d5f7661 64647200 000009f8 0503004e m_vaddr........N + 7d3f0: 88080104 58746861 6c5f696e 73747261 ....Xthal_instra + 7d400: 6d5f7061 64647200 000009f8 0503004e m_paddr........N + 7d410: 880c0104 58746861 6c5f696e 73747261 ....Xthal_instra + 7d420: 6d5f7369 7a650000 0009f805 03004e88 m_size........N. + 7d430: 10010458 7468616c 5f646174 61726f6d ...Xthal_datarom + 7d440: 5f766164 64720000 0009f805 03004e88 _vaddr........N. + 7d450: 14010458 7468616c 5f646174 61726f6d ...Xthal_datarom + 7d460: 5f706164 64720000 0009f805 03004e88 _paddr........N. + 7d470: 18010458 7468616c 5f646174 61726f6d ...Xthal_datarom + 7d480: 5f73697a 65000000 09f80503 004e881c _size........N.. + 7d490: 01045874 68616c5f 64617461 72616d5f ..Xthal_dataram_ + 7d4a0: 76616464 72000000 09f80503 004e8820 vaddr........N. + 7d4b0: 01045874 68616c5f 64617461 72616d5f ..Xthal_dataram_ + 7d4c0: 70616464 72000000 09f80503 004e8824 paddr........N.$ + 7d4d0: 01045874 68616c5f 64617461 72616d5f ..Xthal_dataram_ + 7d4e0: 73697a65 00000009 f8050300 4e882801 size........N.(. + 7d4f0: 04587468 616c5f78 6c6d695f 76616464 .Xthal_xlmi_vadd + 7d500: 72000000 09f80503 004e882c 01045874 r........N.,..Xt + 7d510: 68616c5f 786c6d69 5f706164 64720000 hal_xlmi_paddr.. + 7d520: 0009f805 03004e88 30010458 7468616c ......N.0..Xthal + 7d530: 5f786c6d 695f7369 7a650000 0009f805 _xlmi_size...... + 7d540: 03004e88 34010458 7468616c 5f686176 ..N.4..Xthal_hav + 7d550: 655f6363 6f756e74 00000001 f6050300 e_ccount........ + 7d560: 4e87f801 04587468 616c5f6e 756d5f63 N....Xthal_num_c + 7d570: 636f6d70 61726500 000001f6 0503004e compare........N + 7d580: 87f90100 00000000 cf000200 002e2004 .............. . + 7d590: 010001c1 59008e64 28008e65 5f2f686f ....Y..d(..e_/ho + 7d5a0: 6d652f63 7573746f 6d65722f 74726565 me/customer/tree + 7d5b0: 2f52422d 32303037 2e322f74 6f6f6c73 /RB-2007.2/tools + 7d5c0: 2f737774 6f6f6c73 2d783836 2d6c696e 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...........!.... + 20: 000200a2 008e102a 00000000 00000008 .......*........ + 30: 004e8000 00000010 00002804 008e0c20 .N........(.... + 40: 00000006 00020082 008e0c26 00000000 ...........&.... + 50: 00000008 008e0f20 00000006 00020082 ....... ........ + 60: 008e0f26 00000000 00000008 008e0d40 ...&...........@ + 70: 00000006 00020082 008e0d46 00000000 ...........F.... + 80: 00000008 008e0000 00000003 00020082 ................ + 90: 008e0003 00000000 00002808 008e0004 ..........(..... + a0: 00000018 00002801 008e0020 00000021 ......(.... ...! + b0: 00000082 008e0041 00000000 00004808 .......A......H. + c0: 008e0050 00000008 000001a2 008e0058 ...P...........X + d0: 00000005 00000082 008e005d 00000015 ...........].... + e0: 000000a2 008e0072 0000000a 000000a2 .......r........ + f0: 008e007c 00000001 00000008 008e007d ...|...........} + 100: 00000017 000000a2 008e0094 0000000c ................ + 110: 000000a2 008e00a0 0000000e 000000a2 ................ + 120: 008e00ae 00000002 00000008 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b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/output/fpga/rom.fpga.addrs.ld new file mode 100755 index 0000000..bd322c6 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/output/fpga/rom.fpga.addrs.ld @@ -0,0 +1,62 @@ +PROVIDE ( _indir_tbl = 0x00500000 ); +PROVIDE ( memcpy = 0x008e6a28 ); +PROVIDE ( memset = 0x008e6d0c ); +PROVIDE ( __divsi3 = 0x008e685c ); +PROVIDE ( __udivsi3 = 0x008e6910 ); +PROVIDE ( __umodsi3 = 0x008e6960 ); +PROVIDE ( __modsi3 = 0x008e68c4 ); +PROVIDE ( athos_interrupt_init = 0x008e1614 ); +PROVIDE ( athos_unblock_all_intrlvl = 0x008e1460 ); +PROVIDE ( athos_interrupt_handler = 0x008e1604 ); +PROVIDE ( _xtos_set_interrupt_handler = 0x008e1230 ); +PROVIDE ( generic_hif_module_install = 0x008e1548 ); +PROVIDE ( htc_module_install = 0x008e536c ); +PROVIDE ( buf_pool_module_install = 0x008e6128 ); +PROVIDE ( vbuf_module_install = 0x008e4e24 ); +PROVIDE ( vdesc_module_install = 0x008e4ed4 ); +PROVIDE ( strcmp = 0x008e6424 ); +PROVIDE ( strlen = 0x008e65d4 ); +PROVIDE ( strcpy = 0x008e653c ); +PROVIDE ( strncpy = 0x008e6700 ); +PROVIDE ( Xthal_num_ccompare = 0x004e87e9 ); +PROVIDE ( cticks = 0x0050095c ); +PROVIDE ( UsbDeviceDescriptor = 0x004e0100 ); +PROVIDE ( String00Descriptor = 0x004e01a0 ); +PROVIDE ( String10Descriptor = 0x004e01b0 ); +PROVIDE ( String20Descriptor = 0x004e01c0 ); +PROVIDE ( String30Descriptor = 0x004e01e0 ); +PROVIDE ( HIFusb_DescTraceDump = 0x008e3780 ); +PROVIDE ( xthal_get_intenable = 0x008e6844 ); +PROVIDE ( xthal_set_intenable = 0x008e6854 ); +PROVIDE ( xthal_get_interrupt = 0x008e684c ); +PROVIDE ( xthal_get_ccompare = 0x008e6834 ); +PROVIDE ( xthal_set_ccompare = 0x008e6824 ); +PROVIDE ( xthal_get_ccount = 0x008e681c ); +PROVIDE ( Xthal_num_ccompare = 0x004e87e9 ); +PROVIDE ( zfDmaReclaimPacket = 0x008e5bf0 ); +PROVIDE ( zfDmaPutPacket = 0x008e5c84 ); +PROVIDE ( zfDmaGetPacket = 0x008e5bb4 ); +PROVIDE ( fwd_init = 0x008e5d3c ); +PROVIDE ( usbFifoConf = 0x00500aa4 ); +PROVIDE ( _HIFusb_isr_handler = 0x008e367c ); +PROVIDE ( mUsbFIFOConfig = 0x008e47f8 ); +PROVIDE ( mUsbEPMxPtSzHigh = 0x008e4818 ); +PROVIDE ( mUsbEPMxPtSzLow = 0x008e4840 ); +PROVIDE ( mUsbEPinHighBandSet = 0x008e4864 ); +PROVIDE ( mUsbFIFOConfig = 0x008e47f8 ); +PROVIDE ( mUsbFIFOMap = 0x008e47d8 ); +PROVIDE ( mUsbEPMap = 0x008e47bc ); +PROVIDE ( u8UsbInterfaceValue = 0x00500ad0 ); +PROVIDE ( u8UsbConfigValue = 0x00500ace ); +PROVIDE ( u8UsbInterfaceAlternateSetting = 0x00500ad2 ); +PROVIDE ( ControlCmd = 0x00500a98 ); +PROVIDE ( vUsbFIFO_EPxCfg_HS = 0x008e48b0 ); +PROVIDE ( vUsbClrEPx = 0x008e3868 ); +PROVIDE ( bSet_configuration = 0x008e3aec ); +PROVIDE ( eUsbCxFinishAction = 0x00500ac4 ); +PROVIDE ( pci_sc = 0x00500708 ); +PROVIDE ( __pci_reap_recv = 0x008e3180 ); +PROVIDE ( __pci_reap_xmitted = 0x008e3154 ); +PROVIDE ( _HIFusb_start = 0x008e3438 ); +PROVIDE ( g_hifUSBCtx = 0x00500a54 ); +PROVIDE ( _HIFusb_return_recv_buf = 0x008e3614 ); diff --git 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/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvbuf.a(vbuf.o) + .lit4 0x004e85d0 0x14 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvdesc.a(vdesc.o) + .lit4 0x004e85e4 0x30 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhtc.a(htc.o) + .lit4 0x004e8614 0x50 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libdma.a(dma_engine.o) + .lit4 0x004e8664 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libdma.a(desc.o) + .lit4 0x004e8668 0x54 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libfwd.a(fwd.o) + .lit4 0x004e86bc 0x1c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libbuf_pool.a(buf_pool_static.o) + .lit4 0x004e86d8 0x10 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-sethandler.o) + .lit4 0x004e86e8 0x4 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(windowspill_asm.o) + .lit4 0x004e86ec 0x10 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strcmp.o) + .lit4 0x004e86fc 0x8 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strncmp.o) + *(.gnu.linkonce.lit4.*) + 0x004e8704 _lit4_end = (.) + +.ResetVector.literal + 0x004e8704 0x0 + 0x004e8704 _ResetVector_literal_start = (.) + *(.ResetVector.literal) + 0x004e8704 _ResetVector_literal_end = (.) + +.dport0.stack 0x0053f7f0 0x800 + 0x0053f7f0 _reserved_stack_start = . + 0x0053f7f0 _stack_sentry = ALIGN (0x8) + 0x0053fff0 . = (. + 0x800) + *fill* 0x0053f7f0 0x800 00 + *fill* 0x0053fff0 0x0 00 + *fill* 0x0053fff0 0x0 00 + *fill* 0x0053fff0 0x0 00 + *fill* 0x0053fff0 0x0 00 + 0x0053fff0 __stack = . + 0x0053fff0 _reserved_stack_end = . + +.dport0.usb_in_rom + 0x004e0100 0xec + 0x004e0100 _reserved_rom_data_start = . + 0x004e0100 _reserved_rom_data_end = . + 0x004e0260 _data_start_in_rom = 0x160 + .dport0.usb_in_rom + 0x004e0100 0xec /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_table.o) + 0x004e0100 UsbDeviceDescriptor + 0x004e01c0 String20Descriptor + 0x004e01b0 String10Descriptor + 0x004e0120 u8HSConfigDescriptor01 + 0x004e0160 u8FSConfigDescriptor01 + 0x004e01a0 String00Descriptor + 0x004e01e0 String30Descriptor + +.dport0.data 0x00500000 0x400 + 0x00500000 _reserved_data_start = 0x0 + 0x00500000 _indir_tbl = 0x0 + 0x00500400 . = 0x400 + *fill* 0x00500000 0x400 00 + *fill* 0x00500400 0x0 00 + *fill* 0x00500400 0x0 00 + *fill* 0x00500400 0x0 00 + *fill* 0x00500400 0x0 00 + 0x00500400 _reserved_data_end = . + 0x00500400 _dport0_data_start = (.) + *(.dport0.data) + *(.dport.data) + 0x00500400 _dport0_data_end = (.) + +.dport0.bss 0x00500400 0x0 + 0x00500400 . = ALIGN (0x8) + 0x00500400 _dport0_bss_start = (.) + *(.dport0.bss) + 0x00500400 . = ALIGN (0x8) + 0x00500400 _dport0_bss_end = (.) + +.dram0.rodata 0x004e8704 0x0 + 0x004e8704 _dram0_rodata_start = (.) + *(.dram0.rodata) + *(.dram.rodata) + 0x004e8704 _dram0_rodata_end = (.) + +.rodata 0x004e8710 0x934 + 0x004e8710 _rodata_start = (.) + *(.rodata) + .rodata 0x004e8710 0x30 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + 0x004e8710 _rom_store_table + .rodata 0x004e8740 0x50 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_clock.o) + 0x004e8740 cmnos_clocking_table + .rodata 0x004e8790 0x98 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(misc.o) + 0x004e87a4 Xthal_have_loops + 0x004e87d6 Xthal_have_mimic_cacheattr + 0x004e87d8 Xthal_mmu_rings + 0x004e87a3 Xthal_have_density + 0x004e8798 Xthal_rev_no + 0x004e87a1 Xthal_memory_order + 0x004e8824 Xthal_xlmi_size + 0x004e87ac Xthal_have_highlevel_interrupts + 0x004e87cc Xthal_hw_min_version_major + 0x004e87a9 Xthal_have_exceptions + 0x004e87c4 Xthal_hw_release_major + 0x004e87ec Xthal_instrom_vaddr + 0x004e87f4 Xthal_instrom_size + 0x004e8820 Xthal_xlmi_paddr + 0x004e87d9 Xthal_mmu_ca_bits + 0x004e87d7 Xthal_have_tlbs + 0x004e87f0 Xthal_instrom_paddr + 0x004e87a2 Xthal_have_windowed + 0x004e87e9 Xthal_num_ccompare + 0x004e87a0 Xthal_num_aregs_log2 + 0x004e8818 Xthal_dataram_size + 0x004e8814 Xthal_dataram_paddr + 0x004e8790 Xthal_release_major + 0x004e8810 Xthal_dataram_vaddr + 0x004e87d0 Xthal_hw_max_version_major + 0x004e87e6 Xthal_num_instram + 0x004e87e5 Xthal_dtlb_ways + 0x004e87d4 Xthal_have_spanning_way + 0x004e880c Xthal_datarom_size + 0x004e87a8 Xthal_have_mul16 + 0x004e87b0 Xthal_have_s32c1i + 0x004e87e4 Xthal_itlb_ways + 0x004e87c0 Xthal_hw_configid1 + 0x004e87ab Xthal_have_interrupts + 0x004e87af Xthal_have_release_sync + 0x004e87c8 Xthal_hw_release_name + 0x004e87fc Xthal_instram_paddr + 0x004e87b2 Xthal_have_pif + 0x004e87a6 Xthal_have_minmax + 0x004e879c Xthal_num_aregs + 0x004e87ad Xthal_have_nmi + 0x004e87b8 Xthal_build_unique_id + 0x004e8804 Xthal_datarom_vaddr + 0x004e8808 Xthal_datarom_paddr + 0x004e87d5 Xthal_have_identity_map + 0x004e87aa Xthal_xea_version + 0x004e87dc Xthal_mmu_max_pte_page_size + 0x004e87ae Xthal_have_prid + 0x004e87e0 Xthal_mmu_min_pte_page_size + 0x004e8800 Xthal_instram_size + 0x004e881c Xthal_xlmi_vaddr + 0x004e87a5 Xthal_have_nsa + 0x004e87e8 Xthal_have_ccount + 0x004e87bc Xthal_hw_configid0 + 0x004e87b4 Xthal_num_writebuffer_entries + 0x004e8794 Xthal_release_name + 0x004e87f8 Xthal_instram_vaddr + 0x004e87e7 Xthal_num_dataram + 0x004e87b1 Xthal_have_threadptr + 0x004e87a7 Xthal_have_sext + *fill* 0x004e8828 0x8 00 + .rodata 0x004e8830 0x20 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(interrupts--intlevel.o) + 0x004e8830 Xthal_intlevel + *(.rodata.*) + .rodata.str1.4 + 0x004e8850 0x22a /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + *fill* 0x004e8a7a 0x2 00 + .rodata.str1.4 + 0x004e8a7c 0x5d /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_allocram.o) + *fill* 0x004e8ad9 0x3 00 + .rodata.str1.4 + 0x004e8adc 0x1e /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_eeprom.o) + *fill* 0x004e8afa 0x2 00 + .rodata.str1.4 + 0x004e8afc 0x98 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_misc.o) + 0x9c (size before relaxing) + .rodata.str1.4 + 0x004e8b94 0x3b /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_printf.o) + *fill* 0x004e8bcf 0x1 00 + .rodata.str1.4 + 0x004e8bd0 0x82 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_rompatch.o) + *fill* 0x004e8c52 0x2 00 + .rodata.str1.4 + 0x004e8c54 0x71 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(hif_pci.o) + *fill* 0x004e8cc5 0x3 00 + .rodata.str1.4 + 0x004e8cc8 0xc2 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(HIF_usb.o) + *fill* 0x004e8d8a 0x2 00 + .rodata.str1.4 + 0x004e8d8c 0x11e /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_api.o) + *fill* 0x004e8eaa 0x2 00 + .rodata.str1.4 + 0x004e8eac 0x22 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libdma.a(dma_engine.o) + 0x27 (size before relaxing) + *fill* 0x004e8ece 0x2 00 + .rodata.str1.4 + 0x004e8ed0 0x151 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libfwd.a(fwd.o) + *fill* 0x004e9021 0x3 00 + .rodata.str1.4 + 0x004e9024 0x10 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(misc.o) + *(.gnu.linkonce.r.*) + *(.rodata1) + 0x004e9034 __XT_EXCEPTION_TABLE__ = (.) + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + 0x004e9034 . = ALIGN (0x4) + 0x004e9034 _bss_table_start = (.) + 0x004e9034 0x4 LONG 0x500400 _dport0_bss_start + 0x004e9038 0x4 LONG 0x500400 _dport0_bss_end + 0x004e903c 0x4 LONG 0x500950 _bss_start + 0x004e9040 0x4 LONG 0x500b78 _bss_end + 0x004e9044 _bss_table_end = (.) + 0x004e9044 _rodata_end = (.) + +.dram0.literal 0x004e9044 0x0 + 0x004e9044 _dram0_literal_start = (.) + *(.dram0.literal) + *(.dram.literal) + 0x004e9044 _dram0_literal_end = (.) + +.dram0.data 0x00500400 0x0 + 0x00500400 _dram0_data_start = (.) + *(.dram0.data) + *(.dram.data) + 0x00500400 _dram0_data_end = (.) + +.data 0x00500400 0x550 + 0x00500400 _data_start = (.) + *(.data) + .data 0x00500400 0x100 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(user-vector.o) + 0x00500400 _xtos_exc_handler_table + .data 0x00500500 0x138 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(interrupt-table.o) + 0x00500500 _xtos_enabled + 0x00500500 _xtos_intstruct + 0x00500508 _xtos_interrupt_table + 0x005005a0 _xtos_interrupt_mask_table + 0x00500504 _xtos_vpri_enabled + *fill* 0x00500638 0x8 00 + .data 0x00500640 0xb8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + 0x00500640 basic_ROM_module_table + .data 0x005006f8 0x8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_misc.o) + 0x005006fc assprint + 0x005006f8 assloop + .data 0x00500700 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_printf.o) + 0x00500700 _putc + .data 0x00500704 0x4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_rompatch.o) + 0x00500704 patch_addr + .data 0x00500708 0xc /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(hif_pci.o) + 0x00500708 pci_sc + *fill* 0x00500714 0xc 00 + .data 0x00500720 0x44 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_api.o) + 0x00500720 TestPatn0 + 0x00500730 TestPatn1 + *fill* 0x00500764 0xc 00 + .data 0x00500770 0x4c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_table.o) + 0x00500780 u8OtherSpeedConfigDescriptorEX + 0x00500770 u8DeviceQualifierDescriptorEX + *fill* 0x005007bc 0x4 00 + .data 0x005007c0 0x90 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(dma_lib.o) + 0x005007c0 eng_q + .data 0x00500850 0x100 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-table.o) + 0x00500850 _xtos_c_handler_table + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.eh_frame) + *crtbegin.o(.ctors) + *(EXCLUDE_FILE(*crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + *crtbegin.o(.dtors) + *(EXCLUDE_FILE(*crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + 0x00500950 __XT_EXCEPTION_DESCS__ = (.) + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + 0x00500950 __XT_EXCEPTION_DESCS_END__ = (.) + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + 0x00500950 _data_end = (.) + +.bss 0x00500950 0x2a8 + 0x00500950 . = ALIGN (0x8) + 0x00500950 _bss_start = (.) + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + .bss 0x00500950 0x2 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + *fill* 0x00500952 0x2 00 + .bss 0x00500954 0x8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_allocram.o) + 0x00500954 allocram_current_addr + 0x00500958 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/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-handler-level3.o) + 0x008e12f4 _Level3FromVector + 0x008e13a2 _Level3HandlerLabel + *fill* 0x008e13a2 0x2 00 + .text 0x008e13a4 0x826 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + 0x008e1604 athos_interrupt_handler + 0x008e18c8 turn_off_rc + 0x008e167c athos_init + 0x008e16e8 read_usb_conf + 0x008e178c set_pci_conf + 0x008e1614 athos_interrupt_init + 0x008e1548 generic_hif_module_install + 0x008e16b0 _read_usb_desc + 0x008e13f8 Magpie_fatal_exception_handler + 0x008e1468 athos_restore_intrlvl + 0x008e18fc bootentry + 0x008e1bac main + 0x008e189c pci_gmac_bootload + 0x008e1574 athos_indirection_table_install + 0x008e1860 bootload + 0x008e13a4 post + 0x008e1454 athos_block_all_intrlvl + 0x008e1460 athos_unblock_all_intrlvl + *fill* 0x008e1bca 0x2 00 + .text 0x008e1bcc 0x78 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_allocram.o) + 0x008e1c30 cmnos_allocram_module_install + 0x008e1bdc cmnos_allocram + 0x008e1c0c cmnos_allocram_debug + 0x008e1bcc cmnos_allocram_init + .text 0x008e1c44 0xf2 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_clock.o) + 0x008e1c74 cmnos_refclk_speed_get + 0x008e1c80 cmnos_uart_frequency + 0x008e1c88 cmnos_sysclk_change + 0x008e1c98 cmnos_wlan_band_set + 0x008e1cdc cmnos_tick + 0x008e1ca0 cmnos_pll_init + 0x008e1c44 cmnos_delay_us + 0x008e1c90 cmnos_clockregs_init + 0x008e1c64 cmnos_milliseconds + 0x008e1d04 cmnos_clock_module_install + 0x008e1ca8 cmnos_clock_init + *fill* 0x008e1d36 0x2 00 + .text 0x008e1d38 0x3e5 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_eeprom.o) + 0x008e1dbc cmnos_eep_is_exist + 0x008e1d38 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/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvbuf.a(vbuf.o) + 0x008e4e10 _vbuf_free_vbuf + 0x008e4e24 vbuf_module_install + 0x008e4df0 _vbuf_alloc_vbuf + 0x008e4db4 _vbuf_init + .text 0x008e4e38 0xb5 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvdesc.a(vdesc.o) + 0x008e4e74 _vdesc_alloc_desc + 0x008e4e8c _vdesc_get_hw_desc + 0x008e4ed4 vdesc_module_install + 0x008e4e38 _vdesc_init + 0x008e4e94 _vdesc_swap_vdesc + *fill* 0x008e4eed 0x3 00 + .text 0x008e4ef0 0x8ef /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhtc.a(htc.o) + 0x008e55b8 HTCControlSvcProcessMsg + 0x008e56a8 AdjustCreditThreshold + 0x008e4fd8 _HTC_Init + 0x008e50d0 _HTC_Ready + 0x008e5124 ReturnBuffers + 0x008e51ec _HTC_SendMsg + 0x008e5540 HTCProcessConfigPipeMsg + 0x008e5358 _HTC_GetReservedHeadroom + 0x008e5680 HTCSendDoneHandler + 0x008e53e8 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/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(int-handler-level3.o) + .xt.prop 0x0000054c 0x24 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(interrupt-table.o) + .xt.prop 0x00000570 0x18 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-unhandled.o) + .xt.prop 0x00000588 0x18 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-return.o) + .xt.prop 0x000005a0 0x420 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a(athos_main.o) + .xt.prop 0x000009c0 0x84 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_allocram.o) + .xt.prop 0x00000a44 0x138 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_clock.o) + .xt.prop 0x00000b7c 0x258 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_eeprom.o) + .xt.prop 0x00000dd4 0xf0 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_intr.o) + .xt.prop 0x00000ec4 0x3c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_mem.o) + .xt.prop 0x00000f00 0x180 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_misc.o) + .xt.prop 0x00001080 0x4f8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_printf.o) + .xt.prop 0x00001578 0x144 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_rompatch.o) + .xt.prop 0x000016bc 0x3c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_string.o) + .xt.prop 0x000016f8 0x114 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_tasklet.o) + .xt.prop 0x0000180c 0x150 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_timer.o) + .xt.prop 0x0000195c 0x114 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(cmnos_wdt.o) + .xt.prop 0x00001a70 0x1a4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a(uart_api.o) + .xt.prop 0x00001c14 0x42c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(hif_pci.o) + .xt.prop 0x00002040 0x450 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(HIF_usb.o) + .xt.prop 0x00002490 0xa38 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_api.o) + .xt.prop 0x00002ec8 0x54 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_table.o) + .xt.prop 0x00002f1c 0xe4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(usb_fifo.o) + .xt.prop 0x00003000 0x1f8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a(dma_lib.o) + .xt.prop 0x000031f8 0x9c /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvbuf.a(vbuf.o) + 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/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-sethandler.o) + .xt.prop 0x00004110 0x18 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-table.o) + .xt.prop 0x00004128 0x60 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(exc-c-wrapper-handler.o) + .xt.prop 0x00004188 0x6c /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(clock.o) + .xt.prop 0x000041f4 0x210 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(misc.o) + .xt.prop 0x00004404 0xe4 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(windowspill_asm.o) + .xt.prop 0x000044e8 0x18 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(int_asm--get_intenable.o) + .xt.prop 0x00004500 0x18 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(int_asm--get_interrupt.o) + .xt.prop 0x00004518 0x18 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a(int_asm--set_intenable.o) + .xt.prop 0x00004530 0x90 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib/xcc//libgcc.a(_divsi3.o) + .xt.prop 0x000045c0 0x6c /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib/xcc//libgcc.a(_modsi3.o) + .xt.prop 0x0000462c 0x90 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib/xcc//libgcc.a(_udivsi3.o) + .xt.prop 0x000046bc 0x60 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib/xcc//libgcc.a(_umodsi3.o) + .xt.prop 0x0000471c 0x3c /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(memcmp.o) + .xt.prop 0x00004758 0x198 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(memcpy.o) + .xt.prop 0x000048f0 0xa8 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(memmove.o) + .xt.prop 0x00004998 0xc0 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(memset.o) + .xt.prop 0x00004a58 0xfc /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strcmp.o) + .xt.prop 0x00004b54 0x108 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strcpy.o) + .xt.prop 0x00004c5c 0xb4 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strlen.o) + .xt.prop 0x00004d10 0xe4 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strncmp.o) + .xt.prop 0x00004df4 0x198 /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a(strncpy.o) + *(.xt.prop.*) + *(.gnu.linkonce.prop.*) + +.xt.lit 0x00000000 0x8 + *(.xt.lit) + .xt.lit 0x00000000 0x8 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a(reset-vector-unpack.o) + *(.xt.lit.*) + *(.gnu.linkonce.p.*) + +.xt.profile_range + *(.xt.profile_range) + *(.gnu.linkonce.profile_range.*) + +.xt.profile_ranges + *(.xt.profile_ranges) + *(.gnu.linkonce.xt.profile_ranges.*) + +.xt.profile_files + *(.xt.profile_files) + *(.gnu.linkonce.xt.profile_files.*) +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/_vectors.o +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/crt1-tiny.o +START GROUP +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhandlers-board.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libathos.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libcmnos.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhif.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvbuf.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libvdesc.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libhtc.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libdma.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libfwd.a +LOAD /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/libbuf_pool.a +END GROUP +LOAD /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/arch/lib//libhal.a +LOAD /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib/xcc//libgcc.a +LOAD /opt/xtensa/XtDevTools/install/builds/RB-2007.2-linux/Magpie_P0/xtensa-elf/lib//libc.a +OUTPUT(rom.fpga.out elf32-xtensa-be) + +.xtensa.info 0x00000000 0x1b4 + .xtensa.info 0x00000000 0x1b4 /root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/lib/rom/_vectors.o diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/image/output/fpga/rom.fpga.objdump b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/output/fpga/rom.fpga.objdump new file mode 100755 index 0000000..3a0ae52 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/image/output/fpga/rom.fpga.objdump @@ -0,0 +1,107694 @@ + +rom.fpga.out: file format elf32-xtensa-be +rom.fpga.out +architecture: xtensa, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x008e0000 + +Xtensa header: + +Machine = Base +Insn tables = true +Literal tables = true + +Program Header: + LOAD off 0x00000200 vaddr 0x008e0000 paddr 0x008e0000 align 2**0 + filesz 0x000000de memsz 0x000000de flags r-x + LOAD off 0x000002de vaddr 0x008e0800 paddr 0x008e0800 align 2**0 + filesz 0x0000016a memsz 0x0000016a flags r-x + LOAD off 0x00000448 vaddr 0x008e0a20 paddr 0x008e0a20 align 2**0 + filesz 0x00000006 memsz 0x00000006 flags r-x + LOAD off 0x00000450 vaddr 0x008e0b20 paddr 0x008e0b20 align 2**0 + filesz 0x00000006 memsz 0x00000006 flags r-x + LOAD off 0x00000458 vaddr 0x008e0c20 paddr 0x008e0c20 align 2**0 + filesz 0x00000006 memsz 0x00000006 flags r-x + LOAD off 0x00000460 vaddr 0x008e0ce4 paddr 0x008e0ce4 align 2**0 + filesz 0x00000003 memsz 0x00000003 flags r-x + LOAD off 0x00000464 vaddr 0x008e0d40 paddr 0x008e0d40 align 2**0 + filesz 0x00000006 memsz 0x00000006 flags r-x + LOAD off 0x0000046c vaddr 0x008e0e20 paddr 0x008e0e20 align 2**0 + filesz 0x00000017 memsz 0x00000017 flags r-x + LOAD off 0x00000484 vaddr 0x008e0f20 paddr 0x008e0f20 align 2**0 + filesz 0x00000006 memsz 0x00000006 flags r-x + LOAD off 0x0000048c vaddr 0x008e1000 paddr 0x008e1000 align 2**0 + filesz 0x00005d58 memsz 0x00005d58 flags r-x + LOAD off 0x000061f0 vaddr 0x004e8000 paddr 0x004e8000 align 2**0 + filesz 0x00001044 memsz 0x00001044 flags r-x + LOAD off 0x00007230 vaddr 0x00500000 paddr 0x00500000 align 2**0 + filesz 0x00000950 memsz 0x00000ff8 flags rw- + LOAD off 0x00007b84 vaddr 0x0053f7f0 paddr 0x0053f7f0 align 2**0 + filesz 0x00000000 memsz 0x00000800 flags rw- + LOAD off 0x00007b90 vaddr 0x004e0100 paddr 0x004e0100 align 2**0 + filesz 0x000000ec memsz 0x000000ec flags r-- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .lit4 00000704 004e8000 004e8000 000061f0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .ResetVector.literal 00000000 004e8704 004e8704 000068f4 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .dport0.stack 00000800 0053f7f0 0053f7f0 00007b84 2**0 + ALLOC + 3 .dport0.usb_in_rom 000000ec 004e0100 004e0100 00007b90 2**4 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 4 .dport0.data 00000400 00500000 00500004 00007234 2**0 + CONTENTS, ALLOC, LOAD, DATA + 5 .dport0.bss 00000000 00500400 00500400 00007c7c 2**0 + + 6 .dram0.rodata 00000000 004e8704 004e8704 00007c7c 2**0 + CONTENTS + 7 .rodata 00000934 004e8710 004e8710 00006900 2**4 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 8 .dram0.literal 00000000 004e9044 004e9044 00007c7c 2**0 + CONTENTS + 9 .dram0.data 00000000 00500400 00500400 00007c7c 2**0 + CONTENTS + 10 .data 00000550 00500400 00500400 00007634 2**4 + CONTENTS, ALLOC, LOAD, DATA + 11 .bss 000002a8 00500950 00500950 00007b84 2**4 + ALLOC + 12 .ResetVector.text 000000de 008e0000 008e0000 00000200 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 13 .WindowVectors.text 0000016a 008e0800 008e0800 000002de 2**0 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 14 .KernelExceptionVector.literal 00000000 008e0d00 008e0d00 00007c7c 2**0 + CONTENTS + 15 .KernelExceptionVector.text 00000006 008e0d40 008e0d40 00000464 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 16 .UserExceptionVector.literal 00000000 008e0e00 008e0e00 00007c7c 2**0 + CONTENTS + 17 .UserExceptionVector.text 00000017 008e0e20 008e0e20 0000046c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 18 .DoubleExceptionVector.literal 00000000 008e0f00 008e0f00 00007c7c 2**0 + CONTENTS + 19 .DoubleExceptionVector.text 00000006 008e0f20 008e0f20 00000484 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 20 .Level2InterruptVector.literal 00000000 008e0a00 008e0a00 00007c7c 2**0 + CONTENTS + 21 .Level2InterruptVector.text 00000006 008e0a20 008e0a20 00000448 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 22 .Level3InterruptVector.literal 00000000 008e0b00 008e0b00 00007c7c 2**0 + CONTENTS + 23 .Level3InterruptVector.text 00000006 008e0b20 008e0b20 00000450 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 24 .DebugExceptionVector.literal 00000000 008e0c00 008e0c00 00007c7c 2**0 + CONTENTS + 25 .DebugExceptionVector.text 00000006 008e0c20 008e0c20 00000458 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 26 .NMIExceptionVector.literal 00000000 008e0ce0 008e0ce0 00007c7c 2**0 + CONTENTS + 27 .NMIExceptionVector.text 00000003 008e0ce4 008e0ce4 00000460 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 28 .iram0.text 00000000 008e1000 008e1000 00007c7c 2**0 + CONTENTS + 29 .text 00005d58 008e1000 008e1000 0000048c 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 30 .debug_aranges 00000840 00000000 00000000 00007c80 2**3 + CONTENTS, READONLY, DEBUGGING + 31 .debug_pubnames 000024ff 00000000 00000000 000084c0 2**0 + CONTENTS, READONLY, DEBUGGING + 32 .debug_info 000806eb 00000000 00000000 0000a9bf 2**0 + CONTENTS, READONLY, DEBUGGING + 33 .debug_abbrev 0000321a 00000000 00000000 0008b0aa 2**0 + CONTENTS, READONLY, DEBUGGING + 34 .debug_line 0001e38a 00000000 00000000 0008e2c4 2**0 + CONTENTS, READONLY, DEBUGGING + 35 .xt.prop 00004f8c 00000000 00000000 000ac64e 2**0 + CONTENTS, READONLY + 36 .xt.lit 00000008 00000000 00000000 000b15da 2**0 + CONTENTS, READONLY + 37 .xtensa.info 000001b4 00000000 00000000 000b15e2 2**0 + CONTENTS, READONLY +SYMBOL TABLE: +004e8000 l d .lit4 00000000 .lit4 +004e8704 l d .ResetVector.literal 00000000 .ResetVector.literal +0053f7f0 l d .dport0.stack 00000000 .dport0.stack +004e0100 l d .dport0.usb_in_rom 00000000 .dport0.usb_in_rom +00500000 l d .dport0.data 00000000 .dport0.data +00500400 l d .dport0.bss 00000000 .dport0.bss +004e8704 l d .dram0.rodata 00000000 .dram0.rodata +004e8710 l d .rodata 00000000 .rodata +004e9044 l d .dram0.literal 00000000 .dram0.literal +00500400 l d .dram0.data 00000000 .dram0.data +00500400 l d .data 00000000 .data +00500950 l d .bss 00000000 .bss +008e0000 l d .ResetVector.text 00000000 .ResetVector.text +008e0800 l d .WindowVectors.text 00000000 .WindowVectors.text +008e0d00 l d .KernelExceptionVector.literal 00000000 .KernelExceptionVector.literal +008e0d40 l d .KernelExceptionVector.text 00000000 .KernelExceptionVector.text +008e0e00 l d .UserExceptionVector.literal 00000000 .UserExceptionVector.literal +008e0e20 l d .UserExceptionVector.text 00000000 .UserExceptionVector.text +008e0f00 l d .DoubleExceptionVector.literal 00000000 .DoubleExceptionVector.literal +008e0f20 l d .DoubleExceptionVector.text 00000000 .DoubleExceptionVector.text +008e0a00 l d .Level2InterruptVector.literal 00000000 .Level2InterruptVector.literal +008e0a20 l d .Level2InterruptVector.text 00000000 .Level2InterruptVector.text +008e0b00 l d .Level3InterruptVector.literal 00000000 .Level3InterruptVector.literal +008e0b20 l d .Level3InterruptVector.text 00000000 .Level3InterruptVector.text +008e0c00 l d .DebugExceptionVector.literal 00000000 .DebugExceptionVector.literal +008e0c20 l d .DebugExceptionVector.text 00000000 .DebugExceptionVector.text +008e0ce0 l d .NMIExceptionVector.literal 00000000 .NMIExceptionVector.literal +008e0ce4 l d .NMIExceptionVector.text 00000000 .NMIExceptionVector.text +008e1000 l d .iram0.text 00000000 .iram0.text +008e1000 l d .text 00000000 .text +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_pubnames 00000000 .debug_pubnames +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .xt.prop 00000000 .xt.prop +00000000 l d .xt.lit 00000000 .xt.lit +00000000 l d .xtensa.info 00000000 .xtensa.info +00000000 l d *ABS* 00000000 .shstrtab +00000000 l d *ABS* 00000000 .symtab +00000000 l d *ABS* 00000000 .strtab +00000000 l df *ABS* 00000000 crt1-tiny.S +00000000 l df *ABS* 00000000 reset-vector.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +008e00b6 l .ResetVector.text 00000000 unpackdone +008e0094 l .ResetVector.text 00000000 unpack +008e00b0 l .ResetVector.text 00000000 upnext +008e00a0 l .ResetVector.text 00000000 uploop +00000000 l df *ABS* 00000000 user-vector.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 exc-alloca-handler.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 exc-syscall-handler.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000007 l *ABS* 00000000 .Ldelta_done +00000000 l df *ABS* 00000000 int-lowpri-dispatcher.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +008e11ce l .text 00000000 spurious_int +00000000 l df *ABS* 00000000 int-handler.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +008e12d4 l .text 00000000 spurious2int +008e12e8 l .text 00000000 return2from_exc +00000000 l df *ABS* 00000000 int-handler.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +008e1388 l .text 00000000 spurious3int +008e1399 l .text 00000000 return3from_exc +004e8730 l O .rodata 00000010 pattern.init_91_2 +008e1428 l F .text 00000029 athos_linkage_check +008e1474 l F .text 0000005e AR6002_misaligned_load_handler +008e14d4 l F .text 00000071 AR6002_fatal_exception_handler +00500950 l O .bss 00000002 i.1_140_4 +00500974 l O .bss 00000004 last_tick.1_93_1 +008e247c l F .text 00000054 _cvt +008e24d0 l F .text 00000445 cmnos_vprintf +00500a30 l O .bss 00000004 g_tasklet_ctx_121 +00500a44 l O .bss 00000010 uart_ctl_blk_122 +008e2eb4 l F .text 00000040 _uart_hwinit +008e3348 l F .text 00000012 usbfifo_get_command_buf +008e335c l F .text 00000036 usbfifo_recv_command +008e3394 l F .text 0000001e usbfifo_get_event_buf +008e33b4 l F .text 00000011 usbfifo_send_event_done +008e34b4 l F .text 00000007 _HIFusb_get_reserved_headroom +008e34bc l F .text 0000002b enable_rx +008e34e8 l F .text 0000001e get_queue_from_pipe +008e381c l F .text 00000028 vUsb_ep0tx +008e3844 l F .text 00000022 vUsb_ep0rx +008e3868 l F .text 00000081 vUsbClrEPx +008e38ec l F .text 00000034 bGet_status +008e3920 l F .text 00000023 bClear_feature +008e3944 l F .text 000000d0 bSet_feature +008e3a14 l F .text 0000001f bSet_address +008e3a34 l F .text 0000008f bGet_descriptor +008e3ac4 l F .text 00000026 bGet_configuration +008e3aec l F .text 000000a5 bSet_configuration +008e3b94 l F .text 00000045 bGet_interface +008e3bdc l F .text 0000008d bSet_interface +008e3c6c l F .text 000000b6 vUsbEP0TxData +008e3d24 l F .text 0000007c vUsbEP0RxData +008e3da0 l F .text 0000005b vUsb_SetupDescriptor +008e3dfc l F .text 000000fd bStandardCommand +008e3efc l F .text 000000f2 VendorCommand +008e3ff0 l F .text 00000176 vUsb_ep0setup +008e4168 l F .text 00000081 cFUSB200Init +008e41ec l F .text 0000001a _usbfifo_enable_event_isr +008e4208 l F .text 00000018 _usbfifo_init +008e4220 l F .text 00000068 vUsb_Reg_Out +008e4288 l F .text 000000a2 vUsb_Status_In +008e432c l F .text 00000011 zfResetUSBFIFO +008e4340 l F .text 00000011 zfTurnOffPower +008e4354 l F .text 00000042 zfGenWatchDogEvent +008e4398 l F .text 00000008 zfJumpToBootCode +008e43a0 l F .text 000000c6 _usb_rom_task +008e4468 l F .text 0000012c _usb_fw_task +008e4594 l F .text 000000a4 _usb_clk_init +008e4ef0 l F .text 00000021 adf_nbuf_tailroom +008e4f14 l F .text 00000029 adf_nbuf_push_head +008e4f40 l F .text 0000002b adf_nbuf_put_tail +008e4f6c l F .text 0000002a adf_nbuf_pull_head +008e4f98 l F .text 00000008 adf_nbuf_len +008e4fa0 l F .text 00000015 adf_nbuf_peek_header +008e4fb8 l F .text 00000007 adf_nbuf_get_priv +008e5838 l F .text 0000004b swapData +008e589c l F .text 00000078 config_queue +008e5b6c l F .text 00000047 relinkUSBDescToVdesc +008e5d24 l F .text 00000015 mii_reg_write_32 +00000000 l df *ABS* 00000000 exc-c-wrapper-handler.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/windowspill_asm.S +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/strcmp.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/strcpy.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/strlen.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/strncpy.S +008e66c8 l .text 00000000 __strncpy_aux +00000000 l df *ABS* 00000000 _vectors.S +00000000 l df *ABS* 00000000 debug-vector.S +00000000 l df *ABS* 00000000 double-vector.S +00000000 l df *ABS* 00000000 kernel-vector.S +00000000 l df *ABS* 00000000 nmi-vector.S +00000000 l df *ABS* 00000000 window-vectors.S +00000000 l df *ABS* 00000000 int-vector.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 int-vector.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 interrupt-table.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 exc-unhandled.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 exc-return.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000000 l df *ABS* 00000000 exc-table.S +00000000 l *ABS* 00000000 KEXC_pc +00000004 l *ABS* 00000000 KEXC_ps +00000008 l *ABS* 00000000 KEXC_areg +00000018 l *ABS* 00000000 KEXC_sar +0000001c l *ABS* 00000000 KEXC_lcount +00000020 l *ABS* 00000000 KEXC_lbeg +00000024 l *ABS* 00000000 KEXC_lend +00000028 l *ABS* 00000000 KernelFrameSize +00000000 l *ABS* 00000000 UEXC_pc +00000004 l *ABS* 00000000 UEXC_ps +00000008 l *ABS* 00000000 UEXC_sar +0000000c l *ABS* 00000000 UEXC_vpri +00000010 l *ABS* 00000000 UEXC_a2 +00000014 l *ABS* 00000000 UEXC_a3 +00000018 l *ABS* 00000000 UEXC_a4 +0000001c l *ABS* 00000000 UEXC_a5 +00000020 l *ABS* 00000000 UEXC_exccause +00000024 l *ABS* 00000000 UEXC_lcount +00000028 l *ABS* 00000000 UEXC_lbeg +0000002c l *ABS* 00000000 UEXC_lend +00000030 l *ABS* 00000000 UserFrameSize +00000070 l *ABS* 00000000 UserFrameTotalSize +00000000 l *ABS* 00000000 XTOS_ENABLED_OFS +00000004 l *ABS* 00000000 XTOS_VPRI_ENABLED_OFS +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/clock.S +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/cache_asm.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/cache_asm.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/cache_asm.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/cache_asm.S +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/int_asm.S +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/int_asm.S +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/hal/int_asm.S +00000010 l *ABS* 00000000 .callsz +00000010 l *ABS* 00000000 .locsz +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/tools/swtools-x86-linux/xtensa-elf/src/libgcc-xcc/config/xtensa/lib1funcs.asm +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memcpy.S +008e69e8 l .text 00000000 __memcpy_aux +00000000 l df *ABS* 00000000 /home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S +008e6ce4 l .text 00000000 __memset_aux +00500abc g O .bss 00000002 u16TxRxCounter +008e1c74 g F .text 0000000c cmnos_refclk_speed_get +00000000 *UND* 00000000 _write_usb_desc_to_eeprom +008e22f4 g F .text 00000051 cmnos_misaligned_load_handler +008e3780 g F .text 0000009c HIFusb_DescTraceDump +004e87a4 g O .rodata 00000001 Xthal_have_loops +008e653c g F .text 00000000 strcpy +008e5828 g F .text 00000010 _DMAengine_init_tx_queue +008e1604 g F .text 00000010 athos_interrupt_handler +008e3314 g F .text 00000032 hif_pci_api_install +008e6854 g F .text 00000000 xthal_set_intenable +004e87d6 g O .rodata 00000001 Xthal_have_mimic_cacheattr +004e87d8 g O .rodata 00000001 Xthal_mmu_rings +004e87a3 g O .rodata 00000001 Xthal_have_density +00500b4d g O .bss 00000001 Xthal_have_clamps +008e1c80 g F .text 00000005 cmnos_uart_frequency +00500ad0 g O .bss 00000002 u8UsbInterfaceValue +008e3180 g F .text 00000028 __pci_reap_recv +008e2954 g F .text 0000000f cmnos_printf_module_install +008e2f6c g F .text 00000014 __pci_get_tx_eng +008e2150 g F .text 0000003e cmnos_intr_mask_inum +004e9044 g *ABS* 00000000 _bss_table_end +00000000 *UND* 00000000 __adf_net_register_drv +008e0000 g .ResetVector.text 00000000 _ResetVector +fff00ff0 g *ABS* 00000000 _memmap_cacheattr_unused_mask +008e55b8 g F .text 00000086 HTCControlSvcProcessMsg +008e0b26 g *ABS* 00000000 _Level3InterruptVector_text_end +004e8710 g O .rodata 00000018 _rom_store_table +00500b70 g O .bss 00000001 Xthal_num_xlmi +008e2230 g F .text 0000005f cmnos_intr_invoke_isr +004e8798 g O .rodata 00000004 Xthal_rev_no +004e87a1 g O .rodata 00000001 Xthal_memory_order +008e29e8 g F .text 0000003c cmnos_romp_decode +00500000 g .dport0.data 00000000 _indir_tbl +008e1dbc g F .text 00000037 cmnos_eep_is_exist +00500b48 g O .bss 00000004 Xthal_release_internal +004e8824 g O .rodata 00000004 Xthal_xlmi_size +008e4e10 g F .text 00000014 _vbuf_free_vbuf +008e6128 g F .text 00000023 buf_pool_module_install +00500b6a g O .bss 00000001 Xthal_itlb_way_bits +004e8704 g *ABS* 00000000 _lit4_end +00500a2c g O .bss 00000004 patch_start +008e1c88 g F .text 00000005 cmnos_sysclk_change +00021001 g *ABS* 00000000 _memmap_cacheattr_wt_base +008e2450 g F .text 0000002a cmnos_write_char +008e0c00 g *ABS* 00000000 _DebugExceptionVector_literal_end +00500ae0 g O .bss 00000004 u8String10Descriptor +008e6b20 g F .text 000001c2 memmove +008e6d58 g *ABS* 00000000 _text_end +004e87ac g O .rodata 00000001 Xthal_have_highlevel_interrupts +008e3614 g F .text 0000002a _HIFusb_return_recv_buf +008e4c40 g F .text 00000029 __dma_lib_rx_init +008e18c8 g F .text 00000033 turn_off_rc +008e0f26 g *ABS* 00000000 _DoubleExceptionVector_text_end +004e87cc g O .rodata 00000004 Xthal_hw_min_version_major +008e3658 g F .text 00000010 _HIFusb_is_pipe_supported +004e8000 g *ABS* 00000000 _lit4_start +00500b6b g O .bss 00000001 Xthal_itlb_arf_ways +004e9044 g *ABS* 00000000 _dram0_literal_end +004e8830 g O .rodata 00000020 Xthal_intlevel +00500ad4 g O .bss 00000002 u16FirmwareComplete +00000000 g *ABS* 00000000 _xtos_vectors_ref_ +008e167c g F .text 00000032 athos_init +008e56a8 g F .text 0000002d AdjustCreditThreshold +00500700 g O .data 00000004 _putc +008e2414 g F .text 0000000b cmnos_rom_version_get +004e9044 g *ABS* 00000000 _dram0_literal_start +00500a38 g O .bss 0000000c wdt_ctrl +008e22ec g F .text 00000005 cmnos_mac_reset +004e87a9 g O .rodata 00000001 Xthal_have_exceptions +008e6d58 g .text 00000000 _etext +008e4e24 g F .text 00000014 vbuf_module_install +00000000 *UND* 00000000 wlan_pci_register_drv +004e87c4 g O .rodata 00000004 Xthal_hw_release_major +008e2d28 g F .text 00000028 cmnos_wdt_init +00500b44 g O .bss 00000004 Xthal_release_minor +004e87ec g O .rodata 00000004 Xthal_instrom_vaddr +00500708 g O .data 0000000c pci_sc +004e87f4 g O .rodata 00000004 Xthal_instrom_size +008e470c g F .text 0000000f usbfifo_module_install +008e2fa4 g F .text 00000016 __pci_enable +008e4fd8 g F .text 000000e0 _HTC_Init +008e0ce4 g *ABS* 00000000 _NMIExceptionVector_text_start +004e8820 g O .rodata 00000004 Xthal_xlmi_paddr +008e33c8 g F .text 00000053 _HIFusb_init +004e0100 g O .dport0.usb_in_rom 00000012 UsbDeviceDescriptor +00500954 g O .bss 00000004 allocram_current_addr +008e2d0c g F .text 0000001c cmnos_wdt_disable +008e6a28 g F .text 00000000 memcpy +008e5d74 g F .text 00000018 fwd_retbuf_handler +00000000 *UND* 00000000 _need_user_vector_ +008e0e37 g *ABS* 00000000 _UserExceptionVector_text_end +008e67e4 g F .text 00000000 _xtos_unhandled_interrupt +004e87d9 g O .rodata 00000001 Xthal_mmu_ca_bits +00500b64 g O .bss 00000001 Xthal_have_xlt_cacheattr +004e9044 g *ABS* 00000000 _rodata_end +00500b50 g O .bss 00000001 Xthal_have_speculation +008e4df0 g F .text 0000001e _vbuf_alloc_vbuf +008e2ae8 g F .text 0000000c cmnos_tasklet_init +008e57e8 g F .text 00000040 _DMAengine_init_rx_queue +00500b04 g O .bss 00000008 g_vdescCtx +008e3290 g F .text 0000000e __pci_is_pipe_supported +008e6020 g F .text 0000003d magpie_mdio_copy_bytes +004e87d7 g O .rodata 00000001 Xthal_have_tlbs +008e0ce7 g *ABS* 00000000 _NMIExceptionVector_text_end +00500ad8 g O .bss 00000004 u8UsbDeviceDescriptor +008e0900 g .WindowVectors.text 00000000 _WindowOverflow12 +008e0c20 g *ABS* 00000000 _DebugExceptionVector_text_start +00500970 g O .bss 00000004 pll_ctrl_setting_5ghz +008e6824 g F .text 00000000 xthal_set_ccompare +008e2f80 g F .text 00000023 __pci_get_rx_eng +008e6910 g F .text 00000050 __udivsi3 +008e2e0c g F .text 0000002c _uart_char_put_nowait +004e87f0 g O .rodata 00000004 Xthal_instrom_paddr +008e2f38 g F .text 0000000a __pci_reg_write +008e16e8 g F .text 000000a3 read_usb_conf +008e0800 g *ABS* 00000000 _WindowVectors_text_start +008e50d0 g F .text 00000052 _HTC_Ready +008e2b9c g F .text 0000000f cmnos_timer_setfn +008e2d68 g F .text 00000028 cmnos_wdt_module_install +008e471c g F .text 0000009d cmnos_usb_module_install +00500950 g *ABS* 00000000 _bss_start +008e67ec g .text 00000000 _xtos_unhandled_exception +00500400 g *ABS* 00000000 _dram0_data_end +00500b67 g O .bss 00000001 Xthal_mmu_asid_kernel +008e5124 g F .text 0000007d ReturnBuffers +008e6270 g .text 00000000 _xtos_cause3_handler +00500780 g O .data 0000003c u8OtherSpeedConfigDescriptorEX +004e87a2 g O .rodata 00000001 Xthal_have_windowed +00500ad2 g O .bss 00000002 u8UsbInterfaceAlternateSetting +00500950 g *ABS* 00000000 __XT_EXCEPTION_DESCS__ +008e2290 g F .text 0000001e cmnos_intr_module_install +008e2120 g F .text 00000005 cmnos_intr_dummy +008e2e6c g F .text 0000001d _uart_str_out +22221221 g *ABS* 00000000 _memmap_cacheattr_wb_allvalid +00500a54 g O .bss 00000044 g_hifUSBCtx +008e2bf0 g F .text 00000030 cmnos_timer_disarm +008e1c30 g F .text 00000014 cmnos_allocram_module_install +008e2b20 g F .text 00000031 cmnos_tasklet_disable +008e178c g F .text 000000d2 set_pci_conf +008e32a0 g F .text 0000000e __pci_get_max_msg_len +00000000 *UND* 00000000 send_buffer_via_dma +008e1000 g *ABS* 00000000 _text_start +00500958 g O .bss 00000004 allocram_remaining_bytes +008e4d7c g F .text 00000037 dma_lib_module_install +008e1614 g F .text 00000066 athos_interrupt_init +008e2dd8 g F .text 00000007 _uart_char_get_nothing +008e22d8 g F .text 00000011 cmnos_system_reset +00021001 g *ABS* 00000000 _memmap_cacheattr_wb_base +008e51ec g F .text 0000015a _HTC_SendMsg +008e0b20 g *ABS* 00000000 _Level3InterruptVector_text_start +008e4e74 g F .text 00000018 _vdesc_alloc_desc +008e2aa0 g F .text 00000019 cmnos_romp_module_install +00500b69 g O .bss 00000001 Xthal_mmu_sr_bits +008e2c7c g F .text 0000002b cmnos_wdt_last_boot +008e4d14 g F .text 0000001b __dma_reap_recv +008e2a34 g F .text 00000061 cmnos_romp_download +005007c0 g O .data 00000090 eng_q +004e87e9 g O .rodata 00000001 Xthal_num_ccompare +008e0ce0 g *ABS* 00000000 _NMIExceptionVector_literal_end +008e1548 g F .text 0000002b generic_hif_module_install +fff22ff2 g *ABS* 00000000 _memmap_cacheattr_bp_strict +0050096c g O .bss 00000004 pll_ctrl_setting_24ghz +008e57e0 g F .text 00000005 _DMAengine_init +008e31a8 g F .text 0000009f __pci_isr_handler +008e47f8 g F .text 0000001e mUsbFIFOConfig +008e5bf0 g F .text 00000092 zfDmaReclaimPacket +22221221 g *ABS* 00000000 _memmap_cacheattr_wt_trapnull +008e367c g F .text 000000ad _HIFusb_isr_handler +008e616c g F .text 00000055 _buf_pool_static_create_pool +008e0d40 g .KernelExceptionVector.text 00000000 _KernelExceptionVector +00500964 g O .bss 00000004 clock_info +008e2a98 g F .text 00000005 cmnos_romp_init +008e0e00 g *ABS* 00000000 _UserExceptionVector_literal_start +008e16b0 g F .text 00000036 _read_usb_desc +008e0800 g .WindowVectors.text 00000000 _WindowOverflow4 +008e4b7c g F .text 0000000a __dma_reg_write +00000000 g *ABS* 00000000 xthals_release_minor +008e3248 g F .text 0000002a __pci_xmit_buf +00500400 g .data 00000000 _xtos_exc_handler_table +008e0d40 g *ABS* 00000000 _KernelExceptionVector_text_start +008e30a8 g F .text 00000053 __pci_init +00500640 g O .data 000000b8 basic_ROM_module_table +008e5ec0 g F .text 000000c2 magpie_mdio_boot_init +008e2de0 g F .text 0000002c _uart_char_put +00500b78 g *ABS* 00000000 _bss_end +008e13f8 g F .text 00000030 Magpie_fatal_exception_handler +008e62ec g .text 00000000 xthal_window_spill_nw +008e1240 g .text 00000000 _Level2FromVector +008e6164 g F .text 00000005 _buf_pool_static_shutdown +00500b18 g O .bss 0000002c g_poolCtx +008e0840 g .WindowVectors.text 00000000 _WindowUnderflow4 +00500978 g O .bss 00000002 eep_state +004e87a0 g O .rodata 00000001 Xthal_num_aregs_log2 +008e4c6c g F .text 00000028 __dma_hard_xmit +00500500 g O .data 00000004 _xtos_enabled +00500500 g .data 00000000 _xtos_intstruct +004e8818 g O .rodata 00000004 Xthal_dataram_size +008e5540 g F .text 00000075 HTCProcessConfigPipeMsg +008e61c4 g F .text 00000022 _buf_pool_static_alloc_buf +008e096a g *ABS* 00000000 _WindowVectors_text_end +00500aa4 g O .bss 00000010 usbFifoConf +004e8814 g O .rodata 00000004 Xthal_dataram_paddr +00500ab8 g O .bss 00000004 pu8DescriptorEX +00500400 g *ABS* 00000000 _dram0_data_start +008e2e58 g F .text 00000005 _uart_task +004e0100 g .dport0.usb_in_rom 00000000 _reserved_rom_data_end +004e8790 g O .rodata 00000004 Xthal_release_major +008e0940 g .WindowVectors.text 00000000 _WindowUnderflow12 +008e32c0 g F .text 0000000d __pci_get_def_pipe +22222222 g *ABS* 00000000 _memmap_cacheattr_bp_allvalid +008e1174 g .text 00000000 _xtos_l1int_handler +004e8810 g O .rodata 00000004 Xthal_dataram_vaddr +004e87d0 g O .rodata 00000004 Xthal_hw_max_version_major +004e87e6 g O .rodata 00000001 Xthal_num_instram +22221221 g *ABS* 00000000 _memmap_cacheattr_wt_allvalid +008e6834 g F .text 00000000 xthal_get_ccompare +008e5358 g F .text 00000013 _HTC_GetReservedHeadroom +004e01c0 g O .dport0.usb_in_rom 00000018 String20Descriptor +008e1d38 g F .text 00000057 cmnos_eeprom_write_hword +00500950 g *ABS* 00000000 __XT_EXCEPTION_DESCS_END__ +00500b65 g O .bss 00000001 Xthal_have_cacheattr +004e87e5 g O .rodata 00000001 Xthal_dtlb_ways +008e2190 g F .text 00000039 cmnos_intr_unmask_inum +00500704 g O .data 00000004 patch_addr +008e1c98 g F .text 00000005 cmnos_wlan_band_set +00500ac8 g O .bss 00000004 eUsbCxCommand +00000000 *UND* 00000000 WMI_service_module_install +008e61e8 g F .text 00000010 _buf_pool_static_alloc_buf_align +008e6960 g F .text 0000003d __umodsi3 +00500b6d g O .bss 00000001 Xthal_dtlb_arf_ways +004e01b0 g O .dport0.usb_in_rom 00000010 String10Descriptor +00500400 g *ABS* 00000000 _dport0_data_start +008e297c g F .text 00000069 _read_rom_patch +008e5914 g F .text 00000057 _DMAengine_config_rx_queue +00500af0 g O .bss 00000006 UsbStatus +004e0120 g O .dport0.usb_in_rom 0000003c u8HSConfigDescriptor01 +008e681c g F .text 00000000 xthal_get_ccount +008e6d58 g .text 00000000 _text_end_magic +008e22b0 g F .text 00000005 cmnos_mem_init +0053f7f0 g .dport0.stack 00000000 _stack_sentry +008e2bac g F .text 00000042 cmnos_timer_arm +008e5b1c g F .text 00000050 dma_engine_module_install +008e6298 g .text 00000000 _GeneralException +008e2918 g F .text 00000033 cmnos_printf +008e6060 g F .text 0000001f fw_compute_cksum +008e2104 g F .text 00000019 cmnos_eep_module_install +0d02230f g *ABS* 00000000 xthals_hw_configid1 +008e62ec g .text 00000000 xthal_spill_registers_into_stack_nw +00000000 *UND* 00000000 hif_module_install +00500b6c g O .bss 00000001 Xthal_dtlb_way_bits +008e5680 g F .text 00000027 HTCSendDoneHandler +008e5a34 g F .text 0000001e _DMAengine_has_compl_packets +008e3140 g F .text 00000014 __pci_reg_callback +008e4840 g F .text 00000024 mUsbEPMxPtSzLow +004e87d4 g O .rodata 00000001 Xthal_have_spanning_way +008e53e8 g F .text 0000005e HTCCheckAndSendCreditReport +008e1000 g .text 00000000 _start +008e00de g *ABS* 00000000 _ResetVector_text_end +00500a98 g O .bss 0000000c ControlCmd +00500400 g *ABS* 00000000 _data_start +008e6814 g F .text 00000000 _xtos_p_none +00500ace g O .bss 00000002 u8UsbConfigValue +00500980 g O .bss 00000004 cmnos_enabled_interrupts +008e2e60 g F .text 0000000a _uart_status +008e2d50 g F .text 00000018 cmnos_wdt_task +008e5348 g F .text 00000005 _HTC_PauseRecv +008e1cdc g F .text 00000026 cmnos_tick +008e23f4 g F .text 0000001f cmnos_is_host_present +004e880c g O .rodata 00000004 Xthal_datarom_size +004e87a8 g O .rodata 00000001 Xthal_have_mul16 +008e1d90 g F .text 0000002b cmnos_eeprom_read_hword +008e47bc g F .text 0000001c mUsbEPMap +00500b60 g O .bss 00000004 Xthal_hw_release_internal +00000000 *UND* 00000000 __adf_os_setup_intr +004e87b0 g O .rodata 00000001 Xthal_have_s32c1i +008e4e8c g F .text 00000008 _vdesc_get_hw_desc +008e6638 g F .text 0000008e strncmp +008e0b00 g *ABS* 00000000 _Level3InterruptVector_literal_end +004e87e4 g O .rodata 00000001 Xthal_itlb_ways +008e1ca0 g F .text 00000005 cmnos_pll_init +008e2ac4 g F .text 00000023 cmnos_string_module_install +008e2cc4 g F .text 00000028 cmnos_wdt_set +008e0d00 g *ABS* 00000000 _KernelExceptionVector_literal_end +008e1e54 g F .text 00000045 cmnos_eep_read +004e87c0 g O .rodata 00000004 Xthal_hw_configid1 +008e6700 g F .text 00000000 strncpy +008e0800 g *ABS* 00000000 _memmap_vecbase_reset +008e0a20 g .Level2InterruptVector.text 00000000 _Level2Vector +008e1c44 g F .text 00000020 cmnos_delay_us +004e87ab g O .rodata 00000001 Xthal_have_interrupts +00500b0c g O .bss 0000000c fwd_sc +008e1c90 g F .text 00000005 cmnos_clockregs_init +008e0f20 g *ABS* 00000000 _DoubleExceptionVector_text_start +008e61f8 g F .text 00000013 _buf_pool_static_free_buf +008e1468 g F .text 0000000a athos_restore_intrlvl +fff21ff1 g *ABS* 00000000 _memmap_cacheattr_wb_strict +008e18fc g F .text 000002af bootentry +008e12f4 g .text 00000000 _Level3FromVector +004e87af g O .rodata 00000001 Xthal_have_release_sync +008e620c g F .text 00000061 _xtos_set_exception_handler +004e87c8 g O .rodata 00000004 Xthal_hw_release_name +005006fc g O .data 00000004 assprint +0050095c g O .bss 00000004 cticks +008e2b04 g F .text 00000019 cmnos_tasklet_schedule +008e2d90 g F .text 0000003e _uart_init +00500400 g .dport0.data 00000000 _reserved_data_end +008e4ed4 g F .text 00000019 vdesc_module_install +008e0f00 g *ABS* 00000000 _DoubleExceptionVector_literal_start +008e1c64 g F .text 0000000d cmnos_milliseconds +008e32d0 g F .text 00000041 hif_pci_module_install +008e69a0 g F .text 00000045 memcmp +008e2ef4 g F .text 00000037 cmnos_uart_module_install +008e2e38 g F .text 00000020 _uart_char_get +00500b58 g O .bss 00000004 Xthal_hw_min_version_minor +00500950 g *ABS* 00000000 _data_end +008e4cec g F .text 00000026 __dma_xmit_done +008e102c g .text 00000000 _xtos_alloca_handler +008e1000 g *ABS* 00000000 _iram0_text_end +004e87fc g O .rodata 00000004 Xthal_instram_paddr +004e8704 g *ABS* 00000000 _ResetVector_literal_end +008e5a2c g F .text 00000005 _DMAengine_flush_xmit +008e2c5c g F .text 0000001e cmnos_timer_module_install +004e9034 g *ABS* 00000000 __XT_EXCEPTION_TABLE__ +008e11e4 g F .text 0000004c _xtos_set_interrupt_handler_arg +004e87b2 g O .rodata 00000001 Xthal_have_pif +004e87a6 g O .rodata 00000001 Xthal_have_minmax +008e5a54 g F .text 0000002f _DMAengine_reap_recv_buf +008e5bb4 g F .text 00000039 zfDmaGetPacket +008e30fc g F .text 0000003a __pci_cfg_pipe +008e4a40 g F .text 0000012f vUsbFIFO_EPxCfg_FS +00500ae4 g O .bss 00000004 u8String20Descriptor +00500508 g .data 00000000 _xtos_interrupt_table +00500b4f g O .bss 00000001 Xthal_have_fp +008e6080 g F .text 000000a8 mdio_get_fw_image +008e2b7c g F .text 0000001e cmnos_tasklet_module_install +008e2b54 g F .text 00000028 cmnos_tasklet_run +008e614c g F .text 00000016 _buf_pool_static_init +008e5d8c g F .text 0000002e fwd_tgt_process_last +008e0020 g .ResetVector.text 00000000 _ResetHandler +fff21ff1 g *ABS* 00000000 _memmap_cacheattr_wt_strict +008e6d0c g F .text 00000000 memset +008e6278 g .text 00000000 _xtos_c_wrapper_handler +008e1bac g F .text 0000001e main +00500b68 g O .bss 00000001 Xthal_mmu_ring_bits +008e5dbc g F .text 000000df fwd_tgt_recv +008e5a84 g F .text 00000036 _DMAengine_reap_xmited_buf +008e5abc g F .text 0000005e _DMAengine_desc_dump +008e50b8 g F .text 00000005 _HTC_Shutdown +004e0100 g .dport0.usb_in_rom 00000000 _reserved_rom_data_start +008e4b88 g F .text 00000020 __dma_set_base +005005a0 g .data 00000000 _xtos_interrupt_mask_table +008e23c4 g F .text 0000002d cmnos_get_kbhit +008e0a20 g *ABS* 00000000 _Level2InterruptVector_text_start +008e0c20 g .DebugExceptionVector.text 00000000 _DebugExceptionVector +00500ae8 g O .bss 00000004 u8String30Descriptor +008e1d04 g F .text 00000032 cmnos_clock_module_install +008e5fd8 g F .text 00000045 mdio_read_block +008e0ce4 g .NMIExceptionVector.text 00000000 _NMIExceptionVector +008e2f44 g F .text 00000027 __pci_get_pipe +00500ac4 g O .bss 00000004 eUsbCxFinishAction +004e879c g O .rodata 00000004 Xthal_num_aregs +004e87ad g O .rodata 00000001 Xthal_have_nmi +008e5c84 g F .text 0000009f zfDmaPutPacket +008e32b0 g F .text 00000007 __pci_get_reserved_headroom +008e53b0 g F .text 00000015 HTCFreeMsgBuffer +008e4bf0 g F .text 0000004d __dma_lib_rx_config +004e87b8 g O .rodata 00000004 Xthal_build_unique_id +004e8804 g O .rodata 00000004 Xthal_datarom_vaddr +00500850 g .data 00000000 _xtos_c_handler_table +008e189c g F .text 0000002c pci_gmac_bootload +00500504 g O .data 00000004 _xtos_vpri_enabled +008e0b20 g .Level3InterruptVector.text 00000000 _Level3Vector +008e0d46 g *ABS* 00000000 _KernelExceptionVector_text_end +008e685c g F .text 00000068 __divsi3 +008e0f00 g *ABS* 00000000 _DoubleExceptionVector_literal_end +008e1104 g .text 00000000 _xtos_syscall_handler +008e1192 g .text 00000000 _LevelOneInterrupt +008e3668 g F .text 00000012 _HIFusb_get_max_msg_len +008e6424 g F .text 00000000 strcmp +0053f7f0 g .dport0.stack 00000000 _reserved_stack_start +004e8808 g O .rodata 00000004 Xthal_datarom_paddr +008e2c2c g F .text 0000002d cmnos_timer_handler +004e8704 g *ABS* 00000000 _dram0_rodata_start +004e87d5 g O .rodata 00000001 Xthal_have_identity_map +008e3648 g F .text 00000005 _HIFusb_pause_recv +0053fff0 g .dport0.stack 00000000 _reserved_stack_end +008e3070 g F .text 00000035 __pci_boot_init +008e3508 g F .text 000000ab _HIFusb_config_pipe +008e3154 g F .text 0000002c __pci_reap_xmitted +004e8704 g *ABS* 00000000 _ResetVector_literal_start +008e2ca8 g F .text 0000001a cmnos_wdt_reset +008e3640 g F .text 00000005 _HIFusb_set_recv_bufsz +00500b4e g O .bss 00000001 Xthal_have_mac16 +008e2420 g F .text 0000002d cmnos_misc_module_install +008e0e00 g *ABS* 00000000 _UserExceptionVector_literal_end +004e0260 g .dport0.usb_in_rom 00000000 _data_start_in_rom +008e51dc g F .text 00000010 _HTC_ReturnBuffers +008e1574 g F .text 0000008f athos_indirection_table_install +005006f8 g O .data 00000004 assloop +008e6844 g F .text 00000000 xthal_get_intenable +004e87aa g O .rodata 00000001 Xthal_xea_version +00500a28 g O .bss 00000004 current_dump +008e4ba8 g F .text 00000048 __dma_lib_tx_init +004e87dc g O .rodata 00000004 Xthal_mmu_max_pte_page_size +008e3274 g F .text 0000001b __pci_return_recv +008e2af4 g F .text 0000000f cmnos_tasklet_init_task +008e0c00 g *ABS* 00000000 _DebugExceptionVector_literal_start +00500990 g O .bss 00000098 cmnos_isr_info +008e4818 g F .text 00000027 mUsbEPMxPtSzHigh +008e48b0 g F .text 00000190 vUsbFIFO_EPxCfg_HS +008e0ce0 g *ABS* 00000000 _NMIExceptionVector_literal_start +008e1e9c g F .text 00000267 cmnos_eep_init +00500ac0 g O .bss 00000004 u8ConfigDescriptorEX +004e8740 g O .rodata 00000050 cmnos_clocking_table +008e0e20 g *ABS* 00000000 _UserExceptionVector_text_start +00500acc g O .bss 00000002 UsbChirpFinish +008e56e0 g F .text 000000ff HTCMsgRecvHandler +008e373c g F .text 00000041 hif_usb_module_install +00500b4c g O .bss 00000001 Xthal_have_booleans +008e1860 g F .text 0000003b bootload +00500000 g .dport0.data 00000000 _reserved_data_start +008e32b8 g F .text 00000005 __pci_shutdown +22221221 g *ABS* 00000000 _memmap_cacheattr_wb_trapnull +008e3424 g F .text 00000014 _HIFusb_register_callback +008e67fc g .text 00000000 _xtos_return_from_exc +008e4d30 g F .text 00000028 __dma_return_recv +008e47d8 g F .text 0000001e mUsbFIFOMap +004e9034 g *ABS* 00000000 _bss_table_start +008e0a00 g *ABS* 00000000 _Level2InterruptVector_literal_end +00500b66 g O .bss 00000001 Xthal_mmu_asid_bits +008e12f1 g .text 00000000 _Level2HandlerLabel +008e2348 g F .text 0000006c cmnos_assfail +008e2964 g F .text 00000018 _patch_dump +004e87ae g O .rodata 00000001 Xthal_have_prid +008e4b70 g F .text 0000000a __dma_reg_read +004e87e0 g O .rodata 00000004 Xthal_mmu_min_pte_page_size +008e13a2 g .text 00000000 _Level3HandlerLabel +008e341c g F .text 00000005 _HIFusb_shutdown +008e2c20 g F .text 0000000c cmnos_timer_init +008e4c94 g F .text 0000001b __dma_reap_xmitted +008e2a24 g F .text 0000000d cmnos_romp_install +008e372c g F .text 0000000f _HIFusb_get_default_pipe +004e8800 g O .rodata 00000004 Xthal_instram_size +00500b6e g O .bss 00000001 Xthal_num_instrom +c280dbff g *ABS* 00000000 xthals_hw_configid0 +008e536c g F .text 00000041 htc_module_install +00500400 g *ABS* 00000000 _dport0_data_end +0053fff0 g .dport0.stack 00000000 __stack +008e23b4 g F .text 00000005 cmnos_report_failure_to_host +008e2128 g F .text 00000026 cmnos_intr_init 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_WindowOverflow8 +008e1230 g F .text 00000010 _xtos_set_interrupt_handler +008e5884 g F .text 00000017 _DMAengine_return_recv_buf +008e53c8 g F .text 0000001f HTCAllocMsgBuffer +008e50c0 g F .text 0000000d _HTC_RegisterService +004e881c g O .rodata 00000004 Xthal_xlmi_vaddr +008e35b4 g F .text 0000005e _HIFusb_send_buffer +00500ab4 g O .bss 00000004 fwCheckSum +008e294c g F .text 00000005 cmnos_printf_init +008e5448 g F .text 000000f8 HTCProcessConnectMsg +008e684c g F .text 00000000 xthal_get_interrupt +008e22b8 g F .text 0000001e cmnos_mem_module_install +008e21cc g F .text 00000064 cmnos_intr_attach_isr +004e87a5 g O .rodata 00000001 Xthal_have_nsa +008e6400 g F .text 00000000 xthal_window_spill +00500b5c g O .bss 00000004 Xthal_hw_max_version_minor +004e87e8 g O .rodata 00000001 Xthal_have_ccount +004e87bc g O .rodata 00000004 Xthal_hw_configid0 +008e68c4 g F .text 00000049 __modsi3 +008e1c0c g F .text 00000021 cmnos_allocram_debug +004e87b4 g O .rodata 00000002 Xthal_num_writebuffer_entries +008e3650 g F .text 00000005 _HIFusb_resume_recv +0050097a g O .bss 00000002 eep_exist +004e0160 g O .dport0.usb_in_rom 0000003c u8FSConfigDescriptor01 +22221221 g *ABS* 00000000 _memmap_cacheattr_reset +00000000 *UND* 00000000 download_write_flag +004e8794 g O .rodata 00000004 Xthal_release_name +22222222 g *ABS* 00000000 _memmap_cacheattr_bp_trapnull +008e0c26 g *ABS* 00000000 _DebugExceptionVector_text_end +008e08c0 g .WindowVectors.text 00000000 _WindowUnderflow8 +008e0a26 g *ABS* 00000000 _Level2InterruptVector_text_end +008e4fc0 g F .text 00000017 HTC_AssembleBuffers +008e1bcc g F .text 00000010 cmnos_allocram_init +008e5350 g F .text 00000005 _HTC_ResumeRecv +008e684c g F .text 00000000 xthal_get_intread +008e0e20 g .UserExceptionVector.text 00000000 _UserExceptionVector +008e3138 g F .text 00000005 __pci_start +00500b6f g O .bss 00000001 Xthal_num_datarom +008e1000 g .text 00000000 _stext +008e1ca8 g F .text 00000033 cmnos_clock_init +008e65d4 g F .text 00000000 strlen +008e596c g F .text 000000be _DMAengine_xmit_buf +008e4db4 g F .text 0000003b _vbuf_init +00500968 g O .bss 00000004 cmnos_skip_pll_init +008e2abc g F .text 00000005 cmnos_string_init +008e5fc0 g F .text 00000016 magpie_mdio_release_lock +00500adc g O .bss 00000004 u8String00Descriptor +008e1454 g F .text 0000000b athos_block_all_intrlvl +008e51a4 g F .text 00000037 _HTC_ReturnBuffersList +00500a34 g O .bss 00000004 timer_list +00022002 g *ABS* 00000000 _memmap_cacheattr_bp_base +008e4638 g F .text 000000d4 _usb_init +008e4864 g F .text 0000004a mUsbEPinHighBandSet +004e01a0 g O .dport0.usb_in_rom 00000004 String00Descriptor +008e0d00 g *ABS* 00000000 _KernelExceptionVector_literal_start +004e8704 g *ABS* 00000000 _dram0_rodata_end +00500400 g *ABS* 00000000 _dport0_bss_start +004e87f8 g O .rodata 00000004 Xthal_instram_vaddr +008e2fbc g F .text 000000b4 __pci_reset +008e1460 g F .text 00000008 athos_unblock_all_intrlvl +008e56d8 g F .text 00000005 RedistributeCredit +00500400 g *ABS* 00000000 _dport0_bss_end +004e87e7 g O .rodata 00000001 Xthal_num_dataram +00500730 g O .data 00000034 TestPatn1 +008e1df4 g F .text 00000060 cmnos_eep_write +008e0a00 g *ABS* 00000000 _Level2InterruptVector_literal_start +00500960 g O .bss 00000004 curr_band +00001b62 g *ABS* 00000000 xthals_release_major +008e2cec g F .text 0000001e cmnos_wdt_enable +004e01e0 g O .dport0.usb_in_rom 0000000c String30Descriptor +008e4d58 g F .text 00000023 __dma_recv_pkt +008e1143 g .text 00000000 _SyscallException +008e2dd0 g F .text 00000005 _uart_char_put_nothing +00500770 g O .data 0000000a u8DeviceQualifierDescriptorEX +004e87b1 g O .rodata 00000001 Xthal_have_threadptr +008e2e8c g F .text 00000027 _uart_config +008e4e94 g F .text 0000003d _vdesc_swap_vdesc +004e87a7 g O .rodata 00000001 Xthal_have_sext + + +Contents of section .lit4: + 4e8000 0053fff0 00040020 00500950 00500b78 .S..... .P.P.P.x + 4e8010 008e1240 008e12f4 00500400 008e1074 ...@.....P.....t + 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..Ah..?...:mdio do + 4e8a50 776e6c6f 61642072 65616479 0a000000 wnload ready.... + 4e8a60 362e2053 4e53543a 20686f73 74696620 6. SNST: hostif + 4e8a70 636f7272 7570740a 0d000000 52414d20 corrupt.....RAM + 4e8a80 616c6c6f 63617469 6f6e2028 25642062 allocation (%d b + 4e8a90 79746573 29206661 696c6564 210a0000 ytes) failed!... + 4e8aa0 414c4c4f 4352414d 20437572 72656e74 ALLOCRAM Current + 4e8ab0 20416464 72203078 25780a00 414c4c4f Addr 0x%x..ALLO + 4e8ac0 4352414d 2052656d 61696e69 6e672042 CRAM Remaining B + 4e8ad0 79746573 2025640a 00000000 2d453132 ytes %d.....-E12 + 4e8ae0 2d000000 2d453130 2d000000 2d453131 -...-E10-...-E11 + 4e8af0 2d000000 2d453133 2d000000 4d697361 -...-E13-...Misa + 4e8b00 6c69676e 6564206c 6f61643a 2070633d ligned load: pc= + 4e8b10 30782578 20626164 76616464 723d3078 0x%x badvaddr=0x + 4e8b20 25782064 756d7020 61726561 3d307825 %x dump area=0x% + 4e8b30 780a0000 61737365 7274696f 6e206661 x...assertion fa + 4e8b40 696c6564 3f207063 3d307825 782c206c iled? pc=0x%x, l + 4e8b50 696e653d 25642c20 64756d70 20617265 ine=%d, dump are + 4e8b60 613d3078 25780a00 54617267 65742049 a=0x%x..Target I + 4e8b70 443a2030 78257820 28256429 0a000000 D: 0x%x (%d).... + 4e8b80 44656275 6720496e 666f3a00 30782530 Debug Info:.0x%0 + 4e8b90 38782000 30313233 34353637 38390000 8x .0123456789.. + 4e8ba0 30313233 34353637 38396162 63646566 0123456789abcdef + 4e8bb0 00000000 30313233 34353637 38394142 ....0123456789AB + 4e8bc0 43444546 00000000 3c6e756c 6c3e0000 CDEF...... + 4e8bd0 09737a3a 2025642c 206c643a 2025702c .sz: %d, ld: %p, + 4e8be0 20666e3a 2025700d 00000000 21696e76 fn: %p.....!inv + 4e8bf0 616c6964 2064706f 72742061 64647265 alid dport addre + 4e8c00 73732c20 30782530 38780a0d 00000000 ss, 0x%08x...... + 4e8c10 63702025 64206279 74657320 66726f6d cp %d bytes from + 4e8c20 20307825 30387820 746f2030 78253038 0x%08x to 0x%08 + 4e8c30 78000000 702e6f66 743a2030 78253034 x...p.oft: 0x%04 + 4e8c40 782c2070 2e737a20 3a203078 25303478 x, p.sz : 0x%04x + 4e8c50 0a000000 57616974 696e6720 666f7220 ....Waiting for + 4e8c60 686f7374 20726573 65742e2e 00000000 host reset...... + 4e8c70 72656365 69766564 2e0a0000 42616420 received....Bad + 4e8c80 456e6769 6e65206e 756d6265 720a0000 Engine number... + 4e8c90 456d7074 79205258 20526561 700a0000 Empty RX Reap... + 4e8ca0 456d7074 79205458 20526561 70200a00 Empty TX Reap .. + 4e8cb0 496e7661 6c696420 50697065 206e756d Invalid Pipe num + 4e8cc0 6265720a 00000000 0a0d093d 3e5b646e ber........=>[dn + 4e8cd0 515d2030 78253038 78200a5b 00000000 Q] 0x%08x .[.... + 4e8ce0 093d3e5b 7570515d 20307825 30387820 .=>[upQ] 0x%08x + 4e8cf0 0a5b0000 093d3e5b 68702064 6e515d20 .[...=>[hp dnQ] + 4e8d00 30782530 3878200a 5b000000 093d3e5b 0x%08x .[....=>[ + 4e8d10 6d702064 6e515d20 30782530 3878200a mp dnQ] 0x%08x . + 4e8d20 5b000000 0a0d5b68 7020646e 515d2030 [.....[hp dnQ] 0 + 4e8d30 78253038 782c2000 444d4120 54524143 x%08x, .DMA TRAC + 4e8d40 45203078 25303878 0a0d2020 20205b00 E 0x%08x.. [. + 4e8d50 0a0d5b6d 7020646e 515d2030 78253038 ..[mp dnQ] 0x%08 + 4e8d60 782c2000 0a0d5b64 6e515d20 30782530 x, ...[dnQ] 0x%0 + 4e8d70 38782c20 00000000 0a0a0d5b 7570515d 8x, .......[upQ] + 4e8d80 20307825 3038782c 20000000 2d206375 0x%08x, ...- cu + 4e8d90 73746f6d 20757362 20636f6e 6669670a stom usb config. + 4e8da0 00000000 095b6355 53425f52 45515f44 .....[cUSB_REQ_D + 4e8db0 4f574e4c 4f41445d 3a203078 25303878 OWNLOAD]: 0x%08x + 4e8dc0 2c202530 32780a0d 00000000 090a0d3d , %02x.........= + 4e8dd0 3d3e5b63 5553425f 5245515f 434f4d50 =>[cUSB_REQ_COMP + 4e8de0 5d3a2030 78253038 780a0d00 636b7375 ]: 0x%08x...cksu + 4e8df0 6d3d2578 00000000 56656e64 6f72436d m=%x....VendorCm + 4e8e00 643a2044 6f776e6c 6f616443 6f6d706c d: DownloadCompl + 4e8e10 65746521 0a000000 7a665265 73657455 ete!....zfResetU + 4e8e20 53424649 464f0a0d 00000000 7a665475 SBFIFO......zfTu + 4e8e30 726e4f66 66506f77 65720a0d 00000000 rnOffPower...... + 4e8e40 47656e65 72617465 20457665 6e740a00 Generate Event.. + 4e8e50 215b534f 55524345 5f305d20 62697437 ![SOURCE_0] bit7 + 4e8e60 206f6e0a 0d000000 21555342 20726573 on.....!USB res + 4e8e70 65740a0d 00000000 21555342 20737573 et......!USB sus + 4e8e80 70656e64 0a0d0000 21555342 20726573 pend....!USB res + 4e8e90 756d650a 0d000000 362e2075 73625f68 ume.....6. usb_h + 4e8ea0 636c6b20 7264790a 0d000000 30782530 clk rdy.....0x%0 + 4e8eb0 38782854 295d0000 30782530 38782825 8x(T)]..0x%08x(% + 4e8ec0 63292d3e 00000000 0a0d2020 20000000 c)->...... ... + 4e8ed0 6d69692d 6d64696f 202d2072 65736574 mii-mdio - reset + 4e8ee0 202d2073 74617274 200a0000 6d69692d - start ...mii- + 4e8ef0 6d64696f 202d2072 65736574 202d2065 mdio - reset - e + 4e8f00 6e64200a 00000000 73746172 74656420 nd .....started + 4e8f10 72656365 6976696e 67206279 74657320 receiving bytes + 4e8f20 746f2025 78206c65 6e677468 2025640a to %x length %d. + 4e8f30 00000000 636f6d70 6c657465 64207265 ....completed re + 4e8f40 63656976 696e6720 62797465 7320746f ceiving bytes to + 4e8f50 20257820 6c656e67 74682025 640a0000 %x length %d... + 4e8f60 4669726d 77617265 20446f77 6e6c6f61 Firmware Downloa + 4e8f70 64206c65 6e677468 20307825 780a0000 d length 0x%x... + 4e8f80 4669726d 77617265 20457865 63204164 Firmware Exec Ad + 4e8f90 64726573 73203078 25780a00 4669726d dress 0x%x..Firm + 4e8fa0 77617265 20636865 636b7375 6d203078 ware checksum 0x + 4e8fb0 25780a00 4669726d 77617265 20636865 %x..Firmware che + 4e8fc0 636b7375 6d206661 696c6564 202d2072 cksum failed - r + 4e8fd0 65206e65 676f7469 6174696e 67200a00 e negotiating .. + 4e8fe0 4669726d 77617265 20446f77 6e6c6f61 Firmware Downloa + 4e8ff0 64206973 20676f6f 64200a00 434f4d4d d is good ..COMM + 4e9000 414e4420 544f2053 54415254 20464952 AND TO START FIR + 4e9010 4d574152 45205245 43454956 4544200a MWARE RECEIVED . + 4e9020 00000000 372e312e 30000000 4c58322e ....7.1.0...LX2. + 4e9030 312e3000 00500400 00500400 00500950 1.0..P...P...P.P + 4e9040 00500b78 .P.x +Contents of section .data: + 500400 008e67ec 008e1104 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00020007 f6800400 00000000 ................ + 0790 008e6ce4 00000074 00000000 00000000 ..l....t........ + 07a0 0000001c 00020007 f78d0400 00000000 ................ + 07b0 008e6424 00000118 00000000 00000000 ..d$............ + 07c0 0000001c 00020007 f89a0400 00000000 ................ + 07d0 008e653c 00000098 00000000 00000000 ..e<............ + 07e0 0000001c 00020007 f9a70400 00000000 ................ + 07f0 008e65d4 00000063 00000000 00000000 ..e....c........ + 0800 0000001c 00020007 fab40400 00000000 ................ + 0810 008e6638 0000008e 00000000 00000000 ..f8............ + 0820 0000001c 00020008 05dd0400 00000000 ................ + 0830 008e66c8 0000011b 00000000 00000000 ..f............. +Contents of section .debug_pubnames: + 0000 00000052 00020000 065c0000 00000000 ...R.....\...... + 0010 02f15f78 746f735f 7365745f 696e7465 .._xtos_set_inte + 0020 72727570 745f6861 6e646c65 725f6172 rrupt_handler_ar + 0030 67000000 03655f78 746f735f 7365745f g....e_xtos_set_ + 0040 696e7465 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nos_tasklet_sche + 0990 64756c65 00000047 e9636d6e 6f735f74 dule...G.cmnos_t + 09a0 61736b6c 65745f64 69736162 6c650000 asklet_disable.. + 09b0 00483c63 6d6e6f73 5f746173 6b6c6574 .H__pci_get + 0cd0 5f72785f 656e6700 0000487a 5f5f7063 _rx_eng...Hz__pc + 0ce0 695f656e 61626c65 00000048 ac5f5f70 i_enable...H.__p + 0cf0 63695f72 65736574 00000048 e05f5f70 ci_reset...H.__p + 0d00 63695f62 6f6f745f 696e6974 00000049 ci_boot_init...I + 0d10 045f5f70 63695f69 6e697400 0000493d .__pci_init...I= + 0d20 5f5f7063 695f6366 675f7069 70650000 __pci_cfg_pipe.. + 0d30 0049a95f 5f706369 5f737461 72740000 .I.__pci_start.. + 0d40 0049dd5f 5f706369 5f726567 5f63616c .I.__pci_reg_cal + 0d50 6c626163 6b000000 4a2d5f5f 7063695f lback...J-__pci_ + 0d60 72656170 5f786d69 74746564 0000004a reap_xmitted...J + 0d70 8c5f5f70 63695f72 6561705f 72656376 .__pci_reap_recv + 0d80 0000004a de5f5f70 63695f69 73725f68 ...J.__pci_isr_h + 0d90 616e646c 65720000 004b2a5f 5f706369 andler...K*__pci + 0da0 5f786d69 745f6275 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6164665f 6f735f61 74746163 685f6461 adf_os_attach_da + 0c140 74615f74 00000018 5a030000 18ad0400 ta_t....Z....... + 0c150 03000014 d9040009 5f5f6164 665f6f73 ........__adf_os + 0c160 5f646576 6963655f 74000000 18ce0961 _device_t......a + 0c170 64665f6f 735f6465 76696365 5f740000 df_os_device_t.. + 0c180 0018d506 00001879 01030000 19010400 .......y........ + 0c190 02010300 00190e04 00096164 665f6f73 ..........adf_os + 0c1a0 5f706d5f 74000000 040a0201 03000019 _pm_t........... + 0c1b0 28040014 04000019 680e4144 465f4f53 (.......h.ADF_OS + 0c1c0 5f425553 5f545950 455f5043 4900010e _BUS_TYPE_PCI... + 0c1d0 4144465f 4f535f42 55535f54 5950455f ADF_OS_BUS_TYPE_ + 0c1e0 47454e45 52494300 02000961 64665f6f GENERIC....adf_o + 0c1f0 735f6275 735f7479 70655f74 00000019 s_bus_type_t.... + 0c200 31096164 665f6f73 5f627573 5f726567 1.adf_os_bus_reg + 0c210 5f646174 615f7400 0000183b 03000003 _data_t....;.... + 0c220 22040007 5f616466 5f647276 5f696e66 "..._adf_drv_inf + 0c230 6f002000 001a4508 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f_os_dma_map_t.. + 0c340 001aa202 010d6164 665f6f73 5f636163 ......adf_os_cac + 0c350 68655f73 796e6300 0400001b 2c0e4144 he_sync.....,.AD + 0c360 465f5359 4e435f50 52455245 41440000 F_SYNC_PREREAD.. + 0c370 0e414446 5f53594e 435f5052 45575249 .ADF_SYNC_PREWRI + 0c380 54450002 0e414446 5f53594e 435f504f TE...ADF_SYNC_PO + 0c390 53545245 41440001 0e414446 5f53594e STREAD...ADF_SYN + 0c3a0 435f504f 53545752 49544500 03000961 C_POSTWRITE....a + 0c3b0 64665f6f 735f6361 6368655f 73796e63 df_os_cache_sync + 0c3c0 5f740000 001ac302 01096164 665f6f73 _t........adf_os + 0c3d0 5f73697a 655f7400 00001a65 0600001b _size_t....e.... + 0c3e0 47010961 64665f6f 735f646d 615f6d61 G..adf_os_dma_ma + 0c3f0 705f7400 00001aa9 0300001b 60040006 p_t.........`... + 0c400 0000040a 01030000 1aa90400 06000004 ................ + 0c410 0a010201 06000015 95010201 0473686f .............sho + 0c420 72742069 6e740005 0209415f 494e5431 rt int....A_INT1 + 0c430 36000000 1b9a095f 5f615f69 6e743136 6......__a_int16 + 0c440 5f740000 001ba709 615f696e 7431365f _t......a_int16_ + 0c450 74000000 1bb40473 69676e65 64206368 t......signed ch + 0c460 61720005 0109415f 494e5438 0000001b ar....A_INT8.... + 0c470 d4095f5f 615f696e 74385f74 0000001b ..__a_int8_t.... + 0c480 e309615f 696e7438 5f740000 001bef12 ..a_int8_t...... + 0c490 0c00001c 66087375 70706f72 74656400 ....f.supported. + 0c4a0 0000161a 02230008 61647665 7274697a .....#..advertiz + 0c4b0 65640000 00161a02 23040873 70656564 ed......#..speed + 0c4c0 0000001b c5022308 08647570 6c657800 ......#..duplex. + 0c4d0 00001bff 02230a08 6175746f 6e656700 .....#..autoneg. + 0c4e0 00001681 02230b00 0f000016 81060000 .....#.......... + 0c4f0 1c731005 00076164 665f6e65 745f6574 .s....adf_net_et + 0c500 68616464 72000600 001c9708 61646472 haddr.......addr + 0c510 0000001c 66022300 00095f5f 615f7569 ....f.#...__a_ui + 0c520 6e743136 5f740000 0012ef09 615f7569 nt16_t......a_ui + 0c530 6e743136 5f740000 001c9712 0e00001c nt16_t.......... + 0c540 fb086574 6865725f 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696f6e5f 7461626c indirection_tabl + 183f0 6500034c 000046e8 08636d6e 6f730000 e..L..F..cmnos.. + 18400 0045ba02 23000864 62670000 0003d403 .E..#..dbg...... + 18410 23b80308 68696600 000029a2 0323c003 #...hif...)..#.. + 18420 08687463 0000003b 150323f8 0308776d .htc...;..#...wm + 18430 695f7376 635f6170 69000000 45dc0323 i_svc_api...E..# + 18440 ac040875 73626669 666f5f61 70690000 ...usbfifo_api.. + 18450 0032cd03 23d80408 6275665f 706f6f6c .2..#...buf_pool + 18460 00000037 760323e4 04087662 75660000 ...7v.#...vbuf.. + 18470 0014b503 23800508 76646573 63000000 ....#...vdesc... + 18480 13970323 94050861 6c6c6f63 72616d00 ...#...allocram. + 18490 0000098d 0323a805 08646d61 5f656e67 .....#...dma_eng + 184a0 696e6500 0000444d 0323b405 08646d61 ine...DM.#...dma + 184b0 5f6c6962 0000002c 360323f4 05086869 _lib...,6.#...hi + 184c0 665f7063 69000000 2e960323 a8060009 f_pci......#.... + 184d0 5f415f6d 61677069 655f696e 64697265 _A_magpie_indire + 184e0 6374696f 6e5f7461 626c655f 74000000 ction_table_t... + 184f0 45ee1110 0000473e 08613000 000001af E.....G>.a0..... + 18500 02230008 61310000 0001af02 23040861 .#..a1......#..a + 18510 32000000 01af0223 08086133 00000001 2......#..a3.... + 18520 af02230c 000e0000 470b5000 00474b0f ..#.....G.P..GK. + 18530 04000758 54656e73 615f6578 63657074 ...XTensa_except + 18540 696f6e5f 6672616d 655f7300 80000048 ion_frame_s....H + 18550 2f087874 5f706300 000001af 02230008 /.xt_pc......#.. + 18560 78745f70 73000000 01af0223 04087874 xt_ps......#..xt + 18570 5f736172 00000001 af022308 0878745f _sar......#..xt_ + 18580 76707269 00000001 af02230c 0878745f vpri......#..xt_ + 18590 61320000 0001af02 23100878 745f6133 a2......#..xt_a3 + 185a0 00000001 af022314 0878745f 61340000 ......#..xt_a4.. + 185b0 0001af02 23180878 745f6135 00000001 ....#..xt_a5.... + 185c0 af02231c 0878745f 65786363 61757365 ..#..xt_exccause + 185d0 00000001 af022320 0878745f 6c636f75 ......# .xt_lcou + 185e0 6e740000 0001af02 23240878 745f6c62 nt......#$.xt_lb + 185f0 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MD_HANDLER...>.. + 1c780 5f574d49 5f444953 50415443 485f454e _WMI_DISPATCH_EN + 1c790 54525900 0800003e fa087043 6d644861 TRY....>..pCmdHa + 1c7a0 6e646c65 72000000 3e9a0223 0008436d ndler...>..#..Cm + 1c7b0 64494400 000012e9 02230408 466c6167 dID......#..Flag + 1c7c0 73000000 12e90223 0600075f 574d495f s......#..._WMI_ + 1c7d0 44495350 41544348 5f544142 4c450010 DISPATCH_TABLE.. + 1c7e0 00003f5b 08704e65 78740000 003f5b02 ..?[.pNext...?[. + 1c7f0 23000870 436f6e74 65787400 00000404 #..pContext..... + 1c800 02230408 4e756d62 65724f66 456e7472 .#..NumberOfEntr + 1c810 69657300 0000010f 02230808 70546162 ies......#..pTab + 1c820 6c650000 003f7a02 230c0003 00003efa le...?z.#.....>. + 1c830 04000957 4d495f44 49535041 5443485f ...WMI_DISPATCH_ + 1c840 454e5452 59000000 3eaf0300 003f6204 ENTRY...>....?b. + 1c850 00030000 3efa0400 09485443 5f425546 ....>....HTC_BUF + 1c860 5f434f4e 54455854 00000039 e80d574d _CONTEXT...9..WM + 1c870 495f4556 545f434c 41535300 04000040 I_EVT_CLASS....@ + 1c880 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ted_buf...C..# . + 1cda0 5f737761 705f6461 74610000 0043cc02 _swap_data...C.. + 1cdb0 2324085f 6861735f 636f6d70 6c5f7061 #$._has_compl_pa + 1cdc0 636b6574 73000000 43d90223 28085f64 ckets...C..#(._d + 1cdd0 6573635f 64756d70 00000043 7e02232c esc_dump...C~.#, + 1cde0 085f6765 745f7061 636b6574 00000043 ._get_packet...C + 1cdf0 e6022330 085f7265 636c6169 6d5f7061 ..#0._reclaim_pa + 1ce00 636b6574 00000043 ef022334 085f7075 cket...C..#4._pu + 1ce10 745f7061 636b6574 00000043 ef022338 t_packet...C..#8 + 1ce20 08705265 73657276 65640000 00040402 .pReserved...... + 1ce30 233c0009 5f415f63 6d6e6f73 5f696e64 #<.._A_cmnos_ind + 1ce40 69726563 74696f6e 5f746162 6c655f74 irection_table_t + 1ce50 00000030 a209574d 495f5356 435f4150 ...0..WMI_SVC_AP + 1ce60 49530000 00410b17 5f415f6d 61677069 IS...A.._A_magpi + 1ce70 655f696e 64697265 6374696f 6e5f7461 e_indirection_ta + 1ce80 626c6500 034c0000 46910863 6d6e6f73 ble..L..F..cmnos + 1ce90 00000045 63022300 08646267 00000003 ...Ec.#..dbg.... + 1cea0 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736b0000 000a7a02 2304085f 7461736b sk....z.#.._task + 1daf0 6c65745f 64697361 626c6500 00000a83 let_disable..... + 1db00 02230808 5f746173 6b6c6574 5f736368 .#.._tasklet_sch + 1db10 6564756c 65000000 0a830223 0c085f74 edule......#.._t + 1db20 61736b6c 65745f72 756e0000 00010b02 asklet_run...... + 1db30 23100002 01030000 0b160400 06000009 #............... + 1db40 72010300 000b1f04 00020103 00000b2c r.............., + 1db50 04000763 6c6f636b 5f617069 00240000 ...clock_api.$.. + 1db60 0c0e085f 636c6f63 6b5f696e 69740000 ..._clock_init.. + 1db70 000b1802 2300085f 636c6f63 6b726567 ....#.._clockreg + 1db80 735f696e 69740000 00010b02 2304085f s_init......#.._ + 1db90 75617274 5f667265 7175656e 63790000 uart_frequency.. + 1dba0 000b2502 2308085f 64656c61 795f7573 ..%.#.._delay_us + 1dbb0 0000000b 2e02230c 085f776c 616e5f62 ......#.._wlan_b + 1dbc0 616e645f 73657400 00000b2e 02231008 and_set......#.. + 1dbd0 5f726566 636c6b5f 73706565 645f6765 _refclk_speed_ge + 1dbe0 74000000 0b250223 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00285b02 2324085f andler...([.#$._ + 2a200 4854435f 436f6e74 726f6c53 76635072 HTC_ControlSvcPr + 2a210 6f636573 734d7367 00000039 5b022328 ocessMsg...9[.#( + 2a220 085f4854 435f436f 6e74726f 6c537663 ._HTC_ControlSvc + 2a230 50726f63 65737353 656e6443 6f6d706c ProcessSendCompl + 2a240 65746500 00003964 02232c08 70526573 ete...9d.#,.pRes + 2a250 65727665 64000000 04130223 30000768 erved......#0..h + 2a260 6f73745f 6170705f 61726561 5f730004 ost_app_area_s.. + 2a270 00003c6d 08776d69 5f70726f 746f636f ...# + 2b130 04000473 686f7274 20756e73 69676e65 ...short unsigne + 2b140 6420696e 74000702 0975696e 7431365f d int....uint16_ + 2b150 74000000 017c046c 6f6e6720 756e7369 t....|.long unsi + 2b160 676e6564 20696e74 00070409 75696e74 gned int....uint + 2b170 33325f74 00000001 a0077561 72745f66 32_t......uart_f + 2b180 69666f00 08000002 0e087374 6172745f ifo.......start_ + 2b190 696e6465 78000000 01920223 0008656e index......#..en + 2b1a0 645f696e 64657800 00000192 02230208 d_index......#.. + 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74000000 02c70223 .#.._uart......# + 2b2c0 04085f74 78000000 01c30223 08000600 .._tx......#.... + 2b2d0 0001b501 03000003 18040004 756e7369 ............unsi + 2b2e0 676e6564 20636861 72000701 0975696e gned char....uin + 2b2f0 74385f74 00000003 25020103 00000343 t8_t....%......C + 2b300 04000300 00033604 00060000 01920103 ......6......... + 2b310 00000353 04000201 03000003 60040002 ...S........`... + 2b320 01030000 03690400 02010300 00037204 .....i........r. + 2b330 00030000 011f0400 06000001 18010300 ................ + 2b340 00038204 00074442 5f434f4d 4d414e44 ......DB_COMMAND + 2b350 5f535452 55435400 0c000003 da08636d _STRUCT.......cm + 2b360 645f7374 72000000 037b0223 00086865 d_str....{.#..he + 2b370 6c705f73 74720000 00037b02 23040863 lp_str....{.#..c + 2b380 6d645f66 756e6300 00000388 02230800 md_func......#.. + 2b390 07646267 5f617069 00080000 040d085f .dbg_api......._ + 2b3a0 6462675f 696e6974 00000001 11022300 dbg_init......#. + 2b3b0 085f6462 675f7461 736b0000 00011102 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5f55494e 54363400 0000174e 095f5f61 _UINT64....N.__a + 2c730 5f75696e 7436345f 74000000 17680961 _uint64_t....h.a + 2c740 5f75696e 7436345f 74000000 17761404 _uint64_t....v.. + 2c750 000017d4 0e414446 5f4f535f 5245534f .....ADF_OS_RESO + 2c760 55524345 5f545950 455f4d45 4d00000e URCE_TYPE_MEM... + 2c770 4144465f 4f535f52 45534f55 5243455f ADF_OS_RESOURCE_ + 2c780 54595045 5f494f00 01000961 64665f6f TYPE_IO....adf_o + 2c790 735f7265 736f7572 63655f74 7970655f s_resource_type_ + 2c7a0 74000000 17981218 0000181e 08737461 t............sta + 2c7b0 72740000 00178802 23000865 6e640000 rt......#..end.. + 2c7c0 00178802 23080874 79706500 000017d4 ....#..type..... + 2c7d0 02231000 09616466 5f6f735f 7063695f .#...adf_os_pci_ + 2c7e0 6465765f 69645f74 00000017 05030000 dev_id_t........ + 2c7f0 181e0400 11040000 185d0870 63690000 .........].pci.. + 2c800 00183702 23000872 61770000 00040d02 ..7.#..raw...... + 2c810 23000011 10000018 7c087063 69000000 #.......|.pci... + 2c820 181e0223 00087261 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00041014 0400001a 970e415f 46414c53 ..........A_FALS + 2ca40 4500000e 415f5452 55450001 0009615f E...A_TRUE....a_ + 2ca50 626f6f6c 5f740000 001a7d03 00001505 bool_t....}..... + 2ca60 0400095f 5f616466 5f6f735f 646d615f ...__adf_os_dma_ + 2ca70 6d61705f 74000000 1aa50201 0d616466 map_t........adf + 2ca80 5f6f735f 63616368 655f7379 6e630004 _os_cache_sync.. + 2ca90 00001b2f 0e414446 5f53594e 435f5052 .../.ADF_SYNC_PR + 2caa0 45524541 4400000e 4144465f 53594e43 EREAD...ADF_SYNC + 2cab0 5f505245 57524954 4500020e 4144465f _PREWRITE...ADF_ + 2cac0 53594e43 5f504f53 54524541 4400010e SYNC_POSTREAD... + 2cad0 4144465f 53594e43 5f504f53 54575249 ADF_SYNC_POSTWRI + 2cae0 54450003 00096164 665f6f73 5f636163 TE....adf_os_cac + 2caf0 68655f73 796e635f 74000000 1ac60201 he_sync_t....... + 2cb00 09616466 5f6f735f 73697a65 5f740000 .adf_os_size_t.. + 2cb10 001a6806 00001b4a 01096164 665f6f73 ..h....J..adf_os + 2cb20 5f646d61 5f6d6170 5f740000 001aac03 _dma_map_t...... + 2cb30 00001b63 04000600 00040d01 0300001a ...c............ + 2cb40 ac040006 0000040d 01020106 00001598 ................ + 2cb50 01020104 73686f72 7420696e 74000502 ....short int... + 2cb60 09415f49 4e543136 0000001b 9d095f5f .A_INT16......__ + 2cb70 615f696e 7431365f 74000000 1baa0961 a_int16_t......a + 2cb80 5f696e74 31365f74 0000001b b7047369 _int16_t......si + 2cb90 676e6564 20636861 72000501 09415f49 gned char....A_I + 2cba0 4e543800 00001bd7 095f5f61 5f696e74 NT8......__a_int + 2cbb0 385f7400 00001be6 09615f69 6e74385f 8_t......a_int8_ + 2cbc0 74000000 1bf2120c 00001c69 08737570 t..........i.sup + 2cbd0 706f7274 65640000 00161d02 23000861 ported......#..a + 2cbe0 64766572 74697a65 64000000 161d0223 dvertized......# + 2cbf0 04087370 65656400 00001bc8 02230808 ..speed......#.. + 2cc00 6475706c 65780000 001c0202 230a0861 duplex......#..a + 2cc10 75746f6e 65670000 00168402 230b000f utoneg......#... + 2cc20 00001684 0600001c 76100500 07616466 ........v....adf + 2cc30 5f6e6574 5f657468 61646472 00060000 _net_ethaddr.... + 2cc40 1c9a0861 64647200 00001c69 02230000 ...addr....i.#.. + 2cc50 095f5f61 5f75696e 7431365f 74000000 .__a_uint16_t... + 2cc60 12f20961 5f75696e 7431365f 74000000 ...a_uint16_t... + 2cc70 1c9a120e 00001cfe 08657468 65725f64 .........ether_d + 2cc80 686f7374 0000001c 69022300 08657468 host....i.#..eth + 2cc90 65725f73 686f7374 0000001c 69022306 er_shost....i.#. + 2cca0 08657468 65725f74 79706500 00001cac .ether_type..... + 2ccb0 02230c00 12140000 1dbf1569 705f7665 .#.........ip_ve + 2ccc0 7273696f 6e000000 16840100 04022300 rsion.........#. + 2ccd0 1569705f 686c0000 00168401 04040223 .ip_hl.........# + 2cce0 00086970 5f746f73 00000016 84022301 ..ip_tos......#. + 2ccf0 0869705f 6c656e00 00001cac 02230208 .ip_len......#.. + 2cd00 69705f69 64000000 1cac0223 04086970 ip_id......#..ip + 2cd10 5f667261 675f6f66 66000000 1cac0223 _frag_off......# + 2cd20 06086970 5f74746c 00000016 84022308 ..ip_ttl......#. + 2cd30 0869705f 70726f74 6f000000 16840223 .ip_proto......# + 2cd40 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....WMI_EVT_CLAS + 41220 535f434d 445f4556 454e5400 000e574d S_CMD_EVENT...WM + 41230 495f4556 545f434c 4153535f 434d445f I_EVT_CLASS_CMD_ + 41240 5245504c 5900010e 574d495f 4556545f REPLY...WMI_EVT_ + 41250 434c4153 535f4d41 58000200 09574d49 CLASS_MAX....WMI + 41260 5f455654 5f434c41 53530000 003f9e07 _EVT_CLASS...?.. + 41270 5f574d49 5f425546 5f434f4e 54455854 _WMI_BUF_CONTEXT + 41280 000c0000 40710848 74634275 66437478 ....@q.HtcBufCtx + 41290 0000003f 89022300 08457665 6e74436c ...?..#..EventCl + 412a0 61737300 00004013 02230408 466c6167 ass...@..#..Flag + 412b0 73000000 12ea0223 08000977 6d695f68 s......#...wmi_h + 412c0 616e646c 655f7400 00000405 09574d49 andle_t......WMI + 412d0 5f535643 5f434f4e 46494700 00003e29 _SVC_CONFIG...>) + 412e0 03000040 83040006 00004071 01030000 ...@......@q.... + 412f0 409e0400 09574d49 5f444953 50415443 @....WMI_DISPATC + 41300 485f5441 424c4500 00003efb 03000040 H_TABLE...>....@ + 41310 ab040002 01030000 40ca0400 06000026 ........@......& + 41320 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696e6f72 al_release_minor + 7ca90 00000000 f2050300 500b4401 02636861 ........P.D..cha + 7caa0 72000701 03000001 37030000 01370500 r.......7....7.. + 7cab0 00014404 00030000 01490300 00013705 ..D......I....7. + 7cac0 00000155 04000458 7468616c 5f72656c ...U...Xthal_rel + 7cad0 65617365 5f6e616d 65000000 01500503 ease_name....P.. + 7cae0 004e8794 01060000 01370600 00018d07 .N.......7...... + 7caf0 05000458 7468616c 5f72656c 65617365 ...Xthal_release + 7cb00 5f696e74 65726e61 6c000000 01500503 _internal....P.. + 7cb10 00500b48 01045874 68616c5f 7265765f .P.H..Xthal_rev_ + 7cb20 6e6f0000 0000f205 03004e87 98010458 no........N....X + 7cb30 7468616c 5f6e756d 5f617265 67730000 thal_num_aregs.. + 7cb40 0000f205 03004e87 9c010275 6e736967 ......N....unsig + 7cb50 6e656420 63686172 00070103 000001e5 ned char........ + 7cb60 04587468 616c5f6e 756d5f61 72656773 .Xthal_num_aregs + 7cb70 5f6c6f67 32000000 01f60503 004e87a0 _log2........N.. + 7cb80 01045874 68616c5f 6d656d6f 72795f6f ..Xthal_memory_o + 7cb90 72646572 00000001 f6050300 4e87a101 rder........N... + 7cba0 04587468 616c5f68 6176655f 77696e64 .Xthal_have_wind + 7cbb0 6f776564 00000001 f6050300 4e87a201 owed........N... + 7cbc0 04587468 616c5f68 6176655f 64656e73 .Xthal_have_dens + 7cbd0 69747900 000001f6 0503004e 87a30104 ity........N.... + 7cbe0 58746861 6c5f6861 76655f62 6f6f6c65 Xthal_have_boole + 7cbf0 616e7300 000001f6 05030050 0b4c0104 ans........P.L.. + 7cc00 58746861 6c5f6861 76655f6c 6f6f7073 Xthal_have_loops + 7cc10 00000001 f6050300 4e87a401 04587468 ........N....Xth + 7cc20 616c5f68 6176655f 6e736100 000001f6 al_have_nsa..... + 7cc30 0503004e 87a50104 58746861 6c5f6861 ...N....Xthal_ha + 7cc40 76655f6d 696e6d61 78000000 01f60503 ve_minmax....... + 7cc50 004e87a6 01045874 68616c5f 68617665 .N....Xthal_have + 7cc60 5f736578 74000000 01f60503 004e87a7 _sext........N.. + 7cc70 01045874 68616c5f 68617665 5f636c61 ..Xthal_have_cla + 7cc80 6d707300 000001f6 05030050 0b4d0104 mps........P.M.. + 7cc90 58746861 6c5f6861 76655f6d 61633136 Xthal_have_mac16 + 7cca0 00000001 f6050300 500b4e01 04587468 ........P.N..Xth + 7ccb0 616c5f68 6176655f 6d756c31 36000000 al_have_mul16... + 7ccc0 01f60503 004e87a8 01045874 68616c5f .....N....Xthal_ + 7ccd0 68617665 5f667000 000001f6 05030050 have_fp........P + 7cce0 0b4f0104 58746861 6c5f6861 76655f73 .O..Xthal_have_s + 7ccf0 70656375 6c617469 6f6e0000 0001f605 peculation...... + 7cd00 0300500b 50010458 7468616c 5f686176 ..P.P..Xthal_hav + 7cd10 655f6578 63657074 696f6e73 00000001 e_exceptions.... + 7cd20 f6050300 4e87a901 04587468 616c5f78 ....N....Xthal_x + 7cd30 65615f76 65727369 6f6e0000 0001f605 ea_version...... + 7cd40 03004e87 aa010458 7468616c 5f686176 ..N....Xthal_hav + 7cd50 655f696e 74657272 75707473 00000001 e_interrupts.... + 7cd60 f6050300 4e87ab01 04587468 616c5f68 ....N....Xthal_h + 7cd70 6176655f 68696768 6c657665 6c5f696e ave_highlevel_in + 7cd80 74657272 75707473 00000001 f6050300 terrupts........ + 7cd90 4e87ac01 04587468 616c5f68 6176655f N....Xthal_have_ + 7cda0 6e6d6900 000001f6 0503004e 87ad0104 nmi........N.... + 7cdb0 58746861 6c5f6861 76655f70 72696400 Xthal_have_prid. + 7cdc0 000001f6 0503004e 87ae0104 58746861 .......N....Xtha + 7cdd0 6c5f6861 76655f72 656c6561 73655f73 l_have_release_s + 7cde0 796e6300 000001f6 0503004e 87af0104 ync........N.... + 7cdf0 58746861 6c5f6861 76655f73 33326331 Xthal_have_s32c1 + 7ce00 69000000 01f60503 004e87b0 01045874 i........N....Xt + 7ce10 68616c5f 68617665 5f746872 65616470 hal_have_threadp + 7ce20 74720000 0001f605 03004e87 b1010458 tr........N....X + 7ce30 7468616c 5f686176 655f7069 66000000 thal_have_pif... + 7ce40 01f60503 004e87b2 01027368 6f727420 .....N....short + 7ce50 756e7369 676e6564 20696e74 00070203 unsigned int.... + 7ce60 000004e4 04587468 616c5f6e 756d5f77 .....Xthal_num_w + 7ce70 72697465 62756666 65725f65 6e747269 ritebuffer_entri + 7ce80 65730000 0004fa05 03004e87 b4010458 es........N....X + 7ce90 7468616c 5f627569 6c645f75 6e697175 thal_build_uniqu + 7cea0 655f6964 00000000 f2050300 4e87b801 e_id........N... + 7ceb0 04587468 616c5f68 775f636f 6e666967 .Xthal_hw_config + 7cec0 69643000 000000f2 0503004e 87bc0104 id0........N.... + 7ced0 58746861 6c5f6877 5f636f6e 66696769 Xthal_hw_configi + 7cee0 64310000 0000f205 03004e87 c0010458 d1........N....X + 7cef0 7468616c 5f68775f 72656c65 6173655f thal_hw_release_ + 7cf00 6d616a6f 72000000 00f20503 004e87c4 major........N.. + 7cf10 01045874 68616c5f 68775f72 656c6561 ..Xthal_hw_relea + 7cf20 73655f6d 696e6f72 00000000 f2050300 se_minor........ + 7cf30 500b5401 04587468 616c5f68 775f7265 P.T..Xthal_hw_re + 7cf40 6c656173 655f6e61 6d650000 00015005 lease_name....P. + 7cf50 03004e87 c8010600 00013708 000005fe ..N.......7..... + 7cf60 07070004 58746861 6c5f6877 5f6d696e ....Xthal_hw_min + 7cf70 5f766572 73696f6e 5f6d616a 6f720000 _version_major.. + 7cf80 0000f205 03004e87 cc010458 7468616c ......N....Xthal + 7cf90 5f68775f 6d696e5f 76657273 696f6e5f _hw_min_version_ + 7cfa0 6d696e6f 72000000 00f20503 00500b58 minor........P.X + 7cfb0 01045874 68616c5f 68775f6d 61785f76 ..Xthal_hw_max_v + 7cfc0 65727369 6f6e5f6d 616a6f72 00000000 ersion_major.... + 7cfd0 f2050300 4e87d001 04587468 616c5f68 ....N....Xthal_h + 7cfe0 775f6d61 785f7665 7273696f 6e5f6d69 w_max_version_mi + 7cff0 6e6f7200 000000f2 05030050 0b5c0104 nor........P.\.. + 7d000 58746861 6c5f6877 5f72656c 65617365 Xthal_hw_release + 7d010 5f696e74 65726e61 6c000000 01500503 _internal....P.. + 7d020 00500b60 01045874 68616c5f 68617665 .P.`..Xthal_have + 7d030 5f737061 6e6e696e 675f7761 79000000 _spanning_way... + 7d040 01f60503 004e87d4 01045874 68616c5f .....N....Xthal_ + 7d050 68617665 5f696465 6e746974 795f6d61 have_identity_ma + 7d060 70000000 01f60503 004e87d5 01045874 p........N....Xt + 7d070 68616c5f 68617665 5f6d696d 69635f63 hal_have_mimic_c + 7d080 61636865 61747472 00000001 f6050300 acheattr........ + 7d090 4e87d601 04587468 616c5f68 6176655f N....Xthal_have_ + 7d0a0 786c745f 63616368 65617474 72000000 xlt_cacheattr... + 7d0b0 01f60503 00500b64 01045874 68616c5f .....P.d..Xthal_ + 7d0c0 68617665 5f636163 68656174 74720000 have_cacheattr.. + 7d0d0 0001f605 0300500b 65010458 7468616c ......P.e..Xthal + 7d0e0 5f686176 655f746c 62730000 0001f605 _have_tlbs...... + 7d0f0 03004e87 d7010458 7468616c 5f6d6d75 ..N....Xthal_mmu + 7d100 5f617369 645f6269 74730000 0001f605 _asid_bits...... + 7d110 0300500b 66010458 7468616c 5f6d6d75 ..P.f..Xthal_mmu + 7d120 5f617369 645f6b65 726e656c 00000001 _asid_kernel.... + 7d130 f6050300 500b6701 04587468 616c5f6d ....P.g..Xthal_m + 7d140 6d755f72 696e6773 00000001 f6050300 mu_rings........ + 7d150 4e87d801 04587468 616c5f6d 6d755f72 N....Xthal_mmu_r + 7d160 696e675f 62697473 00000001 f6050300 ing_bits........ + 7d170 500b6801 04587468 616c5f6d 6d755f73 P.h..Xthal_mmu_s + 7d180 725f6269 74730000 0001f605 0300500b r_bits........P. + 7d190 69010458 7468616c 5f6d6d75 5f63615f i..Xthal_mmu_ca_ + 7d1a0 62697473 00000001 f6050300 4e87d901 bits........N... + 7d1b0 04587468 616c5f6d 6d755f6d 61785f70 .Xthal_mmu_max_p + 7d1c0 74655f70 6167655f 73697a65 00000000 te_page_size.... + 7d1d0 f2050300 4e87dc01 04587468 616c5f6d ....N....Xthal_m + 7d1e0 6d755f6d 696e5f70 74655f70 6167655f mu_min_pte_page_ + 7d1f0 73697a65 00000000 f2050300 4e87e001 size........N... + 7d200 04587468 616c5f69 746c625f 7761795f .Xthal_itlb_way_ + 7d210 62697473 00000001 f6050300 500b6a01 bits........P.j. + 7d220 04587468 616c5f69 746c625f 77617973 .Xthal_itlb_ways + 7d230 00000001 f6050300 4e87e401 04587468 ........N....Xth + 7d240 616c5f69 746c625f 6172665f 77617973 al_itlb_arf_ways + 7d250 00000001 f6050300 500b6b01 04587468 ........P.k..Xth + 7d260 616c5f64 746c625f 7761795f 62697473 al_dtlb_way_bits + 7d270 00000001 f6050300 500b6c01 04587468 ........P.l..Xth + 7d280 616c5f64 746c625f 77617973 00000001 al_dtlb_ways.... + 7d290 f6050300 4e87e501 04587468 616c5f64 ....N....Xthal_d + 7d2a0 746c625f 6172665f 77617973 00000001 tlb_arf_ways.... + 7d2b0 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..........e..... + 4c70 00000008 008e65f0 0000000a 000200a2 ......e......... + 4c80 008e65fa 00000011 000200a2 008e660b ..e...........f. + 4c90 00000000 00002808 008e660c 00000002 ......(...f..... + 4ca0 000201a2 008e660e 00000013 00020082 ......f......... + 4cb0 008e6621 00000002 000200b2 008e6623 ..f!..........f# + 4cc0 00000005 000200a2 008e6628 00000000 ..........f(.... + 4cd0 00000008 008e6628 00000007 000200a2 ......f(........ + 4ce0 008e662f 00000001 00000008 008e6630 ..f/..........f0 + 4cf0 00000007 000200a2 008e6637 00000000 ..........f7.... + 4d00 00000008 004e86fc 00000000 00002804 .....N........(. + 4d10 008e6638 0000000f 00020082 008e6647 ..f8..........fG + 4d20 00000028 000200a2 008e666f 00000003 ...(......fo.... + 4d30 00020092 008e6672 00000000 00000008 ......fr........ + 4d40 008e6672 00000004 000200a2 008e6676 ..fr..........fv + 4d50 00000002 00000008 008e6678 00000005 ..........fx.... + 4d60 00020082 008e667d 00000000 00000008 ......f}........ + 4d70 008e667d 0000000b 000200a2 008e6688 ..f}..........f. + 4d80 00000000 00000008 008e6688 00000015 ..........f..... + 4d90 000200a2 008e669d 00000000 00000008 ......f......... + 4da0 008e669d 00000021 000200a2 008e66be ..f....!......f. + 4db0 00000000 00000008 008e66be 00000004 ..........f..... + 4dc0 000200a2 008e66c2 00000000 00000008 ......f......... + 4dd0 008e66c2 00000004 000200a2 008e66c6 ..f...........f. + 4de0 00000000 00000008 004e86fc 00000004 .........N...... + 4df0 00002804 008e66c8 00000014 000200a2 ..(...f......... + 4e00 008e66dc 00000021 000200a2 008e66fd ..f....!......f. + 4e10 00000000 00000008 008e66fd 00000002 ..........f..... + 4e20 000200a2 008e66ff 00000000 00002808 ......f.......(. + 4e30 008e6700 0000001a 00020082 008e671a ..g...........g. + 4e40 00000008 000200a2 008e6722 00000000 ..........g".... + 4e50 00000008 008e6722 00000008 000200a2 ......g"........ + 4e60 008e672a 0000000f 000200a2 008e6739 ..g*..........g9 + 4e70 00000008 00020092 008e6741 0000000b ..........gA.... + 4e80 000200a2 008e674c 00000002 000200a2 ......gL........ + 4e90 008e674e 00000002 00000008 008e6750 ..gN..........gP + 4ea0 0000000d 000200a2 008e675d 00000015 ..........g].... + 4eb0 000200a2 008e6772 00000000 00002808 ......gr......(. + 4ec0 008e6774 00000002 000201a2 008e6776 ..gt..........gv + 4ed0 0000001d 00020082 008e6793 00000003 ..........g..... + 4ee0 00020092 008e6796 00000000 00000008 ......g......... + 4ef0 008e6796 0000000c 000200a2 008e67a2 ..g...........g. + 4f00 00000002 00000008 008e67a4 0000000e ..........g..... + 4f10 000200a2 008e67b2 00000002 00000008 ......g......... + 4f20 008e67b4 00000013 000200a2 008e67c7 ..g...........g. + 4f30 00000000 00002808 008e67c8 00000002 ......(...g..... + 4f40 000201a2 008e67ca 00000014 00020082 ......g......... + 4f50 008e67de 00000003 000200b2 008e67e1 ..g...........g. + 4f60 00000000 00000008 008e67e1 00000002 ..........g..... + 4f70 000200a2 008e67e3 00000000 00000008 ......g......... + 4f80 004e8704 00000000 00002804 .N........(. +Contents of section .xt.lit: + 0000 008e0004 00000018 ........ +Contents of section .xtensa.info: + 0000 0000000c 0000019c 00000001 5874656e ............Xten + 0010 73615f49 6e666f00 48575f43 4f4e4649 sa_Info.HW_CONFI + 0020 47494430 3d307863 32383064 6266660a GID0=0xc280dbff. + 0030 48575f43 4f4e4649 47494431 3d307830 HW_CONFIGID1=0x0 + 0040 64303232 3330660a 4255494c 445f554e d02230f.BUILD_UN + 0050 49515545 5f49443d 30783030 30323233 IQUE_ID=0x000223 + 0060 30660a41 42493d30 0a555345 5f414253 0f.ABI=0.USE_ABS + 0070 4f4c5554 455f4c49 54455241 4c533d31 OLUTE_LITERALS=1 + 0080 0a48575f 56455253 494f4e3d 224c5832 .HW_VERSION="LX2 + 0090 2e312e30 220a4857 5f4d494e 5f564552 .1.0".HW_MIN_VER + 00a0 53494f4e 5f4d414a 4f523d32 3231300a SION_MAJOR=2210. + 00b0 48575f4d 494e5f56 45525349 4f4e5f4d HW_MIN_VERSION_M + 00c0 494e4f52 3d300a48 575f4d41 585f5645 INOR=0.HW_MAX_VE + 00d0 5253494f 4e5f4d41 4a4f523d 32323130 RSION_MAJOR=2210 + 00e0 0a48575f 4d41585f 56455253 494f4e5f .HW_MAX_VERSION_ + 00f0 4d494e4f 523d300a 52454c45 4153455f MINOR=0.RELEASE_ + 0100 4e414d45 3d225242 2d323030 372e3222 NAME="RB-2007.2" + 0110 0a52454c 45415345 5f564552 53494f4e .RELEASE_VERSION + 0120 3d22372e 312e3022 0a52454c 45415345 ="7.1.0".RELEASE + 0130 5f4d414a 4f523d37 3031300a 52454c45 _MAJOR=7010.RELE + 0140 4153455f 4d494e4f 523d300a 434f5245 ASE_MINOR=0.CORE + 0150 5f4e414d 453d224d 61677069 655f5030 _NAME="Magpie_P0 + 0160 220a5449 455f4348 45434b53 554d5f30 ".TIE_CHECKSUM_0 + 0170 3d300a54 49455f43 4845434b 53554d5f =0.TIE_CHECKSUM_ + 0180 313d300a 5449455f 43484543 4b53554d 1=0.TIE_CHECKSUM + 0190 5f323d30 0a544945 5f434845 434b5355 _2=0.TIE_CHECKSU + 01a0 4d5f333d 300a5444 4b5f5041 54483d22 M_3=0.TDK_PATH=" + 01b0 220a0000 "... +Disassembly of section .lit4: + +004e8000 <.lit4>: + 4e8000: 0053fff0 00040020 00500950 00500b78 .S..... .P.P.P.x + +004e8010 <.lit4+0x10>: + 4e8010: 008e1240 008e12f4 ...@.... + +004e8018 <.lit4+0x18>: + 4e8018: 00500400 008e1074 .P.....t + +004e8020 <.lit4+0x20>: + 4e8020: 00050023 ...# + +004e8024 <.lit4+0x24>: + 4e8024: 80000007 .... + +004e8028 <.lit4+0x28>: + 4e8028: c0000000 00500598 008e67fc .....P....g. + +004e8034 <.lit4+0x34>: + 4e8034: 004e8830 00500508 008e67e4 .N.0.P....g. + +004e8040 <.lit4+0x40>: + 4e8040: 00007ffe 008e12e8 ........ + +004e8048 <.lit4+0x48>: + 4e8048: 00038000 008e1399 ........ + +004e8050 <.lit4+0x50>: + 4e8050: 004e8730 0053fe00 00520e00 40000000 .N.0.S...R..@... + 4e8060: 00500000 004e8850 004e885c 004e8898 .P...N.P.N.\.N.. + 4e8070: 004e88a0 004e88b4 004e88f8 004e8928 .N...N...N...N.( + 4e8080: 00500640 005006f8 00500100 008e6844 .P.@.P...P....hD + 4e8090: 008e6854 008e684c 008e1460 008e1454 ..hT..hL...`...T + 4e80a0: 008e1468 008e1428 008e1474 008e14d4 ...h...(...t.... + 4e80b0: 008e1604 02625a00 004e8944 004e8958 .....bZ..N.D.N.X + 4e80c0: 41544852 10000000 00500b7c 00500b9c ATHR.....P.|.P.. + 4e80d0: 00500ba8 00500bc0 00500be0 0004fe00 .P...P...P...... + 4e80e0: 0005be00 00051e00 fffeefef 004e8960 .............N.` + 4e80f0: 13fffe00 a55a0000 00036000 00000b7c .....Z....`....| + 4e8100: 004e8974 008e1860 004e8988 008e189c .N.t...`.N...... + 4e8110: 00500978 008e18fc 004e89a4 004e89a8 .P.x.....N...N.. + 4e8120: 00500950 20000000 004e89d8 004e89f8 .P.P ....N...N.. + 4e8130: 004e8a08 004e8a18 004e8a28 00530000 .N...N...N.(.S.. + 4e8140: 00010000 004e8a38 004e8a44 004e8a60 .....N.8.N.D.N.` + 4e8150: 004e89bc 004e89ac 008e1bac .N...N...... + +004e815c <.lit4+0x15c>: + 4e815c: 00500954 004e8a7c 004e8aa0 004e8abc .P.T.N.|.N...N.. + 4e816c: 008e1bcc 008e1bdc ........ + +004e8174 <.lit4+0x174>: + 4e8174: 008e1c0c .... + +004e8178 <.lit4+0x178>: + 4e8178: 0050095c 000c3500 fff3cb00 004e8740 .P.\..5......N.@ + 4e8188: 00500974 008e1ca8 008e1c90 008e1c44 .P.t...........D + 4e8198: 008e1c98 008e1c74 008e1c64 008e1c80 .......t...d.... + 4e81a8: 008e1c88 .... + +004e81ac <.lit4+0x1ac>: + 4e81ac: 008e1cdc .... + +004e81b0 <.lit4+0x1b0>: + 4e81b0: 00020000 10ff3e00 10ff2000 00000fff ......>... ..... + 4e81c0: 004e8aec 004e8adc 004e8ae4 004e8af4 .N...N...N...N.. + 4e81d0: 5f574454 0003fe00 0001fe00 0000ffc1 _WDT............ + 4e81e0: 04000000 10ff0000 10ff1e00 000c0000 ................ + 4e81f0: 008e1e9c 008e1e54 008e1df4 .......T.... + +004e81fc <.lit4+0x1fc>: + 4e81fc: 008e1dbc .... + +004e8200 <.lit4+0x200>: + 4e8200: 00500980 008e2120 004e0600 004e0601 .P....! .N...N.. + 4e8210: 00500990 004e0771 008e2128 008e2230 .P...N.q..!(.."0 + 4e8220: 008e21cc 008e2150 ..!...!P + +004e8228 <.lit4+0x228>: + 4e8228: 008e2190 ..!. + +004e822c <.lit4+0x22c>: + 4e822c: 008e22b0 008e6d0c 008e6a28 008e6b20 .."...m...j(..k + +004e823c <.lit4+0x23c>: + 4e823c: 008e69a0 ..i. + +004e8240 <.lit4+0x240>: + 4e8240: 01000000 fffe000f 004e0001 004e8afc .........N...N.. + 4e8250: 00500a28 005006f8 004e8b34 004e8b68 .P.(.P...N.4.N.h + 4e8260: 004e8b80 004e8970 004e8b8c 004e0100 .N...N.p.N...N.. + 4e8270: 008e22d8 008e22ec 008e2348 008e22f4 .."..."...#H..". + 4e8280: 008e23b4 008e23f4 008e23c4 ..#...#...#. + +004e828c <.lit4+0x28c>: + 4e828c: 008e2414 ..$. + +004e8290 <.lit4+0x290>: + 4e8290: 004e8ba0 004e8bc8 004e8b94 004e8bb4 .N...N...N...N.. + 4e82a0: 00500700 008e294c .P....)L + +004e82a8 <.lit4+0x2a8>: + 4e82a8: 008e2918 ..). + +004e82ac <.lit4+0x2ac>: + 4e82ac: 004e8bd0 ffb00000 0003ffff 004e8bec .N...........N.. + 4e82bc: 004e8c10 00500704 00500a2c 004e8c34 .N...P...P.,.N.4 + 4e82cc: 0053c000 008e2a98 008e2a34 008e2a24 .S....*...*4..*$ + +004e82dc <.lit4+0x2dc>: + 4e82dc: 008e29e8 ..). + +004e82e0 <.lit4+0x2e0>: + 4e82e0: 008e2abc 008e653c 008e6700 008e65d4 ..*...e<..g...e. + 4e82f0: 008e6424 ..d$ + +004e82f4 <.lit4+0x2f4>: + 4e82f4: 008e6638 ..f8 + +004e82f8 <.lit4+0x2f8>: + 4e82f8: 00500a30 008e2ae8 008e2af4 008e2b20 .P.0..*...*...+ + 4e8308: 008e2b04 ..+. + +004e830c <.lit4+0x30c>: + 4e830c: 008e2b54 ..+T + +004e8310 <.lit4+0x310>: + 4e8310: 00500a34 00009c40 008e2c20 008e2bac .P.4...@.., ..+. + 4e8320: 008e2bf0 008e2b9c ..+...+. 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../...1...1T../. + 4e83f8: 008e2f44 008e2f80 ../D../. + +004e8400 <.lit4+0x400>: + 4e8400: 008e2f6c ../l + +004e8404 <.lit4+0x404>: + 4e8404: 00500a54 008e3348 008e335c 008e3394 .P.T..3H..3\..3. + 4e8414: 008e33b4 00500a60 00500a68 00500a78 ..3..P.`.P.h.P.x + 4e8424: 00500a80 004e8cc8 004e8ce0 00055a00 .P...N...N....Z. + 4e8434: 00055600 004e8cf4 004e8d0c 00054e00 ..V..N...N....N. + 4e8444: 00010007 008e33c8 008e3438 008e3508 ......3...48..5. + 4e8454: 008e367c 008e35b4 008e3614 008e3658 ..6|..5...6...6X + 4e8464: 008e3668 008e3424 008e341c 008e34b4 ..6h..4$..4...4. + 4e8474: 008e372c 004e8d24 004e8d38 004e8d50 ..7,.N.$.N.8.N.P + 4e8484: 004e8d64 004e8d78 .N.d.N.x + +004e848c <.lit4+0x48c>: + 4e848c: 00500a98 0000ff80 0000fe00 00500620 .P...........P. + 4e849c: 00500730 007efdfb 00500780 00500770 .P.0.~...P...P.p + 4e84ac: 004e8d8c 004e01a0 004e01b0 004e01c0 .N...N...N...N.. + 4e84bc: 004e01e0 008e3efc 004e8dcc 004e8dec .N....>..N...N.. + 4e84cc: 08000000 004e8da4 004e8df8 f7ffffff .....N...N...... + 4e84dc: 004e0160 004e0120 00010080 004e8e18 .N.`.N. .....N.. + 4e84ec: 004e8e2c 0000c600 004e8e40 004e8e50 .N.,.....N.@.N.P + 4e84fc: 004e8e68 004e8e78 004e8e88 004e8e98 .N.h.N.x.N...N.. + 4e850c: 008e4208 008e41ec 008e4638 008e43a0 ..B...A...F8..C. + 4e851c: 008e4468 008e4168 008e3ff0 008e3c6c ..Dh..Ah..?...: + 4e857c: 008e4594 ..E. + +004e8580 <.lit4+0x580>: + 4e8580: 00500ace 00500ad0 00500ad2 .P...P...P.. + +004e858c <.lit4+0x58c>: + 4e858c: 005007c0 00053000 00054000 008e4ba8 .P....0...@...K. + 4e859c: 008e4c40 008e4bf0 008e4c6c 008e4cb0 ..L@..K...Ll..L. + 4e85ac: 008e4cec 008e4d14 008e4c94 008e4d30 ..L...M...L...M0 + +004e85bc <.lit4+0x5bc>: + 4e85bc: 008e4d58 ..MX + +004e85c0 <.lit4+0x5c0>: + 4e85c0: 00500af8 008e4db4 008e4df0 .P....M...M. + +004e85cc <.lit4+0x5cc>: + 4e85cc: 008e4e10 ..N. + +004e85d0 <.lit4+0x5d0>: + 4e85d0: 00500b04 008e4e38 008e4e74 008e4e8c .P....N8..Nt..N. + +004e85e0 <.lit4+0x5e0>: + 4e85e0: 008e4e94 ..N. + +004e85e4 <.lit4+0x5e4>: + 4e85e4: 008e4fd8 008e51dc 008e51a4 008e50d0 ..O...Q...Q...P. + 4e85f4: 008e50c0 008e51ec 008e50b8 008e5358 ..P...Q...P...SX + 4e8604: 008e56e0 008e5680 008e55b8 008e5640 ..V...V...U...V@ + +004e8614 <.lit4+0x614>: + 4e8614: 0000ff00 004e8eac 004e8940 004e8eb8 .....N...N.@.N.. + 4e8624: 004e8ec8 008e57e0 008e5914 008e596c .N....W...Y...Yl + 4e8634: 008e5a2c 008e5a54 008e5884 008e5a84 ..Z,..ZT..X...Z. + 4e8644: 008e5838 008e5a34 008e57e8 008e5828 ..X8..Z4..W...X( + 4e8654: 008e5abc 008e5bb4 008e5bf0 ..Z...[...[. + +004e8660 <.lit4+0x660>: + 4e8660: 008e5c84 ..\. + +004e8664 <.lit4+0x664>: + 4e8664: 0000fffc .... + +004e8668 <.lit4+0x668>: + 4e8668: 008e5d74 008e5dbc 00500b0c 00500b14 ..]t..]..P...P.. + 4e8678: 008e5ec0 004e8ed0 00001a00 ffffe5ff ..^..N.......... + 4e8688: 00054100 00060000 004e8eec 00054200 ..A......N....B. + 4e8698: 00054204 004e8f08 004e8f34 004e8f60 ..B..N...N.4.N.` + 4e86a8: 004e8f80 004e8f9c 004e8fb4 004e8fe0 .N...N...N...N.. + 4e86b8: 004e8ffc .N.. + +004e86bc <.lit4+0x6bc>: + 4e86bc: 008e614c 008e616c 008e61c4 008e61e8 ..aL..al..a...a. + 4e86cc: 008e61f8 008e6164 00500b18 ..a...ad.P.. + +004e86d8 <.lit4+0x6d8>: + 4e86d8: 008e6814 00500850 008e6278 008e67ec ..h..P.P..bx..g. + +004e86e8 <.lit4+0x6e8>: + 4e86e8: fffbfff0 .... + +004e86ec <.lit4+0x6ec>: + 4e86ec: ff000000 00ff0000 000000ff 40404040 ............@@@@ + +004e86fc <.lit4+0x6fc>: + 4e86fc: fefefeff .... + +004e8700 <.lit4+0x700>: + 4e8700: 80808080 .... +Disassembly of section .dport0.stack: + +0053f7f0 <_reserved_stack_start>: + ... +Disassembly of section .dport0.usb_in_rom: + +004e0100 : +_reserved_rom_data_start(): + 4e0100: 01120200 ffff40ff 0cf37010 82022010 ......@...p... . + 4e0110: 01300000 00000000 00000000 00000000 .0.............. + +004e0120 : + 4e0120: 0209003c 01018000 09fa0004 060000ff ...<............ + 4e0130: 00000507 02010200 07008205 00020002 ................ + 4e0140: 05070383 00400701 04054003 01000507 .....@....@..... + 4e0150: 02050200 07000605 00020002 00000000 ................ + +004e0160 : + 4e0160: 0209003c 01018000 09fa0004 060000ff ...<............ + 4e0170: 00000507 02010040 07008205 40020000 .......@....@... + 4e0180: 05070383 00400701 04054002 00000507 .....@....@..... + 4e0190: 02050040 07000605 40020000 00000000 ...@....@....... + +004e01a0 : + 4e01a0: 03040409 00000000 00000000 00000000 ................ + +004e01b0 : + 4e01b0: 03100041 00540048 00450052 004f0053 ...A.T.H.E.R.O.S + +004e01c0 : + 4e01c0: 03180055 00530042 0032002e 00300020 ...U.S.B.2...0. + 4e01d0: 0057004c 0041004e 00000000 00000000 .W.L.A.N........ + +004e01e0 : + 4e01e0: 030c0031 00320033 00340035 ...1.2.3.4.5 +Disassembly of section .dport0.data: + +00500000 <_indir_tbl>: + ... +Disassembly of section .rodata: + +004e8710 <_rom_store_table>: + 4e8710: 00500400 00500950 004e0260 00000000 .P...P.P.N.`.... + ... + +004e8730 : + 4e8730: 55aa55aa aa55aa55 ffffffff 00000000 U.U..U.U........ + +004e8740 : + 4e8740: 00000000 00989680 00000000 00000000 ................ + 4e8750: 00000000 00000001 01312d00 00000000 .........1-..... + ... + 4e8768: 00000002 02625a00 00000000 00000000 .....bZ......... + 4e8778: 00000000 ffffffff 00000000 00000000 ................ + ... + +004e8790 : + 4e8790: 00001b62 ...b + +004e8794 : + 4e8794: 004e9024 .N.$ + +004e8798 : + 4e8798: 1b620000 .b.. + +004e879c : + 4e879c: 00000020 ... + +004e87a0 : + 4e87a0: 05 . + +004e87a1 : + 4e87a1: 01 . + +004e87a2 : + 4e87a2: 01 . + +004e87a3 : + 4e87a3: 01 . + +004e87a4 : + 4e87a4: 01 . + +004e87a5 : + 4e87a5: 01 . + +004e87a6 : + 4e87a6: 01 . + +004e87a7 : + 4e87a7: 01 . + +004e87a8 : + 4e87a8: 01 . + +004e87a9 : + 4e87a9: 01 . + +004e87aa : + 4e87aa: 02 . + +004e87ab : + 4e87ab: 01 . + +004e87ac : + 4e87ac: 01 . + +004e87ad : + 4e87ad: 01 . + +004e87ae : + 4e87ae: 01 . + +004e87af : + 4e87af: 01 . + +004e87b0 : + 4e87b0: 01 . + +004e87b1 : + 4e87b1: 01 . + +004e87b2 : + 4e87b2: 0100 .. + +004e87b4 : + 4e87b4: 00040000 .... + +004e87b8 : + 4e87b8: 0002230f ..#. + +004e87bc : + 4e87bc: c280dbff .... + +004e87c0 : + 4e87c0: 0d02230f ..#. + +004e87c4 : + 4e87c4: 000008a2 .... + +004e87c8 : + 4e87c8: 004e902c .N., + +004e87cc : + 4e87cc: 000008a2 .... + +004e87d0 : + 4e87d0: 000008a2 .... + +004e87d4 : + 4e87d4: 01 . + +004e87d5 : + 4e87d5: 01 . + +004e87d6 : + 4e87d6: 01 . + +004e87d7 : + 4e87d7: 01 . + +004e87d8 : + 4e87d8: 01 . + +004e87d9 : + 4e87d9: 040000 ... + +004e87dc : + 4e87dc: 0000001d .... + +004e87e0 : + 4e87e0: 0000001d .... + +004e87e4 : + 4e87e4: 01 . + +004e87e5 : + 4e87e5: 01 . + +004e87e6 : + 4e87e6: 01 . + +004e87e7 : + 4e87e7: 01 . + +004e87e8 : + 4e87e8: 01 . + +004e87e9 : + 4e87e9: 010000 ... + +004e87ec : + 4e87ec: 00000000 .... + +004e87f0 : + 4e87f0: 00000000 .... + +004e87f4 : + 4e87f4: 00000000 .... + +004e87f8 : + 4e87f8: 00800000 .... + +004e87fc : + 4e87fc: 00800000 .... + +004e8800 : + 4e8800: 00400000 .@.. + +004e8804 : + 4e8804: 00000000 .... + +004e8808 : + 4e8808: 00000000 .... + +004e880c : + 4e880c: 00000000 .... + +004e8810 : + 4e8810: 00400000 .@.. + +004e8814 : + 4e8814: 00400000 .@.. + +004e8818 : + 4e8818: 00400000 .@.. + +004e881c : + 4e881c: 00000000 .... + +004e8820 : + 4e8820: 00000000 .... + +004e8824 : + ... + +004e8830 : + 4e8830: 01020202 02020202 02020202 02020203 ................ + 4e8840: 03030500 00000000 00000000 00000000 ................ + 4e8850: 52414d20 6661696c 0a0d0000 46617461 RAM fail....Fata + 4e8860: 6c206578 63657074 696f6e20 28256429 l exception (%d) + 4e8870: 3a207063 3d307825 78206261 64766164 : pc=0x%x badvad + 4e8880: 64723d30 78257820 64756d70 20617265 dr=0x%x dump are + 4e8890: 613d3078 25780a00 2d41312d 0a0d0000 a=0x%x..-A1-.... + 4e88a0: 6d697361 6c69676e 65645f6c 6f61640a misaligned_load. + 4e88b0: 0d000000 46617461 6c206578 63657074 ....Fatal except + 4e88c0: 696f6e20 28256429 3a200970 633d3078 ion (%d): .pc=0x + 4e88d0: 2578200a 0d096261 64766164 64723d30 %x ...badvaddr=0 + 4e88e0: 78257820 0a0d0964 756d7020 61726561 x%x ...dump area + 4e88f0: 3d307825 780a0000 09657063 313d3078 =0x%x....epc1=0x + 4e8900: 25782c20 65706332 3d307825 782c2065 %x, epc2=0x%x, e + 4e8910: 7063333d 30782578 2c206570 63343d30 pc3=0x%x, epc4=0 + 4e8920: 7825780a 00000000 30782530 38782c20 x%x.....0x%08x, + 4e8930: 30782530 38782c20 30782530 38782c20 0x%08x, 0x%08x, + 4e8940: 0a0d0000 202d2025 735f7665 723a2025 .... - %s_ver: % + 4e8950: 78202d20 0a0a0d00 66706761 00000000 x - ....fpga.... + 4e8960: 64696476 69642066 726f6d20 6f776c20 didvid from owl + 4e8970: 0a000000 64656661 756c7420 64696476 ....default didv + 4e8980: 6964200a 00000000 382e2077 61697420 id .....8. wait + 4e8990: 666f7220 646f776e 6c6f6164 2e2e2e2e for download.... + 4e89a0: 200a0d00 32000000 33000000 20332e31 ...2...3... 3.1 + 4e89b0: 206e6f20 70617463 680a0d00 20332e31 no patch... 3.1 + 4e89c0: 206e6f20 65657020 6f722063 6f727275 no eep or corru + 4e89d0: 70740a0d 00000000 20332e31 20534e53 pt...... 3.1 SNS + 4e89e0: 543a2065 65702069 6e697420 6661696c T: eep init fail + 4e89f0: 6564210a 0d000000 342e2077 64742073 ed!.....4. wdt s + 4e8a00: 74617274 0a0d0000 342e2077 61726d20 tart....4. warm + 4e8a10: 73746172 740a0d00 342e2063 6f6c6420 start...4. cold + 4e8a20: 73746172 740a0d00 352e2068 69662028 start...5. hif ( + 4e8a30: 2564290a 00000000 53544152 542e2e2e %d).....START... + 4e8a40: 2e0a0000 524f4d3e 3a6d6469 6f20646f ....ROM>:mdio do + 4e8a50: 776e6c6f 61642072 65616479 0a000000 wnload ready.... + 4e8a60: 362e2053 4e53543a 20686f73 74696620 6. SNST: hostif + 4e8a70: 636f7272 7570740a 0d000000 52414d20 corrupt.....RAM + 4e8a80: 616c6c6f 63617469 6f6e2028 25642062 allocation (%d b + 4e8a90: 79746573 29206661 696c6564 210a0000 ytes) failed!... + 4e8aa0: 414c4c4f 4352414d 20437572 72656e74 ALLOCRAM Current + 4e8ab0: 20416464 72203078 25780a00 414c4c4f Addr 0x%x..ALLO + 4e8ac0: 4352414d 2052656d 61696e69 6e672042 CRAM Remaining B + 4e8ad0: 79746573 2025640a 00000000 2d453132 ytes %d.....-E12 + 4e8ae0: 2d000000 2d453130 2d000000 2d453131 -...-E10-...-E11 + 4e8af0: 2d000000 2d453133 2d000000 4d697361 -...-E13-...Misa + 4e8b00: 6c69676e 6564206c 6f61643a 2070633d ligned load: pc= + 4e8b10: 30782578 20626164 76616464 723d3078 0x%x badvaddr=0x + 4e8b20: 25782064 756d7020 61726561 3d307825 %x dump area=0x% + 4e8b30: 780a0000 61737365 7274696f 6e206661 x...assertion fa + 4e8b40: 696c6564 3f207063 3d307825 782c206c iled? pc=0x%x, l + 4e8b50: 696e653d 25642c20 64756d70 20617265 ine=%d, dump are + 4e8b60: 613d3078 25780a00 54617267 65742049 a=0x%x..Target I + 4e8b70: 443a2030 78257820 28256429 0a000000 D: 0x%x (%d).... + 4e8b80: 44656275 6720496e 666f3a00 30782530 Debug Info:.0x%0 + 4e8b90: 38782000 30313233 34353637 38390000 8x .0123456789.. + 4e8ba0: 30313233 34353637 38396162 63646566 0123456789abcdef + 4e8bb0: 00000000 30313233 34353637 38394142 ....0123456789AB + 4e8bc0: 43444546 00000000 3c6e756c 6c3e0000 CDEF...... + 4e8bd0: 09737a3a 2025642c 206c643a 2025702c .sz: %d, ld: %p, + 4e8be0: 20666e3a 2025700d 00000000 21696e76 fn: %p.....!inv + 4e8bf0: 616c6964 2064706f 72742061 64647265 alid dport addre + 4e8c00: 73732c20 30782530 38780a0d 00000000 ss, 0x%08x...... + 4e8c10: 63702025 64206279 74657320 66726f6d cp %d bytes from + 4e8c20: 20307825 30387820 746f2030 78253038 0x%08x to 0x%08 + 4e8c30: 78000000 702e6f66 743a2030 78253034 x...p.oft: 0x%04 + 4e8c40: 782c2070 2e737a20 3a203078 25303478 x, p.sz : 0x%04x + 4e8c50: 0a000000 57616974 696e6720 666f7220 ....Waiting for + 4e8c60: 686f7374 20726573 65742e2e 00000000 host reset...... + 4e8c70: 72656365 69766564 2e0a0000 42616420 received....Bad + 4e8c80: 456e6769 6e65206e 756d6265 720a0000 Engine number... + 4e8c90: 456d7074 79205258 20526561 700a0000 Empty RX Reap... + 4e8ca0: 456d7074 79205458 20526561 70200a00 Empty TX Reap .. + 4e8cb0: 496e7661 6c696420 50697065 206e756d Invalid Pipe num + 4e8cc0: 6265720a 00000000 0a0d093d 3e5b646e ber........=>[dn + 4e8cd0: 515d2030 78253038 78200a5b 00000000 Q] 0x%08x .[.... + 4e8ce0: 093d3e5b 7570515d 20307825 30387820 .=>[upQ] 0x%08x + 4e8cf0: 0a5b0000 093d3e5b 68702064 6e515d20 .[...=>[hp dnQ] + 4e8d00: 30782530 3878200a 5b000000 093d3e5b 0x%08x .[....=>[ + 4e8d10: 6d702064 6e515d20 30782530 3878200a mp dnQ] 0x%08x . + 4e8d20: 5b000000 0a0d5b68 7020646e 515d2030 [.....[hp dnQ] 0 + 4e8d30: 78253038 782c2000 444d4120 54524143 x%08x, .DMA TRAC + 4e8d40: 45203078 25303878 0a0d2020 20205b00 E 0x%08x.. [. + 4e8d50: 0a0d5b6d 7020646e 515d2030 78253038 ..[mp dnQ] 0x%08 + 4e8d60: 782c2000 0a0d5b64 6e515d20 30782530 x, ...[dnQ] 0x%0 + 4e8d70: 38782c20 00000000 0a0a0d5b 7570515d 8x, .......[upQ] + 4e8d80: 20307825 3038782c 20000000 2d206375 0x%08x, ...- cu + 4e8d90: 73746f6d 20757362 20636f6e 6669670a stom usb config. + 4e8da0: 00000000 095b6355 53425f52 45515f44 .....[cUSB_REQ_D + 4e8db0: 4f574e4c 4f41445d 3a203078 25303878 OWNLOAD]: 0x%08x + 4e8dc0: 2c202530 32780a0d 00000000 090a0d3d , %02x.........= + 4e8dd0: 3d3e5b63 5553425f 5245515f 434f4d50 =>[cUSB_REQ_COMP + 4e8de0: 5d3a2030 78253038 780a0d00 636b7375 ]: 0x%08x...cksu + 4e8df0: 6d3d2578 00000000 56656e64 6f72436d m=%x....VendorCm + 4e8e00: 643a2044 6f776e6c 6f616443 6f6d706c d: DownloadCompl + 4e8e10: 65746521 0a000000 7a665265 73657455 ete!....zfResetU + 4e8e20: 53424649 464f0a0d 00000000 7a665475 SBFIFO......zfTu + 4e8e30: 726e4f66 66506f77 65720a0d 00000000 rnOffPower...... + 4e8e40: 47656e65 72617465 20457665 6e740a00 Generate Event.. + 4e8e50: 215b534f 55524345 5f305d20 62697437 ![SOURCE_0] bit7 + 4e8e60: 206f6e0a 0d000000 21555342 20726573 on.....!USB res + 4e8e70: 65740a0d 00000000 21555342 20737573 et......!USB sus + 4e8e80: 70656e64 0a0d0000 21555342 20726573 pend....!USB res + 4e8e90: 756d650a 0d000000 362e2075 73625f68 ume.....6. usb_h + 4e8ea0: 636c6b20 7264790a 0d000000 30782530 clk rdy.....0x%0 + 4e8eb0: 38782854 295d0000 30782530 38782825 8x(T)]..0x%08x(% + 4e8ec0: 63292d3e 00000000 0a0d2020 20000000 c)->...... ... + 4e8ed0: 6d69692d 6d64696f 202d2072 65736574 mii-mdio - reset + 4e8ee0: 202d2073 74617274 200a0000 6d69692d - start ...mii- + 4e8ef0: 6d64696f 202d2072 65736574 202d2065 mdio - reset - e + 4e8f00: 6e64200a 00000000 73746172 74656420 nd .....started + 4e8f10: 72656365 6976696e 67206279 74657320 receiving bytes + 4e8f20: 746f2025 78206c65 6e677468 2025640a to %x length %d. + 4e8f30: 00000000 636f6d70 6c657465 64207265 ....completed re + 4e8f40: 63656976 696e6720 62797465 7320746f ceiving bytes to + 4e8f50: 20257820 6c656e67 74682025 640a0000 %x length %d... + 4e8f60: 4669726d 77617265 20446f77 6e6c6f61 Firmware Downloa + 4e8f70: 64206c65 6e677468 20307825 780a0000 d length 0x%x... + 4e8f80: 4669726d 77617265 20457865 63204164 Firmware Exec Ad + 4e8f90: 64726573 73203078 25780a00 4669726d dress 0x%x..Firm + 4e8fa0: 77617265 20636865 636b7375 6d203078 ware checksum 0x + 4e8fb0: 25780a00 4669726d 77617265 20636865 %x..Firmware che + 4e8fc0: 636b7375 6d206661 696c6564 202d2072 cksum failed - r + 4e8fd0: 65206e65 676f7469 6174696e 67200a00 e negotiating .. + 4e8fe0: 4669726d 77617265 20446f77 6e6c6f61 Firmware Downloa + 4e8ff0: 64206973 20676f6f 64200a00 434f4d4d d is good ..COMM + 4e9000: 414e4420 544f2053 54415254 20464952 AND TO START FIR + 4e9010: 4d574152 45205245 43454956 4544200a MWARE RECEIVED . + 4e9020: 00000000 372e312e 30000000 4c58322e ....7.1.0...LX2. + 4e9030: 312e3000 00500400 00500400 00500950 1.0..P...P...P.P + 4e9040: 00500b78 .P.x +Disassembly of section .data: + +00500400 <_xtos_exc_handler_table>: +_xtos_exc_handler_table(): + 500400: 008e67ec 008e1104 008e67ec 008e67ec ..g.......g...g. + 500410: 008e1174 008e102c 008e67ec 008e67ec ...t...,..g...g. + 500420: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 500430: 008e6270 008e6270 008e6270 008e6270 ..bp..bp..bp..bp + 500440: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 500450: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 500460: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 500470: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 500480: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 500490: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 5004a0: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 5004b0: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 5004c0: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 5004d0: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 5004e0: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + 5004f0: 008e67ec 008e67ec 008e67ec 008e67ec ..g...g...g...g. + +00500500 <_xtos_enabled>: +_xtos_intstruct(): + 500500: 00000000 .... + +00500504 <_xtos_vpri_enabled>: + 500504: ffffffff .... + +00500508 <_xtos_interrupt_table>: +_xtos_interrupt_table(): + 500508: 008e67e4 00000012 008e67e4 00000011 ..g.......g..... + 500518: 008e67e4 00000010 008e67e4 0000000f ..g.......g..... + 500528: 008e67e4 0000000e 008e67e4 0000000d ..g.......g..... + 500538: 008e67e4 0000000c 008e67e4 0000000b ..g.......g..... + 500548: 008e67e4 0000000a 008e67e4 00000009 ..g.......g..... + 500558: 008e67e4 00000008 008e67e4 00000007 ..g.......g..... + 500568: 008e67e4 00000006 008e67e4 00000005 ..g.......g..... + 500578: 008e67e4 00000004 008e67e4 00000003 ..g.......g..... + 500588: 008e67e4 00000002 008e67e4 00000001 ..g.......g..... + 500598: 008e67e4 00000000 ..g..... + +005005a0 <_xtos_interrupt_mask_table>: +_xtos_interrupt_mask_table(): + 5005a0: fffffffe 00040000 fffffffe 00020000 ................ + 5005b0: fffffffe 00010000 fffffffe 00008000 ................ + 5005c0: fffffffe 00004000 fffffffe 00002000 ......@....... . + 5005d0: fffffffe 00001000 fffffffe 00000800 ................ + 5005e0: fffffffe 00000400 fffffffe 00000200 ................ + 5005f0: fffffffe 00000100 fffffffe 00000080 ................ + 500600: fffffffe 00000040 fffffffe 00000020 .......@....... + 500610: fffffffe 00000010 fffffffe 00000008 ................ + 500620: fffffffe 00000004 fffffffe 00000002 ................ + 500630: fffffffe 00000001 00000000 00000000 ................ + +00500640 : + 500640: 008e22b8 0050000c 008e2420 00500020 .."..P....$ .P. + 500650: 008e2954 00500044 008e2ef4 0050004c ..)T.P.D.....P.L + 500660: 008e471c 00500070 008e2290 00500118 ..G..P.p.."..P.. + 500670: 008e2c5c 00500104 008e1d04 005000e0 ..,\.P.......P.. + 500680: 008e1c30 00500144 008e2aa0 00500150 ...0.P.D..*..P.P + 500690: 008e2d68 00500160 008e2104 0050017c ..-h.P.`..!..P.| + 5006a0: 00000000 0050006c 008e2ac4 0050018c .....P.l..*..P.. + 5006b0: 008e2b7c 005001a4 008e4ed4 00500294 ..+|.P....N..P.. + 5006c0: 008e4e24 00500280 008e1548 005001c0 ..N$.P.....H.P.. + 5006d0: 008e3314 00500328 008e4d7c 005002f4 ..3..P.(..M|.P.. + 5006e0: 008e6128 00500264 008e470c 00500258 ..a(.P.d..G..P.X + 5006f0: 008e5b1c 005002b4 ..[..P.. + +005006f8 : + 5006f8: 00000001 .... + +005006fc : + 5006fc: 00000001 .... + +00500700 <_putc>: + 500700: 008e2450 ..$P + +00500704 : + 500704: 00000000 .... + +00500708 : + ... + +00500720 : + 500720: 00020004 00080000 00000000 00000000 ................ + +00500730 : + ... + 500738: aa00aa00 aaaaaaaa eeaaaaaa eeeeeeee ................ + 500748: feeeeeee ffffffff ffffffff 7fffffff ................ + 500758: f7efdfbf 7efcfdfb fdfbdfbf 00000000 ....~........... + ... + +00500770 : + ... + +00500780 : + 500780: 07090000 00000000 00000000 00000000 ................ + ... + +005007c0 : + 5007c0: 00053000 00000800 00000000 00000000 ..0............. + ... + 5007d8: 00053000 00000900 00000000 00000000 ..0............. + ... + 5007f0: 00053000 00000a00 00000000 00000000 ..0............. + ... + 500808: 00053000 00000b00 00000000 00000000 ..0............. + ... + 500820: 00053000 00000c00 00000000 00000000 ..0............. + ... + 500838: 00053000 00000d00 00000000 00000000 ..0............. + ... + +00500850 <_xtos_c_handler_table>: +_xtos_c_handler_table(): + 500850: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 500860: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 500870: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 500880: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 500890: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 5008a0: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 5008b0: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 5008c0: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 5008d0: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 5008e0: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 5008f0: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 500900: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 500910: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 500920: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 500930: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. + 500940: 008e6814 008e6814 008e6814 008e6814 ..h...h...h...h. +Disassembly of section .bss: + +00500950 : + 500950: 00000000 .... + +00500954 : + 500954: 00000000 .... + +00500958 : + 500958: 00000000 .... + +0050095c : + 50095c: 00000000 .... + +00500960 : + 500960: 00000000 .... + +00500964 : + 500964: 00000000 .... + +00500968 : + 500968: 00000000 .... + +0050096c : + 50096c: 00000000 .... + +00500970 : + 500970: 00000000 .... + +00500974 : + 500974: 00000000 .... + +00500978 : + ... + +0050097a : + 50097a: 00000000 00000000 ...... + +00500980 : + ... + +00500990 : + ... + +00500a28 : + 500a28: 00000000 .... + +00500a2c : + 500a2c: 00000000 .... + +00500a30 : + 500a30: 00000000 .... + +00500a34 : + 500a34: 00000000 .... + +00500a38 : + ... + +00500a44 : + ... + +00500a54 : + ... + +00500a98 : + ... + +00500aa4 : + ... + +00500ab4 : + 500ab4: 00000000 .... + +00500ab8 : + 500ab8: 00000000 .... + +00500abc : + 500abc: 00000000 .... + +00500ac0 : + 500ac0: 00000000 .... + +00500ac4 : + 500ac4: 00000000 .... + +00500ac8 : + 500ac8: 00000000 .... + +00500acc : + ... + +00500ace : + ... + +00500ad0 : + ... + +00500ad2 : + ... + +00500ad4 : + 500ad4: 00000000 .... + +00500ad8 : + 500ad8: 00000000 .... + +00500adc : + 500adc: 00000000 .... + +00500ae0 : + 500ae0: 00000000 .... + +00500ae4 : + 500ae4: 00000000 .... + +00500ae8 : + ... + +00500af0 : + ... + +00500af8 : + ... + +00500b04 : + ... + +00500b0c : + ... + +00500b18 : + ... + +00500b44 : + 500b44: 00000000 .... + +00500b48 : + 500b48: 00000000 .... + +00500b4c : + ... + +00500b4d : + ... + +00500b4e : + ... + +00500b4f : + ... + +00500b50 : + 500b50: 00000000 .... + +00500b54 : + 500b54: 00000000 .... + +00500b58 : + 500b58: 00000000 .... + +00500b5c : + 500b5c: 00000000 .... + +00500b60 : + 500b60: 00000000 .... + +00500b64 : + ... + +00500b65 : + ... + +00500b66 : + ... + +00500b67 : + ... + +00500b68 : + ... + +00500b69 : + ... + +00500b6a : + ... + +00500b6b : + ... + +00500b6c : + ... + +00500b6d : + ... + +00500b6e : + ... + +00500b6f : + ... + +00500b70 : + ... +Disassembly of section .ResetVector.text: + +008e0000 <_ResetVector>: +_ResetVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:56 + 8e0000: 60001c j 8e0020 <_ResetHandler> + +008e0003 <_ResetVector+0x3>: + ... + +008e0004 <_ResetVector+0x4>: + 8e0004: 008e0800 22221221 e0000000 008e0063 ...."".!.......c + 8e0014: 004e8710 00528001 .N...R.. + +008e001c <_ResetVector+0x1c>: + 8e001c: 00000000 .... + +008e0020 <_ResetHandler>: +_ResetHandler(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:73 + 8e0020: c000 movi.n a0, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:76 + 8e0022: 00e431 wsr.intenable a0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:128 + 8e0025: 12fff7 l32r a2, 8e0004 <_ResetVector_text_start+0x4> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:129 + 8e0028: 02e731 wsr.vecbase a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:133 + 8e002b: 021600 rsil a2, 1 +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:161 + 8e002e: 12fff6 l32r a2, 8e0008 <_ResetVector_text_start+0x8> +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:396 + 8e0031: 15fff6 l32r a5, 8e000c <_ResetVector_text_start+0xc> + 8e0034: 16fff7 l32r a6, 8e0010 <_ResetVector_text_start+0x10> + 8e0037: c030 movi.n a3, 0 + 8e0039: d720 mov.n a7, a2 + 8e003b: 056601 and a6, a6, a5 + 8e003e: 600021 j 8e0063 <_ResetHandler+0x43> + +008e0041 <_ResetHandler+0x21>: + ... + +008e0050 <_ResetHandler+0x30>: +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:281 + 8e0050: 043605 witlb a4, a3 + 8e0053: 000200 isync + 8e0056: d30f nop.n + +008e0058 <_ResetHandler+0x38>: + 8e0058: d30f nop.n + 8e005a: 753114 beq a3, a5, 8e0072 <_ResetHandler+0x52> + +008e005d <_ResetHandler+0x3d>: + 8e005d: 074714 srli a7, a7, 4 + 8e0060: 05330c sub a3, a3, a5 +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:304 + 8e0063: 070443 extui a4, a7, 0, 4 + 8e0066: 7631e6 beq a3, a6, 8e0050 <_ResetHandler+0x30> + 8e0069: 043605 witlb a4, a3 + 8e006c: 7539ed bne a3, a5, 8e005d <_ResetHandler+0x3d> + 8e006f: 000200 isync + +008e0072 <_ResetHandler+0x52>: +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:396 + 8e0072: 15ffe6 l32r a5, 8e000c <_ResetVector_text_start+0xc> + 8e0075: c030 movi.n a3, 0 + 8e0077: d720 mov.n a7, a2 + 8e0079: 600006 j 8e0083 <_ResetHandler+0x63> + +008e007c <_ResetHandler+0x5c>: + ... + +008e007d <_ResetHandler+0x5d>: + 8e007d: 074714 srli a7, a7, 4 + 8e0080: 05330c sub a3, a3, a5 +/cad/tensilica/tools/RB-2007.2/XtDevTools/install/tools/RB-2007.2-linux/XtensaTools/xtensa-elf/include/xtensa/cacheattrasm.h:343 + 8e0083: 070443 extui a4, a7, 0, 4 + 8e0086: 043e05 wdtlb a4, a3 + 8e0089: 7539f0 bne a3, a5, 8e007d <_ResetHandler+0x5d> + 8e008c: 030200 dsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:172 + 8e008f: 12ffe1 l32r a2, 8e0014 <_ResetVector_text_start+0x14> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:173 + 8e0092: ca20 beqz.n a2, 8e00b6 + +008e0094 : +unpack(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:174 + 8e0094: 8320 l32i.n a3, a2, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:175 + 8e0096: 8421 l32i.n a4, a2, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:176 + 8e0098: 8522 l32i.n a5, a2, 8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:177 + 8e009a: 222c0c addi a2, a2, 12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:178 + 8e009d: 743b0f bgeu a3, a4, 8e00b0 + +008e00a0 : +uploop(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:179 + 8e00a0: 8650 l32i.n a6, a5, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:180 + 8e00a2: b455 addi.n a5, a5, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:181 + 8e00a4: 9630 s32i.n a6, a3, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:182 + 8e00a6: b433 addi.n a3, a3, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:183 + 8e00a8: 7433f4 bltu a3, a4, 8e00a0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:184 + 8e00ab: 63ffe5 j 8e0094 + +008e00ae : + ... + +008e00b0 : +upnext(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:185 + 8e00b0: 653fe0 bnez a3, 8e0094 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:186 + 8e00b3: 655fdd bnez a5, 8e0094 + +008e00b6 : +unpackdone(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:254 + 8e00b6: 12ffd8 l32r a2, 8e0018 <_ResetVector_text_start+0x18> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:255 + 8e00b9: 020531 wsr.litbase a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:256 + 8e00bc: 010200 rsync + +008e00bf : +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:266 + 8e00bf: 000200 isync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:281 + 8e00c2: c011 movi.n a1, 1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:282 + 8e00c4: 014931 wsr.windowstart a1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:286 + 8e00c7: 004831 wsr.windowbase a0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:287 + 8e00ca: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:288 + 8e00cd: c000 movi.n a0, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:353 + 8e00cf: 140004 l32r a4, 4e8010 <_lit4_start+0x10> + 8e00d2: 04d231 wsr.excsave2 a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:354 + 8e00d5: 140005 l32r a4, 4e8014 <_lit4_start+0x14> + 8e00d8: 04d331 wsr.excsave3 a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/reset-vector.S:372 + 8e00db: 5003c9 call0 8e1000 <_iram0_text_end> +Disassembly of section .WindowVectors.text: + +008e0800 <_WindowOverflow4>: +_WindowOverflow4(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:105 + 8e0800: 005c94 s32e a0, a5, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:106 + 8e0803: 015d94 s32e a1, a5, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:107 + 8e0806: 025e94 s32e a2, a5, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:108 + 8e0809: 035f94 s32e a3, a5, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:110 + 8e080c: 004300 rfwo + +008e080f <_WindowOverflow4+0xf>: + ... + +008e0840 <_WindowUnderflow4>: +_WindowUnderflow4(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:133 + 8e0840: 005c90 l32e a0, a5, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:134 + 8e0843: 015d90 l32e a1, a5, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:135 + 8e0846: 025e90 l32e a2, a5, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:136 + 8e0849: 035f90 l32e a3, a5, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:138 + 8e084c: 005300 rfwu + +008e084f <_WindowUnderflow4+0xf>: + ... + +008e0880 <_WindowOverflow8>: +_WindowOverflow8(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:169 + 8e0880: 009c94 s32e a0, a9, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:170 + 8e0883: 001d90 l32e a0, a1, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:171 + 8e0886: 019d94 s32e a1, a9, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:172 + 8e0889: 029e94 s32e a2, a9, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:173 + 8e088c: 039f94 s32e a3, a9, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:174 + 8e088f: 040894 s32e a4, a0, -32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:175 + 8e0892: 050994 s32e a5, a0, -28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:176 + 8e0895: 060a94 s32e a6, a0, -24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:177 + 8e0898: 070b94 s32e a7, a0, -20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:179 + 8e089b: 004300 rfwo + +008e089e <_WindowOverflow8+0x1e>: + ... + +008e08c0 <_WindowUnderflow8>: +_WindowUnderflow8(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:210 + 8e08c0: 009c90 l32e a0, a9, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:211 + 8e08c3: 019d90 l32e a1, a9, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:212 + 8e08c6: 029e90 l32e a2, a9, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:213 + 8e08c9: 071d90 l32e a7, a1, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:214 + 8e08cc: 039f90 l32e a3, a9, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:215 + 8e08cf: 047890 l32e a4, a7, -32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:216 + 8e08d2: 057990 l32e a5, a7, -28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:217 + 8e08d5: 067a90 l32e a6, a7, -24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:218 + 8e08d8: 077b90 l32e a7, a7, -20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:220 + 8e08db: 005300 rfwu + +008e08de <_WindowUnderflow8+0x1e>: + ... + +008e0900 <_WindowOverflow12>: +_WindowOverflow12(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:255 + 8e0900: 00dc94 s32e a0, a13, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:256 + 8e0903: 001d90 l32e a0, a1, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:257 + 8e0906: 01dd94 s32e a1, a13, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:258 + 8e0909: 02de94 s32e a2, a13, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:259 + 8e090c: 03df94 s32e a3, a13, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:260 + 8e090f: 040494 s32e a4, a0, -48 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:261 + 8e0912: 050594 s32e a5, a0, -44 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:262 + 8e0915: 060694 s32e a6, a0, -40 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:263 + 8e0918: 070794 s32e a7, a0, -36 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:264 + 8e091b: 080894 s32e a8, a0, -32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:265 + 8e091e: 090994 s32e a9, a0, -28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:266 + 8e0921: 0a0a94 s32e a10, a0, -24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:267 + 8e0924: 0b0b94 s32e a11, a0, -20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:269 + 8e0927: 004300 rfwo + +008e092a <_WindowOverflow12+0x2a>: + ... + +008e0940 <_WindowUnderflow12>: +_WindowUnderflow12(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:304 + 8e0940: 00dc90 l32e a0, a13, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:305 + 8e0943: 01dd90 l32e a1, a13, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:306 + 8e0946: 02de90 l32e a2, a13, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:307 + 8e0949: 0b1d90 l32e a11, a1, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:308 + 8e094c: 03df90 l32e a3, a13, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:309 + 8e094f: 04b490 l32e a4, a11, -48 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:310 + 8e0952: 05b590 l32e a5, a11, -44 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:311 + 8e0955: 06b690 l32e a6, a11, -40 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:312 + 8e0958: 07b790 l32e a7, a11, -36 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:313 + 8e095b: 08b890 l32e a8, a11, -32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:314 + 8e095e: 09b990 l32e a9, a11, -28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:315 + 8e0961: 0aba90 l32e a10, a11, -24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:316 + 8e0964: 0bbb90 l32e a11, a11, -20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/window-vectors.S:318 + 8e0967: 005300 rfwu +Disassembly of section .KernelExceptionVector.text: + +008e0d40 <_KernelExceptionVector>: +_KernelExceptionVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/kernel-vector.S:43 + 8e0d40: 001400 break 1, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/kernel-vector.S:51 + 8e0d43: 63fff9 j 8e0d40 <_KernelExceptionVector_text_start> +Disassembly of section .UserExceptionVector.text: + +008e0e20 <_UserExceptionVector>: +_UserExceptionVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:25 + 8e0e20: 211c90 addi a1, a1, -112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:26 + 8e0e23: 9214 s32i.n a2, a1, 16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:27 + 8e0e25: 9315 s32i.n a3, a1, 20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:28 + 8e0e27: 130006 l32r a3, 4e8018 <_lit4_start+0x18> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:29 + 8e0e2a: 02e830 rsr.exccause a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:31 + 8e0e2d: 03230a addx4 a3, a2, a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:32 + 8e0e30: 8330 l32i.n a3, a3, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:33 + 8e0e32: 9416 s32i.n a4, a1, 24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/user-vector.S:34 + 8e0e34: 0a3000 jx a3 +Disassembly of section .DoubleExceptionVector.text: + +008e0f20 <_DoubleExceptionVector>: +_DoubleExceptionVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/double-vector.S:47 + 8e0f20: 041400 break 1, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/double-vector.S:55 + 8e0f23: 63fff9 j 8e0f20 <_DoubleExceptionVector_text_start> +Disassembly of section .Level2InterruptVector.text: + +008e0a20 <_Level2Vector>: +_Level2Vector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-vector.S:37 + 8e0a20: 02d216 xsr.excsave2 a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-vector.S:38 + 8e0a23: 0a2000 jx a2 +Disassembly of section .Level3InterruptVector.text: + +008e0b20 <_Level3Vector>: +_Level3Vector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-vector.S:37 + 8e0b20: 02d316 xsr.excsave3 a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-vector.S:38 + 8e0b23: 0a2000 jx a2 +Disassembly of section .DebugExceptionVector.text: + +008e0c20 <_DebugExceptionVector>: +_DebugExceptionVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/debug-vector.S:42 + 8e0c20: 004700 waiti 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/debug-vector.S:44 + 8e0c23: 63fff9 j 8e0c20 <_DebugExceptionVector_text_start> +Disassembly of section .NMIExceptionVector.text: + +008e0ce4 <_NMIExceptionVector>: +_NMIExceptionVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/nmi-vector.S:40 + 8e0ce4: 015300 rfi 5 +Disassembly of section .text: + +008e1000 <_start>: +_stext(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:49 + 8e1000: 200a00 movi a0, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:50 + 8e1003: 110000 l32r a1, 4e8000 <_lit4_start> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:56 + 8e1006: 130001 l32r a3, 4e8004 <_lit4_start+0x4> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:58 + 8e1009: 03e631 wsr.ps a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:59 + 8e100c: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:68 + 8e100f: 160002 l32r a6, 4e8008 <_lit4_start+0x8> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:69 + 8e1012: 170003 l32r a7, 4e800c <_lit4_start+0xc> + 8e1015: d30f nop.n +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:70 + 8e1017: 776b06 bgeu a6, a7, 8e1021 <_iram0_text_end+0x21> + +008e101a <_start+0x1a>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:71 + 8e101a: 9060 s32i.n a0, a6, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:72 + 8e101c: b466 addi.n a6, a6, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:73 + 8e101e: 7763f8 bltu a6, a7, 8e101a <_iram0_text_end+0x1a> + +008e1021 <_start+0x21>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:80 + 8e1021: 5402e2 call4 8e1bac

+/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:90 + 8e1024: 0f1400 break 1, 15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/crt1-tiny.S:92 + 8e1027: 63fff9 j 8e1024 <_iram0_text_end+0x24> + +008e102a <_start+0x2a>: + ... + +008e102c <_xtos_alloca_handler>: +_xtos_alloca_handler(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:101 + 8e102c: 03b130 rsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:102 + 8e102f: 9517 s32i.n a5, a1, 28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:103 + 8e1031: b332 addi.n a2, a3, 3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:110 + 8e1033: 040130 rsr.lend a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:111 + 8e1036: 050230 rsr.lcount a5 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:112 + 8e1039: 72490b bne a4, a2, 8e1048 <_xtos_alloca_handler+0x1c> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:113 + 8e103c: 645008 beqz a5, 8e1048 <_xtos_alloca_handler+0x1c> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:114 + 8e103f: 255cff addi a5, a5, -1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:115 + 8e1042: 050231 wsr.lcount a5 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:116 + 8e1045: 020030 rsr.lbeg a2 + +008e1048 <_xtos_alloca_handler+0x1c>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:118 + 8e1048: 02b131 wsr.epc1 a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:126 + 8e104b: b133 addi.n a3, a3, 1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:127 + 8e104d: 030241 extui a2, a3, 0, 2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:128 + 8e1050: 02330c sub a3, a3, a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:129 + 8e1053: 8330 l32i.n a3, a3, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:130 + 8e1055: 040330 rsr.sar a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:133 + 8e1058: 002304 ssa8b a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:134 + 8e105b: 00331a sll a3, a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:135 + 8e105e: 03c353 extui a3, a3, 28, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:141 + 8e1061: 040331 wsr.sar a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:144 + 8e1064: 140007 l32r a4, 4e801c <_lit4_start+0x1c> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:145 + 8e1067: d510 mov.n a5, a1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:146 + 8e1069: 211c70 addi a1, a1, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:149 + 8e106c: 04340a addx4 a4, a3, a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:162 + 8e106f: 0a4000 jx a4 + +008e1072 <_xtos_alloca_handler+0x46>: + ... + +008e1074 <_xtos_alloca_handler+0x48>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:165 + 8e1074: d100 mov.n a1, a0 + 8e1076: cf48 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:166 + 8e1078: cf46 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> + +008e107a <_xtos_alloca_handler+0x4e>: + ... + +008e107c <_xtos_alloca_handler+0x50>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:167 + 8e107c: 8154 l32i.n a1, a5, 16 + 8e107e: cf40 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:168 + 8e1080: 8155 l32i.n a1, a5, 20 + 8e1082: ce4c bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:169 + 8e1084: 8156 l32i.n a1, a5, 24 + 8e1086: ce48 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:170 + 8e1088: 8157 l32i.n a1, a5, 28 + 8e108a: ce44 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:171 + 8e108c: d160 mov.n a1, a6 + 8e108e: ce40 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:172 + 8e1090: d170 mov.n a1, a7 + 8e1092: cd4c bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:173 + 8e1094: d180 mov.n a1, a8 + 8e1096: cd48 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:174 + 8e1098: d190 mov.n a1, a9 + 8e109a: cd44 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:175 + 8e109c: d1a0 mov.n a1, a10 + 8e109e: cd40 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:176 + 8e10a0: d1b0 mov.n a1, a11 + 8e10a2: cc4c bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:177 + 8e10a4: d1c0 mov.n a1, a12 + 8e10a6: cc48 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:178 + 8e10a8: d1d0 mov.n a1, a13 + 8e10aa: cc44 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:179 + 8e10ac: d1e0 mov.n a1, a14 + 8e10ae: cc40 bnez.n a4, 8e10b2 <_xtos_alloca_handler+0x86> + +008e10b0 <_xtos_alloca_handler+0x84>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:180 + 8e10b0: d1f0 mov.n a1, a15 + +008e10b2 <_xtos_alloca_handler+0x86>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:187 + 8e10b2: 010341 extui a3, a1, 0, 2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:188 + 8e10b5: c834 beqz.n a3, 8e10bd <_xtos_alloca_handler+0x91> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:193 + 8e10b7: 0f1400 break 1, 15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:195 + 8e10ba: 03110c sub a1, a1, a3 + +008e10bd <_xtos_alloca_handler+0x91>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:200 + 8e10bd: 225c70 addi a2, a5, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:205 + 8e10c0: 240a70 movi a4, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:206 + 8e10c3: 05130c sub a3, a1, a5 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:207 + 8e10c6: 743b16 bgeu a3, a4, 8e10e0 <_xtos_alloca_handler+0xb4> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:210 + 8e10c9: 04550c sub a5, a5, a4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:211 + 8e10cc: 235220 l32i a3, a5, 128 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:212 + 8e10cf: 245221 l32i a4, a5, 132 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:213 + 8e10d2: 9354 s32i.n a3, a5, 16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:214 + 8e10d4: 9455 s32i.n a4, a5, 20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:215 + 8e10d6: 235222 l32i a3, a5, 136 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:216 + 8e10d9: 245223 l32i a4, a5, 140 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:217 + 8e10dc: 9356 s32i.n a3, a5, 24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:218 + 8e10de: 9457 s32i.n a4, a5, 28 + +008e10e0 <_xtos_alloca_handler+0xb4>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:223 + 8e10e0: 032c90 l32e a3, a2, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:224 + 8e10e3: 042d90 l32e a4, a2, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:225 + 8e10e6: 031c94 s32e a3, a1, -16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:226 + 8e10e9: 041d94 s32e a4, a1, -12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:227 + 8e10ec: 032e90 l32e a3, a2, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:228 + 8e10ef: 042f90 l32e a4, a2, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:229 + 8e10f2: 031e94 s32e a3, a1, -8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:230 + 8e10f5: 041f94 s32e a4, a1, -4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:246 + 8e10f8: 8254 l32i.n a2, a5, 16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:247 + 8e10fa: 8355 l32i.n a3, a5, 20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:248 + 8e10fc: 8456 l32i.n a4, a5, 24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:249 + 8e10fe: 8557 l32i.n a5, a5, 28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-alloca-handler.S:250 + 8e1100: 000300 rfe + +008e1103 <_xtos_alloca_handler+0xd7>: + ... + +008e1104 <_xtos_syscall_handler>: +_xtos_syscall_handler(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:74 + 8e1104: 03b130 rsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:80 + 8e1107: 020130 rsr.lend a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:81 + 8e110a: b333 addi.n a3, a3, 3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:82 + 8e110c: 73290c bne a2, a3, 8e111c <_xtos_syscall_handler+0x18> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:83 + 8e110f: 020230 rsr.lcount a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:84 + 8e1112: c826 beqz.n a2, 8e111c <_xtos_syscall_handler+0x18> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:85 + 8e1114: b022 addi.n a2, a2, -1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:86 + 8e1116: 020231 wsr.lcount a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:87 + 8e1119: 030030 rsr.lbeg a3 + +008e111c <_xtos_syscall_handler+0x18>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:88 + 8e111c: 8214 l32i.n a2, a1, 16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:94 + 8e111e: 03b131 wsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:95 + 8e1121: 8315 l32i.n a3, a1, 20 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:99 + 8e1123: 652044 bnez a2, 8e116b <_SyscallException+0x28> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:106 + 8e1126: 231615 s32i a3, a1, 84 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:107 + 8e1129: 241616 s32i a4, a1, 88 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:108 + 8e112c: 251617 s32i a5, a1, 92 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:110 + 8e112f: 130008 l32r a3, 4e8020 <_lit4_start+0x20> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:111 + 8e1132: 02e630 rsr.ps a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:112 + 8e1135: 03e631 wsr.ps a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:114 + 8e1138: 03b130 rsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:115 + 8e113b: 211c70 addi a1, a1, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:116 + 8e113e: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:123 + 8e1141: c040 movi.n a4, 0 + +008e1143 <_SyscallException>: +_SyscallException(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:129 + 8e1143: 6c1008 entry a1, 64 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:131 + 8e1146: 5c0007 call12 8e1164 <_SyscallException+0x21> + +008e1149 <_SyscallException+0x6>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:132 + 8e1149: 1e0009 l32r a14, 4e8024 <_lit4_start+0x24> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:133 + 8e114c: aec0 add.n a0, a12, a14 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:134 + 8e114e: d10f retw.n + +008e1150 <_SyscallException+0xd>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:137 + 8e1150: 02e631 wsr.ps a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:138 + 8e1153: c020 movi.n a2, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:139 + 8e1155: 845a l32i.n a4, a5, 40 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:140 + 8e1157: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:141 + 8e115a: 03b131 wsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:142 + 8e115d: 8359 l32i.n a3, a5, 36 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:143 + 8e115f: 855b l32i.n a5, a5, 44 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:144 + 8e1161: 000300 rfe + +008e1164 <_SyscallException+0x21>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:150 + 8e1164: 6c1006 entry a1, 48 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:152 + 8e1167: dff0 mov.n a15, a15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:163 + 8e1169: d10f retw.n + +008e116b <_SyscallException+0x28>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:168 + 8e116b: c72f movi.n a2, -1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:169 + 8e116d: 211c70 addi a1, a1, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/exc-syscall-handler.S:170 + 8e1170: 000300 rfe + +008e1173 <_SyscallException+0x30>: + ... + +008e1174 <_xtos_l1int_handler>: +_xtos_l1int_handler(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:69 + 8e1174: 9517 s32i.n a5, a1, 28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:85 + 8e1176: 120008 l32r a2, 4e8020 <_lit4_start+0x20> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:87 + 8e1179: 03b130 rsr.epc1 a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:88 + 8e117c: 02e616 xsr.ps a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:98 + 8e117f: 9310 s32i.n a3, a1, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:99 + 8e1181: 9211 s32i.n a2, a1, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:170 + 8e1183: 211c70 addi a1, a1, 112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:172 + 8e1186: 12000a l32r a2, 4e8028 <_lit4_start+0x28> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:174 + 8e1189: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:257 + 8e118c: 032402 or a4, a2, a3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:258 + 8e118f: 042409 addx2 a4, a2, a4 + +008e1192 <_LevelOneInterrupt>: +_LevelOneInterrupt(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:266 + 8e1192: 6c100e entry a1, 112 + +008e1195 <_LevelOneInterrupt+0x3>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:315 + 8e1195: 0f1600 rsil a15, 1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:345 + 8e1198: c0d1 movi.n a13, 1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:348 + 8e119a: 1c000b l32r a12, 4e802c <_lit4_start+0x2c> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:350 + 8e119d: 0de331 wsr.intclear a13 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:554 + 8e11a0: 0d0230 rsr.lcount a13 + 8e11a3: 0f0030 rsr.lbeg a15 + 8e11a6: 9d19 s32i.n a13, a1, 36 + 8e11a8: 0d0130 rsr.lend a13 + 8e11ab: 9f1a s32i.n a15, a1, 40 + 8e11ad: 9d1b s32i.n a13, a1, 44 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:556 + 8e11af: 0f0330 rsr.sar a15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:561 + 8e11b2: 8dc0 l32i.n a13, a12, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:562 + 8e11b4: 9f12 s32i.n a15, a1, 8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:570 + 8e11b6: df10 mov.n a15, a1 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:571 + 8e11b8: 8ec1 l32i.n a14, a12, 4 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:572 + 8e11ba: 0fd000 callx12 a13 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:576 + 8e11bd: 8d19 l32i.n a13, a1, 36 + 8e11bf: 8e1a l32i.n a14, a1, 40 + 8e11c1: 8f1b l32i.n a15, a1, 44 + 8e11c3: 0d0231 wsr.lcount a13 + 8e11c6: 0e0031 wsr.lbeg a14 + 8e11c9: 0f0131 wsr.lend a15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:578 + 8e11cc: 8c12 l32i.n a12, a1, 8 + +008e11ce : +spurious_int(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:684 + 8e11ce: 10000c l32r a0, 4e8030 <_lit4_start+0x30> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:692 + 8e11d1: 1d000a l32r a13, 4e8028 <_lit4_start+0x28> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:693 + 8e11d4: 0c0331 wsr.sar a12 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:694 + 8e11d7: 0d0002 or a0, a0, a13 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:695 + 8e11da: 00d009 addx2 a0, a13, a0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:698 + 8e11dd: 0d3600 rsil a13, 3 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-lowpri-dispatcher.S:701 + 8e11e0: d10f retw.n + +008e11e2 : + ... + +008e11e4 <_xtos_set_interrupt_handler_arg>: +_xtos_set_interrupt_handler_arg(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:31 + 8e11e4: 6c1004 entry a1, 32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:36 + 8e11e7: c152 movi.n a5, 18 + 8e11e9: 72533b bltu a5, a2, 8e1228 <_xtos_set_interrupt_handler_arg+0x44> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:38 + 8e11ec: 18000d l32r a8, 4e8034 <_lit4_start+0x34> + 8e11ef: a828 add.n a8, a2, a8 + 8e11f1: 288000 l8ui a8, a8, 0 + 8e11f4: 17000e l32r a7, 4e8038 <_lit4_start+0x38> + 8e11f7: 6f8531 bgeui a8, 5, 8e122c <_xtos_set_interrupt_handler_arg+0x48> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:41 + 8e11fa: 0d2811 slli a8, a2, 3 + 8e11fd: 08770c sub a7, a7, a8 + 8e1200: 18000f l32r a8, 4e803c <_lit4_start+0x3c> + 8e1203: 267224 l32i a6, a7, 144 + 8e1206: c83e beqz.n a3, 8e1218 <_xtos_set_interrupt_handler_arg+0x34> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:49 + 8e1208: 237624 s32i a3, a7, 144 + 8e120b: 247625 s32i a4, a7, 148 + 8e120e: c020 movi.n a2, 0 + 8e1210: 08690c sub a9, a6, a8 + 8e1213: 096239 movnez a2, a6, a9 + 8e1216: d10f retw.n + +008e1218 <_xtos_set_interrupt_handler_arg+0x34>: + 8e1218: 287624 s32i a8, a7, 144 + 8e121b: 227625 s32i a2, a7, 148 + 8e121e: 086a0c sub a10, a6, a8 + 8e1221: c020 movi.n a2, 0 + 8e1223: 0a6239 movnez a2, a6, a10 + 8e1226: d10f retw.n + +008e1228 <_xtos_set_interrupt_handler_arg+0x44>: + 8e1228: c020 movi.n a2, 0 + 8e122a: d10f retw.n + +008e122c <_xtos_set_interrupt_handler_arg+0x48>: + 8e122c: c020 movi.n a2, 0 + 8e122e: d10f retw.n + +008e1230 <_xtos_set_interrupt_handler>: +_xtos_set_interrupt_handler(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:57 + 8e1230: 6c1004 entry a1, 32 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-sethandler.c:58 + 8e1233: da20 mov.n a10, a2 + 8e1235: db30 mov.n a11, a3 + 8e1237: dc20 mov.n a12, a2 + 8e1239: 5bffea call8 8e11e4 <_xtos_set_interrupt_handler_arg> + 8e123c: d2a0 mov.n a2, a10 + 8e123e: d10f retw.n + +008e1240 <_Level2FromVector>: +_Level2FromVector(): +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:53 + 8e1240: 02d216 xsr.excsave2 a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:57 + 8e1243: 211c90 addi a1, a1, -112 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:58 + 8e1246: 9214 s32i.n a2, a1, 16 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:62 + 8e1248: 120008 l32r a2, 4e8020 <_lit4_start+0x20> +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:64 + 8e124b: 9416 s32i.n a4, a1, 24 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:65 + 8e124d: 9517 s32i.n a5, a1, 28 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:66 + 8e124f: 02e631 wsr.ps a2 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:67 + 8e1252: 010200 rsync +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:84 + 8e1255: c040 movi.n a4, 0 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:85 + 8e1257: 211c70 addi a1, a1, 112 + +008e125a <_Level2FromVector+0x1a>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:86 + 8e125a: 6c100e entry a1, 112 + +008e125d <_Level2FromVector+0x1d>: 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+/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:135 + 8e1272: 64f05e beqz a15, 8e12d4 + +008e1275 <_Level2FromVector+0x35>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:136 + 8e1275: 9e12 s32i.n a14, a1, 8 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:137 + 8e1277: 0d0230 rsr.lcount a13 + 8e127a: 0e0030 rsr.lbeg a14 + 8e127d: 9d19 s32i.n a13, a1, 36 + 8e127f: 0d0130 rsr.lend a13 + 8e1282: 2e160a s32i a14, a1, 40 + 8e1285: 2d160b s32i a13, a1, 44 + +008e1288 <_Level2FromVector+0x48>: +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:142 + 8e1288: 0f0c06 neg a12, a15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:143 + 8e128b: 0fcc01 and a12, a12, a15 +/folks/rhsu/project/p4v/perforce/p0_core/project/src/rom/os/src/xtos/int-medpri-dispatcher.S:144 + 8e128e: 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8e1558: 68a210 beqi a10, 2, 8e156c + 8e155b: 69a30b bnei a10, 3, 8e156a + +008e155e : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:458 + 8e155e: da20 mov.n a10, a2 + 8e1560: 58075b call8 8e32d0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:468 + 8e1563: d10f retw.n + +008e1565 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:453 + 8e1565: da20 mov.n a10, a2 + 8e1567: 580875 call8 8e373c + +008e156a : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:468 + 8e156a: d10f retw.n + +008e156c : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:464 + 8e156c: da20 mov.n a10, a2 + 8e156e: 58124b call8 8e5e9c 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<_lit4_start+0x94> + 8e15aa: 1f0024 l32r a15, 4e8090 <_lit4_start+0x90> + 8e15ad: 1b0022 l32r a11, 4e8088 <_lit4_start+0x88> + 8e15b0: 180023 l32r a8, 4e808c <_lit4_start+0x8c> + 8e15b3: 190029 l32r a9, 4e80a4 <_lit4_start+0xa4> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:503 + 8e15b6: 9930 s32i.n a9, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:509 + 8e15b8: 98bd s32i.n a8, a11, 52 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:510 + 8e15ba: 9fbe s32i.n a15, a11, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:511 + 8e15bc: 9ebf s32i.n a14, a11, 60 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:512 + 8e15be: 2db610 s32i a13, a11, 64 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:514 + 8e15c1: 9ab9 s32i.n a10, a11, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:513 + 8e15c3: 9cb8 s32i.n a12, a11, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:518 + 8e15c5: c0a9 movi.n a10, 9 + 8e15c7: 1b002a l32r a11, 4e80a8 <_lit4_start+0xa8> + 8e15ca: 581310 call8 8e620c <_xtos_set_exception_handler> + 8e15cd: 12002b l32r a2, 4e80ac <_lit4_start+0xac> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:519 + 8e15d0: c0a3 movi.n a10, 3 + 8e15d2: db20 mov.n a11, a2 + 8e15d4: 58130d call8 8e620c <_xtos_set_exception_handler> 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8e1697: 1a002e l32r a10, 4e80b8 <_lit4_start+0xb8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:941 + 8e169a: 282212 l32i a8, a2, 72 + 8e169d: 1b002f l32r a11, 4e80bc <_lit4_start+0xbc> + 8e16a0: 2c2a02 movi a12, 0x202 + 8e16a3: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:943 + 8e16a6: 28225f l32i a8, a2, 0x17c + 8e16a9: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:945 + 8e16ac: d10f retw.n + +008e16ae : + ... + +008e16b0 <_read_usb_desc>: +_read_usb_desc(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/athos/src/athos_main.c:949 + 8e16b0: 6c1006 entry a1, 48 + 8e16b3: 150018 l32r a5, 4e8060 <_lit4_start+0x60> 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8e1c59: 5812f0 call8 8e681c + 8e1c5c: 03a80c sub a8, a10, a3 + 8e1c5f: 7283f6 bltu a8, a2, 8e1c59 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:120 + 8e1c62: d10f retw.n + +008e1c64 : +cmnos_milliseconds(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:129 + 8e1c64: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:143 + 8e1c67: 58001d call8 8e1cdc + 8e1c6a: 12005e l32r a2, 4e8178 <_lit4_start+0x178> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/clock/src/cmnos_clock.c:145 + 8e1c6d: 8220 l32i.n a2, a2, 0 + 8e1c6f: d10f retw.n + +008e1c71 : + 8e1c71: 000000 ... + +008e1c74 : +cmnos_refclk_speed_get(): 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0x218 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/eeprom/src/cmnos_eeprom.c:339 + 8e1ff7: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/eeprom/src/cmnos_eeprom.c:342 + 8e1ffa: c4e6 movi.n a14, 70 + 8e1ffc: 0c0200 memw + 8e1fff: 2d227d l32i a13, a2, 0x1f4 + 8e2002: 04dd01 and a13, a13, a4 + 8e2005: 0edd02 or a13, a13, a14 + 8e2008: 0c0200 memw + 8e200b: 2d267d s32i a13, a2, 0x1f4 + 8e200e: 1c0077 l32r a12, 4e81dc <_lit4_start+0x1dc> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/eeprom/src/cmnos_eeprom.c:343 + 8e2011: 0c0200 memw + 8e2014: 2b5280 l32i a11, a5, 0x200 + 8e2017: 0cbb02 or a11, a11, a12 + 8e201a: 0c0200 memw + 8e201d: 2b5680 s32i a11, a5, 0x200 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/eeprom/src/cmnos_eeprom.c:353 + 8e2020: 0c0200 memw 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:60 + 8e2456: 692911 bnei a2, 10, 8e246b +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:61 + 8e2459: 283214 l32i a8, a3, 80 + 8e245c: c0ad movi.n a10, 13 + 8e245e: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:62 + 8e2461: 283214 l32i a8, a3, 80 + 8e2464: c0aa movi.n a10, 10 + 8e2466: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:67 + 8e2469: d10f retw.n + +008e246b : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:63 + 8e246b: c09d movi.n a9, 13 + 8e246d: 792107 beq a2, a9, 8e2478 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:65 + 8e2470: 283214 l32i a8, a3, 80 + 8e2473: da20 mov.n a10, a2 + +008e2475 : + 8e2475: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:67 + 8e2478: d10f retw.n + +008e247a : + ... + +008e247c <_cvt>: +_cvt(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:72 + 8e247c: 6c100e entry a1, 112 + 8e247f: cc2a bnez.n a2, 8e248d <_cvt+0x11> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:79 + 8e2481: d810 mov.n a8, a1 + 8e2483: c360 movi.n a6, 48 + 8e2485: 268400 s8i a6, a8, 0 + 8e2488: b116 addi.n a6, a1, 1 + 8e248a: 60001e j 8e24ac <_cvt+0x30> + +008e248d <_cvt+0x11>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:81 + 8e248d: d610 mov.n a6, a1 + +008e248f <_cvt+0x13>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:82 + 8e248f: da20 mov.n a10, a2 + 8e2491: db40 mov.n a11, a4 + 8e2493: 581133 call8 8e6960 <__umodsi3> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:83 + 8e2496: db40 mov.n a11, a4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:82 + 8e2498: aa59 add.n a9, a5, a10 + 8e249a: 299000 l8ui a9, a9, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:83 + 8e249d: da20 mov.n a10, a2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:82 + 8e249f: 296400 s8i a9, a6, 0 + 8e24a2: b166 addi.n a6, a6, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:83 + 8e24a4: 58111a call8 8e6910 <__udivsi3> + 8e24a7: d2a0 mov.n a2, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:81 + 8e24a9: 65afe2 bnez a10, 8e248f <_cvt+0x13> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:90 + 8e24ac: c0d0 movi.n a13, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:81 + 8e24ae: da10 mov.n a10, a1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:86 + 8e24b0: 7a6115 beq a6, a10, 8e24c9 <_cvt+0x4d> + 8e24b3: 0a6b0c sub a11, a6, a10 + 8e24b6: 0bb202 or a2, a11, a11 + 8e24b9: 6db909 loopnez a11, 8e24c6 <_cvt+0x4a> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:87 + 8e24bc: b066 addi.n a6, a6, -1 + 8e24be: 2c6000 l8ui a12, a6, 0 + 8e24c1: 2c3400 s8i a12, a3, 0 + 8e24c4: b133 addi.n a3, a3, 1 + +008e24c6 <_cvt+0x4a>: + 8e24c6: 600001 j 8e24cb <_cvt+0x4f> + +008e24c9 <_cvt+0x4d>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:86 + 8e24c9: c020 movi.n a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:90 + 8e24cb: 2d3400 s8i a13, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:91 + 8e24ce: d10f retw.n + +008e24d0 : +cmnos_vprintf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:96 + 8e24d0: 6c100e entry a1, 112 + 8e24d3: d950 mov.n a9, a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:102 + 8e24d5: dd10 mov.n a13, a1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:96 + 8e24d7: da40 mov.n a10, a4 + 8e24d9: 261611 s32i a6, a1, 68 + 8e24dc: 221613 s32i a2, a1, 76 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:102 + 8e24df: c060 movi.n a6, 0 + 8e24e1: c020 movi.n a2, 0 + 8e24e3: c040 movi.n a4, 0 + 8e24e5: 9d18 s32i.n a13, a1, 32 + 8e24e7: 9a1b s32i.n a10, a1, 44 + 8e24e9: 991a s32i.n a9, a1, 40 + +008e24eb : + 8e24eb: 251213 l32i a5, a1, 76 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:104 + 8e24ee: b133 addi.n a3, a3, 1 + 8e24f0: 273dff addmi a7, a3, 0xffffff00 + 8e24f3: 2770ff l8ui a7, a7, 255 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:105 + 8e24f6: c285 movi.n a8, 37 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:104 + 8e24f8: 6473c4 beqz a7, 8e28c0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:105 + 8e24fb: 787915 bne a7, a8, 8e2514 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:106 + 8e24fe: 273000 l8ui a7, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:108 + 8e2501: c29d movi.n a9, 45 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:106 + 8e2503: b133 addi.n a3, a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:108 + 8e2505: 797932 bne a7, a9, 8e253b +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:109 + 8e2508: 273000 l8ui a7, a3, 0 + 8e250b: c0a1 movi.n a10, 1 + 8e250d: b133 addi.n a3, a3, 1 + 8e250f: 9a1d s32i.n a10, a1, 52 + 8e2511: 60002a j 8e253f + +008e2514 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:284 + 8e2514: da70 mov.n a10, a7 + 8e2516: 0b5000 callx8 a5 + 8e2519: 600019 j 8e2536 + +008e251c : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:220 + 8e251c: c1c8 movi.n a12, 24 + 8e251e: 7bc204 blt a12, a11, 8e2526 + 8e2521: c2d4 movi.n a13, 36 + +008e2523 : + 8e2523: 2d1611 s32i a13, a1, 68 + 8e2526: 8b1b l32i.n a11, a1, 44 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:221 + 8e2528: 2a1211 l32i a10, a1, 68 + 8e252b: abaa add.n a10, a10, a11 + 8e252d: 2aadff addmi a10, a10, 0xffffff00 + 8e2530: 2aa0ff l8ui a10, a10, 255 + 8e2533: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:222 + 8e2536: b122 addi.n a2, a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:223 + 8e2538: 63ffb2 j 8e24ee + +008e253b : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:109 + 8e253b: c0b0 movi.n a11, 0 + 8e253d: 9b1d s32i.n a11, a1, 52 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:112 + 8e253f: c3c0 movi.n a12, 48 + 8e2541: 7c790b bne a7, a12, 8e2550 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:114 + 8e2544: 273000 l8ui a7, a3, 0 + 8e2547: c0d1 movi.n a13, 1 + 8e2549: b133 addi.n a3, a3, 1 + 8e254b: 9d1e s32i.n a13, a1, 56 + 8e254d: 600003 j 8e2554 + +008e2550 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:116 + 8e2550: c0e0 movi.n a14, 0 + 8e2552: 9e1e s32i.n a14, a1, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:118 + 8e2554: 2f7cd0 addi a15, a7, -48 + 8e2557: 0f0f47 extui a15, a15, 0, 8 + 8e255a: 6ff923 bgeui a15, 10, 8e2581 + 8e255d: c080 movi.n a8, 0 + 8e255f: 981c s32i.n a8, a1, 48 + +008e2561 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:119 + 8e2561: 891c l32i.n a9, a1, 48 + 8e2563: 099b0a addx4 a11, a9, a9 + 8e2566: 07bb09 addx2 a11, a11, a7 + 8e2569: 29bcd0 addi a9, a11, -48 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:120 + 8e256c: 273000 l8ui a7, a3, 0 + 8e256f: b133 addi.n a3, a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:119 + 8e2571: 991c s32i.n a9, a1, 48 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:124 + 8e2590: 8f1e l32i.n a15, a1, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:123 + 8e2592: b133 addi.n a3, a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:125 + 8e2594: 2e7cd0 addi a14, a7, -48 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:124 + 8e2597: b1ff addi.n a15, a15, 1 + 8e2599: 9f1e s32i.n a15, a1, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:125 + 8e259b: 0e0e47 extui a14, a14, 0, 8 + 8e259e: 6fe90d bgeui a14, 10, 8e25af + +008e25a1 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:127 + 8e25a1: 273000 l8ui a7, a3, 0 + 8e25a4: b133 addi.n a3, a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:125 + 8e25a6: 287cd0 addi a8, a7, -48 + 8e25a9: 080847 extui a8, a8, 0, 8 + 8e25ac: 6e89f1 bltui a8, 10, 8e25a1 + +008e25af : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:178 + 8e25af: c4c2 movi.n a12, 66 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:133 + 8e25b1: 797916 bne a7, a9, 8e25cb +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:135 + 8e25b4: 273000 l8ui a7, a3, 0 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8e26c5 + 8e25dd: c5e5 movi.n a14, 85 + 8e25df: 7e7902 bne a7, a14, 8e25e5 + 8e25e2: 6000df j 8e26c5 + 8e25e5: c5f8 movi.n a15, 88 + 8e25e7: 7f7902 bne a7, a15, 8e25ed + 8e25ea: 6000d7 j 8e26c5 + 8e25ed: 280a62 movi a8, 98 + 8e25f0: 787902 bne a7, a8, 8e25f6 + 8e25f3: 6000ce j 8e26c5 + 8e25f6: 290a64 movi a9, 100 + 8e25f9: 797902 bne a7, a9, 8e25ff + 8e25fc: 6000c5 j 8e26c5 + 8e25ff: 2c0a70 movi a12, 112 + 8e2602: 7c7902 bne a7, a12, 8e2608 + 8e2605: 6000ba j 8e26c3 + 8e2608: 2d0a75 movi a13, 117 + 8e260b: 7d7902 bne a7, a13, 8e2611 + 8e260e: 6000b3 j 8e26c5 + 8e2611: 2e0a78 movi a14, 120 + 8e2614: 7e7902 bne a7, a14, 8e261a + 8e2617: 6000aa j 8e26c5 + +008e261a : + 8e261a: c0f0 movi.n a15, 0 + 8e261c: 2f1610 s32i a15, a1, 64 + 8e261f: 60002c j 8e264f + +008e2622 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:156 + 8e2622: c188 movi.n a8, 24 + 8e2624: 7a8204 blt a8, a10, 8e262c + 8e2627: c294 movi.n a9, 36 + +008e2629 : + 8e2629: 291611 s32i a9, a1, 68 + 8e262c: 8a1b l32i.n a10, a1, 44 + 8e262e: 241211 l32i a4, a1, 68 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:162 + 8e2631: c484 movi.n a8, 68 + 8e2633: 2b0a64 movi a11, 100 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:156 + 8e2636: aa44 add.n a4, a4, a10 + 8e2638: 244dff addmi a4, a4, 0xffffff00 + 8e263b: 24423f l32i a4, a4, 252 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:162 + 8e263e: 7b7102 beq a7, a11, 8e2644 + 8e2641: 7879d5 bne a7, a8, 8e261a + +008e2644 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:163 + 8e2644: 674fd2 bgez a4, 8e261a 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8e268b: 297cab addi a9, a7, -85 + 8e268e: 649230 beqz a9, 8e28c2 + 8e2691: 2a7ca8 addi a10, a7, -88 + 8e2694: 64a267 beqz a10, 8e28ff + 8e2697: 2b7c9c addi a11, a7, -100 + 8e269a: 64b224 beqz a11, 8e28c2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:206 + 8e269d: 2c0a70 movi a12, 112 + 8e26a0: 7c710e beq a7, a12, 8e26b2 + 8e26a3: 2d7c8b addi a13, a7, -117 + 8e26a6: 64d218 beqz a13, 8e28c2 + 8e26a9: 2e0a78 movi a14, 120 + 8e26ac: 7e7102 beq a7, a14, 8e26b2 + 8e26af: 60008a j 8e273d + +008e26b2 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:201 + 8e26b2: da40 mov.n a10, a4 + 8e26b4: db10 mov.n a11, a1 + 8e26b6: c1c0 movi.n a12, 16 + 8e26b8: 1d00a4 l32r a13, 4e8290 <_lit4_start+0x290> + 8e26bb: 5bff70 call8 8e247c <_cvt> + 8e26be: d6a0 mov.n a6, a10 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8e2750: 9b1f s32i.n a11, a1, 60 + 8e2752: c9a4 beqz.n a10, 8e276a +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:254 + 8e2754: 2c1210 l32i a12, a1, 64 + 8e2757: c8ca beqz.n a12, 8e2765 + 8e2759: dac0 mov.n a10, a12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:255 + 8e275b: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:256 + 8e275e: b122 addi.n a2, a2, 1 + 8e2760: c0d0 movi.n a13, 0 + +008e2762 : + 8e2762: 2d1610 s32i a13, a1, 64 + 8e2765: c370 movi.n a7, 48 + 8e2767: 600001 j 8e276c + +008e276a : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:260 + 8e276a: c270 movi.n a7, 32 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6b91e9 bgei a9, 1, 8e2777 + +008e278d : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:268 + 8e278d: 2b1210 l32i a11, a1, 64 + 8e2790: 8718 l32i.n a7, a1, 32 + 8e2792: c8b5 beqz.n a11, 8e279b + 8e2794: dab0 mov.n a10, a11 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:269 + 8e2796: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:270 + 8e2799: b122 addi.n a2, a2, 1 + +008e279b : + 8e279b: b169 addi.n a9, a6, 1 + 8e279d: 60000c j 8e27ad + +008e27a0 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:273 + 8e27a0: 2a7000 l8ui a10, a7, 0 + 8e27a3: b177 addi.n a7, a7, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:274 + 8e27a5: 0b5000 callx8 a5 + 8e27a8: 291212 l32i a9, a1, 72 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:275 + 8e27ab: b122 addi.n a2, a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:272 + 8e27ad: b066 addi.n a6, a6, -1 + 8e27af: b099 addi.n a9, a9, -1 + 8e27b1: 291612 s32i a9, a1, 72 + 8e27b4: 6b91e8 bgei a9, 1, 8e27a0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:277 + 8e27b7: 8c1d l32i.n a12, a1, 52 + 8e27b9: 9718 s32i.n a7, a1, 32 + 8e27bb: 64cd2f beqz a12, 8e24ee + 8e27be: 8d1f l32i.n a13, a1, 60 + 8e27c0: b1dd addi.n a13, a13, 1 + 8e27c2: 9d19 s32i.n a13, a1, 36 + 8e27c4: 60008a j 8e2852 + +008e27c7 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:139 + 8e27c7: c0a0 movi.n a10, 0 + 8e27c9: 63fe02 j 8e25cf + +008e27cc : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:157 + 8e27cc: 64b10c beqz a11, 8e28dc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:158 + 8e27cf: 2f1211 l32i a15, a1, 68 + 8e27d2: c1b8 movi.n a11, 24 + 8e27d4: c1e8 movi.n a14, 24 + 8e27d6: daf0 mov.n a10, a15 + 8e27d8: b4ff addi.n a15, a15, 4 + 8e27da: 2f1611 s32i a15, a1, 68 + 8e27dd: 7fe27d blt a14, a15, 8e285e + 8e27e0: 8a1a l32i.n a10, a1, 40 + 8e27e2: 63fe48 j 8e262e + +008e27e5 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:247 + 8e27e5: 280a64 movi a8, 100 + 8e27e8: 78723d blt a7, a8, 8e2829 + 8e27eb: 290a64 movi a9, 100 + 8e27ee: 779202 blt a9, a7, 8e27f4 + 8e27f1: 63fe90 j 8e2685 + 8e27f4: 2a0a70 movi a10, 112 + 8e27f7: 7a7934 bne a7, a10, 8e282f +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:182 + 8e27fa: c3a0 movi.n a10, 48 + 8e27fc: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:183 + 8e27ff: 2a0a78 movi a10, 120 + 8e2802: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:185 + 8e2805: c0b8 movi.n a11, 8 + 8e2807: c0c1 movi.n a12, 1 + 8e2809: 9c1e s32i.n a12, a1, 56 + 8e280b: 9b1c s32i.n a11, a1, 48 + 8e280d: 63fe74 j 8e2685 + +008e2810 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:247 + 8e2810: c5d3 movi.n a13, 83 + 8e2812: 7d7919 bne a7, a13, 8e282f + +008e2815 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:211 + 8e2815: 2f1211 l32i a15, a1, 68 + 8e2818: c1e8 movi.n a14, 24 + 8e281a: dbf0 mov.n a11, a15 + 8e281c: b4ff addi.n a15, a15, 4 + 8e281e: 2f1611 s32i a15, a1, 68 + 8e2821: 7fe246 blt a14, a15, 8e286b + 8e2824: 891a l32i.n a9, a1, 40 + 8e2826: 60004d j 8e2877 + +008e2829 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:247 + 8e2829: 280a63 movi a8, 99 + 8e282c: 787179 beq a7, a8, 8e28a9 + +008e282f : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:244 + 8e282f: c2a5 movi.n a10, 37 + 8e2831: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:245 + 8e2834: da70 mov.n a10, a7 + 8e2836: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:246 + 8e2839: b222 addi.n a2, a2, 2 + 8e283b: 63ff02 j 8e2741 + +008e283e : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:247 + 8e283e: c295 movi.n a9, 37 + 8e2840: 7979eb bne a7, a9, 8e282f +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:241 + 8e2843: c2a5 movi.n a10, 37 + 8e2845: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:242 + 8e2848: 63fef5 j 8e2741 + +008e284b : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:279 + 8e284b: c2a0 movi.n a10, 32 + 8e284d: 0b5000 callx8 a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:280 + 8e2850: b122 addi.n a2, a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:278 + 8e2852: 8a19 l32i.n a10, a1, 36 + 8e2854: b0aa addi.n a10, a10, -1 + 8e2856: 9a19 s32i.n a10, a1, 36 + 8e2858: 6ba1ef bgei a10, 1, 8e284b + 8e285b: 63fc8f j 8e24ee + +008e285e : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:158 + 8e285e: 7ab204 blt a11, a10, 8e2866 + 8e2861: c2c4 movi.n a12, 36 + +008e2863 : + 8e2863: 2c1611 s32i a12, a1, 68 + 8e2866: 8a1b l32i.n a10, a1, 44 + 8e2868: 63fdc2 j 8e262e + +008e286b : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:211 + 8e286b: c1d8 movi.n a13, 24 + 8e286d: 7bd204 blt a13, a11, 8e2875 + 8e2870: c2e4 movi.n a14, 36 + +008e2872 : + 8e2872: 2e1611 s32i a14, a1, 68 + 8e2875: 891b l32i.n a9, a1, 44 + 8e2877: 2f1211 l32i a15, a1, 68 + 8e287a: a9ff add.n a15, a15, a9 + 8e287c: 2ffdff addmi a15, a15, 0xffffff00 + 8e287f: 2ff23f l32i a15, a15, 252 + 8e2882: 9f18 s32i.n a15, a1, 32 + 8e2884: ccf3 bnez.n a15, 8e288b + 8e2886: 1800a5 l32r a8, 4e8294 <_lit4_start+0x294> + 8e2889: 9818 s32i.n a8, a1, 32 + +008e288b : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:216 + 8e288b: 8918 l32i.n a9, a1, 32 + 8e288d: 299000 l8ui a9, a9, 0 + 8e2890: c060 movi.n a6, 0 + 8e2892: 64907a beqz a9, 8e2910 + 8e2895: 8918 l32i.n a9, a1, 32 + +008e2897 : + 8e2897: 2a9001 l8ui a10, a9, 1 + 8e289a: b166 addi.n a6, a6, 1 + 8e289c: b199 addi.n a9, a9, 1 + 8e289e: 65aff5 bnez a10, 8e2897 + 8e28a1: 63fe9c j 8e2741 + +008e28a4 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:247 + 8e28a4: c4b3 movi.n a11, 67 + 8e28a6: 7b7985 bne a7, a11, 8e282f + +008e28a9 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:220 + 8e28a9: 2d1211 l32i a13, a1, 68 + 8e28ac: c1c8 movi.n a12, 24 + 8e28ae: dbd0 mov.n a11, a13 + 8e28b0: b4dd addi.n a13, a13, 4 + 8e28b2: 2d1611 s32i a13, a1, 68 + 8e28b5: 7dca02 bge a12, a13, 8e28bb + 8e28b8: 63fc60 j 8e251c + 8e28bb: 8b1a l32i.n a11, a1, 40 + 8e28bd: 63fc67 j 8e2528 + +008e28c0 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:288 + 8e28c0: d10f retw.n + +008e28c2 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:197 + 8e28c2: da40 mov.n a10, a4 + 8e28c4: db10 mov.n a11, a1 + 8e28c6: c0ca movi.n a12, 10 + 8e28c8: 1d00a6 l32r a13, 4e8298 <_lit4_start+0x298> + 8e28cb: 5bfeec call8 8e247c <_cvt> + 8e28ce: d6a0 mov.n a6, a10 + 8e28d0: 63fe69 j 8e273d + +008e28d3 : + 8e28d3: 2e7c8b addi a14, a7, -117 + 8e28d6: 65ef55 bnez a14, 8e282f + 8e28d9: 63fda8 j 8e2685 + +008e28dc : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:160 + 8e28dc: 281211 l32i a8, a1, 68 + 8e28df: c1f8 movi.n a15, 24 + 8e28e1: da80 mov.n a10, a8 + 8e28e3: b488 addi.n a8, a8, 4 + 8e28e5: 281611 s32i a8, a1, 68 + 8e28e8: 78f204 blt a15, a8, 8e28f0 + 8e28eb: 8a1a l32i.n a10, a1, 40 + 8e28ed: 63fd3d j 8e262e + +008e28f0 : + 8e28f0: c198 movi.n a9, 24 + 8e28f2: 7a9204 blt a9, a10, 8e28fa + 8e28f5: c2a4 movi.n a10, 36 + +008e28f7 : + 8e28f7: 2a1611 s32i a10, a1, 68 + 8e28fa: 8a1b l32i.n a10, a1, 44 + 8e28fc: 63fd2e j 8e262e + +008e28ff : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:204 + 8e28ff: da40 mov.n a10, a4 + 8e2901: db10 mov.n a11, a1 + 8e2903: c1c0 movi.n a12, 16 + 8e2905: 1d00a7 l32r a13, 4e829c <_lit4_start+0x29c> + 8e2908: 5bfedc call8 8e247c <_cvt> + 8e290b: d6a0 mov.n a6, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:205 + 8e290d: 63fe2c j 8e273d + +008e2910 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:216 + 8e2910: c060 movi.n a6, 0 + 8e2912: 63fe2b j 8e2741 + +008e2915 : + 8e2915: 000000 ... + +008e2918 : +cmnos_printf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:292 + 8e2918: 6c100a entry a1, 80 + 8e291b: db20 mov.n a11, a2 + 8e291d: 9214 s32i.n a2, a1, 16 + 8e291f: 9416 s32i.n a4, a1, 24 + 8e2921: 9517 s32i.n a5, a1, 28 + 8e2923: 9618 s32i.n a6, a1, 32 + 8e2925: 9719 s32i.n a7, a1, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:300 + 8e2927: de10 mov.n a14, a1 + 8e2929: 1a00a8 l32r a10, 4e82a0 <_lit4_start+0x2a0> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:292 + 8e292c: 9315 s32i.n a3, a1, 20 + 8e292e: 2f1c30 addi a15, a1, 48 + 8e2931: 2d1c10 addi a13, a1, 16 + 8e2934: 9d11 s32i.n a13, a1, 4 + 8e2936: 9f10 s32i.n a15, a1, 0 + 8e2938: c034 movi.n a3, 4 + 8e293a: 9312 s32i.n a3, a1, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:300 + 8e293c: 8aa0 l32i.n a10, a10, 0 + 8e293e: 8ce0 l32i.n a12, a14, 0 + 8e2940: 8de1 l32i.n a13, a14, 4 + 8e2942: 8ee2 l32i.n a14, a14, 8 + 8e2944: 5bfee2 call8 8e24d0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:307 + 8e2947: d2a0 mov.n a2, a10 + 8e2949: d10f retw.n + +008e294b : + ... + +008e294c : +cmnos_printf_init(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:312 + 8e294c: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:313 + 8e294f: d10f retw.n + +008e2951 : + 8e2951: 000000 ... + +008e2954 : +cmnos_printf_module_install(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:316 + 8e2954: 6c1004 entry a1, 32 + 8e2957: 1800a9 l32r a8, 4e82a4 <_lit4_start+0x2a4> + 8e295a: 1300aa l32r a3, 4e82a8 <_lit4_start+0x2a8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:318 + 8e295d: 9321 s32i.n a3, a2, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:317 + 8e295f: 9820 s32i.n a8, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/printf/src/cmnos_printf.c:319 + 8e2961: d10f retw.n + +008e2963 : + ... + +008e2964 <_patch_dump>: +_patch_dump(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:36 + 8e2964: 6c1004 entry a1, 32 + 8e2967: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:42 + 8e296a: 2b2101 l16ui a11, a2, 2 + 8e296d: 8c21 l32i.n a12, a2, 4 + 8e296f: 288212 l32i a8, a8, 72 + 8e2972: 8d22 l32i.n a13, a2, 8 + 8e2974: 1a00ab l32r a10, 4e82ac <_lit4_start+0x2ac> + 8e2977: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:43 + 8e297a: d10f retw.n + +008e297c <_read_rom_patch>: +_read_rom_patch(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:49 + 8e297c: 6c1004 entry a1, 32 + 8e297f: 1900ac l32r a9, 4e82b0 <_lit4_start+0x2b0> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:60 + 8e2982: 8321 l32i.n a3, a2, 4 + 8e2984: 1800ad l32r a8, 4e82b4 <_lit4_start+0x2b4> + 8e2987: 140018 l32r a4, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:61 + 8e298a: a939 add.n a9, a3, a9 + 8e298c: 798b0e bgeu a8, a9, 8e299e <_read_rom_patch+0x22> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:64 + 8e298f: 284212 l32i a8, a4, 72 + 8e2992: db30 mov.n a11, a3 + 8e2994: 1a00ae l32r a10, 4e82b8 <_lit4_start+0x2b8> + 8e2997: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:65 + 8e299a: c020 movi.n a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:81 + 8e299c: d10f retw.n + +008e299e <_read_rom_patch+0x22>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/cmnos/rompatch/src/cmnos_rompatch.c:68 + 8e299e: da20 mov.n a10, a2 + 8e29a0: 5bfff0 call8 8e2964 <_patch_dump> + 8e29a3: 1a00af l32r a10, 4e82bc <_lit4_start+0x2bc> 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2822cd l32i a8, a2, 0x334 + 8e307f: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:189 + 8e3082: 2822bd l32i a8, a2, 0x2f4 + 8e3085: c0a4 movi.n a10, 4 + 8e3087: c0b1 movi.n a11, 1 + 8e3089: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:190 + 8e308c: 2822bf l32i a8, a2, 0x2fc + 8e308f: c0a0 movi.n a10, 0 + 8e3091: c0b1 movi.n a11, 1 + 8e3093: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:192 + 8e3096: c0a0 movi.n a10, 0 + 8e3098: 2822c0 l32i a8, a2, 0x300 + 8e309b: c0b2 movi.n a11, 2 + 8e309d: 2c6a80 movi a12, 0x680 + 8e30a0: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:195 + 8e30a3: d10f retw.n + +008e30a5 <__pci_boot_init+0x35>: + 8e30a5: 000000 ... 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:247 + 8e3129: 2862c0 l32i a8, a6, 0x300 + 8e312c: da50 mov.n a10, a5 + 8e312e: 0c0c4f extui a12, a12, 0, 16 + 8e3131: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:248 + 8e3134: d10f retw.n + +008e3136 <__pci_cfg_pipe+0x3a>: + ... + +008e3138 <__pci_start>: +__pci_start(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:256 + 8e3138: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:257 + 8e313b: d10f retw.n + +008e313d <__pci_start+0x5>: + 8e313d: 000000 ... + +008e3140 <__pci_reg_callback>: +__pci_reg_callback(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:267 + 8e3140: 6c1004 entry a1, 32 + 8e3143: 1400e8 l32r a4, 4e83a0 <_lit4_start+0x3a0> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:270 + 8e3146: 8932 l32i.n a9, a3, 8 + 8e3148: 9942 s32i.n a9, a4, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:271 + 8e314a: 8831 l32i.n a8, a3, 4 + 8e314c: 9841 s32i.n a8, a4, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:272 + 8e314e: 8230 l32i.n a2, a3, 0 + 8e3150: 9240 s32i.n a2, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:273 + 8e3152: d10f retw.n + +008e3154 <__pci_reap_xmitted>: +__pci_reap_xmitted(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:283 + 8e3154: 6c1004 entry a1, 32 + 8e3157: 140018 l32r a4, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:287 + 8e315a: 2842d0 l32i a8, a4, 0x340 + 8e315d: da30 mov.n a10, a3 + 8e315f: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:289 + 8e3162: 2842c6 l32i a8, a4, 0x318 + 8e3165: da30 mov.n a10, a3 + 8e3167: 0b8000 callx8 a8 + 8e316a: c8a7 beqz.n a10, 8e3175 <__pci_reap_xmitted+0x21> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:292 + 8e316c: 8820 l32i.n a8, a2, 0 + 8e316e: 8b22 l32i.n a11, a2, 8 + 8e3170: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:297 + 8e3173: d10f retw.n + +008e3175 <__pci_reap_xmitted+0x21>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:294 + 8e3175: 284212 l32i a8, a4, 72 + 8e3178: 1a00ea l32r a10, 4e83a8 <_lit4_start+0x3a8> + 8e317b: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:297 + 8e317e: d10f retw.n + +008e3180 <__pci_reap_recv>: +__pci_reap_recv(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:308 + 8e3180: 6c1004 entry a1, 32 + 8e3183: da30 mov.n a10, a3 + 8e3185: 130018 l32r a3, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:311 + 8e3188: 2832c7 l32i a8, a3, 0x31c + 8e318b: 0b8000 callx8 a8 + 8e318e: dba0 mov.n a11, a10 + 8e3190: c8a9 beqz.n a10, 8e319d <__pci_reap_recv+0x1d> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:314 + 8e3192: 8821 l32i.n a8, a2, 4 + 8e3194: 8c22 l32i.n a12, a2, 8 + 8e3196: c0a0 movi.n a10, 0 + 8e3198: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:317 + 8e319b: d10f retw.n + +008e319d <__pci_reap_recv+0x1d>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:316 + 8e319d: 283212 l32i a8, a3, 72 + 8e31a0: 1a00eb l32r a10, 4e83ac <_lit4_start+0x3ac> + 8e31a3: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:317 + 8e31a6: d10f retw.n + +008e31a8 <__pci_isr_handler>: +__pci_isr_handler(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:325 + 8e31a8: 6c1004 entry a1, 32 + 8e31ab: 1300e8 l32r a3, 4e83a0 <_lit4_start+0x3a0> + 8e31ae: 120018 l32r a2, 4e8060 <_lit4_start+0x60> + 8e31b1: 600009 j 8e31be <__pci_isr_handler+0x16> + +008e31b4 <__pci_isr_handler+0xc>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:330 + 8e31b4: 2822cf l32i a8, a2, 0x33c + 8e31b7: da30 mov.n a10, a3 + 8e31b9: c0b3 movi.n a11, 3 + 8e31bb: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:329 + 8e31be: 2822c9 l32i a8, a2, 0x324 + 8e31c1: c0a3 movi.n a10, 3 + 8e31c3: 0b8000 callx8 a8 + 8e31c6: 65afea bnez a10, 8e31b4 <__pci_isr_handler+0xc> + 8e31c9: 600009 j 8e31d6 <__pci_isr_handler+0x2e> + +008e31cc <__pci_isr_handler+0x24>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:333 + 8e31cc: 2822cf l32i a8, a2, 0x33c + 8e31cf: da30 mov.n a10, a3 + 8e31d1: c0b2 movi.n a11, 2 + 8e31d3: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:332 + 8e31d6: 2822c9 l32i a8, a2, 0x324 + 8e31d9: c0a2 movi.n a10, 2 + 8e31db: 0b8000 callx8 a8 + 8e31de: 65afea bnez a10, 8e31cc <__pci_isr_handler+0x24> + 8e31e1: 600009 j 8e31ee <__pci_isr_handler+0x46> + +008e31e4 <__pci_isr_handler+0x3c>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:336 + 8e31e4: 2822cf l32i a8, a2, 0x33c + 8e31e7: da30 mov.n a10, a3 + 8e31e9: c0b1 movi.n a11, 1 + 8e31eb: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:335 + 8e31ee: 2822c9 l32i a8, a2, 0x324 + 8e31f1: c0a1 movi.n a10, 1 + 8e31f3: 0b8000 callx8 a8 + 8e31f6: 65afea bnez a10, 8e31e4 <__pci_isr_handler+0x3c> + 8e31f9: 600009 j 8e3206 <__pci_isr_handler+0x5e> + +008e31fc <__pci_isr_handler+0x54>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:339 + 8e31fc: 2822ce l32i a8, a2, 0x338 + 8e31ff: da30 mov.n a10, a3 + 8e3201: c0b5 movi.n a11, 5 + 8e3203: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:338 + 8e3206: 2822c5 l32i a8, a2, 0x314 + 8e3209: c0a5 movi.n a10, 5 + 8e320b: 0b8000 callx8 a8 + 8e320e: 65afea bnez a10, 8e31fc <__pci_isr_handler+0x54> + +008e3211 <__pci_isr_handler+0x69>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:345 + 8e3211: 2822c5 l32i a8, a2, 0x314 + 8e3214: c0a4 movi.n a10, 4 + 8e3216: 0b8000 callx8 a8 + 8e3219: c8ad beqz.n a10, 8e322a <__pci_isr_handler+0x82> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:346 + 8e321b: 2822ce l32i a8, a2, 0x338 + 8e321e: da30 mov.n a10, a3 + 8e3220: c0b4 movi.n a11, 4 + 8e3222: 0b8000 callx8 a8 + 8e3225: c041 movi.n a4, 1 + 8e3227: 600001 j 8e322c <__pci_isr_handler+0x84> + +008e322a <__pci_isr_handler+0x82>: + 8e322a: c040 movi.n a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:350 + 8e322c: 2822c9 l32i a8, a2, 0x324 + 8e322f: c0a0 movi.n a10, 0 + 8e3231: 0b8000 callx8 a8 + 8e3234: c8aa beqz.n a10, 8e3242 <__pci_isr_handler+0x9a> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:351 + 8e3236: 2822cf l32i a8, a2, 0x33c + 8e3239: da30 mov.n a10, a3 + 8e323b: c0b0 movi.n a11, 0 + 8e323d: 0b8000 callx8 a8 + 8e3240: c041 movi.n a4, 1 + +008e3242 <__pci_isr_handler+0x9a>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:355 + 8e3242: 654fcb bnez a4, 8e3211 <__pci_isr_handler+0x69> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:357 + 8e3245: d10f retw.n + +008e3247 <__pci_isr_handler+0x9f>: + ... + +008e3248 <__pci_xmit_buf>: +__pci_xmit_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:369 + 8e3248: 6c1004 entry a1, 32 + 8e324b: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:372 + 8e324e: 2822d1 l32i a8, a2, 0x344 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:369 + 8e3251: da30 mov.n a10, a3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:372 + 8e3253: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:374 + 8e3256: 69a60c bnei a10, 6, 8e3266 <__pci_xmit_buf+0x1e> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:375 + 8e3259: 282212 l32i a8, a2, 72 + 8e325c: 1a00ec l32r a10, 4e83b0 <_lit4_start+0x3b0> + 8e325f: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:376 + 8e3262: c72f movi.n a2, -1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:379 + 8e3264: d10f retw.n + +008e3266 <__pci_xmit_buf+0x1e>: + 8e3266: 2822c3 l32i a8, a2, 0x30c + 8e3269: db40 mov.n a11, a4 + 8e326b: 0b8000 callx8 a8 + 8e326e: d2a0 mov.n a2, a10 + 8e3270: d10f retw.n + +008e3272 <__pci_xmit_buf+0x2a>: + ... + +008e3274 <__pci_return_recv>: +__pci_return_recv(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:390 + 8e3274: 6c1004 entry a1, 32 + 8e3277: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:393 + 8e327a: 2822d2 l32i a8, a2, 0x348 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:390 + 8e327d: da30 mov.n a10, a3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:393 + 8e327f: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:395 + 8e3282: 68a607 beqi a10, 6, 8e328d <__pci_return_recv+0x19> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:398 + 8e3285: 2822c8 l32i a8, a2, 0x320 + 8e3288: db40 mov.n a11, a4 + +008e328a <__pci_return_recv+0x16>: + 8e328a: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:399 + 8e328d: d10f retw.n + +008e328f <__pci_return_recv+0x1b>: + ... + +008e3290 <__pci_is_pipe_supported>: +__pci_is_pipe_supported(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:410 + 8e3290: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:411 + 8e3293: 6f3503 bgeui a3, 5, 8e329a <__pci_is_pipe_supported+0xa> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:412 + 8e3296: c021 movi.n a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:414 + 8e3298: d10f retw.n + +008e329a <__pci_is_pipe_supported+0xa>: + 8e329a: c020 movi.n a2, 0 + 8e329c: d10f retw.n + +008e329e <__pci_is_pipe_supported+0xe>: + ... + +008e32a0 <__pci_get_max_msg_len>: +__pci_get_max_msg_len(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:426 + 8e32a0: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:430 + 8e32a3: 246a80 movi a4, 0x680 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:428 + 8e32a6: 222a00 movi a2, 0x200 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:427 + 8e32a9: 034239 movnez a2, a4, a3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/pci//hif_pci.c:430 + 8e32ac: d10f retw.n + +008e32ae <__pci_get_max_msg_len+0xe>: + ... + +008e32b0 <__pci_get_reserved_headroom>: +__pci_get_reserved_headroom(): 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8e3434: 9242 s32i.n a2, a4, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:143 + 8e3436: d10f retw.n + +008e3438 <_HIFusb_start>: +_HIFusb_start(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:148 + 8e3438: 6c1004 entry a1, 32 + 8e343b: 140018 l32r a4, 4e8060 <_lit4_start+0x60> + 8e343e: 130101 l32r a3, 4e8404 <_lit4_start+0x404> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:156 + 8e3441: 284212 l32i a8, a4, 72 + 8e3444: 1a010a l32r a10, 4e8428 <_lit4_start+0x428> + 8e3447: 8b33 l32i.n a11, a3, 12 + 8e3449: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:157 + 8e344c: 284212 l32i a8, a4, 72 + 8e344f: 1a010b l32r a10, 4e842c <_lit4_start+0x42c> + 8e3452: 8b35 l32i.n a11, a3, 20 + 8e3454: 0b8000 callx8 a8 + 8e3457: 15010c l32r a5, 4e8430 <_lit4_start+0x430> + 8e345a: 12010d l32r a2, 4e8434 <_lit4_start+0x434> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:159 + 8e345d: 8a33 l32i.n a10, a3, 12 + 8e345f: 0c0200 memw + 8e3462: 2a2680 s32i a10, a2, 0x200 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:160 + 8e3465: 8935 l32i.n a9, a3, 20 + 8e3467: 0c0200 memw + 8e346a: 295680 s32i a9, a5, 0x200 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:162 + 8e346d: 284212 l32i a8, a4, 72 + 8e3470: 1a010e l32r a10, 4e8438 <_lit4_start+0x438> + 8e3473: 8b39 l32i.n a11, a3, 36 + 8e3475: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:163 + 8e3478: 8939 l32i.n a9, a3, 36 + 8e347a: 0c0200 memw + 8e347d: 2926c0 s32i a9, a2, 0x300 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:167 + 8e3480: 284212 l32i a8, a4, 72 + 8e3483: 1a010f l32r a10, 4e843c <_lit4_start+0x43c> + 8e3486: 8b3b l32i.n a11, a3, 44 + 8e3488: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:168 + 8e348b: c0a1 movi.n a10, 1 + 8e348d: 8d3b l32i.n a13, a3, 44 + 8e348f: 0c0200 memw + 8e3492: 9d50 s32i.n a13, a5, 0 + 8e3494: 1c0110 l32r a12, 4e8440 <_lit4_start+0x440> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:171 + 8e3497: c7bf movi.n a11, -1 + 8e3499: 0c0200 memw + 8e349c: 2bc681 s32i a11, a12, 0x204 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:172 + 8e349f: 0c0200 memw + 8e34a2: 2a2681 s32i a10, a2, 0x204 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:233 + 8e34e8: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:236 + 8e34eb: 692104 bnei a2, 1, 8e34f3 + 8e34ee: 120106 l32r a2, 4e8418 <_lit4_start+0x418> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:255 + 8e34f1: d10f retw.n + +008e34f3 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:240 + 8e34f3: 692504 bnei a2, 5, 8e34fb + 8e34f6: 120108 l32r a2, 4e8420 <_lit4_start+0x420> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:255 + 8e34f9: d10f retw.n + +008e34fb : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:246 + 8e34fb: 682602 beqi a2, 6, 8e3501 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:252 + 8e34fe: 63fffc j 8e34fe + +008e3501 : + 8e3501: 120109 l32r a2, 4e8424 <_lit4_start+0x424> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:255 + 8e3504: d10f retw.n + +008e3506 : + ... + +008e3508 <_HIFusb_config_pipe>: +_HIFusb_config_pipe(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:263 + 8e3508: 6c1006 entry a1, 48 + 8e350b: 9410 s32i.n a4, a1, 0 + 8e350d: 160018 l32r a6, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:269 + 8e3510: 683423 beqi a3, 4, 8e3537 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a1, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:296 + 8e3572: b144 addi.n a4, a4, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:282 + 8e3574: c0c0 movi.n a12, 0 + 8e3576: 9c50 s32i.n a12, a5, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:283 + 8e3578: 2c5505 s16i a12, a5, 10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:284 + 8e357b: 2c5506 s16i a12, a5, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:285 + 8e357e: 2c5507 s16i a12, a5, 14 + 8e3581: c870 beqz.n a7, 8e3585 <_HIFusb_config_pipe+0x7d> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:293 + 8e3583: 9750 s32i.n a7, a5, 0 + +008e3585 <_HIFusb_config_pipe+0x7d>: + 8e3585: d750 mov.n a7, a5 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:274 + 8e3587: 74b9b5 bne a11, a4, 8e3540 <_HIFusb_config_pipe+0x38> + 8e358a: 600001 j 8e358f <_HIFusb_config_pipe+0x87> + +008e358d <_HIFusb_config_pipe+0x85>: + 8e358d: d7c0 mov.n a7, a12 + 8e358f: c97e beqz.n a7, 8e35b1 <_HIFusb_config_pipe+0xa9> + 8e3591: 120101 l32r a2, 4e8404 <_lit4_start+0x404> + +008e3594 <_HIFusb_config_pipe+0x8c>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:196 + 8e3594: 2862a1 l32i a8, a6, 0x284 + 8e3597: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:200 + 8e359a: c0b0 movi.n a11, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:198 + 8e359c: 97a0 s32i.n a7, a10, 0 + 8e359e: dc70 mov.n a12, a7 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:202 + 8e35a0: 892d l32i.n a9, a2, 52 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:199 + 8e35a2: 8770 l32i.n a7, a7, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:200 + 8e35a4: 9bc0 s32i.n a11, a12, 0 + 8e35a6: c890 beqz.n a9, 8e35aa <_HIFusb_config_pipe+0xa2> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:205 + 8e35a8: 99a1 s32i.n a9, a10, 4 + +008e35aa <_HIFusb_config_pipe+0xa2>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:206 + 8e35aa: 9a2d s32i.n a10, a2, 52 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:195 + 8e35ac: 657fe4 bnez a7, 8e3594 <_HIFusb_config_pipe+0x8c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:299 + 8e35af: d10f retw.n + +008e35b1 <_HIFusb_config_pipe+0xa9>: + 8e35b1: d10f retw.n + +008e35b3 <_HIFusb_config_pipe+0xab>: + ... + +008e35b4 <_HIFusb_send_buffer>: +_HIFusb_send_buffer(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:335 + 8e35b4: 6c1004 entry a1, 32 + 8e35b7: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:336 + 8e35ba: 693335 bnei a3, 3, 8e35f3 <_HIFusb_send_buffer+0x3f> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:315 + 8e35bd: 8a40 l32i.n a10, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:317 + 8e35bf: 2da106 l16ui a13, a10, 12 + 8e35c2: 0c0200 memw +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:318 + 8e35c5: 8ca1 l32i.n a12, a10, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:317 + 8e35c7: 2da50b s16i a13, a10, 22 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:318 + 8e35ca: 2ba105 l16ui a11, a10, 10 + 8e35cd: acbb add.n a11, a11, a12 + 8e35cf: 0c0200 memw +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:320 + 8e35d2: 2822b6 l32i a8, a2, 0x2d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:318 + 8e35d5: 9ba7 s32i.n a11, a10, 28 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:320 + 8e35d7: 2aac10 addi a10, a10, 16 + 8e35da: 0b8000 callx8 a8 + 8e35dd: 1a0101 l32r a10, 4e8404 <_lit4_start+0x404> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:323 + 8e35e0: 8eae l32i.n a14, a10, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:327 + 8e35e2: 8baf l32i.n a11, a10, 60 + 8e35e4: cee5 bnez.n a14, 8e360d <_HIFusb_send_buffer+0x59> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:324 + 8e35e6: 94ae s32i.n a4, a10, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:331 + 8e35e8: 282297 l32i a8, a2, 0x25c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:328 + 8e35eb: 94af s32i.n a4, a10, 60 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:331 + 8e35ed: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:337 + 8e35f0: 600015 j 8e3609 <_HIFusb_send_buffer+0x55> + +008e35f3 <_HIFusb_send_buffer+0x3f>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:339 + 8e35f3: 2822b1 l32i a8, a2, 0x2c4 + 8e35f6: db40 mov.n a11, a4 + 8e35f8: 1a0107 l32r a10, 4e841c <_lit4_start+0x41c> + 8e35fb: 0b8000 callx8 a8 + 8e35fe: 1a010c l32r a10, 4e8430 <_lit4_start+0x430> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:343 + 8e3601: c091 movi.n a9, 1 + 8e3603: 0c0200 memw + 8e3606: 29a681 s32i a9, a10, 0x204 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:347 + 8e3609: c020 movi.n a2, 0 + 8e360b: d10f retw.n + +008e360d <_HIFusb_send_buffer+0x59>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:327 + 8e360d: 94b1 s32i.n a4, a11, 4 + 8e360f: 63ffd5 j 8e35e8 <_HIFusb_send_buffer+0x34> + +008e3612 <_HIFusb_send_buffer+0x5e>: + ... + +008e3614 <_HIFusb_return_recv_buf>: +_HIFusb_return_recv_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:352 + 8e3614: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:355 + 8e3617: 69340c bnei a3, 4, 8e3627 <_HIFusb_return_recv_buf+0x13> + 8e361a: 1a0101 l32r a10, 4e8404 <_lit4_start+0x404> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:356 + 8e361d: 89ad l32i.n a9, a10, 52 + 8e361f: c890 beqz.n a9, 8e3623 <_HIFusb_return_recv_buf+0xf> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:359 + 8e3621: 9941 s32i.n a9, a4, 4 + +008e3623 <_HIFusb_return_recv_buf+0xf>: + 8e3623: 94ad s32i.n a4, a10, 52 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:367 + 8e3625: d10f retw.n + +008e3627 <_HIFusb_return_recv_buf+0x13>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:363 + 8e3627: da30 mov.n a10, a3 + 8e3629: 5bffaf call8 8e34e8 + 8e362c: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:364 + 8e362f: 2882b4 l32i a8, a8, 0x2d0 + 8e3632: db40 mov.n a11, a4 + 8e3634: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:365 + 8e3637: da30 mov.n a10, a3 + 8e3639: 5bffa0 call8 8e34bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:367 + 8e363c: d10f retw.n + +008e363e <_HIFusb_return_recv_buf+0x2a>: + ... + +008e3640 <_HIFusb_set_recv_bufsz>: +_HIFusb_set_recv_bufsz(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:370 + 8e3640: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:373 + 8e3643: d10f retw.n + +008e3645 <_HIFusb_set_recv_bufsz+0x5>: + 8e3645: 000000 ... + +008e3648 <_HIFusb_pause_recv>: +_HIFusb_pause_recv(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:376 + 8e3648: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:378 + 8e364b: d10f retw.n + +008e364d <_HIFusb_pause_recv+0x5>: + 8e364d: 000000 ... + +008e3650 <_HIFusb_resume_recv>: +_HIFusb_resume_recv(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:381 + 8e3650: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:383 + 8e3653: d10f retw.n + +008e3655 <_HIFusb_resume_recv+0x5>: + 8e3655: 000000 ... + +008e3658 <_HIFusb_is_pipe_supported>: +_HIFusb_is_pipe_supported(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:386 + 8e3658: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:387 + 8e365b: b034 addi.n a4, a3, -1 + 8e365d: 6e4603 bltui a4, 6, 8e3664 <_HIFusb_is_pipe_supported+0xc> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:388 + 8e3660: c020 movi.n a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:390 + 8e3662: d10f retw.n + +008e3664 <_HIFusb_is_pipe_supported+0xc>: + 8e3664: c021 movi.n a2, 1 + 8e3666: d10f retw.n + +008e3668 <_HIFusb_get_max_msg_len>: +_HIFusb_get_max_msg_len(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:395 + 8e3668: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:403 + 8e366b: 6b3506 bgei a3, 5, 8e3675 <_HIFusb_get_max_msg_len+0xd> + 8e366e: 6a3303 blti a3, 3, 8e3675 <_HIFusb_get_max_msg_len+0xd> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:399 + 8e3671: c420 movi.n a2, 64 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:402 + 8e3673: d10f retw.n + +008e3675 <_HIFusb_get_max_msg_len+0xd>: + 8e3675: 226a40 movi a2, 0x640 + 8e3678: d10f retw.n + +008e367a <_HIFusb_get_max_msg_len+0x12>: + ... + +008e367c <_HIFusb_isr_handler>: +_HIFusb_isr_handler(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:518 + 8e367c: 6c1004 entry a1, 32 + 8e367f: 190110 l32r a9, 4e8440 <_lit4_start+0x440> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:525 + 8e3682: 0c0200 memw + 8e3685: 180111 l32r a8, 4e8444 <_lit4_start+0x444> + 8e3688: 299280 l32i a9, a9, 0x200 + 8e368b: 140108 l32r a4, 4e8420 <_lit4_start+0x420> + 8e368e: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:532 + 8e3691: 798802 bany a8, a9, 8e3697 <_HIFusb_isr_handler+0x1b> + 8e3694: 60008f j 8e3727 <_HIFusb_isr_handler+0xab> + 8e3697: 234cdc addi a3, a4, -36 + 8e369a: 600012 j 8e36b0 <_HIFusb_isr_handler+0x34> + +008e369d <_HIFusb_isr_handler+0x21>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:488 + 8e369d: 2822b3 l32i a8, a2, 0x2cc + 8e36a0: da40 mov.n a10, a4 + 8e36a2: 0b8000 callx8 a8 + 8e36a5: dba0 mov.n a11, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:489 + 8e36a7: 8831 l32i.n a8, a3, 4 + 8e36a9: 8c32 l32i.n a12, a3, 8 + 8e36ab: c0a0 movi.n a10, 0 + 8e36ad: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:538 + 8e36b0: 2822b7 l32i a8, a2, 0x2dc + 8e36b3: da40 mov.n a10, a4 + 8e36b5: 0b8000 callx8 a8 + 8e36b8: 65afe1 bnez a10, 8e369d <_HIFusb_isr_handler+0x21> + 8e36bb: 140109 l32r a4, 4e8424 <_lit4_start+0x424> + 8e36be: 600012 j 8e36d4 <_HIFusb_isr_handler+0x58> + +008e36c1 <_HIFusb_isr_handler+0x45>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:511 + 8e36c1: 2822b3 l32i a8, a2, 0x2cc + 8e36c4: da40 mov.n a10, a4 + 8e36c6: 0b8000 callx8 a8 + 8e36c9: dba0 mov.n a11, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:512 + 8e36cb: 8831 l32i.n a8, a3, 4 + 8e36cd: 8c32 l32i.n a12, a3, 8 + 8e36cf: c0a0 movi.n a10, 0 + 8e36d1: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:553 + 8e36d4: 2822b7 l32i a8, a2, 0x2dc + 8e36d7: da40 mov.n a10, a4 + 8e36d9: 0b8000 callx8 a8 + 8e36dc: 65afe1 bnez a10, 8e36c1 <_HIFusb_isr_handler+0x45> + 8e36df: 160107 l32r a6, 4e841c <_lit4_start+0x41c> + +008e36e2 <_HIFusb_isr_handler+0x66>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:555 + 8e36e2: 246cf8 addi a4, a6, -8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:570 + 8e36e5: 2822b7 l32i a8, a2, 0x2dc + 8e36e8: da60 mov.n a10, a6 + 8e36ea: 0b8000 callx8 a8 + 8e36ed: c9a2 beqz.n a10, 8e3703 <_HIFusb_isr_handler+0x87> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:439 + 8e36ef: 2822b5 l32i a8, a2, 0x2d4 + 8e36f2: da60 mov.n a10, a6 + 8e36f4: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:440 + 8e36f7: 8830 l32i.n a8, a3, 0 + 8e36f9: 8b32 l32i.n a11, a3, 8 + 8e36fb: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:572 + 8e36fe: c051 movi.n a5, 1 + 8e3700: 600001 j 8e3705 <_HIFusb_isr_handler+0x89> + +008e3703 <_HIFusb_isr_handler+0x87>: + 8e3703: c050 movi.n a5, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:577 + 8e3705: 2822b7 l32i a8, a2, 0x2dc + 8e3708: da40 mov.n a10, a4 + 8e370a: 0b8000 callx8 a8 + 8e370d: c9a3 beqz.n a10, 8e3724 <_HIFusb_isr_handler+0xa8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:466 + 8e370f: 2822b3 l32i a8, a2, 0x2cc + 8e3712: da40 mov.n a10, a4 + 8e3714: 0b8000 callx8 a8 + 8e3717: dba0 mov.n a11, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:467 + 8e3719: 8831 l32i.n a8, a3, 4 + 8e371b: 8c32 l32i.n a12, a3, 8 + 8e371d: c0a0 movi.n a10, 0 + 8e371f: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:579 + 8e3722: c051 movi.n a5, 1 + +008e3724 <_HIFusb_isr_handler+0xa8>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:583 + 8e3724: 655fbd bnez a5, 8e36e5 <_HIFusb_isr_handler+0x69> + +008e3727 <_HIFusb_isr_handler+0xab>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:590 + 8e3727: d10f retw.n + +008e3729 <_HIFusb_isr_handler+0xad>: + 8e3729: 000000 ... + +008e372c <_HIFusb_get_default_pipe>: +_HIFusb_get_default_pipe(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:593 + 8e372c: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:595 + 8e372f: c023 movi.n a2, 3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:594 + 8e3731: c084 movi.n a8, 4 + 8e3733: 283400 s8i a8, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:595 + 8e3736: 224400 s8i a2, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:596 + 8e3739: d10f retw.n + +008e373b <_HIFusb_get_default_pipe+0xf>: + ... + +008e373c : +hif_usb_module_install(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:601 + 8e373c: 6c1004 entry a1, 32 + 8e373f: 190112 l32r a9, 4e8448 <_lit4_start+0x448> + 8e3742: 130114 l32r a3, 4e8450 <_lit4_start+0x450> + 8e3745: 1a011a l32r a10, 4e8468 <_lit4_start+0x468> + 8e3748: 1b0119 l32r a11, 4e8464 <_lit4_start+0x464> + 8e374b: 1c0118 l32r a12, 4e8460 <_lit4_start+0x460> + 8e374e: 1d0117 l32r a13, 4e845c <_lit4_start+0x45c> + 8e3751: 1e0116 l32r a14, 4e8458 <_lit4_start+0x458> + 8e3754: 1f0115 l32r a15, 4e8454 <_lit4_start+0x454> + 8e3757: 180113 l32r a8, 4e844c <_lit4_start+0x44c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:604 + 8e375a: 9824 s32i.n a8, a2, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:611 + 8e375c: 9a22 s32i.n a10, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:610 + 8e375e: 9b29 s32i.n a11, a2, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:609 + 8e3760: 9c28 s32i.n a12, a2, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:608 + 8e3762: 9d27 s32i.n a13, a2, 28 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:607 + 8e3764: 9e26 s32i.n a14, a2, 24 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:606 + 8e3766: 9f2b s32i.n a15, a2, 44 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:603 + 8e3768: 9920 s32i.n a9, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:605 + 8e376a: 9325 s32i.n a3, a2, 20 + 8e376c: 18011c l32r a8, 4e8470 <_lit4_start+0x470> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:613 + 8e376f: 982a s32i.n a8, a2, 40 + 8e3771: 13011d l32r a3, 4e8474 <_lit4_start+0x474> + 8e3774: 19011b l32r a9, 4e846c <_lit4_start+0x46c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:612 + 8e3777: 9921 s32i.n a9, a2, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:614 + 8e3779: 932c s32i.n a3, a2, 48 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:618 + 8e377b: d10f retw.n + +008e377d : + 8e377d: 000000 ... + +008e3780 : +HIFusb_DescTraceDump(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:621 + 8e3780: 6c1004 entry a1, 32 + 8e3783: 120018 l32r a2, 4e8060 <_lit4_start+0x60> + 8e3786: 130101 l32r a3, 4e8404 <_lit4_start+0x404> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:623 + 8e3789: 282212 l32i a8, a2, 72 + 8e378c: 1a011e l32r a10, 4e8478 <_lit4_start+0x478> + 8e378f: 8b39 l32i.n a11, a3, 36 + 8e3791: 0b8000 callx8 a8 + 8e3794: 1a011f l32r a10, 4e847c <_lit4_start+0x47c> + 8e3797: 15010d l32r a5, 4e8434 <_lit4_start+0x434> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:624 + 8e379a: 0c0200 memw + 8e379d: 282212 l32i a8, a2, 72 + 8e37a0: 2b52c6 l32i a11, a5, 0x318 + 8e37a3: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:626 + 8e37a6: 2822b8 l32i a8, a2, 0x2e0 + 8e37a9: 1a0108 l32r a10, 4e8420 <_lit4_start+0x420> + 8e37ac: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:630 + 8e37af: 282212 l32i a8, a2, 72 + 8e37b2: 1a0120 l32r a10, 4e8480 <_lit4_start+0x480> + 8e37b5: 8b3b l32i.n a11, a3, 44 + 8e37b7: 0b8000 callx8 a8 + 8e37ba: 1a011f l32r a10, 4e847c <_lit4_start+0x47c> + 8e37bd: 14010c l32r a4, 4e8430 <_lit4_start+0x430> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:631 + 8e37c0: 0c0200 memw + 8e37c3: 282212 l32i a8, a2, 72 + 8e37c6: 8b46 l32i.n a11, a4, 24 + 8e37c8: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:633 + 8e37cb: 2822b8 l32i a8, a2, 0x2e0 + 8e37ce: 1a0109 l32r a10, 4e8424 <_lit4_start+0x424> + 8e37d1: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:636 + 8e37d4: 282212 l32i a8, a2, 72 + 8e37d7: 1a0121 l32r a10, 4e8484 <_lit4_start+0x484> + 8e37da: 8b33 l32i.n a11, a3, 12 + 8e37dc: 0b8000 callx8 a8 + 8e37df: 1a011f l32r a10, 4e847c <_lit4_start+0x47c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:637 + 8e37e2: 0c0200 memw + 8e37e5: 282212 l32i a8, a2, 72 + 8e37e8: 2b5286 l32i a11, a5, 0x218 + 8e37eb: 0b8000 callx8 a8 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<_lit4_start+0x41c> + 8e3817: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/HIF_usb.c:643 + 8e381a: d10f retw.n + +008e381c : +vUsb_ep0tx(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:319 + 8e381c: 6c1004 entry a1, 32 + 8e381f: 120123 l32r a2, 4e848c <_lit4_start+0x48c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:331 + 8e3822: 882c l32i.n a8, a2, 48 + 8e3824: 1a0124 l32r a10, 4e8490 <_lit4_start+0x490> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:328 + 8e3827: c490 movi.n a9, 64 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:331 + 8e3829: 688108 beqi a8, 1, 8e3835 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minu a9, a9, a11 + 8e3a63: 29a512 s16i a9, a10, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:700 + 8e3a66: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:701 + 8e3a69: c021 movi.n a2, 1 + 8e3a6b: d10f retw.n + +008e3a6d : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:643 + 8e3a6d: 0b0947 extui a9, a11, 0, 8 + 8e3a70: cb93 beqz.n a9, 8e3aa7 + +008e3a72 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:693 + 8e3a72: c020 movi.n a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:701 + 8e3a74: d10f retw.n + +008e3a76 : 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a1, 32 + 8e3d27: 190123 l32r a9, 4e848c <_lit4_start+0x48c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1005 + 8e3d2a: c031 movi.n a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1002 + 8e3d2c: c460 movi.n a6, 64 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1005 + 8e3d2e: 259112 l16ui a5, a9, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1010 + 8e3d31: d760 mov.n a7, a6 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1015 + 8e3d33: 8498 l32i.n a4, a9, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1005 + 8e3d35: 050847 extui a8, a5, 0, 8 + 8e3d38: 6e5d01 bltui a5, 64, 8e3d3d + 8e3d3b: c030 movi.n a3, 0 + +008e3d3d : + 8e3d3d: 038639 movnez a6, a8, a3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1010 + 8e3d40: 038739 movnez a7, a8, a3 + 8e3d43: 07550c sub a5, a5, a7 + 8e3d46: 05054f extui a5, a5, 0, 16 + 8e3d49: 259512 s16i a5, a9, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1017 + 8e3d4c: b367 addi.n a7, a6, 3 + 8e3d4e: 072712 srai a7, a7, 2 + 8e3d51: 6a7138 blti a7, 1, 8e3d8d + 8e3d54: 160125 l32r a6, 4e8494 <_lit4_start+0x494> + 8e3d57: c030 movi.n a3, 0 + 8e3d59: 6d7a28 loopgtz a7, 8e3d85 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1021 + 8e3d5c: 0c0200 memw + 8e3d5f: 2b6283 l32i a11, a6, 0x20c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1033 + 8e3d62: b133 addi.n a3, a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1026 + 8e3d64: 2b4400 s8i a11, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1027 + 8e3d67: 0b8814 srli a8, a11, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1028 + 8e3d6a: 0b075f extui a7, a11, 16, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1029 + 8e3d6d: 0b8557 extui a5, a11, 24, 8 + 8e3d70: 254403 s8i a5, a4, 3 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1028 + 8e3d73: 274402 s8i a7, a4, 2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1027 + 8e3d76: 284401 s8i a8, a4, 1 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1054 + 8e3da0: 6c1004 entry a1, 32 + 8e3da3: 180003 l32r a8, 4e800c <_lit4_start+0xc> + 8e3da6: 120123 l32r a2, 4e848c <_lit4_start+0x48c> + 8e3da9: 190030 l32r a9, 4e80c0 <_lit4_start+0xc0> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1061 + 8e3dac: 8880 l32i.n a8, a8, 0 + 8e3dae: 1d012e l32r a13, 4e84b8 <_lit4_start+0x4b8> + 8e3db1: 1e012d l32r a14, 4e84b4 <_lit4_start+0x4b4> + 8e3db4: 79892b bne a8, a9, 8e3de3 + 8e3db7: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1063 + 8e3dba: 288212 l32i a8, a8, 72 + 8e3dbd: 1a012b l32r a10, 4e84ac <_lit4_start+0x4ac> + 8e3dc0: 0b8000 callx8 a8 + 8e3dc3: 1c0032 l32r a12, 4e80c8 <_lit4_start+0xc8> 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a2, 68 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1069 + 8e3dde: 292614 s32i a9, a2, 80 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1085 + 8e3de1: d10f retw.n + +008e3de3 : + 8e3de3: 19012f l32r a9, 4e84bc <_lit4_start+0x4bc> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1077 + 8e3de6: 2d2613 s32i a13, a2, 76 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1076 + 8e3de9: 2e2612 s32i a14, a2, 72 + 8e3dec: 18009b l32r a8, 4e826c <_lit4_start+0x26c> + 8e3def: 1f012c l32r a15, 4e84b0 <_lit4_start+0x4b0> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1075 + 8e3df2: 2f2611 s32i a15, a2, 68 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8e3ef4: 29a6c2 s32i a9, a10, 0x308 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1100 + 8e3ef7: d10f retw.n + +008e3ef9 : + 8e3ef9: 000000 ... + +008e3efc : +VendorCommand(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1239 + 8e3efc: 6c1004 entry a1, 32 + 8e3eff: 190130 l32r a9, 4e84c0 <_lit4_start+0x4c0> + 8e3f02: 160015 l32r a6, 4e8054 <_lit4_start+0x54> + 8e3f05: 120123 l32r a2, 4e848c <_lit4_start+0x48c> + 8e3f08: 130018 l32r a3, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1248 + 8e3f0b: 0c0200 memw +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1306 + 8e3f0e: 2a2102 l16ui a10, a2, 4 + 8e3f11: c380 movi.n a8, 48 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s32i a13, a5, 0x300 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1283 + 8e3fa2: 0c0200 memw + 8e3fa5: 2c5683 s32i a12, a5, 0x20c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1284 + 8e3fa8: 0c0200 memw + 8e3fab: 2e56c0 s32i a14, a5, 0x300 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1285 + 8e3fae: 0c0200 memw + 8e3fb1: 2d4488 s8i a13, a4, 136 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1287 + 8e3fb4: 283212 l32i a8, a3, 72 + 8e3fb7: 1a0135 l32r a10, 4e84d4 <_lit4_start+0x4d4> + 8e3fba: 0b8000 callx8 a8 + 8e3fbd: 1d0136 l32r a13, 4e84d8 <_lit4_start+0x4d8> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:1289 + 8e3fc0: 0c0200 memw + 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<_lit4_start+0x510> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2256 + 8e4715: 9321 s32i.n a3, a2, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2255 + 8e4717: 9820 s32i.n a8, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2257 + 8e4719: d10f retw.n + +008e471b : + ... + +008e471c : +cmnos_usb_module_install(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2261 + 8e471c: 6c1004 entry a1, 32 + 8e471f: 19014c l32r a9, 4e8530 <_lit4_start+0x530> + 8e4722: 1a014b l32r a10, 4e852c <_lit4_start+0x52c> + 8e4725: 1b014a l32r a11, 4e8528 <_lit4_start+0x528> + 8e4728: 1c0149 l32r a12, 4e8524 <_lit4_start+0x524> + 8e472b: 1d0148 l32r a13, 4e8520 <_lit4_start+0x520> + 8e472e: 1e0147 l32r a14, 4e851c <_lit4_start+0x51c> + 8e4731: 1f0146 l32r a15, 4e8518 <_lit4_start+0x518> + 8e4734: 130145 l32r a3, 4e8514 <_lit4_start+0x514> + 8e4737: 18014d l32r a8, 4e8534 <_lit4_start+0x534> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2272 + 8e473a: 982a s32i.n a8, a2, 40 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2271 + 8e473c: 9929 s32i.n a9, a2, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2269 + 8e473e: 2a261a s32i a10, a2, 104 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2268 + 8e4741: 2b2619 s32i a11, a2, 100 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2267 + 8e4744: 9c24 s32i.n a12, a2, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2265 + 8e4746: 9d23 s32i.n a13, a2, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2264 + 8e4748: 9e22 s32i.n a14, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2262 + 8e474a: 9320 s32i.n a3, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2263 + 8e474c: 9f21 s32i.n a15, a2, 4 + 8e474e: 180155 l32r a8, 4e8554 <_lit4_start+0x554> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2285 + 8e4751: 282614 s32i a8, a2, 80 + 8e4754: 1f014f l32r a15, 4e853c <_lit4_start+0x53c> + 8e4757: 13014e l32r a3, 4e8538 <_lit4_start+0x538> + 8e475a: 1e0150 l32r a14, 4e8540 <_lit4_start+0x540> + 8e475d: 1d0130 l32r a13, 4e84c0 <_lit4_start+0x4c0> + 8e4760: 1c0151 l32r a12, 4e8544 <_lit4_start+0x544> + 8e4763: 1b0152 l32r a11, 4e8548 <_lit4_start+0x548> + 8e4766: 1a0153 l32r a10, 4e854c <_lit4_start+0x54c> + 8e4769: 190154 l32r a9, 4e8550 <_lit4_start+0x550> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2283 + 8e476c: 292610 s32i a9, a2, 64 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2282 + 8e476f: 9a2f s32i.n a10, a2, 60 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2281 + 8e4771: 9b2d s32i.n a11, a2, 52 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2280 + 8e4773: 9c2e s32i.n a12, a2, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2278 + 8e4775: 9d2c s32i.n a13, a2, 48 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2277 + 8e4777: 9e2b s32i.n a14, a2, 44 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2274 + 8e4779: 9327 s32i.n a3, a2, 28 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2275 + 8e477b: 9f28 s32i.n a15, a2, 32 + 8e477d: 18015e l32r a8, 4e8578 <_lit4_start+0x578> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2297 + 8e4780: 9826 s32i.n a8, a2, 24 + 8e4782: 1f0157 l32r a15, 4e855c <_lit4_start+0x55c> + 8e4785: 130156 l32r a3, 4e8558 <_lit4_start+0x558> + 8e4788: 1e0158 l32r a14, 4e8560 <_lit4_start+0x560> + 8e478b: 1d0159 l32r a13, 4e8564 <_lit4_start+0x564> + 8e478e: 1c015a l32r a12, 4e8568 <_lit4_start+0x568> + 8e4791: 1b015b l32r a11, 4e856c <_lit4_start+0x56c> + 8e4794: 1a015c l32r a10, 4e8570 <_lit4_start+0x570> + 8e4797: 19015d l32r a9, 4e8574 <_lit4_start+0x574> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2296 + 8e479a: 9925 s32i.n a9, a2, 20 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2294 + 8e479c: 2a2618 s32i a10, a2, 96 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2293 + 8e479f: 2b2617 s32i a11, a2, 92 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2291 + 8e47a2: 2c2616 s32i a12, a2, 88 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2290 + 8e47a5: 2d2615 s32i a13, a2, 84 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2288 + 8e47a8: 2e2611 s32i a14, a2, 68 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2286 + 8e47ab: 232613 s32i a3, a2, 76 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2287 + 8e47ae: 2f2612 s32i a15, a2, 72 + 8e47b1: 13015f l32r a3, 4e857c <_lit4_start+0x57c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2299 + 8e47b4: 23261b s32i a3, a2, 108 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_api.c:2300 + 8e47b7: d10f retw.n + +008e47b9 : + 8e47b9: 000000 ... + +008e47bc : +mUsbEPMap(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:20 + 8e47bc: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:26 + 8e47bf: c053 movi.n a5, 3 + 8e47c1: 242c2f addi a4, a2, 47 + 8e47c4: 054403 xor a4, a4, a5 + 8e47c7: 150050 l32r a5, 4e8140 <_lit4_start+0x140> + 8e47ca: 040447 extui a4, a4, 0, 8 + 8e47cd: 054402 or a4, a4, a5 + 8e47d0: 0c0200 memw + 8e47d3: 234400 s8i a3, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:33 + 8e47d6: d10f retw.n + +008e47d8 : +mUsbFIFOMap(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:36 + 8e47d8: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:45 + 8e47db: c053 movi.n a5, 3 + 8e47dd: 240a80 movi a4, 128 + 8e47e0: a424 add.n a4, a2, a4 + 8e47e2: 054403 xor a4, a4, a5 + 8e47e5: 150050 l32r a5, 4e8140 <_lit4_start+0x140> + 8e47e8: 040447 extui a4, a4, 0, 8 + 8e47eb: 054402 or a4, a4, a5 + 8e47ee: 0c0200 memw + 8e47f1: 234400 s8i a3, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:51 + 8e47f4: d10f retw.n + +008e47f6 : + ... + +008e47f8 : +mUsbFIFOConfig(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:54 + 8e47f8: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:60 + 8e47fb: c053 movi.n a5, 3 + 8e47fd: 240a90 movi a4, 144 + 8e4800: a424 add.n a4, a2, a4 + 8e4802: 054403 xor a4, a4, a5 + 8e4805: 150050 l32r a5, 4e8140 <_lit4_start+0x140> + 8e4808: 040447 extui a4, a4, 0, 8 + 8e480b: 054402 or a4, a4, a5 + 8e480e: 0c0200 memw + 8e4811: 234400 s8i a3, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:66 + 8e4814: d10f retw.n + +008e4816 : + ... + +008e4818 : +mUsbEPMxPtSzHigh(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:69 + 8e4818: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:75 + 8e481b: 0f2711 slli a7, a2, 1 + 8e481e: 0b3611 slli a6, a3, 5 + 8e4821: 048514 srli a5, a4, 8 + 8e4824: a766 add.n a6, a6, a7 + 8e4826: c073 movi.n a7, 3 + 8e4828: 266c3f addi a6, a6, 63 + 8e482b: 076603 xor a6, a6, a7 + 8e482e: 170050 l32r a7, 4e8140 <_lit4_start+0x140> + 8e4831: 060647 extui a6, a6, 0, 8 + 8e4834: 076602 or a6, a6, a7 + 8e4837: 0c0200 memw + 8e483a: 256400 s8i a5, a6, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:79 + 8e483d: d10f retw.n + +008e483f : + ... + +008e4840 : +mUsbEPMxPtSzLow(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:82 + 8e4840: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:88 + 8e4843: 0f2611 slli a6, a2, 1 + 8e4846: 0b3511 slli a5, a3, 5 + 8e4849: a655 add.n a5, a5, a6 + 8e484b: c063 movi.n a6, 3 + 8e484d: 255c3e addi a5, a5, 62 + 8e4850: 065503 xor a5, a5, a6 + 8e4853: 160050 l32r a6, 4e8140 <_lit4_start+0x140> + 8e4856: 050547 extui a5, a5, 0, 8 + 8e4859: 065502 or a5, a5, a6 + 8e485c: 0c0200 memw + 8e485f: 245400 s8i a4, a5, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:91 + 8e4862: d10f retw.n + +008e4864 : +mUsbEPinHighBandSet(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:94 + 8e4864: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:106 + 8e4867: 2a0a9f movi a10, 159 + 8e486a: c073 movi.n a7, 3 + 8e486c: 0f2611 slli a6, a2, 1 + 8e486f: 266c3f addi a6, a6, 63 + 8e4872: 076603 xor a6, a6, a7 + 8e4875: 170050 l32r a7, 4e8140 <_lit4_start+0x140> + 8e4878: 060647 extui a6, a6, 0, 8 + 8e487b: 076602 or a6, a6, a7 + 8e487e: 0c0200 memw + 8e4881: 296000 l8ui a9, a6, 0 + 8e4884: 0a9901 and a9, a9, a10 + 8e4887: 0c0200 memw + 8e488a: 296400 s8i a9, a6, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:107 + 8e488d: c081 movi.n a8, 1 + 8e488f: 04b714 srli a7, a4, 11 + 8e4892: b177 addi.n a7, a7, 1 + 8e4894: 03880c sub a8, a8, a3 + 8e4897: 0b7711 slli a7, a7, 5 + 8e489a: 08771d mul16s a7, a7, a8 + 8e489d: 0c0200 memw + 8e48a0: 256000 l8ui a5, a6, 0 + 8e48a3: 075502 or a5, a5, a7 + 8e48a6: 0c0200 memw + 8e48a9: 256400 s8i a5, a6, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:111 + 8e48ac: d10f retw.n + +008e48ae : + ... + +008e48b0 : +vUsbFIFO_EPxCfg_HS(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:143 + 8e48b0: 6c1004 entry a1, 32 + 8e48b3: 180160 l32r a8, 4e8580 <_lit4_start+0x580> + 8e48b6: 190161 l32r a9, 4e8584 <_lit4_start+0x584> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:302 + 8e48b9: 288100 l16ui a8, a8, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:297 + 8e48bc: 299100 l16ui a9, a9, 0 + 8e48bf: b088 addi.n a8, a8, -1 + 8e48c1: 658179 bnez a8, 8e4a3e + 8e48c4: 659176 bnez a9, 8e4a3e + 8e48c7: 1a0162 l32r a10, 4e8588 <_lit4_start+0x588> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:292 + 8e48ca: 2aa100 l16ui a10, a10, 0 + 8e48cd: 65a16d bnez a10, 8e4a3e +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:164 + 8e48d0: c0a1 movi.n a10, 1 + 8e48d2: c0bf movi.n a11, 15 + 8e48d4: 5bffb9 call8 8e47bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:165 + 8e48d7: c0a0 movi.n a10, 0 + 8e48d9: c0b1 movi.n a11, 1 + 8e48db: 5bffbf call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:167 + 8e48de: c0a1 movi.n a10, 1 + 8e48e0: c0b1 movi.n a11, 1 + 8e48e2: 5bffbd call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:169 + 8e48e5: c0a0 movi.n a10, 0 + 8e48e7: 2b0a86 movi a11, 134 + 8e48ea: 5bffc3 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:175 + 8e48ed: c0a1 movi.n a10, 1 + 8e48ef: c0b6 movi.n a11, 6 + 8e48f1: 5bffc1 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:178 + 8e48f4: c0a1 movi.n a10, 1 + 8e48f6: c0b1 movi.n a11, 1 + 8e48f8: 2c2a00 movi a12, 0x200 + 8e48fb: 5bffc7 call8 8e4818 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:179 + 8e48fe: c0a1 movi.n a10, 1 + 8e4900: c0b1 movi.n a11, 1 + 8e4902: 2c2a00 movi a12, 0x200 + 8e4905: 5bffce call8 8e4840 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:180 + 8e4908: c0a1 movi.n a10, 1 + 8e490a: c0b1 movi.n a11, 1 + 8e490c: 2c2a00 movi a12, 0x200 + 8e490f: 5bffd5 call8 8e4864 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:185 + 8e4912: c0a2 movi.n a10, 2 + 8e4914: 2b0af2 movi a11, 242 + 8e4917: 5bffa9 call8 8e47bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:186 + 8e491a: c0a2 movi.n a10, 2 + 8e491c: c1b2 movi.n a11, 18 + 8e491e: 5bffae call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:188 + 8e4921: c0a3 movi.n a10, 3 + 8e4923: c1b2 movi.n a11, 18 + 8e4925: 5bffac call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:190 + 8e4928: c0a2 movi.n a10, 2 + 8e492a: 2b0a86 movi a11, 134 + 8e492d: 5bffb2 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:196 + 8e4930: c0a3 movi.n a10, 3 + 8e4932: c0b6 movi.n a11, 6 + 8e4934: 5bffb0 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:199 + 8e4937: c0a2 movi.n a10, 2 + 8e4939: c0b0 movi.n a11, 0 + 8e493b: 2c2a00 movi a12, 0x200 + 8e493e: 5bffb6 call8 8e4818 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:200 + 8e4941: c0a2 movi.n a10, 2 + 8e4943: c0b0 movi.n a11, 0 + 8e4945: 2c2a00 movi a12, 0x200 + 8e4948: 5bffbd call8 8e4840 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:201 + 8e494b: c0a2 movi.n a10, 2 + 8e494d: c0b0 movi.n a11, 0 + 8e494f: 2c2a00 movi a12, 0x200 + 8e4952: 5bffc4 call8 8e4864 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:206 + 8e4955: c0a3 movi.n a10, 3 + 8e4957: 2b0afe movi a11, 254 + 8e495a: 5bff98 call8 8e47bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:207 + 8e495d: c0ae movi.n a10, 14 + 8e495f: c1b3 movi.n a11, 19 + 8e4961: 5bff9d call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:208 + 8e4964: c0ae movi.n a10, 14 + 8e4966: 2b0a83 movi a11, 131 + 8e4969: 5bffa3 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:217 + 8e496c: c0a3 movi.n a10, 3 + 8e496e: c0b0 movi.n a11, 0 + 8e4970: c4c0 movi.n a12, 64 + 8e4972: 5bffa9 call8 8e4818 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:218 + 8e4975: c0a3 movi.n a10, 3 + 8e4977: c0b0 movi.n a11, 0 + 8e4979: c4c0 movi.n a12, 64 + 8e497b: 5bffb1 call8 8e4840 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:219 + 8e497e: c0a3 movi.n a10, 3 + 8e4980: c0b0 movi.n a11, 0 + 8e4982: c4c0 movi.n a12, 64 + 8e4984: 5bffb7 call8 8e4864 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:224 + 8e4987: c0a4 movi.n a10, 4 + 8e4989: 2b0aff movi a11, 255 + 8e498c: 5bff8b call8 8e47bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:225 + 8e498f: c0af movi.n a10, 15 + 8e4991: c0b4 movi.n a11, 4 + 8e4993: 5bff91 call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:226 + 8e4996: c0af movi.n a10, 15 + 8e4998: 2b0a83 movi a11, 131 + 8e499b: 5bff97 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:235 + 8e499e: c0a4 movi.n a10, 4 + 8e49a0: c0b1 movi.n a11, 1 + 8e49a2: c4c0 movi.n a12, 64 + 8e49a4: 5bff9c call8 8e4818 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:236 + 8e49a7: c0a4 movi.n a10, 4 + 8e49a9: c0b1 movi.n a11, 1 + 8e49ab: c4c0 movi.n a12, 64 + 8e49ad: 5bffa4 call8 8e4840 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:237 + 8e49b0: c0a4 movi.n a10, 4 + 8e49b2: c0b1 movi.n a11, 1 + 8e49b4: c4c0 movi.n a12, 64 + 8e49b6: 5bffab call8 8e4864 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:244 + 8e49b9: c0a5 movi.n a10, 5 + 8e49bb: c4bf movi.n a11, 79 + 8e49bd: 5bff7f call8 8e47bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:245 + 8e49c0: c0a4 movi.n a10, 4 + 8e49c2: c0b5 movi.n a11, 5 + 8e49c4: 5bff84 call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:247 + 8e49c7: c0a5 movi.n a10, 5 + 8e49c9: c0b5 movi.n a11, 5 + 8e49cb: 5bff83 call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:249 + 8e49ce: c0a4 movi.n a10, 4 + 8e49d0: 2b0a86 movi a11, 134 + 8e49d3: 5bff89 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:255 + 8e49d6: c0a5 movi.n a10, 5 + 8e49d8: c0b6 movi.n a11, 6 + 8e49da: 5bff87 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:258 + 8e49dd: c0a5 movi.n a10, 5 + 8e49df: c0b1 movi.n a11, 1 + 8e49e1: 2c2a00 movi a12, 0x200 + 8e49e4: 5bff8c call8 8e4818 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:259 + 8e49e7: c0a5 movi.n a10, 5 + 8e49e9: c0b1 movi.n a11, 1 + 8e49eb: 2c2a00 movi a12, 0x200 + 8e49ee: 5bff94 call8 8e4840 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:260 + 8e49f1: c0a5 movi.n a10, 5 + 8e49f3: c0b1 movi.n a11, 1 + 8e49f5: 2c2a00 movi a12, 0x200 + 8e49f8: 5bff9a call8 8e4864 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:268 + 8e49fb: c0a6 movi.n a10, 6 + 8e49fd: 2b0a6f movi a11, 111 + 8e4a00: 5bff6e call8 8e47bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:269 + 8e4a03: c0a6 movi.n a10, 6 + 8e4a05: c0b6 movi.n a11, 6 + 8e4a07: 5bff74 call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:271 + 8e4a0a: c0a7 movi.n a10, 7 + 8e4a0c: c0b6 movi.n a11, 6 + 8e4a0e: 5bff72 call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:273 + 8e4a11: c0a6 movi.n a10, 6 + 8e4a13: 2b0a86 movi a11, 134 + 8e4a16: 5bff78 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:279 + 8e4a19: c0a7 movi.n a10, 7 + 8e4a1b: c0b6 movi.n a11, 6 + 8e4a1d: 5bff76 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:282 + 8e4a20: c0a6 movi.n a10, 6 + 8e4a22: c0b1 movi.n a11, 1 + 8e4a24: 2c2a00 movi a12, 0x200 + 8e4a27: 5bff7c call8 8e4818 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:283 + 8e4a2a: c0a6 movi.n a10, 6 + 8e4a2c: c0b1 movi.n a11, 1 + 8e4a2e: 2c2a00 movi a12, 0x200 + 8e4a31: 5bff83 call8 8e4840 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:284 + 8e4a34: c0a6 movi.n a10, 6 + 8e4a36: c0b1 movi.n a11, 1 + 8e4a38: 2c2a00 movi a12, 0x200 + 8e4a3b: 5bff8a call8 8e4864 + +008e4a3e : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:305 + 8e4a3e: d10f retw.n + +008e4a40 : +vUsbFIFO_EPxCfg_FS(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:308 + 8e4a40: 6c1004 entry a1, 32 + 8e4a43: 180160 l32r a8, 4e8580 <_lit4_start+0x580> + 8e4a46: 190161 l32r a9, 4e8584 <_lit4_start+0x584> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:431 + 8e4a49: 288100 l16ui a8, a8, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:426 + 8e4a4c: 299100 l16ui a9, a9, 0 + 8e4a4f: b088 addi.n a8, a8, -1 + 8e4a51: 658118 bnez a8, 8e4b6d + 8e4a54: 659115 bnez a9, 8e4b6d + 8e4a57: 1a0162 l32r a10, 4e8588 <_lit4_start+0x588> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:421 + 8e4a5a: 2aa100 l16ui a10, a10, 0 + 8e4a5d: 65a10c bnez a10, 8e4b6d +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:329 + 8e4a60: c0a1 movi.n a10, 1 + 8e4a62: c0bf movi.n a11, 15 + 8e4a64: 5bff55 call8 8e47bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:330 + 8e4a67: c0a0 movi.n a10, 0 + 8e4a69: c0b1 movi.n a11, 1 + 8e4a6b: 5bff5b call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:331 + 8e4a6e: c0a0 movi.n a10, 0 + 8e4a70: 2b0a86 movi a11, 134 + 8e4a73: 5bff61 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:337 + 8e4a76: c0a1 movi.n a10, 1 + 8e4a78: c0b6 movi.n a11, 6 + 8e4a7a: 5bff5f call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:340 + 8e4a7d: c0a1 movi.n a10, 1 + 8e4a7f: c0b1 movi.n a11, 1 + 8e4a81: c4c0 movi.n a12, 64 + 8e4a83: 5bff65 call8 8e4818 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:341 + 8e4a86: c0a1 movi.n a10, 1 + 8e4a88: c0b1 movi.n a11, 1 + 8e4a8a: c4c0 movi.n a12, 64 + 8e4a8c: 5bff6c call8 8e4840 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:343 + 8e4a8f: c0a1 movi.n a10, 1 + 8e4a91: c0b1 movi.n a11, 1 + 8e4a93: c4c0 movi.n a12, 64 + 8e4a95: 5bff73 call8 8e4864 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:348 + 8e4a98: c0a2 movi.n a10, 2 + 8e4a9a: 2b0af2 movi a11, 242 + 8e4a9d: 5bff47 call8 8e47bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:349 + 8e4aa0: c0a2 movi.n a10, 2 + 8e4aa2: c1b2 movi.n a11, 18 + 8e4aa4: 5bff4c call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:350 + 8e4aa7: c0a2 movi.n a10, 2 + 8e4aa9: 2b0a86 movi a11, 134 + 8e4aac: 5bff52 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:356 + 8e4aaf: c0a3 movi.n a10, 3 + 8e4ab1: c0b6 movi.n a11, 6 + 8e4ab3: 5bff51 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:359 + 8e4ab6: c0a2 movi.n a10, 2 + 8e4ab8: c0b0 movi.n a11, 0 + 8e4aba: c4c0 movi.n a12, 64 + 8e4abc: 5bff56 call8 8e4818 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:360 + 8e4abf: c0a2 movi.n a10, 2 + 8e4ac1: c0b0 movi.n a11, 0 + 8e4ac3: c4c0 movi.n a12, 64 + 8e4ac5: 5bff5e call8 8e4840 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:361 + 8e4ac8: c0a2 movi.n a10, 2 + 8e4aca: c0b0 movi.n a11, 0 + 8e4acc: c4c0 movi.n a12, 64 + 8e4ace: 5bff65 call8 8e4864 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:366 + 8e4ad1: c0a3 movi.n a10, 3 + 8e4ad3: 2b0afe movi a11, 254 + 8e4ad6: 5bff39 call8 8e47bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:367 + 8e4ad9: c0ae movi.n a10, 14 + 8e4adb: c1b3 movi.n a11, 19 + 8e4add: 5bff3e call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:368 + 8e4ae0: c0ae movi.n a10, 14 + 8e4ae2: 2b0a83 movi a11, 131 + 8e4ae5: 5bff44 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:377 + 8e4ae8: c0a3 movi.n a10, 3 + 8e4aea: c0b0 movi.n a11, 0 + 8e4aec: c4c0 movi.n a12, 64 + 8e4aee: 5bff4a call8 8e4818 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:378 + 8e4af1: c0a3 movi.n a10, 3 + 8e4af3: c0b0 movi.n a11, 0 + 8e4af5: c4c0 movi.n a12, 64 + 8e4af7: 5bff52 call8 8e4840 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:379 + 8e4afa: c0a3 movi.n a10, 3 + 8e4afc: c0b0 movi.n a11, 0 + 8e4afe: c4c0 movi.n a12, 64 + 8e4b00: 5bff58 call8 8e4864 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:384 + 8e4b03: c0a4 movi.n a10, 4 + 8e4b05: 2b0aff movi a11, 255 + 8e4b08: 5bff2c call8 8e47bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:385 + 8e4b0b: c0af movi.n a10, 15 + 8e4b0d: c0b4 movi.n a11, 4 + 8e4b0f: 5bff32 call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:386 + 8e4b12: c0af movi.n a10, 15 + 8e4b14: 2b0a82 movi a11, 130 + 8e4b17: 5bff38 call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:395 + 8e4b1a: c0a4 movi.n a10, 4 + 8e4b1c: c0b1 movi.n a11, 1 + 8e4b1e: c4c0 movi.n a12, 64 + 8e4b20: 5bff3d call8 8e4818 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:396 + 8e4b23: c0a4 movi.n a10, 4 + 8e4b25: c0b1 movi.n a11, 1 + 8e4b27: c4c0 movi.n a12, 64 + 8e4b29: 5bff45 call8 8e4840 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:397 + 8e4b2c: c0a4 movi.n a10, 4 + 8e4b2e: c0b1 movi.n a11, 1 + 8e4b30: c4c0 movi.n a12, 64 + 8e4b32: 5bff4c call8 8e4864 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:402 + 8e4b35: c0a5 movi.n a10, 5 + 8e4b37: c4bf movi.n a11, 79 + 8e4b39: 5bff20 call8 8e47bc +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:403 + 8e4b3c: c0a4 movi.n a10, 4 + 8e4b3e: c0b5 movi.n a11, 5 + 8e4b40: 5bff25 call8 8e47d8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:404 + 8e4b43: c0a4 movi.n a10, 4 + 8e4b45: 2b0a86 movi a11, 134 + 8e4b48: 5bff2b call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:410 + 8e4b4b: c0a5 movi.n a10, 5 + 8e4b4d: c0b6 movi.n a11, 6 + 8e4b4f: 5bff2a call8 8e47f8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:413 + 8e4b52: c0a5 movi.n a10, 5 + 8e4b54: c0b1 movi.n a11, 1 + 8e4b56: c4c0 movi.n a12, 64 + 8e4b58: 5bff2f call8 8e4818 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:414 + 8e4b5b: c0a5 movi.n a10, 5 + 8e4b5d: c0b1 movi.n a11, 1 + 8e4b5f: c4c0 movi.n a12, 64 + 8e4b61: 5bff37 call8 8e4840 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:415 + 8e4b64: c0a5 movi.n a10, 5 + 8e4b66: c0b1 movi.n a11, 1 + 8e4b68: c4c0 movi.n a12, 64 + 8e4b6a: 5bff3e call8 8e4864 + +008e4b6d : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/usb/src/usb_fifo.c:433 + 8e4b6d: d10f retw.n + +008e4b6f : + ... + +008e4b70 <__dma_reg_read>: +__dma_reg_read(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:166 + 8e4b70: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:167 + 8e4b73: 0c0200 memw + 8e4b76: 8220 l32i.n a2, a2, 0 + 8e4b78: d10f retw.n + +008e4b7a <__dma_reg_read+0xa>: + ... + +008e4b7c <__dma_reg_write>: +__dma_reg_write(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:177 + 8e4b7c: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:178 + 8e4b7f: 0c0200 memw + 8e4b82: 9320 s32i.n a3, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:179 + 8e4b84: d10f retw.n + +008e4b86 <__dma_reg_write+0xa>: + ... + +008e4b88 <__dma_set_base>: +__dma_set_base(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:188 + 8e4b88: 6c1004 entry a1, 32 + 8e4b8b: 160163 l32r a6, 4e858c <_lit4_start+0x58c> + 8e4b8e: c839 beqz.n a3, 8e4b9b <__dma_set_base+0x13> + 8e4b90: 150164 l32r a5, 4e8590 <_lit4_start+0x590> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:201 + 8e4b93: 683107 beqi a3, 1, 8e4b9e <__dma_set_base+0x16> + 8e4b96: 683204 beqi a3, 2, 8e4b9e <__dma_set_base+0x16> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:202 + 8e4b99: d10f retw.n + +008e4b9b <__dma_set_base+0x13>: + 8e4b9b: 150165 l32r a5, 4e8594 <_lit4_start+0x594> + +008e4b9e <__dma_set_base+0x16>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:197 + 8e4b9e: 022409 addx2 a4, a2, a2 + 8e4ba1: 06440b addx8 a4, a4, a6 + 8e4ba4: 9540 s32i.n a5, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:202 + 8e4ba6: d10f retw.n + +008e4ba8 <__dma_lib_tx_init>: +__dma_lib_tx_init(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:213 + 8e4ba8: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:217 + 8e4bab: 282cfc addi a8, a2, -4 + 8e4bae: 6e8203 bltui a8, 2, 8e4bb5 <__dma_lib_tx_init+0xd> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:218 + 8e4bb1: c021 movi.n a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:232 + 8e4bb3: d10f retw.n + +008e4bb5 <__dma_lib_tx_init+0xd>: + 8e4bb5: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e4bb8: 190163 l32r a9, 4e858c <_lit4_start+0x58c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:220 + 8e4bbb: 022409 addx2 a4, a2, a2 + 8e4bbe: 2882af l32i a8, a8, 0x2bc + 8e4bc1: 09440b addx8 a4, a4, a9 + 8e4bc4: b84a addi.n a10, a4, 8 + 8e4bc6: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:222 + 8e4bc9: db30 mov.n a11, a3 + 8e4bcb: da20 mov.n a10, a2 + 8e4bcd: 5bffee call8 8e4b88 <__dma_set_base> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:224 + 8e4bd0: 8841 l32i.n a8, a4, 4 + 8e4bd2: 8240 l32i.n a2, a4, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:228 + 8e4bd4: 8b42 l32i.n a11, a4, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:224 + 8e4bd6: a822 add.n a2, a2, a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:228 + 8e4bd8: da20 mov.n a10, a2 + 8e4bda: 5bffe8 call8 8e4b7c <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:229 + 8e4bdd: bc2a addi.n a10, a2, 12 + 8e4bdf: c0b2 movi.n a11, 2 + 8e4be1: 5bffe6 call8 8e4b7c <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:230 + 8e4be4: 2a2c18 addi a10, a2, 24 + 8e4be7: c0b1 movi.n a11, 1 + 8e4be9: 5bffe4 call8 8e4b7c <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:232 + 8e4bec: c020 movi.n a2, 0 + 8e4bee: d10f retw.n + +008e4bf0 <__dma_lib_rx_config>: +__dma_lib_rx_config(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:238 + 8e4bf0: 6c1004 entry a1, 32 + 8e4bf3: dc40 mov.n a12, a4 + 8e4bf5: db30 mov.n a11, a3 + 8e4bf7: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e4bfa: 1a0163 l32r a10, 4e858c <_lit4_start+0x58c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:246 + 8e4bfd: 022909 addx2 a9, a2, a2 + 8e4c00: 2882b0 l32i a8, a8, 0x2c0 + 8e4c03: 0a920b addx8 a2, a9, a10 + 8e4c06: b82a addi.n a10, a2, 8 + 8e4c08: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:251 + 8e4c0b: c0c2 movi.n a12, 2 + 8e4c0d: c031 movi.n a3, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:249 + 8e4c0f: 8f21 l32i.n a15, a2, 4 + 8e4c11: 8d20 l32i.n a13, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:257 + 8e4c13: 8b22 l32i.n a11, a2, 8 + 8e4c15: 1e0165 l32r a14, 4e8594 <_lit4_start+0x594> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:249 + 8e4c18: afd2 add.n a2, a13, a15 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:257 + 8e4c1a: da20 mov.n a10, a2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:251 + 8e4c1c: 0edd0c sub a13, a13, a14 + 8e4c1f: 0dc338 moveqz a3, a12, a13 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:257 + 8e4c22: 5bffd6 call8 8e4b7c <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:258 + 8e4c25: db30 mov.n a11, a3 + 8e4c27: b82a addi.n a10, a2, 8 + 8e4c29: 5bffd4 call8 8e4b7c <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:259 + 8e4c2c: 2a2c1c addi a10, a2, 28 + 8e4c2f: c0b1 movi.n a11, 1 + 8e4c31: 5bffd2 call8 8e4b7c <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:260 + 8e4c34: b42a addi.n a10, a2, 4 + 8e4c36: c0b1 movi.n a11, 1 + 8e4c38: 5bffd0 call8 8e4b7c <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:261 + 8e4c3b: d10f retw.n + +008e4c3d <__dma_lib_rx_config+0x4d>: + 8e4c3d: 000000 ... + +008e4c40 <__dma_lib_rx_init>: +__dma_lib_rx_init(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:272 + 8e4c40: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:273 + 8e4c43: 6e2403 bltui a2, 4, 8e4c4a <__dma_lib_rx_init+0xa> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:274 + 8e4c46: c021 movi.n a2, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:284 + 8e4c48: d10f retw.n + +008e4c4a <__dma_lib_rx_init+0xa>: + 8e4c4a: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e4c4d: 1b0163 l32r a11, 4e858c <_lit4_start+0x58c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:280 + 8e4c50: 022a09 addx2 a10, a2, a2 + 8e4c53: 2882ae l32i a8, a8, 0x2b8 + 8e4c56: 0baa0b addx8 a10, a10, a11 + 8e4c59: b8aa addi.n a10, a10, 8 + 8e4c5b: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:282 + 8e4c5e: db30 mov.n a11, a3 + 8e4c60: da20 mov.n a10, a2 + 8e4c62: 5bffc9 call8 8e4b88 <__dma_set_base> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:284 + 8e4c65: c020 movi.n a2, 0 + 8e4c67: d10f retw.n + +008e4c69 <__dma_lib_rx_init+0x29>: + 8e4c69: 000000 ... + +008e4c6c <__dma_hard_xmit>: +__dma_hard_xmit(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:295 + 8e4c6c: 6c1004 entry a1, 32 + 8e4c6f: db30 mov.n a11, a3 + 8e4c71: 1c0163 l32r a12, 4e858c <_lit4_start+0x58c> + 8e4c74: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:298 + 8e4c77: 022a09 addx2 a10, a2, a2 + 8e4c7a: 0caa0b addx8 a10, a10, a12 + 8e4c7d: 8ca1 l32i.n a12, a10, 4 + 8e4c7f: 89a0 l32i.n a9, a10, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:300 + 8e4c81: 2882b1 l32i a8, a8, 0x2c4 + 8e4c84: b8aa addi.n a10, a10, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:298 + 8e4c86: ac92 add.n a2, a9, a12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:300 + 8e4c88: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:304 + 8e4c8b: b42a addi.n a10, a2, 4 + 8e4c8d: c0b1 movi.n a11, 1 + 8e4c8f: 5bffbb call8 8e4b7c <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:305 + 8e4c92: d10f retw.n + +008e4c94 <__dma_reap_xmitted>: +__dma_reap_xmitted(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:315 + 8e4c94: 6c1004 entry a1, 32 + 8e4c97: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e4c9a: 1b0163 l32r a11, 4e858c <_lit4_start+0x58c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:316 + 8e4c9d: 022a09 addx2 a10, a2, a2 + 8e4ca0: 2882b5 l32i a8, a8, 0x2d4 + 8e4ca3: 0baa0b addx8 a10, a10, a11 + 8e4ca6: b8aa addi.n a10, a10, 8 + 8e4ca8: 0b8000 callx8 a8 + 8e4cab: d2a0 mov.n a2, a10 + 8e4cad: d10f retw.n + +008e4caf <__dma_reap_xmitted+0x1b>: + ... + +008e4cb0 <__dma_flush_xmit>: +__dma_flush_xmit(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:326 + 8e4cb0: 6c1004 entry a1, 32 + 8e4cb3: 140163 l32r a4, 4e858c <_lit4_start+0x58c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:339 + 8e4cb6: c0b0 movi.n a11, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:330 + 8e4cb8: 022309 addx2 a3, a2, a2 + 8e4cbb: 04330b addx8 a3, a3, a4 + 8e4cbe: 8831 l32i.n a8, a3, 4 + 8e4cc0: 8430 l32i.n a4, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:332 + 8e4cc2: 8232 l32i.n a2, a3, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:333 + 8e4cc4: 8333 l32i.n a3, a3, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:330 + 8e4cc6: a844 add.n a4, a4, a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:339 + 8e4cc8: b44a addi.n a10, a4, 4 + 8e4cca: 5bffac call8 8e4b7c <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:340 + 8e4ccd: da40 mov.n a10, a4 + 8e4ccf: db30 mov.n a11, a3 + 8e4cd1: 5bffaa call8 8e4b7c <__dma_reg_write> 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a10, 0, 16 + 8e4d10: d10f retw.n + +008e4d12 <__dma_xmit_done+0x26>: + ... + +008e4d14 <__dma_reap_recv>: +__dma_reap_recv(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:375 + 8e4d14: 6c1004 entry a1, 32 + 8e4d17: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e4d1a: 1b0163 l32r a11, 4e858c <_lit4_start+0x58c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:376 + 8e4d1d: 022a09 addx2 a10, a2, a2 + 8e4d20: 2882b3 l32i a8, a8, 0x2cc + 8e4d23: 0baa0b addx8 a10, a10, a11 + 8e4d26: b8aa addi.n a10, a10, 8 + 8e4d28: 0b8000 callx8 a8 + 8e4d2b: d2a0 mov.n a2, a10 + 8e4d2d: d10f retw.n + +008e4d2f <__dma_reap_recv+0x1b>: + ... + +008e4d30 <__dma_return_recv>: +__dma_return_recv(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:387 + 8e4d30: 6c1004 entry a1, 32 + 8e4d33: db30 mov.n a11, a3 + 8e4d35: 1c0163 l32r a12, 4e858c <_lit4_start+0x58c> + 8e4d38: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:390 + 8e4d3b: 022a09 addx2 a10, a2, a2 + 8e4d3e: 0caa0b addx8 a10, a10, a12 + 8e4d41: 8ca1 l32i.n a12, a10, 4 + 8e4d43: 89a0 l32i.n a9, a10, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:392 + 8e4d45: 2882b4 l32i a8, a8, 0x2d0 + 8e4d48: b8aa addi.n a10, a10, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:390 + 8e4d4a: ac92 add.n a2, a9, a12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:392 + 8e4d4c: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:394 + 8e4d4f: b42a addi.n a10, a2, 4 + 8e4d51: c0b1 movi.n a11, 1 + 8e4d53: 5bff8a call8 8e4b7c <__dma_reg_write> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:395 + 8e4d56: d10f retw.n + +008e4d58 <__dma_recv_pkt>: +__dma_recv_pkt(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:405 + 8e4d58: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:406 + 8e4d5b: 6e2403 bltui a2, 4, 8e4d62 <__dma_recv_pkt+0xa> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:407 + 8e4d5e: c020 movi.n a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/hif/dma_lib//dma_lib.c:409 + 8e4d60: d10f retw.n + +008e4d62 <__dma_recv_pkt+0xa>: + 8e4d62: 180018 l32r a8, 4e8060 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a11, 10 + 8e5467: 5bfeb6 call8 8e4f40 + 8e546a: 180018 l32r a8, 4e8060 <_lit4_start+0x60> + 8e546d: d5a0 mov.n a5, a10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:595 + 8e546f: 8884 l32i.n a8, a8, 16 + 8e5471: c0b0 movi.n a11, 0 + 8e5473: c0ca movi.n a12, 10 + 8e5475: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:598 + 8e5478: 265403 s8i a6, a5, 3 + 8e547b: 068914 srli a9, a6, 8 + 8e547e: c0a0 movi.n a10, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:596 + 8e5480: c0b3 movi.n a11, 3 + 8e5482: 2b5401 s8i a11, a5, 1 + 8e5485: 2a5400 s8i a10, a5, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/htc/src/htc.c:598 + 8e5488: 295402 s8i a9, a5, 2 + 8e548b: c946 beqz.n a4, 8e54a5 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<_DMAengine_config_rx_queue+0x15>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:150 + 8e5929: 2832a6 l32i a8, a3, 0x298 + 8e592c: 0b8000 callx8 a8 + 8e592f: d6a0 mov.n a6, a10 + 8e5931: cca1 bnez.n a10, 8e5936 <_DMAengine_config_rx_queue+0x22> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:152 + 8e5933: 63fffc j 8e5933 <_DMAengine_config_rx_queue+0x1f> + +008e5936 <_DMAengine_config_rx_queue+0x22>: +/root/Workspace/0412_v202/tgt/target/adf/os/inc/adf_os_mem_pvt.h:10 + 8e5936: 283252 l32i a8, a3, 0x148 + 8e5939: c0a0 movi.n a10, 0 + 8e593b: db40 mov.n a11, a4 + 8e593d: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:154 + 8e5940: 9a61 s32i.n a10, a6, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:155 + 8e5942: 246504 s16i a4, a6, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:170 + 8e5945: b177 addi.n a7, a7, 1 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:156 + 8e5947: c0b0 movi.n a11, 0 + 8e5949: 9b60 s32i.n a11, a6, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:157 + 8e594b: 2b6505 s16i a11, a6, 10 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:158 + 8e594e: 2b6506 s16i a11, a6, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:159 + 8e5951: 2b6507 s16i a11, a6, 14 + 8e5954: c850 beqz.n a5, 8e5958 <_DMAengine_config_rx_queue+0x44> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:167 + 8e5956: 9560 s32i.n a5, a6, 0 + +008e5958 <_DMAengine_config_rx_queue+0x44>: + 8e5958: d560 mov.n a5, a6 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:148 + 8e595a: 7729cb bne a2, a7, 8e5929 <_DMAengine_config_rx_queue+0x15> + 8e595d: 8a10 l32i.n a10, a1, 0 + 8e595f: 600001 j 8e5964 <_DMAengine_config_rx_queue+0x50> + +008e5962 <_DMAengine_config_rx_queue+0x4e>: + 8e5962: c050 movi.n a5, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:172 + 8e5964: db50 mov.n a11, a5 + 8e5966: 5bffcd call8 8e589c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:173 + 8e5969: d10f retw.n + +008e596b <_DMAengine_config_rx_queue+0x57>: + ... + +008e596c <_DMAengine_xmit_buf>: +_DMAengine_xmit_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:176 + 8e596c: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:185 + 8e596f: 8930 l32i.n a9, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:176 + 8e5971: da20 mov.n a10, a2 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:186 + 8e5973: c0c0 movi.n a12, 0 + 8e5975: 64907a beqz a9, 8e59f3 <_DMAengine_xmit_buf+0x87> + 8e5978: c0f0 movi.n a15, 0 + +008e597a <_DMAengine_xmit_buf+0xe>: + 8e597a: 222a00 movi a2, 0x200 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+/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:235 + 8e5a2f: d10f retw.n + +008e5a31 <_DMAengine_flush_xmit+0x5>: + 8e5a31: 000000 ... + +008e5a34 <_DMAengine_has_compl_packets>: +_DMAengine_has_compl_packets(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:238 + 8e5a34: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:242 + 8e5a37: 8520 l32i.n a5, a2, 0 + 8e5a39: 8321 l32i.n a3, a2, 4 + 8e5a3b: 75310f beq a3, a5, 8e5a4e <_DMAengine_has_compl_packets+0x1a> + 8e5a3e: 0c0200 memw + 8e5a41: 285101 l16ui a8, a5, 2 + 8e5a44: c021 movi.n a2, 1 + 8e5a46: 080841 extui a8, a8, 0, 2 + 8e5a49: 688101 beqi a8, 1, 8e5a4e <_DMAengine_has_compl_packets+0x1a> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:246 + 8e5a4c: d10f retw.n + +008e5a4e <_DMAengine_has_compl_packets+0x1a>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:242 + 8e5a4e: c020 movi.n a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:246 + 8e5a50: d10f retw.n + +008e5a52 <_DMAengine_has_compl_packets+0x1e>: + ... + +008e5a54 <_DMAengine_reap_recv_buf>: +_DMAengine_reap_recv_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:250 + 8e5a54: 6c1004 entry a1, 32 + 8e5a57: da20 mov.n a10, a2 + 8e5a59: 120018 l32r a2, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:256 + 8e5a5c: 2822b9 l32i a8, a2, 0x2e4 + 8e5a5f: 0b8000 callx8 a8 + 8e5a62: d3a0 mov.n a3, a10 + 8e5a64: cca3 bnez.n a10, 8e5a6b <_DMAengine_reap_recv_buf+0x17> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:259 + 8e5a66: c0a0 movi.n a10, 0 + 8e5a68: 600013 j 8e5a7f <_DMAengine_reap_recv_buf+0x2b> + +008e5a6b <_DMAengine_reap_recv_buf+0x17>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:265 + 8e5a6b: 2822a1 l32i a8, a2, 0x284 + 8e5a6e: 0b8000 callx8 a8 + 8e5a71: d2a0 mov.n a2, a10 + 8e5a73: cca1 bnez.n a10, 8e5a78 <_DMAengine_reap_recv_buf+0x24> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:266 + 8e5a75: 63fffc j 8e5a75 <_DMAengine_reap_recv_buf+0x21> + +008e5a78 <_DMAengine_reap_recv_buf+0x24>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:268 + 8e5a78: db30 mov.n a11, a3 + 8e5a7a: 58003c call8 8e5b6c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:269 + 8e5a7d: da20 mov.n a10, a2 + 8e5a7f: d2a0 mov.n a2, a10 + 8e5a81: d10f retw.n + +008e5a83 <_DMAengine_reap_recv_buf+0x2f>: + ... + +008e5a84 <_DMAengine_reap_xmited_buf>: +_DMAengine_reap_xmited_buf(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:273 + 8e5a84: 6c1004 entry a1, 32 + 8e5a87: 180018 l32r a8, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:277 + 8e5a8a: 2882b9 l32i a8, a8, 0x2e4 + 8e5a8d: da20 mov.n a10, a2 + 8e5a8f: 0b8000 callx8 a8 + 8e5a92: dba0 mov.n a11, a10 + 8e5a94: cca3 bnez.n a10, 8e5a9b <_DMAengine_reap_xmited_buf+0x17> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:280 + 8e5a96: c030 movi.n a3, 0 + 8e5a98: 60001a j 8e5ab6 <_DMAengine_reap_xmited_buf+0x32> + +008e5a9b <_DMAengine_reap_xmited_buf+0x17>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:284 + 8e5a9b: 8322 l32i.n a3, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:285 + 8e5a9d: 8923 l32i.n a9, a2, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:284 + 8e5a9f: c0c0 movi.n a12, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:285 + 8e5aa1: 739906 bne a9, a3, 8e5aab <_DMAengine_reap_xmited_buf+0x27> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:286 + 8e5aa4: 9c22 s32i.n a12, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:287 + 8e5aa6: 9c23 s32i.n a12, a2, 12 + 8e5aa8: 600003 j 8e5aaf <_DMAengine_reap_xmited_buf+0x2b> + +008e5aab <_DMAengine_reap_xmited_buf+0x27>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:289 + 8e5aab: 8a31 l32i.n a10, a3, 4 + 8e5aad: 9a22 s32i.n a10, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:292 + 8e5aaf: 9c31 s32i.n a12, a3, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:293 + 8e5ab1: da30 mov.n a10, a3 + 8e5ab3: 58002e call8 8e5b6c +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:294 + 8e5ab6: d230 mov.n a2, a3 + 8e5ab8: d10f retw.n + +008e5aba <_DMAengine_reap_xmited_buf+0x36>: + ... + +008e5abc <_DMAengine_desc_dump>: +_DMAengine_desc_dump(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:298 + 8e5abc: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:302 + 8e5abf: 8320 l32i.n a3, a2, 0 + 8e5ac1: c040 movi.n a4, 0 + 8e5ac3: c478 movi.n a7, 72 + 8e5ac5: c563 movi.n a6, 83 + 8e5ac7: 150018 l32r a5, 4e8060 <_lit4_start+0x60> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:305 + 8e5aca: 8821 l32i.n a8, a2, 4 + 8e5acc: 738915 bne a8, a3, 8e5ae5 <_DMAengine_desc_dump+0x29> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:310 + 8e5acf: 285212 l32i a8, a5, 72 + 8e5ad2: db30 mov.n a11, a3 + 8e5ad4: 1a0186 l32r a10, 4e8618 <_lit4_start+0x618> + 8e5ad7: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:328 + 8e5ada: 285212 l32i a8, a5, 72 + 8e5add: 1a0187 l32r a10, 4e861c <_lit4_start+0x61c> + 8e5ae0: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:329 + 8e5ae3: d10f retw.n + +008e5ae5 <_DMAengine_desc_dump+0x29>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:318 + 8e5ae5: dc60 mov.n a12, a6 + 8e5ae7: 0c0200 memw + 8e5aea: 1a0188 l32r a10, 4e8620 <_lit4_start+0x620> + 8e5aed: 293101 l16ui a9, a3, 2 + 8e5af0: db30 mov.n a11, a3 + 8e5af2: 285212 l32i a8, a5, 72 + 8e5af5: 090940 extui a9, a9, 0, 1 + 8e5af8: 097c39 movnez a12, a7, a9 + 8e5afb: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:321 + 8e5afe: c0b5 movi.n a11, 5 + 8e5b00: b144 addi.n a4, a4, 1 + 8e5b02: da40 mov.n a10, a4 + 8e5b04: 580396 call8 8e6960 <__umodsi3> + 8e5b07: cca7 bnez.n a10, 8e5b12 <_DMAengine_desc_dump+0x56> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:323 + 8e5b09: 285212 l32i a8, a5, 72 + 8e5b0c: 1a0189 l32r a10, 4e8624 <_lit4_start+0x624> + +008e5b0f <_DMAengine_desc_dump+0x53>: + 8e5b0f: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:326 + 8e5b12: 0c0200 memw + 8e5b15: 8334 l32i.n a3, a3, 16 + 8e5b17: 63ffaf j 8e5aca <_DMAengine_desc_dump+0xe> + +008e5b1a <_DMAengine_desc_dump+0x5e>: + ... + +008e5b1c : +dma_engine_module_install(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:334 + 8e5b1c: 6c1004 entry a1, 32 + 8e5b1f: 19018d l32r a9, 4e8634 <_lit4_start+0x634> + 8e5b22: 13018f l32r a3, 4e863c <_lit4_start+0x63c> + 8e5b25: 1a018c l32r a10, 4e8630 <_lit4_start+0x630> + 8e5b28: 1b018b l32r a11, 4e862c <_lit4_start+0x62c> + 8e5b2b: 1c018a l32r a12, 4e8628 <_lit4_start+0x628> + 8e5b2e: 1d0192 l32r a13, 4e8648 <_lit4_start+0x648> + 8e5b31: 1e0191 l32r a14, 4e8644 <_lit4_start+0x644> + 8e5b34: 1f0190 l32r a15, 4e8640 <_lit4_start+0x640> + 8e5b37: 18018e l32r a8, 4e8638 <_lit4_start+0x638> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:340 + 8e5b3a: 9826 s32i.n a8, a2, 24 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:344 + 8e5b3c: 9d2a s32i.n a13, a2, 40 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:343 + 8e5b3e: 9e29 s32i.n a14, a2, 36 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:342 + 8e5b40: 9f28 s32i.n a15, a2, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:339 + 8e5b42: 9925 s32i.n a9, a2, 20 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:341 + 8e5b44: 9327 s32i.n a3, a2, 28 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:338 + 8e5b46: 9a24 s32i.n a10, a2, 16 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:337 + 8e5b48: 9b23 s32i.n a11, a2, 12 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:336 + 8e5b4a: 9c20 s32i.n a12, a2, 0 + 8e5b4c: 180197 l32r a8, 4e865c <_lit4_start+0x65c> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:349 + 8e5b4f: 982d s32i.n a8, a2, 52 + 8e5b51: 1c0193 l32r a12, 4e864c <_lit4_start+0x64c> + 8e5b54: 1b0194 l32r a11, 4e8650 <_lit4_start+0x650> + 8e5b57: 1a0195 l32r a10, 4e8654 <_lit4_start+0x654> + 8e5b5a: 130198 l32r a3, 4e8660 <_lit4_start+0x660> + 8e5b5d: 190196 l32r a9, 4e8658 <_lit4_start+0x658> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:348 + 8e5b60: 992c s32i.n a9, a2, 48 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:350 + 8e5b62: 932e s32i.n a3, a2, 56 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:347 + 8e5b64: 9a2b s32i.n a10, a2, 44 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:346 + 8e5b66: 9b22 s32i.n a11, a2, 8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:345 + 8e5b68: 9c21 s32i.n a12, a2, 4 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:354 + 8e5b6a: d10f retw.n + +008e5b6c : +relinkUSBDescToVdesc(): +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:357 + 8e5b6c: 6c1004 entry a1, 32 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:363 + 8e5b6f: 253cf0 addi a5, a3, -16 + 8e5b72: 9520 s32i.n a5, a2, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:364 + 8e5b74: 0c0200 memw + 8e5b77: 243102 l16ui a4, a3, 4 + 8e5b7a: 242504 s16i a4, a2, 8 + 8e5b7d: ca36 beqz.n a3, 8e5ba7 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:366 + 8e5b7f: c020 movi.n a2, 0 + +008e5b81 : +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:367 + 8e5b81: 0c0200 memw +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/dma_engine/src/dma_engine.c:370 + 8e5b84: 253cf0 addi a5, a3, -16 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4e8390 <_lit4_start+0x390> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:171 + 8e5edb: 2c2a00 movi a12, 0x200 + 8e5ede: 0cbb02 or a11, a11, a12 + 8e5ee1: 0b0b4f extui a11, a11, 0, 16 + 8e5ee4: 5bff8f call8 8e5d24 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:173 + 8e5ee7: 28323b l32i a8, a3, 236 + 8e5eea: 2a3ae8 movi a10, 0x3e8 + 8e5eed: 0b8000 callx8 a8 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:176 + 8e5ef0: 0c0200 memw + 8e5ef3: 2b2284 l32i a11, a2, 0x210 + 8e5ef6: 1a00e4 l32r a10, 4e8390 <_lit4_start+0x390> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/fwd//fwd.c:178 + 8e5ef9: 2cdaff movi a12, 0xfffffdff + 8e5efc: 0cbb01 and a11, a11, a12 + 8e5eff: 0b0b4f extui a11, a11, 0, 16 + 8e5f02: 5bff88 call8 8e5d24 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a1, 32 + 8e61fb: 1201b5 l32r a2, 4e86d4 <_lit4_start+0x6d4> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:122 + 8e61fe: 02330a addx4 a3, a3, a2 + 8e6201: 8530 l32i.n a5, a3, 0 + 8e6203: c850 beqz.n a5, 8e6207 <_buf_pool_static_free_buf+0xf> +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:125 + 8e6205: 9541 s32i.n a5, a4, 4 + +008e6207 <_buf_pool_static_free_buf+0xf>: +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:123 + 8e6207: 9430 s32i.n a4, a3, 0 +/root/Workspace/0412_v202/tgt/build/magpie_1_1/image/magpie/../../../..//build/magpie_1_1/rom/buf_pool/src/buf_pool_static.c:128 + 8e6209: d10f retw.n + +008e620b <_buf_pool_static_free_buf+0x13>: + ... + +008e620c <_xtos_set_exception_handler>: +_xtos_set_exception_handler(): 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8e6238: 092b0c sub a11, a2, a9 + 8e623b: 0ba238 moveqz a2, a10, a11 + 8e623e: d10f retw.n + +008e6240 <_xtos_set_exception_handler+0x34>: + 8e6240: c020 movi.n a2, 0 + 8e6242: d10f retw.n + +008e6244 <_xtos_set_exception_handler+0x38>: + 8e6244: c0a0 movi.n a10, 0 + 8e6246: 09970c sub a7, a9, a9 + 8e6249: 1601b8 l32r a6, 4e86e0 <_lit4_start+0x6e0> + 8e624c: 180006 l32r a8, 4e8018 <_lit4_start+0x18> + 8e624f: 1c01b7 l32r a12, 4e86dc <_lit4_start+0x6dc> + 8e6252: 0e2511 slli a5, a2, 2 + 8e6255: 1401b9 l32r a4, 4e86e4 <_lit4_start+0x6e4> + 8e6258: ac5c add.n a12, a5, a12 + 8e625a: a855 add.n a5, a5, a8 + 8e625c: 82c0 l32i.n a2, a12, 0 + 8e625e: 99c0 s32i.n a9, a12, 0 + 8e6260: 076439 movnez a4, a6, a7 + 8e6263: 9450 s32i.n a4, a5, 0 + 8e6265: 092b0c sub a11, a2, a9 + 8e6268: 0ba238 moveqz a2, a10, a11 + 8e626b: d10f retw.n + +008e626d <_xtos_set_exception_handler+0x61>: + 8e626d: 000000 ... + +008e6270 <_xtos_cause3_handler>: +_xtos_cause3_handler(): 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8e6bba: 22700b l8ui a2, a7, 11 + 8e6bbd: 22440b s8i a2, a4, 11 + 8e6bc0: 22700c l8ui a2, a7, 12 + 8e6bc3: 22440c s8i a2, a4, 12 + 8e6bc6: 22700d l8ui a2, a7, 13 + 8e6bc9: 22440d s8i a2, a4, 13 + 8e6bcc: 22700e l8ui a2, a7, 14 + 8e6bcf: 22440e s8i a2, a4, 14 + 8e6bd2: 22700f l8ui a2, a7, 15 + 8e6bd5: 22440f s8i a2, a4, 15 + 8e6bd8: 277c10 addi a7, a7, 16 + 8e6bdb: 244c10 addi a4, a4, 16 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:141 + 8e6bde: d280 mov.n a2, a8 + 8e6be0: d10f retw.n + +008e6be2 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:114 + 8e6be2: d380 mov.n a3, a8 + 8e6be4: 6f9b02 bgeui a9, 16, 8e6bea + 8e6be7: 600082 j 8e6c6d + 8e6bea: c0a1 movi.n a10, 1 + 8e6bec: 269c0f addi a6, a9, 15 + 8e6bef: 09963b movgez a6, a9, a9 + 8e6bf2: 064612 srai a6, a6, 4 + 8e6bf5: 0a6635 max a6, a6, a10 + 8e6bf8: 060f41 extui a15, a6, 0, 2 + 8e6bfb: 066402 or a4, a6, a6 + 8e6bfe: 042212 srai a2, a4, 2 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8e6c31: 8273 l32i.n a2, a7, 12 + 8e6c33: 9243 s32i.n a2, a4, 12 + 8e6c35: 8274 l32i.n a2, a7, 16 + 8e6c37: 9244 s32i.n a2, a4, 16 + 8e6c39: 8275 l32i.n a2, a7, 20 + 8e6c3b: 9245 s32i.n a2, a4, 20 + 8e6c3d: 8276 l32i.n a2, a7, 24 + 8e6c3f: 9246 s32i.n a2, a4, 24 + 8e6c41: 8277 l32i.n a2, a7, 28 + 8e6c43: 9247 s32i.n a2, a4, 28 + 8e6c45: 8278 l32i.n a2, a7, 32 + 8e6c47: 9248 s32i.n a2, a4, 32 + 8e6c49: 8279 l32i.n a2, a7, 36 + 8e6c4b: 9249 s32i.n a2, a4, 36 + 8e6c4d: 827a l32i.n a2, a7, 40 + 8e6c4f: 924a s32i.n a2, a4, 40 + 8e6c51: 827b l32i.n a2, a7, 44 + 8e6c53: 924b s32i.n a2, a4, 44 + 8e6c55: 827c l32i.n a2, a7, 48 + 8e6c57: 924c s32i.n a2, a4, 48 + 8e6c59: 827d l32i.n a2, a7, 52 + 8e6c5b: 924d s32i.n a2, a4, 52 + 8e6c5d: 827e l32i.n a2, a7, 56 + 8e6c5f: 924e s32i.n a2, a4, 56 + 8e6c61: 827f l32i.n a2, a7, 60 + 8e6c63: 924f s32i.n a2, a4, 60 + 8e6c65: 277c40 addi a7, a7, 64 + 8e6c68: 244c40 addi a4, a4, 64 + +008e6c6b : + 8e6c6b: d340 mov.n a3, a4 + +008e6c6d : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:124 + 8e6c6d: d6a0 mov.n a6, a10 + 8e6c6f: 6fa402 bgeui a10, 4, 8e6c75 + 8e6c72: 63fee2 j 8e6b58 + 8e6c75: 0a2b43 extui a11, a10, 2, 4 + 8e6c78: 0a2914 srli a9, a10, 2 + 8e6c7b: d490 mov.n a4, a9 + 8e6c7d: 6db907 loopnez a11, 8e6c88 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:126 + 8e6c80: 8c70 l32i.n a12, a7, 0 + 8e6c82: 9c30 s32i.n a12, a3, 0 + 8e6c84: b477 addi.n a7, a7, 4 + 8e6c86: b433 addi.n a3, a3, 4 + +008e6c88 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:124 + 8e6c88: 0e9a11 slli a10, a9, 2 + 8e6c8b: 044214 srli a2, a4, 4 + 8e6c8e: 033402 or a4, a3, a3 + 8e6c91: 6d2945 loopnez a2, 8e6cda +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:126 + 8e6c94: 8270 l32i.n a2, a7, 0 + 8e6c96: 9240 s32i.n a2, a4, 0 + 8e6c98: 8271 l32i.n a2, a7, 4 + 8e6c9a: 9241 s32i.n a2, a4, 4 + 8e6c9c: 8272 l32i.n a2, a7, 8 + 8e6c9e: 9242 s32i.n a2, a4, 8 + 8e6ca0: 8273 l32i.n a2, a7, 12 + 8e6ca2: 9243 s32i.n a2, a4, 12 + 8e6ca4: 8274 l32i.n a2, a7, 16 + 8e6ca6: 9244 s32i.n a2, a4, 16 + 8e6ca8: 8275 l32i.n a2, a7, 20 + 8e6caa: 9245 s32i.n a2, a4, 20 + 8e6cac: 8276 l32i.n a2, a7, 24 + 8e6cae: 9246 s32i.n a2, a4, 24 + 8e6cb0: 8277 l32i.n a2, a7, 28 + 8e6cb2: 9247 s32i.n a2, a4, 28 + 8e6cb4: 8278 l32i.n a2, a7, 32 + 8e6cb6: 9248 s32i.n a2, a4, 32 + 8e6cb8: 8279 l32i.n a2, a7, 36 + 8e6cba: 9249 s32i.n a2, a4, 36 + 8e6cbc: 827a l32i.n a2, a7, 40 + 8e6cbe: 924a s32i.n a2, a4, 40 + 8e6cc0: 827b l32i.n a2, a7, 44 + 8e6cc2: 924b s32i.n a2, a4, 44 + 8e6cc4: 827c l32i.n a2, a7, 48 + 8e6cc6: 924c s32i.n a2, a4, 48 + 8e6cc8: 827d l32i.n a2, a7, 52 + 8e6cca: 924d s32i.n a2, a4, 52 + 8e6ccc: 827e l32i.n a2, a7, 56 + 8e6cce: 924e s32i.n a2, a4, 56 + 8e6cd0: 827f l32i.n a2, a7, 60 + 8e6cd2: 924f s32i.n a2, a4, 60 + 8e6cd4: 277c40 addi a7, a7, 64 + 8e6cd7: 244c40 addi a4, a4, 64 + +008e6cda : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/string/memmove.c:124 + 8e6cda: 0a6a0c sub a10, a6, a10 + 8e6cdd: d340 mov.n a3, a4 + 8e6cdf: 63fe75 j 8e6b58 + +008e6ce2 : + ... + +008e6ce4 <__memset_aux>: + ... + +008e6ce5 <__memset_aux+0x1>: +__memset_aux(): +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:59 + 8e6ce5: 6d4904 loopnez a4, 8e6ced <__memset_aux+0x9> +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:64 + 8e6ce8: 235400 s8i a3, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:65 + 8e6ceb: b155 addi.n a5, a5, 1 + +008e6ced <__memset_aux+0x9>: +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:69 + 8e6ced: d10f retw.n + +008e6cef <__memset_aux+0xb>: + ... + +008e6cf0 <__memset_aux+0xc>: +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:79 + 8e6cf0: 6e48f1 bltui a4, 8, 8e6ce5 <__memset_aux+0x1> +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:82 + 8e6cf3: 235400 s8i a3, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:83 + 8e6cf6: b155 addi.n a5, a5, 1 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:84 + 8e6cf8: b044 addi.n a4, a4, -1 + +008e6cfa <__memset_aux+0x16>: +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:87 + 8e6cfa: 7e5728 bbci a5, 30, 8e6d26 + +008e6cfd <__memset_aux+0x19>: +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:92 + 8e6cfd: 6e48e4 bltui a4, 8, 8e6ce5 <__memset_aux+0x1> +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:95 + 8e6d00: 235500 s16i a3, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:96 + 8e6d03: b255 addi.n a5, a5, 2 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:97 + 8e6d05: 244cfe addi a4, a4, -2 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:100 + 8e6d08: 60001a j 8e6d26 + +008e6d0b <__memset_aux+0x27>: + ... + +008e6d0c : +memset(): +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:107 + 8e6d0c: 6c1002 entry a1, 16 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:111 + 8e6d0f: 030347 extui a3, a3, 0, 8 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:112 + 8e6d12: 083711 slli a7, a3, 8 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:113 + 8e6d15: 073302 or a3, a3, a7 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:114 + 8e6d18: 003711 slli a7, a3, 16 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:115 + 8e6d1b: 073302 or a3, a3, a7 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:117 + 8e6d1e: d520 mov.n a5, a2 + +008e6d20 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:120 + 8e6d20: 7f2fcc bbsi a2, 31, 8e6cf0 <__memset_aux+0xc> +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:121 + 8e6d23: 7e2fd6 bbsi a2, 30, 8e6cfd <__memset_aux+0x19> + +008e6d26 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:125 + 8e6d26: 044714 srli a7, a4, 4 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:129 + 8e6d29: 6d790a loopnez a7, 8e6d37 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:136 + 8e6d2c: 9350 s32i.n a3, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:137 + 8e6d2e: 9351 s32i.n a3, a5, 4 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:138 + 8e6d30: 9352 s32i.n a3, a5, 8 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:139 + 8e6d32: 9353 s32i.n a3, a5, 12 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:140 + 8e6d34: 255c10 addi a5, a5, 16 + +008e6d37 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:146 + 8e6d37: 7c4706 bbci a4, 28, 8e6d41 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:149 + 8e6d3a: 9350 s32i.n a3, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:150 + 8e6d3c: 9351 s32i.n a3, a5, 4 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:151 + 8e6d3e: 255c08 addi a5, a5, 8 + +008e6d41 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:153 + 8e6d41: 7d4703 bbci a4, 29, 8e6d48 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:156 + 8e6d44: 9350 s32i.n a3, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:157 + 8e6d46: b455 addi.n a5, a5, 4 + +008e6d48 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:159 + 8e6d48: 7e4704 bbci a4, 30, 8e6d50 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:162 + 8e6d4b: 235500 s16i a3, a5, 0 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:163 + 8e6d4e: b255 addi.n a5, a5, 2 + +008e6d50 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:165 + 8e6d50: 7f4702 bbci a4, 31, 8e6d56 +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:168 + 8e6d53: 235400 s8i a3, a5, 0 + +008e6d56 : +/home/customer/tree/RB-2007.2/p4root/Xtensa/Target-libs/newlib/newlib/libc/machine/xtensa/memset.S:169 + 8e6d56: d10f retw.n +Disassembly of section .debug_aranges: + +00000000 <.debug_aranges>: + 0: 0000001c 00020000 00000400 00000000 ................ + 10: 008e1000 0000002a 00000000 00000000 .......*........ + 20: 0000001c 00020000 00790400 00000000 .........y...... + 30: 008e0c20 00000006 00000000 00000000 ... ............ + 40: 0000001c 00020000 00f50400 00000000 ................ + 50: 008e0f20 00000006 00000000 00000000 ... ............ + 60: 0000001c 00020000 01720400 00000000 .........r...... + 70: 008e0d40 00000006 00000000 00000000 ...@............ + 80: 0000001c 00020000 01ef0400 00000000 ................ + 90: 008e0000 000000de 00000000 00000000 ................ + a0: 0000001c 00020000 026b0400 00000000 .........k...... + b0: 008e0e20 00000017 00000000 00000000 ... ............ + c0: 0000001c 00020000 02e60400 00000000 ................ + d0: 008e0ce4 00000003 00000000 00000000 ................ + e0: 0000001c 00020000 03600400 00000000 .........`...... + f0: 008e0800 0000016a 00000000 00000000 .......j........ + 100: 0000001c 00020000 03de0400 00000000 ................ + 110: 008e0a20 00000006 00000000 00000000 ... ............ + 120: 0000001c 00020000 04580400 00000000 .........X...... + 130: 008e0b20 00000006 00000000 00000000 ... ............ + 140: 0000001c 00020000 04d20400 00000000 ................ + 150: 008e102c 000000d7 00000000 00000000 ...,............ + 160: 0000001c 00020000 05540400 00000000 .........T...... + 170: 008e1104 0000006f 00000000 00000000 .......o........ + 180: 0000001c 00020000 05d70400 00000000 ................ + 190: 008e1174 0000006e 00000000 00000000 ...t...n........ + 1a0: 0000001c 00020000 065c0400 00000000 .........\...... + 1b0: 008e11e4 0000005c 00000000 00000000 .......\........ + 1c0: 0000001c 00020000 0a0e0400 00000000 ................ + 1d0: 008e1240 000000b1 00000000 00000000 ...@............ + 1e0: 0000001c 00020000 0a930400 00000000 ................ + 1f0: 008e12f4 000000ae 00000000 00000000 ................ + 200: 0000001c 00020000 0b180400 00000000 ................ + 210: 008e67e4 00000008 00000000 00000000 ..g............. + 220: 0000001c 00020000 0b970400 00000000 ................ + 230: 008e67ec 0000000d 00000000 00000000 ..g............. + 240: 0000001c 00020000 0c140400 00000000 ................ + 250: 008e67fc 00000018 00000000 00000000 ..g............. + 260: 0000001c 00020000 0c8e0400 00000000 ................ + 270: 008e13a4 00000826 00000000 00000000 .......&........ + 280: 0000001c 00020000 600a0400 00000000 ........`....... + 290: 008e1bcc 00000078 00000000 00000000 .......x........ + 2a0: 0000001c 00020000 a8820400 00000000 ................ + 2b0: 008e1c44 000000f2 00000000 00000000 ...D............ + 2c0: 0000001c 00020000 f3df0400 00000000 ................ + 2d0: 008e1d38 000003e5 00000000 00000000 ...8............ + 2e0: 0000001c 00020001 3de70400 00000000 ........=....... + 2f0: 008e2120 0000018e 00000000 00000000 ..! ............ + 300: 0000001c 00020001 88d00400 00000000 ................ + 310: 008e22b0 00000026 00000000 00000000 .."....&........ + 320: 0000001c 00020001 d01d0400 00000000 ................ + 330: 008e22d8 00000175 00000000 00000000 .."....u........ + 340: 0000001c 00020002 1bba0400 00000000 ................ + 350: 008e2450 00000513 00000000 00000000 ..$P............ + 360: 0000001c 00020002 66210400 00000000 ........f!...... + 370: 008e2964 00000155 00000000 00000000 ..)d...U........ + 380: 0000001c 00020002 afb60400 00000000 ................ + 390: 008e2abc 0000002b 00000000 00000000 ..*....+........ + 3a0: 0000001c 00020002 f6e20400 00000000 ................ + 3b0: 008e2ae8 000000b2 00000000 00000000 ..*............. + 3c0: 0000001c 00020003 3f930400 00000000 ........?....... + 3d0: 008e2b9c 000000de 00000000 00000000 ..+............. + 3e0: 0000001c 00020003 89060400 00000000 ................ + 3f0: 008e2c7c 00000114 00000000 00000000 ..,|............ + 400: 0000001c 00020003 d2490400 00000000 .........I...... + 410: 008e2d90 0000019b 00000000 00000000 ..-............. + 420: 0000001c 00020004 1bf60400 00000000 ................ + 430: 008e2f2c 0000041a 00000000 00000000 ../,............ + 440: 0000001c 00020004 69e20400 00000000 ........i....... + 450: 008e3348 000004d4 00000000 00000000 ..3H............ + 460: 0000001c 00020004 b9550400 00000000 .........U...... + 470: 008e381c 00000f9d 00000000 00000000 ..8............. + 480: 0000001c 00020005 10430400 00000000 .........C...... + 490: 008e47bc 000003b3 00000000 00000000 ..G............. + 4a0: 0000001c 00020005 59d90400 00000000 ........Y....... + 4b0: 008e4b70 00000243 00000000 00000000 ..Kp...C........ + 4c0: 0000001c 00020005 a7030400 00000000 ................ + 4d0: 008e4db4 00000084 00000000 00000000 ..M............. + 4e0: 0000001c 00020005 eee00400 00000000 ................ + 4f0: 008e4e38 000000b5 00000000 00000000 ..N8............ + 500: 0000001c 00020006 37230400 00000000 ........7#...... + 510: 008e4ef0 000008ef 00000000 00000000 ..N............. + 520: 0000001c 00020006 8fc30400 00000000 ................ + 530: 008e57e0 000003d3 00000000 00000000 ..W............. + 540: 0000001c 00020006 dbf20400 00000000 ................ + 550: 008e5bb4 0000016f 00000000 00000000 ..[....o........ + 560: 0000001c 00020007 2c9a0400 00000000 ........,....... + 570: 008e5d24 00000404 00000000 00000000 ..]$............ + 580: 0000001c 00020007 7ac00400 00000000 ........z....... + 590: 008e6128 000000e3 00000000 00000000 ..a(............ + 5a0: 0000001c 00020007 c4af0400 00000000 ................ + 5b0: 008e620c 00000061 00000000 00000000 ..b....a........ + 5c0: 0000001c 00020007 c79e0400 00000000 ................ + 5d0: 008e6814 00000005 00000000 00000000 ..h............. + 5e0: 0000001c 00020007 c8170400 00000000 ................ + 5f0: 008e6270 00000079 00000000 00000000 ..bp...y........ + 600: 0000001c 00020007 c89c0400 00000000 ................ + 610: 008e681c 00000026 00000000 00000000 ..h....&........ + 620: 0000001c 00020007 d5850400 00000000 ................ + 630: 008e62ec 00000137 00000000 00000000 ..b....7........ + 640: 0000001c 00020007 d6580400 00000000 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6765745f 64657363 72697074 6f720000 get_descriptor.. + 71b0: 00082302 2350085f 7573625f 6765745f ..#.#P._usb_get_ + 71c0: 73746174 75730000 00082302 2354085f status....#.#T._ + 71d0: 7573625f 73657475 705f6465 73630000 usb_setup_desc.. + 71e0: 00011702 2358085f 7573625f 7265675f ....#X._usb_reg_ + 71f0: 6f757400 00000117 02235c08 5f757362 out......#\._usb + 7200: 5f737461 7475735f 696e0000 00011702 _status_in...... + 7210: 2360085f 7573625f 6570305f 74785f64 #`._usb_ep0_tx_d + 7220: 61746100 00000117 02236408 5f757362 ata......#d._usb + 7230: 5f657030 5f72785f 64617461 00000001 _ep0_rx_data.... + 7240: 17022368 085f7573 625f636c 6b5f696e ..#h._usb_clk_in + 7250: 69740000 00011702 236c0007 5f564445 it......#l.._VDE + 7260: 53430024 000012dd 086e6578 745f6465 SC.$.....next_de + 7270: 73630000 0012dd02 23000862 75665f61 sc......#..buf_a + 7280: 64647200 000012f1 02230408 6275665f ddr......#..buf_ + 7290: 73697a65 00000012 f8022308 08646174 size......#..dat + 72a0: 615f6f66 66736574 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00000009 21050300 5009741f 63757272 ....!...P.t.curr + f380: 656e745f 7469636b 00000009 211f6465 ent_tick....!.de + f390: 6c74615f 7469636b 00000009 21002301 lta_tick....!.#. + f3a0: 0115636d 6e6f735f 636c6f63 6b5f6d6f ..cmnos_clock_mo + f3b0: 64756c65 5f696e73 74616c6c 00010103 dule_install.... + f3c0: 92012002 9000008e 1d04008e 1d362401 .. ..........6$. + f3d0: 01157462 6c000000 48c70152 00000000 ..tbl...H..R.... + f3e0: 004a0400 02000007 5404012f 726f6f74 .J......T../root + f3f0: 2f576f72 6b737061 63652f30 3431325f /Workspace/0412_ + f400: 76323032 2f746774 2f627569 6c642f6d v202/tgt/build/m + f410: 61677069 655f315f 312f696d 6167652f agpie_1_1/image/ + f420: 6d616770 69652f2e 2e2f2e2e 2f2e2e2f magpie/../../../ + f430: 2e2e2f2f 6275696c 642f6d61 67706965 ..//build/magpie + f440: 5f315f31 2f726f6d 2f636d6e 6f732f65 _1_1/rom/cmnos/e + f450: 6570726f 6d2f7372 632f636d 6e6f735f eprom/src/cmnos_ + f460: 65657072 6f6d2e63 002f726f 6f742f57 eeprom.c./root/W + f470: 6f726b73 70616365 2f303431 325f7632 orkspace/0412_v2 + f480: 30322f74 67742f62 75696c64 2f6d6167 02/tgt/build/mag + f490: 7069655f 315f312f 726f6d2f 636d6e6f pie_1_1/rom/cmno + f4a0: 732f6565 70726f6d 0078742d 78636320 s/eeprom.xt-xcc + f4b0: 666f7220 372e312e 30202d4f 50543a61 for 7.1.0 -OPT:a + f4c0: 6c69676e 5f696e73 74727563 74696f6e lign_instruction + f4d0: 733d3332 202d4f32 202d6733 202d4f50 s=32 -O2 -g3 -OP + f4e0: 543a7370 61636500 01000000 416f0201 T:space.....Ao.. + f4f0: 03000001 0f040004 696e7400 05040463 ........int....c + f500: 68617200 07010500 00011f05 0000011f har............. + f510: 03000001 2c040006 00000118 01030000 ....,........... + f520: 01380400 07707269 6e74665f 61706900 .8...printf_api. + f530: 08000001 7c085f70 72696e74 665f696e ....|._printf_in + f540: 69740000 00011102 2300085f 7072696e it......#.._prin + f550: 74660000 00013e02 23040004 73686f72 tf....>.#...shor + f560: 7420756e 7369676e 65642069 6e740007 t unsigned int.. + f570: 02097569 6e743136 5f740000 00017c04 ..uint16_t....|. + f580: 6c6f6e67 20756e73 69676e65 6420696e long unsigned in + f590: 74000704 0975696e 7433325f 74000000 t....uint32_t... + f5a0: 01a00775 6172745f 6669666f 00080000 ...uart_fifo.... + f5b0: 020e0873 74617274 5f696e64 65780000 ...start_index.. + f5c0: 00019202 23000865 6e645f69 6e646578 ....#..end_index + f5d0: 00000001 92022302 086f7665 7272756e ......#..overrun + f5e0: 5f657272 00000001 b5022304 00077561 _err......#...ua + f5f0: 72745f61 70690020 000002c7 085f7561 rt_api. ....._ua + f600: 72745f69 6e697400 0000031e 02230008 rt_init......#.. + f610: 5f756172 745f6368 61725f70 75740000 _uart_char_put.. + f620: 00034502 2304085f 75617274 5f636861 ..E.#.._uart_cha + f630: 725f6765 74000000 03590223 08085f75 r_get....Y.#.._u + f640: 6172745f 7374725f 6f757400 00000362 art_str_out....b + f650: 02230c08 5f756172 745f7461 736b0000 .#.._uart_task.. + f660: 00011102 2310085f 75617274 5f737461 ....#.._uart_sta + f670: 74757300 0000031e 02231408 5f756172 tus......#.._uar + f680: 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6d645f73 74720000 .......cmd_str.. + f790: 00037b02 23000868 656c705f 73747200 ..{.#..help_str. + f7a0: 0000037b 02230408 636d645f 66756e63 ...{.#..cmd_func + f7b0: 00000003 88022308 00076462 675f6170 ......#...dbg_ap + f7c0: 69000800 00040d08 5f646267 5f696e69 i......._dbg_ini + f7d0: 74000000 01110223 00085f64 62675f74 t......#.._dbg_t + f7e0: 61736b00 00000111 02230400 0a040004 ask......#...... + f7f0: 756e7369 676e6564 20696e74 00070406 unsigned int.... + f800: 0000040d 01030000 04200400 0b0b0300 ......... ...... + f810: 00042e04 00060000 040d0103 00000436 ...............6 + f820: 04000600 00011801 03000004 43040007 ............C... + f830: 6d656d5f 61706900 14000004 b2085f6d mem_api......._m + f840: 656d5f69 6e697400 00000111 02230008 em_init......#.. + f850: 5f6d656d 73657400 00000426 02230408 _memset....&.#.. + f860: 5f6d656d 63707900 0000043c 02230808 _memcpy....<.#.. + f870: 5f6d656d 6d6f7665 00000004 3c02230c _memmove....<.#. + f880: 085f6d65 6d636d70 00000004 49022310 ._memcmp....I.#. + f890: 000c7265 67697374 65725f64 756d705f ..register_dump_ + f8a0: 73000001 03000004 b2040002 01030000 s............... + f8b0: 04cc0400 02010300 0004d504 00060000 ................ + f8c0: 01180103 000004de 04000d68 6f737469 ...........hosti + f8d0: 665f7300 04000005 3a0e4849 465f5553 f_s.....:.HIF_US + f8e0: 4200000e 4849465f 50434945 00010e48 B...HIF_PCIE...H + f8f0: 49465f47 4d414300 020e4849 465f5043 IF_GMAC...HIF_PC + f900: 4900030e 4849465f 4e554d00 040e4849 I...HIF_NUM...HI + f910: 465f4e4f 4e450005 0009415f 484f5354 F_NONE....A_HOST + f920: 49460000 0004eb06 0000053a 01030000 IF.........:.... + f930: 05480400 06000003 36010300 00055504 .H......6.....U. + f940: 00060000 01920103 00000562 0400076d ...........b...m + f950: 6973635f 61706900 24000006 52085f73 isc_api.$...R._s + f960: 79737465 6d5f7265 73657400 00000111 ystem_reset..... + f970: 02230008 5f6d6163 5f726573 65740000 .#.._mac_reset.. + f980: 00011102 2304085f 61737366 61696c00 ....#.._assfail. + f990: 000004ce 02230808 5f6d6973 616c6967 .....#.._misalig + f9a0: 6e65645f 6c6f6164 5f68616e 646c6572 ned_load_handler + f9b0: 00000004 ce02230c 085f7265 706f7274 ......#.._report + f9c0: 5f666169 6c757265 5f746f5f 686f7374 _failure_to_host + f9d0: 00000004 d7022310 085f7461 72676574 ......#.._target + f9e0: 5f69645f 67657400 000004e4 02231408 _id_get......#.. + f9f0: 5f69735f 686f7374 5f707265 73656e74 _is_host_present + fa00: 00000005 4e022318 085f6b62 68697400 ....N.#.._kbhit. + fa10: 0000055b 02231c08 5f726f6d 5f766572 ...[.#.._rom_ver + fa20: 73696f6e 5f676574 00000005 68022320 sion_get....h.# + fa30: 00060000 037b0103 00000652 04000600 .....{.....R.... + fa40: 00037b01 03000006 5f040006 00000118 ..{....._....... + fa50: 01030000 066c0400 06000001 18010300 .....l.......... + fa60: 00067904 00060000 01180103 00000686 ..y............. + fa70: 04000773 7472696e 675f6170 69001800 ...string_api... + fa80: 00070c08 5f737472 696e675f 696e6974 ...._string_init + fa90: 00000001 11022300 085f7374 72637079 ......#.._strcpy + faa0: 00000006 58022304 085f7374 726e6370 ....X.#.._strncp + fab0: 79000000 06650223 08085f73 74726c65 y....e.#.._strle + fac0: 6e000000 06720223 0c085f73 7472636d n....r.#.._strcm + fad0: 70000000 067f0223 10085f73 74726e63 p......#.._strnc + fae0: 6d700000 00068c02 2314000f 00000410 mp......#....... + faf0: 14000007 19100400 095f415f 54494d45 ........._A_TIME + fb00: 525f5350 41434500 0000070c 09415f74 R_SPACE......A_t + fb10: 696d6572 5f740000 00071903 0000072d imer_t.........- + fb20: 04000201 03000007 43040002 01030000 ........C....... + fb30: 074c0400 09415f48 414e444c 45000000 .L...A_HANDLE... + fb40: 04100201 09415f54 494d4552 5f46554e .....A_TIMER_FUN + fb50: 43000000 07630300 00076504 00020103 C....c....e..... + fb60: 0000077e 04000774 696d6572 5f617069 ...~...timer_api + fb70: 00140000 07fd085f 74696d65 725f696e ......._timer_in + fb80: 69740000 00011102 2300085f 74696d65 it......#.._time + fb90: 725f6172 6d000000 07450223 04085f74 r_arm....E.#.._t + fba0: 696d6572 5f646973 61726d00 0000074e imer_disarm....N + fbb0: 02230808 5f74696d 65725f73 6574666e .#.._timer_setfn + fbc0: 00000007 8002230c 085f7469 6d65725f ......#.._timer_ + fbd0: 72756e00 00000111 02231000 09424f4f run......#...BOO + fbe0: 4c45414e 00000001 92060000 07fd0103 LEAN............ + fbf0: 0000080a 04000600 0007fd01 03000008 ................ + fc00: 17040006 000007fd 01030000 08240400 .............$.. + fc10: 07726f6d 705f6170 69001000 00089608 .romp_api....... + fc20: 5f726f6d 705f696e 69740000 00011102 _romp_init...... + fc30: 2300085f 726f6d70 5f646f77 6e6c6f61 #.._romp_downloa + fc40: 64000000 08100223 04085f72 6f6d705f d......#.._romp_ + fc50: 696e7374 616c6c00 0000081d 02230808 install......#.. + fc60: 5f726f6d 705f6465 636f6465 00000008 _romp_decode.... + fc70: 2a02230c 0007726f 6d5f7061 7463685f *.#...rom_patch_ + fc80: 73740010 000008f2 08637263 31360000 st.......crc16.. + fc90: 00019202 2300086c 656e0000 00019202 ....#..len...... + fca0: 2302086c 645f6164 64720000 0001b502 #..ld_addr...... + fcb0: 23040866 756e5f61 64647200 000001b5 #..fun_addr..... + fcc0: 02230808 7066756e 00000003 4c02230c .#..pfun....L.#. + fcd0: 00076565 705f7265 6469725f 61646472 ..eep_redir_addr + fce0: 00040000 0924086f 66667365 74000000 .....$.offset... + fcf0: 01920223 00087369 7a650000 00019202 ...#..size...... + fd00: 23020009 415f5549 4e543332 00000004 #...A_UINT32.... + fd10: 10060000 040d0103 00000932 04000761 ...........2...a + fd20: 6c6c6f63 72616d5f 61706900 0c000009 llocram_api..... + fd30: a308636d 6e6f735f 616c6c6f 6372616d ..cmnos_allocram + fd40: 5f696e69 74000000 09380223 0008636d _init....8.#..cm + fd50: 6e6f735f 616c6c6f 6372616d 00000009 nos_allocram.... + fd60: 38022304 08636d6e 6f735f61 6c6c6f63 8.#..cmnos_alloc + fd70: 72616d5f 64656275 67000000 01110223 ram_debug......# + fd80: 08000201 03000009 a3040009 415f5441 ............A_TA + fd90: 534b4c45 545f4655 4e430000 0009a507 SKLET_FUNC...... + fda0: 5f746173 6b6c6574 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....#........... + feb0: 06000009 24010300 000ad104 00020103 ....$........... + fec0: 00000ade 04000763 6c6f636b 5f617069 .......clock_api + fed0: 00240000 0bc0085f 636c6f63 6b5f696e .$....._clock_in + fee0: 69740000 000aca02 2300085f 636c6f63 it......#.._cloc + fef0: 6b726567 735f696e 69740000 00011102 kregs_init...... + ff00: 2304085f 75617274 5f667265 7175656e #.._uart_frequen + ff10: 63790000 000ad702 2308085f 64656c61 cy......#.._dela + ff20: 795f7573 0000000a e002230c 085f776c y_us......#.._wl + ff30: 616e5f62 616e645f 73657400 00000ae0 an_band_set..... + ff40: 02231008 5f726566 636c6b5f 73706565 .#.._refclk_spee + ff50: 645f6765 74000000 0ad70223 14085f6d d_get......#.._m + ff60: 696c6c69 7365636f 6e647300 00000ad7 illiseconds..... + ff70: 02231808 5f737973 636c6b5f 6368616e .#.._sysclk_chan + ff80: 67650000 00011102 231c085f 636c6f63 ge......#.._cloc + ff90: 6b5f7469 636b0000 00011102 23200006 k_tick......# .. + ffa0: 000001b5 01030000 0bc00400 09415f6f .............A_o + ffb0: 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725f6174 74616368 5f697372 _intr_attach_isr + 100c0: 0000000c 1a022318 085f6765 745f696e ......#.._get_in + 100d0: 7472656e 61626c65 0000000c 2702231c trenable....'.#. + 100e0: 085f7365 745f696e 7472656e 61626c65 ._set_intrenable + 100f0: 0000000c 30022320 085f6765 745f696e ....0.# ._get_in + 10100: 74727065 6e64696e 67000000 0c270223 trpending....'.# + 10110: 24085f75 6e626c6f 636b5f61 6c6c5f69 $._unblock_all_i + 10120: 6e74726c 766c0000 00011102 23280011 ntrlvl......#(.. + 10130: 0400000d 76087469 6d656f75 74000000 ....v.timeout... + 10140: 01b50223 00086163 74696f6e 00000001 ...#..action.... + 10150: b5022300 00120800 000d9108 636d6400 ..#.........cmd. + 10160: 000001b5 02230013 00000d50 02230400 .....#.....P.#.. + 10170: 09545f57 44545f43 4d440000 000d7602 .T_WDT_CMD....v. + 10180: 01030000 0da00400 14040000 0df60e45 ...............E + 10190: 4e554d5f 5744545f 424f4f54 00010e45 NUM_WDT_BOOT...E + 101a0: 4e554d5f 434f4c44 5f424f4f 5400020e NUM_COLD_BOOT... + 101b0: 454e554d 5f535553 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YPE_IO....adf_os + 15610: 5f726573 6f757263 655f7479 70655f74 _resource_type_t + 15620: 00000017 e6111800 00186c08 73746172 ..........l.star + 15630: 74000000 17d60223 0008656e 64000000 t......#..end... + 15640: 17d60223 08087479 70650000 00182202 ...#..type....". + 15650: 23100009 6164665f 6f735f70 63695f64 #...adf_os_pci_d + 15660: 65765f69 645f7400 00001753 03000018 ev_id_t....S.... + 15670: 6c040010 04000018 ab087063 69000000 l.........pci... + 15680: 18850223 00087261 77000000 04070223 ...#..raw......# + 15690: 00001010 000018ca 08706369 00000018 .........pci.... + 156a0: 6c022300 08726177 00000004 07022300 l.#..raw......#. + 156b0: 00096164 665f6472 765f6861 6e646c65 ..adf_drv_handle + 156c0: 5f740000 00040709 6164665f 6f735f72 _t......adf_os_r + 156d0: 65736f75 7263655f 74000000 183e0300 esource_t....>.. + 156e0: 0018e004 00096164 665f6f73 5f617474 ......adf_os_att + 156f0: 6163685f 64617461 5f740000 0018ab03 ach_data_t...... + 15700: 000018fe 04000300 00152a04 00095f5f ..........*...__ + 15710: 6164665f 6f735f64 65766963 655f7400 adf_os_device_t. + 15720: 0000191f 09616466 5f6f735f 64657669 .....adf_os_devi + 15730: 63655f74 00000019 26060000 18ca0103 ce_t....&....... + 15740: 00001952 04000201 03000019 5f040009 ...R........_... + 15750: 6164665f 6f735f70 6d5f7400 00000407 adf_os_pm_t..... + 15760: 02010300 00197904 00130400 0019b90d ......y......... + 15770: 4144465f 4f535f42 55535f54 5950455f ADF_OS_BUS_TYPE_ + 15780: 50434900 010d4144 465f4f53 5f425553 PCI...ADF_OS_BUS + 15790: 5f545950 455f4745 4e455249 43000200 _TYPE_GENERIC... + 157a0: 09616466 5f6f735f 6275735f 74797065 .adf_os_bus_type + 157b0: 5f740000 00198209 6164665f 6f735f62 _t......adf_os_b + 157c0: 75735f72 65675f64 6174615f 74000000 us_reg_data_t... + 157d0: 188c0300 00031f04 00075f61 64665f64 .........._adf_d + 157e0: 72765f69 6e666f00 2000001a 96086472 rv_info. .....dr + 157f0: 765f6174 74616368 00000019 58022300 v_attach....X.#. + 15800: 08647276 5f646574 61636800 00001961 .drv_detach....a + 15810: 02230408 6472765f 73757370 656e6400 .#..drv_suspend. + 15820: 0000197b 02230808 6472765f 72657375 ...{.#..drv_resu + 15830: 6d650000 00196102 230c0862 75735f74 me....a.#..bus_t + 15840: 79706500 000019b9 02231008 6275735f ype......#..bus_ + 15850: 64617461 00000019 d0022314 086d6f64 data......#..mod + 15860: 5f6e616d 65000000 19eb0223 18086966 _name......#..if + 15870: 6e616d65 00000019 eb02231c 00096164 name......#...ad + 15880: 665f6f73 5f68616e 646c655f 74000000 f_os_handle_t... + 15890: 04070300 0016c104 00020102 01095f5f ..............__ + 158a0: 6164665f 6f735f73 697a655f 74000000 adf_os_size_t... + 158b0: 040a1304 00001ae5 0d415f46 414c5345 .........A_FALSE + 158c0: 00000d41 5f545255 45000100 09615f62 ...A_TRUE....a_b + 158d0: 6f6f6c5f 74000000 1acb0300 00155304 ool_t.........S. + 158e0: 00095f5f 6164665f 6f735f64 6d615f6d ..__adf_os_dma_m + 158f0: 61705f74 0000001a f302010c 6164665f ap_t........adf_ + 15900: 6f735f63 61636865 5f73796e 63000400 os_cache_sync... + 15910: 001b7d0d 4144465f 53594e43 5f505245 ..}.ADF_SYNC_PRE + 15920: 52454144 00000d41 44465f53 594e435f READ...ADF_SYNC_ + 15930: 50524557 52495445 00020d41 44465f53 PREWRITE...ADF_S + 15940: 594e435f 504f5354 52454144 00010d41 YNC_POSTREAD...A + 15950: 44465f53 594e435f 504f5354 57524954 DF_SYNC_POSTWRIT + 15960: 45000300 09616466 5f6f735f 63616368 E....adf_os_cach + 15970: 655f7379 6e635f74 0000001b 14020109 e_sync_t........ + 15980: 6164665f 6f735f73 697a655f 74000000 adf_os_size_t... + 15990: 1ab60600 001b9801 09616466 5f6f735f .........adf_os_ + 159a0: 646d615f 6d61705f 74000000 1afa0300 dma_map_t....... + 159b0: 001bb104 00060000 04070103 00001afa ................ + 159c0: 04000600 00040701 02010600 0015e601 ................ + 159d0: 02010473 686f7274 20696e74 00050209 ...short int.... + 159e0: 415f494e 54313600 00001beb 095f5f61 A_INT16......__a + 159f0: 5f696e74 31365f74 0000001b f809615f _int16_t......a_ + 15a00: 696e7431 365f7400 00001c05 04736967 int16_t......sig + 15a10: 6e656420 63686172 00050109 415f494e ned char....A_IN + 15a20: 54380000 001c2509 5f5f615f 696e7438 T8....%.__a_int8 + 15a30: 5f740000 001c3409 615f696e 74385f74 _t....4.a_int8_t + 15a40: 0000001c 40110c00 001cb708 73757070 ....@.......supp + 15a50: 6f727465 64000000 166b0223 00086164 orted....k.#..ad + 15a60: 76657274 697a6564 00000016 6b022304 vertized....k.#. + 15a70: 08737065 65640000 001c1602 23080864 .speed......#..d + 15a80: 75706c65 78000000 1c500223 0a086175 uplex....P.#..au + 15a90: 746f6e65 67000000 16d20223 0b000e00 toneg......#.... + 15aa0: 0016d206 00001cc4 0f050007 6164665f ............adf_ + 15ab0: 6e65745f 65746861 64647200 0600001c net_ethaddr..... + 15ac0: e8086164 64720000 001cb702 23000009 ..addr......#... + 15ad0: 5f5f615f 75696e74 31365f74 00000013 __a_uint16_t.... + 15ae0: 4009615f 75696e74 31365f74 0000001c @.a_uint16_t.... + 15af0: e8110e00 001d4c08 65746865 725f6468 ......L.ether_dh + 15b00: 6f737400 00001cb7 02230008 65746865 ost......#..ethe + 15b10: 725f7368 6f737400 00001cb7 02230608 r_shost......#.. + 15b20: 65746865 725f7479 70650000 001cfa02 ether_type...... + 15b30: 230c0011 1400001e 0d146970 5f766572 #.........ip_ver + 15b40: 73696f6e 00000016 d2010004 02230014 sion.........#.. + 15b50: 69705f68 6c000000 16d20104 04022300 ip_hl.........#. + 15b60: 0869705f 746f7300 000016d2 02230108 .ip_tos......#.. + 15b70: 69705f6c 656e0000 001cfa02 23020869 ip_len......#..i + 15b80: 705f6964 0000001c fa022304 0869705f p_id......#..ip_ + 15b90: 66726167 5f6f6666 0000001c fa022306 frag_off......#. + 15ba0: 0869705f 74746c00 000016d2 02230808 .ip_ttl......#.. + 15bb0: 69705f70 726f746f 00000016 d2022309 ip_proto......#. + 15bc0: 0869705f 63686563 6b000000 1cfa0223 .ip_check......# + 15bd0: 0a086970 5f736164 64720000 00166b02 ..ip_saddr....k. + 15be0: 230c0869 705f6461 64647200 0000166b #..ip_daddr....k + 15bf0: 02231000 07616466 5f6e6574 5f766c61 .#...adf_net_vla + 15c00: 6e686472 00040000 1e5f0874 70696400 nhdr....._.tpid. + 15c10: 00001cfa 02230014 7072696f 00000016 .....#..prio.... + 15c20: d2010003 02230214 63666900 000016d2 .....#..cfi..... + 15c30: 01030102 23021476 69640000 001cfa02 ....#..vid...... + 15c40: 040c0223 02000761 64665f6e 65745f76 ...#...adf_net_v + 15c50: 69640002 00001e90 14726573 00000016 id.......res.... + 15c60: d2010004 02230014 76616c00 00001cfa .....#..val..... + 15c70: 02040c02 23000011 0c00001e cc087278 ....#.........rx + 15c80: 5f627566 73697a65 00000016 6b022300 _bufsize....k.#. + 15c90: 0872785f 6e646573 63000000 166b0223 .rx_ndesc....k.# + 15ca0: 04087478 5f6e6465 73630000 00166b02 ..tx_ndesc....k. + 15cb0: 23080011 0800001e f208706f 6c6c6564 #.........polled + 15cc0: 0000001a e5022300 08706f6c 6c5f7774 ......#..poll_wt + 15cd0: 00000016 6b022304 000e0000 16d24000 ....k.#.......@. + 15ce0: 001eff0f 3f001146 00001f27 0869665f ....?..F...'.if_ + 15cf0: 6e616d65 0000001e f2022300 08646576 name......#..dev + 15d00: 5f616464 72000000 1cb70223 40001304 _addr......#@... + 15d10: 00001f5e 0d414446 5f4f535f 444d415f ...^.ADF_OS_DMA_ + 15d20: 4d41534b 5f333242 49540000 0d414446 MASK_32BIT...ADF + 15d30: 5f4f535f 444d415f 4d41534b 5f363442 _OS_DMA_MASK_64B + 15d40: 49540001 00096164 665f6f73 5f646d61 IT....adf_os_dma + 15d50: 5f6d6173 6b5f7400 00001f27 07616466 _mask_t....'.adf + 15d60: 5f646d61 5f696e66 6f000800 001fab08 _dma_info....... + 15d70: 646d615f 6d61736b 0000001f 5e022300 dma_mask....^.#. + 15d80: 0873675f 6e736567 73000000 166b0223 .sg_nsegs....k.# + 15d90: 04001304 00002001 0d414446 5f4e4554 ...... ..ADF_NET + 15da0: 5f434b53 554d5f4e 4f4e4500 000d4144 _CKSUM_NONE...AD + 15db0: 465f4e45 545f434b 53554d5f 5443505f F_NET_CKSUM_TCP_ + 15dc0: 5544505f 49507634 00010d41 44465f4e UDP_IPv4...ADF_N + 15dd0: 45545f43 4b53554d 5f544350 5f554450 ET_CKSUM_TCP_UDP + 15de0: 5f495076 36000200 09616466 5f6e6574 _IPv6....adf_net + 15df0: 5f636b73 756d5f74 7970655f 74000000 _cksum_type_t... + 15e00: 1fab1108 00002044 0874785f 636b7375 ...... D.tx_cksu + 15e10: 6d000000 20010223 00087278 5f636b73 m... ..#..rx_cks + 15e20: 756d0000 00200102 23040009 6164665f um... ..#...adf_ + 15e30: 6e65745f 636b7375 6d5f696e 666f5f74 net_cksum_info_t + 15e40: 00000020 1b130400 00209d0d 4144465f ... ..... ..ADF_ + 15e50: 4e45545f 54534f5f 4e4f4e45 00000d41 NET_TSO_NONE...A + 15e60: 44465f4e 45545f54 534f5f49 50563400 DF_NET_TSO_IPV4. + 15e70: 010d4144 465f4e45 545f5453 4f5f414c ..ADF_NET_TSO_AL + 15e80: 4c000200 09616466 5f6e6574 5f74736f L....adf_net_tso + 15e90: 5f747970 655f7400 0000205e 11100000 _type_t... ^.... + 15ea0: 20f10863 6b73756d 5f636170 00000020 ..cksum_cap... + 15eb0: 44022300 0874736f 00000020 9d022308 D.#..tso... ..#. + 15ec0: 08766c61 6e5f7375 70706f72 74656400 .vlan_supported. + 15ed0: 000016d2 02230c00 11200000 218a0874 .....#... ..!..t + 15ee0: 785f7061 636b6574 73000000 166b0223 x_packets....k.# + 15ef0: 00087278 5f706163 6b657473 00000016 ..rx_packets.... + 15f00: 6b022304 0874785f 62797465 73000000 k.#..tx_bytes... + 15f10: 166b0223 08087278 5f627974 65730000 .k.#..rx_bytes.. + 15f20: 00166b02 230c0874 785f6472 6f707065 ..k.#..tx_droppe + 15f30: 64000000 166b0223 10087278 5f64726f d....k.#..rx_dro + 15f40: 70706564 00000016 6b022314 0872785f pped....k.#..rx_ + 15f50: 6572726f 72730000 00166b02 23180874 errors....k.#..t + 15f60: 785f6572 726f7273 00000016 6b02231c x_errors....k.#. + 15f70: 00096164 665f6e65 745f6574 68616464 ..adf_net_ethadd + 15f80: 725f7400 00001cc4 15000021 8a030000 r_t........!.... + 15f90: 0021af0f 7f001661 64665f6e 65745f63 .!.....adf_net_c + 15fa0: 6d645f6d 63616464 72000304 000021e6 md_mcaddr.....!. + 15fb0: 086e656c 656d0000 00166b02 2300086d .nelem....k.#..m + 15fc0: 63617374 00000021 a1022304 00096164 cast...!..#...ad + 15fd0: 665f6e65 745f636d 645f6c69 6e6b5f69 f_net_cmd_link_i + 15fe0: 6e666f5f 74000000 1c5e0961 64665f6e nfo_t....^.adf_n + 15ff0: 65745f63 6d645f70 6f6c6c5f 696e666f et_cmd_poll_info + 16000: 5f740000 001ecc09 6164665f 6e65745f _t......adf_net_ + 16010: 636d645f 636b7375 6d5f696e 666f5f74 cmd_cksum_info_t + 16020: 00000020 44096164 665f6e65 745f636d ... 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.BUF_POOL_ID...6 + 17530: c4020103 0000374a 04000600 00269701 ......7J.....&.. + 17540: 03000037 53040006 00002697 01030000 ...7S.....&..... + 17550: 37600400 02010300 00376d04 00076275 7`.......7m...bu + 17560: 665f706f 6f6c5f61 7069001c 0000380f f_pool_api....8. + 17570: 085f696e 69740000 0036b402 2300085f ._init...6..#.._ + 17580: 73687574 646f776e 00000036 bd022304 shutdown...6..#. + 17590: 085f6372 65617465 5f706f6f 6c000000 ._create_pool... + 175a0: 374c0223 08085f61 6c6c6f63 5f627566 7L.#.._alloc_buf + 175b0: 00000037 5902230c 085f616c 6c6f635f ...7Y.#.._alloc_ + 175c0: 6275665f 616c6967 6e000000 37660223 buf_align...7f.# + 175d0: 10085f66 7265655f 62756600 0000376f .._free_buf...7o + 175e0: 02231408 70526573 65727665 64000000 .#..pReserved... + 175f0: 04070223 1800075f 4854435f 53455256 ...#..._HTC_SERV + 17600: 49434500 1c000038 ee08704e 65787400 ICE....8..pNext. + 17610: 000038ee 02230008 50726f63 65737352 ..8..#..ProcessR + 17620: 6563764d 73670000 0039a302 23040850 ecvMsg...9..#..P + 17630: 726f6365 73735365 6e644275 66666572 rocessSendBuffer + 17640: 436f6d70 6c657465 00000039 ac022308 Complete...9..#. + 17650: 0850726f 63657373 436f6e6e 65637400 .ProcessConnect. + 17660: 000039c0 02230c08 53657276 69636549 ..9..#..ServiceI + 17670: 44000000 13400223 10085365 72766963 D....@.#..Servic + 17680: 65466c61 67730000 00134002 2312084d eFlags....@.#..M + 17690: 61785376 634d7367 53697a65 00000013 axSvcMsgSize.... + 176a0: 40022314 08547261 696c6572 53706343 @.#..TrailerSpcC + 176b0: 6865636b 4c696d69 74000000 13400223 heckLimit....@.# + 176c0: 16085365 72766963 65437478 00000004 ..ServiceCtx.... + 176d0: 07022318 00030000 380f0400 13040000 ..#.....8....... + 176e0: 398c1845 4e44504f 494e545f 554e5553 9..ENDPOINT_UNUS + 176f0: 454400ff ffffff0d 454e4450 4f494e54 ED......ENDPOINT + 17700: 3000000d 454e4450 4f494e54 3100010d 0...ENDPOINT1... + 17710: 454e4450 4f494e54 3200020d 454e4450 ENDPOINT2...ENDP + 17720: 4f494e54 3300030d 454e4450 4f494e54 OINT3...ENDPOINT + 17730: 3400040d 454e4450 4f494e54 3500050d 4...ENDPOINT5... + 17740: 454e4450 4f494e54 3600060d 454e4450 ENDPOINT6...ENDP + 17750: 4f494e54 3700070d 454e4450 4f494e54 OINT7...ENDPOINT + 17760: 3800080d 454e4450 4f494e54 5f4d4158 8...ENDPOINT_MAX + 17770: 00160009 4854435f 454e4450 4f494e54 ....HTC_ENDPOINT + 17780: 5f494400 000038f5 02010300 0039a104 _ID...8......9.. + 17790: 00020103 000039aa 04000300 00011204 ......9......... + 177a0: 00060000 132c0103 000039ba 04000300 .....,....9..... + 177b0: 00380f04 00075f48 54435f43 4f4e4649 .8...._HTC_CONFI + 177c0: 47001400 003a3f08 43726564 69745369 G....:?.CreditSi + 177d0: 7a650000 00011202 23000843 72656469 ze......#..Credi + 177e0: 744e756d 62657200 00000112 02230408 tNumber......#.. + 177f0: 4f534861 6e646c65 0000001a 96022308 OSHandle......#. + 17800: 08484946 48616e64 6c650000 0028ff02 .HIFHandle...(.. + 17810: 230c0850 6f6f6c48 616e646c 65000000 #..PoolHandle... + 17820: 369b0223 1000075f 4854435f 4255465f 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essMsg...9..#(._ + 17a30: 4854435f 436f6e74 726f6c53 76635072 HTC_ControlSvcPr + 17a40: 6f636573 7353656e 64436f6d 706c6574 ocessSendComplet + 17a50: 65000000 39ac0223 2c087052 65736572 e...9..#,.pReser + 17a60: 76656400 00000407 02233000 07686f73 ved......#0..hos + 17a70: 745f6170 705f6172 65615f73 00040000 t_app_area_s.... + 17a80: 3cb50877 6d695f70 726f746f 636f6c5f <..wmi_protocol_ + 17a90: 76657200 0000166b 02230000 110e0000 ver....k.#...... + 17aa0: 3cec0864 73744d61 63000000 1cb70223 <..dstMac......# + 17ab0: 00087372 634d6163 0000001c b7022306 ..srcMac......#. + 17ac0: 08747970 654f724c 656e0000 001cfa02 .typeOrLen...... + 17ad0: 230c000e 000016d2 0300003c f90f0200 #..........<.... + 17ae0: 11080000 3d490864 73617000 000016d2 ....=I.dsap..... + 17af0: 02230008 73736170 00000016 d2022301 .#..ssap......#. + 17b00: 08636e74 6c000000 16d20223 02086f72 .cntl......#..or + 17b10: 67436f64 65000000 3cec0223 03086574 gCode...<..#..et + 17b20: 68657254 79706500 00001cfa 02230600 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D....@.#..Flags. + 17d30: 00001340 02230600 075f574d 495f4449 ...@.#..._WMI_DI + 17d40: 53504154 43485f54 41424c45 00100000 SPATCH_TABLE.... + 17d50: 3fb20870 4e657874 0000003f b2022300 ?..pNext...?..#. + 17d60: 0870436f 6e746578 74000000 04070223 .pContext......# + 17d70: 04084e75 6d626572 4f66456e 74726965 ..NumberOfEntrie + 17d80: 73000000 01120223 08087054 61626c65 s......#..pTable + 17d90: 0000003f d102230c 00030000 3f510400 ...?..#.....?Q.. + 17da0: 09574d49 5f444953 50415443 485f454e .WMI_DISPATCH_EN + 17db0: 54525900 00003f06 0300003f b9040003 TRY...?....?.... + 17dc0: 00003f51 04000948 54435f42 55465f43 ..?Q...HTC_BUF_C + 17dd0: 4f4e5445 58540000 003a3f0c 574d495f ONTEXT...:?.WMI_ + 17de0: 4556545f 434c4153 53000400 00406918 EVT_CLASS....@i. + 17df0: 574d495f 4556545f 434c4153 535f4e4f WMI_EVT_CLASS_NO + 17e00: 4e4500ff ffffff0d 574d495f 4556545f NE......WMI_EVT_ + 17e10: 434c4153 535f434d 445f4556 454e5400 CLASS_CMD_EVENT. + 17e20: 000d574d 495f4556 545f434c 4153535f ..WMI_EVT_CLASS_ + 17e30: 434d445f 5245504c 5900010d 574d495f CMD_REPLY...WMI_ + 17e40: 4556545f 434c4153 535f4d41 58000200 EVT_CLASS_MAX... + 17e50: 09574d49 5f455654 5f434c41 53530000 .WMI_EVT_CLASS.. + 17e60: 003ff407 5f574d49 5f425546 5f434f4e .?.._WMI_BUF_CON + 17e70: 54455854 000c0000 40c70848 74634275 TEXT....@..HtcBu + 17e80: 66437478 0000003f df022300 08457665 fCtx...?..#..Eve + 17e90: 6e74436c 61737300 00004069 02230408 ntClass...@i.#.. + 17ea0: 466c6167 73000000 13400223 08000977 Flags....@.#...w + 17eb0: 6d695f68 616e646c 655f7400 00000407 mi_handle_t..... + 17ec0: 09574d49 5f535643 5f434f4e 46494700 .WMI_SVC_CONFIG. + 17ed0: 00003e7f 03000040 d9040006 000040c7 ..>....@......@. + 17ee0: 01030000 40f40400 09574d49 5f444953 ....@....WMI_DIS + 17ef0: 50415443 485f5441 424c4500 00003f51 PATCH_TABLE...?Q + 17f00: 03000041 01040002 01030000 41200400 ...A........A .. + 17f10: 06000026 97010300 00412904 00020103 ...&.....A)..... + 17f20: 00004136 04000600 00011201 03000041 ..A6...........A + 17f30: 3f040002 01030000 414c0400 06000013 ?.......AL...... + 17f40: 2c010300 00415504 00075f77 6d695f73 ,....AU..._wmi_s + 17f50: 76635f61 70697300 2c000042 9d085f57 vc_apis.,..B.._W + 17f60: 4d495f49 6e697400 000040fa 02230008 MI_Init...@..#.. + 17f70: 5f574d49 5f526567 69737465 72446973 _WMI_RegisterDis + 17f80: 70617463 68546162 6c650000 00412202 patchTable...A". + 17f90: 2304085f 574d495f 416c6c6f 63457665 #.._WMI_AllocEve + 17fa0: 6e740000 00412f02 2308085f 574d495f nt...A/.#.._WMI_ + 17fb0: 53656e64 4576656e 74000000 41380223 SendEvent...A8.# + 17fc0: 0c085f57 4d495f47 65745065 6e64696e .._WMI_GetPendin + 17fd0: 67457665 6e747343 6f756e74 00000041 gEventsCount...A + 17fe0: 45022310 085f574d 495f5365 6e64436f E.#.._WMI_SendCo + 17ff0: 6d706c65 74654861 6e646c65 72000000 mpleteHandler... + 18000: 39ac0223 14085f57 4d495f47 6574436f 9..#.._WMI_GetCo + 18010: 6e74726f 6c457000 00004145 02231808 ntrolEp...AE.#.. + 18020: 5f574d49 5f536875 74646f77 6e000000 _WMI_Shutdown... + 18030: 414e0223 1c085f57 4d495f52 6563764d AN.#.._WMI_RecvM + 18040: 65737361 67654861 6e646c65 72000000 essageHandler... + 18050: 39a30223 20085f57 4d495f53 65727669 9..# ._WMI_Servi + 18060: 6365436f 6e6e6563 74000000 415b0223 ceConnect...A[.# + 18070: 24087052 65736572 76656400 00000407 $.pReserved..... + 18080: 02232800 077a7344 6d614465 73630014 .#(..zsDmaDesc.. + 18090: 0000431f 08637472 6c000000 01760223 ..C..ctrl....v.# + 180a0: 00087374 61747573 00000001 76022302 ..status....v.#. + 180b0: 08746f74 616c4c65 6e000000 01760223 .totalLen....v.# + 180c0: 04086461 74615369 7a650000 00017602 ..dataSize....v. + 180d0: 2306086c 61737441 64647200 0000431f #..lastAddr...C. + 180e0: 02230808 64617461 41646472 00000001 .#..dataAddr.... + 180f0: 9a02230c 086e6578 74416464 72000000 ..#..nextAddr... + 18100: 431f0223 10000300 00429d04 00030000 C..#.....B...... + 18110: 429d0400 077a7344 6d615175 65756500 B....zsDmaQueue. + 18120: 08000043 5f086865 61640000 00432602 ...C_.head...C&. + 18130: 23000874 65726d69 6e61746f 72000000 #..terminator... + 18140: 43260223 0400077a 73547844 6d615175 C&.#...zsTxDmaQu + 18150: 65756500 10000043 c3086865 61640000 eue....C..head.. + 18160: 00432602 23000874 65726d69 6e61746f .C&.#..terminato + 18170: 72000000 43260223 0408786d 69746564 r...C&.#..xmited + 18180: 5f627566 5f686561 64000000 148b0223 _buf_head......# + 18190: 0808786d 69746564 5f627566 5f746169 ..xmited_buf_tai + 181a0: 6c000000 148b0223 0c000201 03000043 l......#.......C + 181b0: c3040003 0000432d 04000201 03000043 ......C-.......C + 181c0: d3040003 0000435f 04000201 03000043 ......C_.......C + 181d0: e3040002 01030000 43ec0400 02010300 ........C....... + 181e0: 0043f504 00060000 148b0103 000043fe .C............C. + 181f0: 04000201 03000044 0b040006 0000148b .......D........ + 18200: 01030000 44140400 02010300 00442104 ....D........D!. + 18210: 00060000 01120103 0000442a 04000600 ..........D*.... + 18220: 00432601 03000044 37040002 01030000 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.htc...;..#...wm + 18430: 695f7376 635f6170 69000000 45dc0323 i_svc_api...E..# + 18440: ac040875 73626669 666f5f61 70690000 ...usbfifo_api.. + 18450: 0032cd03 23d80408 6275665f 706f6f6c .2..#...buf_pool + 18460: 00000037 760323e4 04087662 75660000 ...7v.#...vbuf.. + 18470: 0014b503 23800508 76646573 63000000 ....#...vdesc... + 18480: 13970323 94050861 6c6c6f63 72616d00 ...#...allocram. + 18490: 0000098d 0323a805 08646d61 5f656e67 .....#...dma_eng + 184a0: 696e6500 0000444d 0323b405 08646d61 ine...DM.#...dma + 184b0: 5f6c6962 0000002c 360323f4 05086869 _lib...,6.#...hi + 184c0: 665f7063 69000000 2e960323 a8060009 f_pci......#.... + 184d0: 5f415f6d 61677069 655f696e 64697265 _A_magpie_indire + 184e0: 6374696f 6e5f7461 626c655f 74000000 ction_table_t... + 184f0: 45ee1110 0000473e 08613000 000001af E.....G>.a0..... + 18500: 02230008 61310000 0001af02 23040861 .#..a1......#..a + 18510: 32000000 01af0223 08086133 00000001 2......#..a3.... + 18520: af02230c 000e0000 470b5000 00474b0f ..#.....G.P..GK. + 18530: 04000758 54656e73 615f6578 63657074 ...XTensa_except + 18540: 696f6e5f 6672616d 655f7300 80000048 ion_frame_s....H + 18550: 2f087874 5f706300 000001af 02230008 /.xt_pc......#.. + 18560: 78745f70 73000000 01af0223 04087874 xt_ps......#..xt + 18570: 5f736172 00000001 af022308 0878745f _sar......#..xt_ + 18580: 76707269 00000001 af02230c 0878745f vpri......#..xt_ + 18590: 61320000 0001af02 23100878 745f6133 a2......#..xt_a3 + 185a0: 00000001 af022314 0878745f 61340000 ......#..xt_a4.. + 185b0: 0001af02 23180878 745f6135 00000001 ....#..xt_a5.... + 185c0: af02231c 0878745f 65786363 61757365 ..#..xt_exccause + 185d0: 00000001 af022320 0878745f 6c636f75 ......# .xt_lcou + 185e0: 6e740000 0001af02 23240878 745f6c62 nt......#$.xt_lb + 185f0: 65670000 0001af02 23280878 745f6c65 eg......#(.xt_le + 18600: 6e640000 0001af02 232c0877 62000000 nd......#,.wb... + 18610: 473e0223 30000943 50555f65 78636570 G>.#0..CPU_excep + 18620: 74696f6e 5f667261 6d655f74 00000047 tion_frame_t...G + 18630: 4b110800 00486d08 69737200 00000c59 K....Hm.isr....Y + 18640: 02230008 6973725f 61726700 00000407 .#..isr_arg..... + 18650: 02230400 0e000048 4a980000 487a0f12 .#.....HJ...Hz.. + 18660: 0019636d 6e6f735f 6973725f 696e666f ..cmnos_isr_info + 18670: 00000048 6d050300 50099001 19636d6e ...Hm...P....cmn + 18680: 6f735f65 6e61626c 65645f69 6e746572 os_enabled_inter + 18690: 72757074 73000000 01af0503 00500980 rupts........P.. + 186a0: 011a0000 01121a00 00011203 000048bf ..............H. + 186b0: 04000300 000c8504 0002011b 011e636d ..............cm + 186c0: 6e6f735f 696e7472 5f64756d 6d790000 nos_intr_dummy.. + 186d0: 0001af01 01039201 20029000 008e2120 ........ .....! + 186e0: 008e2125 00004911 1c011e70 5061726d ..!%..I....pParm + 186f0: 00000004 07015200 1d012a63 6d6e6f73 ......R...*cmnos + 18700: 5f696e74 725f696e 69740001 01039201 _intr_init...... + 18710: 20029000 008e2128 008e214e 00004941 .....!(..!N..IA + 18720: 1e690000 0001af00 1d013c63 6d6e6f73 .i..........tupleNumL. + 1c6b0: 00001ca3 02230008 7475706c 654e756d .....#..tupleNum + 1c6c0: 48000000 1ca30223 02086176 74000000 H......#..avt... + 1c6d0: 3dc20223 04001201 00003e28 08626561 =..#......>(.bea + 1c6e0: 636f6e50 656e6469 6e67436f 756e7400 conPendingCount. + 1c6f0: 0000167b 02230000 075f574d 495f5356 ...{.#..._WMI_SV + 1c700: 435f434f 4e464947 00100000 3e910848 C_CONFIG....>..H + 1c710: 74634861 6e646c65 0000003a 24022300 tcHandle...:$.#. + 1c720: 08506f6f 6c48616e 646c6500 00003644 .PoolHandle...6D + 1c730: 02230408 4d617843 6d645265 706c7945 .#..MaxCmdReplyE + 1c740: 76747300 0000010f 02230808 4d617845 vts......#..MaxE + 1c750: 76656e74 45767473 00000001 0f02230c ventEvts......#. + 1c760: 00020103 00003e91 04000957 4d495f43 ......>....WMI_C + 1c770: 4d445f48 414e444c 45520000 003e9307 MD_HANDLER...>.. + 1c780: 5f574d49 5f444953 50415443 485f454e _WMI_DISPATCH_EN + 1c790: 54525900 0800003e fa087043 6d644861 TRY....>..pCmdHa + 1c7a0: 6e646c65 72000000 3e9a0223 0008436d ndler...>..#..Cm + 1c7b0: 64494400 000012e9 02230408 466c6167 dID......#..Flag + 1c7c0: 73000000 12e90223 0600075f 574d495f s......#..._WMI_ + 1c7d0: 44495350 41544348 5f544142 4c450010 DISPATCH_TABLE.. + 1c7e0: 00003f5b 08704e65 78740000 003f5b02 ..?[.pNext...?[. + 1c7f0: 23000870 436f6e74 65787400 00000404 #..pContext..... + 1c800: 02230408 4e756d62 65724f66 456e7472 .#..NumberOfEntr + 1c810: 69657300 0000010f 02230808 70546162 ies......#..pTab + 1c820: 6c650000 003f7a02 230c0003 00003efa le...?z.#.....>. + 1c830: 04000957 4d495f44 49535041 5443485f ...WMI_DISPATCH_ + 1c840: 454e5452 59000000 3eaf0300 003f6204 ENTRY...>....?b. + 1c850: 00030000 3efa0400 09485443 5f425546 ....>....HTC_BUF + 1c860: 5f434f4e 54455854 00000039 e80d574d _CONTEXT...9..WM + 1c870: 495f4556 545f434c 41535300 04000040 I_EVT_CLASS....@ + 1c880: 1219574d 495f4556 545f434c 4153535f ..WMI_EVT_CLASS_ + 1c890: 4e4f4e45 00ffffff ff0e574d 495f4556 NONE......WMI_EV + 1c8a0: 545f434c 4153535f 434d445f 4556454e T_CLASS_CMD_EVEN + 1c8b0: 5400000e 574d495f 4556545f 434c4153 T...WMI_EVT_CLAS + 1c8c0: 535f434d 445f5245 504c5900 010e574d S_CMD_REPLY...WM + 1c8d0: 495f4556 545f434c 4153535f 4d415800 I_EVT_CLASS_MAX. + 1c8e0: 02000957 4d495f45 56545f43 4c415353 ...WMI_EVT_CLASS + 1c8f0: 0000003f 9d075f57 4d495f42 55465f43 ...?.._WMI_BUF_C + 1c900: 4f4e5445 5854000c 00004070 08487463 ONTEXT....@p.Htc + 1c910: 42756643 74780000 003f8802 23000845 BufCtx...?..#..E + 1c920: 76656e74 436c6173 73000000 40120223 ventClass...@..# + 1c930: 0408466c 61677300 000012e9 02230800 ..Flags......#.. + 1c940: 09776d69 5f68616e 646c655f 74000000 .wmi_handle_t... + 1c950: 04040957 4d495f53 56435f43 4f4e4649 ...WMI_SVC_CONFI + 1c960: 47000000 3e280300 00408204 00060000 G...>(...@...... + 1c970: 40700103 0000409d 04000957 4d495f44 @p....@....WMI_D + 1c980: 49535041 5443485f 5441424c 45000000 ISPATCH_TABLE... + 1c990: 3efa0300 0040aa04 00020103 000040c9 >....@........@. + 1c9a0: 04000600 00264001 03000040 d2040002 .....&@....@.... + 1c9b0: 01030000 40df0400 06000001 0f010300 ....@........... + 1c9c0: 0040e804 00020103 000040f5 04000600 .@........@..... + 1c9d0: 0012d501 03000040 fe040007 5f776d69 .......@...._wmi + 1c9e0: 5f737663 5f617069 73002c00 00424608 _svc_apis.,..BF. + 1c9f0: 5f574d49 5f496e69 74000000 40a30223 _WMI_Init...@..# + 1ca00: 00085f57 4d495f52 65676973 74657244 .._WMI_RegisterD + 1ca10: 69737061 74636854 61626c65 00000040 ispatchTable...@ + 1ca20: cb022304 085f574d 495f416c 6c6f6345 ..#.._WMI_AllocE + 1ca30: 76656e74 00000040 d8022308 085f574d vent...@..#.._WM + 1ca40: 495f5365 6e644576 656e7400 000040e1 I_SendEvent...@. + 1ca50: 02230c08 5f574d49 5f476574 50656e64 .#.._WMI_GetPend + 1ca60: 696e6745 76656e74 73436f75 6e740000 ingEventsCount.. + 1ca70: 0040ee02 2310085f 574d495f 53656e64 .@..#.._WMI_Send + 1ca80: 436f6d70 6c657465 48616e64 6c657200 CompleteHandler. + 1ca90: 00003955 02231408 5f574d49 5f476574 ..9U.#.._WMI_Get + 1caa0: 436f6e74 726f6c45 70000000 40ee0223 ControlEp...@..# + 1cab0: 18085f57 4d495f53 68757464 6f776e00 .._WMI_Shutdown. + 1cac0: 000040f7 02231c08 5f574d49 5f526563 ..@..#.._WMI_Rec + 1cad0: 764d6573 73616765 48616e64 6c657200 vMessageHandler. + 1cae0: 0000394c 02232008 5f574d49 5f536572 ..9L.# ._WMI_Ser + 1caf0: 76696365 436f6e6e 65637400 00004104 viceConnect...A. + 1cb00: 02232408 70526573 65727665 64000000 .#$.pReserved... + 1cb10: 04040223 2800077a 73446d61 44657363 ...#(..zsDmaDesc + 1cb20: 00140000 42c80863 74726c00 00000173 ....B..ctrl....s + 1cb30: 02230008 73746174 75730000 00017302 .#..status....s. + 1cb40: 23020874 6f74616c 4c656e00 00000173 #..totalLen....s + 1cb50: 02230408 64617461 53697a65 00000001 .#..dataSize.... + 1cb60: 73022306 086c6173 74416464 72000000 s.#..lastAddr... + 1cb70: 42c80223 08086461 74614164 64720000 B..#..dataAddr.. + 1cb80: 00019702 230c086e 65787441 64647200 ....#..nextAddr. + 1cb90: 000042c8 02231000 03000042 46040003 ..B..#.....BF... + 1cba0: 00004246 0400077a 73446d61 51756575 ..BF...zsDmaQueu + 1cbb0: 65000800 00430808 68656164 00000042 e....C..head...B + 1cbc0: cf022300 08746572 6d696e61 746f7200 ..#..terminator. + 1cbd0: 000042cf 02230400 077a7354 78446d61 ..B..#...zsTxDma + 1cbe0: 51756575 65001000 00436c08 68656164 Queue....Cl.head + 1cbf0: 00000042 cf022300 08746572 6d696e61 ...B..#..termina + 1cc00: 746f7200 000042cf 02230408 786d6974 tor...B..#..xmit + 1cc10: 65645f62 75665f68 65616400 00001434 ed_buf_head....4 + 1cc20: 02230808 786d6974 65645f62 75665f74 .#..xmited_buf_t + 1cc30: 61696c00 00001434 02230c00 02010300 ail....4.#...... + 1cc40: 00436c04 00030000 42d60400 02010300 .Cl.....B....... + 1cc50: 00437c04 00030000 43080400 02010300 .C|.....C....... + 1cc60: 00438c04 00020103 00004395 04000201 .C........C..... + 1cc70: 03000043 9e040006 00001434 01030000 ...C.......4.... + 1cc80: 43a70400 02010300 0043b404 00060000 C........C...... + 1cc90: 14340103 000043bd 04000201 03000043 .4....C........C + 1cca0: ca040006 0000010f 01030000 43d30400 ............C... + 1ccb0: 06000042 cf010300 0043e004 00020103 ...B.....C...... + 1ccc0: 000043ed 04000764 6d615f65 6e67696e ..C....dma_engin + 1ccd0: 655f6170 69004000 00456308 5f696e69 e_api.@..Ec._ini + 1cce0: 74000000 436e0223 00085f69 6e69745f t...Cn.#.._init_ + 1ccf0: 72785f71 75657565 00000043 7e022304 rx_queue...C~.#. + 1cd00: 085f696e 69745f74 785f7175 65756500 ._init_tx_queue. + 1cd10: 0000438e 02230808 5f636f6e 6669675f ..C..#.._config_ + 1cd20: 72785f71 75657565 00000043 9702230c rx_queue...C..#. + 1cd30: 085f786d 69745f62 75660000 0043a002 ._xmit_buf...C.. + 1cd40: 2310085f 666c7573 685f786d 69740000 #.._flush_xmit.. + 1cd50: 00437e02 2314085f 72656170 5f726563 .C~.#.._reap_rec + 1cd60: 765f6275 66000000 43ad0223 18085f72 v_buf...C..#.._r + 1cd70: 65747572 6e5f7265 63765f62 75660000 eturn_recv_buf.. + 1cd80: 0043b602 231c085f 72656170 5f786d69 .C..#.._reap_xmi + 1cd90: 7465645f 62756600 000043c3 02232008 ted_buf...C..# . + 1cda0: 5f737761 705f6461 74610000 0043cc02 _swap_data...C.. + 1cdb0: 2324085f 6861735f 636f6d70 6c5f7061 #$._has_compl_pa + 1cdc0: 636b6574 73000000 43d90223 28085f64 ckets...C..#(._d + 1cdd0: 6573635f 64756d70 00000043 7e02232c esc_dump...C~.#, + 1cde0: 085f6765 745f7061 636b6574 00000043 ._get_packet...C + 1cdf0: e6022330 085f7265 636c6169 6d5f7061 ..#0._reclaim_pa + 1ce00: 636b6574 00000043 ef022334 085f7075 cket...C..#4._pu + 1ce10: 745f7061 636b6574 00000043 ef022338 t_packet...C..#8 + 1ce20: 08705265 73657276 65640000 00040402 .pReserved...... + 1ce30: 233c0009 5f415f63 6d6e6f73 5f696e64 #<.._A_cmnos_ind + 1ce40: 69726563 74696f6e 5f746162 6c655f74 irection_table_t + 1ce50: 00000030 a209574d 495f5356 435f4150 ...0..WMI_SVC_AP + 1ce60: 49530000 00410b17 5f415f6d 61677069 IS...A.._A_magpi + 1ce70: 655f696e 64697265 6374696f 6e5f7461 e_indirection_ta + 1ce80: 626c6500 034c0000 46910863 6d6e6f73 ble..L..F..cmnos + 1ce90: 00000045 63022300 08646267 00000003 ...Ec.#..dbg.... + 1cea0: d10323b8 03086869 66000000 294b0323 ..#...hif...)K.# + 1ceb0: c0030868 74630000 003abe03 23f80308 ...htc...:..#... + 1cec0: 776d695f 7376635f 61706900 00004585 wmi_svc_api...E. + 1ced0: 0323ac04 08757362 6669666f 5f617069 .#...usbfifo_api + 1cee0: 00000032 760323d8 04086275 665f706f ...2v.#...buf_po + 1cef0: 6f6c0000 00371f03 23e40408 76627566 ol...7..#...vbuf + 1cf00: 00000014 5e032380 05087664 65736300 ....^.#...vdesc. + 1cf10: 00001340 03239405 08616c6c 6f637261 ...@.#...allocra + 1cf20: 6d000000 09360323 a8050864 6d615f65 m....6.#...dma_e + 1cf30: 6e67696e 65000000 43f60323 b4050864 ngine...C..#...d + 1cf40: 6d615f6c 69620000 002bdf03 23f40508 ma_lib...+..#... + 1cf50: 6869665f 70636900 00002e3f 0323a806 hif_pci....?.#.. + 1cf60: 00095f41 5f6d6167 7069655f 696e6469 .._A_magpie_indi + 1cf70: 72656374 696f6e5f 7461626c 655f7400 rection_table_t. + 1cf80: 00004597 03000004 47040002 01060000 ..E.....G....... + 1cf90: 04040103 000046bd 04000b0b 03000046 ......F........F + 1cfa0: cb040006 00000404 01030000 46d30400 ............F... + 1cfb0: 06000001 0f010300 0046e004 001a010a .........F...... + 1cfc0: 636d6e6f 735f6d65 6d5f696e 69740001 cmnos_mem_init.. + 1cfd0: 01039201 20029000 008e22b0 008e22b5 .... ....."...". + 1cfe0: 1b011663 6d6e6f73 5f6d656d 5f6d6f64 ...cmnos_mem_mod + 1cff0: 756c655f 696e7374 616c6c00 01010392 ule_install..... + 1d000: 01200290 00008e22 b8008e22 d61c0116 . ....."...".... + 1d010: 74626c00 000046b4 01520000 0000004b tbl...F..R.....K + 1d020: 99000200 000b7c04 012f726f 6f742f57 ......|../root/W + 1d030: 6f726b73 70616365 2f303431 325f7632 orkspace/0412_v2 + 1d040: 30322f74 67742f62 75696c64 2f6d6167 02/tgt/build/mag + 1d050: 7069655f 315f312f 696d6167 652f6d61 pie_1_1/image/ma + 1d060: 67706965 2f2e2e2f 2e2e2f2e 2e2f2e2e gpie/../../../.. + 1d070: 2f2f6275 696c642f 6d616770 69655f31 //build/magpie_1 + 1d080: 5f312f72 6f6d2f63 6d6e6f73 2f6d6973 _1/rom/cmnos/mis + 1d090: 632f7372 632f636d 6e6f735f 6d697363 c/src/cmnos_misc + 1d0a0: 2e63002f 726f6f74 2f576f72 6b737061 .c./root/Workspa + 1d0b0: 63652f30 3431325f 76323032 2f746774 ce/0412_v202/tgt + 1d0c0: 2f627569 6c642f6d 61677069 655f315f /build/magpie_1_ + 1d0d0: 312f726f 6d2f636d 6e6f732f 6d697363 1/rom/cmnos/misc + 1d0e0: 0078742d 78636320 666f7220 372e312e .xt-xcc for 7.1. + 1d0f0: 30202d4f 50543a61 6c69676e 5f696e73 0 -OPT:align_ins + 1d100: 74727563 74696f6e 733d3332 202d4f32 tructions=32 -O2 + 1d110: 202d6733 202d4f50 543a7370 61636500 -g3 -OPT:space. + 1d120: 01000000 6d2a0201 03000001 09040004 ....m*.......... + 1d130: 696e7400 05040463 68617200 07010500 int....char..... + 1d140: 00011905 00000119 03000001 26040006 ............&... + 1d150: 00000112 01030000 01320400 07707269 .........2...pri + 1d160: 6e74665f 61706900 08000001 76085f70 ntf_api.....v._p + 1d170: 72696e74 665f696e 69740000 00010b02 rintf_init...... + 1d180: 2300085f 7072696e 74660000 00013802 #.._printf....8. + 1d190: 23040004 73686f72 7420756e 7369676e #...short unsign + 1d1a0: 65642069 6e740007 02097569 6e743136 ed int....uint16 + 1d1b0: 5f740000 00017604 6c6f6e67 20756e73 _t....v.long uns + 1d1c0: 69676e65 6420696e 74000704 0975696e igned int....uin + 1d1d0: 7433325f 74000000 019a0775 6172745f t32_t......uart_ + 1d1e0: 6669666f 00080000 02080873 74617274 fifo.......start + 1d1f0: 5f696e64 65780000 00018c02 23000865 _index......#..e + 1d200: 6e645f69 6e646578 00000001 8c022302 nd_index......#. + 1d210: 086f7665 7272756e 5f657272 00000001 .overrun_err.... + 1d220: af022304 00077561 72745f61 70690020 ..#...uart_api. + 1d230: 000002c1 085f7561 72745f69 6e697400 ....._uart_init. + 1d240: 00000318 02230008 5f756172 745f6368 .....#.._uart_ch + 1d250: 61725f70 75740000 00033f02 2304085f ar_put....?.#.._ + 1d260: 75617274 5f636861 725f6765 74000000 uart_char_get... + 1d270: 03530223 08085f75 6172745f 7374725f .S.#.._uart_str_ + 1d280: 6f757400 0000035c 02230c08 5f756172 out....\.#.._uar + 1d290: 745f7461 736b0000 00010b02 2310085f t_task......#.._ + 1d2a0: 75617274 5f737461 74757300 00000318 uart_status..... + 1d2b0: 02231408 5f756172 745f636f 6e666967 .#.._uart_config + 1d2c0: 00000003 65022318 085f7561 72745f68 ....e.#.._uart_h + 1d2d0: 77696e69 74000000 036e0223 1c000300 winit....n.#.... + 1d2e0: 00020804 00077561 72745f62 6c6b0010 ......uart_blk.. + 1d2f0: 00000312 08646562 75675f6d 6f646500 .....debug_mode. + 1d300: 0000018c 02230008 62617564 00000001 .....#..baud.... + 1d310: 8c022302 085f7561 72740000 0002c102 ..#.._uart...... + 1d320: 2304085f 74780000 0001bd02 23080006 #.._tx......#... + 1d330: 000001af 01030000 03120400 04756e73 .............uns + 1d340: 69676e65 64206368 61720007 01097569 igned char....ui + 1d350: 6e74385f 74000000 031f0201 03000003 nt8_t........... + 1d360: 3d040003 00000330 04000600 00018c01 =......0........ + 1d370: 03000003 4d040002 01030000 035a0400 ....M........Z.. + 1d380: 02010300 00036304 00020103 0000036c ......c........l + 1d390: 04000300 00011904 00060000 01120103 ................ + 1d3a0: 0000037c 04000744 425f434f 4d4d414e ...|...DB_COMMAN + 1d3b0: 445f5354 52554354 000c0000 03d40863 D_STRUCT.......c + 1d3c0: 6d645f73 74720000 00037502 23000868 md_str....u.#..h + 1d3d0: 656c705f 73747200 00000375 02230408 elp_str....u.#.. + 1d3e0: 636d645f 66756e63 00000003 82022308 cmd_func......#. + 1d3f0: 00076462 675f6170 69000800 00040708 ..dbg_api....... + 1d400: 5f646267 5f696e69 74000000 010b0223 _dbg_init......# + 1d410: 00085f64 62675f74 61736b00 0000010b .._dbg_task..... + 1d420: 02230400 0a040004 756e7369 676e6564 .#......unsigned + 1d430: 20696e74 00070406 00000407 01030000 int............ + 1d440: 041a0400 0b0b0300 00042804 00060000 ..........(..... + 1d450: 04070103 00000430 04000600 00011201 .......0........ + 1d460: 03000004 3d040007 6d656d5f 61706900 ....=...mem_api. + 1d470: 14000004 ac085f6d 656d5f69 6e697400 ......_mem_init. + 1d480: 0000010b 02230008 5f6d656d 73657400 .....#.._memset. + 1d490: 00000420 02230408 5f6d656d 63707900 ... .#.._memcpy. + 1d4a0: 00000436 02230808 5f6d656d 6d6f7665 ...6.#.._memmove + 1d4b0: 00000004 3602230c 085f6d65 6d636d70 ....6.#.._memcmp + 1d4c0: 00000004 43022310 00077265 67697374 ....C.#...regist + 1d4d0: 65725f64 756d705f 73009000 00051308 er_dump_s....... + 1d4e0: 74617267 65745f69 64000000 01af0223 target_id......# + 1d4f0: 00086173 736c696e 65000000 01af0223 ..assline......# + 1d500: 04087063 00000001 af022308 08626164 ..pc......#..bad + 1d510: 76616464 72000000 01af0223 0c086578 vaddr......#..ex + 1d520: 635f6672 616d6500 0000482f 02231000 c_frame...H/.#.. + 1d530: 03000004 ac040002 01030000 051a0400 ................ + 1d540: 02010300 00052304 00060000 01120103 ......#......... + 1d550: 0000052c 04000c68 6f737469 665f7300 ...,...hostif_s. + 1d560: 04000005 880d4849 465f5553 4200000d ......HIF_USB... + 1d570: 4849465f 50434945 00010d48 49465f47 HIF_PCIE...HIF_G + 1d580: 4d414300 020d4849 465f5043 4900030d MAC...HIF_PCI... + 1d590: 4849465f 4e554d00 040d4849 465f4e4f HIF_NUM...HIF_NO + 1d5a0: 4e450005 0009415f 484f5354 49460000 NE....A_HOSTIF.. + 1d5b0: 00053906 00000588 01030000 05960400 ..9............. + 1d5c0: 06000003 30010300 0005a304 00060000 ....0........... + 1d5d0: 018c0103 000005b0 0400076d 6973635f ...........misc_ + 1d5e0: 61706900 24000006 a0085f73 79737465 api.$....._syste + 1d5f0: 6d5f7265 73657400 0000010b 02230008 m_reset......#.. + 1d600: 5f6d6163 5f726573 65740000 00010b02 _mac_reset...... + 1d610: 2304085f 61737366 61696c00 0000051c #.._assfail..... + 1d620: 02230808 5f6d6973 616c6967 6e65645f .#.._misaligned_ + 1d630: 6c6f6164 5f68616e 646c6572 00000005 load_handler.... + 1d640: 1c02230c 085f7265 706f7274 5f666169 ..#.._report_fai + 1d650: 6c757265 5f746f5f 686f7374 00000005 lure_to_host.... + 1d660: 25022310 085f7461 72676574 5f69645f %.#.._target_id_ + 1d670: 67657400 00000532 02231408 5f69735f get....2.#.._is_ + 1d680: 686f7374 5f707265 73656e74 00000005 host_present.... + 1d690: 9c022318 085f6b62 68697400 000005a9 ..#.._kbhit..... + 1d6a0: 02231c08 5f726f6d 5f766572 73696f6e .#.._rom_version + 1d6b0: 5f676574 00000005 b6022320 00060000 _get......# .... + 1d6c0: 03750103 000006a0 04000600 00037501 .u............u. + 1d6d0: 03000006 ad040006 00000112 01030000 ................ + 1d6e0: 06ba0400 06000001 12010300 0006c704 ................ + 1d6f0: 00060000 01120103 000006d4 04000773 ...............s + 1d700: 7472696e 675f6170 69001800 00075a08 tring_api.....Z. + 1d710: 5f737472 696e675f 696e6974 00000001 _string_init.... + 1d720: 0b022300 085f7374 72637079 00000006 ..#.._strcpy.... + 1d730: a6022304 085f7374 726e6370 79000000 ..#.._strncpy... + 1d740: 06b30223 08085f73 74726c65 6e000000 ...#.._strlen... + 1d750: 06c00223 0c085f73 7472636d 70000000 ...#.._strcmp... + 1d760: 06cd0223 10085f73 74726e63 6d700000 ...#.._strncmp.. + 1d770: 0006da02 2314000e 0000040a 14000007 ....#........... + 1d780: 670f0400 095f415f 54494d45 525f5350 g...._A_TIMER_SP + 1d790: 41434500 0000075a 09415f74 696d6572 ACE....Z.A_timer + 1d7a0: 5f740000 00076703 0000077b 04000201 _t....g....{.... + 1d7b0: 03000007 91040002 01030000 079a0400 ................ + 1d7c0: 09415f48 414e444c 45000000 040a0201 .A_HANDLE....... + 1d7d0: 09415f54 494d4552 5f46554e 43000000 .A_TIMER_FUNC... + 1d7e0: 07b10300 0007b304 00020103 000007cc ................ + 1d7f0: 04000774 696d6572 5f617069 00140000 ...timer_api.... + 1d800: 084b085f 74696d65 725f696e 69740000 .K._timer_init.. + 1d810: 00010b02 2300085f 74696d65 725f6172 ....#.._timer_ar + 1d820: 6d000000 07930223 04085f74 696d6572 m......#.._timer + 1d830: 5f646973 61726d00 0000079c 02230808 _disarm......#.. + 1d840: 5f74696d 65725f73 6574666e 00000007 _timer_setfn.... + 1d850: ce02230c 085f7469 6d65725f 72756e00 ..#.._timer_run. + 1d860: 0000010b 02231000 09424f4f 4c45414e .....#...BOOLEAN + 1d870: 00000001 8c060000 084b0103 00000858 .........K.....X + 1d880: 04000600 00084b01 03000008 65040006 ......K.....e... + 1d890: 0000084b 01030000 08720400 07726f6d ...K.....r...rom + 1d8a0: 705f6170 69001000 0008e408 5f726f6d p_api......._rom + 1d8b0: 705f696e 69740000 00010b02 2300085f p_init......#.._ + 1d8c0: 726f6d70 5f646f77 6e6c6f61 64000000 romp_download... + 1d8d0: 085e0223 04085f72 6f6d705f 696e7374 .^.#.._romp_inst + 1d8e0: 616c6c00 0000086b 02230808 5f726f6d all....k.#.._rom + 1d8f0: 705f6465 636f6465 00000008 7802230c p_decode....x.#. + 1d900: 0007726f 6d5f7061 7463685f 73740010 ..rom_patch_st.. + 1d910: 00000940 08637263 31360000 00018c02 ...@.crc16...... + 1d920: 2300086c 656e0000 00018c02 2302086c #..len......#..l + 1d930: 645f6164 64720000 0001af02 23040866 d_addr......#..f + 1d940: 756e5f61 64647200 000001af 02230808 un_addr......#.. + 1d950: 7066756e 00000003 4602230c 00076565 pfun....F.#...ee + 1d960: 705f7265 6469725f 61646472 00040000 p_redir_addr.... + 1d970: 0972086f 66667365 74000000 018c0223 .r.offset......# + 1d980: 00087369 7a650000 00018c02 23020009 ..size......#... + 1d990: 415f5549 4e543332 00000004 0a060000 A_UINT32........ + 1d9a0: 04070103 00000980 04000761 6c6c6f63 ...........alloc + 1d9b0: 72616d5f 61706900 0c000009 f108636d ram_api.......cm + 1d9c0: 6e6f735f 616c6c6f 6372616d 5f696e69 nos_allocram_ini + 1d9d0: 74000000 09860223 0008636d 6e6f735f t......#..cmnos_ + 1d9e0: 616c6c6f 6372616d 00000009 86022304 allocram......#. + 1d9f0: 08636d6e 6f735f61 6c6c6f63 72616d5f .cmnos_allocram_ + 1da00: 64656275 67000000 010b0223 08000201 debug......#.... + 1da10: 03000009 f1040009 415f5441 534b4c45 ........A_TASKLE + 1da20: 545f4655 4e430000 0009f307 5f746173 T_FUNC......_tas + 1da30: 6b6c6574 00100000 0a520866 756e6300 klet.....R.func. + 1da40: 000009fa 02230008 61726700 00000407 .....#..arg..... + 1da50: 02230408 73746174 65000000 01120223 .#..state......# + 1da60: 08086e65 78740000 000a5202 230c0003 ..next....R.#... + 1da70: 00000a0e 04000300 000a0e04 0009415f ..............A_ + 1da80: 7461736b 6c65745f 74000000 0a0e0300 tasklet_t....... + 1da90: 000a6004 00020103 00000a78 04000201 ..`........x.... + 1daa0: 0300000a 81040007 7461736b 6c65745f ........tasklet_ + 1dab0: 61706900 1400000b 16085f74 61736b6c api......._taskl + 1dac0: 65745f69 6e697400 0000010b 02230008 et_init......#.. + 1dad0: 5f746173 6b6c6574 5f696e69 745f7461 _tasklet_init_ta + 1dae0: 736b0000 000a7a02 2304085f 7461736b sk....z.#.._task + 1daf0: 6c65745f 64697361 626c6500 00000a83 let_disable..... + 1db00: 02230808 5f746173 6b6c6574 5f736368 .#.._tasklet_sch + 1db10: 6564756c 65000000 0a830223 0c085f74 edule......#.._t + 1db20: 61736b6c 65745f72 756e0000 00010b02 asklet_run...... + 1db30: 23100002 01030000 0b160400 06000009 #............... + 1db40: 72010300 000b1f04 00020103 00000b2c r.............., + 1db50: 04000763 6c6f636b 5f617069 00240000 ...clock_api.$.. + 1db60: 0c0e085f 636c6f63 6b5f696e 69740000 ..._clock_init.. + 1db70: 000b1802 2300085f 636c6f63 6b726567 ....#.._clockreg + 1db80: 735f696e 69740000 00010b02 2304085f s_init......#.._ + 1db90: 75617274 5f667265 7175656e 63790000 uart_frequency.. + 1dba0: 000b2502 2308085f 64656c61 795f7573 ..%.#.._delay_us + 1dbb0: 0000000b 2e02230c 085f776c 616e5f62 ......#.._wlan_b + 1dbc0: 616e645f 73657400 00000b2e 02231008 and_set......#.. + 1dbd0: 5f726566 636c6b5f 73706565 645f6765 _refclk_speed_ge + 1dbe0: 74000000 0b250223 14085f6d 696c6c69 t....%.#.._milli + 1dbf0: 7365636f 6e647300 00000b25 02231808 seconds....%.#.. + 1dc00: 5f737973 636c6b5f 6368616e 67650000 _sysclk_change.. + 1dc10: 00010b02 231c085f 636c6f63 6b5f7469 ....#.._clock_ti + 1dc20: 636b0000 00010b02 23200006 000001af ck......# ...... + 1dc30: 01030000 0c0e0400 09415f6f 6c645f69 .........A_old_i + 1dc40: 6e74725f 74000000 01af0600 000c1b01 ntr_t........... + 1dc50: 0300000c 2d040002 01030000 0c3a0400 ....-........:.. + 1dc60: 02010300 000c4304 00060000 01af0103 ......C......... + 1dc70: 00000c4c 04000941 5f697372 5f740000 ...L...A_isr_t.. + 1dc80: 000c5202 01030000 0c660400 06000004 ..R......f...... + 1dc90: 0a010300 000c6f04 00020103 00000c7c ......o........| + 1dca0: 04000769 6e74725f 61706900 2c00000d ...intr_api.,... + 1dcb0: 9e085f69 6e74725f 696e6974 00000001 .._intr_init.... + 1dcc0: 0b022300 085f696e 74725f69 6e766f6b ..#.._intr_invok + 1dcd0: 655f6973 72000000 0c140223 04085f69 e_isr......#.._i + 1dce0: 6e74725f 64697361 626c6500 00000c33 ntr_disable....3 + 1dcf0: 02230808 5f696e74 725f7265 73746f72 .#.._intr_restor + 1dd00: 65000000 0c3c0223 0c085f69 6e74725f e....<.#.._intr_ + 1dd10: 6d61736b 5f696e75 6d000000 0c450223 mask_inum....E.# + 1dd20: 10085f69 6e74725f 756e6d61 736b5f69 .._intr_unmask_i + 1dd30: 6e756d00 00000c45 02231408 5f696e74 num....E.#.._int + 1dd40: 725f6174 74616368 5f697372 0000000c r_attach_isr.... + 1dd50: 68022318 085f6765 745f696e 7472656e h.#.._get_intren + 1dd60: 61626c65 0000000c 7502231c 085f7365 able....u.#.._se + 1dd70: 745f696e 7472656e 61626c65 0000000c t_intrenable.... + 1dd80: 7e022320 085f6765 745f696e 74727065 ~.# ._get_intrpe + 1dd90: 6e64696e 67000000 0c750223 24085f75 nding....u.#$._u + 1dda0: 6e626c6f 636b5f61 6c6c5f69 6e74726c nblock_all_intrl + 1ddb0: 766c0000 00010b02 23280010 0400000d vl......#(...... + 1ddc0: c4087469 6d656f75 74000000 01af0223 ..timeout......# + 1ddd0: 00086163 74696f6e 00000001 af022300 ..action......#. + 1dde0: 00110800 000ddf08 636d6400 000001af ........cmd..... + 1ddf0: 02230012 00000d9e 02230400 09545f57 .#.......#...T_W + 1de00: 44545f43 4d440000 000dc402 01030000 DT_CMD.......... + 1de10: 0dee0400 13040000 0e440d45 4e554d5f .........D.ENUM_ + 1de20: 5744545f 424f4f54 00010d45 4e554d5f WDT_BOOT...ENUM_ + 1de30: 434f4c44 5f424f4f 5400020d 454e554d COLD_BOOT...ENUM + 1de40: 5f535553 505f424f 4f540003 0d454e55 _SUSP_BOOT...ENU + 1de50: 4d5f554e 4b4e4f57 4e5f424f 4f540004 M_UNKNOWN_BOOT.. + 1de60: 0009545f 424f4f54 5f545950 45000000 ..T_BOOT_TYPE... + 1de70: 0df70600 000e4401 0300000e 55040007 ......D.....U... + 1de80: 7764745f 61706900 1c00000e f9085f77 wdt_api......._w + 1de90: 64745f69 6e697400 0000010b 02230008 dt_init......#.. + 1dea0: 5f776474 5f656e61 626c6500 0000010b _wdt_enable..... + 1deb0: 02230408 5f776474 5f646973 61626c65 .#.._wdt_disable + 1dec0: 00000001 0b022308 085f7764 745f7365 ......#.._wdt_se + 1ded0: 74000000 0df00223 0c085f77 64745f74 t......#.._wdt_t + 1dee0: 61736b00 0000010b 02231008 5f776474 ask......#.._wdt + 1def0: 5f726573 65740000 00010b02 2314085f _reset......#.._ + 1df00: 7764745f 6c617374 5f626f6f 74000000 wdt_last_boot... + 1df10: 0e5b0223 18001304 00000f60 0d524554 .[.#.......`.RET + 1df20: 5f535543 43455353 00000d52 45545f4e _SUCCESS...RET_N + 1df30: 4f545f49 4e495400 010d5245 545f4e4f OT_INIT...RET_NO + 1df40: 545f4558 49535400 020d5245 545f4545 T_EXIST...RET_EE + 1df50: 505f434f 52525550 5400030d 5245545f P_CORRUPT...RET_ + 1df60: 4545505f 4f564552 464c4f57 00040d52 EEP_OVERFLOW...R + 1df70: 45545f55 4e4b4e4f 574e0005 0009545f ET_UNKNOWN....T_ + 1df80: 4545505f 52455400 00000ef9 03000001 EEP_RET......... + 1df90: 8c040006 00000f60 01030000 0f760400 .......`.....v.. + 1dfa0: 0600000f 60010300 000f8304 00076565 ....`.........ee + 1dfb0: 705f6170 69001000 000fec08 5f656570 p_api......._eep + 1dfc0: 5f696e69 74000000 010b0223 00085f65 _init......#.._e + 1dfd0: 65705f72 65616400 00000f7c 02230408 ep_read....|.#.. + 1dfe0: 5f656570 5f777269 74650000 000f7c02 _eep_write....|. + 1dff0: 2308085f 6565705f 69735f65 78697374 #.._eep_is_exist + 1e000: 0000000f 8902230c 00077573 625f6170 ......#...usb_ap + 1e010: 69007000 00129908 5f757362 5f696e69 i.p....._usb_ini + 1e020: 74000000 010b0223 00085f75 73625f72 t......#.._usb_r + 1e030: 6f6d5f74 61736b00 0000010b 02230408 om_task......#.. + 1e040: 5f757362 5f66775f 7461736b 00000001 _usb_fw_task.... + 1e050: 0b022308 085f7573 625f696e 69745f70 ..#.._usb_init_p + 1e060: 68790000 00010b02 230c085f 7573625f hy......#.._usb_ + 1e070: 6570305f 73657475 70000000 010b0223 ep0_setup......# + 1e080: 10085f75 73625f65 70305f74 78000000 .._usb_ep0_tx... + 1e090: 010b0223 14085f75 73625f65 70305f72 ...#.._usb_ep0_r + 1e0a0: 78000000 010b0223 18085f75 73625f67 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Y.......9b...... + 29f90: 1e040006 000012e4 01030000 39720400 ............9r.. + 29fa0: 03000037 c7040007 5f485443 5f434f4e ...7...._HTC_CON + 29fb0: 46494700 14000039 f7084372 65646974 FIG....9..Credit + 29fc0: 53697a65 00000001 1e022300 08437265 Size......#..Cre + 29fd0: 6469744e 756d6265 72000000 011e0223 ditNumber......# + 29fe0: 04084f53 48616e64 6c650000 001a4e02 ..OSHandle....N. + 29ff0: 23080848 49464861 6e646c65 00000028 #..HIFHandle...( + 2a000: b702230c 08506f6f 6c48616e 646c6500 ..#..PoolHandle. + 2a010: 00003653 02231000 075f4854 435f4255 ..6S.#..._HTC_BU + 2a020: 465f434f 4e544558 54000200 003a3308 F_CONTEXT....:3. + 2a030: 656e645f 706f696e 74000000 12e40223 end_point......# + 2a040: 00086874 635f666c 61677300 000012e4 ..htc_flags..... + 2a050: 02230100 09687463 5f68616e 646c655f .#...htc_handle_ + 2a060: 74000000 04130948 54435f53 45545550 t......HTC_SETUP + 2a070: 5f434f4d 504c4554 455f4342 00000001 _COMPLETE_CB.... + 2a080: 17094854 435f434f 4e464947 00000039 ..HTC_CONFIG...9 + 2a090: 86030000 3a600400 0600003a 33010300 ....:`.....:3... + 2a0a0: 003a7704 00020103 00003a84 04000948 .:w.......:....H + 2a0b0: 54435f53 45525649 43450000 0037c703 TC_SERVICE...7.. + 2a0c0: 00003a8d 04000201 0300003a a5040002 ..:........:.... + 2a0d0: 01030000 3aae0400 02010300 003ab704 ....:........:.. + 2a0e0: 00060000 011e0103 00003ac0 04000768 ..........:....h + 2a0f0: 74635f61 70697300 3400003c 3d085f48 tc_apis.4..<=._H + 2a100: 54435f49 6e697400 00003a7d 02230008 TC_Init...:}.#.. + 2a110: 5f485443 5f536875 74646f77 6e000000 _HTC_Shutdown... + 2a120: 3a860223 04085f48 54435f52 65676973 :..#.._HTC_Regis + 2a130: 74657253 65727669 63650000 003aa702 terService...:.. + 2a140: 2308085f 4854435f 52656164 79000000 #.._HTC_Ready... + 2a150: 3a860223 0c085f48 54435f52 65747572 :..#.._HTC_Retur + 2a160: 6e427566 66657273 0000003a b0022310 nBuffers...:..#. + 2a170: 085f4854 435f5265 7475726e 42756666 ._HTC_ReturnBuff + 2a180: 6572734c 69737400 00003ab9 02231408 ersList...:..#.. + 2a190: 5f485443 5f53656e 644d7367 0000003a _HTC_SendMsg...: + 2a1a0: b0022318 085f4854 435f4765 74526573 ..#.._HTC_GetRes + 2a1b0: 65727665 64486561 64726f6f 6d000000 ervedHeadroom... + 2a1c0: 3ac60223 1c085f48 54435f4d 73675265 :..#.._HTC_MsgRe + 2a1d0: 63764861 6e646c65 72000000 28640223 cvHandler...(d.# + 2a1e0: 20085f48 54435f53 656e6444 6f6e6548 ._HTC_SendDoneH + 2a1f0: 616e646c 65720000 00285b02 2324085f andler...([.#$._ + 2a200: 4854435f 436f6e74 726f6c53 76635072 HTC_ControlSvcPr + 2a210: 6f636573 734d7367 00000039 5b022328 ocessMsg...9[.#( + 2a220: 085f4854 435f436f 6e74726f 6c537663 ._HTC_ControlSvc + 2a230: 50726f63 65737353 656e6443 6f6d706c ProcessSendCompl + 2a240: 65746500 00003964 02232c08 70526573 ete...9d.#,.pRes + 2a250: 65727665 64000000 04130223 30000768 erved......#0..h + 2a260: 6f73745f 6170705f 61726561 5f730004 ost_app_area_s.. + 2a270: 00003c6d 08776d69 5f70726f 746f636f ...# + 2b130: 04000473 686f7274 20756e73 69676e65 ...short unsigne + 2b140: 6420696e 74000702 0975696e 7431365f d int....uint16_ + 2b150: 74000000 017c046c 6f6e6720 756e7369 t....|.long unsi + 2b160: 676e6564 20696e74 00070409 75696e74 gned int....uint + 2b170: 33325f74 00000001 a0077561 72745f66 32_t......uart_f + 2b180: 69666f00 08000002 0e087374 6172745f ifo.......start_ + 2b190: 696e6465 78000000 01920223 0008656e index......#..en + 2b1a0: 645f696e 64657800 00000192 02230208 d_index......#.. + 2b1b0: 6f766572 72756e5f 65727200 000001b5 overrun_err..... + 2b1c0: 02230400 07756172 745f6170 69002000 .#...uart_api. . + 2b1d0: 0002c708 5f756172 745f696e 69740000 ...._uart_init.. + 2b1e0: 00031e02 2300085f 75617274 5f636861 ....#.._uart_cha + 2b1f0: 725f7075 74000000 03450223 04085f75 r_put....E.#.._u + 2b200: 6172745f 63686172 5f676574 00000003 art_char_get.... + 2b210: 59022308 085f7561 72745f73 74725f6f Y.#.._uart_str_o + 2b220: 75740000 00036202 230c085f 75617274 ut....b.#.._uart + 2b230: 5f746173 6b000000 01110223 10085f75 _task......#.._u + 2b240: 6172745f 73746174 75730000 00031e02 art_status...... + 2b250: 2314085f 75617274 5f636f6e 66696700 #.._uart_config. + 2b260: 0000036b 02231808 5f756172 745f6877 ...k.#.._uart_hw + 2b270: 696e6974 00000003 7402231c 00030000 init....t.#..... + 2b280: 020e0400 07756172 745f626c 6b001000 .....uart_blk... + 2b290: 00031808 64656275 675f6d6f 64650000 ....debug_mode.. + 2b2a0: 00019202 23000862 61756400 00000192 ....#..baud..... + 2b2b0: 02230208 5f756172 74000000 02c70223 .#.._uart......# + 2b2c0: 04085f74 78000000 01c30223 08000600 .._tx......#.... + 2b2d0: 0001b501 03000003 18040004 756e7369 ............unsi + 2b2e0: 676e6564 20636861 72000701 0975696e gned char....uin + 2b2f0: 74385f74 00000003 25020103 00000343 t8_t....%......C + 2b300: 04000300 00033604 00060000 01920103 ......6......... + 2b310: 00000353 04000201 03000003 60040002 ...S........`... + 2b320: 01030000 03690400 02010300 00037204 .....i........r. + 2b330: 00030000 011f0400 06000001 18010300 ................ + 2b340: 00038204 00074442 5f434f4d 4d414e44 ......DB_COMMAND + 2b350: 5f535452 55435400 0c000003 da08636d _STRUCT.......cm + 2b360: 645f7374 72000000 037b0223 00086865 d_str....{.#..he + 2b370: 6c705f73 74720000 00037b02 23040863 lp_str....{.#..c + 2b380: 6d645f66 756e6300 00000388 02230800 md_func......#.. + 2b390: 07646267 5f617069 00080000 040d085f .dbg_api......._ + 2b3a0: 6462675f 696e6974 00000001 11022300 dbg_init......#. + 2b3b0: 085f6462 675f7461 736b0000 00011102 ._dbg_task...... + 2b3c0: 2304000a 04000475 6e736967 6e656420 #......unsigned + 2b3d0: 696e7400 07040600 00040d01 03000004 int............. + 2b3e0: 2004000b 0b030000 042e0400 06000004 ............... + 2b3f0: 0d010300 00043604 00060000 01180103 ......6......... + 2b400: 00000443 0400076d 656d5f61 70690014 ...C...mem_api.. + 2b410: 000004b2 085f6d65 6d5f696e 69740000 ....._mem_init.. + 2b420: 00011102 2300085f 6d656d73 65740000 ....#.._memset.. + 2b430: 00042602 2304085f 6d656d63 70790000 ..&.#.._memcpy.. + 2b440: 00043c02 2308085f 6d656d6d 6f766500 ..<.#.._memmove. + 2b450: 0000043c 02230c08 5f6d656d 636d7000 ...<.#.._memcmp. + 2b460: 00000449 02231000 0c726567 69737465 ...I.#...registe + 2b470: 725f6475 6d705f73 00000103 000004b2 r_dump_s........ + 2b480: 04000201 03000004 cc040002 01030000 ................ + 2b490: 04d50400 06000001 18010300 0004de04 ................ + 2b4a0: 000d686f 73746966 5f730004 0000053a ..hostif_s.....: + 2b4b0: 0e484946 5f555342 00000e48 49465f50 .HIF_USB...HIF_P + 2b4c0: 43494500 010e4849 465f474d 41430002 CIE...HIF_GMAC.. + 2b4d0: 0e484946 5f504349 00030e48 49465f4e .HIF_PCI...HIF_N + 2b4e0: 554d0004 0e484946 5f4e4f4e 45000500 UM...HIF_NONE... + 2b4f0: 09415f48 4f535449 46000000 04eb0600 .A_HOSTIF....... + 2b500: 00053a01 03000005 48040006 00000336 ..:.....H......6 + 2b510: 01030000 05550400 06000001 92010300 .....U.......... + 2b520: 00056204 00076d69 73635f61 70690024 ..b...misc_api.$ + 2b530: 00000652 085f7379 7374656d 5f726573 ...R._system_res + 2b540: 65740000 00011102 2300085f 6d61635f et......#.._mac_ + 2b550: 72657365 74000000 01110223 04085f61 reset......#.._a + 2b560: 73736661 696c0000 0004ce02 2308085f ssfail......#.._ + 2b570: 6d697361 6c69676e 65645f6c 6f61645f misaligned_load_ + 2b580: 68616e64 6c657200 000004ce 02230c08 handler......#.. + 2b590: 5f726570 6f72745f 6661696c 7572655f _report_failure_ + 2b5a0: 746f5f68 6f737400 000004d7 02231008 to_host......#.. + 2b5b0: 5f746172 6765745f 69645f67 65740000 _target_id_get.. + 2b5c0: 0004e402 2314085f 69735f68 6f73745f ....#.._is_host_ + 2b5d0: 70726573 656e7400 0000054e 02231808 present....N.#.. + 2b5e0: 5f6b6268 69740000 00055b02 231c085f _kbhit....[.#.._ + 2b5f0: 726f6d5f 76657273 696f6e5f 67657400 rom_version_get. + 2b600: 00000568 02232000 06000003 7b010300 ...h.# .....{... + 2b610: 00065204 00060000 037b0103 0000065f ..R......{....._ + 2b620: 04000600 00011801 03000006 6c040006 ............l... + 2b630: 00000118 01030000 06790400 06000001 .........y...... + 2b640: 18010300 00068604 00077374 72696e67 ..........string + 2b650: 5f617069 00180000 070c085f 73747269 _api......._stri + 2b660: 6e675f69 6e697400 00000111 02230008 ng_init......#.. + 2b670: 5f737472 63707900 00000658 02230408 _strcpy....X.#.. + 2b680: 5f737472 6e637079 00000006 65022308 _strncpy....e.#. + 2b690: 085f7374 726c656e 00000006 7202230c ._strlen....r.#. + 2b6a0: 085f7374 72636d70 00000006 7f022310 ._strcmp......#. + 2b6b0: 085f7374 726e636d 70000000 068c0223 ._strncmp......# + 2b6c0: 14000f00 00041014 00000719 10040009 ................ + 2b6d0: 5f415f54 494d4552 5f535041 43450000 _A_TIMER_SPACE.. + 2b6e0: 00070c09 415f7469 6d65725f 74000000 ....A_timer_t... + 2b6f0: 07190300 00072d04 00020103 00000743 ......-........C + 2b700: 04000201 03000007 4c040009 415f4841 ........L...A_HA + 2b710: 4e444c45 00000004 10020109 415f5449 NDLE........A_TI + 2b720: 4d45525f 46554e43 00000007 63030000 MER_FUNC....c... + 2b730: 07650400 02010300 00077e04 00077469 .e........~...ti + 2b740: 6d65725f 61706900 14000007 fd085f74 mer_api......._t + 2b750: 696d6572 5f696e69 74000000 01110223 imer_init......# + 2b760: 00085f74 696d6572 5f61726d 00000007 .._timer_arm.... + 2b770: 45022304 085f7469 6d65725f 64697361 E.#.._timer_disa + 2b780: 726d0000 00074e02 2308085f 74696d65 rm....N.#.._time + 2b790: 725f7365 74666e00 00000780 02230c08 r_setfn......#.. + 2b7a0: 5f74696d 65725f72 756e0000 00011102 _timer_run...... + 2b7b0: 23100009 424f4f4c 45414e00 00000192 #...BOOLEAN..... + 2b7c0: 06000007 fd010300 00080a04 00060000 ................ + 2b7d0: 07fd0103 00000817 04000600 0007fd01 ................ + 2b7e0: 03000008 24040007 726f6d70 5f617069 ....$...romp_api + 2b7f0: 00100000 0896085f 726f6d70 5f696e69 ......._romp_ini + 2b800: 74000000 01110223 00085f72 6f6d705f t......#.._romp_ + 2b810: 646f776e 6c6f6164 00000008 10022304 download......#. + 2b820: 085f726f 6d705f69 6e737461 6c6c0000 ._romp_install.. + 2b830: 00081d02 2308085f 726f6d70 5f646563 ....#.._romp_dec + 2b840: 6f646500 0000082a 02230c00 07726f6d ode....*.#...rom + 2b850: 5f706174 63685f73 74001000 0008f208 _patch_st....... + 2b860: 63726331 36000000 01920223 00086c65 crc16......#..le + 2b870: 6e000000 01920223 02086c64 5f616464 n......#..ld_add + 2b880: 72000000 01b50223 04086675 6e5f6164 r......#..fun_ad + 2b890: 64720000 0001b502 23080870 66756e00 dr......#..pfun. + 2b8a0: 0000034c 02230c00 07656570 5f726564 ...L.#...eep_red + 2b8b0: 69725f61 64647200 04000009 24086f66 ir_addr.....$.of + 2b8c0: 66736574 00000001 92022300 0873697a fset......#..siz + 2b8d0: 65000000 01920223 02000941 5f55494e e......#...A_UIN + 2b8e0: 54333200 00000410 06000004 0d010300 T32............. + 2b8f0: 00093204 0007616c 6c6f6372 616d5f61 ..2...allocram_a + 2b900: 7069000c 000009a3 08636d6e 6f735f61 pi.......cmnos_a + 2b910: 6c6c6f63 72616d5f 696e6974 00000009 llocram_init.... + 2b920: 38022300 08636d6e 6f735f61 6c6c6f63 8.#..cmnos_alloc + 2b930: 72616d00 00000938 02230408 636d6e6f ram....8.#..cmno + 2b940: 735f616c 6c6f6372 616d5f64 65627567 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isable....5.#.._ + 2ba50: 7461736b 6c65745f 73636865 64756c65 tasklet_schedule + 2ba60: 0000000a 3502230c 085f7461 736b6c65 ....5.#.._taskle + 2ba70: 745f7275 6e000000 01110223 10000201 t_run......#.... + 2ba80: 0300000a c8040006 00000924 01030000 ...........$.... + 2ba90: 0ad10400 02010300 000ade04 0007636c ..............cl + 2baa0: 6f636b5f 61706900 2400000b c0085f63 ock_api.$....._c + 2bab0: 6c6f636b 5f696e69 74000000 0aca0223 lock_init......# + 2bac0: 00085f63 6c6f636b 72656773 5f696e69 .._clockregs_ini + 2bad0: 74000000 01110223 04085f75 6172745f t......#.._uart_ + 2bae0: 66726571 75656e63 79000000 0ad70223 frequency......# + 2baf0: 08085f64 656c6179 5f757300 00000ae0 .._delay_us..... + 2bb00: 02230c08 5f776c61 6e5f6261 6e645f73 .#.._wlan_band_s + 2bb10: 65740000 000ae002 2310085f 72656663 et......#.._refc + 2bb20: 6c6b5f73 70656564 5f676574 0000000a lk_speed_get.... + 2bb30: d7022314 085f6d69 6c6c6973 65636f6e ..#.._millisecon + 2bb40: 64730000 000ad702 2318085f 73797363 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._usb_get_descri + 2c150: 70746f72 00000008 1d022350 085f7573 ptor......#P._us + 2c160: 625f6765 745f7374 61747573 00000008 b_get_status.... + 2c170: 1d022354 085f7573 625f7365 7475705f ..#T._usb_setup_ + 2c180: 64657363 00000001 11022358 085f7573 desc......#X._us + 2c190: 625f7265 675f6f75 74000000 01110223 b_reg_out......# + 2c1a0: 5c085f75 73625f73 74617475 735f696e \._usb_status_in + 2c1b0: 00000001 11022360 085f7573 625f6570 ......#`._usb_ep + 2c1c0: 305f7478 5f646174 61000000 01110223 0_tx_data......# + 2c1d0: 64085f75 73625f65 70305f72 785f6461 d._usb_ep0_rx_da + 2c1e0: 74610000 00011102 2368085f 7573625f ta......#h._usb_ + 2c1f0: 636c6b5f 696e6974 00000001 1102236c clk_init......#l + 2c200: 00075f56 44455343 00240000 12d7086e .._VDESC.$.....n + 2c210: 6578745f 64657363 00000012 d7022300 ext_desc......#. + 2c220: 08627566 5f616464 72000000 12eb0223 .buf_addr......# + 2c230: 04086275 665f7369 7a650000 0012f202 ..buf_size...... + 2c240: 23080864 6174615f 6f666673 65740000 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...addr....i.#.. + 2cc50: 095f5f61 5f75696e 7431365f 74000000 .__a_uint16_t... + 2cc60: 12f20961 5f75696e 7431365f 74000000 ...a_uint16_t... + 2cc70: 1c9a120e 00001cfe 08657468 65725f64 .........ether_d + 2cc80: 686f7374 0000001c 69022300 08657468 host....i.#..eth + 2cc90: 65725f73 686f7374 0000001c 69022306 er_shost....i.#. + 2cca0: 08657468 65725f74 79706500 00001cac .ether_type..... + 2ccb0: 02230c00 12140000 1dbf1569 705f7665 .#.........ip_ve + 2ccc0: 7273696f 6e000000 16840100 04022300 rsion.........#. + 2ccd0: 1569705f 686c0000 00168401 04040223 .ip_hl.........# + 2cce0: 00086970 5f746f73 00000016 84022301 ..ip_tos......#. + 2ccf0: 0869705f 6c656e00 00001cac 02230208 .ip_len......#.. + 2cd00: 69705f69 64000000 1cac0223 04086970 ip_id......#..ip + 2cd10: 5f667261 675f6f66 66000000 1cac0223 _frag_off......# + 2cd20: 06086970 5f74746c 00000016 84022308 ..ip_ttl......#. + 2cd30: 0869705f 70726f74 6f000000 16840223 .ip_proto......# + 2cd40: 09086970 5f636865 636b0000 001cac02 ..ip_check...... + 2cd50: 230a0869 705f7361 64647200 0000161d #..ip_saddr..... + 2cd60: 02230c08 69705f64 61646472 00000016 .#..ip_daddr.... + 2cd70: 1d022310 00076164 665f6e65 745f766c ..#...adf_net_vl + 2cd80: 616e6864 72000400 001e1108 74706964 anhdr.......tpid + 2cd90: 0000001c ac022300 15707269 6f000000 ......#..prio... + 2cda0: 16840100 03022302 15636669 00000016 ......#..cfi.... + 2cdb0: 84010301 02230215 76696400 00001cac .....#..vid..... + 2cdc0: 02040c02 23020007 6164665f 6e65745f ....#...adf_net_ + 2cdd0: 76696400 0200001e 42157265 73000000 vid.....B.res... + 2cde0: 16840100 04022300 1576616c 0000001c ......#..val.... + 2cdf0: ac02040c 02230000 120c0000 1e7e0872 .....#.......~.r + 2ce00: 785f6275 6673697a 65000000 161d0223 x_bufsize......# + 2ce10: 00087278 5f6e6465 73630000 00161d02 ..rx_ndesc...... + 2ce20: 23040874 785f6e64 65736300 0000161d #..tx_ndesc..... + 2ce30: 02230800 12080000 1ea40870 6f6c6c65 .#.........polle + 2ce40: 64000000 1a970223 0008706f 6c6c5f77 d......#..poll_w + 2ce50: 74000000 161d0223 04000f00 00168440 t......#.......@ + 2ce60: 00001eb1 103f0012 4600001e d9086966 .....?..F.....if + 2ce70: 5f6e616d 65000000 1ea40223 00086465 _name......#..de + 2ce80: 765f6164 64720000 001c6902 23400014 v_addr....i.#@.. + 2ce90: 0400001f 100e4144 465f4f53 5f444d41 ......ADF_OS_DMA + 2cea0: 5f4d4153 4b5f3332 42495400 000e4144 _MASK_32BIT...AD + 2ceb0: 465f4f53 5f444d41 5f4d4153 4b5f3634 F_OS_DMA_MASK_64 + 2cec0: 42495400 01000961 64665f6f 735f646d BIT....adf_os_dm + 2ced0: 615f6d61 736b5f74 0000001e d9076164 a_mask_t......ad + 2cee0: 665f646d 615f696e 666f0008 00001f5d f_dma_info.....] + 2cef0: 08646d61 5f6d6173 6b000000 1f100223 .dma_mask......# + 2cf00: 00087367 5f6e7365 67730000 00161d02 ..sg_nsegs...... + 2cf10: 23040014 0400001f b30e4144 465f4e45 #.........ADF_NE + 2cf20: 545f434b 53554d5f 4e4f4e45 00000e41 T_CKSUM_NONE...A + 2cf30: 44465f4e 45545f43 4b53554d 5f544350 DF_NET_CKSUM_TCP + 2cf40: 5f554450 5f495076 3400010e 4144465f _UDP_IPv4...ADF_ + 2cf50: 4e45545f 434b5355 4d5f5443 505f5544 NET_CKSUM_TCP_UD + 2cf60: 505f4950 76360002 00096164 665f6e65 P_IPv6....adf_ne + 2cf70: 745f636b 73756d5f 74797065 5f740000 t_cksum_type_t.. + 2cf80: 001f5d12 0800001f f6087478 5f636b73 ..].......tx_cks + 2cf90: 756d0000 001fb302 23000872 785f636b um......#..rx_ck + 2cfa0: 73756d00 00001fb3 02230400 09616466 sum......#...adf + 2cfb0: 5f6e6574 5f636b73 756d5f69 6e666f5f _net_cksum_info_ + 2cfc0: 74000000 1fcd1404 0000204f 0e414446 t......... O.ADF + 2cfd0: 5f4e4554 5f54534f 5f4e4f4e 4500000e _NET_TSO_NONE... + 2cfe0: 4144465f 4e45545f 54534f5f 49505634 ADF_NET_TSO_IPV4 + 2cff0: 00010e41 44465f4e 45545f54 534f5f41 ...ADF_NET_TSO_A + 2d000: 4c4c0002 00096164 665f6e65 745f7473 LL....adf_net_ts + 2d010: 6f5f7479 70655f74 00000020 10121000 o_type_t... .... + 2d020: 0020a308 636b7375 6d5f6361 70000000 . ..cksum_cap... + 2d030: 1ff60223 00087473 6f000000 204f0223 ...#..tso... O.# + 2d040: 0808766c 616e5f73 7570706f 72746564 ..vlan_supported + 2d050: 00000016 8402230c 00122000 00213c08 ......#... ..!<. + 2d060: 74785f70 61636b65 74730000 00161d02 tx_packets...... + 2d070: 23000872 785f7061 636b6574 73000000 #..rx_packets... + 2d080: 161d0223 04087478 5f627974 65730000 ...#..tx_bytes.. + 2d090: 00161d02 23080872 785f6279 74657300 ....#..rx_bytes. + 2d0a0: 0000161d 02230c08 74785f64 726f7070 .....#..tx_dropp + 2d0b0: 65640000 00161d02 23100872 785f6472 ed......#..rx_dr + 2d0c0: 6f707065 64000000 161d0223 14087278 opped......#..rx + 2d0d0: 5f657272 6f727300 0000161d 02231808 _errors......#.. + 2d0e0: 74785f65 72726f72 73000000 161d0223 tx_errors......# + 2d0f0: 1c000961 64665f6e 65745f65 74686164 ...adf_net_ethad + 2d100: 64725f74 0000001c 76160000 213c0300 dr_t....v...!<.. + 2d110: 00002161 107f0017 6164665f 6e65745f ..!a....adf_net_ + 2d120: 636d645f 6d636164 64720003 04000021 cmd_mcaddr.....! + 2d130: 98086e65 6c656d00 0000161d 02230008 ..nelem......#.. + 2d140: 6d636173 74000000 21530223 04000961 mcast...!S.#...a + 2d150: 64665f6e 65745f63 6d645f6c 696e6b5f df_net_cmd_link_ + 2d160: 696e666f 5f740000 001c1009 6164665f info_t......adf_ + 2d170: 6e65745f 636d645f 706f6c6c 5f696e66 net_cmd_poll_inf + 2d180: 6f5f7400 00001e7e 09616466 5f6e6574 o_t....~.adf_net + 2d190: 5f636d64 5f636b73 756d5f69 6e666f5f _cmd_cksum_info_ + 2d1a0: 74000000 1ff60961 64665f6e 65745f63 t......adf_net_c + 2d1b0: 6d645f72 696e675f 696e666f 5f740000 md_ring_info_t.. + 2d1c0: 001e4209 6164665f 6e65745f 636d645f ..B.adf_net_cmd_ + 2d1d0: 646d615f 696e666f 5f740000 001f2709 dma_info_t....'. + 2d1e0: 6164665f 6e65745f 636d645f 7669645f adf_net_cmd_vid_ + 2d1f0: 74000000 1cac0961 64665f6e 65745f63 t......adf_net_c + 2d200: 6d645f6f 66666c6f 61645f63 61705f74 md_offload_cap_t + 2d210: 00000020 67096164 665f6e65 745f636d ... g.adf_net_cm + 2d220: 645f7374 6174735f 74000000 20a30961 d_stats_t... ..a + 2d230: 64665f6e 65745f63 6d645f6d 63616464 df_net_cmd_mcadd + 2d240: 725f7400 00002161 0d616466 5f6e6574 r_t...!a.adf_net + 2d250: 5f636d64 5f6d6361 73745f63 61700004 _cmd_mcast_cap.. + 2d260: 000022da 0e414446 5f4e4554 5f4d4341 .."..ADF_NET_MCA + 2d270: 53545f53 55500000 0e414446 5f4e4554 ST_SUP...ADF_NET + 2d280: 5f4d4341 53545f4e 4f545355 50000100 _MCAST_NOTSUP... + 2d290: 09616466 5f6e6574 5f636d64 5f6d6361 .adf_net_cmd_mca + 2d2a0: 73745f63 61705f74 00000022 92180304 st_cap_t...".... + 2d2b0: 000023ac 086c696e 6b5f696e 666f0000 ..#..link_info.. + 2d2c0: 00219802 23000870 6f6c6c5f 696e666f .!..#..poll_info + 2d2d0: 00000021 b5022300 08636b73 756d5f69 ...!..#..cksum_i + 2d2e0: 6e666f00 000021d2 02230008 72696e67 nfo...!..#..ring + 2d2f0: 5f696e66 6f000000 21f00223 0008646d _info...!..#..dm + 2d300: 615f696e 666f0000 00220d02 23000876 a_info..."..#..v + 2d310: 69640000 00222902 2300086f 66666c6f id...").#..offlo + 2d320: 61645f63 61700000 00224002 23000873 ad_cap..."@.#..s + 2d330: 74617473 00000022 5f022300 086d6361 tats..."_.#..mca + 2d340: 73745f69 6e666f00 00002278 02230008 st_info..."x.#.. + 2d350: 6d636173 745f6361 70000000 22da0223 mcast_cap..."..# + 2d360: 00001404 00002403 0e414446 5f4e4255 ......$..ADF_NBU + 2d370: 465f5258 5f434b53 554d5f4e 4f4e4500 F_RX_CKSUM_NONE. + 2d380: 000e4144 465f4e42 55465f52 585f434b ..ADF_NBUF_RX_CK + 2d390: 53554d5f 48570001 0e414446 5f4e4255 SUM_HW...ADF_NBU + 2d3a0: 465f5258 5f434b53 554d5f55 4e4e4543 F_RX_CKSUM_UNNEC + 2d3b0: 45535341 52590002 00096164 665f6e62 ESSARY....adf_nb + 2d3c0: 75665f72 785f636b 73756d5f 74797065 uf_rx_cksum_type + 2d3d0: 5f740000 0023ac12 08000024 43087265 _t...#.....$C.re + 2d3e0: 73756c74 00000024 03022300 0876616c sult...$..#..val + 2d3f0: 00000016 1d022304 00120800 00247308 ......#......$s. + 2d400: 74797065 00000020 4f022300 086d7373 type... O.#..mss + 2d410: 0000001c ac022304 08686472 5f6f6666 ......#..hdr_off + 2d420: 00000016 84022306 00075f5f 6164665f ......#...__adf_ + 2d430: 6e627566 5f716865 6164000c 000024b2 nbuf_qhead....$. + 2d440: 08686561 64000000 143d0223 00087461 .head....=.#..ta + 2d450: 696c0000 00143d02 23040871 6c656e00 il....=.#..qlen. + 2d460: 0000161d 02230800 095f5f61 64665f6e .....#...__adf_n + 2d470: 6275665f 74000000 143d0300 00169304 buf_t....=...... + 2d480: 00030000 161d0400 02010600 00131f01 ................ + 2d490: 06000016 1d010600 00169301 06000016 ................ + 2d4a0: 93010300 00130004 00095f5f 6164665f ..........__adf_ + 2d4b0: 6e627566 5f716865 61645f74 00000024 nbuf_qhead_t...$ + 2d4c0: 73095f5f 6164665f 6e627566 5f717565 s.__adf_nbuf_que + 2d4d0: 75655f74 00000024 f3030000 250b0400 ue_t...$....%... + 2d4e0: 06000024 b2010600 0024b201 14040000 ...$.....$...... + 2d4f0: 262b0e41 5f535441 5455535f 4f4b0000 &+.A_STATUS_OK.. + 2d500: 0e415f53 54415455 535f4641 494c4544 .A_STATUS_FAILED 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04000026 900e4144 465f4f53 5f444d41 ...&..ADF_OS_DMA + 2d620: 5f544f5f 44455649 43450000 0e414446 _TO_DEVICE...ADF + 2d630: 5f4f535f 444d415f 46524f4d 5f444556 _OS_DMA_FROM_DEV + 2d640: 49434500 01000961 64665f6f 735f646d ICE....adf_os_dm + 2d650: 615f6469 725f7400 00002659 06000026 a_dir_t...&Y...& + 2d660: 2b010201 09616466 5f6f735f 646d616d +....adf_os_dmam + 2d670: 61705f69 6e666f5f 74000000 163a0300 ap_info_t....:.. + 2d680: 0026ae04 00020102 01060000 26490106 .&..........&I.. + 2d690: 000024b2 01020102 01060000 26490106 ..$.........&I.. + 2d6a0: 000024b2 01060000 26490106 000024b2 ..$.....&I....$. + 2d6b0: 01060000 26490102 01020106 0000161d ....&I.......... + 2d6c0: 01060000 16930102 01020106 00001b4a ...............J + 2d6d0: 01060000 1a970106 00001a97 01096164 ..............ad + 2d6e0: 665f6f73 5f73676c 6973745f 74000000 f_os_sglist_t... + 2d6f0: 16d20300 00272704 00020102 01020106 .....''......... + 2d700: 00001693 01096164 665f6e62 75665f71 ......adf_nbuf_q + 2d710: 75657565 5f740000 00250b03 0000274f ueue_t...%....'O + 2d720: 04000201 03000024 f3040002 01020102 .......$........ + 2d730: 01060000 26490106 000024b2 01060000 ....&I....$..... + 2d740: 161d0106 0000161d 01060000 1a970106 ................ + 2d750: 00001a97 01060000 1fb30106 0000161d ................ + 2d760: 01096164 665f6e62 75665f72 785f636b ..adf_nbuf_rx_ck + 2d770: 73756d5f 74000000 24210300 0027ab04 sum_t...$!...'.. + 2d780: 00020102 01096164 665f6e62 75665f74 ......adf_nbuf_t + 2d790: 736f5f74 00000024 43030000 27cf0400 so_t...$C...'... + 2d7a0: 02010201 09616466 5f6e6574 5f68616e .....adf_net_han + 2d7b0: 646c655f 74000000 040d0961 64665f6e dle_t......adf_n + 2d7c0: 65745f76 6c616e68 64725f74 0000001d et_vlanhdr_t.... + 2d7d0: bf030000 28040400 06000026 2b010600 ....(......&+... + 2d7e0: 00262b01 02010201 075f4849 465f434f .&+......_HIF_CO + 2d7f0: 4e464947 00040000 28530864 756d6d79 NFIG....(S.dummy + 2d800: 00000001 18022300 00020103 00002853 ......#.......(S + 2d810: 04000201 03000028 5c040007 5f484946 .......(\..._HIF + 2d820: 5f43414c 4c424143 4b000c00 0028b108 _CALLBACK....(.. + 2d830: 73656e64 5f627566 5f646f6e 65000000 send_buf_done... + 2d840: 28550223 00087265 63765f62 75660000 (U.#..recv_buf.. + 2d850: 00285e02 23040863 6f6e7465 78740000 .(^.#..context.. + 2d860: 00040d02 23080009 6869665f 68616e64 ....#...hif_hand + 2d870: 6c655f74 00000004 0d094849 465f434f le_t......HIF_CO + 2d880: 4e464947 00000028 32030000 28c30400 NFIG...(2...(... + 2d890: 06000028 b1010300 0028da04 00020103 ...(.....(...... + 2d8a0: 000028e7 04000948 49465f43 414c4c42 ..(....HIF_CALLB + 2d8b0: 41434b00 00002865 03000028 f0040002 ACK...(e...(.... + 2d8c0: 01030000 29090400 06000001 18010300 ....)........... + 2d8d0: 00291204 00020103 0000291f 04000600 .)........)..... + 2d8e0: 00011801 03000029 28040002 01030000 .......)(....... + 2d8f0: 29350400 06000001 18010300 00293e04 )5...........)>. + 2d900: 00020103 0000294b 04000768 69665f61 ......)K...hif_a + 2d910: 70690038 00002aa4 085f696e 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*....cmnos_strin + 2f6b0: 675f6d6f 64756c65 5f696e73 74616c6c g_module_install + 2f6c0: 00010103 92012002 9000008e 2ac4008e ...... .....*... + 2f6d0: 2ae71c01 1274626c 00000046 bd015200 *....tbl...F..R. + 2f6e0: 00000000 48ad0002 000011a4 04012f72 ....H........./r + 2f6f0: 6f6f742f 576f726b 73706163 652f3034 oot/Workspace/04 + 2f700: 31325f76 3230322f 7467742f 6275696c 12_v202/tgt/buil + 2f710: 642f6d61 67706965 5f315f31 2f696d61 d/magpie_1_1/ima + 2f720: 67652f6d 61677069 652f2e2e 2f2e2e2f ge/magpie/../../ + 2f730: 2e2e2f2e 2e2f2f62 75696c64 2f6d6167 ../..//build/mag + 2f740: 7069655f 315f312f 726f6d2f 636d6e6f pie_1_1/rom/cmno + 2f750: 732f7461 736b6c65 742f7372 632f636d s/tasklet/src/cm + 2f760: 6e6f735f 7461736b 6c65742e 63002f72 nos_tasklet.c./r + 2f770: 6f6f742f 576f726b 73706163 652f3034 oot/Workspace/04 + 2f780: 31325f76 3230322f 7467742f 6275696c 12_v202/tgt/buil + 2f790: 642f6d61 67706965 5f315f31 2f726f6d d/magpie_1_1/rom + 2f7a0: 2f636d6e 6f732f74 61736b6c 65740078 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ach_data_t....`. + 30fb0: 000018b3 04000300 0014df04 00095f5f ..............__ + 30fc0: 6164665f 6f735f64 65766963 655f7400 adf_os_device_t. + 30fd0: 000018d4 09616466 5f6f735f 64657669 .....adf_os_devi + 30fe0: 63655f74 00000018 db060000 187f0103 ce_t............ + 30ff0: 00001907 04000201 03000019 14040009 ................ + 31000: 6164665f 6f735f70 6d5f7400 00000410 adf_os_pm_t..... + 31010: 02010300 00192e04 00140400 00196e0e ..............n. + 31020: 4144465f 4f535f42 55535f54 5950455f ADF_OS_BUS_TYPE_ + 31030: 50434900 010e4144 465f4f53 5f425553 PCI...ADF_OS_BUS + 31040: 5f545950 455f4745 4e455249 43000200 _TYPE_GENERIC... + 31050: 09616466 5f6f735f 6275735f 74797065 .adf_os_bus_type + 31060: 5f740000 00193709 6164665f 6f735f62 _t....7.adf_os_b + 31070: 75735f72 65675f64 6174615f 74000000 us_reg_data_t... + 31080: 18410300 00032804 00075f61 64665f64 .A....(..._adf_d + 31090: 72765f69 6e666f00 2000001a 4b086472 rv_info. ...K.dr + 310a0: 765f6174 74616368 00000019 0d022300 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....5.#...short + 38a80: 756e7369 676e6564 20696e74 00070209 unsigned int.... + 38a90: 75696e74 31365f74 00000001 73046c6f uint16_t....s.lo + 38aa0: 6e672075 6e736967 6e656420 696e7400 ng unsigned int. + 38ab0: 07040975 696e7433 325f7400 00000197 ...uint32_t..... + 38ac0: 07756172 745f6669 666f0008 00000205 .uart_fifo...... + 38ad0: 08737461 72745f69 6e646578 00000001 .start_index.... + 38ae0: 89022300 08656e64 5f696e64 65780000 ..#..end_index.. + 38af0: 00018902 2302086f 76657272 756e5f65 ....#..overrun_e + 38b00: 72720000 0001ac02 23040007 75617274 rr......#...uart + 38b10: 5f617069 00200000 02be085f 75617274 _api. ....._uart + 38b20: 5f696e69 74000000 03150223 00085f75 _init......#.._u + 38b30: 6172745f 63686172 5f707574 00000003 art_char_put.... + 38b40: 3c022304 085f7561 72745f63 6861725f <.#.._uart_char_ + 38b50: 67657400 00000350 02230808 5f756172 get....P.#.._uar + 38b60: 745f7374 725f6f75 74000000 03590223 t_str_out....Y.# + 38b70: 0c085f75 6172745f 7461736b 00000001 .._uart_task.... + 38b80: 08022310 085f7561 72745f73 74617475 ..#.._uart_statu + 38b90: 73000000 03150223 14085f75 6172745f s......#.._uart_ + 38ba0: 636f6e66 69670000 00036202 2318085f config....b.#.._ + 38bb0: 75617274 5f687769 6e697400 0000036b uart_hwinit....k + 38bc0: 02231c00 03000002 05040007 75617274 .#..........uart + 38bd0: 5f626c6b 00100000 030f0864 65627567 _blk.......debug + 38be0: 5f6d6f64 65000000 01890223 00086261 _mode......#..ba + 38bf0: 75640000 00018902 2302085f 75617274 ud......#.._uart + 38c00: 00000002 be022304 085f7478 00000001 ......#.._tx.... + 38c10: ba022308 00060000 01ac0103 0000030f ..#............. + 38c20: 04000475 6e736967 6e656420 63686172 ...unsigned char + 38c30: 00070109 75696e74 385f7400 0000031c ....uint8_t..... + 38c40: 02010300 00033a04 00030000 032d0400 ......:......-.. + 38c50: 06000001 89010300 00034a04 00020103 ..........J..... + 38c60: 00000357 04000201 03000003 60040002 ...W........`... + 38c70: 01030000 03690400 03000001 16040006 .....i.......... + 38c80: 0000010f 01030000 03790400 0744425f .........y...DB_ + 38c90: 434f4d4d 414e445f 53545255 4354000c COMMAND_STRUCT.. + 38ca0: 000003d1 08636d64 5f737472 00000003 .....cmd_str.... + 38cb0: 72022300 0868656c 705f7374 72000000 r.#..help_str... + 38cc0: 03720223 0408636d 645f6675 6e630000 .r.#..cmd_func.. + 38cd0: 00037f02 23080007 6462675f 61706900 ....#...dbg_api. + 38ce0: 08000004 04085f64 62675f69 6e697400 ......_dbg_init. + 38cf0: 00000108 02230008 5f646267 5f746173 .....#.._dbg_tas + 38d00: 6b000000 01080223 04000a04 0004756e k......#......un + 38d10: 7369676e 65642069 6e740007 04060000 signed int...... + 38d20: 04040103 00000417 04000b0b 03000004 ................ + 38d30: 25040006 00000404 01030000 042d0400 %............-.. + 38d40: 06000001 0f010300 00043a04 00076d65 ..........:...me + 38d50: 6d5f6170 69001400 0004a908 5f6d656d m_api......._mem + 38d60: 5f696e69 74000000 01080223 00085f6d _init......#.._m + 38d70: 656d7365 74000000 041d0223 04085f6d emset......#.._m + 38d80: 656d6370 79000000 04330223 08085f6d emcpy....3.#.._m + 38d90: 656d6d6f 76650000 00043302 230c085f emmove....3.#.._ + 38da0: 6d656d63 6d700000 00044002 2310000c memcmp....@.#... + 38db0: 72656769 73746572 5f64756d 705f7300 register_dump_s. + 38dc0: 00010300 0004a904 00020103 000004c3 ................ + 38dd0: 04000201 03000004 cc040006 0000010f ................ + 38de0: 01030000 04d50400 0d686f73 7469665f .........hostif_ + 38df0: 73000400 0005310e 4849465f 55534200 s.....1.HIF_USB. + 38e00: 000e4849 465f5043 49450001 0e484946 ..HIF_PCIE...HIF + 38e10: 5f474d41 4300020e 4849465f 50434900 _GMAC...HIF_PCI. + 38e20: 030e4849 465f4e55 4d00040e 4849465f ..HIF_NUM...HIF_ + 38e30: 4e4f4e45 00050009 415f484f 53544946 NONE....A_HOSTIF + 38e40: 00000004 e2060000 05310103 0000053f .........1.....? + 38e50: 04000600 00032d01 03000005 4c040006 ......-.....L... + 38e60: 00000189 01030000 05590400 076d6973 .........Y...mis + 38e70: 635f6170 69002400 00064908 5f737973 c_api.$...I._sys + 38e80: 74656d5f 72657365 74000000 01080223 tem_reset......# + 38e90: 00085f6d 61635f72 65736574 00000001 .._mac_reset.... + 38ea0: 08022304 085f6173 73666169 6c000000 ..#.._assfail... + 38eb0: 04c50223 08085f6d 6973616c 69676e65 ...#.._misaligne + 38ec0: 645f6c6f 61645f68 616e646c 65720000 d_load_handler.. + 38ed0: 0004c502 230c085f 7265706f 72745f66 ....#.._report_f + 38ee0: 61696c75 72655f74 6f5f686f 73740000 ailure_to_host.. + 38ef0: 0004ce02 2310085f 74617267 65745f69 ....#.._target_i + 38f00: 645f6765 74000000 04db0223 14085f69 d_get......#.._i + 38f10: 735f686f 73745f70 72657365 6e740000 s_host_present.. + 38f20: 00054502 2318085f 6b626869 74000000 ..E.#.._kbhit... + 38f30: 05520223 1c085f72 6f6d5f76 65727369 .R.#.._rom_versi + 38f40: 6f6e5f67 65740000 00055f02 23200006 on_get...._.# .. + 38f50: 00000372 01030000 06490400 06000003 ...r.....I...... + 38f60: 72010300 00065604 00060000 010f0103 r.....V......... + 38f70: 00000663 04000600 00010f01 03000006 ...c............ + 38f80: 70040006 0000010f 01030000 067d0400 p............}.. + 38f90: 07737472 696e675f 61706900 18000007 .string_api..... + 38fa0: 03085f73 7472696e 675f696e 69740000 .._string_init.. + 38fb0: 00010802 2300085f 73747263 70790000 ....#.._strcpy.. + 38fc0: 00064f02 2304085f 7374726e 63707900 ..O.#.._strncpy. + 38fd0: 0000065c 02230808 5f737472 6c656e00 ...\.#.._strlen. + 38fe0: 00000669 02230c08 5f737472 636d7000 ...i.#.._strcmp. + 38ff0: 00000676 02231008 5f737472 6e636d70 ...v.#.._strncmp + 39000: 00000006 83022314 000f0000 04071400 ......#......... + 39010: 00071010 0400095f 415f5449 4d45525f ......._A_TIMER_ + 39020: 53504143 45000000 07030941 5f74696d SPACE......A_tim + 39030: 65725f74 00000007 10030000 07240400 er_t.........$.. + 39040: 02010300 00073a04 00020103 00000743 ......:........C + 39050: 04000941 5f48414e 444c4500 00000407 ...A_HANDLE..... + 39060: 02010941 5f54494d 45525f46 554e4300 ...A_TIMER_FUNC. + 39070: 0000075a 03000007 5c040002 01030000 ...Z....\....... + 39080: 07750400 0774696d 65725f61 70690014 .u...timer_api.. + 39090: 000007f4 085f7469 6d65725f 696e6974 ....._timer_init + 390a0: 00000001 08022300 085f7469 6d65725f ......#.._timer_ + 390b0: 61726d00 0000073c 02230408 5f74696d arm....<.#.._tim + 390c0: 65725f64 69736172 6d000000 07450223 er_disarm....E.# + 390d0: 08085f74 696d6572 5f736574 666e0000 .._timer_setfn.. + 390e0: 00077702 230c085f 74696d65 725f7275 ..w.#.._timer_ru + 390f0: 6e000000 01080223 10000942 4f4f4c45 n......#...BOOLE + 39100: 414e0000 00018906 000007f4 01030000 AN.............. + 39110: 08010400 06000007 f4010300 00080e04 ................ + 39120: 00060000 07f40103 0000081b 04000772 ...............r + 39130: 6f6d705f 61706900 10000008 8d085f72 omp_api......._r + 39140: 6f6d705f 696e6974 00000001 08022300 omp_init......#. + 39150: 085f726f 6d705f64 6f776e6c 6f616400 ._romp_download. + 39160: 00000807 02230408 5f726f6d 705f696e .....#.._romp_in + 39170: 7374616c 6c000000 08140223 08085f72 stall......#.._r + 39180: 6f6d705f 6465636f 64650000 00082102 omp_decode....!. + 39190: 230c0007 726f6d5f 70617463 685f7374 #...rom_patch_st + 391a0: 00100000 08e90863 72633136 00000001 .......crc16.... + 391b0: 89022300 086c656e 00000001 89022302 ..#..len......#. + 391c0: 086c645f 61646472 00000001 ac022304 .ld_addr......#. + 391d0: 0866756e 5f616464 72000000 01ac0223 .fun_addr......# + 391e0: 08087066 756e0000 00034302 230c0007 ..pfun....C.#... + 391f0: 6565705f 72656469 725f6164 64720004 eep_redir_addr.. + 39200: 0000091b 086f6666 73657400 00000189 .....offset..... + 39210: 02230008 73697a65 00000001 89022302 .#..size......#. + 39220: 0009415f 55494e54 33320000 00040706 ..A_UINT32...... + 39230: 00000404 01030000 09290400 07616c6c .........)...all + 39240: 6f637261 6d5f6170 69000c00 00099a08 ocram_api....... + 39250: 636d6e6f 735f616c 6c6f6372 616d5f69 cmnos_allocram_i + 39260: 6e697400 0000092f 02230008 636d6e6f nit..../.#..cmno + 39270: 735f616c 6c6f6372 616d0000 00092f02 s_allocram..../. + 39280: 23040863 6d6e6f73 5f616c6c 6f637261 #..cmnos_allocra + 39290: 6d5f6465 62756700 00000108 02230800 m_debug......#.. + 392a0: 02010300 00099a04 0009415f 5441534b ..........A_TASK + 392b0: 4c45545f 46554e43 00000009 9c075f74 LET_FUNC......_t + 392c0: 61736b6c 65740010 000009fb 0866756e asklet.......fun + 392d0: 63000000 09a30223 00086172 67000000 c......#..arg... + 392e0: 04040223 04087374 61746500 0000010f ...#..state..... + 392f0: 02230808 6e657874 00000009 fb02230c .#..next......#. + 39300: 00030000 09b70400 03000009 b7040009 ................ + 39310: 415f7461 736b6c65 745f7400 000009b7 A_tasklet_t..... + 39320: 0300000a 09040002 01030000 0a210400 .............!.. + 39330: 02010300 000a2a04 00077461 736b6c65 ......*...taskle + 39340: 745f6170 69001400 000abf08 5f746173 t_api......._tas + 39350: 6b6c6574 5f696e69 74000000 01080223 klet_init......# + 39360: 00085f74 61736b6c 65745f69 6e69745f .._tasklet_init_ + 39370: 7461736b 0000000a 23022304 085f7461 task....#.#.._ta + 39380: 736b6c65 745f6469 7361626c 65000000 sklet_disable... + 39390: 0a2c0223 08085f74 61736b6c 65745f73 .,.#.._tasklet_s + 393a0: 63686564 756c6500 00000a2c 02230c08 chedule....,.#.. + 393b0: 5f746173 6b6c6574 5f72756e 00000001 _tasklet_run.... + 393c0: 08022310 00020103 00000abf 04000600 ..#............. + 393d0: 00091b01 0300000a c8040002 01030000 ................ + 393e0: 0ad50400 07636c6f 636b5f61 70690024 .....clock_api.$ + 393f0: 00000bb7 085f636c 6f636b5f 696e6974 ....._clock_init + 39400: 0000000a c1022300 085f636c 6f636b72 ......#.._clockr + 39410: 6567735f 696e6974 00000001 08022304 egs_init......#. + 39420: 085f7561 72745f66 72657175 656e6379 ._uart_frequency + 39430: 0000000a ce022308 085f6465 6c61795f ......#.._delay_ + 39440: 75730000 000ad702 230c085f 776c616e us......#.._wlan + 39450: 5f62616e 645f7365 74000000 0ad70223 _band_set......# + 39460: 10085f72 6566636c 6b5f7370 6565645f .._refclk_speed_ + 39470: 67657400 00000ace 02231408 5f6d696c get......#.._mil + 39480: 6c697365 636f6e64 73000000 0ace0223 liseconds......# + 39490: 18085f73 7973636c 6b5f6368 616e6765 .._sysclk_change + 394a0: 00000001 0802231c 085f636c 6f636b5f ......#.._clock_ + 394b0: 7469636b 00000001 08022320 00060000 tick......# .... + 394c0: 01ac0103 00000bb7 04000941 5f6f6c64 ...........A_old + 394d0: 5f696e74 725f7400 000001ac 0600000b _intr_t......... + 394e0: c4010300 000bd604 00020103 00000be3 ................ + 394f0: 04000201 0300000b ec040006 000001ac ................ + 39500: 01030000 0bf50400 09415f69 73725f74 .........A_isr_t + 39510: 0000000b fb020103 00000c0f 04000600 ................ + 39520: 00040701 0300000c 18040002 01030000 ................ + 39530: 0c250400 07696e74 725f6170 69002c00 .%...intr_api.,. + 39540: 000d4708 5f696e74 725f696e 69740000 ..G._intr_init.. + 39550: 00010802 2300085f 696e7472 5f696e76 ....#.._intr_inv + 39560: 6f6b655f 69737200 00000bbd 02230408 oke_isr......#.. + 39570: 5f696e74 725f6469 7361626c 65000000 _intr_disable... + 39580: 0bdc0223 08085f69 6e74725f 72657374 ...#.._intr_rest + 39590: 6f726500 00000be5 02230c08 5f696e74 ore......#.._int + 395a0: 725f6d61 736b5f69 6e756d00 00000bee r_mask_inum..... + 395b0: 02231008 5f696e74 725f756e 6d61736b .#.._intr_unmask + 395c0: 5f696e75 6d000000 0bee0223 14085f69 _inum......#.._i + 395d0: 6e74725f 61747461 63685f69 73720000 ntr_attach_isr.. + 395e0: 000c1102 2318085f 6765745f 696e7472 ....#.._get_intr + 395f0: 656e6162 6c650000 000c1e02 231c085f enable......#.._ + 39600: 7365745f 696e7472 656e6162 6c650000 set_intrenable.. + 39610: 000c2702 2320085f 6765745f 696e7472 ..'.# ._get_intr + 39620: 70656e64 696e6700 00000c1e 02232408 pending......#$. + 39630: 5f756e62 6c6f636b 5f616c6c 5f696e74 _unblock_all_int + 39640: 726c766c 00000001 08022328 00110400 rlvl......#(.... + 39650: 000d6d08 74696d65 6f757400 000001ac ..m.timeout..... + 39660: 02230008 61637469 6f6e0000 0001ac02 .#..action...... + 39670: 23000012 0800000d 8808636d 64000000 #.........cmd... + 39680: 01ac0223 00130000 0d470223 04000954 ...#.....G.#...T + 39690: 5f574454 5f434d44 0000000d 6d020103 _WDT_CMD....m... + 396a0: 00000d97 04001404 00000ded 0e454e55 .............ENU + 396b0: 4d5f5744 545f424f 4f540001 0e454e55 M_WDT_BOOT...ENU + 396c0: 4d5f434f 4c445f42 4f4f5400 020e454e M_COLD_BOOT...EN + 396d0: 554d5f53 5553505f 424f4f54 00030e45 UM_SUSP_BOOT...E + 396e0: 4e554d5f 554e4b4e 4f574e5f 424f4f54 NUM_UNKNOWN_BOOT + 396f0: 00040009 545f424f 4f545f54 59504500 ....T_BOOT_TYPE. + 39700: 00000da0 0600000d ed010300 000dfe04 ................ + 39710: 00077764 745f6170 69001c00 000ea208 ..wdt_api....... + 39720: 5f776474 5f696e69 74000000 01080223 _wdt_init......# + 39730: 00085f77 64745f65 6e61626c 65000000 .._wdt_enable... + 39740: 01080223 04085f77 64745f64 69736162 ...#.._wdt_disab + 39750: 6c650000 00010802 2308085f 7764745f le......#.._wdt_ + 39760: 73657400 00000d99 02230c08 5f776474 set......#.._wdt + 39770: 5f746173 6b000000 01080223 10085f77 _task......#.._w + 39780: 64745f72 65736574 00000001 08022314 dt_reset......#. + 39790: 085f7764 745f6c61 73745f62 6f6f7400 ._wdt_last_boot. + 397a0: 00000e04 02231800 14040000 0f090e52 .....#.........R + 397b0: 45545f53 55434345 53530000 0e524554 ET_SUCCESS...RET + 397c0: 5f4e4f54 5f494e49 5400010e 5245545f _NOT_INIT...RET_ + 397d0: 4e4f545f 45584953 5400020e 5245545f NOT_EXIST...RET_ + 397e0: 4545505f 434f5252 55505400 030e5245 EEP_CORRUPT...RE + 397f0: 545f4545 505f4f56 4552464c 4f570004 T_EEP_OVERFLOW.. + 39800: 0e524554 5f554e4b 4e4f574e 00050009 .RET_UNKNOWN.... + 39810: 545f4545 505f5245 54000000 0ea20300 T_EEP_RET....... + 39820: 00018904 00060000 0f090103 00000f1f ................ + 39830: 04000600 000f0901 0300000f 2c040007 ............,... + 39840: 6565705f 61706900 1000000f 95085f65 eep_api......._e + 39850: 65705f69 6e697400 00000108 02230008 ep_init......#.. + 39860: 5f656570 5f726561 64000000 0f250223 _eep_read....%.# + 39870: 04085f65 65705f77 72697465 0000000f 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...._wdt_init... + 3e070: 01090223 00085f77 64745f65 6e61626c ...#.._wdt_enabl + 3e080: 65000000 01090223 04085f77 64745f64 e......#.._wdt_d + 3e090: 69736162 6c650000 00010902 2308085f isable......#.._ + 3e0a0: 7764745f 73657400 00000d9a 02230c08 wdt_set......#.. + 3e0b0: 5f776474 5f746173 6b000000 01090223 _wdt_task......# + 3e0c0: 10085f77 64745f72 65736574 00000001 .._wdt_reset.... + 3e0d0: 09022314 085f7764 745f6c61 73745f62 ..#.._wdt_last_b + 3e0e0: 6f6f7400 00000e05 02231800 14040000 oot......#...... + 3e0f0: 0f0a0e52 45545f53 55434345 53530000 ...RET_SUCCESS.. + 3e100: 0e524554 5f4e4f54 5f494e49 5400010e .RET_NOT_INIT... + 3e110: 5245545f 4e4f545f 45584953 5400020e RET_NOT_EXIST... + 3e120: 5245545f 4545505f 434f5252 55505400 RET_EEP_CORRUPT. + 3e130: 030e5245 545f4545 505f4f56 4552464c ..RET_EEP_OVERFL + 3e140: 4f570004 0e524554 5f554e4b 4e4f574e OW...RET_UNKNOWN + 3e150: 00050009 545f4545 505f5245 54000000 ....T_EEP_RET... + 3e160: 0ea30300 00018a04 00060000 0f0a0103 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adf_os_pci_dev_i + 3ea70: 645f7400 000016fd 03000018 16040011 d_t............. + 3ea80: 04000018 55087063 69000000 182f0223 ....U.pci..../.# + 3ea90: 00087261 77000000 04050223 00001110 ..raw......#.... + 3eaa0: 00001874 08706369 00000018 16022300 ...t.pci......#. + 3eab0: 08726177 00000004 05022300 00096164 .raw......#...ad + 3eac0: 665f6472 765f6861 6e646c65 5f740000 f_drv_handle_t.. + 3ead0: 00040509 6164665f 6f735f72 65736f75 ....adf_os_resou + 3eae0: 7263655f 74000000 17e80300 00188a04 rce_t........... + 3eaf0: 00096164 665f6f73 5f617474 6163685f ..adf_os_attach_ + 3eb00: 64617461 5f740000 00185503 000018a8 data_t....U..... + 3eb10: 04000300 0014d404 00095f5f 6164665f ..........__adf_ + 3eb20: 6f735f64 65766963 655f7400 000018c9 os_device_t..... + 3eb30: 09616466 5f6f735f 64657669 63655f74 .adf_os_device_t + 3eb40: 00000018 d0060000 18740103 000018fc .........t...... + 3eb50: 04000201 03000019 09040009 6164665f ............adf_ + 3eb60: 6f735f70 6d5f7400 00000405 02010300 os_pm_t......... + 3eb70: 00192304 00140400 0019630e 4144465f ..#.......c.ADF_ + 3eb80: 4f535f42 55535f54 5950455f 50434900 OS_BUS_TYPE_PCI. + 3eb90: 010e4144 465f4f53 5f425553 5f545950 ..ADF_OS_BUS_TYP + 3eba0: 455f4745 4e455249 43000200 09616466 E_GENERIC....adf + 3ebb0: 5f6f735f 6275735f 74797065 5f740000 _os_bus_type_t.. + 3ebc0: 00192c09 6164665f 6f735f62 75735f72 ..,.adf_os_bus_r + 3ebd0: 65675f64 6174615f 74000000 18360300 eg_data_t....6.. + 3ebe0: 00031d04 00075f61 64665f64 72765f69 ......_adf_drv_i + 3ebf0: 6e666f00 2000001a 40086472 765f6174 nfo. ...@.drv_at + 3ec00: 74616368 00000019 02022300 08647276 tach......#..drv + 3ec10: 5f646574 61636800 0000190b 02230408 _detach......#.. + 3ec20: 6472765f 73757370 656e6400 00001925 drv_suspend....% + 3ec30: 02230808 6472765f 72657375 6d650000 .#..drv_resume.. + 3ec40: 00190b02 230c0862 75735f74 79706500 ....#..bus_type. + 3ec50: 00001963 02231008 6275735f 64617461 ...c.#..bus_data + 3ec60: 00000019 7a022314 086d6f64 5f6e616d ....z.#..mod_nam + 3ec70: 65000000 19950223 18086966 6e616d65 e......#..ifname + 3ec80: 00000019 9502231c 00096164 665f6f73 ......#...adf_os + 3ec90: 5f68616e 646c655f 74000000 04050300 _handle_t....... + 3eca0: 00166b04 00020102 01095f5f 6164665f ..k.......__adf_ + 3ecb0: 6f735f73 697a655f 74000000 04081404 os_size_t....... + 3ecc0: 00001a8f 0e415f46 414c5345 00000e41 .....A_FALSE...A + 3ecd0: 5f545255 45000100 09615f62 6f6f6c5f _TRUE....a_bool_ + 3ece0: 74000000 1a750300 0014fd04 00095f5f t....u........__ + 3ecf0: 6164665f 6f735f64 6d615f6d 61705f74 adf_os_dma_map_t + 3ed00: 0000001a 9d02010d 6164665f 6f735f63 ........adf_os_c + 3ed10: 61636865 5f73796e 63000400 001b270e ache_sync.....'. + 3ed20: 4144465f 53594e43 5f505245 52454144 ADF_SYNC_PREREAD + 3ed30: 00000e41 44465f53 594e435f 50524557 ...ADF_SYNC_PREW + 3ed40: 52495445 00020e41 44465f53 594e435f RITE...ADF_SYNC_ + 3ed50: 504f5354 52454144 00010e41 44465f53 POSTREAD...ADF_S + 3ed60: 594e435f 504f5354 57524954 45000300 YNC_POSTWRITE... + 3ed70: 09616466 5f6f735f 63616368 655f7379 .adf_os_cache_sy + 3ed80: 6e635f74 0000001a be020109 6164665f nc_t........adf_ + 3ed90: 6f735f73 697a655f 74000000 1a600600 os_size_t....`.. + 3eda0: 001b4201 09616466 5f6f735f 646d615f ..B..adf_os_dma_ + 3edb0: 6d61705f 74000000 1aa40300 001b5b04 map_t.........[. + 3edc0: 00060000 04050103 00001aa4 04000600 ................ + 3edd0: 00040501 02010600 00159001 02010473 ...............s + 3ede0: 686f7274 20696e74 00050209 415f494e hort int....A_IN + 3edf0: 54313600 00001b95 095f5f61 5f696e74 T16......__a_int + 3ee00: 31365f74 0000001b a209615f 696e7431 16_t......a_int1 + 3ee10: 365f7400 00001baf 04736967 6e656420 6_t......signed + 3ee20: 63686172 00050109 415f494e 54380000 char....A_INT8.. + 3ee30: 001bcf09 5f5f615f 696e7438 5f740000 ....__a_int8_t.. + 3ee40: 001bde09 615f696e 74385f74 0000001b ....a_int8_t.... + 3ee50: ea120c00 001c6108 73757070 6f727465 ......a.supporte + 3ee60: 64000000 16150223 00086164 76657274 d......#..advert + 3ee70: 697a6564 00000016 15022304 08737065 ized......#..spe + 3ee80: 65640000 001bc002 23080864 75706c65 ed......#..duple + 3ee90: 78000000 1bfa0223 0a086175 746f6e65 x......#..autone + 3eea0: 67000000 167c0223 0b000f00 00167c06 g....|.#......|. + 3eeb0: 00001c6e 10050007 6164665f 6e65745f ...n....adf_net_ + 3eec0: 65746861 64647200 0600001c 92086164 ethaddr.......ad + 3eed0: 64720000 001c6102 23000009 5f5f615f dr....a.#...__a_ + 3eee0: 75696e74 31365f74 00000012 ea09615f uint16_t......a_ + 3eef0: 75696e74 31365f74 0000001c 92120e00 uint16_t........ + 3ef00: 001cf608 65746865 725f6468 6f737400 ....ether_dhost. + 3ef10: 00001c61 02230008 65746865 725f7368 ...a.#..ether_sh + 3ef20: 6f737400 00001c61 02230608 65746865 ost....a.#..ethe + 3ef30: 725f7479 70650000 001ca402 230c0012 r_type......#... + 3ef40: 1400001d b7156970 5f766572 73696f6e ......ip_version + 3ef50: 00000016 7c010004 02230015 69705f68 ....|....#..ip_h + 3ef60: 6c000000 167c0104 04022300 0869705f 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..........A_HAND + 43bb0: 4c450000 0003ea09 0106415f 54494d45 LE........A_TIME + 43bc0: 525f4655 4e430000 001fc104 00001fc3 R_FUNC.......... + 43bd0: 04000901 0400001f dc040002 74696d65 ............time + 43be0: 725f6170 69001400 00205b03 5f74696d r_api.... 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p_check......#.. + 48770: 69705f73 61646472 00000016 0e02230c ip_saddr......#. + 48780: 0869705f 64616464 72000000 160e0223 .ip_daddr......# + 48790: 10000761 64665f6e 65745f76 6c616e68 ...adf_net_vlanh + 487a0: 64720004 00001e02 08747069 64000000 dr.......tpid... + 487b0: 1c9d0223 00157072 696f0000 00167501 ...#..prio....u. + 487c0: 00030223 02156366 69000000 16750103 ...#..cfi....u.. + 487d0: 01022302 15766964 0000001c 9d02040c ..#..vid........ + 487e0: 02230200 07616466 5f6e6574 5f766964 .#...adf_net_vid + 487f0: 00020000 1e331572 65730000 00167501 .....3.res....u. + 48800: 00040223 00157661 6c000000 1c9d0204 ...#..val....... + 48810: 0c022300 00120c00 001e6f08 72785f62 ..#.......o.rx_b + 48820: 75667369 7a650000 00160e02 23000872 ufsize......#..r + 48830: 785f6e64 65736300 0000160e 02230408 x_ndesc......#.. + 48840: 74785f6e 64657363 00000016 0e022308 tx_ndesc......#. + 48850: 00120800 001e9508 706f6c6c 65640000 ........polled.. + 48860: 001a8802 23000870 6f6c6c5f 77740000 ....#..poll_wt.. + 48870: 00160e02 2304000f 00001675 4000001e ....#......u@... + 48880: a2103f00 12460000 1eca0869 665f6e61 ..?..F.....if_na + 48890: 6d650000 001e9502 23000864 65765f61 me......#..dev_a + 488a0: 64647200 00001c5a 02234000 14040000 ddr....Z.#@..... + 488b0: 1f010e41 44465f4f 535f444d 415f4d41 ...ADF_OS_DMA_MA + 488c0: 534b5f33 32424954 00000e41 44465f4f SK_32BIT...ADF_O + 488d0: 535f444d 415f4d41 534b5f36 34424954 S_DMA_MASK_64BIT + 488e0: 00010009 6164665f 6f735f64 6d615f6d ....adf_os_dma_m + 488f0: 61736b5f 74000000 1eca0761 64665f64 ask_t......adf_d + 48900: 6d615f69 6e666f00 0800001f 4e08646d ma_info.....N.dm + 48910: 615f6d61 736b0000 001f0102 23000873 a_mask......#..s + 48920: 675f6e73 65677300 0000160e 02230400 g_nsegs......#.. + 48930: 14040000 1fa40e41 44465f4e 45545f43 .......ADF_NET_C + 48940: 4b53554d 5f4e4f4e 4500000e 4144465f KSUM_NONE...ADF_ + 48950: 4e45545f 434b5355 4d5f5443 505f5544 NET_CKSUM_TCP_UD + 48960: 505f4950 76340001 0e414446 5f4e4554 P_IPv4...ADF_NET + 48970: 5f434b53 554d5f54 43505f55 44505f49 _CKSUM_TCP_UDP_I + 48980: 50763600 02000961 64665f6e 65745f63 Pv6....adf_net_c + 48990: 6b73756d 5f747970 655f7400 00001f4e ksum_type_t....N + 489a0: 12080000 1fe70874 785f636b 73756d00 .......tx_cksum. + 489b0: 00001fa4 02230008 72785f63 6b73756d .....#..rx_cksum + 489c0: 0000001f a4022304 00096164 665f6e65 ......#...adf_ne + 489d0: 745f636b 73756d5f 696e666f 5f740000 t_cksum_info_t.. + 489e0: 001fbe14 04000020 400e4144 465f4e45 ....... @.ADF_NE + 489f0: 545f5453 4f5f4e4f 4e450000 0e414446 T_TSO_NONE...ADF + 48a00: 5f4e4554 5f54534f 5f495056 3400010e _NET_TSO_IPV4... + 48a10: 4144465f 4e45545f 54534f5f 414c4c00 ADF_NET_TSO_ALL. + 48a20: 02000961 64665f6e 65745f74 736f5f74 ...adf_net_tso_t + 48a30: 7970655f 74000000 20011210 00002094 ype_t... ..... . + 48a40: 08636b73 756d5f63 61700000 001fe702 .cksum_cap...... + 48a50: 23000874 736f0000 00204002 23080876 #..tso... @.#..v + 48a60: 6c616e5f 73757070 6f727465 64000000 lan_supported... + 48a70: 16750223 0c001220 0000212d 0874785f .u.#... ..!-.tx_ + 48a80: 7061636b 65747300 0000160e 02230008 packets......#.. + 48a90: 72785f70 61636b65 74730000 00160e02 rx_packets...... + 48aa0: 23040874 785f6279 74657300 0000160e #..tx_bytes..... + 48ab0: 02230808 72785f62 79746573 00000016 .#..rx_bytes.... + 48ac0: 0e02230c 0874785f 64726f70 70656400 ..#..tx_dropped. + 48ad0: 0000160e 02231008 72785f64 726f7070 .....#..rx_dropp + 48ae0: 65640000 00160e02 23140872 785f6572 ed......#..rx_er + 48af0: 726f7273 00000016 0e022318 0874785f rors......#..tx_ + 48b00: 6572726f 72730000 00160e02 231c0009 errors......#... + 48b10: 6164665f 6e65745f 65746861 6464725f adf_net_ethaddr_ + 48b20: 74000000 1c671600 00212d03 00000021 t....g...!-....! + 48b30: 52107f00 17616466 5f6e6574 5f636d64 R....adf_net_cmd + 48b40: 5f6d6361 64647200 03040000 2189086e _mcaddr.....!..n + 48b50: 656c656d 00000016 0e022300 086d6361 elem......#..mca + 48b60: 73740000 00214402 23040009 6164665f st...!D.#...adf_ + 48b70: 6e65745f 636d645f 6c696e6b 5f696e66 net_cmd_link_inf + 48b80: 6f5f7400 00001c01 09616466 5f6e6574 o_t......adf_net + 48b90: 5f636d64 5f706f6c 6c5f696e 666f5f74 _cmd_poll_info_t + 48ba0: 0000001e 6f096164 665f6e65 745f636d ....o.adf_net_cm + 48bb0: 645f636b 73756d5f 696e666f 5f740000 d_cksum_info_t.. + 48bc0: 001fe709 6164665f 6e65745f 636d645f ....adf_net_cmd_ + 48bd0: 72696e67 5f696e66 6f5f7400 00001e33 ring_info_t....3 + 48be0: 09616466 5f6e6574 5f636d64 5f646d61 .adf_net_cmd_dma + 48bf0: 5f696e66 6f5f7400 00001f18 09616466 _info_t......adf + 48c00: 5f6e6574 5f636d64 5f766964 5f740000 _net_cmd_vid_t.. + 48c10: 001c9d09 6164665f 6e65745f 636d645f ....adf_net_cmd_ + 48c20: 6f66666c 6f61645f 6361705f 74000000 offload_cap_t... + 48c30: 20580961 64665f6e 65745f63 6d645f73 X.adf_net_cmd_s + 48c40: 74617473 5f740000 00209409 6164665f tats_t... ..adf_ + 48c50: 6e65745f 636d645f 6d636164 64725f74 net_cmd_mcaddr_t + 48c60: 00000021 520d6164 665f6e65 745f636d ...!R.adf_net_cm + 48c70: 645f6d63 6173745f 63617000 04000022 d_mcast_cap...." + 48c80: cb0e4144 465f4e45 545f4d43 4153545f ..ADF_NET_MCAST_ + 48c90: 53555000 000e4144 465f4e45 545f4d43 SUP...ADF_NET_MC + 48ca0: 4153545f 4e4f5453 55500001 00096164 AST_NOTSUP....ad + 48cb0: 665f6e65 745f636d 645f6d63 6173745f f_net_cmd_mcast_ + 48cc0: 6361705f 74000000 22831803 04000023 cap_t..."......# + 48cd0: 9d086c69 6e6b5f69 6e666f00 00002189 ..link_info...!. + 48ce0: 02230008 706f6c6c 5f696e66 6f000000 .#..poll_info... + 48cf0: 21a60223 0008636b 73756d5f 696e666f !..#..cksum_info + 48d00: 00000021 c3022300 0872696e 675f696e ...!..#..ring_in + 48d10: 666f0000 0021e102 23000864 6d615f69 fo...!..#..dma_i + 48d20: 6e666f00 000021fe 02230008 76696400 nfo...!..#..vid. + 48d30: 0000221a 02230008 6f66666c 6f61645f .."..#..offload_ + 48d40: 63617000 00002231 02230008 73746174 cap..."1.#..stat + 48d50: 73000000 22500223 00086d63 6173745f s..."P.#..mcast_ + 48d60: 696e666f 00000022 69022300 086d6361 info..."i.#..mca + 48d70: 73745f63 61700000 0022cb02 23000014 st_cap..."..#... + 48d80: 04000023 f40e4144 465f4e42 55465f52 ...#..ADF_NBUF_R + 48d90: 585f434b 53554d5f 4e4f4e45 00000e41 X_CKSUM_NONE...A + 48da0: 44465f4e 4255465f 52585f43 4b53554d DF_NBUF_RX_CKSUM + 48db0: 5f485700 010e4144 465f4e42 55465f52 _HW...ADF_NBUF_R + 48dc0: 585f434b 53554d5f 554e4e45 43455353 X_CKSUM_UNNECESS + 48dd0: 41525900 02000961 64665f6e 6275665f ARY....adf_nbuf_ + 48de0: 72785f63 6b73756d 5f747970 655f7400 rx_cksum_type_t. + 48df0: 0000239d 12080000 24340872 6573756c ..#.....$4.resul + 48e00: 74000000 23f40223 00087661 6c000000 t...#..#..val... + 48e10: 160e0223 04001208 00002464 08747970 ...#......$d.typ + 48e20: 65000000 20400223 00086d73 73000000 e... @.#..mss... + 48e30: 1c9d0223 04086864 725f6f66 66000000 ...#..hdr_off... + 48e40: 16750223 0600075f 5f616466 5f6e6275 .u.#...__adf_nbu + 48e50: 665f7168 65616400 0c000024 a3086865 f_qhead....$..he + 48e60: 61640000 00142e02 23000874 61696c00 ad......#..tail. + 48e70: 0000142e 02230408 716c656e 00000016 .....#..qlen.... + 48e80: 0e022308 00095f5f 6164665f 6e627566 ..#...__adf_nbuf + 48e90: 5f740000 00142e03 00001684 04000300 _t.............. + 48ea0: 00160e04 00020106 00001310 01060000 ................ + 48eb0: 160e0106 00001684 01060000 16840103 ................ + 48ec0: 000012f1 0400095f 5f616466 5f6e6275 .......__adf_nbu + 48ed0: 665f7168 6561645f 74000000 2464095f f_qhead_t...$d._ + 48ee0: 5f616466 5f6e6275 665f7175 6575655f _adf_nbuf_queue_ + 48ef0: 74000000 24e40300 0024fc04 00060000 t...$....$...... + 48f00: 24a30106 000024a3 01140400 00261c0e $.....$......&.. + 48f10: 415f5354 41545553 5f4f4b00 000e415f A_STATUS_OK...A_ + 48f20: 53544154 55535f46 41494c45 4400010e STATUS_FAILED... + 48f30: 415f5354 41545553 5f454e4f 454e5400 A_STATUS_ENOENT. + 48f40: 020e415f 53544154 55535f45 4e4f4d45 ..A_STATUS_ENOME + 48f50: 4d00030e 415f5354 41545553 5f45494e M...A_STATUS_EIN + 48f60: 56414c00 040e415f 53544154 55535f45 VAL...A_STATUS_E + 48f70: 494e5052 4f475245 53530005 0e415f53 INPROGRESS...A_S + 48f80: 54415455 535f454e 4f545355 50500006 TATUS_ENOTSUPP.. + 48f90: 0e415f53 54415455 535f4542 55535900 .A_STATUS_EBUSY. + 48fa0: 070e415f 53544154 55535f45 32424947 ..A_STATUS_E2BIG + 48fb0: 00080e41 5f535441 5455535f 45414444 ...A_STATUS_EADD + 48fc0: 524e4f54 41564149 4c00090e 415f5354 RNOTAVAIL...A_ST + 48fd0: 41545553 5f454e58 494f000a 0e415f53 ATUS_ENXIO...A_S + 48fe0: 54415455 535f4546 41554c54 000b0e41 TATUS_EFAULT...A + 48ff0: 5f535441 5455535f 45494f00 0c000961 _STATUS_EIO....a + 49000: 5f737461 7475735f 74000000 25270600 _status_t...%'.. + 49010: 00261c01 06000001 09010201 09616466 .&...........adf + 49020: 5f6e6275 665f7400 000024a3 14040000 _nbuf_t...$..... + 49030: 26810e41 44465f4f 535f444d 415f544f &..ADF_OS_DMA_TO + 49040: 5f444556 49434500 000e4144 465f4f53 _DEVICE...ADF_OS + 49050: 5f444d41 5f46524f 4d5f4445 56494345 _DMA_FROM_DEVICE + 49060: 00010009 6164665f 6f735f64 6d615f64 ....adf_os_dma_d + 49070: 69725f74 00000026 4a060000 261c0102 ir_t...&J...&... + 49080: 01096164 665f6f73 5f646d61 6d61705f ..adf_os_dmamap_ + 49090: 696e666f 5f740000 00162b03 0000269f info_t....+...&. + 490a0: 04000201 02010600 00263a01 06000024 .........&:....$ + 490b0: a3010201 02010600 00263a01 06000024 .........&:....$ + 490c0: a3010600 00263a01 06000024 a3010600 .....&:....$.... + 490d0: 00263a01 02010201 06000016 0e010600 .&:............. + 490e0: 00168401 02010201 0600001b 3b010600 ............;... + 490f0: 001a8801 0600001a 88010961 64665f6f ...........adf_o + 49100: 735f7367 6c697374 5f740000 0016c303 s_sglist_t...... + 49110: 00002718 04000201 02010201 06000016 ..'............. + 49120: 84010961 64665f6e 6275665f 71756575 ...adf_nbuf_queu + 49130: 655f7400 000024fc 03000027 40040002 e_t...$....'@... + 49140: 01030000 24e40400 02010201 02010600 ....$........... + 49150: 00263a01 06000024 a3010600 00160e01 .&:....$........ + 49160: 06000016 0e010600 001a8801 0600001a ................ + 49170: 88010600 001fa401 06000016 0e010961 ...............a + 49180: 64665f6e 6275665f 72785f63 6b73756d df_nbuf_rx_cksum + 49190: 5f740000 00241203 0000279c 04000201 _t...$....'..... + 491a0: 02010961 64665f6e 6275665f 74736f5f ...adf_nbuf_tso_ + 491b0: 74000000 24340300 0027c004 00020102 t...$4...'...... + 491c0: 01096164 665f6e65 745f6861 6e646c65 ..adf_net_handle + 491d0: 5f740000 0003fe09 6164665f 6e65745f _t......adf_net_ + 491e0: 766c616e 6864725f 74000000 1db00300 vlanhdr_t....... + 491f0: 0027f504 00060000 261c0106 0000261c .'......&.....&. + 49200: 01020102 01075f48 49465f43 4f4e4649 ......_HIF_CONFI + 49210: 47000400 00284408 64756d6d 79000000 G....(D.dummy... + 49220: 01090223 00000201 03000028 44040002 ...#.......(D... + 49230: 01030000 284d0400 075f4849 465f4341 ....(M..._HIF_CA + 49240: 4c4c4241 434b000c 000028a2 0873656e LLBACK....(..sen + 49250: 645f6275 665f646f 6e650000 00284602 d_buf_done...(F. + 49260: 23000872 6563765f 62756600 0000284f #..recv_buf...(O + 49270: 02230408 636f6e74 65787400 000003fe .#..context..... + 49280: 02230800 09686966 5f68616e 646c655f .#...hif_handle_ + 49290: 74000000 03fe0948 49465f43 4f4e4649 t......HIF_CONFI + 492a0: 47000000 28230300 0028b404 00060000 G...(#...(...... + 492b0: 28a20103 000028cb 04000201 03000028 (.....(........( + 492c0: d8040009 4849465f 43414c4c 4241434b ....HIF_CALLBACK + 492d0: 00000028 56030000 28e10400 02010300 ...(V...(....... + 492e0: 0028fa04 00060000 01090103 00002903 .(............). + 492f0: 04000201 03000029 10040006 00000109 .......)........ + 49300: 01030000 29190400 02010300 00292604 ....)........)&. + 49310: 00060000 01090103 0000292f 04000201 ..........)/.... + 49320: 03000029 3c040007 6869665f 61706900 ...)<...hif_api. + 49330: 3800002a 95085f69 6e697400 000028d1 8..*.._init...(. + 49340: 02230008 5f736875 74646f77 6e000000 .#.._shutdown... + 49350: 28da0223 04085f72 65676973 7465725f (..#.._register_ + 49360: 63616c6c 6261636b 00000028 fc022308 callback...(..#. + 49370: 085f6765 745f746f 74616c5f 63726564 ._get_total_cred + 49380: 69745f63 6f756e74 00000029 0902230c it_count...)..#. + 49390: 085f7374 61727400 000028da 02231008 ._start...(..#.. + 493a0: 5f636f6e 6669675f 70697065 00000029 _config_pipe...) + 493b0: 12022314 085f7365 6e645f62 75666665 ..#.._send_buffe + 493c0: 72000000 291f0223 18085f72 65747572 r...)..#.._retur + 493d0: 6e5f7265 63765f62 75660000 00292802 n_recv_buf...)(. + 493e0: 231c085f 69735f70 6970655f 73757070 #.._is_pipe_supp + 493f0: 6f727465 64000000 29350223 20085f67 orted...)5.# ._g + 49400: 65745f6d 61785f6d 73675f6c 656e0000 et_max_msg_len.. + 49410: 00293502 2324085f 6765745f 72657365 .)5.#$._get_rese + 49420: 72766564 5f686561 64726f6f 6d000000 rved_headroom... + 49430: 29090223 28085f69 73725f68 616e646c )..#(._isr_handl + 49440: 65720000 0028da02 232c085f 6765745f er...(..#,._get_ + 49450: 64656661 756c745f 70697065 00000029 default_pipe...) + 49460: 3e022330 08705265 73657276 65640000 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............__ad + 4d430: 665f6f73 5f73697a 655f7400 0000047e f_os_size_t....~ + 4d440: 14040000 1b050e41 5f46414c 53450000 .......A_FALSE.. + 4d450: 0e415f54 52554500 01000361 5f626f6f .A_TRUE....a_boo + 4d460: 6c5f7400 00001aeb 07000015 73040003 l_t.........s... + 4d470: 5f5f6164 665f6f73 5f646d61 5f6d6170 __adf_os_dma_map + 4d480: 5f740000 001b1306 010d6164 665f6f73 _t........adf_os + 4d490: 5f636163 68655f73 796e6300 0400001b _cache_sync..... + 4d4a0: 9d0e4144 465f5359 4e435f50 52455245 ..ADF_SYNC_PRERE + 4d4b0: 41440000 0e414446 5f53594e 435f5052 AD...ADF_SYNC_PR + 4d4c0: 45575249 54450002 0e414446 5f53594e EWRITE...ADF_SYN + 4d4d0: 435f504f 53545245 41440001 0e414446 C_POSTREAD...ADF + 4d4e0: 5f53594e 435f504f 53545752 49544500 _SYNC_POSTWRITE. + 4d4f0: 03000361 64665f6f 735f6361 6368655f ...adf_os_cache_ + 4d500: 73796e63 5f740000 001b3406 01036164 sync_t....4...ad + 4d510: 665f6f73 5f73697a 655f7400 00001ad6 f_os_size_t..... + 4d520: 0900001b b8010361 64665f6f 735f646d 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x_ndesc......#.. + 4d830: 74785f6e 64657363 00000016 8b022308 tx_ndesc......#. + 4d840: 00120800 001f1205 706f6c6c 65640000 ........polled.. + 4d850: 001b0502 23000570 6f6c6c5f 77740000 ....#..poll_wt.. + 4d860: 00168b02 2304000f 000016f2 4000001f ....#.......@... + 4d870: 1f103f00 12460000 1f470569 665f6e61 ..?..F...G.if_na + 4d880: 6d650000 001f1202 23000564 65765f61 me......#..dev_a + 4d890: 64647200 00001cd7 02234000 14040000 ddr......#@..... + 4d8a0: 1f7e0e41 44465f4f 535f444d 415f4d41 .~.ADF_OS_DMA_MA + 4d8b0: 534b5f33 32424954 00000e41 44465f4f SK_32BIT...ADF_O + 4d8c0: 535f444d 415f4d41 534b5f36 34424954 S_DMA_MASK_64BIT + 4d8d0: 00010003 6164665f 6f735f64 6d615f6d ....adf_os_dma_m + 4d8e0: 61736b5f 74000000 1f470461 64665f64 ask_t....G.adf_d + 4d8f0: 6d615f69 6e666f00 0800001f cb05646d ma_info.......dm + 4d900: 615f6d61 736b0000 001f7e02 23000573 a_mask....~.#..s + 4d910: 675f6e73 65677300 0000168b 02230400 g_nsegs......#.. + 4d920: 14040000 20210e41 44465f4e 45545f43 .... !.ADF_NET_C + 4d930: 4b53554d 5f4e4f4e 4500000e 4144465f KSUM_NONE...ADF_ + 4d940: 4e45545f 434b5355 4d5f5443 505f5544 NET_CKSUM_TCP_UD + 4d950: 505f4950 76340001 0e414446 5f4e4554 P_IPv4...ADF_NET + 4d960: 5f434b53 554d5f54 43505f55 44505f49 _CKSUM_TCP_UDP_I + 4d970: 50763600 02000361 64665f6e 65745f63 Pv6....adf_net_c + 4d980: 6b73756d 5f747970 655f7400 00001fcb ksum_type_t..... + 4d990: 12080000 20640574 785f636b 73756d00 .... d.tx_cksum. + 4d9a0: 00002021 02230005 72785f63 6b73756d .. !.#..rx_cksum + 4d9b0: 00000020 21022304 00036164 665f6e65 ... !.#...adf_ne + 4d9c0: 745f636b 73756d5f 696e666f 5f740000 t_cksum_info_t.. + 4d9d0: 00203b14 04000020 bd0e4144 465f4e45 . ;.... ..ADF_NE + 4d9e0: 545f5453 4f5f4e4f 4e450000 0e414446 T_TSO_NONE...ADF + 4d9f0: 5f4e4554 5f54534f 5f495056 3400010e _NET_TSO_IPV4... + 4da00: 4144465f 4e45545f 54534f5f 414c4c00 ADF_NET_TSO_ALL. + 4da10: 02000361 64665f6e 65745f74 736f5f74 ...adf_net_tso_t + 4da20: 7970655f 74000000 207e1210 00002111 ype_t... ~....!. + 4da30: 05636b73 756d5f63 61700000 00206402 .cksum_cap... d. + 4da40: 23000574 736f0000 0020bd02 23080576 #..tso... ..#..v + 4da50: 6c616e5f 73757070 6f727465 64000000 lan_supported... + 4da60: 16f20223 0c001220 000021aa 0574785f ...#... ..!..tx_ + 4da70: 7061636b 65747300 0000168b 02230005 packets......#.. + 4da80: 72785f70 61636b65 74730000 00168b02 rx_packets...... + 4da90: 23040574 785f6279 74657300 0000168b #..tx_bytes..... + 4daa0: 02230805 72785f62 79746573 00000016 .#..rx_bytes.... + 4dab0: 8b02230c 0574785f 64726f70 70656400 ..#..tx_dropped. + 4dac0: 0000168b 02231005 72785f64 726f7070 .....#..rx_dropp + 4dad0: 65640000 00168b02 23140572 785f6572 ed......#..rx_er + 4dae0: 726f7273 00000016 8b022318 0574785f rors......#..tx_ + 4daf0: 6572726f 72730000 00168b02 231c0003 errors......#... + 4db00: 6164665f 6e65745f 65746861 6464725f adf_net_ethaddr_ + 4db10: 74000000 1ce41600 0021aa03 00000021 t........!.....! + 4db20: cf107f00 17616466 5f6e6574 5f636d64 .....adf_net_cmd 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74617473 5f740000 00211103 6164665f tats_t...!..adf_ + 4dc40: 6e65745f 636d645f 6d636164 64725f74 net_cmd_mcaddr_t + 4dc50: 00000021 cf0d6164 665f6e65 745f636d ...!..adf_net_cm + 4dc60: 645f6d63 6173745f 63617000 04000023 d_mcast_cap....# + 4dc70: 480e4144 465f4e45 545f4d43 4153545f H.ADF_NET_MCAST_ + 4dc80: 53555000 000e4144 465f4e45 545f4d43 SUP...ADF_NET_MC + 4dc90: 4153545f 4e4f5453 55500001 00036164 AST_NOTSUP....ad + 4dca0: 665f6e65 745f636d 645f6d63 6173745f f_net_cmd_mcast_ + 4dcb0: 6361705f 74000000 23001803 04000024 cap_t...#......$ + 4dcc0: 1a056c69 6e6b5f69 6e666f00 00002206 ..link_info...". + 4dcd0: 02230005 706f6c6c 5f696e66 6f000000 .#..poll_info... + 4dce0: 22230223 0005636b 73756d5f 696e666f "#.#..cksum_info + 4dcf0: 00000022 40022300 0572696e 675f696e ..."@.#..ring_in + 4dd00: 666f0000 00225e02 23000564 6d615f69 fo..."^.#..dma_i + 4dd10: 6e666f00 0000227b 02230005 76696400 nfo..."{.#..vid. + 4dd20: 00002297 02230005 6f66666c 6f61645f .."..#..offload_ + 4dd30: 63617000 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5f616466 5f6e6275 ...#...__adf_nbu + 4de40: 665f7168 65616400 0c000025 20056865 f_qhead....% .he + 4de50: 61640000 0014ab02 23000574 61696c00 ad......#..tail. + 4de60: 000014ab 02230405 716c656e 00000016 .....#..qlen.... + 4de70: 8b022308 00035f5f 6164665f 6e627566 ..#...__adf_nbuf + 4de80: 5f740000 0014ab07 00001701 04000700 _t.............. + 4de90: 00168b04 00060109 0000138d 01090000 ................ + 4dea0: 168b0109 00001701 01090000 17010107 ................ + 4deb0: 0000136e 0400035f 5f616466 5f6e6275 ...n...__adf_nbu + 4dec0: 665f7168 6561645f 74000000 24e1035f f_qhead_t...$.._ + 4ded0: 5f616466 5f6e6275 665f7175 6575655f _adf_nbuf_queue_ + 4dee0: 74000000 25610700 00257904 00090000 t...%a...%y..... + 4def0: 25200109 00002520 01140400 0026990e % ....% .....&.. + 4df00: 415f5354 41545553 5f4f4b00 000e415f A_STATUS_OK...A_ + 4df10: 53544154 55535f46 41494c45 4400010e STATUS_FAILED... + 4df20: 415f5354 41545553 5f454e4f 454e5400 A_STATUS_ENOENT. + 4df30: 020e415f 53544154 55535f45 4e4f4d45 ..A_STATUS_ENOME + 4df40: 4d00030e 415f5354 41545553 5f45494e M...A_STATUS_EIN + 4df50: 56414c00 040e415f 53544154 55535f45 VAL...A_STATUS_E + 4df60: 494e5052 4f475245 53530005 0e415f53 INPROGRESS...A_S + 4df70: 54415455 535f454e 4f545355 50500006 TATUS_ENOTSUPP.. + 4df80: 0e415f53 54415455 535f4542 55535900 .A_STATUS_EBUSY. + 4df90: 070e415f 53544154 55535f45 32424947 ..A_STATUS_E2BIG + 4dfa0: 00080e41 5f535441 5455535f 45414444 ...A_STATUS_EADD + 4dfb0: 524e4f54 41564149 4c00090e 415f5354 RNOTAVAIL...A_ST + 4dfc0: 41545553 5f454e58 494f000a 0e415f53 ATUS_ENXIO...A_S + 4dfd0: 54415455 535f4546 41554c54 000b0e41 TATUS_EFAULT...A + 4dfe0: 5f535441 5455535f 45494f00 0c000361 _STATUS_EIO....a + 4dff0: 5f737461 7475735f 74000000 25a40900 _status_t...%... + 4e000: 00269901 09000001 c8010601 03616466 .&...........adf + 4e010: 5f6e6275 665f7400 00002520 14040000 _nbuf_t...% .... + 4e020: 26fe0e41 44465f4f 535f444d 415f544f &..ADF_OS_DMA_TO + 4e030: 5f444556 49434500 000e4144 465f4f53 _DEVICE...ADF_OS + 4e040: 5f444d41 5f46524f 4d5f4445 56494345 _DMA_FROM_DEVICE + 4e050: 00010003 6164665f 6f735f64 6d615f64 ....adf_os_dma_d + 4e060: 69725f74 00000026 c7090000 26990106 ir_t...&....&... + 4e070: 01036164 665f6f73 5f646d61 6d61705f ..adf_os_dmamap_ + 4e080: 696e666f 5f740000 0016a807 0000271c info_t........'. + 4e090: 04000601 06010900 0026b701 09000025 .........&.....% + 4e0a0: 20010601 06010900 0026b701 09000025 ........&.....% + 4e0b0: 20010900 0026b701 09000025 20010900 ....&.....% ... + 4e0c0: 0026b701 06010601 09000016 8b010900 .&.............. + 4e0d0: 00170101 06010601 0900001b b8010900 ................ + 4e0e0: 001b0501 0900001b 05010361 64665f6f ...........adf_o + 4e0f0: 735f7367 6c697374 5f740000 00174007 s_sglist_t....@. + 4e100: 00002795 04000601 06010601 09000017 ..'............. + 4e110: 01010361 64665f6e 6275665f 71756575 ...adf_nbuf_queu + 4e120: 655f7400 00002579 07000027 bd040006 e_t...%y...'.... + 4e130: 01070000 25610400 06010601 06010900 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#............int + 51210: 00050402 63686172 00070108 000001d0 ....char........ + 51220: 08000001 d0070000 01dd0400 09000001 ................ + 51230: c9010700 0001e904 00047072 696e7466 ..........printf + 51240: 5f617069 00080000 022d055f 7072696e _api.....-._prin + 51250: 74665f69 6e697400 000001c2 02230005 tf_init......#.. + 51260: 5f707269 6e746600 000001ef 02230400 _printf......#.. + 51270: 026c6f6e 6720756e 7369676e 65642069 .long unsigned i + 51280: 6e740007 04037569 6e743332 5f740000 nt....uint32_t.. + 51290: 00022d04 75617274 5f666966 6f000800 ..-.uart_fifo... + 512a0: 00029b05 73746172 745f696e 64657800 ....start_index. + 512b0: 00000135 02230005 656e645f 696e6465 ...5.#..end_inde + 512c0: 78000000 01350223 02056f76 65727275 x....5.#..overru + 512d0: 6e5f6572 72000000 02420223 04000475 n_err....B.#...u + 512e0: 6172745f 61706900 20000003 54055f75 art_api. ...T._u + 512f0: 6172745f 696e6974 00000003 ab022300 art_init......#. + 51300: 055f7561 72745f63 6861725f 70757400 ._uart_char_put. + 51310: 000003b4 02230405 5f756172 745f6368 .....#.._uart_ch + 51320: 61725f67 65740000 0003c802 2308055f ar_get......#.._ + 51330: 75617274 5f737472 5f6f7574 00000003 uart_str_out.... + 51340: d102230c 055f7561 72745f74 61736b00 ..#.._uart_task. + 51350: 000001c2 02231005 5f756172 745f7374 .....#.._uart_st + 51360: 61747573 00000003 ab022314 055f7561 atus......#.._ua + 51370: 72745f63 6f6e6669 67000000 03da0223 rt_config......# + 51380: 18055f75 6172745f 6877696e 69740000 .._uart_hwinit.. + 51390: 0003e302 231c0007 0000029b 04000475 ....#..........u + 513a0: 6172745f 626c6b00 10000003 a5056465 art_blk.......de + 513b0: 6275675f 6d6f6465 00000001 35022300 bug_mode....5.#. + 513c0: 05626175 64000000 01350223 02055f75 .baud....5.#.._u + 513d0: 61727400 00000354 02230405 5f747800 art....T.#.._tx. + 513e0: 00000250 02230800 09000002 42010700 ...P.#......B... + 513f0: 0003a504 00060107 000003b2 04000700 ................ + 51400: 00011204 00090000 01350107 000003c2 .........5...... + 51410: 04000601 07000003 cf040006 01070000 ................ + 51420: 03d80400 06010700 0003e104 00070000 ................ + 51430: 01d00400 09000001 c9010700 0003f104 ................ + 51440: 00044442 5f434f4d 4d414e44 5f535452 ..DB_COMMAND_STR + 51450: 55435400 0c000004 4905636d 645f7374 UCT.....I.cmd_st + 51460: 72000000 03ea0223 00056865 6c705f73 r......#..help_s + 51470: 74720000 0003ea02 23040563 6d645f66 tr......#..cmd_f + 51480: 756e6300 000003f7 02230800 04646267 unc......#...dbg + 51490: 5f617069 00080000 047c055f 6462675f _api.....|._dbg_ + 514a0: 696e6974 00000001 c2022300 055f6462 init......#.._db + 514b0: 675f7461 736b0000 0001c202 2304000a g_task......#... + 514c0: 04000275 6e736967 6e656420 696e7400 ...unsigned int. + 514d0: 07040900 00047c01 07000004 8f04000b ......|......... + 514e0: 0b070000 049d0400 09000004 7c010700 ............|... + 514f0: 0004a504 00090000 01c90107 000004b2 ................ + 51500: 0400046d 656d5f61 70690014 00000521 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................ + 51610: 05c40400 09000001 35010700 0005d104 ........5....... + 51620: 00046d69 73635f61 70690024 000006c1 ..misc_api.$.... + 51630: 055f7379 7374656d 5f726573 65740000 ._system_reset.. + 51640: 0001c202 2300055f 6d61635f 72657365 ....#.._mac_rese + 51650: 74000000 01c20223 04055f61 73736661 t......#.._assfa + 51660: 696c0000 00053d02 2308055f 6d697361 il....=.#.._misa + 51670: 6c69676e 65645f6c 6f61645f 68616e64 ligned_load_hand + 51680: 6c657200 0000053d 02230c05 5f726570 ler....=.#.._rep + 51690: 6f72745f 6661696c 7572655f 746f5f68 ort_failure_to_h + 516a0: 6f737400 00000546 02231005 5f746172 ost....F.#.._tar + 516b0: 6765745f 69645f67 65740000 00055302 get_id_get....S. + 516c0: 2314055f 69735f68 6f73745f 70726573 #.._is_host_pres + 516d0: 656e7400 000005bd 02231805 5f6b6268 ent......#.._kbh + 516e0: 69740000 0005ca02 231c055f 726f6d5f it......#.._rom_ + 516f0: 76657273 696f6e5f 67657400 000005d7 version_get..... + 51700: 02232000 09000003 ea010700 0006c104 .# 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........A_HANDLE + 51810: 00000004 7f060103 415f5449 4d45525f ........A_TIMER_ + 51820: 46554e43 00000007 d2070000 07d40400 FUNC............ + 51830: 06010700 0007ed04 00047469 6d65725f ..........timer_ + 51840: 61706900 14000008 6c055f74 696d6572 api.....l._timer + 51850: 5f696e69 74000000 01c20223 00055f74 _init......#.._t + 51860: 696d6572 5f61726d 00000007 b4022304 imer_arm......#. + 51870: 055f7469 6d65725f 64697361 726d0000 ._timer_disarm.. + 51880: 0007bd02 2308055f 74696d65 725f7365 ....#.._timer_se + 51890: 74666e00 000007ef 02230c05 5f74696d tfn......#.._tim + 518a0: 65725f72 756e0000 0001c202 23100003 er_run......#... + 518b0: 424f4f4c 45414e00 00000135 09000008 BOOLEAN....5.... + 518c0: 6c010700 00087904 00090000 086c0107 l.....y......l.. + 518d0: 00000886 04000900 00086c01 07000008 ..........l..... + 518e0: 93040004 726f6d70 5f617069 00100000 ....romp_api.... + 518f0: 0905055f 726f6d70 5f696e69 74000000 ..._romp_init... + 51900: 01c20223 00055f72 6f6d705f 646f776e ...#.._romp_down + 51910: 6c6f6164 00000008 7f022304 055f726f load......#.._ro + 51920: 6d705f69 6e737461 6c6c0000 00088c02 mp_install...... + 51930: 2308055f 726f6d70 5f646563 6f646500 #.._romp_decode. + 51940: 00000899 02230c00 04726f6d 5f706174 .....#...rom_pat + 51950: 63685f73 74001000 00096105 63726331 ch_st.....a.crc1 + 51960: 36000000 01350223 00056c65 6e000000 6....5.#..len... + 51970: 01350223 02056c64 5f616464 72000000 .5.#..ld_addr... + 51980: 02420223 04056675 6e5f6164 64720000 .B.#..fun_addr.. + 51990: 00024202 23080570 66756e00 000003bb ..B.#..pfun..... + 519a0: 02230c00 04656570 5f726564 69725f61 .#...eep_redir_a + 519b0: 64647200 04000009 93056f66 66736574 ddr.......offset + 519c0: 00000001 35022300 0573697a 65000000 ....5.#..size... + 519d0: 01350223 02000341 5f55494e 54333200 .5.#...A_UINT32. + 519e0: 0000047f 09000004 7c010700 0009a104 ........|....... + 519f0: 0004616c 6c6f6372 616d5f61 7069000c ..allocram_api.. + 51a00: 00000a12 05636d6e 6f735f61 6c6c6f63 .....cmnos_alloc + 51a10: 72616d5f 696e6974 00000009 a7022300 ram_init......#. + 51a20: 05636d6e 6f735f61 6c6c6f63 72616d00 .cmnos_allocram. + 51a30: 000009a7 02230405 636d6e6f 735f616c .....#..cmnos_al + 51a40: 6c6f6372 616d5f64 65627567 00000001 locram_debug.... + 51a50: c2022308 00060107 00000a12 04000341 ..#............A + 51a60: 5f544153 4b4c4554 5f46554e 43000000 _TASKLET_FUNC... + 51a70: 0a14045f 7461736b 6c657400 1000000a ..._tasklet..... + 51a80: 73056675 6e630000 000a1b02 23000561 s.func......#..a + 51a90: 72670000 00047c02 23040573 74617465 rg....|.#..state + 51aa0: 00000001 c9022308 056e6578 74000000 ......#..next... + 51ab0: 0a730223 0c000700 000a2f04 00070000 .s.#....../..... + 51ac0: 0a2f0400 03415f74 61736b6c 65745f74 ./...A_tasklet_t + 51ad0: 0000000a 2f070000 0a810400 06010700 ..../........... + 51ae0: 000a9904 00060107 00000aa2 04000474 ...............t + 51af0: 61736b6c 65745f61 70690014 00000b37 asklet_api.....7 + 51b00: 055f7461 736b6c65 745f696e 69740000 ._tasklet_init.. + 51b10: 0001c202 2300055f 7461736b 6c65745f ....#.._tasklet_ + 51b20: 696e6974 5f746173 6b000000 0a9b0223 init_task......# + 51b30: 04055f74 61736b6c 65745f64 69736162 .._tasklet_disab + 51b40: 6c650000 000aa402 2308055f 7461736b le......#.._task + 51b50: 6c65745f 73636865 64756c65 0000000a let_schedule.... + 51b60: a402230c 055f7461 736b6c65 745f7275 ..#.._tasklet_ru + 51b70: 6e000000 01c20223 10000601 0700000b n......#........ + 51b80: 37040009 00000993 01070000 0b400400 7............@.. + 51b90: 06010700 000b4d04 0004636c 6f636b5f ......M...clock_ + 51ba0: 61706900 2400000c 2f055f63 6c6f636b api.$.../._clock + 51bb0: 5f696e69 74000000 0b390223 00055f63 _init....9.#.._c + 51bc0: 6c6f636b 72656773 5f696e69 74000000 lockregs_init... + 51bd0: 01c20223 04055f75 6172745f 66726571 ...#.._uart_freq + 51be0: 75656e63 79000000 0b460223 08055f64 uency....F.#.._d + 51bf0: 656c6179 5f757300 00000b4f 02230c05 elay_us....O.#.. + 51c00: 5f776c61 6e5f6261 6e645f73 65740000 _wlan_band_set.. + 51c10: 000b4f02 2310055f 72656663 6c6b5f73 ..O.#.._refclk_s + 51c20: 70656564 5f676574 0000000b 46022314 peed_get....F.#. + 51c30: 055f6d69 6c6c6973 65636f6e 64730000 ._milliseconds.. + 51c40: 000b4602 2318055f 73797363 6c6b5f63 ..F.#.._sysclk_c + 51c50: 68616e67 65000000 01c20223 1c055f63 hange......#.._c + 51c60: 6c6f636b 5f746963 6b000000 01c20223 lock_tick......# + 51c70: 20000900 00024201 0700000c 2f040003 .....B...../... + 51c80: 415f6f6c 645f696e 74725f74 00000002 A_old_intr_t.... + 51c90: 42090000 0c3c0107 00000c4e 04000601 B....<.....N.... + 51ca0: 0700000c 5b040006 01070000 0c640400 ....[........d.. + 51cb0: 09000002 42010700 000c6d04 0003415f ....B.....m...A_ + 51cc0: 6973725f 74000000 0c730601 0700000c isr_t....s...... + 51cd0: 87040009 0000047f 01070000 0c900400 ................ + 51ce0: 06010700 000c9d04 0004696e 74725f61 ..........intr_a + 51cf0: 7069002c 00000dbf 055f696e 74725f69 pi.,....._intr_i + 51d00: 6e697400 000001c2 02230005 5f696e74 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..valueL......#. + 54e60: 0576616c 75654800 00001d1b 02230600 .valueH......#.. + 54e70: 03574d49 5f415654 0000003d e60f0000 .WMI_AVT...=.... + 54e80: 3e2d0800 003e4710 0000120c 00003e7e >-...>G.......>~ + 54e90: 05747570 6c654e75 6d4c0000 001d1b02 .tupleNumL...... + 54ea0: 23000574 75706c65 4e756d48 0000001d #..tupleNumH.... + 54eb0: 1b022302 05617674 0000003e 3a022304 ..#..avt...>:.#. + 54ec0: 00120100 003ea005 62656163 6f6e5065 .....>..beaconPe + 54ed0: 6e64696e 67436f75 6e740000 0016f302 ndingCount...... + 54ee0: 23000004 5f574d49 5f535643 5f434f4e #..._WMI_SVC_CON + 54ef0: 46494700 1000003f 09054874 6348616e FIG....?..HtcHan + 54f00: 646c6500 00003a9c 02230005 506f6f6c dle...:..#..Pool + 54f10: 48616e64 6c650000 0036bc02 2304054d Handle...6..#..M + 54f20: 6178436d 64526570 6c794576 74730000 axCmdReplyEvts.. + 54f30: 0001c902 2308054d 61784576 656e7445 ....#..MaxEventE + 54f40: 76747300 000001c9 02230c00 06010700 vts......#...... + 54f50: 003f0904 0003574d 495f434d 445f4841 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............&... + 5f110: 04000276 64657363 5f617069 00140000 ...vdesc_api.... + 5f120: 02a1035f 696e6974 00000001 f3022300 ..._init......#. + 5f130: 035f616c 6c6f635f 76646573 63000000 ._alloc_vdesc... + 5f140: 02120223 04035f67 65745f68 775f6465 ...#.._get_hw_de + 5f150: 73630000 00021f02 2308035f 73776170 sc......#.._swap + 5f160: 5f766465 73630000 00022802 230c0370 _vdesc....(.#..p + 5f170: 52657365 72766564 00000002 2f022310 Reserved..../.#. + 5f180: 00090104 000002a1 04000563 68617200 ...........char. + 5f190: 07010c00 0002aa0c 000002aa 04000002 ................ + 5f1a0: b704000a 000001ea 01040000 02c30400 ................ + 5f1b0: 02707269 6e74665f 61706900 08000003 .printf_api..... + 5f1c0: 07035f70 72696e74 665f696e 69740000 .._printf_init.. + 5f1d0: 0002a302 2300035f 7072696e 74660000 ....#.._printf.. + 5f1e0: 0002c902 23040006 75696e74 31365f74 ....#...uint16_t + 5f1f0: 00000001 b2056c6f 6e672075 6e736967 ......long unsig + 5f200: 6e656420 696e7400 07040675 696e7433 ned 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igned_load_handl + 5f610: 65720000 00062f02 230c035f 7265706f er..../.#.._repo + 5f620: 72745f66 61696c75 72655f74 6f5f686f rt_failure_to_ho + 5f630: 73740000 00063802 2310035f 74617267 st....8.#.._targ + 5f640: 65745f69 645f6765 74000000 06450223 et_id_get....E.# + 5f650: 14035f69 735f686f 73745f70 72657365 .._is_host_prese + 5f660: 6e740000 0006af02 2318035f 6b626869 nt......#.._kbhi + 5f670: 74000000 06bc0223 1c035f72 6f6d5f76 t......#.._rom_v + 5f680: 65727369 6f6e5f67 65740000 0006c902 ersion_get...... + 5f690: 2320000a 000004df 01040000 07b30400 # .............. + 5f6a0: 0a000004 df010400 0007c004 000a0000 ................ + 5f6b0: 01ea0104 000007cd 04000a00 0001ea01 ................ + 5f6c0: 04000007 da04000a 000001ea 01040000 ................ + 5f6d0: 07e70400 02737472 696e675f 61706900 .....string_api. + 5f6e0: 18000008 6d035f73 7472696e 675f696e ....m._string_in + 5f6f0: 69740000 0002a302 2300035f 73747263 it......#.._strc + 5f700: 70790000 0007b902 2304035f 7374726e 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_timer_disarm... + 5f810: 08af0223 08035f74 696d6572 5f736574 ...#.._timer_set + 5f820: 666e0000 0008e102 230c035f 74696d65 fn......#.._time + 5f830: 725f7275 6e000000 02a30223 10000642 r_run......#...B + 5f840: 4f4f4c45 414e0000 0003070a 0000095e OOLEAN.........^ + 5f850: 01040000 096b0400 0a000009 5e010400 .....k......^... + 5f860: 00097804 000a0000 095e0104 00000985 ..x......^...... + 5f870: 04000272 6f6d705f 61706900 10000009 ...romp_api..... + 5f880: f7035f72 6f6d705f 696e6974 00000002 .._romp_init.... + 5f890: a3022300 035f726f 6d705f64 6f776e6c ..#.._romp_downl + 5f8a0: 6f616400 00000971 02230403 5f726f6d oad....q.#.._rom + 5f8b0: 705f696e 7374616c 6c000000 097e0223 p_install....~.# + 5f8c0: 08035f72 6f6d705f 6465636f 64650000 .._romp_decode.. + 5f8d0: 00098b02 230c0002 726f6d5f 70617463 ....#...rom_patc + 5f8e0: 685f7374 00100000 0a530363 72633136 h_st.....S.crc16 + 5f8f0: 00000003 07022300 036c656e 00000003 ......#..len.... + 5f900: 07022302 036c645f 61646472 00000003 ..#..ld_addr.... + 5f910: 2a022304 0366756e 5f616464 72000000 *.#..fun_addr... + 5f920: 032a0223 08037066 756e0000 0004b002 .*.#..pfun...... + 5f930: 230c0002 6565705f 72656469 725f6164 #...eep_redir_ad + 5f940: 64720004 00000a85 036f6666 73657400 dr.......offset. + 5f950: 00000307 02230003 73697a65 00000003 .....#..size.... + 5f960: 07022302 0006415f 55494e54 33320000 ..#...A_UINT32.. + 5f970: 0005710a 0000022f 01040000 0a930400 ..q..../........ + 5f980: 02616c6c 6f637261 6d5f6170 69000c00 .allocram_api... + 5f990: 000b0403 636d6e6f 735f616c 6c6f6372 ....cmnos_allocr + 5f9a0: 616d5f69 6e697400 00000a99 02230003 am_init......#.. + 5f9b0: 636d6e6f 735f616c 6c6f6372 616d0000 cmnos_allocram.. + 5f9c0: 000a9902 23040363 6d6e6f73 5f616c6c ....#..cmnos_all + 5f9d0: 6f637261 6d5f6465 62756700 000002a3 ocram_debug..... + 5f9e0: 02230800 09010400 000b0404 0006415f .#............A_ + 5f9f0: 5441534b 4c45545f 46554e43 0000000b TASKLET_FUNC.... + 5fa00: 06025f74 61736b6c 65740010 00000b65 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....O.#.._intr_a + 5fd10: 74746163 685f6973 72000000 0d720223 ttach_isr....r.# + 5fd20: 18035f67 65745f69 6e747265 6e61626c .._get_intrenabl + 5fd30: 65000000 0d7f0223 1c035f73 65745f69 e......#.._set_i + 5fd40: 6e747265 6e61626c 65000000 0d880223 ntrenable......# + 5fd50: 20035f67 65745f69 6e747270 656e6469 ._get_intrpendi + 5fd60: 6e670000 000d7f02 2324035f 756e626c ng......#$._unbl + 5fd70: 6f636b5f 616c6c5f 696e7472 6c766c00 ock_all_intrlvl. + 5fd80: 000002a3 02232800 11040000 0ece0374 .....#(........t + 5fd90: 696d656f 75740000 00032a02 23000361 imeout....*.#..a + 5fda0: 6374696f 6e000000 032a0223 00001208 ction....*.#.... + 5fdb0: 00000ee9 03636d64 00000003 2a022300 .....cmd....*.#. + 5fdc0: 1300000e a8022304 0006545f 5744545f ......#...T_WDT_ + 5fdd0: 434d4400 00000ece 09010400 000ef804 CMD............. + 5fde0: 00140400 000f4e10 454e554d 5f574454 ......N.ENUM_WDT + 5fdf0: 5f424f4f 54000110 454e554d 5f434f4c _BOOT...ENUM_COL + 5fe00: 445f424f 4f540002 10454e55 4d5f5355 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INIT...RET_NOT_E + 5ff10: 58495354 00021052 45545f45 45505f43 XIST...RET_EEP_C + 5ff20: 4f525255 50540003 10524554 5f454550 ORRUPT...RET_EEP + 5ff30: 5f4f5645 52464c4f 57000410 5245545f _OVERFLOW...RET_ + 5ff40: 554e4b4e 4f574e00 05000654 5f454550 UNKNOWN....T_EEP + 5ff50: 5f524554 00000010 03040000 03070400 _RET............ + 5ff60: 0a000010 6a010400 00108004 000a0000 ....j........... + 5ff70: 106a0104 0000108d 04000265 65705f61 .j.........eep_a + 5ff80: 70690010 000010f6 035f6565 705f696e pi......._eep_in + 5ff90: 69740000 0002a302 2300035f 6565705f it......#.._eep_ + 5ffa0: 72656164 00000010 86022304 035f6565 read......#.._ee + 5ffb0: 705f7772 69746500 00001086 02230803 p_write......#.. + 5ffc0: 5f656570 5f69735f 65786973 74000000 _eep_is_exist... + 5ffd0: 10930223 0c000275 73625f61 70690070 ...#...usb_api.p + 5ffe0: 000013a3 035f7573 625f696e 69740000 ....._usb_init.. + 5fff0: 0002a302 2300035f 7573625f 726f6d5f ....#.._usb_rom_ + 60000: 7461736b 00000002 a3022304 035f7573 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s_type....P.#..b + 65120: 75735f64 61746100 00001967 02231408 us_data....g.#.. + 65130: 6d6f645f 6e616d65 00000019 82022318 mod_name......#. + 65140: 0869666e 616d6500 00001982 02231c00 .ifname......#.. + 65150: 09616466 5f6f735f 68616e64 6c655f74 .adf_os_handle_t + 65160: 00000003 f2030000 16580400 02010201 .........X...... + 65170: 095f5f61 64665f6f 735f7369 7a655f74 .__adf_os_size_t + 65180: 00000003 f5140400 001a7c0e 415f4641 ..........|.A_FA + 65190: 4c534500 000e415f 54525545 00010009 LSE...A_TRUE.... + 651a0: 615f626f 6f6c5f74 0000001a 62030000 a_bool_t....b... + 651b0: 14ea0400 095f5f61 64665f6f 735f646d .....__adf_os_dm + 651c0: 615f6d61 705f7400 00001a8a 02010d61 a_map_t........a + 651d0: 64665f6f 735f6361 6368655f 73796e63 df_os_cache_sync + 651e0: 00040000 1b140e41 44465f53 594e435f .......ADF_SYNC_ + 651f0: 50524552 45414400 000e4144 465f5359 PREREAD...ADF_SY + 65200: 4e435f50 52455752 49544500 020e4144 NC_PREWRITE...AD + 65210: 465f5359 4e435f50 4f535452 45414400 F_SYNC_POSTREAD. + 65220: 010e4144 465f5359 4e435f50 4f535457 ..ADF_SYNC_POSTW + 65230: 52495445 00030009 6164665f 6f735f63 RITE....adf_os_c + 65240: 61636865 5f73796e 635f7400 00001aab ache_sync_t..... + 65250: 02010961 64665f6f 735f7369 7a655f74 ...adf_os_size_t + 65260: 0000001a 4d060000 1b2f0109 6164665f ....M..../..adf_ + 65270: 6f735f64 6d615f6d 61705f74 0000001a os_dma_map_t.... + 65280: 91030000 1b480400 06000003 f2010300 .....H.......... + 65290: 001a9104 00060000 03f20102 01060000 ................ + 652a0: 157d0102 01047368 6f727420 696e7400 .}....short int. + 652b0: 05020941 5f494e54 31360000 001b8209 ...A_INT16...... + 652c0: 5f5f615f 696e7431 365f7400 00001b8f __a_int16_t..... + 652d0: 09615f69 6e743136 5f740000 001b9c04 .a_int16_t...... + 652e0: 7369676e 65642063 68617200 05010941 signed char....A + 652f0: 5f494e54 38000000 1bbc095f 5f615f69 _INT8......__a_i + 65300: 6e74385f 74000000 1bcb0961 5f696e74 nt8_t......a_int + 65310: 385f7400 00001bd7 120c0000 1c4e0873 8_t..........N.s + 65320: 7570706f 72746564 00000016 02022300 upported......#. + 65330: 08616476 65727469 7a656400 00001602 .advertized..... + 65340: 02230408 73706565 64000000 1bad0223 .#..speed......# + 65350: 08086475 706c6578 0000001b e702230a ..duplex......#. + 65360: 08617574 6f6e6567 00000016 6902230b .autoneg....i.#. + 65370: 000f0000 16690600 001c5b10 05000761 .....i....[....a + 65380: 64665f6e 65745f65 74686164 64720006 df_net_ethaddr.. + 65390: 00001c7f 08616464 72000000 1c4e0223 .....addr....N.# + 653a0: 0000095f 5f615f75 696e7431 365f7400 ...__a_uint16_t. + 653b0: 000012d7 09615f75 696e7431 365f7400 .....a_uint16_t. + 653c0: 00001c7f 120e0000 1ce30865 74686572 ...........ether + 653d0: 5f64686f 73740000 001c4e02 23000865 _dhost....N.#..e + 653e0: 74686572 5f73686f 73740000 001c4e02 ther_shost....N. + 653f0: 23060865 74686572 5f747970 65000000 #..ether_type... + 65400: 1c910223 0c001214 00001da4 1569705f ...#.........ip_ + 65410: 76657273 696f6e00 00001669 01000402 version....i.... + 65420: 23001569 705f686c 00000016 69010404 #..ip_hl....i... + 65430: 02230008 69705f74 6f730000 00166902 .#..ip_tos....i. + 65440: 23010869 705f6c65 6e000000 1c910223 #..ip_len......# + 65450: 02086970 5f696400 00001c91 02230408 ..ip_id......#.. + 65460: 69705f66 7261675f 6f666600 00001c91 ip_frag_off..... + 65470: 02230608 69705f74 746c0000 00166902 .#..ip_ttl....i. + 65480: 23080869 705f7072 6f746f00 00001669 #..ip_proto....i + 65490: 02230908 69705f63 6865636b 0000001c .#..ip_check.... + 654a0: 9102230a 0869705f 73616464 72000000 ..#..ip_saddr... + 654b0: 16020223 0c086970 5f646164 64720000 ...#..ip_daddr.. + 654c0: 00160202 23100007 6164665f 6e65745f ....#...adf_net_ + 654d0: 766c616e 68647200 0400001d f6087470 vlanhdr.......tp + 654e0: 69640000 001c9102 23001570 72696f00 id......#..prio. + 654f0: 00001669 01000302 23021563 66690000 ...i....#..cfi.. + 65500: 00166901 03010223 02157669 64000000 ..i....#..vid... + 65510: 1c910204 0c022302 00076164 665f6e65 ......#...adf_ne + 65520: 745f7669 64000200 001e2715 72657300 t_vid.....'.res. + 65530: 00001669 01000402 23001576 616c0000 ...i....#..val.. + 65540: 001c9102 040c0223 0000120c 00001e63 .......#.......c + 65550: 0872785f 62756673 697a6500 00001602 .rx_bufsize..... + 65560: 02230008 72785f6e 64657363 00000016 .#..rx_ndesc.... + 65570: 02022304 0874785f 6e646573 63000000 ..#..tx_ndesc... + 65580: 16020223 08001208 00001e89 08706f6c ...#.........pol + 65590: 6c656400 00001a7c 02230008 706f6c6c led....|.#..poll + 655a0: 5f777400 00001602 02230400 0f000016 _wt......#...... + 655b0: 69400000 1e96103f 00124600 001ebe08 i@.....?..F..... + 655c0: 69665f6e 616d6500 00001e89 02230008 if_name......#.. + 655d0: 6465765f 61646472 0000001c 4e022340 dev_addr....N.#@ + 655e0: 00140400 001ef50e 4144465f 4f535f44 ........ADF_OS_D + 655f0: 4d415f4d 41534b5f 33324249 5400000e MA_MASK_32BIT... + 65600: 4144465f 4f535f44 4d415f4d 41534b5f ADF_OS_DMA_MASK_ + 65610: 36344249 54000100 09616466 5f6f735f 64BIT....adf_os_ + 65620: 646d615f 6d61736b 5f740000 001ebe07 dma_mask_t...... + 65630: 6164665f 646d615f 696e666f 00080000 adf_dma_info.... + 65640: 1f420864 6d615f6d 61736b00 00001ef5 .B.dma_mask..... + 65650: 02230008 73675f6e 73656773 00000016 .#..sg_nsegs.... + 65660: 02022304 00140400 001f980e 4144465f ..#.........ADF_ + 65670: 4e45545f 434b5355 4d5f4e4f 4e450000 NET_CKSUM_NONE.. + 65680: 0e414446 5f4e4554 5f434b53 554d5f54 .ADF_NET_CKSUM_T + 65690: 43505f55 44505f49 50763400 010e4144 CP_UDP_IPv4...AD + 656a0: 465f4e45 545f434b 53554d5f 5443505f F_NET_CKSUM_TCP_ + 656b0: 5544505f 49507636 00020009 6164665f UDP_IPv6....adf_ + 656c0: 6e65745f 636b7375 6d5f7479 70655f74 net_cksum_type_t + 656d0: 0000001f 42120800 001fdb08 74785f63 ....B.......tx_c + 656e0: 6b73756d 0000001f 98022300 0872785f ksum......#..rx_ + 656f0: 636b7375 6d000000 1f980223 04000961 cksum......#...a + 65700: 64665f6e 65745f63 6b73756d 5f696e66 df_net_cksum_inf + 65710: 6f5f7400 00001fb2 14040000 20340e41 o_t......... 4.A + 65720: 44465f4e 45545f54 534f5f4e 4f4e4500 DF_NET_TSO_NONE. + 65730: 000e4144 465f4e45 545f5453 4f5f4950 ..ADF_NET_TSO_IP + 65740: 56340001 0e414446 5f4e4554 5f54534f V4...ADF_NET_TSO + 65750: 5f414c4c 00020009 6164665f 6e65745f _ALL....adf_net_ + 65760: 74736f5f 74797065 5f740000 001ff512 tso_type_t...... + 65770: 10000020 8808636b 73756d5f 63617000 ... ..cksum_cap. + 65780: 00001fdb 02230008 74736f00 00002034 .....#..tso... 4 + 65790: 02230808 766c616e 5f737570 706f7274 .#..vlan_support + 657a0: 65640000 00166902 230c0012 20000021 ed....i.#... ..! + 657b0: 21087478 5f706163 6b657473 00000016 !.tx_packets.... + 657c0: 02022300 0872785f 7061636b 65747300 ..#..rx_packets. + 657d0: 00001602 02230408 74785f62 79746573 .....#..tx_bytes + 657e0: 00000016 02022308 0872785f 62797465 ......#..rx_byte + 657f0: 73000000 16020223 0c087478 5f64726f s......#..tx_dro + 65800: 70706564 00000016 02022310 0872785f pped......#..rx_ + 65810: 64726f70 70656400 00001602 02231408 dropped......#.. + 65820: 72785f65 72726f72 73000000 16020223 rx_errors......# + 65830: 18087478 5f657272 6f727300 00001602 ..tx_errors..... + 65840: 02231c00 09616466 5f6e6574 5f657468 .#...adf_net_eth + 65850: 61646472 5f740000 001c5b16 00002121 addr_t....[...!! + 65860: 03000000 2146107f 00176164 665f6e65 ....!F....adf_ne + 65870: 745f636d 645f6d63 61646472 00030400 t_cmd_mcaddr.... + 65880: 00217d08 6e656c65 6d000000 16020223 .!}.nelem......# + 65890: 00086d63 61737400 00002138 02230400 ..mcast...!8.#.. + 658a0: 09616466 5f6e6574 5f636d64 5f6c696e .adf_net_cmd_lin + 658b0: 6b5f696e 666f5f74 0000001b f5096164 k_info_t......ad + 658c0: 665f6e65 745f636d 645f706f 6c6c5f69 f_net_cmd_poll_i + 658d0: 6e666f5f 74000000 1e630961 64665f6e nfo_t....c.adf_n + 658e0: 65745f63 6d645f63 6b73756d 5f696e66 et_cmd_cksum_inf + 658f0: 6f5f7400 00001fdb 09616466 5f6e6574 o_t......adf_net + 65900: 5f636d64 5f72696e 675f696e 666f5f74 _cmd_ring_info_t + 65910: 0000001e 27096164 665f6e65 745f636d ....'.adf_net_cm + 65920: 645f646d 615f696e 666f5f74 0000001f d_dma_info_t.... + 65930: 0c096164 665f6e65 745f636d 645f7669 ..adf_net_cmd_vi + 65940: 645f7400 00001c91 09616466 5f6e6574 d_t......adf_net + 65950: 5f636d64 5f6f6666 6c6f6164 5f636170 _cmd_offload_cap + 65960: 5f740000 00204c09 6164665f 6e65745f _t... L.adf_net_ + 65970: 636d645f 73746174 735f7400 00002088 cmd_stats_t... . + 65980: 09616466 5f6e6574 5f636d64 5f6d6361 .adf_net_cmd_mca + 65990: 6464725f 74000000 21460d61 64665f6e ddr_t...!F.adf_n + 659a0: 65745f63 6d645f6d 63617374 5f636170 et_cmd_mcast_cap + 659b0: 00040000 22bf0e41 44465f4e 45545f4d ...."..ADF_NET_M + 659c0: 43415354 5f535550 00000e41 44465f4e CAST_SUP...ADF_N + 659d0: 45545f4d 43415354 5f4e4f54 53555000 ET_MCAST_NOTSUP. + 659e0: 01000961 64665f6e 65745f63 6d645f6d ...adf_net_cmd_m + 659f0: 63617374 5f636170 5f740000 00227718 cast_cap_t..."w. + 65a00: 03040000 2391086c 696e6b5f 696e666f ....#..link_info + 65a10: 00000021 7d022300 08706f6c 6c5f696e ...!}.#..poll_in + 65a20: 666f0000 00219a02 23000863 6b73756d fo...!..#..cksum + 65a30: 5f696e66 6f000000 21b70223 00087269 _info...!..#..ri + 65a40: 6e675f69 6e666f00 000021d5 02230008 ng_info...!..#.. + 65a50: 646d615f 696e666f 00000021 f2022300 dma_info...!..#. + 65a60: 08766964 00000022 0e022300 086f6666 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ED...A_STATUS_EN + 65c70: 4f454e54 00020e41 5f535441 5455535f OENT...A_STATUS_ + 65c80: 454e4f4d 454d0003 0e415f53 54415455 ENOMEM...A_STATU + 65c90: 535f4549 4e56414c 00040e41 5f535441 S_EINVAL...A_STA + 65ca0: 5455535f 45494e50 524f4752 45535300 TUS_EINPROGRESS. + 65cb0: 050e415f 53544154 55535f45 4e4f5453 ..A_STATUS_ENOTS + 65cc0: 55505000 060e415f 53544154 55535f45 UPP...A_STATUS_E + 65cd0: 42555359 00070e41 5f535441 5455535f BUSY...A_STATUS_ + 65ce0: 45324249 4700080e 415f5354 41545553 E2BIG...A_STATUS + 65cf0: 5f454144 44524e4f 54415641 494c0009 _EADDRNOTAVAIL.. + 65d00: 0e415f53 54415455 535f454e 58494f00 .A_STATUS_ENXIO. + 65d10: 0a0e415f 53544154 55535f45 4641554c ..A_STATUS_EFAUL + 65d20: 54000b0e 415f5354 41545553 5f45494f T...A_STATUS_EIO + 65d30: 000c0009 615f7374 61747573 5f740000 ....a_status_t.. + 65d40: 00251b06 00002610 01060000 00fd0102 .%....&......... + 65d50: 01096164 665f6e62 75665f74 00000024 ..adf_nbuf_t...$ + 65d60: 97140400 0026750e 4144465f 4f535f44 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_disarm....I.#.. + 78290: 5f74696d 65725f73 6574666e 00000007 _timer_setfn.... + 782a0: 7b02230c 085f7469 6d65725f 72756e00 {.#.._timer_run. + 782b0: 0000010c 02231000 09424f4f 4c45414e .....#...BOOLEAN + 782c0: 00000001 8d060000 07f80103 00000805 ................ + 782d0: 04000600 0007f801 03000008 12040006 ................ + 782e0: 000007f8 01030000 081f0400 07726f6d .............rom + 782f0: 705f6170 69001000 00089108 5f726f6d p_api......._rom + 78300: 705f696e 69740000 00010c02 2300085f p_init......#.._ + 78310: 726f6d70 5f646f77 6e6c6f61 64000000 romp_download... + 78320: 080b0223 04085f72 6f6d705f 696e7374 ...#.._romp_inst + 78330: 616c6c00 00000818 02230808 5f726f6d all......#.._rom + 78340: 705f6465 636f6465 00000008 2502230c p_decode....%.#. + 78350: 0007726f 6d5f7061 7463685f 73740010 ..rom_patch_st.. + 78360: 000008ed 08637263 31360000 00018d02 .....crc16...... + 78370: 2300086c 656e0000 00018d02 2302086c #..len......#..l + 78380: 645f6164 64720000 0001b002 23040866 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klet.......func. + 78490: 000009a7 02230008 61726700 00000408 .....#..arg..... + 784a0: 02230408 73746174 65000000 01130223 .#..state......# + 784b0: 08086e65 78740000 0009ff02 230c0003 ..next......#... + 784c0: 000009bb 04000300 0009bb04 0009415f ..............A_ + 784d0: 7461736b 6c65745f 74000000 09bb0300 tasklet_t....... + 784e0: 000a0d04 00020103 00000a25 04000201 ...........%.... + 784f0: 0300000a 2e040007 7461736b 6c65745f ........tasklet_ + 78500: 61706900 1400000a c3085f74 61736b6c api......._taskl + 78510: 65745f69 6e697400 0000010c 02230008 et_init......#.. + 78520: 5f746173 6b6c6574 5f696e69 745f7461 _tasklet_init_ta + 78530: 736b0000 000a2702 2304085f 7461736b sk....'.#.._task + 78540: 6c65745f 64697361 626c6500 00000a30 let_disable....0 + 78550: 02230808 5f746173 6b6c6574 5f736368 .#.._tasklet_sch + 78560: 6564756c 65000000 0a300223 0c085f74 edule....0.#.._t + 78570: 61736b6c 65745f72 756e0000 00010c02 asklet_run...... + 78580: 23100002 01030000 0ac30400 06000009 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./project/cust/g + 7c9d0: 656e6170 702f5242 2d323030 372e322f enapp/RB-2007.2/ + 7c9e0: 6275696c 642f6174 6865726f 732f7072 build/atheros/pr + 7c9f0: 6f642f4d 61677069 655f5030 2f383337 od/Magpie_P0/837 + 7ca00: 34332f78 6275696c 642f4f53 2f68616c 43/xbuild/OS/hal + 7ca10: 0078742d 78636320 666f7220 372e312e .xt-xcc for 7.1. + 7ca20: 30202d4f 50543a61 6c69676e 5f696e73 0 -OPT:align_ins + 7ca30: 74727563 74696f6e 733d3332 202d4f32 tructions=32 -O2 + 7ca40: 202d6733 00010002 756e7369 676e6564 -g3....unsigned + 7ca50: 20696e74 00070403 000000e2 04587468 int.........Xth + 7ca60: 616c5f72 656c6561 73655f6d 616a6f72 al_release_major + 7ca70: 00000000 f2050300 4e879001 04587468 ........N....Xth + 7ca80: 616c5f72 656c6561 73655f6d 696e6f72 al_release_minor + 7ca90: 00000000 f2050300 500b4401 02636861 ........P.D..cha + 7caa0: 72000701 03000001 37030000 01370500 r.......7....7.. + 7cab0: 00014404 00030000 01490300 00013705 ..D......I....7. + 7cac0: 00000155 04000458 7468616c 5f72656c ...U...Xthal_rel + 7cad0: 65617365 5f6e616d 65000000 01500503 ease_name....P.. + 7cae0: 004e8794 01060000 01370600 00018d07 .N.......7...... + 7caf0: 05000458 7468616c 5f72656c 65617365 ...Xthal_release + 7cb00: 5f696e74 65726e61 6c000000 01500503 _internal....P.. + 7cb10: 00500b48 01045874 68616c5f 7265765f .P.H..Xthal_rev_ + 7cb20: 6e6f0000 0000f205 03004e87 98010458 no........N....X + 7cb30: 7468616c 5f6e756d 5f617265 67730000 thal_num_aregs.. + 7cb40: 0000f205 03004e87 9c010275 6e736967 ......N....unsig + 7cb50: 6e656420 63686172 00070103 000001e5 ned char........ + 7cb60: 04587468 616c5f6e 756d5f61 72656773 .Xthal_num_aregs + 7cb70: 5f6c6f67 32000000 01f60503 004e87a0 _log2........N.. + 7cb80: 01045874 68616c5f 6d656d6f 72795f6f ..Xthal_memory_o + 7cb90: 72646572 00000001 f6050300 4e87a101 rder........N... + 7cba0: 04587468 616c5f68 6176655f 77696e64 .Xthal_have_wind + 7cbb0: 6f776564 00000001 f6050300 4e87a201 owed........N... + 7cbc0: 04587468 616c5f68 6176655f 64656e73 .Xthal_have_dens + 7cbd0: 69747900 000001f6 0503004e 87a30104 ity........N.... + 7cbe0: 58746861 6c5f6861 76655f62 6f6f6c65 Xthal_have_boole + 7cbf0: 616e7300 000001f6 05030050 0b4c0104 ans........P.L.. + 7cc00: 58746861 6c5f6861 76655f6c 6f6f7073 Xthal_have_loops + 7cc10: 00000001 f6050300 4e87a401 04587468 ........N....Xth + 7cc20: 616c5f68 6176655f 6e736100 000001f6 al_have_nsa..... + 7cc30: 0503004e 87a50104 58746861 6c5f6861 ...N....Xthal_ha + 7cc40: 76655f6d 696e6d61 78000000 01f60503 ve_minmax....... + 7cc50: 004e87a6 01045874 68616c5f 68617665 .N....Xthal_have + 7cc60: 5f736578 74000000 01f60503 004e87a7 _sext........N.. + 7cc70: 01045874 68616c5f 68617665 5f636c61 ..Xthal_have_cla + 7cc80: 6d707300 000001f6 05030050 0b4d0104 mps........P.M.. + 7cc90: 58746861 6c5f6861 76655f6d 61633136 Xthal_have_mac16 + 7cca0: 00000001 f6050300 500b4e01 04587468 ........P.N..Xth + 7ccb0: 616c5f68 6176655f 6d756c31 36000000 al_have_mul16... + 7ccc0: 01f60503 004e87a8 01045874 68616c5f .....N....Xthal_ + 7ccd0: 68617665 5f667000 000001f6 05030050 have_fp........P + 7cce0: 0b4f0104 58746861 6c5f6861 76655f73 .O..Xthal_have_s + 7ccf0: 70656375 6c617469 6f6e0000 0001f605 peculation...... + 7cd00: 0300500b 50010458 7468616c 5f686176 ..P.P..Xthal_hav + 7cd10: 655f6578 63657074 696f6e73 00000001 e_exceptions.... + 7cd20: f6050300 4e87a901 04587468 616c5f78 ....N....Xthal_x + 7cd30: 65615f76 65727369 6f6e0000 0001f605 ea_version...... + 7cd40: 03004e87 aa010458 7468616c 5f686176 ..N....Xthal_hav + 7cd50: 655f696e 74657272 75707473 00000001 e_interrupts.... + 7cd60: f6050300 4e87ab01 04587468 616c5f68 ....N....Xthal_h + 7cd70: 6176655f 68696768 6c657665 6c5f696e ave_highlevel_in + 7cd80: 74657272 75707473 00000001 f6050300 terrupts........ + 7cd90: 4e87ac01 04587468 616c5f68 6176655f N....Xthal_have_ + 7cda0: 6e6d6900 000001f6 0503004e 87ad0104 nmi........N.... + 7cdb0: 58746861 6c5f6861 76655f70 72696400 Xthal_have_prid. + 7cdc0: 000001f6 0503004e 87ae0104 58746861 .......N....Xtha + 7cdd0: 6c5f6861 76655f72 656c6561 73655f73 l_have_release_s + 7cde0: 796e6300 000001f6 0503004e 87af0104 ync........N.... + 7cdf0: 58746861 6c5f6861 76655f73 33326331 Xthal_have_s32c1 + 7ce00: 69000000 01f60503 004e87b0 01045874 i........N....Xt + 7ce10: 68616c5f 68617665 5f746872 65616470 hal_have_threadp + 7ce20: 74720000 0001f605 03004e87 b1010458 tr........N....X + 7ce30: 7468616c 5f686176 655f7069 66000000 thal_have_pif... + 7ce40: 01f60503 004e87b2 01027368 6f727420 .....N....short + 7ce50: 756e7369 676e6564 20696e74 00070203 unsigned int.... + 7ce60: 000004e4 04587468 616c5f6e 756d5f77 .....Xthal_num_w + 7ce70: 72697465 62756666 65725f65 6e747269 ritebuffer_entri + 7ce80: 65730000 0004fa05 03004e87 b4010458 es........N....X + 7ce90: 7468616c 5f627569 6c645f75 6e697175 thal_build_uniqu + 7cea0: 655f6964 00000000 f2050300 4e87b801 e_id........N... + 7ceb0: 04587468 616c5f68 775f636f 6e666967 .Xthal_hw_config + 7cec0: 69643000 000000f2 0503004e 87bc0104 id0........N.... + 7ced0: 58746861 6c5f6877 5f636f6e 66696769 Xthal_hw_configi + 7cee0: 64310000 0000f205 03004e87 c0010458 d1........N....X + 7cef0: 7468616c 5f68775f 72656c65 6173655f thal_hw_release_ + 7cf00: 6d616a6f 72000000 00f20503 004e87c4 major........N.. + 7cf10: 01045874 68616c5f 68775f72 656c6561 ..Xthal_hw_relea + 7cf20: 73655f6d 696e6f72 00000000 f2050300 se_minor........ + 7cf30: 500b5401 04587468 616c5f68 775f7265 P.T..Xthal_hw_re + 7cf40: 6c656173 655f6e61 6d650000 00015005 lease_name....P. + 7cf50: 03004e87 c8010600 00013708 000005fe ..N.......7..... + 7cf60: 07070004 58746861 6c5f6877 5f6d696e ....Xthal_hw_min + 7cf70: 5f766572 73696f6e 5f6d616a 6f720000 _version_major.. + 7cf80: 0000f205 03004e87 cc010458 7468616c ......N....Xthal + 7cf90: 5f68775f 6d696e5f 76657273 696f6e5f _hw_min_version_ + 7cfa0: 6d696e6f 72000000 00f20503 00500b58 minor........P.X + 7cfb0: 01045874 68616c5f 68775f6d 61785f76 ..Xthal_hw_max_v + 7cfc0: 65727369 6f6e5f6d 616a6f72 00000000 ersion_major.... + 7cfd0: f2050300 4e87d001 04587468 616c5f68 ....N....Xthal_h + 7cfe0: 775f6d61 785f7665 7273696f 6e5f6d69 w_max_version_mi + 7cff0: 6e6f7200 000000f2 05030050 0b5c0104 nor........P.\.. + 7d000: 58746861 6c5f6877 5f72656c 65617365 Xthal_hw_release + 7d010: 5f696e74 65726e61 6c000000 01500503 _internal....P.. + 7d020: 00500b60 01045874 68616c5f 68617665 .P.`..Xthal_have + 7d030: 5f737061 6e6e696e 675f7761 79000000 _spanning_way... + 7d040: 01f60503 004e87d4 01045874 68616c5f .....N....Xthal_ + 7d050: 68617665 5f696465 6e746974 795f6d61 have_identity_ma + 7d060: 70000000 01f60503 004e87d5 01045874 p........N....Xt + 7d070: 68616c5f 68617665 5f6d696d 69635f63 hal_have_mimic_c + 7d080: 61636865 61747472 00000001 f6050300 acheattr........ + 7d090: 4e87d601 04587468 616c5f68 6176655f N....Xthal_have_ + 7d0a0: 786c745f 63616368 65617474 72000000 xlt_cacheattr... + 7d0b0: 01f60503 00500b64 01045874 68616c5f .....P.d..Xthal_ + 7d0c0: 68617665 5f636163 68656174 74720000 have_cacheattr.. + 7d0d0: 0001f605 0300500b 65010458 7468616c ......P.e..Xthal + 7d0e0: 5f686176 655f746c 62730000 0001f605 _have_tlbs...... + 7d0f0: 03004e87 d7010458 7468616c 5f6d6d75 ..N....Xthal_mmu + 7d100: 5f617369 645f6269 74730000 0001f605 _asid_bits...... + 7d110: 0300500b 66010458 7468616c 5f6d6d75 ..P.f..Xthal_mmu + 7d120: 5f617369 645f6b65 726e656c 00000001 _asid_kernel.... + 7d130: f6050300 500b6701 04587468 616c5f6d ....P.g..Xthal_m + 7d140: 6d755f72 696e6773 00000001 f6050300 mu_rings........ + 7d150: 4e87d801 04587468 616c5f6d 6d755f72 N....Xthal_mmu_r + 7d160: 696e675f 62697473 00000001 f6050300 ing_bits........ + 7d170: 500b6801 04587468 616c5f6d 6d755f73 P.h..Xthal_mmu_s + 7d180: 725f6269 74730000 0001f605 0300500b r_bits........P. + 7d190: 69010458 7468616c 5f6d6d75 5f63615f i..Xthal_mmu_ca_ + 7d1a0: 62697473 00000001 f6050300 4e87d901 bits........N... + 7d1b0: 04587468 616c5f6d 6d755f6d 61785f70 .Xthal_mmu_max_p + 7d1c0: 74655f70 6167655f 73697a65 00000000 te_page_size.... + 7d1d0: f2050300 4e87dc01 04587468 616c5f6d ....N....Xthal_m + 7d1e0: 6d755f6d 696e5f70 74655f70 6167655f mu_min_pte_page_ + 7d1f0: 73697a65 00000000 f2050300 4e87e001 size........N... + 7d200: 04587468 616c5f69 746c625f 7761795f .Xthal_itlb_way_ + 7d210: 62697473 00000001 f6050300 500b6a01 bits........P.j. + 7d220: 04587468 616c5f69 746c625f 77617973 .Xthal_itlb_ways + 7d230: 00000001 f6050300 4e87e401 04587468 ........N....Xth + 7d240: 616c5f69 746c625f 6172665f 77617973 al_itlb_arf_ways + 7d250: 00000001 f6050300 500b6b01 04587468 ........P.k..Xth + 7d260: 616c5f64 746c625f 7761795f 62697473 al_dtlb_way_bits + 7d270: 00000001 f6050300 500b6c01 04587468 ........P.l..Xth + 7d280: 616c5f64 746c625f 77617973 00000001 al_dtlb_ways.... + 7d290: f6050300 4e87e501 04587468 616c5f64 ....N....Xthal_d + 7d2a0: 746c625f 6172665f 77617973 00000001 tlb_arf_ways.... + 7d2b0: f6050300 500b6d01 04587468 616c5f6e ....P.m..Xthal_n + 7d2c0: 756d5f69 6e737472 6f6d0000 0001f605 um_instrom...... + 7d2d0: 0300500b 6e010458 7468616c 5f6e756d ..P.n..Xthal_num + 7d2e0: 5f696e73 7472616d 00000001 f6050300 _instram........ + 7d2f0: 4e87e601 04587468 616c5f6e 756d5f64 N....Xthal_num_d + 7d300: 61746172 6f6d0000 0001f605 0300500b atarom........P. + 7d310: 6f010458 7468616c 5f6e756d 5f646174 o..Xthal_num_dat + 7d320: 6172616d 00000001 f6050300 4e87e701 aram........N... + 7d330: 04587468 616c5f6e 756d5f78 6c6d6900 .Xthal_num_xlmi. + 7d340: 000001f6 05030050 0b700103 000000e2 .......P.p...... + 7d350: 06000009 e6040000 09f80700 00030000 ................ + 7d360: 09eb0300 0000e206 000009fd 0400000a ................ + 7d370: 0f070000 04587468 616c5f69 6e737472 .....Xthal_instr + 7d380: 6f6d5f76 61646472 00000009 f8050300 om_vaddr........ + 7d390: 4e87ec01 04587468 616c5f69 6e737472 N....Xthal_instr + 7d3a0: 6f6d5f70 61646472 00000009 f8050300 om_paddr........ + 7d3b0: 4e87f001 04587468 616c5f69 6e737472 N....Xthal_instr + 7d3c0: 6f6d5f73 697a6500 000009f8 0503004e om_size........N + 7d3d0: 87f40104 58746861 6c5f696e 73747261 ....Xthal_instra + 7d3e0: 6d5f7661 64647200 000009f8 0503004e m_vaddr........N + 7d3f0: 87f80104 58746861 6c5f696e 73747261 ....Xthal_instra + 7d400: 6d5f7061 64647200 000009f8 0503004e m_paddr........N + 7d410: 87fc0104 58746861 6c5f696e 73747261 ....Xthal_instra + 7d420: 6d5f7369 7a650000 0009f805 03004e88 m_size........N. + 7d430: 00010458 7468616c 5f646174 61726f6d ...Xthal_datarom + 7d440: 5f766164 64720000 0009f805 03004e88 _vaddr........N. + 7d450: 04010458 7468616c 5f646174 61726f6d ...Xthal_datarom + 7d460: 5f706164 64720000 0009f805 03004e88 _paddr........N. + 7d470: 08010458 7468616c 5f646174 61726f6d ...Xthal_datarom + 7d480: 5f73697a 65000000 09f80503 004e880c _size........N.. + 7d490: 01045874 68616c5f 64617461 72616d5f ..Xthal_dataram_ + 7d4a0: 76616464 72000000 09f80503 004e8810 vaddr........N.. + 7d4b0: 01045874 68616c5f 64617461 72616d5f ..Xthal_dataram_ + 7d4c0: 70616464 72000000 09f80503 004e8814 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b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/Magpie_api.h @@ -0,0 +1,226 @@ +/* + * @File: Magpie_api.h + * + * @Abstract: Magpie FW api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _MAGPIE_API_H +#define _MAGPIE_API_H + +#define MAGPIE_FW_BUILD + +#include "cmnos_api.h" +#ifdef MAGPIE_FW_BUILD +#include "vbuf_api.h" +#include "vdesc_api.h" +#include "usbfifo_api.h" +//#include "allocram_api.h" +#endif + +#include "hif_api.h" +#include "htc_api.h" +#include "wmi_svc_api.h" +#include "buf_pool_api.h" +#include "dma_engine_api.h" +#include "dma_lib.h" + +#if (SYSTEM_MODULE_SFLASH != 0) +#include "sflash_api.h" +#endif + +#define A_INDIR(sym) _A_MAGPIE_INDIRECTION_TABLE->sym + +#if SYSTEM_MODULE_DBG +/* debug Support */ +#define DBG_MODULE_INSTALL() cmnos_dbg_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dbg) +#define A_DBG_INIT() A_INDIR(dbg._dbg_init()) +#define A_DBG_TASK() A_INDIR(dbg._dbg_task()) +#else +#define A_DBG_INIT() +#define A_DBG_TASK() +#endif + +/* Serial Flash support */ +#if (SYSTEM_MODULE_SFLASH != 0) +#define SFLASH_MODULE_INSTALL() cmnos_sflash_module_install(&_A_MAGPIE_INDIRECTION_TABLE->sflash) +#define A_SFLASH_INIT() A_INDIR(sflash._sflash_init()) +#define A_SFLASH_ERASE(erase_type, addr) A_INDIR(sflash._sflash_erase(erase_type, addr)) +#define A_SFLASH_PROG(addr, len, buf) A_INDIR(sflash._sflash_program(addr, len, buf)) +#define A_SFLASH_READ(fast, addr, len, buf) A_INDIR(sflash._sflash_read(fast, addr, len, buf)) +#define A_SFLASH_RDSR() A_INDIR(sflash._sflash_rdsr()) +#else +#define A_SFLASH_INIT() +#define A_SFLASH_ERASE(erase_type, addr) +#define A_SFLASH_PROG(addr, len, buf) +#define A_SFLASH_READ(fast, addr, len, buf) +#define A_SFLASH_RDSR() +#endif + +/* DMA Engine Interface */ +#define DMA_ENGINE_MODULE_INSTALL() dma_engine_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_engine); +#define DMA_Engine_init() A_INDIR(dma_engine._init()) +#define DMA_Engine_config_rx_queue(q, nDesc, size) A_INDIR(dma_engine._config_rx_queue(q, nDesc, size)) +#define DMA_Engine_xmit_buf(q, buf) A_INDIR(dma_engine._xmit_buf(q, buf)) +#define DMA_Engine_flush_xmit(q) A_INDIR(dma_engine._flush_xmit(q)) +#define DMA_Engine_reap_recv_buf(q) A_INDIR(dma_engine._reap_recv_buf(q)) +#define DMA_Engine_return_recv_buf(q,buf) A_INDIR(dma_engine._return_recv_buf(q, buf)) +#define DMA_Engine_reap_xmited_buf(q) A_INDIR(dma_engine._reap_xmited_buf(q)) +#define DMA_Engine_swap_data(desc) A_INDIR(dma_engine._swap_data(desc)) +#define DMA_Engine_init_rx_queue(q) A_INDIR(dma_engine._init_rx_queue(q)) +#define DMA_Engine_init_tx_queue(q) A_INDIR(dma_engine._init_tx_queue(q)) +#define DMA_Engine_has_compl_packets(q) A_INDIR(dma_engine._has_compl_packets(q)) +#define DMA_Engine_desc_dump(q) A_INDIR(dma_engine._desc_dump(q)) +#define DMA_Engine_get_packet(q) A_INDIR(dma_engine._get_packet(q)) +#define DMA_Engine_reclaim_packet(q,desc) A_INDIR(dma_engine._reclaim_packet(q,desc)) +#define DMA_Engine_put_packet(q,desc) A_INDIR(dma_engine._put_packet(q,desc)) + +/*DMA Library support for GMAC & PCI(E)*/ +#define DMA_LIB_MODULE_INSTALL() dma_lib_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_lib) +#define dma_lib_tx_init(eng_no, if_type) A_INDIR(dma_lib.tx_init(eng_no, if_type)) +#define dma_lib_rx_init(eng_no, if_type) A_INDIR(dma_lib.rx_init(eng_no, if_type)) +#define dma_lib_rx_config(eng_no, desc, gran) A_INDIR(dma_lib.rx_config(eng_no, desc, gran)) +#define dma_lib_tx_start(eng_no) A_INDIR(dma_lib.tx_start(eng_no)) +#define dma_lib_rx_start(eng_no) A_INDIR(dma_lib.rx_start(eng_no)) +#define dma_lib_intr_status(if_type) A_INDIR(dma_lib.intr_status(if_type)) +#define dma_lib_hard_xmit(eng_no, buf) A_INDIR(dma_lib.hard_xmit(eng_no, buf)) +#define dma_lib_flush_xmit(eng_no) A_INDIR(dma_lib.flush_xmit(eng_no)) +#define dma_lib_xmit_done(eng_no) A_INDIR(dma_lib.xmit_done(eng_no)) +#define dma_lib_reap_xmitted(eng_no) A_INDIR(dma_lib.reap_xmitted(eng_no)) +#define dma_lib_reap_recv(eng_no) A_INDIR(dma_lib.reap_recv(eng_no)) +#define dma_lib_return_recv(eng_no, buf) A_INDIR(dma_lib.return_recv(eng_no, buf)) +#define dma_lib_recv_pkt(eng_no) A_INDIR(dma_lib.recv_pkt(eng_no)) + +/* HIF PCI Api's */ +#define hif_pci_boot_init() A_INDIR(hif_pci.pci_boot_init()) +#define hif_pci_init(pConfig) A_INDIR(hif_pci.pci_init(pConfig)) +#define hif_pci_reset() A_INDIR(hif_pci.pci_reset()) +#define hif_pci_enable() A_INDIR(hif_pci.pci_enable()) +#define hif_pci_get_pipe(eng) A_INDIR(hif_pci.pci_get_pipe(eng)) +#define hif_pci_get_tx_eng(pipe) A_INDIR(hif_pci.pci_get_tx_eng(pipe)) +#define hif_pci_get_rx_eng(pipe) A_INDIR(hif_pci.pci_get_rx_eng(pipe)) +#define hif_pci_reap_recv(sc, eng_no) A_INDIR(hif_pci.pci_reap_recv(sc, eng_no)) +#define hif_pci_reap_xmitted(sc, eng_no) A_INDIR(hif_pci.pci_reap_xmitted(sc, eng_no)) + +/* HIF support */ +#define HIF_MODULE_INSTALL() generic_hif_module_install(&_A_MAGPIE_INDIRECTION_TABLE->hif) +#define HIF_init(pConfig) A_INDIR(hif._init(pConfig)) +#define HIF_shutdown(h) A_INDIR(hif._shutdown(h)) +#define HIF_register_callback(h, pConfig) A_INDIR(hif._register_callback(h, pConfig)) +#define HIF_start(h) A_INDIR(hif._start(h)) +#define HIF_config_pipe(h, pipe, desc_list) A_INDIR(hif._config_pipe(h, pipe, desc_list)) +#define HIF_send_buffer(h, pipe, buf) A_INDIR(hif._send_buffer(h, pipe, buf)) +#define HIF_return_recv_buf(h, pipe, buf) A_INDIR(hif._return_recv_buf(h, pipe, buf)) +#define HIF_isr_handler(h) A_INDIR(hif._isr_handler(h)) +#define HIF_is_pipe_supported(h, pipe) A_INDIR(hif._is_pipe_supported(h, pipe)) +#define HIF_get_max_msg_len(h, pipe) A_INDIR(hif._get_max_msg_len(h, pipe)) +#define HIF_get_reserved_headroom(h) A_INDIR(hif._get_reserved_headroom(h)) +#define HIF_get_default_pipe(h,u,d) A_INDIR(hif._get_default_pipe(h,u,d)) +typedef void (*HIF_INSTALL_FUNC_T)(struct hif_api *apis); + +/* VBUF APIs */ +#ifdef MAGPIE_FW_BUILD +#define VBUF_MODULE_INSTALL() vbuf_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vbuf) +#define VBUF_init(nBuf) A_INDIR(vbuf._init(nBuf)) +#define VBUF_alloc_vbuf() A_INDIR(vbuf._alloc_vbuf()) +#define VBUF_free_vbuf(buf) A_INDIR(vbuf._free_vbuf(buf)) +#endif + +/* VDESC APIs */ +#ifdef MAGPIE_FW_BUILD +#define VDESC_MODULE_INSTALL() vdesc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vdesc) +#define VDESC_init(nDesc) A_INDIR(vdesc._init(nDesc)) +#define VDESC_alloc_vdesc() A_INDIR(vdesc._alloc_vdesc()) +#define VDESC_get_hw_desc(desc) A_INDIR(vdesc._get_hw_desc(desc)) +#define VDESC_swap_vdesc(dst, src) A_INDIR(vdesc._swap_vdesc(dst, src)) +#endif + +#define HTC_MODULE_INSTALL() htc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->htc) +#define HTC_init(SetupComplete, pConfig) A_INDIR(htc._HTC_Init(SetupComplete, pConfig)) +#define HTC_Shutdown(h) A_INDIR(htc._HTC_Shutdown(h)) +#define HTC_RegisterService(h, s) A_INDIR(htc._HTC_RegisterService(h, s)) +#define HTC_Ready(h) A_INDIR(htc._HTC_Ready(h)) +#define HTC_SendMsg(h, endpt, buf) A_INDIR(htc._HTC_SendMsg(h, endpt, buf)) +#define HTC_ReturnBuffers(h, endpt, buf) A_INDIR(htc._HTC_ReturnBuffers(h, endpt, buf)) +#define HTC_ReturnBuffersList(h, endpt, hd) A_INDIR(htc._HTC_ReturnBuffersList(h, endpt, hd)) +#define HTC_GetReservedHeadroom(h) A_INDIR(htc._HTC_GetReservedHeadroom(h)) + +#define HTC_NotifyTargetInserted(h) +#define HTC_NotifyTargetDetached(h) + +/* WMI SVC module */ +#define WMI_SERVICE_MODULE_INSTALL() WMI_service_module_install(&_A_MAGPIE_INDIRECTION_TABLE->wmi_svc_api) +#define WMI_Init(pCfg) A_INDIR(wmi_svc_api._WMI_Init(pCfg)) +#define WMI_RegisterDispatchTable(h,pT) A_INDIR(wmi_svc_api._WMI_RegisterDispatchTable(h, pT)) +#define WMI_AllocEvent(h,ec,len) A_INDIR(wmi_svc_api._WMI_AllocEvent(h, ec, len)) +#define WMI_SendEvent(h,ev,id,seq,len) A_INDIR(wmi_svc_api._WMI_SendEvent(h, ev, id, seq, len)) +#define WMI_GetPendingEventsCount() A_INDIR(wmi_svc_api._WMI_GetPendingEventsCount()) +#define WMI_GetControlEp() A_INDIR(wmi_svc_api._WMI_GetControlEp()) +#define WMI_SendCompleteHandler(ep, buf) A_INDIR(wmi_svc_api._WMI_SendCompleteHandler(ep, buf)) +#define WMI_Shutdown(h) A_INDIR(wmi_svc_api._WMI_Shutdown(h)) + +/* USB FIFO module */ +#define USBFIFO_MODULE_INSTALL() usbfifo_module_install(&_A_MAGPIE_INDIRECTION_TABLE->usbfifo_api) +#define USBFIFO_init(pConfig) A_INDIR(usbfifo_api._init(pConfig)) +#define USBFIFO_enable_event_isr() A_INDIR(usbfifo_api._enable_event_isr()) + +/* BUF pool module */ +#define BUF_POOL_MODULE_INSTALL() buf_pool_module_install(&_A_MAGPIE_INDIRECTION_TABLE->buf_pool) +#define BUF_Pool_init(h) A_INDIR(buf_pool._init(h)) +#define BUF_Pool_shutdown(h) A_INDIR(buf_pool._shutdown(h)) +#define BUF_Pool_create_pool(h, id, nItems, nSize) A_INDIR(buf_pool._create_pool(h, id, nItems, nSize)) +#define BUF_Pool_alloc_buf(h, id, reserve) A_INDIR(buf_pool._alloc_buf(h, id, reserve)) +#define BUF_Pool_alloc_buf_align(h, id, reserve,align) A_INDIR(buf_pool._alloc_buf_align(h, id, reserve,align)) +#define BUF_Pool_free_buf(h, id, buf) A_INDIR(buf_pool._free_buf(h, id, buf)) + +/* + * This defines the layout of the indirection table, which + * is used to access exported APIs of various modules. The + * layout is shared across ROM and RAM code. RAM code may + * call into ROM and ROM code may call into RAM. Because + * of the latter, existing offsets must not change for the + * lifetime of a revision of ROM; but new members may be + * added at the end. + */ +typedef struct _A_magpie_indirection_table { + _A_cmnos_indirection_table_t cmnos; + +//#if SYSTEM_MODULE_DBG + struct dbg_api dbg; // move to firmware not in cmnos +//#endif + struct hif_api hif; + struct htc_apis htc; + WMI_SVC_APIS wmi_svc_api; + struct usbfifo_api usbfifo_api; + struct buf_pool_api buf_pool; +#ifdef MAGPIE_FW_BUILD + struct vbuf_api vbuf; + struct vdesc_api vdesc; + struct allocram_api allocram; +#endif + struct dma_engine_api dma_engine; + struct dma_lib_api dma_lib; + +#if SYSTEM_MODULE_PCI + struct hif_pci_api hif_pci; +#endif + // structure to be added after this.... +#if (SYSTEM_MODULE_SFLASH != 0) + struct sflash_api sflash; +#endif +} _A_magpie_indirection_table_t; + +extern _A_magpie_indirection_table_t _indir_tbl; +#define _A_MAGPIE_INDIRECTION_TABLE_SIZE sizeof(_A_magpie_indirection_table_t) +#if defined(__mips__) +#define _A_MAGPIE_INDIRECTION_TABLE ((_A_magpie_indirection_table_t *)0x700) +#else +#define _A_MAGPIE_INDIRECTION_TABLE (&_indir_tbl) +#endif + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/adf_nbuf_pvt.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/adf_nbuf_pvt.h new file mode 100755 index 0000000..eb200fe --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/adf_nbuf_pvt.h @@ -0,0 +1,425 @@ +/* + * (c) Copyright Atheros Communications + * FreeBSD specific prototypes + */ +#ifndef _ADF_NBUF_PVT_H +#define _ADF_NBUF_PVT_H + +#include +//#include +#include +//#include + +#define __ADF_NBUF_NULL NULL +#define __ADF_NBUF_CTX_BUF + +typedef VBUF * __adf_nbuf_t; + +/** + * queue head + */ +typedef struct __adf_nbuf_qhead { + VBUF *head; + VBUF *tail; + a_uint32_t qlen; +}__adf_nbuf_qhead_t; + +typedef __adf_nbuf_qhead_t __adf_nbuf_queue_t; + +__adf_nbuf_t +__adf_nbuf_alloc(adf_os_size_t size, + a_uint32_t reserve, a_uint32_t align); + +void +__adf_nbuf_free(__adf_nbuf_t buf); + +#ifndef _ROM_ +a_uint8_t * +__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t size); + +a_uint8_t * +__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t size); + +a_uint8_t * +__adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t size); +#endif + +void +__adf_nbuf_trim_tail(__adf_nbuf_t buf, adf_os_size_t size); + +__adf_nbuf_t +__adf_nbuf_realloc_headroom(__adf_nbuf_t buf, + a_uint32_t headroom); + +__adf_nbuf_t +__adf_nbuf_realloc_tailroom(__adf_nbuf_t buf, + a_uint32_t tailroom); + +__adf_nbuf_t +__adf_nbuf_expand(__adf_nbuf_t buf, + a_uint32_t headroom, a_uint32_t tailroom); + +__adf_nbuf_t +__adf_nbuf_copy(__adf_nbuf_t src); + +__adf_nbuf_t +__adf_nbuf_unshare(__adf_nbuf_t src); + +void +__adf_nbuf_frag_info(__adf_nbuf_t buf, adf_os_sglist_t *sg); + +#ifndef _ROM_ +a_uint8_t * +__adf_nbuf_get_priv(__adf_nbuf_t buf); +#endif + +void +__adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead, + __adf_nbuf_t buf); + +__adf_nbuf_t +__adf_nbuf_queue_remove(__adf_nbuf_qhead_t *qhead); + +a_uint32_t +__adf_nbuf_tx_cksum_info(__adf_nbuf_t buf, + a_uint8_t **hdr_off, + a_uint8_t **where); + +void +__adf_nbuf_set_rx_cksum(__adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum); +void +__adf_nbuf_get_tso_info(__adf_nbuf_t buf, adf_nbuf_tso_t *tso); + +a_status_t +__adf_nbuf_get_vlan_info(adf_net_handle_t hdl, + __adf_nbuf_t buf, + adf_net_vlanhdr_t *vlan); + +void +__adf_nbuf_dmamap_info(__adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg); + +/** + * @brief return the last mbuf + * + * @param m0 + * + * @return struct mbuf* + */ +#ifndef _ROM_ +VDESC * +__adf_nbuf_last(VBUF *buf); +#endif + +/** + * @brief num bytes in the head + * + * @param adf_nbuf + * + * @return num of bytes available + */ +#ifndef _ROM_ +a_uint32_t +__adf_nbuf_headroom(__adf_nbuf_t buf); +#endif + +/** + * @brief num of bytes available in the tail excluding the priv + * portion + * + * @param adf_nbuf + * + * @return num of bytes + */ +#ifndef _ROM_ +a_uint32_t +__adf_nbuf_tailroom(__adf_nbuf_t buf); +#endif + +/** + * @brief get the entire packet length + * + * @param adf_nbuf + * + * @return total length of packet (sum of all frag lengths) + */ +#ifndef _ROM_ +a_uint32_t +__adf_nbuf_len(__adf_nbuf_t buf); +#endif + +/** + * @brief Clone the nbuf (will not create writeable copies) + * + * @param adf_nbuf + * + * @return Read-only copy of the nbuf (including clusters) + */ +__adf_nbuf_t +__adf_nbuf_clone(__adf_nbuf_t src); + +void +__adf_nbuf_cat(__adf_nbuf_t dst, __adf_nbuf_t src); + + +/* + * @brief check if the mbuf is cloned or not + * + * @param buf + * + * @return a_bool_t + */ +a_bool_t +__adf_nbuf_is_cloned(__adf_nbuf_t buf); + +/** + * @brief This will return the header's addr & m_len + */ +#ifndef _ROM_ +void +__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr, + a_uint32_t *len); +#endif + +/** + * @brief init the queue + * @param qhead + */ +void +__adf_nbuf_queue_init(__adf_nbuf_qhead_t *qhead); + +/** + * @brief return the length of queue + * @param adf_qhead + * + * @return length + * + */ +a_uint32_t +__adf_nbuf_queue_len(__adf_nbuf_qhead_t *qhead); + +/** + * @brief returns the first guy in the Q + * @param qhead + * + * @return (NULL if the Q is empty) + */ +#ifndef _ROM_ +__adf_nbuf_t +__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead); + +/** + * @brief return the next packet from packet chain + * + * @param buf (packet) + * + * @return (NULL if no packets are there) + */ +__adf_nbuf_t +__adf_nbuf_queue_next(__adf_nbuf_t buf); +#endif + +/** + * @brief check if the queue is empty or not + * + * @param qhead + * + * @return a_bool_t + */ +a_bool_t +__adf_nbuf_is_queue_empty(__adf_nbuf_qhead_t *qhead); + +__adf_nbuf_t +__adf_nbuf_create_frm_frag(__adf_nbuf_queue_t *head); +void +__adf_nbuf_split_to_frag(__adf_nbuf_t buf, __adf_nbuf_queue_t *qhead); + +#ifdef _ROM_ + +/** + * @brief This will return the header's addr & m_len + */ +static inline void +__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr, + a_uint32_t *len) +{ + VDESC *desc = buf->desc_list; + + *addr = desc->buf_addr + desc->data_offset; + *len = desc->data_size; +} + +/** + * @brief return the last mbuf + * + * @param m0 + * + * @return struct mbuf* + */ +static inline VDESC * +__adf_nbuf_last(VBUF *buf) +{ + VDESC *desc = buf->desc_list; + + //for(; desc->next_desc != NULL; desc = desc->next_desc) + // ; + while(desc->next_desc != NULL) + { + desc = desc->next_desc; + } + + return desc; +} + +/** + * @brief num bytes in the head + * + * @param adf_nbuf + * + * @return num of bytes available + */ +static inline a_uint32_t +__adf_nbuf_headroom(__adf_nbuf_t buf) +{ + return buf->desc_list->data_offset; +} + +/** + * @brief num of bytes available in the tail excluding the priv + * portion + * + * @param adf_nbuf + * + * @return num of bytes + */ + +static inline a_uint32_t +__adf_nbuf_tailroom(__adf_nbuf_t buf) +{ + VDESC *last_desc = __adf_nbuf_last(buf); + + return last_desc->buf_size - last_desc->data_offset - last_desc->data_size; +} + +/** + * @brief get the entire packet length + * + * @param adf_nbuf + * + * @return total length of packet (sum of all frag lengths) + */ +static inline a_uint32_t +__adf_nbuf_len(__adf_nbuf_t buf) +{ + return buf->buf_length; +} + +/** + * @brief put data in the head + * + * @param buf + * @param len (how much data to put) + * + * @return new data pointer ,NULL if the len is more than the + * space available in the head frag. + */ +static inline a_uint8_t * +__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *ptr = NULL; + VDESC *desc = buf->desc_list; + + desc->data_offset -= len; + desc->data_size += len; + buf->buf_length += len; + ptr = desc->buf_addr + desc->data_offset; + return(ptr); +} + +/** + * + * @brief add data in the end of tail + * + * @param buf + * @param len (how much data to put) + * + * @return previous tail (data+len),NULL if the len is more than + * space available + */ +static inline a_uint8_t * +__adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *tail = NULL; + VDESC *last_desc = __adf_nbuf_last(buf); + + tail = last_desc->buf_addr + last_desc->data_offset + last_desc->data_size; + last_desc->data_size += len; + buf->buf_length += len; + + return tail; +} + +/** + * @brief strip data from head + * + * @param adf_nbuf + * @param len (how much data to rip) + * + * @return new data pointer + */ +static inline a_uint8_t * +__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *ptr = NULL; + VDESC *desc = buf->desc_list; + + desc->data_offset += len; + desc->data_size -= len; + buf->buf_length -= len; + ptr = desc->buf_addr + desc->data_offset; + + return ptr; +} + +/** + * @brief retrieve the priv space pointer from nbuf + * + * @param buf (nbuf to attach the priv space) + * + * @return uint8_t* ( pointer to the data ) + */ +static inline a_uint8_t * +__adf_nbuf_get_priv(__adf_nbuf_t buf) +{ + //adf_os_assert(buf != NULL); + + return buf->ctx; +} + +/** + * @brief returns the first guy in the Q + * @param qhead + * + * @return (NULL if the Q is empty) + */ +static inline __adf_nbuf_t +__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead) +{ + return qhead->head; +} +/** + * @brief return the next packet from packet chain + * + * @param buf (packet) + * + * @return (NULL if no packets are there) + */ +static inline __adf_nbuf_t +__adf_nbuf_queue_next(__adf_nbuf_t buf) +{ + return buf->next_buf; +} + +#endif + +#endif + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/allocram_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/allocram_api.h new file mode 100755 index 0000000..f86d34f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/allocram_api.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2007 Atheros Communications, Inc. All rights reserved. + */ + +#ifndef __ALLOCRAM_API_H__ +#define __ALLOCRAM_API_H__ + +/* API for Target-side startup-time RAM allocations */ + +struct allocram_api { + /* + * Initialize allocram, providing it with a block of RAM + * (an "arena") from which to allocate. + * + * If arena_start is 0, a default start -- the end of + * the application's text & data -- is used. + * + * If arena_sz is 0, a default size -- which uses most + * of physical RAM beyond arena_start -- is used. + * + * Return value is reserved for future use -- it's an arena handle. + */ + void *(* cmnos_allocram_init)(void *arena_start, A_UINT32 arena_sz); + + /* + * Allocate nbytes of memory, returning a pointer to the start + * of the allocated block. Allocation size is rounded up to the + * nearest A_CACHE_LINE_SIZE and the returned address similarly + * aligned. + * + * There is no need to check the return value from this function. + * A failure to satisfy a RAM allocation request is treated as a + * fatal error. + * + * Allocations are expected to occur only during startup; this + * API does not, for instance, guarantee atomicity with respect + * to allocations that might (foolishly) be attempted from + * interrupt handlers. + * + * The "which_arena" parameter is currently unused, and should + * be set to 0 -- only a single arena is currently supported. + */ + void *(* cmnos_allocram)(void *which_arena, A_UINT32 nbytes); + + void (* cmnos_allocram_debug)(void); +}; + +extern void allocram_module_install(struct allocram_api *api); + + +#endif /* __ALLOCRAM_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/athos_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/athos_api.h new file mode 100755 index 0000000..ea658fe --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/athos_api.h @@ -0,0 +1,188 @@ +#ifndef __ATHOS_API_H__ +#define __ATHOS_API_H__ + +/* + * This file contains wrappers to OS operating system functions + * that are available in the Athos version of the operating system. + * + * Target software must always use these wrappers to access OS + * services -- it may not access any OS services directly. + * + * These wrappers are intended to provide OS-independence for applications. + * Using this header file, an application should be able to compile and + * fully link without any other OS header files, source files, or + * binary files. + */ + +#include +#include "dt_defs.h" +#include "cmnos_api.h" +//#include "HIF_api.h" +//#include "vbuf_api.h" +//#include "vdesc_api.h" +//#include "htc_api.h" +#include "Magpie_api.h" + +/* ROM Patch API */ + + +/* HTC API */ + + +/* WMI Adaptive API - required for WMI SVCs as they refer some of them*/ + + +/* WLAN WMI API - required for WMI SVCs and others...*/ + +#if 0 +#define A_INDIR(sym) _A_OS_INDIRECTION_TABLE->sym + +/* HIF support */ +#define HIF_MODULE_INSTALL() hif_module_install(&_A_OS_INDIRECTION_TABLE->hif) +#define HIF_init(pConfig) A_INDIR(hif._init(pConfig)) +#define HIF_start() A_INDIR(hif._start()) +#define HIF_config_pipe(pipe, desc_list) A_INDIR(hif._config_pipe(pipe, desc_list)) +#define HIF_send_buffer(pipe, buf) A_INDIR(hif._send_buffer(pipe, buf)) +#define HIF_return_recv_buf(pipe, buf) A_INDIR(hif._return_recv_buf(pipe, buf)) +#define HIF_isr_handler() A_INDIR(hif._isr_handler()) +#define HIF_is_pipe_supported(pipe) A_INDIR(hif._is_pipe_supported(pipe)) + +/* VBUF APIs */ +#define VBUF_MODULE_INSTALL() vbuf_module_install(&_A_OS_INDIRECTION_TABLE->vbuf) +#define VBUF_init(dataAddr, nBuf) A_INDIR(vbuf._init(dataAddr, nBuf)) +#define VBUF_alloc_vbuf() A_INDIR(vbuf._alloc_vbuf()) +#define VBUF_free_vbuf(buf) A_INDIR(vbuf._free_vbuf(buf)) + +/* VDESC APIs */ +#define VDESC_MODULE_INSTALL() vdesc_module_install(&_A_OS_INDIRECTION_TABLE->vdesc) +#define VDESC_init(dataAddr, nTxDesc, nRxDesc) A_INDIR(vdesc._init(dataAddr, nTxDesc, nRxDesc)) +#define VDESC_alloc_vdesc(type) A_INDIR(vdesc._alloc_vdesc(type)) +#define VDESC_get_hw_desc(type, desc) A_INDIR(vdesc._get_hw_desc(type, desc)) +//#define VDESC_free_vdesc(buf) A_INDIR(vdesc._free_vdesc(buf)) + +#define HTC_MODULE_INSTALL() htc_module_install(&_A_OS_INDIRECTION_TABLE->htc) +//#define HTC_init(dataAddr, SetupComplete, RecvBufferSize) A_INDIR(htc._HTC_Init(dataAddr, SetupComplete, RecvBufferSize)) +#define HTC_init(dataAddr, SetupComplete, pConfig) A_INDIR(htc._HTC_Init(dataAddr, SetupComplete, pConfig)) +#define HTC_RegisterService(s) A_INDIR(htc._HTC_RegisterService(s)) +#define HTC_Ready() A_INDIR(htc._HTC_Ready()) +#define HTC_SendMsg(endpt, buf) A_INDIR(htc._HTC_SendMsg(endpt, buf)) +#define HTC_ReturnBuffers(endpt, buf) A_INDIR(htc._HTC_ReturnBuffers(endpt, buf)) + +#if 0 +/* WMI SVC module */ +#define WMI_SERVICE_MODULE_INSTALL() WMI_service_module_install(&_A_OS_INDIRECTION_TABLE->wmi_svc_api) +#define WMI_Init(dataAddr, pCfg) A_INDIR(wmi_svc_api._WMI_Init(dataAddr, pCfg)) +#define WMI_RegisterDispatchTable(pT) A_INDIR(wmi_svc_api._WMI_RegisterDispatchTable(pT)) +#define WMI_AllocEvent(ec,len) A_INDIR(wmi_svc_api._WMI_AllocEvent(ec, len)) +#define WMI_SendEvent(ev,id,seq,len) A_INDIR(wmi_svc_api._WMI_SendEvent(ev, id, seq, len)) +#define WMI_GetPendingEventsCount() A_INDIR(wmi_svc_api._WMI_GetPendingEventsCount()) +#define WMI_GetControlEp() A_INDIR(wmi_svc_api._WMI_GetControlEp()) +#define WMI_SendCompleteHandler(ep, buf) A_INDIR(wmi_svc_api._WMI_SendCompleteHandler(ep, buf)) +#endif + +/* + * This defines the layout of the indirection table, which + * is used to access exported APIs of various modules. The + * layout is shared across ROM and RAM code. RAM code may + * call into ROM and ROM code may call into RAM. Because + * of the latter, existing offsets must not change for the + * lifetime of a revision of ROM; but new members may be + * added at the end. + */ +typedef struct _A_athos_indirection_table { + _A_cmnos_indirection_table_t cmnos; + + /* TBD: to be added */ + struct hif_api hif; + struct vbuf_api vbuf; + struct vdesc_api vdesc; + struct htc_apis htc; + //WMI_SVC_APIS wmi_svc_api; +} _A_athos_indirection_table_t; + +#if 1 +extern _A_athos_indirection_table_t _indir_tbl; +#define _A_OS_INDIRECTION_TABLE_SIZE sizeof(_A_athos_indirection_table_t) +#define _A_OS_INDIRECTION_TABLE (&_indir_tbl) +#endif +#endif + +extern unsigned int _data_start_in_rom; +extern unsigned int _data_start; +extern unsigned int _data_end; +extern unsigned int _bss_start; +extern unsigned int _bss_end; +extern unsigned int _stack_sentry; +extern unsigned int __stack; +extern unsigned int _fw_image_end; + +#if defined(__XTENSA__) +#define START_DATA _data_start +#define END_DATA _data_end +#define START_BSS _bss_start +#define END_BSS _bss_end + +#define STACK_START _stack_sentry +#define STACK_END __stack +#endif + + +struct _A_os_linkage_check { + int version; + int table; +}; + + +/* + * A_INIT() handles any initialization needed by the OS abstraction, + * and it clears the application's BSS, if necessary. (Application BSS + * is not cleared if the application is linked into a single image that + * includes AthOS.) + * + * A_INIT() must be called first thing in the application (from app_start) + * in order to guarantee that BSS has been cleared properly. + */ +static INLINE int +A_INIT(void) +{ + struct _A_os_linkage_check link_check; + unsigned int *clrptr; + + if (&START_BSS != _A_MAGPIE_INDIRECTION_TABLE->cmnos.start_bss) { + /* Clear BSS */ + for (clrptr = &START_BSS; clrptr < &END_BSS; clrptr++) { + *clrptr = 0; + } + } + + { + /* Copy writable data from flash to RAM. */ + unsigned int *srcptr, *destptr; + + /* + * The _data_start symbol points to the start of data IN FLASH. + * It is defined by flash.ld at application link time. If flash.ld + * is not used, it is defined (on the link line) as 0. + */ + static int *data_start_addr = &_data_start; + + if (data_start_addr != 0) { + for (srcptr = &_data_start, destptr = &START_DATA; + destptr < &END_DATA; + srcptr++, destptr++) + { + *destptr = *srcptr; + } + } + } + +#define OS_LINKAGE_VERSION 4 + link_check.version = OS_LINKAGE_VERSION; + link_check.table = _A_MAGPIE_INDIRECTION_TABLE_SIZE; + + return A_CMN(hal_linkage_check(sizeof(link_check), &link_check)); +} + + +#endif /* __ATHOS_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/buf_pool_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/buf_pool_api.h new file mode 100755 index 0000000..c69e1b7 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/buf_pool_api.h @@ -0,0 +1,50 @@ +/* + * @File: buf_pool_api.h + * + * @Abstract: BUF Pool api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _BUF_POOL_API_H +#define _BUF_POOL_API_H + +#include + +/* endpoint defines */ +typedef enum +{ + POOL_ID_HTC_CONTROL = 0, + POOL_ID_WMI_SVC_CMD_REPLY = 1, + POOL_ID_WMI_SVC_EVENT = 2, + POOL_ID_WLAN_RX_BUF = 3, + POOL_ID_MAX = 10 +} BUF_POOL_ID; + +typedef void* pool_handle_t; + +/* hardware API table structure (API descriptions below) */ +struct buf_pool_api { + pool_handle_t (*_init)(adf_os_handle_t handle); + + void (*_shutdown)(pool_handle_t handle); + + void (*_create_pool)(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize); + + adf_nbuf_t (*_alloc_buf)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve); + + adf_nbuf_t (*_alloc_buf_align)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align); + + void (*_free_buf)(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void buf_pool_module_install(struct buf_pool_api *apis); + +#endif /* #ifndef _BUF_POOL_API_H */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/clock_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/clock_api.h new file mode 100755 index 0000000..e4c9b27 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/clock_api.h @@ -0,0 +1,21 @@ +#ifndef __CLOCK_API_H__ +#define __CLOCK_API_H__ + +#define TICK_MSEC_RATIO 1 +#define TICK_TO_MSEC(tick) ((tick)/TICK_MSEC_RATIO) +#define MSEC_TO_TICK(msec) ((msec)* TICK_MSEC_RATIO) + +struct clock_api { + void (* _clock_init)(A_UINT32 ref_clk); + void (* _clockregs_init)(void); + A_UINT32 (* _uart_frequency)(void); + void (* _delay_us)(int); + void (* _wlan_band_set)(int); + A_UINT32 (* _refclk_speed_get)(void); + A_UINT32 (* _milliseconds)(void); + void (* _sysclk_change)(void); + + void (* _clock_tick)(void); +}; + +#endif /* __CLOCK_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/cmnos_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/cmnos_api.h new file mode 100755 index 0000000..f660f7b --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/cmnos_api.h @@ -0,0 +1,628 @@ +#ifndef __CMNOS_API_H__ +#define __CMNOS_API_H__ + +/* + * This file contains wrappers to OS operating system functions + * that are available in all versions of the operating system. + * + * Target software must always use these wrappers to access OS + * services -- it may not access any OS services directly. + */ + +#include "sys_cfg.h" + +#include "xtensa/config/core.h" +#include "xtensa/hal.h" +#include "xtensa/xtruntime.h" + +/* cmnos interface */ +#include "printf_api.h" +#include "uart_api.h" +#include "dbg_api.h" +#include "mem_api.h" +#include "misc_api.h" +#include "string_api.h" +#include "timer_api.h" +#include "romp_api.h" +#include "allocram_api.h" +#include "tasklet_api.h" +#include "clock_api.h" +#include "intr_api.h" +#include "wdt_api.h" +#include "eeprom_api.h" +#include "usb_api.h" +#include +#include + +#if defined(PROJECT_K2) +#if SYSTEM_MODULE_SFLASH +#include "cmnos/sflash_api.h" +#endif +#endif + +#define AR6K_ROM_START 0x004e0000 +#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) +#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) + +#define IML_SIGNAL_UNUSED0_ADDR TARG_ROM_ADDRS(0) /* Cannot be used -- aligned */ +#define IML_SIGNAL_ASSERT_ADDR TARG_ROM_ADDRS(1) /* Signal an assertion failure */ +#define IML_SIGNAL_PRINTF_ADDR TARG_ROM_ADDRS(2) /* Signal a printf request */ +#define IML_SIGNAL_UNUSED4_ADDR TARG_ROM_ADDRS(4) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSED8_ADDR TARG_ROM_ADDRS(8) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSEDC_ADDR TARG_ROM_ADDRS(0xc) /* Cannot be used -- aligned */ +#define IML_SIGNAL_MASK 0xfffe000f +#define IML_LINENUM_SHIFT 4 + +#define NOW() xthal_get_ccount() + +#if defined(__XTENSA__) +#define _A_BARRIER asm volatile("memw") +#else +#define _A_BARRIER +#endif + +#define A_ASSERT( __bool ) \ + do { \ + if (0 == (__bool)) { \ + (void)*((volatile int *)(IML_SIGNAL_ASSERT_ADDR+(__LINE__<<4)));\ + _A_BARRIER; \ + } \ + } while (0) + + +#define A_IML_IS_ASSERT(vaddr) \ + (((vaddr) & IML_SIGNAL_MASK) == (IML_SIGNAL_ASSERT_ADDR & IML_SIGNAL_MASK)) + + +#define PRINT_FAILURE_STATE() \ +do { \ + uint32_t epc1, epc2, epc3, epc4; \ + \ + asm volatile("rsr %0,%1" : "=r" (epc1) : "n" (EPC_1)); \ + asm volatile("rsr %0,%1" : "=r" (epc2) : "n" (EPC_2)); \ + asm volatile("rsr %0,%1" : "=r" (epc3) : "n" (EPC_3)); \ + asm volatile("rsr %0,%1" : "=r" (epc4) : "n" (EPC_4)); \ + \ + A_PRINTF("\tepc1=0x%x, epc2=0x%x, epc3=0x%x, epc4=0x%x\n", \ + epc1, epc2, epc3, epc4); \ + A_PRINTF("0x%08x, 0x%08x, 0x%08x, \n\r", \ + DEBUG_SYSTEM_STATE, WATCH_DOG_RESET_COUNTER, \ + WATCH_DOG_MAGIC_PATTERN); \ +} while(0) +//////////////////////////////////////////////////////////////////////////////////// + + +//#define A_CMN(sym) _A_OS_INDIRECTION_TABLE->cmnos.sym +#define A_CMN(sym) _A_MAGPIE_INDIRECTION_TABLE->cmnos.sym + +#if SYSTEM_MODULE_MEM +/* Mem interfaces */ +#define A_MEMSET(addr, value, size) \ + A_CMN(mem._memset((char *)(addr), (int)(value), (int)(size))) + +#define A_MEMZERO(addr, size) \ + A_CMN(mem._memset((char *)(addr), (int)0, (int)(size))) + +#define A_MEMCPY(dst, src, size) \ + A_CMN(mem._memcpy((char *)(dst), (char *)(src), (int)(size))) + +#define A_MEMMOVE(dst, src, size) \ + A_CMN(mem._memmove((char *)(dst), (char *)(src), (int)(size))) + +#define A_MEMCMP(p1, p2, nbytes) \ + A_CMN(mem._memcmp)((void *)(p1), (void *)(p2), (int)(nbytes)) +#else +/* Mem interfaces */ +#define A_MEMSET(addr, value, size) + +#define A_MEMZERO(addr, size) + +#define A_MEMCPY(dst, src, size) + +#define A_MEMMOVE(dst, src, size) + +#define A_MEMCMP(p1, p2, nbytes) +#endif + + +#if 1 + /* String interfaces */ + #define A_STRCPY(dst, src) A_CMN(string._strcpy((dst), (src))) + #define A_STRNCPY(dst, src, n) A_CMN(string._strncpy((dst), (src), (n))) + #define A_STRLEN(str) A_CMN(string._strlen(str)) + #define A_STRCMP(str1, str2) A_CMN(string._strcmp((str1), (str2))) + #define A_STRNCMP(str1, str2, n) A_CMN(string._strncmp((str1), (str2), (n))) +#endif + +#if SYSTEM_MODULE_PRINT +/* Printf support */ +#define A_PRINTF_INIT() A_CMN(printf._printf_init()) +#define A_PRINTF A_CMN(printf._printf) +#else +#define A_PRINTF_INIT() +#define A_PRINTF +#endif /* SYSTEM_MODULE_PRINT */ + +#if SYSTEM_MODULE_UART +/* Serial port support */ +#define A_UART_INIT() A_CMN(uart._uart_init()) + +#define A_UART_HWINIT(freq, baud) \ + A_CMN(uart._uart_hwinit((freq), (baud))) + +#define A_UART_ENABLED() (HOST_INTEREST->hi_uart_enable) + +#define A_PUTS(str) A_CMN(uart._uart_str_out(str)) + +#define A_PUTC(ch) A_CMN(uart._uart_char_put(ch)) +#define A_GETC(pCh) A_CMN(uart._uart_char_get(pCh)) + +#define A_UART_TASK() A_CMN(uart._uart_task()) +#define A_UART_CONFIG(x) A_CMN(uart._uart_config(x)) + +#else + +#define A_UART_INIT() + +#define A_UART_HWINIT(freq, baud) + +#define A_UART_ENABLED() + +#define A_PUTS(str) + +#define A_PUTC(ch) +#define A_GETC(pCh) + +#define A_UART_TASK() +#define A_UART_CONFIG(x) + +#endif + +#if SYSTEM_MODULE_MISC +/* Reset Support */ +#define A_RESET() A_CMN(misc._system_reset()) +#define A_RESET_MAC() A_CMN(misc._mac_reset()) + +/* Assertion failure */ +#define A_ASSFAIL(regdump) A_CMN(misc._assfail((regdump))) + +/* Report a failure to the Host */ +#define A_REPORT_FAILURE(data, len) \ + A_CMN(misc._report_failure_to_host((data), (len))) + +/* UNALIGNED references are used for ASSERTs */ +#define A_MISALIGNED_LOAD_HANDLER(dump) A_CMN(misc._misaligned_load_handler(dump)) + +/* reture the host interface type */ +#define A_IS_HOST_PRESENT() A_CMN(misc._is_host_present()) +#define A_KBHIT(delay) A_CMN(misc._kbhit(delay)) +#define A_GET_ROM_VER() A_CMN(misc._rom_version_get()) +#else +/* Reset Support */ +#define A_RESET() +#define A_RESET_MAC() + +/* Assertion failure */ +#define A_ASSFAIL(regdump) + +#define A_MISALIGNED_LOAD_HANDLER(dump) + +/* Report a failure to the Host */ +#define A_REPORT_FAILURE(data, len) + +#define A_IS_HOST_PRESENT() +#define A_KBHIT(delay) +#define A_GET_ROM_VER() +#endif + +//#if SYSTEM_MODULE_DBG +/* debug Support */ +//#define A_DBG_INIT() A_CMN(dbg._dbg_init()) +//#define A_DBG_TASK() A_CMN(dbg._dbg_task()) +//#else +//#define A_DBG_INIT() +//#define A_DBG_TASK() +//#endif + +#if SYSTEM_MODULE_USB +/* debug Support */ +#define A_USB_INIT() A_CMN(usb._usb_init()) +#define A_USB_ROM_TASK() A_CMN(usb._usb_rom_task()) +#define A_USB_FW_TASK() A_CMN(usb._usb_fw_task()) +#define A_USB_INIT_PHY() A_CMN(usb._usb_init_phy()) + +#define A_USB_EP0_SETUP() A_CMN(usb._usb_ep0_setup()) +#define A_USB_EP0_TX_DATA() A_CMN(usb._usb_ep0_tx_data()) +#define A_USB_EP0_RX_DATA() A_CMN(usb._usb_ep0_rx_data()) + +#define A_USB_GET_CONFIG() A_CMN(usb._usb_get_configuration()) +#define A_USB_SET_CONFIG() A_CMN(usb._usb_set_configuration()) + +#define A_USB_GET_INTERFACE() A_CMN(usb._usb_get_interface()) +#define A_USB_SET_INTERFACE() A_CMN(usb._usb_set_interface()) + +#define A_USB_STANDARD_CMD() A_CMN(usb._usb_standard_cmd()) +#define A_USB_VENDOR_CMD() A_CMN(usb._usb_vendor_cmd()) + +#define A_USB_POWER_OFF() A_CMN(usb._usb_power_off()) +#define A_USB_RESET_FIFO() A_CMN(usb._usb_reset_fifo()) +#define A_USB_GEN_WDT() A_CMN(usb._usb_gen_wdt()) +#define A_USB_JUMP_BOOT() A_CMN(usb._usb_jump_boot()) + +#define A_USB_GET_DESCRIPTOR() A_CMN(usb._usb_get_descriptor()) +#define A_USB_SET_ADDRESS() A_CMN(usb._usb_set_address()) +#define A_USB_SET_FEATURE() A_CMN(usb._usb_set_feature()) +#define A_USB_CLEAR_FEATURE() A_CMN(usb._usb_clr_feature()) + +#define A_USB_GET_STATUS() A_CMN(usb._usb_get_status()) +#define A_USB_SETUP_DESC() A_CMN(usb._usb_setup_desc()) +#define A_USB_STATUS_IN() A_CMN(usb._usb_status_in()) +#define A_USB_REG_OUT() A_CMN(usb._usb_reg_out()) + +#define A_USB_EP0_TX() A_CMN(usb._usb_ep0_tx()) +#define A_USB_EP0_RX() A_CMN(usb._usb_ep0_rx()) +#define A_USB_CLK_INIT() A_CMN(usb._usb_clk_init()) + +#else +#define A_USB_INIT() +#define A_USB_TASK() +#define A_USB_INIT_PHY() + +#define A_USB_EP0_SETUP() +#define A_USB_EP0_TX() +#define A_USB_EP0_RX() + +#define A_USB_GET_CONFIG() +#define A_USB_SET_CONFIG() + +#define A_USB_GET_INTERFACE() +#define A_USB_SET_INTERFACE() + +#define A_USB_STANDARD_CMD() +#define A_USB_VENDOR_CMD() + +#define A_USB_POWER_OFF() +#define A_USB_RESET_FIFO() +#define A_USB_GEN_WDT() +#define A_USB_JUMP_BOOT() + +#define A_USB_GET_DESCRIPTOR() +#define A_USB_SET_ADDRESS() +#define A_USB_SET_FEATURE() +#define A_USB_CLEAR_FEATURE() + +#define A_USB_GET_STATUS() +#define A_USB_SETUP_DESC() + + +#define A_USB_STATUS_IN() +#define A_USB_REG_OUT() + +#define A_USB_EP0_TX() +#define A_USB_EP0_RX() + +#define A_USB_CLK_INIT() +#endif + +#if SYSTEM_MODULE_INTR +/* Low-level interrupt support intended for use by OS modules */ +#define A_INTR_GET_INTRENABLE() A_CMN(intr._get_intrenable()) +#define A_INTR_SET_INTRENABLE(val) A_CMN(intr._set_intrenable(val)) +#define A_INTR_GET_INTRPENDING() A_CMN(intr._get_intrpending()) +#define A_INTR_UNBLOCK_ALL_INTRLVL() A_CMN(intr._unblock_all_intrlvl()) + +/* Interrupt support */ +#define A_INTR_INIT() A_CMN(intr._intr_init()) + +#define A_INTR_DISABLE(pOld) \ + do { \ + *(pOld) = A_CMN(intr._intr_disable()); \ + } while (0) + +#define A_INTR_RESTORE(old) A_CMN(intr._intr_restore((old))) + +#define A_INVOKE_ISR(inum) A_CMN(intr._intr_invoke_isr(inum)) + +#define A_INTR_MASK(inum) A_CMN(intr._intr_mask_inum(inum)) +#define A_INTR_UNMASK(inum) A_CMN(intr._intr_unmask_inum(inum)) + +#define A_ATTACH_ISR(inum, isr, arg) A_CMN(intr._intr_attach_isr(inum, isr, arg)) +#else +#define A_INTR_INIT() +#define A_INTR_DISABLE(pOld) +#define A_INTR_RESTORE(old) + +#define A_INTR_GET_INTRENABLE() +#define A_INTR_SET_INTRENABLE(val) +#define A_INTR_GET_INTRPENDING() +#define A_INTR_UNBLOCK_ALL_INTRLVL() +#define A_INVOKE_ISR(inum) +#define A_INTR_MASK(inum) +#define A_INTR_UNMASK(inum) +#define A_ATTACH_ISR(inum, isr, arg) + +#endif + +/* Tasklet Support */ +#define A_TASKLET_INIT() A_CMN(tasklet._tasklet_init()) +#define A_TASKLET_INIT_TASK(f, arg, t) A_CMN(tasklet._tasklet_init_task(f, arg, t)) +#define A_TASKLET_DISABLE(t) A_CMN(tasklet._tasklet_disable(t)) +#define A_TASKLET_SCHEDULE(t) A_CMN(tasklet._tasklet_schedule(t)) +#define A_TASKLET_RUN() A_CMN(tasklet._tasklet_run()) + + +/* RAM Allocation Support */ +#if defined(__mips__) +#define alloc_arena_start _end +#endif +#if defined(__XTENSA__) +#define alloc_arena_start _end +#endif + +#if SYSTEM_MODULE_CLOCK + +#define A_CLOCK_INIT(refclk_guess) A_CMN(clock._clock_init(refclk_guess)) +#define A_CLOCK_TICK() A_CMN(clock._clock_tick()) +#define A_CLOCK_GET_TICK() A_CMN(clock._clock_get_tick()) + +/* + * Get the number of millisecond ticks since the system was started. + * Note that this only approximates 1Ms. It's actually 32 ticks of + * a 32KHz clock. + * + * Returns a A_UINT32 value. + */ +#define A_MILLISECONDS() A_CMN(clock._milliseconds()) + +/* + * Get the frequency of the reference clock, expressed as + * an A_refclk_speed_t. + */ +#define A_REFCLK_SPEED_GET() A_CMN(clock._refclk_speed_get()) + +/* Spin delay */ +#define A_DELAY_USECS(us) A_CMN(clock._delay_us(us)) + +#define A_UART_FREQUENCY() A_CMN(clock._uart_frequency()) + +#define A_CLOCKREGS_INIT() A_CMN(clock._clockregs_init()) + +/* which_band is either A_BAND_24GHZ or A_BAND_5GHZ */ +#define A_WLAN_BAND_SET(which_band) \ + A_CMN(clock._wlan_band_set(which_band)) + +/* Called whenever the system clock changes speed */ +#define A_SYSCLK_CHANGE() A_CMN(clock._sysclk_change()) + +#else + +#define A_CLOCK_INIT(refclk_guess) +#define A_CLOCK_TICK() +#define A_CLOCK_GET_TICK() +#define A_MILLISECONDS() +#define A_REFCLK_SPEED_GET() +#define A_DELAY_USECS(us) +#define A_UART_FREQUENCY() +#define A_CLOCKREGS_INIT() +#define A_WLAN_BAND_SET(which_band) +#define A_SYSCLK_CHANGE() + +#endif + +// Timer +#define A_INIT_TIMER(pTimer, pFunction, pArg) \ + A_CMN(timer._timer_setfn((pTimer), (pFunction), (pArg))) + +/* Set a (possibly periodic) timer for "period" Milliseconds. */ +#define A_TIMEOUT_MS(pTimer, period) \ + A_CMN(timer._timer_arm((pTimer), (period))) + +#define A_UNTIMEOUT(pTimer) \ + A_CMN(timer._timer_disarm(pTimer)) + +#define A_TIMER_RUN() \ + A_CMN(timer._timer_run()) + +#define A_GMAC_BOOT_INIT() \ + A_CMN(gmac.gmac_boot_init()) + +#if SYSTEM_MODULE_ALLOCRAM +/* Default size of ALLOCRAM area */ +#define ARENA_SZ_DEFAULT 12000 + +#define A_ALLOCRAM_INIT(arena_start, arena_size) \ +do { \ + extern unsigned int alloc_arena_start; \ + void *astart; \ + int asize; \ + astart = (arena_start) ? (void *)(arena_start) : &alloc_arena_start; \ + asize = (arena_size) ? (arena_size) : (ARENA_SZ_DEFAULT); \ + A_CMN(allocram.cmnos_allocram_init((astart), (asize))); \ +} while (0) + +#define A_ALLOCRAM(nbytes) A_CMN(allocram.cmnos_allocram(0, (nbytes))) + +#define A_ALLOCRAM_DEBUG() A_CMN(allocram.cmnos_allocram_debug()) + +#else +#define A_ALLOCRAM_INIT(arena_start, arena_size) +#define A_ALLOCRAM(nbytes) +#define A_ALLOCRAM_DEBUG() +#endif + +#if SYSTEM_MODULE_ROM_PATCH + +#define A_ROMP_INIT() A_CMN(romp._romp_init()) +#define A_ROMP_DOWNLOAD(x) A_CMN(romp._romp_download(x)) +#define A_ROMP_DECODE(addr) A_CMN(romp._romp_decode(addr)) +#define A_ROMP_INSTALL() A_CMN(romp._romp_install()) +#else +#define A_ROMP_INIT() +#define A_ROMP_DOWNLOAD(x) +#define A_ROMP_DECODE(addr) +#define A_ROMP_INSTALL() +#endif + +#if SYSTEM_MODULE_WDT + +#define A_WDT_INIT() A_CMN(wdt_timer._wdt_init()) +#define A_WDT_ENABLE() A_CMN(wdt_timer._wdt_enable()) +#define A_WDT_DISABLE() A_CMN(wdt_timer._wdt_disable()) +#define A_WDT_SET(t) A_CMN(wdt_timer._wdt_set(t)) +#define A_WDT_TASK() A_CMN(wdt_timer._wdt_task()) +#define A_WDT_LASTBOOT() A_CMN(wdt_timer._wdt_last_boot()) +#define A_WDT_RESET() A_CMN(wdt_timer._wdt_reset()) + +#else +#define A_WDT_INIT() +#define A_WDT_ENABLE() +#define A_WDT_DISABLE() +#define A_WDT_SET(t) +#define A_WDT_TASK() +#define A_WDT_LASTBOOT() +#define A_WDT_RESET() +#endif + + +#if SYSTEM_MODULE_EEPROM +#define A_EEP_INIT() A_CMN(eep._eep_init()) +#define A_EEP_READ(off, len, buf) A_CMN(eep._eep_read(off, len, buf)) +#define A_EEP_WRITE(off, len, buf) A_CMN(eep._eep_write(off, len, buf)) +#define A_EEP_IS_EXIST() A_CMN(eep._eep_is_exist()) +#else +#define A_EEP_INIT() +#define A_EEP_READ(off, len, buf) +#define A_EEP_WRITE(off, len, buf) +#define A_EEP_IS_EXIST() +#endif + + + +struct _A_os_linkage_check; /* OS-dependent */ + +typedef struct _A_cmnos_indirection_table { + int (* hal_linkage_check)(int sz, struct _A_os_linkage_check *); + unsigned int *start_bss; + void (* app_start)(void); + +#if SYSTEM_MODULE_MEM + struct mem_api mem; +#endif + +#if SYSTEM_MODULE_MISC + struct misc_api misc; +#endif + +#if SYSTEM_MODULE_PRINT + struct printf_api printf; +#endif + +#if SYSTEM_MODULE_UART + struct uart_api uart; +#endif + +//#if SYSTEM_MODULE_DBG +// struct dbg_api dbg; +//#endif + + +#if SYSTEM_MODULE_GMAC + struct gmac_api gmac; +#endif + +#if SYSTEM_MODULE_USB + struct usb_api usb; +#endif + +#if SYSTEM_MODULE_CLOCK + struct clock_api clock; +#endif + +#if SYSTEM_MODULE_TIMER + struct timer_api timer; +#endif + +#if SYSTEM_MODULE_INTR + struct intr_api intr; +#endif + +#if SYSTEM_MODULE_ALLOCRAM + struct allocram_api allocram; +#endif + +#if SYSTEM_MODULE_ROM_PATCH + struct romp_api romp; +#endif + +#if SYSTEM_MODULE_WDT + struct wdt_api wdt_timer; +#endif + +#if SYSTEM_MODULE_EEPROM + struct eep_api eep; +#endif + + struct string_api string; + struct tasklet_api tasklet; + +} _A_cmnos_indirection_table_t; + +/* Module installation for cmnos modules */ + +#if SYSTEM_MODULE_MEM +extern void cmnos_mem_module_install(struct mem_api *); +#endif + +#if SYSTEM_MODULE_MISC +extern void cmnos_misc_module_install(struct misc_api *); +#endif + +#if SYSTEM_MODULE_PRINT +extern void cmnos_printf_module_install(struct printf_api *); +#endif + +#if SYSTEM_MODULE_UART +extern void cmnos_uart_module_install(struct uart_api *); +#endif + +//#if SYSTEM_MODULE_DBG +//extern void cmnos_dbg_module_install(struct dbg_api *); +//#endif + +#if SYSTEM_MODULE_USB +extern void cmnos_usb_module_install(struct usb_api *); +#endif + +#if SYSTEM_MODULE_INTR +extern void cmnos_intr_module_install(struct intr_api *); +#endif + +#if SYSTEM_MODULE_CLOCK +extern void cmnos_clock_module_install(struct clock_api *); +#endif + +#if SYSTEM_MODULE_TIMER +extern void cmnos_timer_module_install(struct timer_api *); +#endif + +#if SYSTEM_MODULE_ALLOCRAM +extern void cmnos_allocram_module_install(struct allocram_api *); +#endif + +#if SYSTEM_MODULE_ROM_PATCH +extern void cmnos_romp_module_install(struct romp_api *); +#endif + +#if SYSTEM_MODULE_WDT +extern void cmnos_wdt_module_install(struct wdt_api *); +#endif + +#if SYSTEM_MODULE_EEPROM +extern void cmnos_eep_module_install(struct eep_api *); +#endif + +extern void cmnos_tasklet_module_install(struct tasklet_api *); + +extern void cmnos_string_module_install(struct string_api *tbl); + +#endif /* __CMNOS_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/dma_engine_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/dma_engine_api.h new file mode 100755 index 0000000..6996cb8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/dma_engine_api.h @@ -0,0 +1,92 @@ +/* + * @File: dma_engine_api.h + * + * @Abstract: DMA Engine api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _DMA_ENGINE_API_H +#define _DMA_ENGINE_API_H + +#include +#include + +struct zsDmaDesc +{ +#if 1 // BIG_ENDIAN + volatile u16_t ctrl; // Descriptor control + volatile u16_t status; // Descriptor status + volatile u16_t totalLen; // Total length + volatile u16_t dataSize; // Data size +#else + volatile u16_t status; // Descriptor status + volatile u16_t ctrl; // Descriptor control + volatile u16_t dataSize; // Data size + volatile u16_t totalLen; // Total length +#endif + struct zsDmaDesc* lastAddr; // Last address of this chain + volatile u32_t dataAddr; // Data buffer address + struct zsDmaDesc* nextAddr; // Next TD address +}; + +struct zsDmaQueue +{ + struct zsDmaDesc* head; + struct zsDmaDesc* terminator; +}; + +// Subclass of zsDmaQueue for TX +struct zsTxDmaQueue +{ + struct zsDmaDesc* head; + struct zsDmaDesc* terminator; + + /* Below are fields specific to TX */ + VBUF *xmited_buf_head; + VBUF *xmited_buf_tail; +}; + +/* hardware API table structure (API descriptions below) */ +struct dma_engine_api +{ + void (*_init)(); + + void (*_init_rx_queue)(struct zsDmaQueue *q); + + void (*_init_tx_queue)(struct zsTxDmaQueue *q); + + void (*_config_rx_queue)(struct zsDmaQueue *q, int num_desc, int buf_size); + + void (*_xmit_buf)(struct zsTxDmaQueue *q, VBUF *buf); + + void (*_flush_xmit)(struct zsDmaQueue *q); + + VBUF* (*_reap_recv_buf)(struct zsDmaQueue *q); + + void (*_return_recv_buf)(struct zsDmaQueue *q, VBUF *buf); + + VBUF* (*_reap_xmited_buf)(struct zsTxDmaQueue *q); + + void (*_swap_data)(struct zsDmaDesc* desc); + + int (*_has_compl_packets)(struct zsDmaQueue *q); + + void (*_desc_dump)(struct zsDmaQueue *q); + + /* The functions below are for patchable */ + struct zsDmaDesc* (*_get_packet)(struct zsDmaQueue* q); + void (*_reclaim_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc); + void (*_put_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void dma_engine_module_install(struct dma_engine_api *apis); + +#endif /* #ifndef _DMA_ENGINE_API_H */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/dma_lib.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/dma_lib.h new file mode 100755 index 0000000..7b44c56 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/dma_lib.h @@ -0,0 +1,57 @@ +#ifndef __DMA_LIB_H +#define __DMA_LIB_H + + +/***********************External***************************/ + +/** + * @brief DMA engine numbers, HIF need to map them to there + * respective order + */ +typedef enum dma_engine{ + DMA_ENGINE_RX0, + DMA_ENGINE_RX1, + DMA_ENGINE_RX2, + DMA_ENGINE_RX3, + DMA_ENGINE_TX0, + DMA_ENGINE_TX1, + DMA_ENGINE_MAX +}dma_engine_t; + +/** + * @brief Interface type, each HIF should call with its own interface type + */ +typedef enum dma_iftype{ + DMA_IF_GMAC = 0x0,/* GMAC */ + DMA_IF_PCI = 0x1,/*PCI */ + DMA_IF_PCIE = 0x2 /*PCI Express */ +}dma_iftype_t; + + +struct dma_lib_api{ + A_UINT16 (*tx_init)(dma_engine_t eng_no, dma_iftype_t if_type); + void (*tx_start)(dma_engine_t eng_no); + A_UINT16 (*rx_init)(dma_engine_t eng_no, dma_iftype_t if_type); + void (*rx_config)(dma_engine_t eng_no, a_uint16_t num_desc, + a_uint16_t gran); + void (*rx_start)(dma_engine_t eng_no); + A_UINT32 (*intr_status)(dma_iftype_t if_type); + A_UINT16 (*hard_xmit)(dma_engine_t eng_no, VBUF *buf); + void (*flush_xmit)(dma_engine_t eng_no); + A_UINT16 (*xmit_done)(dma_engine_t eng_no); + VBUF * (*reap_xmitted)(dma_engine_t eng_no); + VBUF * (*reap_recv)(dma_engine_t eng_no); + void (*return_recv)(dma_engine_t eng_no, VBUF *buf); + A_UINT16 (*recv_pkt)(dma_engine_t eng_no); +}; + + +/** + * @brief Install the DMA lib api's this for ROM patching + * support + * + * @param apis + */ +void dma_lib_module_install(struct dma_lib_api *apis); + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/eeprom_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/eeprom_api.h new file mode 100755 index 0000000..deab32a --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/eeprom_api.h @@ -0,0 +1,32 @@ +#ifndef __EEPROM_API_H__ +#define __EEPROM_API_H__ +/* + * + */ + + +typedef enum { + RET_SUCCESS = 0, + RET_NOT_INIT, + RET_NOT_EXIST, + RET_EEP_CORRUPT, + RET_EEP_OVERFLOW, + + // add return code from here + RET_UNKNOWN +}T_EEP_RET; + + +/*!- interface of eeprom access + * + */ +struct eep_api { + void (* _eep_init)(void); + T_EEP_RET (* _eep_read)(uint16_t, uint16_t, uint16_t *); + T_EEP_RET (* _eep_write)(uint16_t, uint16_t, uint16_t *); + T_EEP_RET (*_eep_is_exist)(void); + +}; + +#endif /* __EEPROM_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_api.h new file mode 100755 index 0000000..33dde31 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_api.h @@ -0,0 +1,70 @@ +/* + * @File: HIF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _HIF_API_H +#define _HIF_API_H + +#include + +/* mailbox hw module configuration structure */ +typedef struct _HIF_CONFIG { + int dummy; +} HIF_CONFIG; + +typedef struct _HIF_CALLBACK { + /* callback when a buffer has be sent to the host*/ + void (*send_buf_done)(adf_nbuf_t buf, void *context); + /* callback when a receive message is received */ + void (*recv_buf)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); + /* context used for all callbacks */ + void *context; +} HIF_CALLBACK; + +typedef void* hif_handle_t; + +/* hardware API table structure (API descriptions below) */ +struct hif_api { + hif_handle_t (*_init)(HIF_CONFIG *pConfig); + + void (* _shutdown)(hif_handle_t); + + void (*_register_callback)(hif_handle_t, HIF_CALLBACK *); + + int (*_get_total_credit_count)(hif_handle_t); + + void (*_start)(hif_handle_t); + + void (*_config_pipe)(hif_handle_t handle, int pipe, int creditCount); + + int (*_send_buffer)(hif_handle_t handle, int pipe, adf_nbuf_t buf); + + void (*_return_recv_buf)(hif_handle_t handle, int pipe, adf_nbuf_t buf); + //void (*_set_recv_bufsz)(int pipe, int bufsz); + //void (*_pause_recv)(int pipe); + //void (*_resume_recv)(int pipe); + int (*_is_pipe_supported)(hif_handle_t handle, int pipe); + + int (*_get_max_msg_len)(hif_handle_t handle, int pipe); + + int (*_get_reserved_headroom)(hif_handle_t handle); + + void (*_isr_handler)(hif_handle_t handle); + + void (*_get_default_pipe)(hif_handle_t handle, A_UINT8 *pipe_uplink, A_UINT8 *pipe_downlink); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void generic_hif_module_install(struct hif_api *apis); + +#endif /* #ifndef _HIF_API_H */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_gmac.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_gmac.h new file mode 100755 index 0000000..58dee8d --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_gmac.h @@ -0,0 +1,257 @@ + +#ifndef __HIF_GMAC_H +#define __HIF_GMAC_H + +#include +#include + + +#define ETH_ALEN 6 +#define GMAC_MAX_PKT_LEN 1600 +#define GMAC_MAX_DESC 5 + +#define GMAC_DISCV_PKT_SZ 1024 +#define GMAC_DISCV_WAIT 2000 + +#define ATH_P_MAGBOOT 0x12 /*Magpie GMAC 18 for boot downloader*/ +#define ATH_P_MAGNORM 0x13 /*Magpie GMAC 19 for HTC & others*/ + +#define ETH_P_ATH 0x88bd + +typedef enum hif_gmac_pipe{ + HIF_GMAC_PIPE_RX = 1, /*Normal Priority RX*/ + HIF_GMAC_PIPE_TX = 2, /*Normal Priority TX*/ +}hif_gmac_pipe_t; + +struct gmac_api{ + void (*gmac_boot_init)(void); +}; + +void cmnos_gmac_module_install(struct gmac_api *boot_apis); +void hif_gmac_module_install(struct hif_api *apis); + +enum __gmac_mii_mode { + GMAC_MIIMODE_NONE=0, + GMAC_MIIMODE_MII=1, + GMAC_MIIMODE_RMII=2, + GMAC_MIIMODE_GMII=3, + GMAC_MIIMODE_RGMII=4, + GMAC_MIIMODE_MAX=5 +}; +enum __gmac_msg_type{ + GMAC_HST_QUERY = 0x0001, + GMAC_HST_REPLY = 0x0002, + GMAC_TGT_QUERY = 0x0003, + GMAC_TGT_REPLY = 0x0004 +}; + +enum __magpie_regs{ + MAG_REG_GPIO_OE = 0x00052000,/*GPIO Output Enable*/ + MAG_REG_RST = 0x00050010,/*Magpie reset reg*/ + MAG_REG_RST_AHB = 0x00050018,/*Magpie AHB_ARB reset reg*/ + MAG_REG_MII0_CTRL = 0x00054100,/*Magpie MII0 Control reg*/ + MAG_REG_STAT_CTRL = 0x00054104,/*Magpie Status reg*/ + + MAG_REG_ETH_PLL = 0x5600c, + MAG_REG_ETHPLL_BYPASS = 0x56010, +}; + +enum __gmac_regs{ + GMAC_REG_BASE = 0x00060000, + GMAC_REG_MAC_CFG1 = 0x00 + GMAC_REG_BASE,/*MAC config 1*/ + GMAC_REG_MAC_CFG2 = 0x04 + GMAC_REG_BASE,/*MAC config 2*/ + GMAC_REG_IPG_IFG = 0x08 + GMAC_REG_BASE,/*Inter-packet-gap*/ + GMAC_REG_HALF_DPLX = 0x0c + GMAC_REG_BASE,/*Half duplex*/ + GMAC_REG_MAX_FRAME = 0x10 + GMAC_REG_BASE,/*Max frame length*/ + GMAC_REG_MII_CFG = 0x20 + GMAC_REG_BASE,/*MII mgmt config*/ + GMAC_REG_MII_CMD = 0x24 + GMAC_REG_BASE,/*MII mgmt command*/ + GMAC_REG_MII_ADDR = 0x28 + GMAC_REG_BASE,/*MII mgmt address*/ + GMAC_REG_MII_CTRL = 0x2c + GMAC_REG_BASE,/*MII mgmt control*/ + GMAC_REG_MII_STAT = 0x30 + GMAC_REG_BASE,/*MII mgmt status*/ + GMAC_REG_MII_PSTAT = 0x34 + GMAC_REG_BASE,/*MII mgmt Phy status/ind*/ + GMAC_REG_IF_CTRL = 0x38 + GMAC_REG_BASE,/*Interface control*/ + GMAC_REG_IF_STAT = 0x3c + GMAC_REG_BASE,/*Interface status*/ + GMAC_REG_MAC_ADDR1 = 0x40 + GMAC_REG_BASE,/*MAC address 1*/ + GMAC_REG_MAC_ADDR2 = 0x44 + GMAC_REG_BASE,/*MAC address 2*/ + GMAC_REG_FIFO_CFG0 = 0x48 + GMAC_REG_BASE,/*FIFO config reg0*/ + GMAC_REG_FIFO_CFG1 = 0x4c + GMAC_REG_BASE,/*FIFO config reg1*/ + GMAC_REG_FIFO_CFG2 = 0x50 + GMAC_REG_BASE,/*FIFO config reg2*/ + GMAC_REG_FIFO_CFG3 = 0x54 + GMAC_REG_BASE,/*FIFO config reg3*/ + GMAC_REG_FIFO_CFG4 = 0x58 + GMAC_REG_BASE,/*FIFO config reg4*/ + GMAC_REG_FIFO_CFG5 = 0x5c + GMAC_REG_BASE,/*FIFO config reg5*/ + GMAC_REG_FIFO_RAM0 = 0x60 + GMAC_REG_BASE,/*FIFO RAM access reg0*/ + GMAC_REG_FIFO_RAM1 = 0x64 + GMAC_REG_BASE,/*FIFO RAM access reg1*/ + GMAC_REG_FIFO_RAM2 = 0x68 + GMAC_REG_BASE,/*FIFO RAM access reg2*/ + GMAC_REG_FIFO_RAM3 = 0x6c + GMAC_REG_BASE,/*FIFO RAM access reg3*/ + GMAC_REG_FIFO_RAM4 = 0x70 + GMAC_REG_BASE,/*FIFO RAM access reg4*/ + GMAC_REG_FIFO_RAM5 = 0x74 + GMAC_REG_BASE,/*FIFO RAM access reg5*/ + GMAC_REG_FIFO_RAM6 = 0x78 + GMAC_REG_BASE,/*FIFO RAM access reg6*/ + GMAC_REG_FIFO_RAM7 = 0x7c + GMAC_REG_BASE,/*FIFO RAM access reg7*/ +}; + +enum __mag_reg_rst{ + RST_GMAC = (1 << 9),/*Reset the GMAC */ + RST_MII = (3 << 11),/*Reset the MII*/ + RST_OTHERS = 0x5df,/*Reset everybody other than GMAC & MII*/ +}; + +enum __mag_reg_rst_ahb{ + RST_AHB_GMAC = 0x1 +}; +enum __mag_mii0_ctrl_mode{ + MII0_CTRL_MODE_GMII = 0x00, /* GMII*/ + MII0_CTRL_MODE_MII = 0x01, /*MII*/ + MII0_CTRL_MODE_RGMII = 0x02,/* RGMII */ + MII0_CTRL_MODE_RMII = 0x03, /* RMII */ + MII0_CTRL_MASTER_MODE = 0x04 /* master mode */ +}; +enum __mag_mii0_ctrl_speed { + MII0_CTLR_SPEED_10 = 0x00, /* 10 mbps*/ + MII0_CTRL_SPEED_100 = 0x10, /*MII control address 100 Mbps*/ + MII0_CTRL_SPEED_1000 = 0x20 /* 1000 */ +}; + + +enum __gmac_reg_mac_cfg1{ + MAC_CFG1_TX_EN = (1 << 0),/*TX enable*/ + MAC_CFG1_RX_EN = (1 << 2),/*RX enable*/ + MAC_CFG1_TX_FLOW = (1 << 4),/*TX Flow control enable*/ + MAC_CFG1_RX_FLOW = (1 << 5),/*RX Flow control enable*/ + MAC_CFG1_LOOP_EN = (1 << 8),/*Enable loopback*/ +}; +enum __gmac_reg_mac_cfg2{ + MAC_CFG2_FULL_DUP = (1 << 0),/*Enable Full Duplex*/ + MAC_CFG2_PAD_CRC = (1 << 2),/*Enable MAC based CRC insertion*/ + MAC_CFG2_CHK_LEN = (1 << 4),/*Check Length field*/ + MAC_CFG2_HUGE_FRM = (1 << 5),/*Allow sending huge frames*/ + MAC_CFG2_MII = (1 << 8),/*MAC is MII in mode*/ + MAC_CFG2_GMII = (1 << 9),/*MAC is in GMII mode*/ + MAC_CFG2_PREAMBLE = (7 << 12),/*Default Preamble Length*/ +}; +enum __gmac_reg_mii_cfg{ + MII_CFG_CLK_2MHZ = 0x0006,/*Clock is 2Mhz*/ +}; + + +/* following are only for F1 phy on emulation board.*/ +enum __gmac_reg_mii_addr{ + MII_ADDR_RESET = 0x000,/*Flush the MII address register*/ + MII_ADDR_STATS = 0x001,/* Stauts register*/ + MII_ADDR_PHY_IDENT_1 = 0x002,/* phy identifier [18:3]*/ + MII_ADDR_PHY_IDENT_2 = 0x003,/* phy identifier [19:24]*/ + MII_ADDR_AUTONEG_ADV = 0x004,/* Autonegotiaion advertise*/ + MII_ADDR_LINKPART_ABILITY = 0x0005,/* link partner ability*/ + MII_ADDR_AUTONEG_EXP = 0x0006,/* Autonegotiation expansion*/ + MII_ADDR_NEXTPG_TX = 0x0007,/* Next page transmit*/ + MII_ADDR_LINKPART_NEXTPG = 0x0008,/* Link partnet next page*/ + MII_ADDR_1000BASET_CNTRL = 0x0009,/* 1000 base-t control*/ + MII_ADDR_1000BSAET_STATUS = 0x000a,/* 1000 base-t status*/ + MII_ADDR_EXTENDED_STATUS = 0x000f,/* extended status*/ + MII_ADDR_FUNCTION_CTRL = 0x0010,/* function control*/ + MII_ADDR_PHY_REG = 0x0011,/*Phy Status Reg*/ + MII_ADDR_INTERRUPT_ENA = 0x0012,/* interrupt enable*/ + MII_ADDR_INTERRUPT_STATUS = 0x0013,/* interrupt status*/ + MII_ADDR_EXTPHY_CTRL = 0x0014,/* extemded phy specific control*/ + MII_ADDR_CABDET_CTRL = 0x0016,/* cable detect testser control*/ + MII_ADDR_LED_CTRL = 0x0018,/* LED control*/ + MII_ADDR_MANLED_OVER = 0x0019,/* Manual LED override*/ + MII_ADDR_CABDET_STAT = 0x001c,/* cable detect tester status*/ + MII_ADDR_DEBUGPORT_OFF = 0x001d,/* Debug port address offset*/ + MII_ADDR_DEBUGPORT_DATA = 0x001e,/* Debug port data */ +}; + +/* definitions for MII_ADDR_RESET register definitions*/ +#define MII_ADDR_RESET_RESTART_AUTONEG (1 << 9) +#define MII_ADDR_RESET_ENABLE_AUTONEG (1 << 12) +#define MII_ADDR_RESET_ENABLE_LOOPBACK (1<<14) +#define MII_ADDR_RESET_SOFT_RESET (1<<15) +/* flags for autonegotiaion register MII_ADDR_AUTONEG_ADV, + All writes to this register should be followed by a soft + reset on the phy + The list is not exhaustive, only required fields added + */ +#define MII_AUTONEG_10BT_HALF (1<<5) +#define MII_AUTONEG_10BT_FULL (1<<6) +#define MII_AUTONEG_100BT_HALF (1<<7) +#define MII_AUTONEG_100BT_FULL (1<<8) +#define MII_AUTONEG_PAUSE (1<<9) +#define MII_1000BASET_1000BT_HALF (1<<8) +#define MII_1000BASET_1000BT_FULL (1<<9) +enum __gmac_reg_mii_ctrl{ + MII_CTRL_FULL_DPLX = 0x0100,/*Full Duplex mode*/ + MII_CTRL_SPEED_100 = 0x2000,/*Link Speed 100 Mbps*/ + MII_CTRL_LOOPBACK = 0x4000,/*Enable Loopback mode at PHY*/ + MII_CTRL_RESET = 0x8000,/*BMCR reset*/ +}; +enum __gma_reg_mii_cmd{ + MII_CMD_WRITE = 0x0, + MII_CMD_READ = 0x1,/*Perform a Read cycle*/ +}; +enum __gmac_reg_fifo_cfg0{ + FIFO_CFG0_EN = 0x1f00,/*Enable all the Fifo module*/ +}; +enum __gmac_reg_fifo_cfg1{ + FIFO_CFG1_SIZE_2K = (0x7ff << 16),/*Fifo size is 2K*/ +}; +enum __gmac_reg_fifo_cfg4{ + FIFO_CFG4_RX_ALL = 0x3ffff,/*receive all frames*/ +}; +enum __gmac_reg_if_ctrl{ + IF_CTRL_SPEED_100 = (1 << 16),/*Interface speed 100 Mbps for MII*/ +}; + + +#define MAX_MDIO_IO_LEN 14 +#define MDIO_REG_WIDTH 4 +#define MDIO_REG_BASE 0x54200 +#define MDIO_REG_TO_OFFSET( __reg_number__)\ + (MDIO_REG_BASE + (MDIO_REG_WIDTH * (__reg_number__))) + +#define MDIO_OWN_TGT 0x01 +#define MDIO_OWN_HST 0x02 +#define MDIO_REG_WRITE_DELAY 5 /* 5 micro seconds */ + +/*************************GMAC Data types*******************************/ +typedef enum __gmac_pkt_type{ + GMAC_PKT_IS_BCAST, + GMAC_PKT_IS_UCAST +}__gmac_pkt_type_t; + +struct __ethhdr{ + unsigned char dst[ETH_ALEN];/*destination eth addr */ + unsigned char src[ETH_ALEN]; /*source ether addr*/ + A_UINT16 etype;/*ether type*/ +}__attribute__((packed)); +/** + * @brief this is will be in big endian format + */ +struct __athhdr{ +#ifdef LITTLE_ENDIAN + A_UINT8 proto:6, + res:2; +#else + A_UINT8 res:2, + proto:6; +#endif + A_UINT8 res_lo; + A_UINT16 res_hi; +}__attribute__((packed)); + +typedef struct __gmac_hdr{ + struct __ethhdr eth; + struct __athhdr ath; + A_UINT16 align_pad;/*pad it for 4 byte boundary*/ +}__attribute__((packed)) __gmac_hdr_t; + +/*********************************GMAC softC************************/ + +typedef struct __gmac_softc{ + __gmac_hdr_t hdr; + A_UINT16 gran; + HIF_CALLBACK sw; +}__gmac_softc_t; + + + +#endif + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_pci.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_pci.h new file mode 100755 index 0000000..485a659 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_pci.h @@ -0,0 +1,49 @@ + +#ifndef __HIF_PCI_H +#define __HIF_PCI_H + +#include +#include + + +#define PCI_MAX_DATA_PKT_LEN 1664 +#define PCI_MAX_CMD_PKT_LEN 512 +#define PCI_MAX_BOOT_DESC 2 + +typedef enum hif_pci_pipe_rx{ + HIF_PCI_PIPE_RX0, /*Normal Priority RX*/ + HIF_PCI_PIPE_RX1, + HIF_PCI_PIPE_RX2, + HIF_PCI_PIPE_RX3, + HIF_PCI_PIPE_RX_MAX +}hif_pci_pipe_rx_t; + +typedef enum hif_pci_pipe_tx{ + HIF_PCI_PIPE_TX0, /*Normal Priority TX*/ + HIF_PCI_PIPE_TX1, + HIF_PCI_PIPE_TX_MAX +}hif_pci_pipe_tx_t; + +typedef struct __pci_softc{ + HIF_CALLBACK sw; +}__pci_softc_t; + +struct hif_pci_api{ + void (*pci_boot_init)(void); + hif_handle_t (*pci_init)(HIF_CONFIG *pConfig); + void (*pci_reset)(void); + void (*pci_enable)(void); + void (*pci_reap_xmitted)(__pci_softc_t *sc, + dma_engine_t eng_no); + void (*pci_reap_recv)(__pci_softc_t *sc, dma_engine_t eng_no); + A_UINT8 (*pci_get_pipe)(dma_engine_t eng); + dma_engine_t (*pci_get_tx_eng)(hif_pci_pipe_tx_t pipe); + dma_engine_t (*pci_get_rx_eng)(hif_pci_pipe_rx_t pipe); + +}; + +void hif_pci_api_install(struct hif_pci_api *apis); +void hif_pci_module_install(struct hif_api *apis); +#endif + + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_usb.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_usb.h new file mode 100755 index 0000000..addc17e --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/hif_usb.h @@ -0,0 +1,58 @@ +/* + * @File: mbox_hw.h + * + * @Abstract: mailbox hardware definitions + * + * @Notes: + * * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef __HIF_USB_H__ +#define __HIF_USB_H__ + +#include + +#include +#include +#include +//#include +//#include + +#define HIF_USB_PIPE_TX 1 +#define HIF_USB_PIPE_RX 2 +#define HIF_USB_PIPE_INTERRUPT 3 +#define HIF_USB_PIPE_COMMAND 4 +#define HIF_USB_PIPE_HP_TX 5 +#define HIF_USB_PIPE_MP_TX 6 + +struct VBUF_QUEUE +{ + VBUF *head; + VBUF *tail; +}; + + /* the mailbox hardware layer context */ +typedef struct _HIF_USB_CONTEXT { + HIF_CALLBACK hifCb; + struct zsDmaQueue dnQ; + struct zsTxDmaQueue upQ; +#if SYSTEM_MODULE_HP_EP5 + struct zsDmaQueue hpdnQ; // high priority +#endif +#if SYSTEM_MODULE_HP_EP6 + struct zsDmaQueue mpdnQ; // medium priority +#endif + //struct VBUF_QUEUE upVbufQ; + VBUF *cmdQueue; + struct VBUF_QUEUE eventBufQ; + + // Left a door for extension the structure + void *pReserved; +} HIF_USB_CONTEXT; + +void hif_usb_module_install(struct hif_api *apis); + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/htc_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/htc_api.h new file mode 100755 index 0000000..ac053c0 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/htc_api.h @@ -0,0 +1,126 @@ +/* + * @File: htc_api.h + * + * @Abstract: host-target communications API + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef __HTC_API_H__ +#define __HTC_API_H__ + +#include +#include +//#include +//#include +#include +#include + +#define HTC_HDR_SZ HTC_HDR_LENGTH +#define HTC_BUFSZ_MAX_SEND 2048 + +typedef void (* HTC_SERVICE_ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx); +typedef void (* HTC_SERVICE_ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx); + +/* HTC service structure : + * the caller is required to allocate storage for the service structure and register the + * structure using HTC_RegisterService() The service must set the following fields: + * ProcessRecvMsg + * ProcessSendBufferComplete + * ProcessConnect + * ServiceID + * MaxSvcMsgSize (for message validation) + * */ +typedef struct _HTC_SERVICE { + struct _HTC_SERVICE *pNext; + /* Callback for processing receive messages. HTC calls this callback whenever a + * message arrives on the endpoint assigned to this service. + * HTC_BUFFER is a chain of buffers containing a full application message. + * HTC_BUFFER->buffer points to the start of the msg buffer (past the HTC header) */ + //void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, HTC_BUFFER *); + void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx); + /* callback to process completed send buffers */ + //void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, HTC_BUFFER *); + void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx); + /* optional callback when a connection request occurs. + * The EndpointID is the assigned endpoint, the callback returns a connect + * response status code to allow or disallow the connection. + * pDataIn points to the optional meta data supplied in the connection request + * pDataOut points to a buffer to send back meta data + * If no callback is supplied, HTC assumes the connect is allowed */ + A_UINT8 (* ProcessConnect)(struct _HTC_SERVICE *pService, + HTC_ENDPOINT_ID EndpointID, + A_UINT8 *pDataIn, + int LengthIn, + A_UINT8 *pDataOut, + int *pLengthOut); + A_UINT16 ServiceID; /* service ID to match connection requests */ + A_UINT16 ServiceFlags; /* service flags */ + A_UINT16 MaxSvcMsgSize; /* maximum length of service-specific messages exchanged on the endpoint */ + A_UINT16 TrailerSpcCheckLimit; /* amount of space in each send buffer that HTC can check for trailer + data. This should be set to the smallest HTC buffer that can be sent + through the service. The service can disable trailer data insertion + by setting this value to 0. */ + void *ServiceCtx; +} HTC_SERVICE; + +#define HTC_SERVICE_FLAGS_CONNECTED (1 << 0) /* service has at least 1 connection */ + +#define IS_SERVICE_CONNECTED(s) ((s)->ServiceFlags & HTC_SERVICE_FLAGS_CONNECTED) + + /* configuration settings for the WMI service */ +typedef struct _HTC_CONFIG { + int CreditSize; /* */ + int CreditNumber; + //int ControlDownLinkPipeID; + //int ControlUpLinkPipeID; + adf_os_handle_t OSHandle; + hif_handle_t HIFHandle; + pool_handle_t PoolHandle; +} HTC_CONFIG; + +typedef struct _HTC_BUF_CONTEXT { + A_UINT8 end_point; + A_UINT8 htc_flags; /* htc flags (used by HTC layer only) */ +} HTC_BUF_CONTEXT; + +typedef void* htc_handle_t; + +/* + * setup complete function, supplied by HTC caller at HTC_init time. + * HTC calls this function after the host has indicated that the service connection + * phase is complete. + * + */ +typedef void (* HTC_SETUP_COMPLETE_CB)(void); + +struct htc_apis { + htc_handle_t (* _HTC_Init)(HTC_SETUP_COMPLETE_CB, HTC_CONFIG *pConfig); + void (* _HTC_Shutdown)(htc_handle_t); + void (* _HTC_RegisterService)(htc_handle_t, HTC_SERVICE *); + void (* _HTC_Ready)(htc_handle_t); + void (* _HTC_ReturnBuffers)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t); + void (* _HTC_ReturnBuffersList)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t); + void (* _HTC_SendMsg)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t); + int (* _HTC_GetReservedHeadroom)(htc_handle_t handle); + + //void (* _HTC_PauseRecv)(HTC_ENDPOINT_ID EndpointID); + //void (* _HTC_ResumeRecv)(HTC_ENDPOINT_ID EndpointID); + //void (* _HTC_AddBufferResources)(int buffers); + + /* These APIs below are for patch purpose only */ + void (*_HTC_MsgRecvHandler)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); + void (*_HTC_SendDoneHandler)(adf_nbuf_t buf, void *context); + void (*_HTC_ControlSvcProcessMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *arg); + void (*_HTC_ControlSvcProcessSendComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg); + + void *pReserved; /* for expansion if need be */ +}; + +extern void htc_module_install(struct htc_apis *pAPIs); + +#endif /* _HTC_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/intr_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/intr_api.h new file mode 100755 index 0000000..3755241 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/intr_api.h @@ -0,0 +1,150 @@ +#ifndef __INTR_API_H__ +#define __INTR_API_H__ + +/* + * Interrupt handler, for application-managed interrupts. + * When an interrupt occurs, it is automatically disabled. + * See A_WMAC_INTR_ATTACH() and A_MBOX_INTR_ATTACH(). + * + * If a handler returns A_HANDLER_DONE, the interrupt is + * re-enabled. The OS calls the handler next time service + * is required. This is the normal case for a handler. + * + * If a handler returns A_HANDLER_YIELD, the interrupt + * remains masked. The handler is called again when + * it is "convenient". This gives the OS an opportunity + * to run other code/handlers. A handler should return + * A_HANDLER_YIELD if it might dominate the CPU for too + * long. + * + * If a handler returns A_HANDLER_NOENABLE, the interrupt + * remains disabled. It is up to the application to re-enable + * the interrupt (via A_*_INTR_UNMASK) when it's appropriate. + * + * Note that many combinations of interrupt functions and + * interrupt vectors are NOT supported: Callers should use + * only the macros defined in cmnos_api.h to access the + * interrupt API. + */ +#include "cmnos_api.h" + +typedef uint32_t A_old_intr_t; + +////////////////////////////////////////////////////////////////// +// this is copied from mercury/cmnos_xtensa.h +/* + * These are CMNOS interrupt manifest constants. + * They have specially-chosen values that align with hardware and or + * operating system values (see cmnos_interrupt_info). + */ +#if defined(__XTENSA__) +/* + * Enumeration of low and medium priority interrupt numbers + * which match the CPU hardware configuration: + */ + +/* XTensa Level 1 interrupt */ +#define A_INUM_SOFTWARE 0 /* currently unused */ + +/* XTensa Level2 interrupts */ +#define A_INUM_XTTIMER 1 /* currently unused */ + +#define A_INUM_TBD_0 2 /* TBD */ +#define A_INUM_CPU_WDT 3 /* RST_CPU watchodg interrupt */ +#define A_INUM_GMAC_DMA 4 /* GMAC DMA interrupt */ +#define A_INUM_GMAC_MDIO 5 /* GMAC MDIO interrupt */ +#define A_INUM_HOST_DMA 6 /* HOST DMA */ +#define A_INUM_CPU_GEN_TIMER 7 /* CPU general timer */ +#define A_INUM_TBD_8 8 /* TBD */ +#define A_INUM_TBD_9 9 /* TBD */ +#define A_INUM_USB_CTRL 10 /* USB core control */ +#define A_INUM_USB_DMA 11 /* USB DMA */ +#define A_INUM_TBD_12 12 /* TBD */ +#define A_INUM_TBD_13 13 /* TBD */ +#define A_INUM_EMUX_CPU 14 /* EMUX CPU */ +#define A_INUM_GPIO_CPU 15 /* GPIO CPU interrupt */ +#define A_INUM_TBD_16 16 /* TBD */ +#define A_INUM_PCIE_CPU 17 /* CPU PCIE interrupt */ +#define A_INUM_RST_CPU_NMI 18 /* RST CPU nmi interrupt */ + +/* Number of interrupts that map directly into CPU/hal interrupt bits. */ +#define NUM_DIRECT_INTR 19 + +#endif +////////////////////////////////////////////////////////////////// + +#define CMNOS_IMASK_XTTIMER (1<>2)) + +#endif /* _MEM_ADDRS_H_ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/magpie_regdump.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/magpie_regdump.h new file mode 100755 index 0000000..6a599f8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/magpie_regdump.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006 Atheros Communications Inc. + * All rights reserved. + */ + +#ifndef __MAGPIE_REGDUMP_H__ +#define __MAGPIE_REGDUMP_H__ + +#if !defined(__ASSEMBLER__) +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ +struct XTensa_exception_frame_s { + uint32_t xt_pc; + uint32_t xt_ps; + uint32_t xt_sar; + uint32_t xt_vpri; + uint32_t xt_a2; + uint32_t xt_a3; + uint32_t xt_a4; + uint32_t xt_a5; + uint32_t xt_exccause; + uint32_t xt_lcount; + uint32_t xt_lbeg; + uint32_t xt_lend; + + /* Extra info to simplify post-mortem stack walkback */ +#define MAGPIE_REGDUMP_FRAMES 5 + struct { + uint32_t a0; /* pc */ + uint32_t a1; /* sp */ + uint32_t a2; + uint32_t a3; + } wb[MAGPIE_REGDUMP_FRAMES]; +}; + +typedef struct XTensa_exception_frame_s CPU_exception_frame_t; +#define RD_SIZE sizeof(CPU_exception_frame_t) + +#endif +#endif /* __MAGPIE_REGDUMP_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/mem_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/mem_api.h new file mode 100755 index 0000000..e3197dc --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/mem_api.h @@ -0,0 +1,10 @@ +#ifndef __MEM_API_H__ +#define __MEM_API_H__ +struct mem_api { + void (* _mem_init)(void); + void *(* _memset)(void *, int, unsigned int); + void *(* _memcpy)(void *, const void *, unsigned int); + void *(* _memmove)(void *, const void *, unsigned int); + int (* _memcmp)(const void *, const void *, unsigned int); +}; +#endif /* __MEM_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/misc_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/misc_api.h new file mode 100755 index 0000000..3b5da6d --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/misc_api.h @@ -0,0 +1,34 @@ +#ifndef __MISC_API_H__ +#define __MISC_API_H__ + +enum hostif_s{ + HIF_USB = 0, + HIF_PCIE, + HIF_GMAC, + HIF_PCI, + + // HIF should be added above here + HIF_NUM, + HIF_NONE + +}; + +typedef enum hostif_s A_HOSTIF; + +struct register_dump_s; + +struct misc_api { + void (* _system_reset)(void); + void (* _mac_reset)(void); + void (* _assfail)(struct register_dump_s *); + void (* _misaligned_load_handler)(struct register_dump_s *); + + void (* _report_failure_to_host)(struct register_dump_s *, int); + int (* _target_id_get)(void); + A_HOSTIF (* _is_host_present)(void); + + uint8_t (*_kbhit)(uint8_t); + + uint16_t (* _rom_version_get)(void); +}; +#endif /* __MISC_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/opt_ah.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/opt_ah.h new file mode 100755 index 0000000..1a9ba30 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/opt_ah.h @@ -0,0 +1,8 @@ +#define AH_SUPPORT_AR5416 1 +#define AH_SUPPORT_2133 1 +#define AH_SUPPORT_5413 1 +//#define AH_DEBUG 1 +//#define AR5416_EMULATION 1 +#define ATH_FORCE_PPM 1 +#define ATH_FORCE_BIAS 1 +#define AH_SUPPORT_DFS 1 diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/printf_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/printf_api.h new file mode 100755 index 0000000..afcb837 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/printf_api.h @@ -0,0 +1,15 @@ +#ifndef __PRINTF_API_H__ +#define __PRINTF_API_H__ + +struct printf_api { + void (* _printf_init)(void); + int (* _printf)(const char * fmt, ...); +}; + +/* NB: The printf module requires the serial module. */ +void cmnos_printf_module_install(struct printf_api *tbl); +int cmnos_printf(const char *fmt, ...); + + + +#endif /* __PRINTF_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/regdump.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/regdump.h new file mode 100755 index 0000000..6b8df63 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/regdump.h @@ -0,0 +1,33 @@ +#ifndef __REGDUMP_H__ +#define __REGDUMP_H__ + +#include "magpie_regdump.h" + + +#if !defined(__ASSEMBLER__) + +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ + +#define RD_SIZE sizeof(CPU_exception_frame_t) + +/* + * Target CPU state at the time of failure is reflected + * in a register dump, which the Host can fetch through + * the diagnostic window. + */ +struct register_dump_s { + uint32_t target_id; /* Target ID */ + uint32_t assline; /* Line number (if assertion failure) */ + uint32_t pc; /* Program Counter at time of exception */ + uint32_t badvaddr; /* Virtual address causing exception */ + CPU_exception_frame_t exc_frame; /* CPU-specific exception info */ + + /* Could copy top of stack here, too.... */ +}; + + +#endif /* __ASSEMBLER__ */ +#endif /* __REGDUMP_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/romp_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/romp_api.h new file mode 100755 index 0000000..ee476f3 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/romp_api.h @@ -0,0 +1,48 @@ +/*************************************************************************/ +/* Copyright (c) 2008 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : romp_api.h */ +/* */ +/* Abstract */ +/* This file contains definition of data structure and interface */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _ROMP_API_H_ +#define _ROMP_API_H_ + +#include "dt_defs.h" + +/******** hardware API table structure (API descriptions below) *************/ +struct romp_api { + void (*_romp_init)(void); + BOOLEAN (*_romp_download)(uint16_t ); + BOOLEAN (*_romp_install)(void); + BOOLEAN (*_romp_decode)(uint32_t ); +}; + +#define _ROMP_MAGIC_ "[PaTcH]" + +struct rom_patch_st { + uint16_t crc16; // crc filed to maintain the integrity + uint16_t len; // length of the patch code + uint32_t ld_addr; // load address of the patch code + uint32_t fun_addr; // entry address of the patch code + uint8_t *pfun; // patch code +}; + + +struct eep_redir_addr { + uint16_t offset; + uint16_t size; +}; + + +/************************* EXPORT function ***************************/ +uint16_t cal_crc16(uint32_t sz, uint8_t *p); + +#endif // end of _UART_API_H_ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/string_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/string_api.h new file mode 100755 index 0000000..9a15021 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/string_api.h @@ -0,0 +1,11 @@ +#ifndef __STRING_API_H__ +#define __STRING_API_H__ +struct string_api { + void (* _string_init)(void); + char *(* _strcpy)(char *, const char *); + char *(* _strncpy)(char *, const char *, unsigned int); + int (* _strlen)(const char *); + int (* _strcmp)(const char *, const char *); + int (* _strncmp)(const char *, const char *, unsigned int); +}; +#endif /* __STRING_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/sys_cfg.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/sys_cfg.h new file mode 100755 index 0000000..c2a2092 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/sys_cfg.h @@ -0,0 +1,67 @@ +/*************************************************************************/ +/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : sys_cfg.h */ +/* */ +/* Abstract */ +/* This file contains definition of platform and sysmte config . */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _SYS_CFG_H_ +#define _SYS_CFG_H_ + +/************************** FPGA version **************************/ +#define MAGPIE_FPGA_RAM_256K 1 + +/************************** ROM DEFINE ***************************/ + +#if defined(_ROM_) +#include "rom_cfg.h" + +#if MAGPIE_FPGA_RAM_256K == 1 +#undef MAX_BUF_NUM +#define MAX_BUF_NUM 100 +#endif + +#elif defined(_RAM_) + +#include "rom_cfg.h" +#include "magpie_mem.h" + +/************************* Resource DEFS ***********************/ +#define MAX_DESC_NUM 100 + +#ifdef RX_SCATTER +#define MAX_BUF_NUM 60 +#else +#define MAX_BUF_NUM 40 +#endif + +#if MAGPIE_FPGA_RAM_256K == 1 +#undef MAX_BUF_NUM +#define MAX_BUF_NUM 100 +#endif + +#undef SYSTEM_MODULE_DBG +#define SYSTEM_MODULE_DBG 1 + +/************************* WLAN DEFS ***************************/ +#define MAGPIE_ENABLE_WLAN 1 +#define MAGPIE_ENABLE_PCIE 1 +#define MAGPIE_ENABLE_WLAN_IN_TARGET 0 +#define MAGPIE_ENABLE_WLAN_SELF_TX 0 +#define MAGPIE_ENABLE_WLAN_RATE_CTRL 1 +#define WLAN_MAX_RXBUF 15 +#define WLAN_MAX_TXBUF 10 + +/****************************** WATCH DOG *******************************/ +#define WDT_DEFAULT_TIMEOUT_VALUE 3*ONE_MSEC*1000 // Initial value is 3 seconds, firmware changes it to 65 milliseconds + +#endif + + +#endif /* _SYS_CFG_H_ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/tasklet_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/tasklet_api.h new file mode 100755 index 0000000..8ba85f1 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/tasklet_api.h @@ -0,0 +1,28 @@ +#ifndef __TASKLET_API_H__ +#define __TASKLET_API_H__ + +//typedef int A_tasklet_t; + +typedef void (*A_TASKLET_FUNC)(void *arg); + +#define A_TASKLET_STATE_DISABLE 0 +#define A_TASKLET_STATE_SCHEDULED 1 +#define A_TASKLET_STATE_RUNNING 2 + +struct _tasklet { + A_TASKLET_FUNC func; + void *arg; + int state; + struct _tasklet *next; +}; + +typedef struct _tasklet A_tasklet_t; + +struct tasklet_api { + void (* _tasklet_init)(void); + void (* _tasklet_init_task)(A_TASKLET_FUNC, void * arg, A_tasklet_t *); + void (* _tasklet_disable)(A_tasklet_t *); + void (* _tasklet_schedule)(A_tasklet_t *); + void (* _tasklet_run)(void); +}; +#endif /* __TASKLET_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/timer_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/timer_api.h new file mode 100755 index 0000000..025a8e8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/timer_api.h @@ -0,0 +1,23 @@ +#ifndef __TIMER_API_H__ +#define __TIMER_API_H__ +/* + * In order to remain completely independent of OS header files, + * "_SPACE" structures are declared with sufficient room to hold + * corresponding OS structures. + */ +typedef unsigned int _A_TIMER_SPACE[5]; +typedef _A_TIMER_SPACE A_timer_t; +#define A_TIMER A_timer_t /* historical */ + +typedef unsigned int A_HANDLE; /* historical */ +typedef void A_TIMER_FUNC(A_HANDLE timer_handle, void *arg); + +struct timer_api { + void (* _timer_init)(void); + void (* _timer_arm)(A_timer_t *, unsigned int); + void (* _timer_disarm)(A_timer_t *); + void (* _timer_setfn)(A_timer_t *, A_TIMER_FUNC, void *); + void (* _timer_run)(void); +}; +#endif /* __TIMER_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/uart_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/uart_api.h new file mode 100755 index 0000000..392e513 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/uart_api.h @@ -0,0 +1,309 @@ +/*************************************************************************/ +/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : uart.h */ +/* */ +/* Abstract */ +/* This file contains definition of uart registers, marco and api. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _UART_API_H_ +#define _UART_API_H_ + +#include "reg_defs.h" + +/************************* Register Process marco ************************/ +#define UART_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(UART_BASE_ADDRESS|(uint32_t)(addr), (val)) +#define UART_REG_READ(addr) HAL_WORD_REG_READ(UART_BASE_ADDRESS|(uint32_t)(addr)) + +/************************** Register deinition ***************************/ +#define RBR_ADDRESS 0x00051000 +#define RBR_OFFSET 0x00000000 +#define RBR_RBR_MSB 7 +#define RBR_RBR_LSB 0 +#define RBR_RBR_MASK 0x000000ff +#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) +#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) + +#define THR_ADDRESS 0x00051000 +#define THR_OFFSET 0x00000000 +#define THR_THR_MSB 7 +#define THR_THR_LSB 0 +#define THR_THR_MASK 0x000000ff +#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) +#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) + +#define DLL_ADDRESS 0x00051000 +#define DLL_OFFSET 0x00000000 +#define DLL_DLL_MSB 7 +#define DLL_DLL_LSB 0 +#define DLL_DLL_MASK 0x000000ff +#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) +#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) + +#define DLH_ADDRESS 0x00051004 +#define DLH_OFFSET 0x00000004 +#define DLH_DLH_MSB 7 +#define DLH_DLH_LSB 0 +#define DLH_DLH_MASK 0x000000ff +#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) +#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) + +#define IER_ADDRESS 0x00051004 +#define IER_OFFSET 0x00000004 +#define IER_EDDSI_MSB 3 +#define IER_EDDSI_LSB 3 +#define IER_EDDSI_MASK 0x00000008 +#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) +#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) +#define IER_ELSI_MSB 2 +#define IER_ELSI_LSB 2 +#define IER_ELSI_MASK 0x00000004 +#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) +#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) +#define IER_ETBEI_MSB 1 +#define IER_ETBEI_LSB 1 +#define IER_ETBEI_MASK 0x00000002 +#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) +#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) +#define IER_ERBFI_MSB 0 +#define IER_ERBFI_LSB 0 +#define IER_ERBFI_MASK 0x00000001 +#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) +#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) + +#define IIR_ADDRESS 0x00051008 +#define IIR_OFFSET 0x00000008 +#define IIR_FIFO_STATUS_MSB 7 +#define IIR_FIFO_STATUS_LSB 6 +#define IIR_FIFO_STATUS_MASK 0x000000c0 +#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) +#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) +#define IIR_IID_MSB 3 +#define IIR_IID_LSB 0 +#define IIR_IID_MASK 0x0000000f +#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) +#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) + +#define FCR_ADDRESS 0x00051008 +#define FCR_OFFSET 0x00000008 +#define FCR_RCVR_TRIG_MSB 7 +#define FCR_RCVR_TRIG_LSB 6 +#define FCR_RCVR_TRIG_MASK 0x000000c0 +#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) +#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) +#define FCR_DMA_MODE_MSB 3 +#define FCR_DMA_MODE_LSB 3 +#define FCR_DMA_MODE_MASK 0x00000008 +#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) +#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) +#define FCR_XMIT_FIFO_RST_MSB 2 +#define FCR_XMIT_FIFO_RST_LSB 2 +#define FCR_XMIT_FIFO_RST_MASK 0x00000004 +#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) +#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) +#define FCR_RCVR_FIFO_RST_MSB 1 +#define FCR_RCVR_FIFO_RST_LSB 1 +#define FCR_RCVR_FIFO_RST_MASK 0x00000002 +#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) +#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) +#define FCR_FIFO_EN_MSB 0 +#define FCR_FIFO_EN_LSB 0 +#define FCR_FIFO_EN_MASK 0x00000001 +#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) +#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) + +#define LCR_ADDRESS 0x0005100c +#define LCR_OFFSET 0x0000000c +#define LCR_DLAB_MSB 7 +#define LCR_DLAB_LSB 7 +#define LCR_DLAB_MASK 0x00000080 +#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) +#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) +#define LCR_BREAK_MSB 6 +#define LCR_BREAK_LSB 6 +#define LCR_BREAK_MASK 0x00000040 +#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) +#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) +#define LCR_EPS_MSB 4 +#define LCR_EPS_LSB 4 +#define LCR_EPS_MASK 0x00000010 +#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) +#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) +#define LCR_PEN_MSB 3 +#define LCR_PEN_LSB 3 +#define LCR_PEN_MASK 0x00000008 +#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) +#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) +#define LCR_STOP_MSB 2 +#define LCR_STOP_LSB 2 +#define LCR_STOP_MASK 0x00000004 +#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) +#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) +#define LCR_CLS_MSB 1 +#define LCR_CLS_LSB 0 +#define LCR_CLS_MASK 0x00000003 +#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) +#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) + +#define MCR_ADDRESS 0x00051010 +#define MCR_OFFSET 0x00000010 +#define MCR_LOOPBACK_MSB 5 +#define MCR_LOOPBACK_LSB 5 +#define MCR_LOOPBACK_MASK 0x00000020 +#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) +#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) +#define MCR_OUT2_MSB 3 +#define MCR_OUT2_LSB 3 +#define MCR_OUT2_MASK 0x00000008 +#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) +#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) +#define MCR_OUT1_MSB 2 +#define MCR_OUT1_LSB 2 +#define MCR_OUT1_MASK 0x00000004 +#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) +#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) +#define MCR_RTS_MSB 1 +#define MCR_RTS_LSB 1 +#define MCR_RTS_MASK 0x00000002 +#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) +#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) +#define MCR_DTR_MSB 0 +#define MCR_DTR_LSB 0 +#define MCR_DTR_MASK 0x00000001 +#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) +#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) + +#define LSR_ADDRESS 0x00051014 +#define LSR_OFFSET 0x00000014 +#define LSR_FERR_MSB 7 +#define LSR_FERR_LSB 7 +#define LSR_FERR_MASK 0x00000080 +#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) +#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) +#define LSR_TEMT_MSB 6 +#define LSR_TEMT_LSB 6 +#define LSR_TEMT_MASK 0x00000040 +#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) +#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) +#define LSR_THRE_MSB 5 +#define LSR_THRE_LSB 5 +#define LSR_THRE_MASK 0x00000020 +#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) +#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) +#define LSR_BI_MSB 4 +#define LSR_BI_LSB 4 +#define LSR_BI_MASK 0x00000010 +#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) +#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) +#define LSR_FE_MSB 3 +#define LSR_FE_LSB 3 +#define LSR_FE_MASK 0x00000008 +#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) +#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) +#define LSR_PE_MSB 2 +#define LSR_PE_LSB 2 +#define LSR_PE_MASK 0x00000004 +#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) +#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) +#define LSR_OE_MSB 1 +#define LSR_OE_LSB 1 +#define LSR_OE_MASK 0x00000002 +#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) +#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) +#define LSR_DR_MSB 0 +#define LSR_DR_LSB 0 +#define LSR_DR_MASK 0x00000001 +#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) +#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) + +#define MSR_ADDRESS 0x00051018 +#define MSR_OFFSET 0x00000018 +#define MSR_DCD_MSB 7 +#define MSR_DCD_LSB 7 +#define MSR_DCD_MASK 0x00000080 +#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) +#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) +#define MSR_RI_MSB 6 +#define MSR_RI_LSB 6 +#define MSR_RI_MASK 0x00000040 +#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) +#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) +#define MSR_DSR_MSB 5 +#define MSR_DSR_LSB 5 +#define MSR_DSR_MASK 0x00000020 +#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) +#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) +#define MSR_CTS_MSB 4 +#define MSR_CTS_LSB 4 +#define MSR_CTS_MASK 0x00000010 +#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) +#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) +#define MSR_DDCD_MSB 3 +#define MSR_DDCD_LSB 3 +#define MSR_DDCD_MASK 0x00000008 +#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) +#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) +#define MSR_TERI_MSB 2 +#define MSR_TERI_LSB 2 +#define MSR_TERI_MASK 0x00000004 +#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) +#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) +#define MSR_DDSR_MSB 1 +#define MSR_DDSR_LSB 1 +#define MSR_DDSR_MASK 0x00000002 +#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) +#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) +#define MSR_DCTS_MSB 0 +#define MSR_DCTS_LSB 0 +#define MSR_DCTS_MASK 0x00000001 +#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) +#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) + + +/************************** config definition ***************************/ +#define UART_FIFO_SIZE 512 //Must be 2^N + +#define USE_POST_BUFFER 0 // ENABLE a tx buffer for post processing, +/*********************** data struction definition ************************/ +// data struction definition +struct uart_fifo { +#if USE_POST_BUFFER + uint8_t buf[UART_FIFO_SIZE]; +#endif + uint16_t start_index; + uint16_t end_index; + uint32_t overrun_err; +}; + + +struct uart_blk { + uint16_t debug_mode; + uint16_t baud; + struct uart_api *_uart; + struct uart_fifo _tx; +}; + + +/******** hardware API table structure (API descriptions below) *************/ +struct uart_api { + uint32_t (*_uart_init)(void); + void (*_uart_char_put)(uint8_t ch); + uint16_t (*_uart_char_get)(uint8_t* ch); + void (*_uart_str_out)(uint8_t* str); + void (*_uart_task)(void); + uint32_t (*_uart_status)(void); + void (*_uart_config)(uint16_t flag); + void (*_uart_hwinit)(uint32_t freq, uint32_t baud); + //void (*_uart_config)(uint8_t cmd, void *pData); +}; + +/************************* EXPORT function ***************************/ + + +#endif // end of _UART_API_H_ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_api.h new file mode 100755 index 0000000..a9c3168 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_api.h @@ -0,0 +1,52 @@ +#ifndef USB_API_H +#define USB_API_H + +#include "dt_defs.h" + +/******** hardware API table structure (API descriptions below) *************/ +struct usb_api { + void (*_usb_init)(void); + void (*_usb_rom_task)(void); + void (*_usb_fw_task)(void); + void (*_usb_init_phy)(void); + + // ep0 operation + void (*_usb_ep0_setup)(void); + + void (*_usb_ep0_tx)(void); + void (*_usb_ep0_rx)(void); + + // get/set interface + BOOLEAN (*_usb_get_interface)(void); + BOOLEAN (*_usb_set_interface)(void); + + // get/set configuration + BOOLEAN (*_usb_get_configuration)(void); + BOOLEAN (*_usb_set_configuration)(void); + + // standard/vendor command + BOOLEAN (*_usb_standard_cmd)(void); + void (*_usb_vendor_cmd)(void); + + void (*_usb_power_off)(void); + void (*_usb_reset_fifo)(void); + void (*_usb_gen_wdt)(void); + void (*_usb_jump_boot)(void); + + BOOLEAN (*_usb_clr_feature)(void); + BOOLEAN (*_usb_set_feature)(void); + BOOLEAN (*_usb_set_address)(void); + BOOLEAN (*_usb_get_descriptor)(void); + + BOOLEAN (*_usb_get_status)(void); + void (*_usb_setup_desc)(void); + void (*_usb_reg_out)(void); + void (*_usb_status_in)(void); + + void (*_usb_ep0_tx_data)(void); + void (*_usb_ep0_rx_data)(void); + + void (*_usb_clk_init)(void); +}; + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_defs.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_defs.h new file mode 100755 index 0000000..bef0190 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_defs.h @@ -0,0 +1,904 @@ +#ifndef USB_DEFS_H +#define USB_DEFS_H + +#include "usb_table.h" +#include "dt_defs.h" +#include "reg_defs.h" + +#define CHECK_SWITCH_BY_BOOTCODE 1 //to be verified for ZD1215, OK for ZD1211 +#define VERIFY_CHECKSUM_BY_BOOTCODE 1 + +/***********************************************************************/ +/* for SEEPROM Boot */ +/***********************************************************************/ +#define WLAN_BOOT_SIGNATURE (0x19710303) + +#define WLAN_SIGNATURE_ADDR (0x102000) + +#define cMAX_ADDR 0x10000 + +#define cEEPROM_SIZE 0x800 // 2k word (4k byte) + +#define cRESERVE_LOAD_SPACE 0 + +// start addr. of boot code +#define cBOOT_CODE_ADDR (cMAX_ADDR - cEEPROM_SIZE) // 0xF800 + +/************************** Register Addr Process *********************/ +#define mpADDR(addr) ((volatile uint16_t*) (addr)) +#define mADDR(addr) (*mpADDR(addr)) +#define muADDR(addr) ((uint16_t) (&(addr))) + +#define USB_BYTE_REG_WRITE(addr, val) HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val)) +#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3)) +//#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr)) + +#define USB_HALF_WORD_REG_WRITE(addr, val) HAL_HALF_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr), (val)) +#define USB_HALF_WORD_REG_READ(addr) HAL_HALF_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr)) + +#define USB_WORD_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val)) +#define USB_WORD_REG_READ(addr) HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr)) + + +/************************** Register Deinition ***************************/ +//#define USB_BASE_ADDR_SOC 0x8000 + +//#define SOC_Reg mpADDR(USB_BASE_ADDR_SOC) + +#define cSOC_USB_OFST (0x100) + +#define ZM_CBUS_FIFO_SIZE_OFFSET (cSOC_USB_OFST) //OFFSET 0 + +#define cSOC_CBUS_CTL_OFFSET 0xF0 + +#define ZM_FUSB_BASE USB_CTRL_BASE_ADDRESS + +#define ZM_MAIN_CTRL_OFFSET 0x00 +#define ZM_DEVICE_ADDRESS_OFFSET 0x01 +#define ZM_TEST_OFFSET 0x02 +#define ZM_PHY_TEST_SELECT_OFFSET 0x08 +#define ZM_VDR_SPECIFIC_MODE_OFFSET 0x0A +#define ZM_CX_CONFIG_STATUS_OFFSET 0x0B +#define ZM_EP0_DATA1_OFFSET 0x0C +#define ZM_EP0_DATA2_OFFSET 0x0D +#define ZM_EP0_DATA_OFFSET 0x0C + +#define ZM_INTR_MASK_BYTE_0_OFFSET 0x11 +#define ZM_INTR_MASK_BYTE_1_OFFSET 0x12 +#define ZM_INTR_MASK_BYTE_2_OFFSET 0x13 +#define ZM_INTR_MASK_BYTE_3_OFFSET 0x14 +#define ZM_INTR_MASK_BYTE_4_OFFSET 0x15 +#define ZM_INTR_MASK_BYTE_5_OFFSET 0x16 +#define ZM_INTR_MASK_BYTE_6_OFFSET 0x17 +#define ZM_INTR_MASK_BYTE_7_OFFSET 0x18 + +#define ZM_INTR_GROUP_OFFSET 0x20 +#define ZM_INTR_SOURCE_0_OFFSET 0x21 +#define ZM_INTR_SOURCE_1_OFFSET 0x22 +#define ZM_INTR_SOURCE_2_OFFSET 0x23 +#define ZM_INTR_SOURCE_3_OFFSET 0x24 +#define ZM_INTR_SOURCE_4_OFFSET 0x25 +#define ZM_INTR_SOURCE_5_OFFSET 0x26 +#define ZM_INTR_SOURCE_6_OFFSET 0x27 +#define ZM_INTR_SOURCE_7_OFFSET 0x28 + +#define ZM_EP_IN_MAX_SIZE_HIGH_OFFSET 0x3F +#define ZM_EP_IN_MAX_SIZE_LOW_OFFSET 0x3E + +#define ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET 0x5F +#define ZM_EP_OUT_MAX_SIZE_LOW_OFFSET 0x5E + +#define ZM_EP3_BYTE_COUNT_HIGH_OFFSET 0xAE +#define ZM_EP3_BYTE_COUNT_LOW_OFFSET 0xBE +#define ZM_EP4_BYTE_COUNT_HIGH_OFFSET 0xAF +#define ZM_EP4_BYTE_COUNT_LOW_OFFSET 0xBF + +#define ZM_EP3_DATA_OFFSET 0xF8 +#define ZM_EP4_DATA_OFFSET 0xFC + +#define ZM_SOC_USB_MODE_CTRL_OFFSET 0x108 +#define ZM_SOC_USB_MAX_AGGREGATE_OFFSET 0x110 +#define ZM_SOC_USB_TIME_CTRL_OFFSET 0x114 + +#define ZM_ADDR_CONV 0x0 + +#define ZM_CBUS_FIFO_SIZE_REG (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV) + +#define ZM_CBUS_CTRL_REG (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV) + +#define ZM_MAIN_CTRL_REG (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV) + +#define ZM_DEVICE_ADDRESS_REG (ZM_DEVICE_ADDRESS_OFFSET^ZM_ADDR_CONV) + +#define ZM_TEST_REG (ZM_TEST_OFFSET^ZM_ADDR_CONV) + +#define ZM_PHY_TEST_SELECT_REG (ZM_PHY_TEST_SELECT_OFFSET^ZM_ADDR_CONV))) + +#define ZM_CX_CONFIG_STATUS_REG (ZM_CX_CONFIG_STATUS_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP0_DATA1_REG (ZM_EP0_DATA1_OFFSET^ZM_ADDR_CONV))) + +#define ZM_EP0_DATA2_REG (ZM_EP0_DATA2_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP0_DATA_REG (ZM_EP0_DATA_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_0_REG (ZM_INTR_MASK_BYTE_0_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_1_REG (ZM_INTR_MASK_BYTE_1_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_2_REG (ZM_INTR_MASK_BYTE_2_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_3_REG (ZM_INTR_MASK_BYTE_3_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_4_REG (ZM_INTR_MASK_BYTE_4_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_5_REG (ZM_INTR_MASK_BYTE_5_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_6_REG (ZM_INTR_MASK_BYTE_6_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_7_REG (ZM_INTR_MASK_BYTE_7_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_0_REG (ZM_INTR_SOURCE_0_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_1_REG (ZM_INTR_SOURCE_1_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_2_REG (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_3_REG (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_4_REG (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_5_REG (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_6_REG (ZM_INTR_SOURCE_6_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_7_REG (ZM_INTR_SOURCE_7_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_GROUP_REG (ZM_INTR_GROUP_OFFSET^ZM_ADDR_CONV))) + +#define ZM_EP3_BYTE_COUNT_HIGH_REG (ZM_EP3_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP3_BYTE_COUNT_LOW_REG (ZM_EP3_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP4_BYTE_COUNT_HIGH_REG (ZM_EP4_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP4_BYTE_COUNT_LOW_REG (ZM_EP4_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP3_DATA_REG (ZM_EP3_DATA_OFFSET) + +#define ZM_EP4_DATA_REG (ZM_EP4_DATA_OFFSET) + +#define ZM_SOC_USB_MODE_CTRL_REG (ZM_SOC_USB_MODE_CTRL_OFFSET) + +#define ZM_SOC_USB_MAX_AGGREGATE_REG (ZM_SOC_USB_MAX_AGGREGATE_OFFSET) + +#define ZM_SOC_USB_TIME_CTRL_REG (ZM_SOC_USB_TIME_CTRL_OFFSET) + +#define bmHIGH_SPEED BIT6 +#define bmCWR_BUF_END BIT1 + +#define mUsbEP0DataRd1() (USB_BYTE_REG_READ(ZM_EP0_DATA1_OFFSET)) +//#define mUsbEP0DataRd2() ZM_EP0_DATA2_REG +//#define mUsbEP0DataRd3() ZM_EP0_DATA3_REG +//#define mUsbEP0DataRd4() ZM_EP0_DATA4_REG +#define mUsbEP0DataWr1(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA1_OFFSET, data)) +#define mUsbEP0DataWr2(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA2_OFFSET, data)) + +#define mGetByte0(data) ( data & 0xff ) +#define mGetByte1(data) ( (data >> 8) & 0xff ) +#define mGetByte2(data) ( (data >> 16) & 0xff ) +#define mGetByte3(data) ( (data >> 24) & 0xff ) + +//#define mUsbHighSpeedST() (ZM_MAIN_CTRL_REG & BIT6) +//#define mUsbCfgST() (ZM_DEVICE_ADDRESS_REG & BIT7) +//#define mUsbApWrEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END) +//#define mUsbApRdEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END) + +#define mUsbHighSpeedST() (USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET) & BIT6) +#define mUsbCfgST() (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET) & BIT7) +#define mUsbApWrEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END) +#define mUsbApRdEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END) + +#define mUsbRmWkupST() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT0) +#define mUsbRmWkupClr() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0) +#define mUsbRmWkupSet() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0) + +#define mUsbGlobIntEnable() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2) + +#define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f) +#define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)|0xc0) +#define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf) +#define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0) +// USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0x40) + +#define mUSB_EP3_XFER_DONE() USB_BYTE_REG_WRITE(ZM_EP3_BYTE_COUNT_HIGH_OFFSET, \ + USB_BYTE_REG_READ(ZM_EP3_BYTE_COUNT_HIGH_OFFSET)|0x08) + + + +#define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512 +#define HS_C1_I0_A0_EP1_bInterval 00 + +#define HS_C1_I0_A0_EP_NUMBER 0x06 +#define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER) +#define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH) +#define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH) + +#define HS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + HS_C1_INTERFACE_LENGTH) +#define FS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + FS_C1_INTERFACE_LENGTH) + +#define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64 +//#define FS_C1_I0_A0_EP1_bInterval HS_C1_I0_A0_EP1_bInterval + +#define HS_CONFIGURATION_NUMBER 1 +#define FS_CONFIGURATION_NUMBER 1 + +#define fDOUBLE_BUF 1 +#define fDOUBLE_BUF_IN 1 + +#define fFLASH_DISK 0 +#define fENABLE_ISO 0 + +#if (HS_CONFIGURATION_NUMBER >= 1) + // Configuration 0X01 + #define HS_C1_INTERFACE_NUMBER 0x01 + #define HS_C1 0x01 + #define HS_C1_iConfiguration 0x00 + #define HS_C1_bmAttribute 0x80 + #if !(fFLASH_DISK && !fFLASH_BOOT) + #define HS_C1_iMaxPower 0xFA + #else + #define HS_C1_iMaxPower 0x32 + #endif + + #if (HS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #define HS_C1_I0_ALT_NUMBER 0X01 + #if (HS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0X00 + #define HS_C1_I0_A0_bInterfaceNumber 0X00 + #define HS_C1_I0_A0_bAlternateSetting 0X00 + //JWEI 2003/07/14 + //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT) + #define HS_C1_I0_A0_EP_NUMBER 0x06 + //#else + //#define HS_C1_I0_A0_EP_NUMBER 0X03 + //#endif + #if !(fFLASH_DISK && !fFLASH_BOOT) + #define HS_C1_I0_A0_bInterfaceClass 0XFF + #define HS_C1_I0_A0_bInterfaceSubClass 0X00 + #define HS_C1_I0_A0_bInterfaceProtocol 0X00 + #else + #define HS_C1_I0_A0_bInterfaceClass 0X08 + #define HS_C1_I0_A0_bInterfaceSubClass 0X06 + #define HS_C1_I0_A0_bInterfaceProtocol 0X50 + #endif + #define HS_C1_I0_A0_iInterface 0X00 + + #if (HS_C1_I0_A0_EP_NUMBER >= 1) + //EP0X01 + #define HS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE + //JWEI 2003/05/19 + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP1_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK + //JWEI 2003/05/07 + #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP1_bInterval 00 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 2) + //EP0X02 + #define HS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE + //JWEI 2003/08/20 + #if fDOUBLE_BUF_IN + #define HS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP2_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN + #define HS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK + #define HS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP2_bInterval 00 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 3) + //EP0X03 + #define HS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE + #define HS_C1_I0_A0_EP3_BLKNO SINGLE_BLK + #define HS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN + #define HS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT + #define HS_C1_I0_A0_EP3_MAX_PACKET 0x0040 + #define HS_C1_I0_A0_EP3_bInterval 01 + #endif + // Note: HS Bulk type require max pkt size = 512 + // ==> must use Interrupt type for max pkt size = 64 + #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + //EP0X04 + #define HS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE + #define HS_C1_I0_A0_EP4_BLKNO SINGLE_BLK + #define HS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP4_TYPE TF_TYPE_INTERRUPT + #define HS_C1_I0_A0_EP4_MAX_PACKET 0x0040 + #define HS_C1_I0_A0_EP4_bInterval 01 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 5) + //EP0X04 + #define HS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP5_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK + #define HS_C1_I0_A0_EP5_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP5_bInterval 00 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 6) + //EP0X04 + #define HS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP6_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK + #define HS_C1_I0_A0_EP6_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP6_bInterval 00 + #endif + #endif + #endif +#endif + +#if (HS_CONFIGURATION_NUMBER >= 1) + // Configuration 1 + #if (HS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #if (HS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER) + #if (HS_C1_I0_A0_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I0_A0_EP1_FIFO_START FIFO0 + #define HS_C1_I0_A0_EP1_FIFO_NO (HS_C1_I0_A0_EP1_BLKNO * HS_C1_I0_A0_EP1_BLKSIZE) + #define HS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP1_BLKNO - 1) << 2) | HS_C1_I0_A0_EP1_TYPE) + #define HS_C1_I0_A0_EP1_FIFO_MAP (((1 - HS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I0_A0_EP1_MAP (HS_C1_I0_A0_EP1_FIFO_START | (HS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP1_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 2) + // EP2 + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP2_FIFO_START (HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO) + #else + #define HS_C1_I0_A0_EP2_FIFO_START FIFO2 + #endif + #define HS_C1_I0_A0_EP2_FIFO_NO (HS_C1_I0_A0_EP2_BLKNO * HS_C1_I0_A0_EP2_BLKSIZE) + #define HS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP2_BLKNO - 1) << 2) | HS_C1_I0_A0_EP2_TYPE) + #define HS_C1_I0_A0_EP2_FIFO_MAP (((1 - HS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I0_A0_EP2_MAP (HS_C1_I0_A0_EP2_FIFO_START | (HS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP2_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 3) + // EP3 + //JWEI 2003/07/15 + // #define HS_C1_I0_A0_EP3_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO) + #define HS_C1_I0_A0_EP3_FIFO_START FIFO14 + #define HS_C1_I0_A0_EP3_FIFO_NO (HS_C1_I0_A0_EP3_BLKNO * HS_C1_I0_A0_EP3_BLKSIZE) + #define HS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP3_BLKNO - 1) << 2) | HS_C1_I0_A0_EP3_TYPE) + #define HS_C1_I0_A0_EP3_FIFO_MAP (((1 - HS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I0_A0_EP3_MAP (HS_C1_I0_A0_EP3_FIFO_START | (HS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP3_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + // EP4 + #define HS_C1_I0_A0_EP4_FIFO_START (HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO) + #define HS_C1_I0_A0_EP4_FIFO_NO (HS_C1_I0_A0_EP4_BLKNO * HS_C1_I0_A0_EP4_BLKSIZE) + #define HS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP4_BLKNO - 1) << 2) | HS_C1_I0_A0_EP4_TYPE) + #define HS_C1_I0_A0_EP4_FIFO_MAP (((1 - HS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4) + #define HS_C1_I0_A0_EP4_MAP (HS_C1_I0_A0_EP4_FIFO_START | (HS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP4_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 5) + // EP5 + #define HS_C1_I0_A0_EP5_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO) + #define HS_C1_I0_A0_EP5_FIFO_NO (HS_C1_I0_A0_EP5_BLKNO * HS_C1_I0_A0_EP5_BLKSIZE) + #define HS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP5_BLKNO - 1) << 2) | HS_C1_I0_A0_EP5_TYPE) + #define HS_C1_I0_A0_EP5_FIFO_MAP (((1 - HS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5) + #define HS_C1_I0_A0_EP5_MAP (HS_C1_I0_A0_EP5_FIFO_START | (HS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP5_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 6) + // EP5 + #define HS_C1_I0_A0_EP6_FIFO_START (HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO) + #define HS_C1_I0_A0_EP6_FIFO_NO (HS_C1_I0_A0_EP6_BLKNO * HS_C1_I0_A0_EP6_BLKSIZE) + #define HS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP6_BLKNO - 1) << 2) | HS_C1_I0_A0_EP6_TYPE) + #define HS_C1_I0_A0_EP6_FIFO_MAP (((1 - HS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6) + #define HS_C1_I0_A0_EP6_MAP (HS_C1_I0_A0_EP6_FIFO_START | (HS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP6_DIRECTION))) + #endif + #endif + + #if (HS_C1_I0_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define HS_C1_I0_A1_EP_LENGTH (EP_LENGTH * HS_C1_I0_A1_EP_NUMBER) + #if (HS_C1_I0_A1_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I0_A1_EP1_FIFO_START FIFO0 + #define HS_C1_I0_A1_EP1_FIFO_NO (HS_C1_I0_A1_EP1_BLKNO * HS_C1_I0_A1_EP1_BLKSIZE) + #define HS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP1_BLKNO - 1) << 2) | HS_C1_I0_A1_EP1_TYPE) + #define HS_C1_I0_A1_EP1_FIFO_MAP (((1 - HS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I0_A1_EP1_MAP (HS_C1_I0_A1_EP1_FIFO_START | (HS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP1_DIRECTION))) + #endif + #if (HS_C1_I0_A1_EP_NUMBER >= 2) + // EP2 + #define HS_C1_I0_A1_EP2_FIFO_START (HS_C1_I0_A1_EP1_FIFO_START + HS_C1_I0_A1_EP1_FIFO_NO) + #define HS_C1_I0_A1_EP2_FIFO_NO (HS_C1_I0_A1_EP2_BLKNO * HS_C1_I0_A1_EP2_BLKSIZE) + #define HS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP2_BLKNO - 1) << 2) | HS_C1_I0_A1_EP2_TYPE) + #define HS_C1_I0_A1_EP2_FIFO_MAP (((1 - HS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I0_A1_EP2_MAP (HS_C1_I0_A1_EP2_FIFO_START | (HS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP2_DIRECTION))) + #endif + #if (HS_C1_I0_A1_EP_NUMBER >= 3) + // EP3 + #define HS_C1_I0_A1_EP3_FIFO_START (HS_C1_I0_A1_EP2_FIFO_START + HS_C1_I0_A1_EP2_FIFO_NO) + #define HS_C1_I0_A1_EP3_FIFO_NO (HS_C1_I0_A1_EP3_BLKNO * HS_C1_I0_A1_EP3_BLKSIZE) + #define HS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP3_BLKNO - 1) << 2) | HS_C1_I0_A1_EP3_TYPE) + #define HS_C1_I0_A1_EP3_FIFO_MAP (((1 - HS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I0_A1_EP3_MAP (HS_C1_I0_A1_EP3_FIFO_START | (HS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP3_DIRECTION))) + #endif + #endif + + #if (HS_C1_I0_ALT_NUMBER == 1) + #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH) + #elif (HS_C1_I0_ALT_NUMBER == 2) + #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH + HS_C1_I0_A1_EP_LENGTH) + #endif + #endif + + #if (HS_C1_INTERFACE_NUMBER >= 2) + // Interface 1 + #if (HS_C1_I1_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define HS_C1_I1_A0_EP_LENGTH (EP_LENGTH * HS_C1_I1_A0_EP_NUMBER) + #if (HS_C1_I1_A0_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I1_A0_EP1_FIFO_START FIFO0 + #define HS_C1_I1_A0_EP1_FIFO_NO (HS_C1_I1_A0_EP1_BLKNO * HS_C1_I1_A0_EP1_BLKSIZE) + #define HS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP1_BLKNO - 1) << 2) | HS_C1_I1_A0_EP1_TYPE) + #define HS_C1_I1_A0_EP1_FIFO_MAP (((1 - HS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I1_A0_EP1_MAP (HS_C1_I1_A0_EP1_FIFO_START | (HS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP1_DIRECTION))) + #endif + #if (HS_C1_I1_A0_EP_NUMBER >= 2) + // EP2 + #define HS_C1_I1_A0_EP2_FIFO_START (HS_C1_I1_A0_EP1_FIFO_START + HS_C1_I1_A0_EP1_FIFO_NO) + #define HS_C1_I1_A0_EP2_FIFO_NO (HS_C1_I1_A0_EP2_BLKNO * HS_C1_I1_A0_EP2_BLKSIZE) + #define HS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP2_BLKNO - 1) << 2) | HS_C1_I1_A0_EP2_TYPE) + #define HS_C1_I1_A0_EP2_FIFO_MAP (((1 - HS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I1_A0_EP2_MAP (HS_C1_I1_A0_EP2_FIFO_START | (HS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP2_DIRECTION))) + #endif + #if (HS_C1_I1_A0_EP_NUMBER >= 3) + // EP3 + #define HS_C1_I1_A0_EP3_FIFO_START (HS_C1_I1_A0_EP2_FIFO_START + HS_C1_I1_A0_EP2_FIFO_NO) + #define HS_C1_I1_A0_EP3_FIFO_NO (HS_C1_I1_A0_EP3_BLKNO * HS_C1_I1_A0_EP3_BLKSIZE) + #define HS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP3_BLKNO - 1) << 2) | HS_C1_I1_A0_EP3_TYPE) + #define HS_C1_I1_A0_EP3_FIFO_MAP (((1 - HS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I1_A0_EP3_MAP (HS_C1_I1_A0_EP3_FIFO_START | (HS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP3_DIRECTION))) + #endif + #endif + + #if (HS_C1_I1_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define HS_C1_I1_A1_EP_LENGTH (EP_LENGTH * HS_C1_I1_A1_EP_NUMBER) + #if (HS_C1_I1_A1_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I1_A1_EP1_FIFO_START FIFO0 + #define HS_C1_I1_A1_EP1_FIFO_NO (HS_C1_I1_A1_EP1_BLKNO * HS_C1_I1_A1_EP1_BLKSIZE) + #define HS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP1_BLKNO - 1) << 2) | HS_C1_I1_A1_EP1_TYPE) + #define HS_C1_I1_A1_EP1_FIFO_MAP (((1 - HS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I1_A1_EP1_MAP (HS_C1_I1_A1_EP1_FIFO_START | (HS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP1_DIRECTION))) + #endif + #if (HS_C1_I1_A1_EP_NUMBER >= 2) + // EP2 + #define HS_C1_I1_A1_EP2_FIFO_START (HS_C1_I1_A1_EP1_FIFO_START + HS_C1_I1_A1_EP1_FIFO_NO) + #define HS_C1_I1_A1_EP2_FIFO_NO (HS_C1_I1_A1_EP2_BLKNO * HS_C1_I1_A1_EP2_BLKSIZE) + #define HS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP2_BLKNO - 1) << 2) | HS_C1_I1_A1_EP2_TYPE) + #define HS_C1_I1_A1_EP2_FIFO_MAP (((1 - HS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I1_A1_EP2_MAP (HS_C1_I1_A1_EP2_FIFO_START | (HS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP2_DIRECTION))) + #endif + #if (HS_C1_I1_A1_EP_NUMBER >= 3) + // EP3 + #define HS_C1_I1_A1_EP3_FIFO_START (HS_C1_I1_A1_EP2_FIFO_START + HS_C1_I1_A1_EP2_FIFO_NO) + #define HS_C1_I1_A1_EP3_FIFO_NO (HS_C1_I1_A1_EP3_BLKNO * HS_C1_I1_A1_EP3_BLKSIZE) + #define HS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP3_BLKNO - 1) << 2) | HS_C1_I1_A1_EP3_TYPE) + #define HS_C1_I1_A1_EP3_FIFO_MAP (((1 - HS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I1_A1_EP3_MAP (HS_C1_I1_A1_EP3_FIFO_START | (HS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP3_DIRECTION))) + #endif + #endif + + #if (HS_C1_I1_ALT_NUMBER == 1) + #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH) + #elif (HS_C1_I1_ALT_NUMBER == 2) + #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH + HS_C1_I1_A1_EP_LENGTH) + #endif + #endif + + #if (HS_C1_INTERFACE_NUMBER == 1) + #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH) + #elif (HS_C1_INTERFACE_NUMBER == 2) + #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH + HS_C1_I1_ALT_LENGTH) + #endif +#endif + +#if (FS_CONFIGURATION_NUMBER >= 1) + // Configuration 0X01 + #define FS_C1_INTERFACE_NUMBER 0X01 + #define FS_C1 0X01 + #define FS_C1_iConfiguration 0X00 + #define FS_C1_bmAttribute 0X80 + #define FS_C1_iMaxPower 0XFA + + #if (FS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #define FS_C1_I0_ALT_NUMBER 0X01 + #if (FS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0X00 + #define FS_C1_I0_A0_bInterfaceNumber 0X00 + #define FS_C1_I0_A0_bAlternateSetting 0X00 + //JWEI 2003/07/14 + //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT) + #define FS_C1_I0_A0_EP_NUMBER 0x05 + //#else + //#define FS_C1_I0_A0_EP_NUMBER 0X03 + //#endif + #if !(fFLASH_DISK && !fFLASH_BOOT) + #define FS_C1_I0_A0_bInterfaceClass 0XFF + #define FS_C1_I0_A0_bInterfaceSubClass 0X00 + #define FS_C1_I0_A0_bInterfaceProtocol 0X00 + #else + #define FS_C1_I0_A0_bInterfaceClass 0X08 + #define FS_C1_I0_A0_bInterfaceSubClass 0X06 + #define FS_C1_I0_A0_bInterfaceProtocol 0X50 + #endif + #define FS_C1_I0_A0_iInterface 0X00 + + #if (FS_C1_I0_A0_EP_NUMBER >= 1) + //EP0X01 + #define FS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE + //JWEI 2003/05/19 + #if fDOUBLE_BUF + #define FS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP1_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK + //JWEI 2003/05/07 + #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64 + #define FS_C1_I0_A0_EP1_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 2) + //EP0X02 + #define FS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE + //JWEI 2003/08/20 + #if fDOUBLE_BUF_IN + #define FS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP2_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN + #define FS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_64 + #define FS_C1_I0_A0_EP2_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 3) + //EP0X03 + #define FS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE + #define FS_C1_I0_A0_EP3_BLKNO SINGLE_BLK + #define FS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN + #define FS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT + #define FS_C1_I0_A0_EP3_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP3_bInterval 01 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + //EP0X04 + #define FS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE + #define FS_C1_I0_A0_EP4_BLKNO SINGLE_BLK + #define FS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP4_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP4_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP4_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 5) + //EP0X04 + #define FS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF_IN + #define FS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP5_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP5_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP5_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 6) + //EP0X04 + #define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF_IN + #define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP6_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP6_bInterval 00 + #endif + #endif + #endif +#endif + +#if (FS_CONFIGURATION_NUMBER >= 1) + // Configuration 1 + #if (FS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #if (FS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define FS_C1_I0_A0_EP_LENGTH (EP_LENGTH * FS_C1_I0_A0_EP_NUMBER) + #if (FS_C1_I0_A0_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I0_A0_EP1_FIFO_START FIFO0 + #define FS_C1_I0_A0_EP1_FIFO_NO (FS_C1_I0_A0_EP1_BLKNO * FS_C1_I0_A0_EP1_BLKSIZE) + #define FS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP1_BLKNO - 1) << 2) | FS_C1_I0_A0_EP1_TYPE) + #define FS_C1_I0_A0_EP1_FIFO_MAP (((1 - FS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I0_A0_EP1_MAP (FS_C1_I0_A0_EP1_FIFO_START | (FS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP1_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I0_A0_EP2_FIFO_START (FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO) + #define FS_C1_I0_A0_EP2_FIFO_NO (FS_C1_I0_A0_EP2_BLKNO * FS_C1_I0_A0_EP2_BLKSIZE) + #define FS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP2_BLKNO - 1) << 2) | FS_C1_I0_A0_EP2_TYPE) + #define FS_C1_I0_A0_EP2_FIFO_MAP (((1 - FS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I0_A0_EP2_MAP (FS_C1_I0_A0_EP2_FIFO_START | (FS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP2_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 3) + // EP3 + //JWEI 2003/07/15 + // #define FS_C1_I0_A0_EP3_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO) + #define FS_C1_I0_A0_EP3_FIFO_START FIFO14 + #define FS_C1_I0_A0_EP3_FIFO_NO (FS_C1_I0_A0_EP3_BLKNO * FS_C1_I0_A0_EP3_BLKSIZE) + #define FS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP3_BLKNO - 1) << 2) | FS_C1_I0_A0_EP3_TYPE) + #define FS_C1_I0_A0_EP3_FIFO_MAP (((1 - FS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I0_A0_EP3_MAP (FS_C1_I0_A0_EP3_FIFO_START | (FS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP3_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + // EP4 + #define FS_C1_I0_A0_EP4_FIFO_START (FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO) + #define FS_C1_I0_A0_EP4_FIFO_NO (FS_C1_I0_A0_EP4_BLKNO * FS_C1_I0_A0_EP4_BLKSIZE) + #define FS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP4_BLKNO - 1) << 2) | FS_C1_I0_A0_EP4_TYPE) + #define FS_C1_I0_A0_EP4_FIFO_MAP (((1 - FS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4) + #define FS_C1_I0_A0_EP4_MAP (FS_C1_I0_A0_EP4_FIFO_START | (FS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP4_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 5) + // EP5 + #define FS_C1_I0_A0_EP5_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO) + #define FS_C1_I0_A0_EP5_FIFO_NO (FS_C1_I0_A0_EP5_BLKNO * FS_C1_I0_A0_EP5_BLKSIZE) + #define FS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP5_BLKNO - 1) << 2) | FS_C1_I0_A0_EP5_TYPE) + #define FS_C1_I0_A0_EP5_FIFO_MAP (((1 - FS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5) + #define FS_C1_I0_A0_EP5_MAP (FS_C1_I0_A0_EP5_FIFO_START | (FS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP5_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 6) + // EP5 + #define FS_C1_I0_A0_EP6_FIFO_START (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO) + #define FS_C1_I0_A0_EP6_FIFO_NO (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE) + #define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE) + #define FS_C1_I0_A0_EP6_FIFO_MAP (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6) + #define FS_C1_I0_A0_EP6_MAP (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION))) + #endif + #endif + + #if (FS_C1_I0_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define FS_C1_I0_A1_EP_LENGTH (EP_LENGTH * FS_C1_I0_A1_EP_NUMBER) + #if (FS_C1_I0_A1_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I0_A1_EP1_FIFO_START FIFO0 + #define FS_C1_I0_A1_EP1_FIFO_NO (FS_C1_I0_A1_EP1_BLKNO * FS_C1_I0_A1_EP1_BLKSIZE) + #define FS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP1_BLKNO - 1) << 2) | FS_C1_I0_A1_EP1_TYPE) + #define FS_C1_I0_A1_EP1_FIFO_MAP (((1 - FS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I0_A1_EP1_MAP (FS_C1_I0_A1_EP1_FIFO_START | (FS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP1_DIRECTION))) + #endif + #if (FS_C1_I0_A1_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I0_A1_EP2_FIFO_START (FS_C1_I0_A1_EP1_FIFO_START + FS_C1_I0_A1_EP1_FIFO_NO) + #define FS_C1_I0_A1_EP2_FIFO_NO (FS_C1_I0_A1_EP2_BLKNO * FS_C1_I0_A1_EP2_BLKSIZE) + #define FS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP2_BLKNO - 1) << 2) | FS_C1_I0_A1_EP2_TYPE) + #define FS_C1_I0_A1_EP2_FIFO_MAP (((1 - FS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I0_A1_EP2_MAP (FS_C1_I0_A1_EP2_FIFO_START | (FS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP2_DIRECTION))) + #endif + #if (FS_C1_I0_A1_EP_NUMBER >= 3) + // EP3 + #define FS_C1_I0_A1_EP3_FIFO_START (FS_C1_I0_A1_EP2_FIFO_START + FS_C1_I0_A1_EP2_FIFO_NO) + #define FS_C1_I0_A1_EP3_FIFO_NO (FS_C1_I0_A1_EP3_BLKNO * FS_C1_I0_A1_EP3_BLKSIZE) + #define FS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP3_BLKNO - 1) << 2) | FS_C1_I0_A1_EP3_TYPE) + #define FS_C1_I0_A1_EP3_FIFO_MAP (((1 - FS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I0_A1_EP3_MAP (FS_C1_I0_A1_EP3_FIFO_START | (FS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP3_DIRECTION))) + #endif + #endif + + #if (FS_C1_I0_ALT_NUMBER == 1) + #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH) + #elif (FS_C1_I0_ALT_NUMBER == 2) + #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH + FS_C1_I0_A1_EP_LENGTH) + #endif + #endif + + #if (FS_C1_INTERFACE_NUMBER >= 2) + // Interface 1 + #if (FS_C1_I1_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define FS_C1_I1_A0_EP_LENGTH (EP_LENGTH * FS_C1_I1_A0_EP_NUMBER) + #if (FS_C1_I1_A0_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I1_A0_EP1_FIFO_START FIFO0 + #define FS_C1_I1_A0_EP1_FIFO_NO (FS_C1_I1_A0_EP1_BLKNO * FS_C1_I1_A0_EP1_BLKSIZE) + #define FS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP1_BLKNO - 1) << 2) | FS_C1_I1_A0_EP1_TYPE) + #define FS_C1_I1_A0_EP1_FIFO_MAP (((1 - FS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I1_A0_EP1_MAP (FS_C1_I1_A0_EP1_FIFO_START | (FS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP1_DIRECTION))) + #endif + #if (FS_C1_I1_A0_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I1_A0_EP2_FIFO_START (FS_C1_I1_A0_EP1_FIFO_START + FS_C1_I1_A0_EP1_FIFO_NO) + #define FS_C1_I1_A0_EP2_FIFO_NO (FS_C1_I1_A0_EP2_BLKNO * FS_C1_I1_A0_EP2_BLKSIZE) + #define FS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP2_BLKNO - 1) << 2) | FS_C1_I1_A0_EP2_TYPE) + #define FS_C1_I1_A0_EP2_FIFO_MAP (((1 - FS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I1_A0_EP2_MAP (FS_C1_I1_A0_EP2_FIFO_START | (FS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP2_DIRECTION))) + #endif + #if (FS_C1_I1_A0_EP_NUMBER >= 3) + // EP3 + #define FS_C1_I1_A0_EP3_FIFO_START (FS_C1_I1_A0_EP2_FIFO_START + FS_C1_I1_A0_EP2_FIFO_NO) + #define FS_C1_I1_A0_EP3_FIFO_NO (FS_C1_I1_A0_EP3_BLKNO * FS_C1_I1_A0_EP3_BLKSIZE) + #define FS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP3_BLKNO - 1) << 2) | FS_C1_I1_A0_EP3_TYPE) + #define FS_C1_I1_A0_EP3_FIFO_MAP (((1 - FS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I1_A0_EP3_MAP (FS_C1_I1_A0_EP3_FIFO_START | (FS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP3_DIRECTION))) + #endif + #endif + + #if (FS_C1_I1_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define FS_C1_I1_A1_EP_LENGTH (EP_LENGTH * FS_C1_I1_A1_EP_NUMBER) + #if (FS_C1_I1_A1_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I1_A1_EP1_FIFO_START FIFO0 + #define FS_C1_I1_A1_EP1_FIFO_NO (FS_C1_I1_A1_EP1_BLKNO * FS_C1_I1_A1_EP1_BLKSIZE) + #define FS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP1_BLKNO - 1) << 2) | FS_C1_I1_A1_EP1_TYPE) + #define FS_C1_I1_A1_EP1_FIFO_MAP (((1 - FS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I1_A1_EP1_MAP (FS_C1_I1_A1_EP1_FIFO_START | (FS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP1_DIRECTION))) + #endif + #if (FS_C1_I1_A1_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I1_A1_EP2_FIFO_START (FS_C1_I1_A1_EP1_FIFO_START + FS_C1_I1_A1_EP1_FIFO_NO) + #define FS_C1_I1_A1_EP2_FIFO_NO (FS_C1_I1_A1_EP2_BLKNO * FS_C1_I1_A1_EP2_BLKSIZE) + #define FS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP2_BLKNO - 1) << 2) | FS_C1_I1_A1_EP2_TYPE) + #define FS_C1_I1_A1_EP2_FIFO_MAP (((1 - FS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I1_A1_EP2_MAP (FS_C1_I1_A1_EP2_FIFO_START | (FS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP2_DIRECTION))) + #endif + #if (FS_C1_I1_A1_EP_NUMBER >= 3) + // EP3 + #define FS_C1_I1_A1_EP3_FIFO_START (FS_C1_I1_A1_EP2_FIFO_START + FS_C1_I1_A1_EP2_FIFO_NO) + #define FS_C1_I1_A1_EP3_FIFO_NO (FS_C1_I1_A1_EP3_BLKNO * FS_C1_I1_A1_EP3_BLKSIZE) + #define FS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP3_BLKNO - 1) << 2) | FS_C1_I1_A1_EP3_TYPE) + #define FS_C1_I1_A1_EP3_FIFO_MAP (((1 - FS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I1_A1_EP3_MAP (FS_C1_I1_A1_EP3_FIFO_START | (FS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP3_DIRECTION))) + #endif + #endif + + #if (FS_C1_I1_ALT_NUMBER == 1) + #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH) + #elif (FS_C1_I1_ALT_NUMBER == 2) + #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH + FS_C1_I1_A1_EP_LENGTH) + #endif + #endif + + #if (FS_C1_INTERFACE_NUMBER == 1) + #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH) + #elif (FS_C1_INTERFACE_NUMBER == 2) + #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH + HS_FS_C1_I1_ALT_LENGTH) + #endif +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable + +#define USB_DISABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable + +#define USB_UP_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))) // upQ stream mode + +#define USB_UP_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3)) // upQ packet mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1)) // lp downstream DMA enable + +#define USB_DISABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))) // lp downstream DMA disable + +#define USB_LP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT6))) // lpQ packet mode + +#define USB_LP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)) // lpQ stream mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable + +#define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable + +#define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7))) // hpQ packet mode + +#define USB_HP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7)) // hpQ stream mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable + +#define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable + +#define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10))) // hpQ packet mode + +#define USB_MP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10)) // hpQ stream mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define USB_ENABLE_UP_PACKET_MODE() USB_DISABLE_UP_DMA(); \ + USB_UP_PACKET_MODE(); \ + USB_ENABLE_UP_DMA(); + +#define USB_ENABLE_LP_DN_PACKET_MODE() USB_DISABLE_LP_DN_DMA(); \ + USB_LP_DN_PACKET_MODE(); \ + USB_ENABLE_LP_DN_DMA() + +#define USB_ENABLE_MP_DN_PACKET_MODE() USB_DISABLE_MP_DN_DMA(); \ + USB_MP_DN_PACKET_MODE(); \ + USB_ENABLE_MP_DN_DMA(); + +#define USB_ENABLE_HP_DN_PACKET_MODE() USB_DISABLE_HP_DN_DMA(); \ + USB_HP_DN_PACKET_MODE(); \ + USB_ENABLE_HP_DN_DMA(); + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_UP_STREAM_MODE() USB_DISABLE_UP_DMA(); \ + USB_UP_STREAM_MODE(); \ + USB_ENABLE_UP_DMA(); + +#define USB_ENABLE_LP_DN_STREAM_MODE() USB_DISABLE_LP_DN_DMA(); \ + USB_LP_DN_STREAM_MODE(); \ + USB_ENABLE_LP_DN_DMA() + +#define USB_ENABLE_MP_DN_STREAM_MODE() USB_DISABLE_MP_DN_DMA(); \ + USB_MP_DN_STREAM_MODE(); \ + USB_ENABLE_MP_DN_DMA(); + +#define USB_ENABLE_HP_DN_STREAM_MODE() USB_DISABLE_HP_DN_DMA(); \ + USB_HP_DN_STREAM_MODE(); \ + USB_ENABLE_HP_DN_DMA(); + +#define USB_STREAM_HOST_BUF_SIZE(size) USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size))); +#define USB_STREAM_TIMEOUT(time_cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt); // set stream mode timeout critirea +#define USB_STREAM_AGG_PKT_CNT(cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_extr.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_extr.h new file mode 100755 index 0000000..1886800 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_extr.h @@ -0,0 +1,34 @@ +#ifndef USB_EXTR_H +#define USB_EXTR_H + +#if 0 +#include "dt_defs.h" +#include "usb_type.h" + +/* Variable for USB EP0 pipe (USB.c) */ +uint16_t *pu8DescriptorEX; +uint16_t u16TxRxCounter; +uint16_t *u8ConfigDescriptorEX; +//extern BOOLEAN bUsbEP0HaltSt; +Action eUsbCxFinishAction; +CommandType eUsbCxCommand; +BOOLEAN UsbChirpFinish; +uint16_t u8UsbConfigValue; +uint16_t u8UsbInterfaceValue; +uint16_t u8UsbInterfaceAlternateSetting; +uint16_t u16FirmwareComplete; + +uint16_t *UsbDeviceDescriptor; +uint16_t *String00Descriptor; +uint16_t *String10Descriptor; +uint16_t *String20Descriptor; +uint16_t *String30Descriptor; +uint16_t *u8DeviceQualifierDescriptorEX; +uint16_t *u8OtherSpeedConfigDescriptorEX; +uint16_t *u8UsbDeviceDescriptor; +uint16_t *u8String00Descriptor; +uint16_t *u8String10Descriptor; +uint16_t *u8String20Descriptor; +uint16_t *u8String30Descriptor; +#endif +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_pre.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_pre.h new file mode 100755 index 0000000..b63e3a9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_pre.h @@ -0,0 +1,99 @@ +#ifndef __USB_USER_PRE_H +#define __USB_USER_PRE_H + +#define FUSB200_MAX_EP 10 // 1..10 +#define FUSB200_MAX_FIFO 10 // 0.. 9 +#define EP0MAXPACKETSIZE 0x40 +// #define EP0FIFOSIZE 64 // EP0_FIFO +//JWEI 2003/04/29 +//#define EP0MAXPACKETSIZE 0x08 + +// Max. Packet Size define +#define MX_PA_SZ_8 8 +#define MX_PA_SZ_16 16 +#define MX_PA_SZ_32 32 +#define MX_PA_SZ_64 64 +#define MX_PA_SZ_128 128 +#define MX_PA_SZ_256 256 +#define MX_PA_SZ_512 512 +#define MX_PA_SZ_1024 1024 + +#define MASK_F0 0xF0 + +// Block Size define +#define BLK512BYTE 1 +#define BLK1024BYTE 2 + +#define BLK64BYTE 1 +#define BLK128BYTE 2 + +// Block toggle number define +#define SINGLE_BLK 1 +#define DOUBLE_BLK 2 +#define TRIBLE_BLK 3 + +// Endpoint transfer type +#define TF_TYPE_ISOCHRONOUS 1 +#define TF_TYPE_BULK 2 +#define TF_TYPE_INTERRUPT 3 + +// Endpoint or FIFO direction define +#define DIRECTION_IN 0 +#define DIRECTION_OUT 1 + +// FIFO number define +#define FIFO0 0x0 +#define FIFO1 0x1 +#define FIFO2 0x2 +#define FIFO3 0x3 +#define FIFO4 0x4 +#define FIFO5 0x5 +#define FIFO6 0x6 +#define FIFO7 0x7 +#define FIFO8 0x8 +#define FIFO9 0x9 +#define FIFO10 10 +#define FIFO11 11 +#define FIFO12 12 +#define FIFO13 13 +#define FIFO14 14 +#define FIFO15 15 + +// Descriptor Table uses the following parameters : fixed +#define DEVICE_LENGTH 0x12 +#define CONFIG_LENGTH 0x09 +#define INTERFACE_LENGTH 0x09 +#define EP_LENGTH 0x07 +#define DEVICE_QUALIFIER_LENGTH 0x0A + +//JWEI 2003/04/29 +// Endpoint number define +#define EP0 0 +#define EP1 1 +#define EP2 2 +#define EP3 3 +#define EP4 4 +#define EP5 5 +#define EP6 6 +#define EP7 7 +#define EP8 8 +#define EP9 9 +#define EP10 10 +#define EP11 11 +#define EP12 12 +#define EP13 13 +#define EP14 14 +#define EP15 15 + +#define STRING_00_LENGTH 0x04 +#define STRING_10_LENGTH 0x0c +#define STRING_20_LENGTH 0x18 +#define STRING_30_LENGTH 0x18 +#define STRING_40_LENGTH 0x04 +#define STRING_50_LENGTH 0x04 +#define STRING_60_LENGTH 0x04 +#define STRING_70_LENGTH 0x04 +#define STRING_80_LENGTH 0x04 +#define STRING_90_LENGTH 0x00 + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_std.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_std.h new file mode 100755 index 0000000..7272eaf --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_std.h @@ -0,0 +1,106 @@ +#ifndef USB_STD_H +#define USB_STD_H + +#define mDEV_REQ_REQ_DIR() (ControlCmd.Direction) +#define mDEV_REQ_REQ_TYPE() (ControlCmd.Type) +#define mDEV_REQ_REQ_RECI() (ControlCmd.Object) +#define mDEV_REQ_REQ() (ControlCmd.Request) +#define mDEV_REQ_VALUE() (ControlCmd.Value) +#define mDEV_REQ_VALUE_LOW() (mLOW_BYTE(mDEV_REQ_VALUE())) +#define mDEV_REQ_VALUE_HIGH() (mHIGH_BYTE(mDEV_REQ_VALUE())) +#define mDEV_REQ_INDEX() (ControlCmd.Index) +#define mDEV_REQ_LENGTH() (ControlCmd.Length) + +/******************** USB Protocol Definition *************************/ +/* Standard Request Code (Table 9-4) */ +#define USB_GET_STATUS 0 +#define USB_CLEAR_FEATURE 1 +#define USB_SET_FEATURE 3 +#define USB_SET_ADDRESS 5 +#define USB_GET_DESCRIPTOR 6 +#define USB_SET_DESCRIPTOR 7 +#define USB_GET_CONFIGURATION 8 +#define USB_SET_CONFIGURATION 9 +#define USB_GET_INTERFACE 10 +#define USB_SET_INTERFACE 11 +#define USB_SYNCH_FRAME 12 + +/* Descriptor Type (Table 9-5) */ +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIG 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 + +/* Endpoint Attribute (Table 9-10) */ +#define USB_EP_ATTR_CTRL 0 +#define USB_EP_ATTR_ISOCH 1 +#define USB_EP_ATTR_BULK 2 +#define USB_EP_ATTR_INTRPT 3 + +/*********************** for USB 2.0 **********************************/ +// Table 9-5. Descriptor Types +#define DT_DEVICE 1 +#define DT_CONFIGURATION 2 +#define DT_STRING 3 +#define DT_INTERFACE 4 +#define DT_ENDPOINT 5 +#define DT_DEVICE_QUALIFIER 6 +#define DT_OTHER_SPEED_CONFIGURATION 7 +#define DT_INTERFACE_POWER 8 + +/**********************************************************************/ +// Values for bmAttributes Field in USB_CONFIGURATION_DESCRIPTOR +#define USB_BUS_POWERED 0x80 +#define USB_SELF_POWERED 0x40 +#define USB_REMOTE_WAKEUP 0x20 + +#define cUSB_REQTYPE_DIR_POS 7 +#define cUSB_REQTYPE_DIR_LEN 1 +#define cUSB_REQTYPE_TYPE_POS 5 +#define cUSB_REQTYPE_TYPE_LEN 2 +#define cUSB_REQTYPE_RX_POS 0 +#define cUSB_REQTYPE_RX_LEN 5 + +/* for USB State */ +#define cUSB_DEFAULT_STATE 0 +#define cUSB_ADDRESS_STATE 1 +#define cUSB_CONFIG_STATE 2 + +/* for Data transfer direction */ +#define bmUSB_HOST_DIR 7 /* Bit 7 */ +#define cUSB_DIR_HOST_OUT 0 +#define cUSB_DIR_HOST_IN 1 + +/* for Type */ +#define cUSB_REQTYPE_STD 0 +#define cUSB_REQTYPE_CLASS 1 +#define cUSB_REQTYPE_VENDOR 2 + +/* for Recipient */ +#define cUSB_REQTYPE_DEVICE 0 +#define cUSB_REQTYPE_INTERFACE 1 +#define cUSB_REQTYPE_ENDPOINT 2 +#define cUSB_REQTYPE_OTHER 3 + +/* for Descriptor Type */ +#define cUSB_DESTYPE_DEVICE 1 +#define cUSB_DESTYPE_CONFIG 2 +#define cUSB_DESTYPE_STRING 3 +#define cUSB_DESTYPE_INTERFACE 4 +#define cUSB_DESTYPE_ENDPOINT 5 +#define cUSB_DESTYPE_END cUSB_DESTYPE_ENDPOINT // for range check + +/* for Feature selector */ +#define cUSB_FEATSEL_RMWAKEUP 0 +#define cUSB_FEATSEL_EPHAL 1 +#define cUSB_FEATSEL_END cUSB_FEATSEL_EPHAL // for range check + +#define bmREQ_RECI 0 +#define bmwREQ_RECI 5 // mMASKS(bmwREQ_RECI, bmREQ_RECI) +#define bmREQ_TYPE 5 +#define bmwREQ_TYPE 2 // mMASKS(bmwREQ_TYPE, bmREQ_TYPE) +#define bmREQ_DIR 7 +#define bmwREQ_DIR 1 + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_table.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_table.h new file mode 100755 index 0000000..31fe7e4 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_table.h @@ -0,0 +1,131 @@ +#ifndef _USB_TABLE_H_ +#define _USB_TABLE_H_ + +// UsbDeviceDescriptor +#define USB_DEVICE_DESC_TYPE 0x01 +#define USB_DEVICE_DESC_LEN 0x12 +#define USB_SPEC_VERSION 0x0200 +#define USB_DEVICE_CLASS 0xFF +#define USB_DEVICE_SUB_CLASS 0xFF +#define USB_DEVICE_PROTOCOL 0xFF +#define USB_MAX_PKT_SIZE 0x40 +#define USB_VENDOR_ID 0x0CF3 +#define USB_PRODUCT_ID 0x7010 +#define USB_DEVICE_BCD BOOTROM_VER +#define USB_MANUFACTURER_INDEX 0x10 +#define USB_PRODUCT_INDEX 0x20 +#define USB_SERIAL_INDEX 0x30 +#define USB_CONFIGURATION_NUM 0x01 +// end UsbDeviceDescriptor + +#define USB_CONFIG_DESC_TYPE 0x02 +#define USB_CONFIG_DESC_LEN 0x09 +//#define USB_TOTAL_DESC_LEN 0x002E // 4 ep +//#define USB_TOTAL_DESC_LEN 0x0035 // 5 ep +#define USB_TOTAL_DESC_LEN 0x003C // 6 ep +#define USB_INTERFACE_NUM 0x01 +#define USB_CONFIG_NUM 0x01 +#define USB_STRING_INDEX 0x00 +#define USB_ATTRIBUTE 0x80 +#define USB_MAX_POWER 0xFA + +#define USB_INTERFACE_DESC_TYPE 0x04 +#define USB_INTERFACE_DESC_LEN 0x09 +#define USB_INTERFACE_INDEX_NUM 0x00 +#define USB_INTERFACE_ALT_SETTING 0x00 +//#define USB_INTERFACE_EP_NUM 0x04 +//#define USB_INTERFACE_EP_NUM 0x05 +#define USB_INTERFACE_EP_NUM 0x06 +#define USB_INTERFACE_CLASS 0xFF +#define USB_INTERFACE_SUB_CLASS 0x00 +#define USB_INTERFACE_PROTOCOL 0x00 +#define USB_INTERFACE_STRING_INDEX 0x00 + +#define USB_EP_DESC_TYPE 0x05 +#define USB_EP_DESC_LEN 0x07 + +/* USB Endpoint attribute */ +#define bUSB_EP1_NUM 0x01 +#define bUSB_EP2_NUM 0x02 +#define bUSB_EP3_NUM 0x03 +#define bUSB_EP4_NUM 0x04 +#define bUSB_EP5_NUM 0x05 +#define bUSB_EP6_NUM 0x06 + +#define bUSB_EP_DIRECTION_IN 0x80 +#define bUSB_EP_DIRECTION_OUT 0x00 + +#define bUSB_EP_TYPE_CONTROL 0x00 +#define bUSB_EP_TYPE_ISOCHRONOUS 0x01 +#define bUSB_EP_TYPE_BULK 0x02 +#define bUSB_EP_TYPE_INTERRUPT 0x03 + +#define bUSB_EP_MAX_PKT_SIZE_64 0x0040 +#define bUSB_EP_MAX_PKT_SIZE_512 0x0200 + +/* High Speed Endpoint */ +#define USB_HS_EP1_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP1_NUM) +#define USB_HS_EP1_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP1_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP1_INTERVAL 0x00 + +#define USB_HS_EP2_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP2_NUM) +#define USB_HS_EP2_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP2_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP2_INTERVAL 0x00 + +#define USB_HS_EP3_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP3_NUM) +#define USB_HS_EP3_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT +#define USB_HS_EP3_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_HS_EP3_INTERVAL 0x01 + +#define USB_HS_EP4_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP4_NUM) +#define USB_HS_EP4_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT //bUSB_EP_TYPE_BULK +#define USB_HS_EP4_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_HS_EP4_INTERVAL 0x01 //0x00 + +#define USB_HS_EP5_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP5_NUM) +#define USB_HS_EP5_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP5_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP5_INTERVAL 0x00 + +#define USB_HS_EP6_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP6_NUM) +#define USB_HS_EP6_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP6_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP6_INTERVAL 0x00 + +/* Full Speed Endpoint */ +#define USB_FS_EP1_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP1_NUM) +#define USB_FS_EP1_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP1_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP1_INTERVAL 0x00 + +#define USB_FS_EP2_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP2_NUM) +#define USB_FS_EP2_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP2_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP2_INTERVAL 0x00 + +#define USB_FS_EP3_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP3_NUM) +#define USB_FS_EP3_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT +#define USB_FS_EP3_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP3_INTERVAL 0x01 + +#define USB_FS_EP4_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP4_NUM) +#define USB_FS_EP4_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP4_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP4_INTERVAL 0x00 + +#define USB_FS_EP5_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP5_NUM) +#define USB_FS_EP5_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP5_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP5_INTERVAL 0x00 + +#define USB_FS_EP6_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP6_NUM) +#define USB_FS_EP6_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP6_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP6_INTERVAL 0x00 + +//#define USB_QUALIFIER_DESC_ADDR 0x8cff00 +//#define USB_OTHER_SPEED_DESC_ADDR 0x8cffA + +#endif // end of _USB_TABLE_H_ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_type.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_type.h new file mode 100755 index 0000000..7e31478 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usb_type.h @@ -0,0 +1,60 @@ +#ifndef USB_TYPE_H +#define USB_TYPE_H + +#include "dt_defs.h" + +/*********************** for Faraday USB controller *******************/ +typedef enum +{ + CMD_VOID, // No command + CMD_GET_DESCRIPTOR, // Get_Descriptor command + CMD_SET_DESCRIPTOR // Set_Descriptor command +} CommandType; + +typedef enum +{ + ACT_IDLE, + ACT_DONE, + ACT_STALL +} Action; + +typedef struct Setup_Packet +{ + uint8_t Direction; /* Data transfer direction: IN, OUT */ + uint8_t Type; /* Request Type: Standard, Class, Vendor */ + uint8_t Object; /* Recipient: Device, Interface, Endpoint,other */ + uint16_t Request; /* Refer to Table 9-3 */ + uint16_t Value; + uint16_t Index; + uint16_t Length; +} SetupPacket; + +#define mBIT(b) (1 << (b)) +#define mMASK(w) (mBIT(w) - 1) + +#define mWORD_IDX(bsize) ((bsize) >> 1) +#define mWORD_SIZE(bsize) (((bsize) + 1) >> 1) + +#define mTABLE_WID mWORD_SIZE +#define mTABLE_IDX mWORD_IDX +#define mTABLE_LEN mLOW_BYTE + +#define mLOW_MASK(u16) ((uint8_t) ((u16) & mMASK(8))) +#define mHIGH_MASK(u16) ((uint8_t) ((u16) & ~mMASK(8))) +#define mLOW2HIGH(u16) (((uint8_t) (u16)) << 8) + +/* (1234) -> 0034 */ +//#define mLOW_BYTE(u16) ((U_8)(u16)) +#define mLOW_BYTE(u16) mLOW_MASK(u16) +/* (1234) -> 0012 */ +#define mHIGH_BYTE(u16) ((uint8_t) (((uint16_t) (u16)) >> 8)) + +#define mGET_REG1(var0, reg0) { var0 = reg0; } + +/* (1234, 5678) -> 7834 */ +#define m2BYTE(ch1L, ch2H) (mLOW_MASK(ch1L) | mLOW2HIGH(ch2H)) + +#define mREAD_WORD(var0, reg0, reg1) \ + { var0 = reg0; var0 += mLOW2HIGH(reg1); } + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usbfifo_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usbfifo_api.h new file mode 100755 index 0000000..08c4644 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/usbfifo_api.h @@ -0,0 +1,43 @@ +/* + * @File: HIF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _USB_FIFO_API_H +#define _USB_FIFO_API_H + +#include "vbuf_api.h" + +typedef struct _USB_FIFO_CONFIG { + /* callback to get the buf for receiving commands from USB FIFO */ + VBUF* (*get_command_buf)(void); + /* callback when receiving a command */ + void (*recv_command)(VBUF *cmd); + /* callback to get the buf for event to send to the host */ + VBUF* (*get_event_buf)(void); + /* callback to indicate the event has been sent to the host */ + void (*send_event_done)(VBUF *buf); + + /* context used for all callbacks */ + //void *context; +} USB_FIFO_CONFIG; + +/* hardware API table structure (API descriptions below) */ +struct usbfifo_api { + void (*_init)(USB_FIFO_CONFIG *pConfig); + void (*_enable_event_isr)(void); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void usbfifo_module_install(struct usbfifo_api *apis); + +#endif /* #ifndef _USB_FIFO_API_H */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/vbuf_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/vbuf_api.h new file mode 100755 index 0000000..6119eb5 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/vbuf_api.h @@ -0,0 +1,46 @@ +/* + * @File: VBUF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _VBUF_API_H +#define _VBUF_API_H + +#include + +#define MAX_BUF_CTX_LEN 20 + +typedef struct _VBUF +{ + VDESC *desc_list; + struct _VBUF *next_buf; + A_UINT16 buf_length; + A_UINT8 reserved[2]; + A_UINT8 ctx[MAX_BUF_CTX_LEN]; + //A_UINT8 end_point; + //A_UINT8 reserved[1]; +} VBUF; + +#define VBUF_GET_DATA_ADDR(vbuf) (vbuf->desc_list->buf_addr + vbuf->desc_list->data_offset) + +/* hardware API table structure (API descriptions below) */ +struct vbuf_api { + void (*_init)(int nBuf); + VBUF* (*_alloc_vbuf)(void); + VBUF* (*_alloc_vbuf_with_size)(int size, int reserve); + void (*_free_vbuf)(VBUF *buf); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void vbuf_module_install(struct vbuf_api *apis); + +#endif /* #ifndef _HIF_API_H */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/vdesc_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/vdesc_api.h new file mode 100755 index 0000000..631f134 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/vdesc_api.h @@ -0,0 +1,46 @@ +/* + * @File: VBUF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _VDESC_API_H +#define _VDESC_API_H + +//#define VDESC_CONTROL_BUF_HDR (1 << 6) /* the buffer was manipulated and a header added */ + +#define MAX_HW_DESC_SIZE 20 + +typedef struct _VDESC +{ + struct _VDESC *next_desc; + A_UINT8 *buf_addr; + A_UINT16 buf_size; + A_UINT16 data_offset; + A_UINT16 data_size; + A_UINT16 control; + A_UINT8 hw_desc_buf[MAX_HW_DESC_SIZE]; +} VDESC; + +//#define VDESC_HW_TO_VDESC(hwdesc) ((VDESC *)(((A_UINT32 *)hwdesc - 4))) +#define VDESC_HW_TO_VDESC(hwdesc) ((VDESC *)(((A_UINT32 *)hwdesc - 4))) + +struct vdesc_api { + void (*_init)(int nDesc); + VDESC* (*_alloc_vdesc)(); + A_UINT8* (*_get_hw_desc)(VDESC *desc); + void (*_swap_vdesc)(VDESC *dest, VDESC *src); + //void (*_free_vdesc)(void); + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void vdesc_module_install(struct vdesc_api *apis); + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/wdt_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/wdt_api.h new file mode 100755 index 0000000..f480590 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/inc/wdt_api.h @@ -0,0 +1,56 @@ +#ifndef __WDT_API_H__ +#define __WDT_API_H__ +/* + * + */ + +typedef enum { + WDT_ACTION_NO = 0, // bit1, bit0: 00 + WDT_ACTION_INTR, // bit1, bit0: 01 + WDT_ACTION_NMI, // bit1, bit0: 10 + WDT_ACTION_RESET, // bit1, bit0: 11 + + WDT_ACTION_UNKNOWN +}T_WDT_ACTION_TYPE; + + +typedef enum { + WDT_TIMEOUT = 1, + WDT_ACTION, + + WDT_UNKNOWN +}T_WDT_CMD_TYPE; + +typedef struct { + uint32_t cmd; + union { + uint32_t timeout; + uint32_t action; + }; +}T_WDT_CMD; + + +typedef enum{ + ENUM_WDT_BOOT = 1, + ENUM_COLD_BOOT, + ENUM_SUSP_BOOT, + + // add above here + ENUM_UNKNOWN_BOOT +}T_BOOT_TYPE; + + +/*!- interface of watchdog timer + * + */ +struct wdt_api { + void (* _wdt_init)(void); + void (* _wdt_enable)(void); + void (* _wdt_disable)(void); + void (* _wdt_set)(T_WDT_CMD); + void (* _wdt_task)(void); + void (* _wdt_reset)(void); + T_BOOT_TYPE (*_wdt_last_boot)(void); +}; +#endif /* __WDT_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/lib/ram/dummy.txt b/target_firmware/magpie_fw_dev/build/magpie_1_1/lib/ram/dummy.txt new file mode 100755 index 0000000..e69de29 diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/lib/rom/dummy.txt b/target_firmware/magpie_fw_dev/build/magpie_1_1/lib/rom/dummy.txt new file mode 100755 index 0000000..e69de29 diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/lib/sboot/dummy.txt b/target_firmware/magpie_fw_dev/build/magpie_1_1/lib/sboot/dummy.txt new file mode 100755 index 0000000..e69de29 diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/adf/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/adf/Makefile new file mode 100755 index 0000000..eee2bb6 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/adf/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = adf + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(LAYERNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +# export SSOBJPATH = $(PRJ_ROOT)/build/$(TARGET)/$(LAYERNAME)/obj + + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/obj + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . +#DIRS = net os nbuf + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libadf.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/adf/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/adf/Makefile.ss new file mode 100755 index 0000000..8611c2a --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/adf/Makefile.ss @@ -0,0 +1,48 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/adf_nbuf.o \ + $(SSOBJPATH)/adf_net.o \ + $(SSOBJPATH)/adf_os_defer_pvt.o \ + $(SSOBJPATH)/adf_os_dma.o \ + $(SSOBJPATH)/adf_os_irq_pvt.o \ + $(SSOBJPATH)/adf_os_timer.o + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/carrier_apd/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/carrier_apd/Makefile new file mode 100755 index 0000000..c0eedf6 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/carrier_apd/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = carrier_apd +export SLAYERNAME = ../wlan + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/$(SLAYERNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +# export SSOBJPATH = $(PRJ_ROOT)/build/$(TARGET)/$(LAYERNAME)/usb/obj + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SLAYERNAME)/$(SSNAME)/obj + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcarrier_apd.a + + +# +# Targets +# + +all: + echo $(SSOBJPATH) + echo $(SSMPATH) + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/carrier_apd/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/carrier_apd/Makefile.ss new file mode 100755 index 0000000..bef6db9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/carrier_apd/Makefile.ss @@ -0,0 +1,53 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/ah.o \ + $(SSOBJPATH)/ar5416_hw.o \ + $(SSOBJPATH)/ar5416_phy.o \ + $(SSOBJPATH)/ah_osdep.o \ + $(SSOBJPATH)/if_ath.o \ + $(SSOBJPATH)/if_ath_pci.o \ + $(SSOBJPATH)/if_owl.o \ + $(SSOBJPATH)/ieee80211_output.o \ + $(SSOBJPATH)/ar5416Phy.o \ + $(SSOBJPATH)/ratectrl_11n_ln.o + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/cmnos/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/cmnos/Makefile new file mode 100755 index 0000000..cf1f8fc --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/cmnos/Makefile @@ -0,0 +1,57 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = cmnos + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(LAYERNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +# export SSOBJPATH = $(PRJ_ROOT)/build/$(TARGET)/$(LAYERNAME)/obj +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/obj + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . +#DIRS = dbg sflash + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/cmnos/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/cmnos/Makefile.ss new file mode 100755 index 0000000..24730ba --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/cmnos/Makefile.ss @@ -0,0 +1,46 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/dbg_api.o \ + $(SSOBJPATH)/cmnos_sflash.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/init/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/init/Makefile new file mode 100755 index 0000000..81da922 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/init/Makefile @@ -0,0 +1,60 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = ram +export SSNAME = init + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libinit.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/init/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/init/Makefile.ss new file mode 100755 index 0000000..318ee59 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/init/Makefile.ss @@ -0,0 +1,47 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/app_start.o \ + $(SSOBJPATH)/init.o \ + $(SSOBJPATH)/magpie.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/rompatch/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/rompatch/Makefile new file mode 100755 index 0000000..c1cf094 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/rompatch/Makefile @@ -0,0 +1,59 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = rompatch + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(LAYERNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/obj + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . +#DIRS = hif cmnos + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/librompatch.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/rompatch/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/rompatch/Makefile.ss new file mode 100755 index 0000000..1155799 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/rompatch/Makefile.ss @@ -0,0 +1,47 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_clock_patch.o \ + $(SSOBJPATH)/usb_api_patch.o \ + $(SSOBJPATH)/HIF_usb_patch.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wlan/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wlan/Makefile new file mode 100755 index 0000000..c05e4e9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wlan/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = ram +export SSNAME = wlan + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libwlan.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wlan/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wlan/Makefile.ss new file mode 100755 index 0000000..64e447f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wlan/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/wlan_pci.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wmi/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wmi/Makefile new file mode 100755 index 0000000..6a3704f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wmi/Makefile @@ -0,0 +1,59 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export SSNAME = wmi + + +# +# Sub-system source main path +# + +export SSMPATH = $(MAGPIE_ROOT)/target/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libwmi.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wmi/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wmi/Makefile.ss new file mode 100755 index 0000000..e39e737 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/ram/wmi/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH) + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/wmi_svc.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/Makefile new file mode 100755 index 0000000..5871553 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/Makefile @@ -0,0 +1,58 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = adf + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +# export SSOBJPATH = $(PRJ_ROOT)/build/$(TARGET)/$(LAYERNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +DIRS = nbuf + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libadf.a + + +# +# Targets +# + +all : + for i in $(DIRS) ; do $(MAKE) -C $$i all || exit $? ; done + #ar -rcs $(L_TARGET) `find . -name "*.o"` + +dep: + for i in $(DIRS) ; do $(MAKE) -C $$i dep || exit $? ; done + +clean: + for i in $(DIRS) ; do $(MAKE) -C $$i clean; done + +init: + for i in $(DIRS) ; do $(MAKE) -C $$i init; done + + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/nbuf/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/nbuf/Makefile new file mode 100755 index 0000000..e0ab54f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/nbuf/Makefile @@ -0,0 +1,59 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = adf +export SSNAME = nbuf + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +#export L_TARGET = $(LIB_PATH)/libadf.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/nbuf/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/nbuf/Makefile.ss new file mode 100755 index 0000000..4510371 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/nbuf/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/adf_nbuf.o + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/nbuf/inc/adf_nbuf_pvt.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/nbuf/inc/adf_nbuf_pvt.h new file mode 100755 index 0000000..eb200fe --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/adf/nbuf/inc/adf_nbuf_pvt.h @@ -0,0 +1,425 @@ +/* + * (c) Copyright Atheros Communications + * FreeBSD specific prototypes + */ +#ifndef _ADF_NBUF_PVT_H +#define _ADF_NBUF_PVT_H + +#include +//#include +#include +//#include + +#define __ADF_NBUF_NULL NULL +#define __ADF_NBUF_CTX_BUF + +typedef VBUF * __adf_nbuf_t; + +/** + * queue head + */ +typedef struct __adf_nbuf_qhead { + VBUF *head; + VBUF *tail; + a_uint32_t qlen; +}__adf_nbuf_qhead_t; + +typedef __adf_nbuf_qhead_t __adf_nbuf_queue_t; + +__adf_nbuf_t +__adf_nbuf_alloc(adf_os_size_t size, + a_uint32_t reserve, a_uint32_t align); + +void +__adf_nbuf_free(__adf_nbuf_t buf); + +#ifndef _ROM_ +a_uint8_t * +__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t size); + +a_uint8_t * +__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t size); + +a_uint8_t * +__adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t size); +#endif + +void +__adf_nbuf_trim_tail(__adf_nbuf_t buf, adf_os_size_t size); + +__adf_nbuf_t +__adf_nbuf_realloc_headroom(__adf_nbuf_t buf, + a_uint32_t headroom); + +__adf_nbuf_t +__adf_nbuf_realloc_tailroom(__adf_nbuf_t buf, + a_uint32_t tailroom); + +__adf_nbuf_t +__adf_nbuf_expand(__adf_nbuf_t buf, + a_uint32_t headroom, a_uint32_t tailroom); + +__adf_nbuf_t +__adf_nbuf_copy(__adf_nbuf_t src); + +__adf_nbuf_t +__adf_nbuf_unshare(__adf_nbuf_t src); + +void +__adf_nbuf_frag_info(__adf_nbuf_t buf, adf_os_sglist_t *sg); + +#ifndef _ROM_ +a_uint8_t * +__adf_nbuf_get_priv(__adf_nbuf_t buf); +#endif + +void +__adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead, + __adf_nbuf_t buf); + +__adf_nbuf_t +__adf_nbuf_queue_remove(__adf_nbuf_qhead_t *qhead); + +a_uint32_t +__adf_nbuf_tx_cksum_info(__adf_nbuf_t buf, + a_uint8_t **hdr_off, + a_uint8_t **where); + +void +__adf_nbuf_set_rx_cksum(__adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum); +void +__adf_nbuf_get_tso_info(__adf_nbuf_t buf, adf_nbuf_tso_t *tso); + +a_status_t +__adf_nbuf_get_vlan_info(adf_net_handle_t hdl, + __adf_nbuf_t buf, + adf_net_vlanhdr_t *vlan); + +void +__adf_nbuf_dmamap_info(__adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg); + +/** + * @brief return the last mbuf + * + * @param m0 + * + * @return struct mbuf* + */ +#ifndef _ROM_ +VDESC * +__adf_nbuf_last(VBUF *buf); +#endif + +/** + * @brief num bytes in the head + * + * @param adf_nbuf + * + * @return num of bytes available + */ +#ifndef _ROM_ +a_uint32_t +__adf_nbuf_headroom(__adf_nbuf_t buf); +#endif + +/** + * @brief num of bytes available in the tail excluding the priv + * portion + * + * @param adf_nbuf + * + * @return num of bytes + */ +#ifndef _ROM_ +a_uint32_t +__adf_nbuf_tailroom(__adf_nbuf_t buf); +#endif + +/** + * @brief get the entire packet length + * + * @param adf_nbuf + * + * @return total length of packet (sum of all frag lengths) + */ +#ifndef _ROM_ +a_uint32_t +__adf_nbuf_len(__adf_nbuf_t buf); +#endif + +/** + * @brief Clone the nbuf (will not create writeable copies) + * + * @param adf_nbuf + * + * @return Read-only copy of the nbuf (including clusters) + */ +__adf_nbuf_t +__adf_nbuf_clone(__adf_nbuf_t src); + +void +__adf_nbuf_cat(__adf_nbuf_t dst, __adf_nbuf_t src); + + +/* + * @brief check if the mbuf is cloned or not + * + * @param buf + * + * @return a_bool_t + */ +a_bool_t +__adf_nbuf_is_cloned(__adf_nbuf_t buf); + +/** + * @brief This will return the header's addr & m_len + */ +#ifndef _ROM_ +void +__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr, + a_uint32_t *len); +#endif + +/** + * @brief init the queue + * @param qhead + */ +void +__adf_nbuf_queue_init(__adf_nbuf_qhead_t *qhead); + +/** + * @brief return the length of queue + * @param adf_qhead + * + * @return length + * + */ +a_uint32_t +__adf_nbuf_queue_len(__adf_nbuf_qhead_t *qhead); + +/** + * @brief returns the first guy in the Q + * @param qhead + * + * @return (NULL if the Q is empty) + */ +#ifndef _ROM_ +__adf_nbuf_t +__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead); + +/** + * @brief return the next packet from packet chain + * + * @param buf (packet) + * + * @return (NULL if no packets are there) + */ +__adf_nbuf_t +__adf_nbuf_queue_next(__adf_nbuf_t buf); +#endif + +/** + * @brief check if the queue is empty or not + * + * @param qhead + * + * @return a_bool_t + */ +a_bool_t +__adf_nbuf_is_queue_empty(__adf_nbuf_qhead_t *qhead); + +__adf_nbuf_t +__adf_nbuf_create_frm_frag(__adf_nbuf_queue_t *head); +void +__adf_nbuf_split_to_frag(__adf_nbuf_t buf, __adf_nbuf_queue_t *qhead); + +#ifdef _ROM_ + +/** + * @brief This will return the header's addr & m_len + */ +static inline void +__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr, + a_uint32_t *len) +{ + VDESC *desc = buf->desc_list; + + *addr = desc->buf_addr + desc->data_offset; + *len = desc->data_size; +} + +/** + * @brief return the last mbuf + * + * @param m0 + * + * @return struct mbuf* + */ +static inline VDESC * +__adf_nbuf_last(VBUF *buf) +{ + VDESC *desc = buf->desc_list; + + //for(; desc->next_desc != NULL; desc = desc->next_desc) + // ; + while(desc->next_desc != NULL) + { + desc = desc->next_desc; + } + + return desc; +} + +/** + * @brief num bytes in the head + * + * @param adf_nbuf + * + * @return num of bytes available + */ +static inline a_uint32_t +__adf_nbuf_headroom(__adf_nbuf_t buf) +{ + return buf->desc_list->data_offset; +} + +/** + * @brief num of bytes available in the tail excluding the priv + * portion + * + * @param adf_nbuf + * + * @return num of bytes + */ + +static inline a_uint32_t +__adf_nbuf_tailroom(__adf_nbuf_t buf) +{ + VDESC *last_desc = __adf_nbuf_last(buf); + + return last_desc->buf_size - last_desc->data_offset - last_desc->data_size; +} + +/** + * @brief get the entire packet length + * + * @param adf_nbuf + * + * @return total length of packet (sum of all frag lengths) + */ +static inline a_uint32_t +__adf_nbuf_len(__adf_nbuf_t buf) +{ + return buf->buf_length; +} + +/** + * @brief put data in the head + * + * @param buf + * @param len (how much data to put) + * + * @return new data pointer ,NULL if the len is more than the + * space available in the head frag. + */ +static inline a_uint8_t * +__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *ptr = NULL; + VDESC *desc = buf->desc_list; + + desc->data_offset -= len; + desc->data_size += len; + buf->buf_length += len; + ptr = desc->buf_addr + desc->data_offset; + return(ptr); +} + +/** + * + * @brief add data in the end of tail + * + * @param buf + * @param len (how much data to put) + * + * @return previous tail (data+len),NULL if the len is more than + * space available + */ +static inline a_uint8_t * +__adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *tail = NULL; + VDESC *last_desc = __adf_nbuf_last(buf); + + tail = last_desc->buf_addr + last_desc->data_offset + last_desc->data_size; + last_desc->data_size += len; + buf->buf_length += len; + + return tail; +} + +/** + * @brief strip data from head + * + * @param adf_nbuf + * @param len (how much data to rip) + * + * @return new data pointer + */ +static inline a_uint8_t * +__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *ptr = NULL; + VDESC *desc = buf->desc_list; + + desc->data_offset += len; + desc->data_size -= len; + buf->buf_length -= len; + ptr = desc->buf_addr + desc->data_offset; + + return ptr; +} + +/** + * @brief retrieve the priv space pointer from nbuf + * + * @param buf (nbuf to attach the priv space) + * + * @return uint8_t* ( pointer to the data ) + */ +static inline a_uint8_t * +__adf_nbuf_get_priv(__adf_nbuf_t buf) +{ + //adf_os_assert(buf != NULL); + + return buf->ctx; +} + +/** + * @brief returns the first guy in the Q + * @param qhead + * + * @return (NULL if the Q is empty) + */ +static inline __adf_nbuf_t +__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead) +{ + return qhead->head; +} +/** + * @brief return the next packet from packet chain + * + * @param buf (packet) + * + * @return (NULL if no packets are there) + */ +static inline __adf_nbuf_t +__adf_nbuf_queue_next(__adf_nbuf_t buf) +{ + return buf->next_buf; +} + +#endif + +#endif + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/Makefile new file mode 100755 index 0000000..934b1c2 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/Makefile @@ -0,0 +1,60 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export SSNAME = athos + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libathos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/Makefile.ss new file mode 100755 index 0000000..a36f027 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/athos_main.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/_vectors.o b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/_vectors.o new file mode 100755 index 0000000000000000000000000000000000000000..4226dde72f735c6fdc10f8ec835a72e592d667d0 GIT binary patch literal 1638 zcmb7@F>ll`6vusSfpP)~M#R(z2?hwhv{lQHA$ONjx49hTE^Q?wtlY(E52Xo8()O6x znAuqP0_;qD20jBbD-wHoPU19ms1TMM`~Q3YJipk^d(+x#EwoV8TIe;*Yhd94LW>Bk z<&H;a8C`?fEwFs%zJrWKsYgi^#Ath;_J;Nrc~1IR$MdPSiTz0sv}?Qr9Q#<)R&mho zy2R>J*CsDrlaf9U;WA`&iH_Uu$fQPhG_>5YNi8xq9m5*w9iDK{bVg)o>xy-tsT~z7 z91e&r0(4;P3>{t5I=B%bHbe?+99;E6JyO2ln3ickNwzUCb;apE(JARZ$y7 zNrD%(Y+$IRLS@e0&=CoJ7I-INrnJYzq`hskw>xqN6n645fGxZXG#RXN(BGvmjPbUv zDDC{@)b!nP=1q{AW=Sy~iCMO^N>18Q>4!GLse(|Q2(#p=XV17_42ji)?DNe z_iCl|!NtnkRlbK1U55TI-(&FH$TJlW$k+N>(_-Dbz(g*Xwtm9n*iRXudSDBUJLw>MdL+5 zyH^ZFkuZNM=`BgWl63VAWxfwm{F9`=Ncx+kzf1auq^mtB*E_!)Z{3#kilo;iy(4LQ zp<%!2DVt_-lBy#_9hS0eFV~3n+2rKVoKM-?Y!*j??y@9eVFSA + +#include "regdump.h" + +/* dhry mips stone test */ +//#include "dhry.h" + +/* usb support */ +//#include "usb_defs.h" +//#include "usb_type.h" + +/* xtensa related */ +#include "xtensa/corebits.h" +#include "xtensa/tie/xt_core.h" + +#include +#include +#include +#include + + +BOOLEAN download_enable = FALSE; + +/* #define ALLOCRAM_START 0x512800 */ +/* #define ALLOCRAM_SIZE ( SYS_RAM_SZIE - ( ALLOCRAM_START - SYS_D_RAM_REGION_0_BASE) - SYS_D_RAM_STACK_SIZE) */ + +#define ALLOCRAM_START SYS_D_RAM_REGION_3_BASE +#define ALLOCRAM_SIZE SYS_RAM_BLOCK_SIZE + +extern unsigned int _text_start_in_rom; +extern unsigned int _text_start; +extern unsigned int _text_end; + +extern unsigned int _rodata_start_in_rom; +extern unsigned int _lit4_start; +extern unsigned int _lit4_end; + +/* + * This special table is used by Xtensa startup code to copy + * ROM-based data into RAM. See Xtensa documentation or + * "unpack" code in ResetVector.S for details. + */ +const uint32_t _rom_store_table[] = { + (uint32_t)&_data_start, (uint32_t)&_data_end, (uint32_t)&_data_start_in_rom, + (uint32_t)&_text_start, (uint32_t)&_text_end, (uint32_t)0xf002000, + (uint32_t)&_lit4_start, (uint32_t)&_lit4_end, (uint32_t)0xf008000, + (uint32_t)0x00500400, (uint32_t)0x00500940, (uint32_t)0x004e0260, + 0, 0, 0 +}; + + +#define ATH_DATE_STRING __DATE__" "__TIME__ + + +/* + * 03/09: it'll always fall into this exception if we enable this exception handler, need to do more testing, Ryan + */ +void +Magpie_fatal_exception_handler(CPU_exception_frame_t *exc_frame) +{ + struct register_dump_s dump; + + dump.exc_frame = *exc_frame; /* structure copy */ + dump.badvaddr = XT_RSR_EXCVADDR(); + dump.exc_frame.xt_exccause = XT_RSR_EXCCAUSE(); + dump.pc = exc_frame->xt_pc; + dump.assline = 0; + + A_PRINTF("Fatal exception (%d): pc=0x%x badvaddr=0x%x dump area=0x%x\n", + dump.exc_frame.xt_exccause, dump.pc, dump.badvaddr, &dump); + // PRINT_FAILURE_STATE(); + + // A_ASSFAIL(&dump); // misc module +} + +//dummy now +//void app_start(void); + +static int +athos_linkage_check(int sz, struct _A_os_linkage_check *link_check) +{ + if (sz != sizeof(struct _A_os_linkage_check)) { + goto app_link_error; + } + + if (link_check->version != OS_LINKAGE_VERSION) { + goto app_link_error; + } + + if (link_check->table != sizeof(struct _A_magpie_indirection_table) && + (link_check->table != 0)) { + goto app_link_error; + } + + return 1; /* successful linkage check */ + +app_link_error: +// A_PRINTF("athos_linkage_check failure!\n"); + A_PUTS("-A1-\n\r"); + return 0; +} + + +#ifdef SYSTEM_MODULE_INTR + +/* Mask of Interrupt Level bits in Xtensa's Processor Status register */ +#define XTENSA_PS_INTLEVEL_MASK 0xf + +LOCAL uint32_t +athos_block_all_intrlvl(void) +{ + uint32_t tmp; + + /* + * This function doesn't actually block ALL interrupts; + * it leaves ERROR & WDT interrupts -- which are fatal + * and are at level 3 -- active. + */ + asm volatile("rsil %0,2" : "=r" (tmp)); + + return (uint32_t)((A_UINT32)tmp & XTENSA_PS_INTLEVEL_MASK); +} + +LOCAL void +athos_unblock_all_intrlvl(void) +{ + unsigned int tmp; + + asm volatile("rsil %0, 0" : "=r" (tmp)); +} + +LOCAL void +athos_restore_intrlvl(uint32_t old_intr) +{ + if (old_intr == 0) { + athos_unblock_all_intrlvl(); + } +} +#endif + + +static void +AR6002_misaligned_load_handler(CPU_exception_frame_t *exc_frame) +{ + struct register_dump_s dump; + uint32_t *stkptr; + +#if SYSTEM_MODULE_PRINT + A_PRINTF("misaligned_load\n\r"); +#else + A_PUTS("misaligned_load\n\r"); +#endif + + dump.exc_frame = *exc_frame; /* structure copy */ + dump.badvaddr = XT_RSR_EXCVADDR(); + dump.pc = exc_frame->xt_pc; + + asm volatile("mov %0,a1" : "=r" (stkptr)); + + /* Stores a0,a1,a2,a3 on stack; but leaves sp unchanged */ + xthal_window_spill(); + + { + int i; + +#define MAGPIE_REGDUMP_FRAMES 5 + + /* Walk back the stack */ + for (i=0; ixt_pc; + dump.assline = 0; + +#if SYSTEM_MODULE_PRINT + A_PRINTF("Fatal exception (%d): \tpc=0x%x \n\r\tbadvaddr=0x%x \n\r\tdump area=0x%x\n", + dump.exc_frame.xt_exccause, dump.pc, dump.badvaddr, &dump); + PRINT_FAILURE_STATE(); + #else + A_PUTS("Fatal exception\n\r"); +#endif + + A_ASSFAIL(&dump); + + // trigger wdt, in case hang +#if defined(_ROM_) + //HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR, 0x03); + //HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_ADDR, 0x10); + A_WDT_ENABLE(); +#endif + + while(1) + ; +} + + +typedef void (*INSTFN)(void *); + +/* + * These are all modules that reside in ROM which are installed + * by default by the operating system. Other ROM modules may + * be installed by the application if they are needed. + */ +struct { + void (* install_fn)(void *); + void *api_tbl; +} basic_ROM_module_table[] = +{ + +#if SYSTEM_MODULE_MEM + {(INSTFN)cmnos_mem_module_install, (void *)&A_CMN(mem)}, +#endif + +#if SYSTEM_MODULE_MISC + {(INSTFN)cmnos_misc_module_install, (void *)&A_CMN(misc)}, +#endif + +#if SYSTEM_MODULE_PRINT + {(INSTFN)cmnos_printf_module_install, (void *)&A_CMN(printf)}, +#endif + +#if SYSTEM_MODULE_UART + {(INSTFN)cmnos_uart_module_install, (void *)&A_CMN(uart)}, +#endif + +#if SYSTEM_MODULE_USB + {(INSTFN)cmnos_usb_module_install, (void *)&A_CMN(usb)}, +#endif + +#if SYSTEM_MODULE_INTR + {(INSTFN)cmnos_intr_module_install, (void *)&A_CMN(intr)}, +#endif + +#if SYSTEM_MODULE_TIMER + {(INSTFN)cmnos_timer_module_install, (void *)&A_CMN(timer)}, +#endif + +#if SYSTEM_MODULE_CLOCK + {(INSTFN)cmnos_clock_module_install, (void *)&A_CMN(clock)}, +#endif + +#if SYSTEM_MODULE_ALLOCRAM + {(INSTFN)cmnos_allocram_module_install, (void *)&A_CMN(allocram)}, +#endif + +#if SYSTEM_MODULE_ROM_PATCH + {(INSTFN)cmnos_romp_module_install, (void *)&A_CMN(romp)}, +#endif + +#if SYSTEM_MODULE_WDT + {(INSTFN)cmnos_wdt_module_install, (void *)&A_CMN(wdt_timer)}, +#endif + +#if SYSTEM_MODULE_EEPROM + {(INSTFN)cmnos_eep_module_install, (void *)&A_CMN(eep)}, +#endif + {(INSTFN)cmnos_string_module_install, (void *)&A_CMN(string)}, + {(INSTFN)cmnos_tasklet_module_install, (void *)&A_CMN(tasklet)}, + {(INSTFN)vdesc_module_install, (void *)&A_INDIR(vdesc)}, + {(INSTFN)vbuf_module_install, (void *)&A_INDIR(vbuf)}, + {(INSTFN)generic_hif_module_install, (void *)&A_INDIR(hif)}, + {(INSTFN)buf_pool_module_install, (void *)&A_INDIR(buf_pool)}, + {(INSTFN)usbfifo_module_install, (void *)&A_INDIR(usbfifo_api)}, + {(INSTFN)dma_engine_module_install, (void *)&A_INDIR(dma_engine)}, + {(INSTFN)dma_lib_module_install, (void *)&A_INDIR(dma_lib)}, +}; + +#define BASIC_ROM_MODULE_TABLE_SZ (sizeof(basic_ROM_module_table)/sizeof(basic_ROM_module_table[0])) + +void +generic_hif_module_install(struct hif_api *apis) +{ + A_HOSTIF hostif; + + hostif = A_IS_HOST_PRESENT(); + + switch(hostif){ + case HIF_USB: + hif_usb_module_install(apis); + break; + } +} + +void +athos_indirection_table_install(void) +{ + unsigned int i; + + /* Sanity: start with a clear table */ + { + //char *tbl = (char *)_A_OS_INDIRECTION_TABLE; + char *tbl = (char *)_A_MAGPIE_INDIRECTION_TABLE; + + //for (i=0; i<_A_OS_INDIRECTION_TABLE_SIZE; i++) { + for (i=0; i<_A_MAGPIE_INDIRECTION_TABLE_SIZE; i++) { + tbl[i] = 0; + } + } + + /* Install basic ROM modules */ + for (i=0; icmnos.app_start = app_start; + //_A_OS_INDIRECTION_TABLE->cmnos.hal_linkage_check = athos_linkage_check; + //_A_MAGPIE_INDIRECTION_TABLE->cmnos.app_start = app_start; + _A_MAGPIE_INDIRECTION_TABLE->cmnos.hal_linkage_check = athos_linkage_check; + +// _A_OS_INDIRECTION_TABLE->cmnos.start_bss = &START_BSS; + +#if SYSTEM_MODULE_INTR + /* Install a few CPU-specific functions */ + _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._get_intrenable = xthal_get_intenable; + _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._set_intrenable = xthal_set_intenable; + _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._get_intrpending = xthal_get_interrupt; + _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._unblock_all_intrlvl = athos_unblock_all_intrlvl; + _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._intr_disable = athos_block_all_intrlvl; + _A_MAGPIE_INDIRECTION_TABLE->cmnos.intr._intr_restore = athos_restore_intrlvl; +#endif + + /* UNALIGNED references are used for ASSERTs */ + (void)_xtos_set_exception_handler(EXCCAUSE_UNALIGNED, AR6002_misaligned_load_handler); + (void)_xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_ERROR, AR6002_fatal_exception_handler); + (void)_xtos_set_exception_handler(EXCCAUSE_ILLEGAL, AR6002_fatal_exception_handler); + (void)_xtos_set_exception_handler(EXCCAUSE_INSTR_ERROR, AR6002_fatal_exception_handler); + (void)_xtos_set_exception_handler(EXCCAUSE_PRIVILEGED, AR6002_fatal_exception_handler); + (void)_xtos_set_exception_handler(EXCCAUSE_INSTR_DATA_ERROR, AR6002_fatal_exception_handler); + (void)_xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, AR6002_fatal_exception_handler); + (void)_xtos_set_exception_handler(EXCCAUSE_DIVIDE_BY_ZERO, AR6002_fatal_exception_handler); +} + + +#ifdef SYSTEM_MODULE_INTR +/* + * All interrupts pass through here. Yes, it adds a + * bit of overhead; but it may be very helpful with + * debugging, ROM patching, and workarounds. + * + * NB: Assembler code that calls this loops through all + * pending & enabled interrupts. + */ +void +athos_interrupt_handler(unsigned int inum, unsigned int *interrupt_frame) +{ + A_INVOKE_ISR(inum); +} +#endif + +void +athos_interrupt_init(void) +{ +#ifdef SYSTEM_MODULE_INTR + int i; + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x20; + + for (i=0; i 200 Mhz CPU clock (PLL / 2) or < 200 Mhz (PLL / 4) */ + if (cpu_freq > 195) + rd_data = (rd_data & ~(0xff<<16)) | (1<<16); + else + rd_data = (rd_data & ~(0xff<<16)) | (2<<16); + + /* AHB Clock, AHB_FREQ = CPU_FREQ / ahb_div */ + switch (ahb_div) { + case 1: + rd_data = (rd_data & ~(0x3<<8) & ~(1<<4)) | 0x1; + break; + case 2: + rd_data = (rd_data & ~(0x3<<8) & ~(1<<4)) | (1<<8) | 0x1; + break; + case 4: + rd_data = (rd_data & ~(0x3<<8) & ~(1<<4)) | (2<<8) | 0x1; + break; + default: + rd_data = (rd_data & ~(0x3<<8) & ~(1<<4)) | (1<<8) | 0x1; + break; + } + + HAL_WORD_REG_WRITE(0x00056004, rd_data); + rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1; + + while(rd_data) + rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1; + + while(i++ < 1000) + ; + + /* UART Setting */ + A_UART_HWINIT((cpu_freq / ahb_div) * (1000*1000), 115200); + +// A_PRINTF("reg_read(0x56000): %p \n", HAL_WORD_REG_READ(0x00056000)); +// A_PRINTF("reg_read(0x56004): %p \n", HAL_WORD_REG_READ(0x00056004)); + + /* set the current reference clock */ +// A_CLOCK_INIT(cpu_freq); + +} + +/* + * rom1.0 fix: turn off rc if no patch/eeprom exist +*/ +void turn_off_rc() +{ + extern BOOLEAN eep_state; + + // clear the cmnos_eeprom init state + eep_state = FALSE; + + // reset the pcie_rc shift, pll and phy + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|(BIT10|BIT9|BIT8|BIT7))); + + // reset ahb_arb of pcie_rc + HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT1)); +} + +void bootentry(void) +{ + /* uint32_t reset_temp; */ + A_HOSTIF hostif=0x0; + T_BOOT_TYPE rst_status; + T_EEP_RET retEEP; + + /////////////////////////////////// + athos_indirection_table_install(); + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x1; + CURRENT_PROGRAM = (uint32_t)bootentry; + // athos module install + athos_init(hostif); // move all the athos indirection table init function to here + + athos_interrupt_init(); // install all interrupt function to known state + + A_WDT_DISABLE(); // make srue wdt is diable + + rst_status = A_WDT_LASTBOOT(); + + // pump up flash clock to 12.5Mhz + HAL_WORD_REG_WRITE(0x5b01c, 0x401); + + /* + * + * 1. turn on CPU PLL, reg(0x560000), 0x305 + * 2. pll reset reg(0x50010), 0x03 + * 3. pll reset reg(0x50010), 0x01 + * + * - after enabling CPU PLL, left the interface pll setting + * be done in each interface + * + * e.g usb_init we mdid + * 4. usb divide reg(0x56008), 0x0808 + * 5. clear register reg(0x50010), bit0, bit3, bit4 + * 6. set register reg(0x50010), bit0, bit3, bit4 + * 7. clear register reg(0x50010), bit0, bit3, bit4 + * + * - wait for 200ms for usb phy 30mhz stable - + * + * 8. usb clock up, proceed reset of things + */ + + /* reset_temp = HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR); */ + /* A_PRINTF("reset temp is %x \n",reset_temp); */ + /* HAL_WORD_REG_WRITE( MAGPIE_REG_RST_RESET_ADDR, 0); */ + + + /*! move the whole cpu pll setup to host interface specific + * since when bootup, we have an external clock source + */ + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x2; + + hostif = A_IS_HOST_PRESENT(); + +/*! + * GPIO_FUNCTION(0x28) - config uart (sin, sout) pair, + * + * pci host interface will only have (GPIO1, GPIO0), other hif (usb, pcie, gmac) + * will use (GPIO5, GPIO4) + * + * BIT8 --> (9,8) + * BIT7 --> (7,6) + * BIT6 --> (5,4) + * BIT5 --> (3,2) + * BIT4 --> (1,0) + * + */ + { + HAL_WORD_REG_WRITE( MAGPIE_REG_GPIO_FUNCTION, (HAL_WORD_REG_READ(MAGPIE_REG_GPIO_FUNCTION)&(~(BIT4|BIT5|BIT6|BIT7|BIT8))) ); + HAL_WORD_REG_WRITE( MAGPIE_REG_GPIO_FUNCTION, (HAL_WORD_REG_READ(MAGPIE_REG_GPIO_FUNCTION)|(BIT8)) ); + } + + change_magpie_clk(200, 2); + + // power on self test + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x5; + A_PUTS("\n - Boot from SFLASH - \n\r"); + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x9; + + /*! + * check the host interface type, + */ + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x15; + hostif = A_IS_HOST_PRESENT(); + + retEEP = A_EEP_IS_EXIST(); + + turn_off_rc(); + + if( hostif == HIF_USB ) + { + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0xb; +#if 0 + if( retEEP == RET_SUCCESS) + { + A_EEP_INIT(); + /* read the usb descriptor information from rom to ram */ + read_usb_conf(); + + turn_off_rc(); + } +#endif + A_USB_INIT(); + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0xd; + bootload(); + } + +} + + +int main(void) +{ + *(unsigned long *)0x52000 = 0x7ebff; // set bit10/bit12 output mode + *(unsigned long *)0x0053fff8 = 0x0; + + // for debug purpose in case we don't know where we are + // keep this address update, so that we could trace the where is is + DEBUG_SYSTEM_STATE = 0x0; + + bootentry(); + + A_PRINTF("FLASH_READ_COMP, jump to firmware\n"); + + led_on(10); + led_on(12); + + return 0; +} + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/crt1-tiny.o b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/crt1-tiny.o new file mode 100755 index 0000000000000000000000000000000000000000..2c6d420e4e92a6bdc46fca16d4b556078a22f931 GIT binary patch literal 3352 zcma);O>7%g5XWcj#7#_T>m~x!R@60L6>8UOCu#uIqE6yAOC5*WF^Q01z5Yr~96Pc% zG?frUhyy}^DulSesiz(gr<@RnoH%hnAR$hiDv&rp5f>y5;F^Iy`uf=r-%%85w1W@2C&a2qk^c^^F?Qhhs#Q zyLXhWyu&#jM5>>mHCDY=Z|FL9uidAG6=!a#bkV+K&s#ZbyODjyYS!EBcu1dt-fCLe z?3C4x&sOc?yi+aNSE>cao@bM#P5D_nXT__Pf|H-EEETKE1*d2)7s~l!C70oVFBQra zd#RL56<4!n#^-}R=yWq?%6y`2hs*4U* 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zsq44H1T{ARr&tSmY|vxbUEMT#EcGzTZ|ZA{p~q5JKp(y2dTbx=Y2{c9J$3@=-6%bl zI=_+0I^*pe`3F5#^va;eYRd?EEItl@Xy?KEbECt>!-|UIg~UUp;^eN${8(}S(a#pk z+~BdP{HS;>o*tX2&|}>P=lW4PpVCdH!)6yWPnZchY;MmjxsWC3u-e52Tdb>yyK$ne ziDPckY&KikOnh6+V%uVa4lC84h}&X=4qIsp4Yt@|iyhHl&X(LcKM5UCthA;4qywWP z$BsjV6i-nh9ij^PU~zK1IO-{pR5K?=oRT?Fa%Uza`lsv^D=43FKKU*^XZ76e&iH@P zNd9;UTB+!*E(14MhwYlF!*<=gI;{PN-C1Mj`oAu|5eolppZO(F<>I*TjZpj1@k7U) zXr1?w-^b84gKzqTIN#@!*=;t$lh|~p+2X}@tl8qlbu7fII^P|ehh5Nr+pi$M)Z^y* zMu>BCMpj!PTw=MK5p&*@tbP6l67q+X& z74%6#I=NLfg>wHa(q$C9u5J;23jEu6l~B3#G8+/xtensa-elf/src/xtos + +# Copyright (c) 2000-2007 by Tensilica Inc. ALL RIGHTS RESERVED. +# These coded instructions, statements, and computer programs are the +# copyrighted works and confidential proprietary information of Tensilica Inc. +# They may not be modified, copied, reproduced, distributed, or disclosed to +# third parties in any manner, medium, or form, in whole or in part, without +# the prior written consent of Tensilica Inc. + +# +# This makefile assumes GNU make features +# +# Invoke this Makefile like this: +# cd +# make -f \ +# MAKEFILE_SRC= \ +# XTENSA_TOOLS_ROOT= \ +# XTENSA_ROOT= \ +# INSTLIBDIR= +# + +ifndef XTENSA_TOOLS_ROOT +$(error Please set XTENSA_TOOLS_ROOT to the path to Xtensa Tools) +endif +# NOTE: For now, we assume $(XTENSA_TOOLS_ROOT)/bin is on the PATH. +ifndef XTENSA_ROOT +$(error Please set XTENSA_ROOT to the path to your specific Xtensa core package) +endif + +#ifndef INSTLIBDIR +#$(error Please set INSTLIBDIR to the path where libraries and objects are installed) +#INSTLIBDIR = $(call fixpath,$(XTENSA_ROOT)/xtensa-elf/arch/lib) +#endif + +# Select the specified Xtensa configuration: +export XTENSA_SYSTEM = $(XTENSA_ROOT)/config +export XTENSA_CORE = default + +include $(XTENSA_TOOLS_ROOT)/misc/defs.mk + +ifndef SRCDIR +$(error Please set MAKEFILE_SRC to the path to the XTOS Makefile.src) +endif + +# Native commands like $(MKPATH) and $(CP) need native directory separators: +#fixpath = $(subst /,$S,$(1)) + +XTCC = $(CC_FOR_TARGET) +XTAR = xt-ar + +.PHONY: all clean + +# Compilation flags +ASFLAGS = -O2 -g -mlongcalls +CFLAGS = -O2 -g -mlongcalls + +# File splitting: +# Compile "split" files in separate parts that can be linked independently. +# This allows keeping multiple related functions/etc together in one file +# without forcing linking of unused functions (the GNU linker takes entire +# object files; it does not currently provide automated dead code removal). +# Files are split with "#[el]if defined(__SPLIT__)" lines using normal +# C preprocessor syntax, where each must be unique and consist of +# lowercase alphanumeric and underscore characters only (no dash etc). +# The makefile function $(split_objs ...) returns the set of objects that +# result for a given list of splittable source files; each ends in a -.o +# suffix recognized by special rules further below. +# +split_objs = $(shell cd $(SRCDIR) && $(PERL) -ne '/__SPLIT__(\w+)/ and $$h{$$ARGV."--".$$1}++;\ + END {foreach (sort keys %h) {s/\.(.)--/-$$1--/; print "$$_-.o\n";}}' $(1)) + +# Vectors, handlers, and other code to build: +PERLEVEL_INTVECTOR_OBJS = $(foreach N,2 3 4 5 6,int-vector-level$(N).o) +PERLEVEL_INTHANDLER_OBJS = $(foreach N,2 3 4 5 6,int-handler-level$(N).o) +PERLEVEL_INTINITLEV_OBJS = $(foreach N,1 2 3 4 5 6,int-init-level$(N).o) +XTOS_COMMON_OBJS = \ + reset-vector-unpack.o \ + user-vector.o \ + nmi-vector.o \ + window-vectors.o \ + reloc-vectors.o \ + $(call split_objs, memerror-vector.S) \ + $(PERLEVEL_INTVECTOR_OBJS) \ + exc-alloca-handler.o \ + exc-return.o \ + exc-sethandler.o \ + exc-syscall-handler.o \ + exc-syscall-c-handler.o \ + exc-table.o \ + exit.o \ + init.o \ + int-lowpri-dispatcher.o \ + int-sethandler.o \ + intlevel-set.o \ + intlevel-setmin.o \ + intlevel-restore.o \ + ints-on.o \ + ints-off.o \ + switch_context.o \ + $(call split_objs, deprecated.S tiny-refs.S) \ + $(PERLEVEL_INTHANDLER_OBJS) \ + $(PERLEVEL_INTINITLEV_OBJS) +# These objects have simulator and board variants: +XTOS_SIMBOARD_OBJS = \ + debug-vector.o \ + double-vector.o \ + kernel-vector.o \ + interrupt-table.o \ + exc-unhandled.o \ + exc-c-wrapper-handler.o \ + memep-initrams.o \ + memep-enable.o +XTOS_BOARD_OBJS = $(XTOS_SIMBOARD_OBJS) +XTOS_SIM_OBJS = $(XTOS_SIMBOARD_OBJS:.o=-sim.o) + +# Optimize a few things for size rather than speed: +#FLAGS_exc-syscall-handler = -Os --no-target-align + +TARGETS = \ + _vectors.o \ + crt0-app.o \ + crt1-boards.o \ + crt1-tiny.o \ + crt1-sim.o \ + libhandlers-sim.a \ + libhandlers-board.a \ + libhandlers-min.a \ + libhandlers-null.a \ + libnomovsp.a \ + libnosyscall.a \ + libhandler-reset.a +ifdef TENSILICA_INTERNAL +TARGETS += libhandler-reset-mp.a +endif + +all: $(TARGETS) + + +# Here's an example of how one could put a selected set of +# objects into a specific section: +# +#XTOSSECFLAGS = \ +# -mrename-section-.text=.xtos.text \ +# -mrename-section-.literal=.xtos.literal \ +# -mrename-section-.rodata=.xtos.rodata \ +# -mrename-section-.data=.xtos.data +#$(XTOS_SIM_OBJS) : XTFLAGS = $(XTOSSECFLAGS) + +libhandlers-sim.a: $(XTOS_SIM_OBJS) $(XTOS_COMMON_OBJS) + +libhandlers-board.a: $(XTOS_BOARD_OBJS) $(XTOS_COMMON_OBJS) + +libhandlers-min.a: user-vector-min.o tiny-refs-min.o + +libhandlers-null.a: $(call split_objs, null-vectors.S) _vectors.o + +libnomovsp.a: null-alloca.o + +libnosyscall.a: null-syscall.o + +$(PERLEVEL_INTVECTOR_OBJS): int-vector-level%.o: int-vector.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_int-vector-level$*) $(XTFLAGS) -D_INTERRUPT_LEVEL=$* -o $@ $< + +$(PERLEVEL_INTHANDLER_OBJS): int-handler-level%.o: int-handler.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_int-handler-level$*) $(XTFLAGS) -D_INTERRUPT_LEVEL=$* -o $@ $< + +$(PERLEVEL_INTINITLEV_OBJS): int-init-level%.o: int-initlevel.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_int-init-level$*) $(XTFLAGS) -D_INTERRUPT_LEVEL=$* -o $@ $< + + +# For split-source rules, determine various things from $* (extended basename): +# +SPLIT_SRC = $(patsubst %/,%,$(dir $(subst -c--,.c/,$(subst -S--,.S/,$*)))) +SPLIT_FLAGS = $(FLAGS_$(basename $(SPLIT_SRC))) \ + -D__SPLIT__$(notdir $(subst --,/,$*)) + +# (Okay we cheat a bit, CFLAGS matches ASFLAGS so this works; it's also simpler:) +%-.o: + $(XTCC) -c $(CFLAGS) $(SPLIT_FLAGS) $(XTFLAGS) -o $@ $(SRCDIR)/$(SPLIT_SRC) +%--sim.o: + $(XTCC) -c $(CFLAGS) $(SPLIT_FLAGS) $(XTFLAGS) -DSIMULATOR -o $@ $(SRCDIR)/$(SPLIT_SRC) + + +%.o: %.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_$*) $(XTFLAGS) $< + +%.o: %.c + $(XTCC) -c $(CFLAGS) $(FLAGS_$*) $(XTFLAGS) $< + +%-sim.o: %.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_$*) $(XTFLAGS) -DSIMULATOR -o $@ $< + +%-sim.o: %.c + $(XTCC) -c $(CFLAGS) $(FLAGS_$*) $(XTFLAGS) -DSIMULATOR -o $@ $< + +# Explicit rule for crt1-sim.o to avoid using %-sim.o rule above: +crt1-sim.o: crt1-sim.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_$*) $(XTFLAGS) $< + + +# When building the reset vector, leave the literals in +# the text section, so that the reset vector can be placed +# at address 0 (there's no lower address for the literals). +# +#FLAGS_reset-vector = -mtext-section-literals +# +reset-vector.o: reset-vector.S + $(XTCC) -c $(ASFLAGS) $(XTFLAGS) -mtext-section-literals -o $@ $< +reset-vector-unpack.o: reset-vector.S + $(XTCC) -c $(ASFLAGS) $(XTFLAGS) -mtext-section-literals -DXTOS_UNPACK -o $@ $< +reset-vector-mp.o: reset-vector.S + $(XTCC) -c $(ASFLAGS) $(XTFLAGS) -mtext-section-literals -DXTOS_MP -o $@ $< +# +# These libraries provide alternative reset vectors: +# Without any unpacking: +libhandler-reset.a: reset-vector.o +# With experimental MP unpacking: +libhandler-reset-mp.a: reset-vector-mp.o + +%.a: + -$(RM) $@ + $(XTAR) rs $@ $^ + +#install: +# -$(MKPATH) $(INSTLIBDIR) +# $(CP) $(TARGETS) $(INSTLIBDIR) + +clean: + -$(RM) *.o *.a + +# NOTE: Header file dependencies not specified! + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/Makefile.src b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/Makefile.src new file mode 100644 index 0000000..3d135c1 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/Makefile.src @@ -0,0 +1,256 @@ +# Makefile for XTOS in /xtensa-elf/src/xtos + +# Copyright (c) 2000-2010 Tensilica Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining +# a copy of this software and associated documentation files (the +# "Software"), to deal in the Software without restriction, including +# without limitation the rights to use, copy, modify, merge, publish, +# distribute, sublicense, and/or sell copies of the Software, and to +# permit persons to whom the Software is furnished to do so, subject to +# the following conditions: +# +# The above copyright notice and this permission notice shall be included +# in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +# +# This makefile assumes GNU make features +# +# Invoke this Makefile like this: +# cd +# make -f \ +# MAKEFILE_SRC= \ +# XTENSA_TOOLS_ROOT= \ +# XTENSA_ROOT= \ +# INSTLIBDIR= +# + +ifndef XTENSA_TOOLS_ROOT +$(error Please set XTENSA_TOOLS_ROOT to the path to Xtensa Tools) +endif +# NOTE: For now, we assume $(XTENSA_TOOLS_ROOT)/bin is on the PATH. +ifndef XTENSA_ROOT +$(error Please set XTENSA_ROOT to the path to your specific Xtensa core package) +endif +ifndef INSTLIBDIR +$(error Please set INSTLIBDIR to the path where libraries and objects are installed) +#INSTLIBDIR = $(call fixpath,$(XTENSA_ROOT)/xtensa-elf/arch/lib) +endif + +# Select the specified Xtensa configuration: +export XTENSA_SYSTEM = $(XTENSA_ROOT)/config +export XTENSA_CORE = default + +include $(XTENSA_TOOLS_ROOT)/misc/defs.mk +include $(XTENSA_ROOT)/misc/build.mk + +ifndef SRCDIR +$(error Please set MAKEFILE_SRC to the path to the XTOS Makefile.src) +endif + +# Native commands like $(MKPATH) and $(CP) need native directory separators: +#fixpath = $(subst /,$S,$(1)) + +XTCC = $(CC_FOR_TARGET) +XTAR = xt-ar + +.PHONY: all install clean + +# Compilation flags +ASFLAGS = -O2 -g -mlongcalls +CFLAGS = -O2 -g -mlongcalls + +# File splitting: +# Compile "split" files in separate parts that can be linked independently. +# This allows keeping multiple related functions/etc together in one file +# without forcing linking of unused functions (the GNU linker takes entire +# object files; it does not currently provide automated dead code removal). +# Files are split with "#[el]if defined(__SPLIT__)" lines using normal +# C preprocessor syntax, where each must be unique and consist of +# lowercase alphanumeric and underscore characters only (no dash etc). +# The makefile function $(split_objs ...) returns the set of objects that +# result for a given list of splittable source files; each ends in a -.o +# suffix recognized by special rules further below. +# +split_objs = $(shell cd $(SRCDIR) && $(PERL) -ne '/__SPLIT__(\w+)/ and $$h{$$ARGV."--".$$1}++;\ + END {foreach (sort keys %h) {s/\.(.)--/-$$1--/; print "$$_-.o\n";}}' $(1)) + +# Vectors, handlers, and other code to build: +PERLEVEL_INTVECTOR_OBJS = $(foreach N,2 3 4 5 6,int-vector-level$(N).o) +PERLEVEL_INTHANDLER_OBJS = $(foreach N,2 3 4 5 6,int-handler-level$(N).o) +PERLEVEL_INTINITLEV_OBJS = $(foreach N,1 2 3 4 5 6,int-init-level$(N).o) +XTOS_COMMON_OBJS = \ + reset-vector-unpack.o \ + shared-reset-vector.o \ + user-vector.o \ + nmi-vector.o \ + window-vectors.o \ + reloc-vectors.o \ + $(call split_objs, memerror-vector.S) \ + $(PERLEVEL_INTVECTOR_OBJS) \ + exc-alloca-handler.o \ + exc-return.o \ + exc-sethandler.o \ + exc-syscall-handler.o \ + exc-syscall-c-handler.o \ + exc-table.o \ + exit.o \ + init.o \ + int-lowpri-dispatcher.o \ + int-sethandler.o \ + intlevel-set.o \ + intlevel-setmin.o \ + intlevel-restore.o \ + ints-on.o \ + ints-off.o \ + switch_context.o \ + $(call split_objs, deprecated.S tiny-refs.S) \ + $(PERLEVEL_INTHANDLER_OBJS) \ + $(PERLEVEL_INTINITLEV_OBJS) +# These objects have simulator and board variants: +XTOS_SIMBOARD_OBJS = \ + debug-vector.o \ + double-vector.o \ + kernel-vector.o \ + interrupt-table.o \ + exc-unhandled.o \ + exc-c-wrapper-handler.o \ + memep-initrams.o \ + memep-enable.o +XTOS_BOARD_OBJS = $(XTOS_SIMBOARD_OBJS) +XTOS_SIM_OBJS = $(XTOS_SIMBOARD_OBJS:.o=-sim.o) + +# Optimize a few things for size rather than speed: +#FLAGS_exc-syscall-handler = -Os --no-target-align + +TARGETS = \ + _vectors.o \ + _sharedvectors.o \ + _sharedvectors-for-reset.o \ + crt0-app.o \ + crt1-boards.o \ + crt1-tiny.o \ + crt1-sim.o \ + libhandlers-sim.a \ + libhandlers-board.a \ + libhandlers-min.a \ + libhandlers-null.a \ + libnomovsp.a \ + libnosyscall.a \ + libhandler-reset-unpack.a \ + libhandler-reset.a +ifdef TENSILICA_INTERNAL +TARGETS += libhandler-reset-mp.a +endif + +all: $(TARGETS) + + +# Here's an example of how one could put a selected set of +# objects into a specific section: +# +#XTOSSECFLAGS = \ +# -mrename-section-.text=.xtos.text \ +# -mrename-section-.literal=.xtos.literal \ +# -mrename-section-.rodata=.xtos.rodata \ +# -mrename-section-.data=.xtos.data +#$(XTOS_SIM_OBJS) : XTFLAGS = $(XTOSSECFLAGS) + +libhandlers-sim.a: $(XTOS_SIM_OBJS) $(XTOS_COMMON_OBJS) + +libhandlers-board.a: $(XTOS_BOARD_OBJS) $(XTOS_COMMON_OBJS) + +libhandlers-min.a: user-vector-min.o tiny-refs-min.o + +libhandlers-null.a: $(call split_objs, null-vectors.S) _vectors.o _sharedvectors.o + +libnomovsp.a: null-alloca.o + +libnosyscall.a: null-syscall.o + +$(PERLEVEL_INTVECTOR_OBJS): int-vector-level%.o: int-vector.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_int-vector-level$*) $(XTFLAGS) -D_INTERRUPT_LEVEL=$* -o $@ $< + +$(PERLEVEL_INTHANDLER_OBJS): int-handler-level%.o: int-handler.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_int-handler-level$*) $(XTFLAGS) -D_INTERRUPT_LEVEL=$* -o $@ $< + +$(PERLEVEL_INTINITLEV_OBJS): int-init-level%.o: int-initlevel.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_int-init-level$*) $(XTFLAGS) -D_INTERRUPT_LEVEL=$* -o $@ $< + + +# For split-source rules, determine various things from $* (extended basename): +# +SPLIT_SRC = $(patsubst %/,%,$(dir $(subst -c--,.c/,$(subst -S--,.S/,$*)))) +SPLIT_FLAGS = $(FLAGS_$(basename $(SPLIT_SRC))) \ + -D__SPLIT__$(notdir $(subst --,/,$*)) + +# (Okay we cheat a bit, CFLAGS matches ASFLAGS so this works; it's also simpler:) +%-.o: + $(XTCC) -c $(CFLAGS) $(SPLIT_FLAGS) $(XTFLAGS) -o $@ $(SRCDIR)/$(SPLIT_SRC) +%--sim.o: + $(XTCC) -c $(CFLAGS) $(SPLIT_FLAGS) $(XTFLAGS) -DSIMULATOR -o $@ $(SRCDIR)/$(SPLIT_SRC) + + +%.o: %.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_$*) $(XTFLAGS) $< + +%.o: %.c + $(XTCC) -c $(CFLAGS) $(FLAGS_$*) $(XTFLAGS) $< + +%-sim.o: %.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_$*) $(XTFLAGS) -DSIMULATOR -o $@ $< + +%-sim.o: %.c + $(XTCC) -c $(CFLAGS) $(FLAGS_$*) $(XTFLAGS) -DSIMULATOR -o $@ $< + +# Explicit rule for crt1-sim.o to avoid using %-sim.o rule above: +crt1-sim.o: crt1-sim.S + $(XTCC) -c $(ASFLAGS) $(FLAGS_$*) $(XTFLAGS) $< + + +# When building the reset vector, leave the literals in +# the text section, so that the reset vector can be placed +# at address 0 (there's no lower address for the literals). +# (Can't do that on Xtensa TX without load/store to IRAM/IROM.) + +ifneq ($(XPAL_HAVE_IMEM_LOADSTORE),0) +FLAGS_reset-vector = -mtext-section-literals +FLAGS_shared-reset-vector = -mtext-section-literals +endif + +#reset-vector.o: reset-vector.S +# $(XTCC) -c $(ASFLAGS) $(XTFLAGS) $(FLAGS_reset-vector) -o $@ $< +reset-vector-unpack.o: reset-vector.S + $(XTCC) -c $(ASFLAGS) $(XTFLAGS) $(FLAGS_reset-vector) -DXTOS_UNPACK -o $@ $< +reset-vector-mp.o: reset-vector.S + $(XTCC) -c $(ASFLAGS) $(XTFLAGS) $(FLAGS_reset-vector) -DXTOS_MP -o $@ $< +# +# These libraries provide alternative reset vectors: +# With ROM unpacking (the default): +libhandler-reset-unpack.a: reset-vector-unpack.o +# Without any unpacking: +libhandler-reset.a: reset-vector.o +# With experimental MP unpacking: +libhandler-reset-mp.a: reset-vector-mp.o + +%.a: + -$(RM) $@ + $(XTAR) rs $@ $^ + +install: + -$(MKPATH) $(INSTLIBDIR) + $(CP) $(TARGETS) $(INSTLIBDIR) + +clean: + -$(RM) *.o *.a + +# NOTE: Header file dependencies not specified! + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/_sharedvectors-for-reset.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/_sharedvectors-for-reset.S new file mode 100644 index 0000000..4dfa8ca --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/_sharedvectors-for-reset.S @@ -0,0 +1,40 @@ +// _sharedvectors-for-reset.S -- Reference to pull in a shared reset vector +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/_sharedvectors-for-reset.S#2 $ + +// Copyright (c) 2008 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include + +/* Multicore build flows can use this file (_sharedvectors-for-reset.o) + by copying it to _sharedvectors.o early in the linker search path + (to override the default one), and updating the memory map or linker + scripts accordingly. + This file pulls in a sharable reset vector (typically + shared-reset-vector.S, which requires the PRID option). */ + +.global _SharedResetVector + +/* The following allows this object file to be pulled in by reference: */ +.text +.global _xtos_sharedvectors_ref_ +.set _xtos_sharedvectors_ref_, 0 + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/_sharedvectors.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/_sharedvectors.S new file mode 100644 index 0000000..d7ec870 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/_sharedvectors.S @@ -0,0 +1,37 @@ +// _sharedvectors.S -- Reference symbols to pull in any shared vectors +// (default version, used when not sharing any vector) +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/_sharedvectors.S#2 $ + +// Copyright (c) 2008 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include + +/* Not present by default. Multicore build flows build/use a custom + version of _sharedvectors.o that may pull in shared vectors. */ + +/* .global _SharedResetVector */ + +/* The following allows this object file to be pulled in by reference: */ +.text +.global _xtos_sharedvectors_ref_ +.set _xtos_sharedvectors_ref_, 0 + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/_vectors.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/_vectors.S new file mode 100755 index 0000000..db51d34 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/_vectors.S @@ -0,0 +1,94 @@ +// _vectors.S -- Reference symbols to pull in all required vectors +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/_vectors.S#2 $ + +// Copyright (c) 2004, 2006-2007 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include /* for XSHAL_VECTORS_PACKED */ + +.global _ResetVector + +#if XCHAL_HAVE_EXCEPTIONS + +# if XCHAL_HAVE_DEBUG +.global _DebugExceptionVector +# endif + +.global _KernelExceptionVector +.global _UserExceptionVector + +# ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR +.global _DoubleExceptionVector +# endif + +# if XCHAL_HAVE_NMI +.global _NMIExceptionVector +# endif + +# if XCHAL_HAVE_WINDOWED +.global _WindowOverflow4 +.global _WindowUnderflow4 +.global _WindowOverflow8 +.global _WindowUnderflow8 +.global _WindowOverflow12 +.global _WindowUnderflow12 +# endif + +# if XCHAL_HAVE_MEM_ECC_PARITY +.global _MemErrorVector +# endif + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + + +#if (XCHAL_NUM_INTLEVELS >= 2) && (2 != XCHAL_DEBUGLEVEL) +.global _Level2Vector +#endif +#if (XCHAL_NUM_INTLEVELS >= 3) && (3 != XCHAL_DEBUGLEVEL) +.global _Level3Vector +#endif +#if (XCHAL_NUM_INTLEVELS >= 4) && (4 != XCHAL_DEBUGLEVEL) +.global _Level4Vector +#endif +#if (XCHAL_NUM_INTLEVELS >= 5) && (5 != XCHAL_DEBUGLEVEL) +.global _Level5Vector +#endif +#if (XCHAL_NUM_INTLEVELS >= 6) && (6 != XCHAL_DEBUGLEVEL) +.global _Level6Vector +#endif + +#if XCHAL_HAVE_VECBASE && XSHAL_VECTORS_PACKED +.global _RelocVectors +#endif + +/* These don't take up space: */ +.global xthals_hw_configid0 +.global xthals_hw_configid1 +.global xthals_release_major +.global xthals_release_minor + +/* The following allows this object file to be pulled in by reference: */ +.text +.global _xtos_vectors_ref_ +.set _xtos_vectors_ref_, 0 + + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/checkvecsize b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/checkvecsize new file mode 100755 index 0000000..ac02e5c --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/checkvecsize @@ -0,0 +1,71 @@ +# Script to check that vector code is 16 bytes or less +# $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/checkvecsize#2 $ + +# Copyright (c) 2001 Tensilica Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining +# a copy of this software and associated documentation files (the +# "Software"), to deal in the Software without restriction, including +# without limitation the rights to use, copy, modify, merge, publish, +# distribute, sublicense, and/or sell copies of the Software, and to +# permit persons to whom the Software is furnished to do so, subject to +# the following conditions: +# +# The above copyright notice and this permission notice shall be included +# in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +package Xtensa::checkvecsize; + +# Perl library modules +use strict; +use Getopt::Long; +use FileHandle; + +# Program + +use vars qw($objdump $maxsize); + +{ + $::myname = 'checkvecsize'; + + # command line + $maxsize = 16; + die("Usage is: $::myname -objdump prog [-maxsize n] files...\n") + unless &GetOptions("objdump=s" => \$objdump, + "maxsize=i" => \$maxsize) + && @ARGV > 0 && defined($objdump); + my $file; + foreach $file (@ARGV) { + checkvecsize ($file); + } +} + +sub checkvecsize { + my ($file) = @_; + my $od = new FileHandle "${objdump} -h $file|"; + die("$::myname: $!, opening pipe to $objdump -h $file.\n") + unless $od; + while (<$od>) { + if (/^\s*\d+\s+(\S+)\s+([0-9A-Fa-f]{8})\s/) { + my $size = hex($2); + die("$::myname: $file $1 section size is $size bytes.\n") + if $size > $maxsize; + } + } + $od->close(); +} + + +# Local Variables: +# mode:perl +# perl-indent-level:2 +# cperl-indent-level:2 +# End: diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt0-app.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt0-app.S new file mode 100755 index 0000000..78e63c2 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt0-app.S @@ -0,0 +1,165 @@ +// crt0-app.S +// Applications downloaded in RAM using a debug monitor (eg. XMON, RedBoot) +// start here at _app_reset. Such applications don't have any vectors: +// all exceptions are handled by the debug monitor. +// Thus, this file essentially plays the role of the reset vector +// to setup a few things before jumping to _start (in crt1*.S). + +// Copyright (c) 2005-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include + + +// Assumptions on entry to _app_reset: +// - debug monitor handles all exceptions, has setup all vectors +// - interrupt related state is initialized +// (interrupts disabled or enabled for debug monitor's purposes) +// - debug option related state is initialized (for debug monitor) +// - any MMU related state is initialized (all handled by debug monitor) +// - caches are initialized (cache attributes not necessarily correct) +// - entire application is loaded (no unpacking needed here) + +// Assumptions on exit from _app_reset, ie. when jumping to _start: +// - low (level-one) and medium priority interrupts are disabled +// - C calling context not initialized: +// - PS not fully initialized (eg. PS.WOE not set per ABI) +// - SP not initialized +// - the following are initialized: +// - LITBASE, WindowBase, WindowStart, LCOUNT, CPENABLE, FP's FCR and FSR, +// cache attributes + +/**************************************************************************/ + + .text + .global _app_reset +_app_reset: + /* _app_reset may be required to be located at the beginning of the text + segment. However, the constant pool for _app_reset must be placed + before the code. Jump over the constant pool to solve this. */ + j .LpastInitialConstants + + .literal_position // tells the assembler/linker to place literals here + +.LpastInitialConstants: + // Keep a0 zero. It is used to initialize a few things. + // It is also the return address, where zero indicates + // that the frame used by _start is the bottommost frame. + // + movi a0, 0 // keep this register zero. + +#if XCHAL_HAVE_LOOPS + wsr a0, LCOUNT // loop count = 0 +#endif /* XCHAL_HAVE_LOOPS */ + + // Interrupts might be enabled, make sure at least medium and low priority + // interrupts are disabled until WindowBase, WindowStart, SP, and the stack + // are all properly setup (which will happen outside this file, after the + // _start label). We leave loops enabled on new exception architecture. +#if XCHAL_HAVE_EXCEPTIONS + movi a2, XCHAL_EXCM_LEVEL + wsr a2, PS // set PS.INTLEVEL=EXCM_LEVEL, PS.WOE=0, PS.EXCM=0 + rsync +#endif + + // DO THIS FIRST: initialize the window start and base + // before, so that windows don't move under us. +#if XCHAL_HAVE_WINDOWED + // We do this even if we are assembling for the + // call0 abi, but it's not really needed. + movi a2, 1 + wsr a2, WINDOWSTART // window start = 1 + wsr a0, WINDOWBASE // window base = 0 + rsync + + // NOTE: a0 may no longer be zero here, because + // we wrote to WindowBase. So clear it again. + movi a0, 0 +#endif + + // Now, BEFORE we do any L32R (or MOVI with non-immediate + // range which results in an L32R), ensure LITBASE is set + // correctly. This is necessary for RAM applications loaded + // using a target-side debug monitor -- such applications + // don't have a reset vector and start execution at _start. + // (This part is unnecessary if running from a reset vector.) + // The target-side debug monitor might have set LITBASE to + // anything at all, so we cannot rely on its value here. +#if XCHAL_HAVE_ABSOLUTE_LITERALS + wsr a0, LITBASE // force PC-relative L32R + rsync +# if XSHAL_USE_ABSOLUTE_LITERALS + .begin no-absolute-literals // use PC-rel L32R to load + movi a2, _lit4_start + 0x40001 // address of absolute literals + .end no-absolute-literals // (see handlers/ResetVector.S + wsr a2, LITBASE // for explanation) + rsync +# endif +#endif + + + /* + * Enable the caches correctly for this board. + * We use the "safe" sequence. + * + * NOTE: We don't *initialize* the caches here, because the + * target debugger agent (debug monitor) has initialized them for us. + */ + movi a2, XTBOARD_CACHEATTR_DEFAULT + cacheattr_set /* set CACHEATTR from a2 (clobbers a3-a8) */ + + + + // Coprocessor option initialization +#if XCHAL_HAVE_CP + //movi a2, XCHAL_CP_MASK // enable existing CPs + // To allow creating new coprocessors using TC that are not known + // at GUI build time without having to explicitly enable them, + // all CPENABLE bits must be set, even though they may not always + // correspond to a coprocessor. + movi a2, 0xFF // enable *all* bits, to allow dynamic TIE + wsr a2, CPENABLE +#endif + + // Floating point coprocessor option initialization +#if XCHAL_HAVE_FP +# define FCR 232 /* floating-point control register (user register number) */ +# define FSR 233 /* floating-point status register (user register number) */ + rsync /* wait for WSR to CPENABLE to complete before accessing FP coproc state */ + wur a0, FCR /* clear FCR (default rounding mode, round-nearest) */ + wur a0, FSR /* clear FSR */ +#endif + + + /* NOTE: Future releases may clear BSS here rather than in the CRT1. */ + + + /* + * Now jump to the application. This is typically the + * C run-time initialization ("CRT") which in turn calls main(): + */ + movi a4, _start + jx a4 // jump to _start + + .size _app_reset, . - _app_reset + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt1-boards.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt1-boards.S new file mode 100755 index 0000000..1800b73 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt1-boards.S @@ -0,0 +1,237 @@ +// crt1-boards.S +// +// For most hardware / boards, this code sets up the C calling context +// (setting up stack, PS, and clearing BSS) and jumps to __clibrary_start +// which sets up the C library, calls constructors and registers destructors, +// and calls main(). +// +// Control arrives here at _start from the reset vector or from crt0-app.S. + +// Copyright (c) 1998-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include "xtos-internal.h" + + +// Exports +.global _start + +// Imports +// __clibrary_init from C library (eg. newlib or uclibc) +// exit from C library +// main from user application +// board_init board-specific (uart/mingloss/tinygloss.c) +// xthal_dcache_all_writeback from HAL library +// __stack from linker script (see LSP Ref Manual) +// _bss_table_start from linker script (see LSP Ref Manual) +// _bss_table_end from linker script (see LSP Ref Manual) + +.type main, @function + +// Macros to abstract away ABI differences + +#if __XTENSA_CALL0_ABI__ +# define CALL call0 +# define ARG1 a2 /* 1st outgoing call argument */ +# define ARG2 a3 /* 2nd outgoing call argument */ +# define ARG3 a4 /* 3rd outgoing call argument */ +# define ARG4 a5 /* 4th outgoing call argument */ +# define ARG5 a6 /* 5th outgoing call argument */ +#else +# define CALL call4 +# define ARG1 a6 /* 1st outgoing call argument */ +# define ARG2 a7 /* 2nd outgoing call argument */ +# define ARG3 a8 /* 3rd outgoing call argument */ +# define ARG4 a9 /* 4th outgoing call argument */ +# define ARG5 a10 /* 5th outgoing call argument */ +#endif + + +/**************************************************************************/ + + .text + .align 4 +_start: + // _start is typically NOT at the beginning of the text segment -- + // it is always called from either the reset vector or other code + // that does equivalent initialization (such as crt0-app.S). + // + // Assumptions on entry to _start: + // - low (level-one) and medium priority interrupts are disabled + // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to + // be zeroed, to potentially enable them, before calling main) + // - C calling context not initialized: + // - PS not initialized + // - SP not initialized + // - the following are initialized: + // - LITBASE, cache attributes, WindowBase, WindowStart, + // CPENABLE, FP's FCR and FSR, EXCSAVE[n] + + // Keep a0 zero. It is used to initialize a few things. + // It is also the return address, where zero indicates + // that the frame used by _start is the bottommost frame. + // +#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER // not needed for Xtensa TX + movi a0, 0 // keep this register zero. +#endif + +#if XTOS_RESET_UNNEEDED && !XCHAL_HAVE_HALT +#include "reset-unneeded.S" +#endif + + // Initialize the stack pointer. + // See the "ABI and Software Conventions" chapter in the + // Xtensa ISA Reference manual for details. + + // NOTE: Because the _start routine does not use any memory in its + // stack frame, and because all of its CALL instructions use a + // window size of 4 (or zero), the stack frame for _start can be empty. + + movi sp, __stack + + /* + * Now that sp (a1) is set, we can set PS as per the application + * (user vector mode, enable interrupts, enable window exceptions if applicable). + */ +#if XCHAL_HAVE_EXCEPTIONS +# ifdef __XTENSA_CALL0_ABI__ + movi a3, PS_UM // PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 +# else + movi a3, PS_UM|PS_WOE // PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 +# endif + wsr a3, PS + rsync +#endif + + +#if !XCHAL_HAVE_BOOTLOADER /* boot loader takes care of zeroing BSS */ + /* + * Clear the BSS (uninitialized data) segments. + * This code supports multiple zeroed sections (*.bss). + * + * Register allocation: + * a0 = 0 + * a6 = pointer to start of table, and through table + * a7 = pointer to end of table + * a8 = start address of bytes to be zeroed + * a9 = end address of bytes to be zeroed + * a10 = length of bytes to be zeroed + */ + movi a6, _bss_table_start + movi a7, _bss_table_end + bgeu a6, a7, .L3zte + +.L0zte: l32i a8, a6, 0 // get start address, assumed multiple of 4 + l32i a9, a6, 4 // get end address, assumed multiple of 4 + addi a6, a6, 8 // next entry + sub a10, a9, a8 // a10 = length, assumed a multiple of 4 + bbci.l a10, 2, .L1zte + s32i a0, a8, 0 // clear 4 bytes to make length multiple of 8 + addi a8, a8, 4 +.L1zte: bbci.l a10, 3, .L2zte + s32i a0, a8, 0 // clear 8 bytes to make length multiple of 16 + s32i a0, a8, 4 + addi a8, a8, 8 +.L2zte: srli a10, a10, 4 // length is now multiple of 16, divide by 16 + floopnez a10, clearzte + s32i a0, a8, 0 // clear 16 bytes at a time... + s32i a0, a8, 4 + s32i a0, a8, 8 + s32i a0, a8, 12 + addi a8, a8, 16 + floopend a10, clearzte + + bltu a6, a7, .L0zte // loop until end of table of *.bss sections +.L3zte: +#endif + + + // We can now call C code, the C calling environment has been initialized. + // + // From this point on, we use ABI-specific macros to refer to registers a0 .. a15 + // (ARG#). + + +#if XCHAL_HAVE_HALT + + // Assume minimalist environment for memory-constrained TX cores. + // No C library or board initialization, no parameters passed to main + // (assume declared as "void main(void)") and no call to exit(). + + CALL main + halt + +#else /* !HALT */ + + .type board_init, @function + .type __clibrary_init, @function + .type exit, @function + + + // Initialize the board (eg. the UART on the XT2000). + CALL board_init + + /* + * Call __clibrary_init to initialize the C library: + * + * void __clibrary_init(int argc, char ** argv, char ** environ, + * void(*init_func)(void), void(*fini_func)(void)); + */ + + // Pass an empty argv array, with an empty string as the program name. + + movi ARG1, _start_argc // argc address + movi ARG2, _start_argv // argv = ["", 0] + movi ARG3, _start_envp // envp = [0] + movi ARG4, _init // function that calls constructors + movi ARG5, _fini // function that calls destructors + l32i ARG1, ARG1, 0 // argc = 1 + CALL __clibrary_init + + // Call: int main(int argc, char ** argv, char ** environ); + movi ARG1, _start_argc // argc address + movi ARG2, _start_argv // argv = ["", 0] + movi ARG3, _start_envp // envp = [0] + l32i ARG1, ARG1, 0 // argc = 1 + CALL main + // The return value is the same register as the first outgoing argument. + CALL exit // exit with main's return value + // Does not return here. + + .data + // Mark argc/argv/envp parameters as weak so that an external + // object file can override them. + .weak _start_argc, _start_argv, _start_envp + .align 4 +_start_argv: + .word _start_null // empty program name +_start_null: +_start_envp: + .word 0 // end of argv array, empty string, empty environ +_start_argc: + .word 1 // one argument (program name) + .text + +#endif /* !HALT */ + + .size _start, . - _start + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt1-sim.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt1-sim.S new file mode 100755 index 0000000..5615931 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt1-sim.S @@ -0,0 +1,246 @@ +// crt1-sim.S +// For the Xtensa simulator target, this code sets up the C calling context +// and calls main() (via __clibrary_start). +// Control arrives here at _start from the reset vector or from crt0-app.S. + +// Copyright (c) 1998-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include +#include "xtos-internal.h" + + +// Exports +.global _start + +// Imports +// __clibrary_init from C library (eg. newlib or uclibc) +// exit from C library +// main from user application +// __stack from linker script (see LSP Ref Manual) + +.type __clibrary_init, @function +.type main, @function +.type exit, @function + + +// Macros to abstract away ABI differences + +#if __XTENSA_CALL0_ABI__ +# define CALL call0 +# define ARG1 a2 /* 1st outgoing call argument */ +# define ARG2 a3 /* 2nd outgoing call argument */ +# define ARG3 a4 /* 3rd outgoing call argument */ +# define ARG4 a5 /* 4th outgoing call argument */ +# define ARG5 a6 /* 5th outgoing call argument */ +#else +# define CALL call4 +# define ARG1 a6 /* 1st outgoing call argument */ +# define ARG2 a7 /* 2nd outgoing call argument */ +# define ARG3 a8 /* 3rd outgoing call argument */ +# define ARG4 a9 /* 4th outgoing call argument */ +# define ARG5 a10 /* 5th outgoing call argument */ +#endif + + .data + .weak _start_envp // allow overriding + .align 4 +_start_envp: .word 0 // empty environ + + + + .text + .align 4 + +_start: + // _start is typically NOT at the beginning of the text segment -- + // it is always called from either the reset vector or other code + // that does equivalent initialization (such as crt0-app.S). + // + // Assumptions on entry to _start: + // - low (level-one) and medium priority interrupts are disabled + // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to + // be zeroed, to potentially enable them, before calling main) + // - C calling context not initialized: + // - PS not initialized + // - SP not initialized + // - the following are initialized: + // - LITBASE, cache attributes, WindowBase, WindowStart, + // CPENABLE, FP's FCR and FSR, EXCSAVE[n] + + // Keep a0 zero. It is used to initialize a few things. + // It is also the return address, where zero indicates + // that the frame used by _start is the bottommost frame. + // + movi a0, 0 // keep this register zero. + +#if XTOS_RESET_UNNEEDED +#include "reset-unneeded.S" +#endif + + + // Initialize the stack pointer. + // See the "ABI and Software Conventions" chapter in the + // Xtensa ISA Reference manual for details. + + // NOTE: Because the _start routine does not use any memory in its + // stack frame, and because all of its CALL instructions use a + // window size of 4, the stack frame for _start can be empty. + movi sp, __stack + + // reserve stack space for + // - argv array + // - argument strings + movi a2, SYS_iss_argv_size + simcall // returns size of argv[] + its strings in a2 +#if XCHAL_HAVE_PIF + // The stack only needs 16-byte alignment. + // However, here we round up the argv size further to 128 byte multiples + // so that in most cases, variations in argv[0]'s path do not result in + // different stack allocation. Otherwise, such variations can impact + // execution timing (eg. due to cache effects etc) for the same code and data. + // If we have a PIF, it's more likely the extra required space is okay. + addi a2, a2, 127 + srli a2, a2, 7 + slli a2, a2, 7 +#else + // Keep stack 16-byte aligned. + addi a2, a2, 15 + srli a2, a2, 4 + slli a2, a2, 4 +#endif + // No need to use MOVSP because we have no caller (we're the + // base caller); in fact it's better not to use MOVSP in this + // context, to avoid unnecessary ALLOCA exceptions and copying + // from undefined memory: + // sub a3, sp, a2 + // movsp sp, a3 + sub sp, sp, a2 + + + /* + * Now that sp (a1) is set, we can set PS as per the application + * (user vector mode, enable interrupts, enable window exceptions if applicable). + */ +#if XCHAL_HAVE_EXCEPTIONS +# ifdef __XTENSA_CALL0_ABI__ + movi a3, PS_UM // PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 +# else + movi a3, PS_UM|PS_WOE // PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 +# endif + wsr a3, PS + rsync +#endif + + + /* The new ISS simcall only appeared after RB-2007.2: */ +#if !XCHAL_HAVE_BOOTLOADER && (XCHAL_HW_MAX_VERSION > XTENSA_HWVERSION_RB_2007_2) /* pre-LX2 cores only */ + /* + * Clear the BSS (uninitialized data) segments. + * This code supports multiple zeroed sections (*.bss). + * For speed, we clear memory using an ISS simcall + * (see crt1-boards.S for more generic BSS clearing code). + */ + movi a6, _bss_table_start + movi a7, _bss_table_end + bgeu a6, a7, .Lnobss +.Lbssloop: + movi a2, SYS_memset + l32i a3, a6, 0 // arg1 = fill start address + movi a4, 0 // arg2 = fill pattern + l32i a5, a6, 4 // get end address + addi a6, a6, 8 // next bss table entry + sub a5, a5, a3 // arg3 = fill size in bytes + simcall // memset(a3,a4,a5) + bltu a6, a7, .Lbssloop // loop until end of bss table +.Lnobss: +#endif + + + /* + * Call __clibrary_init to initialize the C library: + * + * void __clibrary_init(int argc, char ** argv, char ** environ, + * void(*init_func)(void), void(*fini_func)(void)); + */ + + // Get argv with the arguments from the ISS + mov a3, sp // tell simcall where to write argv[] + movi a2, SYS_iss_set_argv + simcall // write argv[] array at a3 + + movi a2, SYS_iss_argc + simcall // put argc in a2 + + +// Alternative smaller code for Xtensa TX. +// Many starting with simulation assume a full C env, so NOT DONE FOR NOW. +// +//#if XCHAL_HAVE_HALT +// +// // Assume minimalist environment for memory-constrained TX cores. +// // No C library or board initialization, and no call to exit(). +// // However, in the interest of software regressions, for now we +// // still pass parameters to main (but not the rarely used envp). +// +// //mov ARG1, a2 // argc already in a2. +// mov ARG2, sp // argv +// CALL main +// halt +// +//#else /* !HALT */ +// ... + + +#if __XTENSA_CALL0_ABI__ + mov a12, a2 // save argc (a2 is ARG1) +#else + mov ARG1, a2 // argc +#endif + mov ARG2, sp // argv + movi ARG3, _start_envp // envp + movi ARG4, _init // _init + movi ARG5, _fini // _fini + CALL __clibrary_init + + // Call: int main(int argc, char ** argv, char ** environ); +#if __XTENSA_CALL0_ABI__ + mov ARG1, a12 // argc +#else + mov ARG1, a2 // argc +#endif + mov ARG2, sp // argv + movi ARG3, _start_envp // envp = [0] + CALL main + // The return value is the same register as the first outgoing argument. + CALL exit // exit with main's return value + // Does not return here. + + .size _start, . - _start + + +// Local Variables: +// mode:fundamental +// comment-start: "// " +// comment-start-skip: "// *" +// End: diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt1-tiny.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt1-tiny.S new file mode 100755 index 0000000..58fe9f9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/crt1-tiny.S @@ -0,0 +1,122 @@ +// crt1-tiny.S +// +// This is a reduced version of the code in crt1-boards.S . +// For most hardware / boards, this code sets up the C calling context +// (setting up stack, PS, and clearing BSS) and calls main(). +// It has some limitations (see LSP Ref Manual for details) such as: +// - does not setup the C library (...) +// - does not call C++ static constructors and destructors +// - only clears .bss , not other *.bss sections +// +// Control arrives here at _start from the reset vector or from crt0-app.S. + +// Copyright (c) 1998-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include + + +// Imports +// __stack from linker script (see LSP Ref Manual) +// _bss_start from linker script (see LSP Ref Manual) +// _bss_end from linker script (see LSP Ref Manual) +// main from user application + + + +#ifdef __XTENSA_CALL0_ABI__ +# define CALL call0 +#else +# define CALL call4 +#endif + + +/**************************************************************************/ + + .text + .global _start +_start: + // _start is typically NOT at the beginning of the text segment -- + // it is always called from either the reset vector or other code + // that does equivalent initialization (such as crt0-app.S). + // See crt1-boards.S for assumptions on entry to _start , + // and for comments on what is being done in this file. + +#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER // not needed for Xtensa TX + movi a0, 0 // mark base of call stack +#endif + + movi sp, __stack // setup the stack + +#if XCHAL_HAVE_EXCEPTIONS +# ifdef __XTENSA_CALL0_ABI__ + movi a3, PS_UM // PS: WOE=0, UM=1, EXCM=0, INTLEVEL=0 +# else + movi a3, PS_UM|PS_WOE // PS: WOE=1, UM=1, EXCM=0, INTLEVEL=0 +# endif + wsr a3, PS // setup PS for the application + rsync +#endif + + + // Clear the BSS (uninitialized data) segment. + // + // This code only supports .bss, not multiple *.bss sections. + // Corresponding code in crt1-boards.S does, and is faster but bigger. + +#if !XCHAL_HAVE_BOOTLOADER + movi a6, _bss_start + movi a7, _bss_end + bgeu a6, a7, 2f +1: s32i a0, a6, 0 + addi a6, a6, 4 + bltu a6, a7, 1b +2: +#endif + + // We can now call C code, the C calling environment is initialized. + // This tiny C runtime assumes main is declared as "void main(void)" + // rather than with the usual argc,argv. So there are no arguments. + + CALL main + + // In this tiny C runtime, main() is not expected to return. + // If it does, just loop forever. + + //CALL xthal_dcache_all_writeback // sync dirty dcaches to memory + //extw // sync TIE queues/ports/etc (LX or later only) + +.L0: +#if XCHAL_HAVE_DEBUG + break 1, 15 // give control to debugger +#elif XCHAL_HAVE_HALT + halt +#endif + j .L0 + + .size _start, . - _start + + +// Local Variables: +// mode:fundamental +// comment-start: "// " +// comment-start-skip: "// *" +// End: diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/debug-vector.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/debug-vector.S new file mode 100755 index 0000000..35fb1be --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/debug-vector.S @@ -0,0 +1,65 @@ +// debug-vector.S -- Debug Exception Vector +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/debug-vector.S#3 $ + +// Copyright (c) 2003-2004, 2006, 2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#ifdef SIMULATOR +#include +#endif + +#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS + + // This code goes at the debug exception vector + + .begin literal_prefix .DebugExceptionVector + .section .DebugExceptionVector.text, "ax" + .align 4 + .global _DebugExceptionVector +_DebugExceptionVector: + +# ifdef SIMULATOR + // In the simulator (ISS), let the debugger (if any is attached) + // handle the debug exception, else simply stop the simulation: + // + wsr a2, EXCSAVE+XCHAL_DEBUGLEVEL // save a2 where simulator expects it + movi a2, SYS_gdb_enter_sktloop + simcall // have ISS handle the debug exception +# else + // For hardware, this code does not handle debug exceptions. + // To implement a target-side debug monitor, replace this + // vector with a real one that uses target-specific facilities + // to communicate with the debugger. + // +1: +#if XCHAL_HAVE_INTERRUPTS + waiti XCHAL_DEBUGLEVEL // unexpected debug exception, loop in low-power mode +#endif + j 1b // infinite loop - unexpected debug exception +# endif /*!SIMULATOR*/ + + .end literal_prefix + .size _DebugExceptionVector, . - _DebugExceptionVector + +#endif /* XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/deprecated.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/deprecated.S new file mode 100755 index 0000000..2eb2af3 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/deprecated.S @@ -0,0 +1,120 @@ +// deprecated.S -- Deprecated assembler functions + +// Copyright (c) 2003-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" + + + + .text + +/* + void _xtos_timer__delta(int cycles) + + Set the timer from the current ccount. + DEPRECATED. PLEASE USE xthal_set_ccompare() AND xthal_get_ccount() + INSTEAD, OR USE DIFFERENT ALGORITHM THAT UPDATES CCOMPAREn RELATIVE TO + LAST CCOMPAREn FOR DRIFT-FREE PERIODIC TIMER INTERRUPTS. +*/ + .macro define_timer_delta num, numtimers + .if ((\num-\numtimers) & ~0xFFF) // num < numtimers ? + .align 4 + .global _xtos_timer_&num&_delta + .type _xtos_timer_&num&_delta,@function +_xtos_timer_&num&_delta: + abi_entry + rsr a3, CCOUNT + add a3, a3, a2 + wsr a3, CCOMPARE_0+&num& + abi_return + .size _xtos_timer_&num&_delta, . - _xtos_timer_&num&_delta + .endif + .endm + + + +#if defined(__SPLIT__t0_delta) + + define_timer_delta 0, XCHAL_NUM_TIMERS + +#elif defined(__SPLIT__t1_delta) + + define_timer_delta 1, XCHAL_NUM_TIMERS + +#elif defined(__SPLIT__t2_delta) + + define_timer_delta 2, XCHAL_NUM_TIMERS + +#elif defined(__SPLIT__t3_delta) + + define_timer_delta 3, XCHAL_NUM_TIMERS + + +#elif defined(__SPLIT__read_ints) + + // + // u32 _xtos_read_ints( void ) + // + // _xtos_read_ints() reads the INTERRUPT register and returns it. + // DEPRECATED. PLEASE USE xthal_get_interrupt() INSTEAD. + // [Kept temporarily because it was documented in T1050 System SW Ref Manual.] + // + .text + .align 4 + .global _xtos_read_ints + .type _xtos_read_ints,@function +_xtos_read_ints: + abi_entry +#if XCHAL_HAVE_INTERRUPTS + rsr a2, INTERRUPT +#else /*XCHAL_HAVE_INTERRUPTS*/ + movi a2, 0 +#endif /*XCHAL_HAVE_INTERRUPTS*/ + abi_return + .size _xtos_read_ints, . - _xtos_read_ints + + +#elif defined(__SPLIT__clear_ints) + + // + // void _xtos_clear_ints( u32 mask ) + // + // _xtos_clear_ints() clears selected bits of the INTERRUPT register. + // DEPRECATED. PLEASE USE xthal_set_intclear() INSTEAD. + // [Kept temporarily because it was documented in T1050 System SW Ref Manual.] + // + .text + .align 4 + .global _xtos_clear_ints + .type _xtos_clear_ints,@function +_xtos_clear_ints: + abi_entry +#if XCHAL_HAVE_INTERRUPTS + wsr a2, INTCLEAR +#endif /*XCHAL_HAVE_INTERRUPTS*/ + abi_return + .size _xtos_clear_ints, . - _xtos_clear_ints + +#endif /* splitting */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/double-vector.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/double-vector.S new file mode 100755 index 0000000..ad96144 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/double-vector.S @@ -0,0 +1,98 @@ +// double-vector.S -- Double Exception Vector +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/double-vector.S#3 $ + +// Copyright (c) 2000-2004, 2006, 2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include +#ifdef SIMULATOR +#include +#endif + + +#if XCHAL_HAVE_EXCEPTIONS && defined(XCHAL_DOUBLEEXC_VECTOR_VADDR) + +/* + * This is a very minimalist implementation of the double + * exception vector. For XEA2 configurations without a + * full MMU, this vector is only expected to be executed + * upon fatal errors (exceptions that occur within critical + * sections of exception vectors and handlers). + * + * For configurations with a full MMU (ie. with TLBs and + * auto-refill) and the windowed address registers option, + * a more complete version of this handler is necessary if: + * dynamic page mapping is implemented, and the stack + * can ever point to a dynamically mapped area. + * In this case, a double exception is a normal occurrence + * when a stack access within a window handler causes + * a TLB miss exception or other expected MMU fault. + * XTOS does not support this scenario, hence a minimalist + * double exception vector is sufficient. + */ + + .begin literal_prefix .DoubleExceptionVector + .section .DoubleExceptionVector.text, "ax" + + .align 4 + .global _DoubleExceptionVector +_DoubleExceptionVector: +# if XCHAL_HAVE_DEBUG +1: break 1,4 // unhandled double exception +# elif defined(SIMULATOR) + wsr a2, EXCSAVE1 // save a2 where simulator expects it + movi a2, SYS_unhandled_double_exc +1: simcall // let simulator/debugger report unhandled exception +# else +1: +# endif + j 1b // infinite loop + + // NOTE: a non-minimalist vector may choose to + // process the double exception in the vector itself + // (by default, much more space is allocated to double + // exception vectors than to most other vectors); + // or, to jump to a double exception handler located + // elsewhere. If only the normal case of double + // exceptions occurring within a window handler is + // being handled, then it is safe to use EXCSAVE_1 to + // do this jump (window handlers don't use EXCSAVE_1). + // For example: + // + // wsr a0, EXCSAVE_1 + // movi a0, _DoubleExceptionFromVector + // jx a0 + // + // .text + // .align 4 + // .global _DoubleExceptionFromVector + //_DoubleExceptionFromVector: + // ... + + + .size _DoubleExceptionVector, . - _DoubleExceptionVector + .text + .end literal_prefix + +#endif /* have double exceptions */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-alloca-handler.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-alloca-handler.S new file mode 100755 index 0000000..34a9a6e --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-alloca-handler.S @@ -0,0 +1,273 @@ +// exc-alloca-handler.S - ALLOCA cause exception assembly-level handler +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/exc-alloca-handler.S#3 $ + +// Copyright (c) 2002-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +/* + * Code written to the windowed ABI must use the MOVSP instruction to modify + * the stack pointer (except for startup code, which doesn't have a caller). + * The compiler uses MOVSP to allocate very large or variable size stack frames. + * MOVSP guarantees that the caller frame's a0-a3 registers, stored below the + * stack pointer, are moved atomically with respect to interrupts and exceptions + * to satisfy windowed ABI requirements. When user code executes the MOVSP + * instruction and the caller frame is on the stack rather than in the register + * file, the processor takes an ALLOCA exception. The ALLOCA exception handler + * moves the caller frame's a0-a3 registers to follow the stack pointer. + * This file implements this ALLOCA exception handler. + * + * Code written in C can generate a MOVSP in four situations: + * + * 1. By calling "alloca": + * + * void foo(int array_size) { + * char * bar = alloca(array_size); + * ... + * + * 2. By using variable sized arrays (a GNU C extension): + * + * void foo(int array_size) { + * char bar[array_size]; + * ... + * + * 3. By using nested C functions (also a GNU C extension): + * + * void afunction(void) { + * ... + * int anotherfunction(void) { + * } + * ... + * + * 4. By using very large amounts of stack space in a single function. The exact + * limit is 32,760 bytes (including 16-48 bytes of caller frame overhead). + * Typically, users don't encounter this limit unless they have functions + * that locally declare large arrays, for example: + * + * void foo(void) { + * int an_array[8192]; // 32,768 bytes + * int another_array[100]; // 400 bytes + * ... + * + * + * NOTE: This handler only works when MOVSP's destination register is the stack + * pointer "a1" (synonym with "sp"), i.e. "MOVSP a1, ". This is the only + * meaningful form of MOVSP in the windowed ABI, and the only form generated + * by the compiler and used in assembly. The code below does not check the + * destination register, so other forms of MOVSP cause unexpected behaviour. + */ + +#include +#include +#include "xtos-internal.h" + +#define ERROR_CHECKING 1 // define as 0 to save a few bytes + + +#if XCHAL_HAVE_EXCEPTIONS + +//Vector: +// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc. +// s32i a2, a1, UEXC_a2 +// s32i a3, a1, UEXC_a3 +// movi a3, _xtos_exc_handler_table +// rsr a2, EXCCAUSE +// addx4 a2, a2, a3 +// l32i a2, a2, 0 +// s32i a4, a1, UEXC_a4 +// jx a2 // jump to cause-specific handler + + .global _need_user_vector_ // pull-in real user vector (tiny LSP) + + .text + .align 4 + .global _xtos_alloca_handler +_xtos_alloca_handler: +#if !XCHAL_HAVE_WINDOWED || defined(__XTENSA_CALL0_ABI__) + rfe_rfue +#else /* we have windows w/o call0 abi */ + // HERE: a2, a3, a4 have been saved to + // exception stack frame allocated with a1 (sp). + // a2 contains EXCCAUSE. + // (12 cycles from vector to here, assuming cache hits, 5-stage pipe, etc) + + /* + * Skip the MOVSP instruction so we don't execute it again on return: + */ + + rsr a3, EPC_1 // load instruction address (PC) + s32i a5, a1, UEXC_a5 // save a5 + addi a2, a3, 3 // increment PC to skip MOVSP instruction +#if XCHAL_HAVE_LOOPS + /* + * If the MOVSP instruction is the last instruction in the body of + * a zero-overhead loop that must be executed again, then decrement + * the loop count and resume execution at the head of the loop. + */ + rsr a4, LEND + rsr a5, LCOUNT + bne a4, a2, 1f // done unless next-PC matches LEND + beqz a5, 1f // if LCOUNT zero, not in loop + addi a5, a5, -1 // z.o. loopback! decrement LCOUNT... + wsr a5, LCOUNT + rsr a2, LBEG // PC back to start of loop +#endif /*XCHAL_HAVE_LOOPS*/ +1: wsr a2, EPC_1 // update return PC past MOVSP + + /* + * Figure out what register MOVSP is moving from ('s' field, 2nd byte). + * If MOVSP is in an instruction RAM or ROM, we can only access it with + * 32-bit loads. So use shifts to read the byte from a 32-bit load. + */ + + addi a3, a3, 1 // advance to byte containing 's' field + extui a2, a3, 0, 2 // get bits 0 and 1 of address of this byte + sub a3, a3, a2 // put address on 32-bit boundary + l32i a3, a3, 0 // get word containing byte (can't use l8ui on IRAM/IROM) + rsr a4, SAR // save SAR + // NOTE: possible addition here: verify destination register is indeed a1. +# if XCHAL_HAVE_BE + ssa8b a2 + sll a3, a3 + extui a3, a3, 28, 4 // extract source register number +# else + ssa8l a2 + srl a3, a3 + extui a3, a3, 0, 4 // extract source register number +# endif + wsr a4, SAR // restore SAR + // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, no zoloops, etc) + + movi a4, .Ljmptable // jump table + mov a5, a1 // save the exception stack frame ptr in a5 + addi a1, a1, ESF_TOTALSIZE // restore a1 (in case of MOVSP a1,a1) + +# if XCHAL_HAVE_DENSITY + addx4 a4, a3, a4 // index by src reg number * 4 +# define ALIGN .align 4 // 4-byte jmptable entries +# define MOV _mov.n +# define L32I _l32i.n +# define DONE _bnez.n a4, .Lmove_save_area // a4 known non-zero +# else + addx8 a4, a3, a4 // index by src reg number * 8 +# define ALIGN .align 8 // 8-byte jmptable entries +# define MOV mov +# define L32I l32i +# define DONE j .Lmove_save_area +# endif + + jx a4 // jump into the following table + + ALIGN +.Ljmptable: MOV a1, a0 ; DONE // MOVSP a1, a0 + ALIGN ; DONE // MOVSP a1, a1 + ALIGN ; L32I a1, a5, UEXC_a2 ; DONE // MOVSP a1, a2 + ALIGN ; L32I a1, a5, UEXC_a3 ; DONE // MOVSP a1, a3 + ALIGN ; L32I a1, a5, UEXC_a4 ; DONE // MOVSP a1, a4 + ALIGN ; L32I a1, a5, UEXC_a5 ; DONE // MOVSP a1, a5 + ALIGN ; MOV a1, a6 ; DONE // MOVSP a1, a6 + ALIGN ; MOV a1, a7 ; DONE // MOVSP a1, a7 + ALIGN ; MOV a1, a8 ; DONE // MOVSP a1, a8 + ALIGN ; MOV a1, a9 ; DONE // MOVSP a1, a9 + ALIGN ; MOV a1, a10 ; DONE // MOVSP a1, a10 + ALIGN ; MOV a1, a11 ; DONE // MOVSP a1, a11 + ALIGN ; MOV a1, a12 ; DONE // MOVSP a1, a12 + ALIGN ; MOV a1, a13 ; DONE // MOVSP a1, a13 + ALIGN ; MOV a1, a14 ; DONE // MOVSP a1, a14 + ALIGN ; MOV a1, a15 // MOVSP a1, a15 + +.Lmove_save_area: + // Okay. a1 now contains the new SP value. + +# if ERROR_CHECKING + // Verify it is sensible: + extui a3, a1, 0, 2 // verify that new SP is 4-byte aligned + beqz a3, 1f // if so, skip fixup + +// .global _xtos_misaligned_movsp // make label visible for debugging +//_xtos_misaligned_movsp: +# if XCHAL_HAVE_DEBUG + break 1, 15 // break into debugger (if any) +# endif + sub a1, a1, a3 // FORCE alignment of the new pointer (!) +1: +# endif + +# if XCHAL_HAVE_XEA2 + addi a2, a5, ESF_TOTALSIZE // compute a2 = old SP +# else /*XEA1:*/ + addi a2, a5, ESF_TOTALSIZE-16 // compute a2 = old SP's save area +# endif + // Does new SP (in a1) overlap with exception stack frame (in a5)?: + movi a4, ESF_TOTALSIZE // size of exception stack frame + sub a3, a1, a5 // distance from ESF ptr to new SP + bgeu a3, a4, 1f // does new SP overlap ESF? branch if not + // Move ESF down so it doesn't overlap with the new register save area: + // (a1 = current ESF, a2 = new SP, a4 = ESF_TOTALSIZE) + sub a5, a5, a4 // shift down ESF (by ESF size) + l32i a3, a5, UEXC_a2+ESF_TOTALSIZE + l32i a4, a5, UEXC_a3+ESF_TOTALSIZE + s32i a3, a5, UEXC_a2 + s32i a4, a5, UEXC_a3 + l32i a3, a5, UEXC_a4+ESF_TOTALSIZE + l32i a4, a5, UEXC_a5+ESF_TOTALSIZE + s32i a3, a5, UEXC_a4 + s32i a4, a5, UEXC_a5 +1: + + // Move the register save area (from old SP to new SP): +# if XCHAL_HAVE_XEA2 + l32e a3, a2, -16 + l32e a4, a2, -12 + s32e a3, a1, -16 + s32e a4, a1, -12 + l32e a3, a2, -8 + l32e a4, a2, -4 + s32e a3, a1, -8 + s32e a4, a1, -4 +# else /*XEA1:*/ + addi a1, a1, -16 // point to new save area + l32i a3, a2, 0 + l32i a4, a2, 4 + s32i a3, a1, 0 + s32i a4, a1, 4 + l32i a3, a2, 8 + l32i a4, a2, 12 + s32i a3, a1, 8 + s32i a4, a1, 12 + addi a1, a1, 16 // back to correct new SP +# endif /*XEA1*/ + // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, etc) + + // Restore a2, a3, a4, a5, and return: + l32i a2, a5, UEXC_a2 + l32i a3, a5, UEXC_a3 + l32i a4, a5, UEXC_a4 + l32i a5, a5, UEXC_a5 + rfe_rfue + // (+?? cycles max above = ?? cycles, assuming cache hits, 5-stage pipe, etc) + + +#endif /* !XCHAL_HAVE_WINDOWED || __XTENSA_CALL0_ABI */ + + .size _xtos_alloca_handler, . - _xtos_alloca_handler + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-c-wrapper-handler.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-c-wrapper-handler.S new file mode 100755 index 0000000..b5a0e34 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-c-wrapper-handler.S @@ -0,0 +1,400 @@ +// exc-c-wrapper-handler.S - General Exception Handler that Dispatches C Handlers + +// Copyright (c) 2002-2004, 2006-2007, 2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include +#include "xtos-internal.h" +#ifdef SIMULATOR +#include +#endif + +#if XCHAL_HAVE_EXCEPTIONS + + +/* + * This assembly-level handler causes the associated exception (usually causes 12-15) + * to be handled as if it were exception cause 3 (load/store error exception). + * This provides forward-compatibility with a possible future split of the + * load/store error cause into multiple more specific causes. + */ + .align 4 + .global _xtos_cause3_handler +_xtos_cause3_handler: + movi a2, EXCCAUSE_LOAD_STORE_ERROR + j _xtos_c_wrapper_handler + .size _xtos_cause3_handler, . - _xtos_cause3_handler + + + +/* + * This is the general exception assembly-level handler that dispatches C handlers. + */ + .align 4 + .global _xtos_c_wrapper_handler +_xtos_c_wrapper_handler: + + // HERE: a2, a3, a4 have been saved to exception stack frame allocated with a1 (sp). + // a2 contains EXCCAUSE. + s32i a5, a1, UEXC_a5 // a5 will get clobbered by ENTRY after the pseudo-CALL4 + // (a4..a15 spilled as needed; save if modified) + + //NOTA: Possible future improvement: + // keep interrupts disabled until we get into the handler, such that + // we don't have to save other critical state such as EXCVADDR here. + //rsr a3, EXCVADDR + s32i a2, a1, UEXC_exccause + //s32i a3, a1, UEXC_excvaddr + +#if XCHAL_HAVE_XEA1 +# if XCHAL_HAVE_INTERRUPTS + rsilft a3, 1, XTOS_LOCKLEVEL // lockout + rsr a2, INTENABLE + //movi a3, ~XCHAL_EXCM_MASK + movi a3, ~XTOS_LOCKOUT_MASK // mask out low and medium priority levels, and high priority levels covered by + // XTOS_LOCKLEVEL if any, so we can run at PS.INTLEVEL=0 while manipulating INTENABLE + s32i a2, a1, UEXC_sar // (temporary holding place for INTENABLE value to restore after pseudo-CALL4 below) + and a3, a2, a3 // mask out selected interrupts + wsr a3, INTENABLE // disable all interrupts up to and including XTOS_LOCKLEVEL +# endif + movi a3, PS_WOE|PS_CALLINC(1)|PS_UM // WOE=1, UM=1, INTLEVEL=0, CALLINC=1 (call4 emul), OWB=(dontcare)=0 + + // NOTE: could use XSR here if targeting T1040 or T1050 hardware (requiring slight sequence adjustment as for XEA2): + rsr a2, PS + rsync //NOT-ISA-DEFINED // wait for WSR to INTENABLE to complete before clearing PS.INTLEVEL + wsr a3, PS // PS.INTLEVEL=0, effective INTLEVEL (via INTENABLE) is XTOS_LOCKLEVEL + + // HERE: window overflows enabled, but NOT SAFE because we're not quite + // in a valid windowed context (haven't restored a1 yet...); + // so don't cause any (keep to a0..a3) until we've saved critical state and restored a1: + + // NOTE: MUST SAVE EPC1 before causing any overflows, because overflows corrupt EPC1. + rsr a3, EPC_1 + s32i a2, a1, UEXC_ps + s32i a3, a1, UEXC_pc + +#else /* !XEA1 */ + + // Set PS fields: + // EXCM = 0 + // WOE = __XTENSA_CALL0_ABI__ ? 0 : 1 + // UM = 1 + // INTLEVEL = EXCM_LEVEL = 1 + // CALLINC = __XTENSA_CALL0_ABI__ ? 0 : 1 + // OWB = 0 (really, a dont care if !__XTENSA_CALL0_ABI__) + +# ifdef __XTENSA_CALL0_ABI__ + movi a2, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) +# else + movi a2, PS_WOE|PS_CALLINC(1)|PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) // CALL4 emulation +# endif + rsr a3, EPC_1 + xsr a2, PS + + // HERE: window overflows enabled, but NOT SAFE because we're not quite + // in a valid windowed context (haven't restored a1 yet...); + // so don't cause any (keep to a0..a3) until we've saved critical state and restored a1: + + // NOTE: MUST SAVE EPC1 before causing any overflows, because overflows corrupt EPC1. + s32i a3, a1, UEXC_pc + s32i a2, a1, UEXC_ps +#endif + +#ifdef __XTENSA_CALL0_ABI__ + + s32i a0, a1, UEXC_a0 // save the rest of the registers + s32i a6, a1, UEXC_a6 + s32i a7, a1, UEXC_a7 + s32i a8, a1, UEXC_a8 + s32i a9, a1, UEXC_a9 + s32i a10, a1, UEXC_a10 + s32i a11, a1, UEXC_a11 + s32i a12, a1, UEXC_a12 + s32i a13, a1, UEXC_a13 + s32i a14, a1, UEXC_a14 + s32i a15, a1, UEXC_a15 +# if XTOS_DEBUG_PC + // TODO: setup return PC for call traceback through interrupt dispatch +# endif + + rsync // wait for WSR to PS to complete + +#else /* ! __XTENSA_CALL0_ABI__ */ + +# if XTOS_CNEST + l32i a2, a1, ESF_TOTALSIZE-20 // save nested-C-func call-chain ptr +# endif + addi a1, a1, ESF_TOTALSIZE // restore sp (dealloc ESF) for sane stack again + rsync // wait for WSR to PS to complete + + /* HERE: we can SAFELY get window overflows. + * + * From here, registers a4..a15 automatically get spilled if needed. + * They become a0..a11 after the ENTRY instruction. + * Currently, we don't check whether or not these registers + * get spilled, so we must save and restore any that we + * modify. We've already saved a4 and a5 + * which we modify as part of the pseudo-CALL. + * + * IMPLEMENTATION NOTE: + * + * The pseudo-CALL below effectively saves registers a2..a3 so + * that they are available again after the corresponding + * RETW when returning from the exception handling. We + * could choose to put something like EPC1 or PS in + * there, so they're available more quickly when + * restoring. HOWEVER, exception handlers may wish to + * change such values, or anything on the exception stack + * frame, and expect these to be restored as modified. + * + * NOTA: future: figure out what's the best thing to put + * in a2 and a3. (candidate: a4 and a5 below; but what + * if exception handler manipulates ARs, as in a syscall + * handler.... oh well) + * + * + * Now do the pseudo-CALL. + * Make it look as if the code that got the exception made a + * CALL4 to the exception handling code. (We call + * this the "pseudo-CALL".) + * + * This pseudo-CALL is important and done this way: + * + * 1. There are only three ways to safely update the stack pointer + * in the windowed ABI, such that window exceptions work correctly: + * (a) spill all live windows to stack then switch to a new stack + * (or, save the entire address register file and window + * registers, which is likely even more expensive) + * (b) use MOVSP (or equivalent) + * (c) use ENTRY/RETW + * Doing (a) is excessively expensive, and doing (b) here requires + * copying 16 bytes back and forth which is also time-consuming; + * whereas (c) is very efficient, so that's what we do here. + * + * 2. Normally we cannot do a pseudo-CALL8 or CALL12 here. + * According to the + * windowed ABI, a function must allocate enough space + * for the largest call that it makes. However, the + * pseudo-CALL is executed in the context of the + * function that happened to be executing at the time + * the interrupt was taken, and that function might or + * might not have allocated enough stack space for a + * CALL8 or a CALL12. If we try doing a pseudo-CALL8 + * or -CALL12 here, we corrupt the stack if the + * interrupted function happened to not have allocated + * space for such a call. + * + * 3. We set the return PC, but it's not strictly + * necessary for proper operation. It does make + * debugging, ie. stack tracebacks, much nicer if it + * can point to the interrupted code (not always + * possible, eg. if interrupted code is in a different + * GB than the interrupt handling code, which is + * unlikely in a system without protection where + * interrupt handlers and general application code are + * typically linked together). + * + * IMPORTANT: Interrupts must stay disabled while doing the pseudo-CALL, + * or at least until after the ENTRY instruction, because SP has been + * restored to its original value that does not reflect the exception + * stack frame's allocation. An interrupt taken here would + * corrupt the exception stack frame (ie. allocate another over it). + * (High priority interrupts can remain enabled, they save and restore + * all of their state and use their own stack or save area.) + * For the same reason, we mustn't get any exceptions in this code + * (other than window exceptions where noted) until ENTRY is done. + */ + + // HERE: may get a single window overflow (caused by the following instruction). + +# if XTOS_DEBUG_PC + movi a4, 0xC0000000 // [for debug] for return PC computation below + or a3, a4, a3 // [for debug] set upper two bits of return PC + addx2 a4, a4, a3 // [for debug] clear upper bit +# else + movi a4, 0 // entry cannot cause overflow, cause it here +# endif + + .global _GeneralException +_GeneralException: // this label makes tracebacks through exceptions look nicer + + _entry a1, ESF_TOTALSIZE // as if after a CALL4 (PS.CALLINC set to 1 above) + + /* + * The above ENTRY instruction does a number of things: + * + * 1. Because we're emulating CALL4, the ENTRY rotates windows + * forward by 4 registers (as per 'ROTW +1'), so that + * a4-a15 became a0-a11. So now: a0-a11 are part of + * the interrupted context to be preserved. a0-a1 + * were already saved above when they were a4-a5. + * a12-a15 are free to use as they're NOT part of the + * interrupted context. We don't need to save/restore + * them, and they will get spilled if needed. + * + * 2. Updates SP (new a1), allocating the exception stack + * frame in the new window, preserving the old a1 in + * the previous window. + * + * 3. The underscore prefix prevents the assembler from + * automatically aligning the ENTRY instruction on a + * 4-byte boundary, which could create a fatal gap in + * the instruction stream. + * + * At this point, ie. before we re-enable interrupts, we know the caller is + * always live so we can safely modify a1 without using MOVSP (we can use MOVSP + * but it will never cause an ALLOCA or underflow exception here). + * So this is a good point to modify the stack pointer if we want eg. to + * switch to an interrupt stack (if we do, we need to save the current SP + * because certain things have been saved to that exception stack frame). + * We couldn't do this easily before ENTRY, where the caller wasn't + * necessarily live. + * + * NOTE: We don't switch to an interrupt stack here, because exceptions + * are generally caused by executing code -- so we handle exceptions in + * the context of the thread that cause them, and thus remain on the same + * stack. This means a thread's stack must be large enough to handle + * the maximum level of nesting of exceptions that the thread can cause. + */ + + // NOTA: exception handlers for certain causes may need interrupts to be kept + // disabled through their dispatch, so they can turn them off themselves at + // the right point (if at all), eg. to save critical state unknown to this + // code here, or for some recovery action that must be atomic with respect + // to interrupts.... + // + // Perhaps two versions of this assembly-level handler are needed, one that restores + // interrupts to what they were before the exception was taken (as here) + // and one that ensures at least low-priority interrupts are kept disabled? + // NOTA: For now, always enable interrupts here. + + /* + * Now we can enable interrupts. + * (Pseudo-CALL is complete, and SP reflects allocation of exception stack frame.) + */ + +#endif /* __XTENSA_CALL0_ABI__ */ + + +#if XCHAL_HAVE_INTERRUPTS +# if XCHAL_HAVE_XEA1 + //... recompute and set INTENABLE ... + l32i a13, a1, UEXC_sar // (temporary holding place for INTENABLE value saved before pseudo-CALL4 above) + rsr a12, SAR + wsr a13, INTENABLE // restore INTENABLE as it was on entry +# else + rsr a12, SAR + rsil a13, 0 +# endif +#else + rsr a12, SAR +#endif + + movi a13, _xtos_c_handler_table // &table + l32i a15, a1, UEXC_exccause // arg2: exccause + + s32i a12, a1, UEXC_sar + save_loops_mac16 a1, a12, a14 // save LOOP & MAC16 regs, if configured + + addx4 a12, a15, a13 // a12 = table[exccause] + l32i a12, a12, 0 // ... +#ifdef __XTENSA_CALL0_ABI__ + mov a2, a1 // arg1: exception parameters + mov a3, a15 // arg2: exccause + beqz a12, 1f // null handler => skip call + callx0 a12 // call C exception handler for this exception +#else + mov a14, a1 // arg1: exception parameters + // mov a15, a15 // arg2: exccause, already in a15 + beqz a12, 1f // null handler => skip call + callx12 a12 // call C exception handler for this exception +#endif +1: + // Now exit the handler. + + + // Restore special registers + + restore_loops_mac16 a1, a13, a14, a15 // restore LOOP & MAC16 regs, if configured + l32i a14, a1, UEXC_sar + + /* + * Disable interrupts while returning from the pseudo-CALL setup above, + * for the same reason they were disabled while doing the pseudo-CALL: + * this sequence restores SP such that it doesn't reflect the allocation + * of the exception stack frame, which we still need to return from + * the exception. + */ + +#if XCHAL_HAVE_INTERRUPTS +# if XCHAL_HAVE_XEA1 + // Must disable interrupts via INTENABLE, because PS.INTLEVEL gets zeroed + // by any window exception exit, eg. the window underflow that may happen + // upon executing the RETW instruction. + // Also, must disable at XTOS_LOCKLEVEL, not just EXCM_LEVEL, because this + // code effectively manipulates virtual INTENABLE state up to the point + // INTENABLE is written in _xtos_return_from_exc. + // + rsilft a12, 1, XTOS_LOCKLEVEL // lockout + rsr a12, INTENABLE + //movi a13, ~XCHAL_EXCM_MASK + movi a13, ~XTOS_LOCKOUT_MASK // mask out low and medium priority levels, and high priority levels covered by + // XTOS_LOCKLEVEL if any, so we can run at PS.INTLEVEL=0 while manipulating INTENABLE + s32i a12, a1, UEXC_sar // (temporary holding place for INTENABLE value to restore after pseudo-CALL4 below) + and a13, a12, a13 // mask out selected interrupts + wsr a13, INTENABLE // disable all interrupts up to and including XTOS_LOCKLEVEL +# else + rsil a12, XCHAL_EXCM_LEVEL +# endif +#endif + wsr a14, SAR + + movi a0, _xtos_return_from_exc +#ifdef __XTENSA_CALL0_ABI__ + jx a0 +#else /* ! __XTENSA_CALL0_ABI__ */ + /* Now return from the pseudo-CALL from the interrupted code, to rotate + * our windows back... */ + + movi a13, 0xC0000000 + //movi a13, 3 + //slli a13, a13, 30 +# if XCHAL_HAVE_XEA1 && XCHAL_HAVE_INTERRUPTS + rsync //NOT-ISA-DEFINED // wait for WSR to INTENABLE to complete before doing RETW + // (ie. before underflow exception exit) + // (not needed, because underflow exception entry does implicit ISYNC ?? + // but in case underflow not taken, WSR must complete before wsr to PS that lowers PS.INTLEVEL + // possibly below XTOS_LOCKLEVEL, in which RETW's jump is not sufficient sync, so a sync + // is needed but it can be placed just before WSR to PS -- but here is fine) +# endif + or a0, a0, a13 // set upper two bits + addx2 a0, a13, a0 // clear upper bit + retw +#endif /* ! __XTENSA_CALL0_ABI__ */ + + /* FIXME: what about _GeneralException ? */ + .size _xtos_c_wrapper_handler, . - _xtos_c_wrapper_handler + + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-return.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-return.S new file mode 100755 index 0000000..5a85b10 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-return.S @@ -0,0 +1,123 @@ +// exc-return.S - Shared exception/interrupt return code + +// Copyright (c) 2002-2004, 2006-2007, 2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include +#include "xtos-internal.h" + +#if XCHAL_HAVE_EXCEPTIONS + + .text + .align 4 + .global _xtos_return_from_exc +_xtos_return_from_exc: + +#ifdef __XTENSA_CALL0_ABI__ + + l32i a0, a1, UEXC_a0 // restore general registers, pc, ps + l32i a4, a1, UEXC_a4 + l32i a5, a1, UEXC_a5 + l32i a6, a1, UEXC_a6 + l32i a7, a1, UEXC_a7 + l32i a8, a1, UEXC_a8 + l32i a9, a1, UEXC_a9 + l32i a10, a1, UEXC_a10 + l32i a11, a1, UEXC_a11 + l32i a12, a1, UEXC_a12 + l32i a13, a1, UEXC_a13 + l32i a14, a1, UEXC_a14 + l32i a15, a1, UEXC_a15 + + l32i a2, a1, UEXC_pc + l32i a3, a1, UEXC_ps + wsr a2, EPC_1 + wsr a3, PS + + l32i a2, a1, UEXC_a2 + l32i a3, a1, UEXC_a3 + + rsync // wait for WSR to PS to complete + + addi a1, a1, ESF_TOTALSIZE // restore sp + + rfe + +#else /* ! __XTENSA_CALL0_ABI__ */ + + + // Here we rotated back by N registers, to the interrupted code's register window. + // NOTA: a2 and a3 might contain something useful, but we haven't determined + // what that might be yet (for now, a2 contains nested-C-func call-chain ptr). + + // NOTE: a5 still contains the exception window's exception stack frame pointer. + +# if XTOS_CNEST + s32i a2, a5, ESF_TOTALSIZE-20 // restore nested-C-func call-chain ptr +# endif + l32i a2, a5, UEXC_ps + l32i a3, a5, UEXC_pc + wsr a2, PS // for XEA2, this sets EXCM; for XEA1, this sets INTLEVEL to 1; ... + +# if XCHAL_HAVE_XEA1 && XCHAL_HAVE_INTERRUPTS + l32i a4, a5, UEXC_sar // load INTENABLE value that restores original vpri + l32i a2, a5, UEXC_a2 + rsync // wait for WSR to PS to complete + wsr a4, INTENABLE // update INTENABLE to restore original vpri (PS.INTLEVEL=1 here) + l32i a4, a5, UEXC_a4 +# else + l32i a2, a5, UEXC_a2 + l32i a4, a5, UEXC_a4 + rsync // wait for WSR to PS to complete +# endif + + /* FIXME: Enabling this here may break task-engine builds + * because task engines have exceptions (sort of), but they do + * not have the EPC_1 special register. XCHAL_HAVE_INTERRUPTS + * is incorrect for normal configs without interrupts but with + * exceptions (we still need to restore EPC_1). The correct + * solution is to define XCHAL_HAVE_EXCEPTIONS more strictly + * to mean something like "Have exceptions with + * user/kernel/double vectors" so that task engines are + * excluded. This would be a change to + * . */ + + wsr a3, EPC_1 + // HERE: + // - we cannot get window overflows anymore -- we're NOT in a valid windowed context + // - low-priority interrupts are still disabled + + // NOTE: we don't restore EXCCAUSE or EXCVADDR, not needed. + + // Restore a3, a5: + l32i a3, a5, UEXC_a3 + l32i a5, a5, UEXC_a5 + + rfe_rfue + +#endif /* __XTENSA_CALL0_ABI__ */ + + .size _xtos_return_from_exc, . - _xtos_return_from_exc + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-sethandler.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-sethandler.c new file mode 100755 index 0000000..7d83b73 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-sethandler.c @@ -0,0 +1,66 @@ +/* exc-sethandler.c - register an exception handler in XTOS */ + +/* + * Copyright (c) 1999-2006 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "xtos-internal.h" + + +#if XCHAL_HAVE_EXCEPTIONS + +extern void _xtos_c_wrapper_handler(void); /* assembly-level handler for C handlers */ +extern void _xtos_unhandled_exception(void); /* assembly-level handler for exceptions + with no registered handler */ +extern void _xtos_p_none(void); /* default/empty C handler */ + + +extern _xtos_handler _xtos_c_handler_table[]; +extern _xtos_handler _xtos_exc_handler_table[]; + +/* + * Register a C handler for the specified general exception + * (specified EXCCAUSE value). + */ +_xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f ) +{ + _xtos_handler ret; + + if( (unsigned) n >= XCHAL_EXCCAUSE_NUM ) + return 0; + if( f == 0 ) + f = &_xtos_p_none; + ret = _xtos_c_handler_table[n]; + _xtos_exc_handler_table[n] = ( (f == &_xtos_p_none) + ? &_xtos_unhandled_exception + : &_xtos_c_wrapper_handler ); + _xtos_c_handler_table[n] = f; + if( ret == &_xtos_p_none ) + ret = 0; + + return ret; +} + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-syscall-c-handler.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-syscall-c-handler.c new file mode 100755 index 0000000..405f7b6 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-syscall-c-handler.c @@ -0,0 +1,101 @@ +/* exc-syscall-c-handler.c - SYSCALL instruction XTOS handler in C */ + +/* + * Copyright (c) 1999-2006 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "xtos-internal.h" + + +/* + * User vector mode exception handler for the SYSCALL cause. + * + * NOTE: This function is NOT used by default. The assembly-level + * handler version of this function is normally used instead. + * This function is provided as an example only. + * To use it instead of the default assembly-level version, + * you can register it using _xtos_set_exception_handler(). + * For example: + * + * #include + * #include + * _xtos_set_exception_handler( EXCCAUSE_SYSCALL, + * (_xtos_handler)_xtos_p_syscall_handler ); + */ +UserFrame* _xtos_p_syscall_handler( UserFrame *uf /*, int cause */ ) +{ + uf->pc += 3; /* skip SYSCALL instruction */ + +#if XCHAL_HAVE_LOOPS + /* + * If the SYSCALL instruction was the last instruction in the body + * of a zero-overhead loop, then we should decrement the loop count + * and resume execution at the head of the loop. + */ + + if( uf->pc == uf->lend && uf->lcount != 0 ) + { + uf->lcount--; + uf->pc = uf->lbeg; + } +#endif /*XCHAL_HAVE_LOOP*/ + + /* + * Handle the system call. + * + * A typical SYSCALL handler uses code such as this to handle + * the system call, where the operation to be done is determined + * by the a2 register. Parameters to the operation are typically + * passed in address registers a3 and up. Results are typically + * returned in a2. (See Linux source code for example.) + */ + switch( uf->a2 ) { + case 0: + /* Spill register windows to the stack. */ + /* + * The Xtensa architecture reserves the a2==0 condition as a request + * to flush (spill) register windows to the stack. The current exception + * handling implementation never spills windows to the stack (it used + * to always spill, not true anymore), so we have to spill windows + * explicitly here. (Note that xthal_window_spill() spills windows + * that are part of the interrupt handling context, that don't + * really need to be spilled, but that's harmless other than being + * less than optimally efficient.) + * + * Also, be nice to programmers here. If they're + * building for Call0 ABI, silently do nothing for + * syscall a2==0. + */ +#ifdef __XTENSA_WINDOWED_ABI__ + xthal_window_spill(); +#endif + break; + + default: + uf->a2 = -1 /*ENOSYS*/; /* system call not supported */ + break; + } + + return( uf ); +} + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-syscall-handler.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-syscall-handler.S new file mode 100755 index 0000000..2429b76 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-syscall-handler.S @@ -0,0 +1,190 @@ +/* exc-syscall-handler.S - XTOS syscall instruction handler */ + +/* + * Copyright (c) 1999-2010 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * The SYSCALL instruction is typically used to implement system calls. + * By convention, register a2 identifies the requested system call. + * Typically, other parameters are passed in registers a3 and up, + * and results are returned in a2. + * + * The Xtensa windowed ABI reserves the value zero of register a2 + * as a request to force register windows to the stack. The call0 ABI, + * which has no equivalent operation, reserves this value as a no-op. + * + * Generally, only code that traverses the stack in unusual ways needs + * to force (spill) register windows to the stack. In generic C or C++, + * there are four cases, and they all use the standard SYSCALL mechanism: + * + * 1. C++ exceptions + * 2. setjmp and longjmp + * 3. functions using the GNU extension "__builtin_return_address" + * 4. functions using the GNU extension "nonlocal goto" + * + * NOTE: Specific operating systems often need to spill register windows + * to the stack in other situations such as context-switching, passing + * Unix-like signals to threads, displaying stack tracebacks, etc. + * They may choose to use the SYSCALL mechanism to do so, or use other + * means such as calling xthal_window_spill() or other methods. + * + * If you want to handle other system calls, you can modify this file, or + * use the C version of it in exc-syscall-handler.c . The Xtensa ABIs only + * define system call zero; the behavior of other system calls is up to you. + */ + +#include +#include "xtos-internal.h" + + +#if XCHAL_HAVE_EXCEPTIONS + +//Vector: +// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc. +// s32i a2, a1, UEXC_a2 +// s32i a3, a1, UEXC_a3 +// movi a3, _xtos_exc_handler_table +// rsr a2, EXCCAUSE +// addx4 a2, a2, a3 +// l32i a2, a2, 0 +// s32i a4, a1, UEXC_a4 +// jx a2 // jump to cause-specific handler + + .global _need_user_vector_ // pull-in real user vector (tiny LSP) + + + /* + * The SYSCALL handler is entered when the processor + * executes the SYSCALL instruction. + * By convention, the system call to execute is specified in a2. + */ + .text + .align 4 + .global _xtos_syscall_handler +_xtos_syscall_handler: + // HERE: a2, a3, a4 have been saved to the exception stack frame allocated with a1 (sp). + // We ignore that a4 was saved, we don't clobber it. + + rsr a3, EPC_1 +#if XCHAL_HAVE_LOOPS + // If the SYSCALL instruction was the last instruction in the body of + // a zero-overhead loop, and the loop will execute again, decrement + // the loop count and resume execution at the head of the loop: + // + rsr a2, LEND + addi a3, a3, 3 // increment EPC to skip the SYSCALL instruction + bne a2, a3, 1f + rsr a2, LCOUNT + beqz a2, 1f + addi a2, a2, -1 + wsr a2, LCOUNT + rsr a3, LBEG +1: l32i a2, a1, UEXC_a2 // get the system call number +#else + // No loop registers. + l32i a2, a1, UEXC_a2 // get the system call number + addi a3, a3, 3 // increment EPC to skip the SYSCALL instruction +#endif + wsr a3, EPC_1 // update EPC1 past SYSCALL + l32i a3, a1, UEXC_a3 // restore a3 + // If you want to handle other system calls, check a2 here. + +#ifdef __XTENSA_WINDOWED_ABI__ + bnez a2, .Lnotzero // is syscall number zero? + + /* Spill register windows to the stack. */ + + // Save a2 thru a5 in the nested-C-function area, where an interrupt + // won't clobber them. The pseudo-CALL's ENTRY below clobbers a4 and a5. + //s32i a2, a1, (ESF_TOTALSIZE - 32) + 0 // a2 is zero, no need to save + s32i a3, a1, (ESF_TOTALSIZE - 32) + 4 + s32i a4, a1, (ESF_TOTALSIZE - 32) + 8 + s32i a5, a1, (ESF_TOTALSIZE - 32) + 12 + + movi a3, PS_WOE|PS_CALLINC(1)|PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) // CALL4 emulation + rsr a2, PS // save PS in a2 + wsr a3, PS // PS.INTLEVEL=EXCMLEVEL (1 for XEA1) + // HERE: window overflows enabled but NOT SAFE yet, touch only a0..a3 until it's safe. + rsr a3, EPC_1 // save EPC1 in a3 + addi a1, a1, ESF_TOTALSIZE // restore sp (dealloc ESF) for sane stack again + rsync // wait for WSR to PS to complete + // HERE: Window overflows and interrupts are safe, we saved EPC1 and + // restored a1, and a4-a15 are unmodified. + // Pseudo-CALL: make it look as if the code that executed SYSCALL + // made a CALL4 to here. See user exc. handler comments for details. + // ENTRY cannot cause window overflow; touch a4 to ensure a4-a7 + // overflow if needed: + movi a4, 0 // clears pseudo-CALL's return PC + // NOTE: On XEA1 processors, return from window overflow re-enables + // interrupts (by clearing PS.INTLEVEL). This is okay even though SP + // is unallocated because we saved state safe from interrupt dispatch. + .global _SyscallException +_SyscallException: // label makes tracebacks look nicer + _entry a1, 64 // as if after a CALL4 (PS.CALLINC==1) + // Call deep enough to force spill of entire address register file. + _call12 .Ldeep +1: movi a14, 0x80000000 + .Ldelta_done + add a0, a12, a14 // clear a0 msbit (per CALL4), offset +3: retw // return from pseudo-CALL4 + + // NOTE: a5 still contains the exception window's exception stack frame pointer. +.LMdon: wsr a2, PS // for XEA2, this sets EXCM; for XEA1, this sets INTLEVEL to 1; ... + movi a2, 0 // indicate successful SYSCALL (?) + l32i a4, a5, 32 + 8 + rsync // complete WSR to PS for safe write to EPC1 + wsr a3, EPC_1 + l32i a3, a5, 32 + 4 + l32i a5, a5, 32 + 12 + rfe_rfue + + .set .Ldelta_retw, (3b - 1b) + .set .Ldelta_done, (.LMdon - 1b) + + .align 4 +.Ldeep: entry a1, 48 +#if XCHAL_NUM_AREGS < 64 + mov a15, a15 // touch just far enough to overflow 32 +#else + movi a12, .Ldelta_retw // use movi/add because of relocation + add a12, a0, a12 // set return PC as per CALL12 + _entry a1, 48 // last call was call12 so PS.CALLINC==3 + mov a12, a0 // set return PC + _entry a1, 48 + mov a12, a0 // set return PC + _entry a1, 16 + mov a11, a11 // touch just far enough to overflow 64 +#endif + retw + +#endif /* __XTENSA_WINDOWED_ABI__ */ + +.Lnotzero: + movi a2, -1 /*ENOSYS*/ // system call not supported + addi a1, a1, ESF_TOTALSIZE + rfe_rfue + + .size _xtos_syscall_handler, . - _xtos_syscall_handler + + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-table.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-table.S new file mode 100755 index 0000000..db6eaa5 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-table.S @@ -0,0 +1,62 @@ +// exc-table.S - general exception C handler table + +// Copyright (c) 1999-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" + + +#if XCHAL_HAVE_EXCEPTIONS + + /* + * Table of exception handlers (in C) for user vectored exceptions. + * Provides entries for all possible 64 exception causes + * currently allowed for in the EXCCAUSE register. + */ + .data + .global _xtos_c_handler_table + .align 4 +_xtos_c_handler_table: + .rept XCHAL_EXCCAUSE_NUM + .word _xtos_p_none + .endr + + /* + * Default/empty exception C handler. + * This is just a placeholder for exception causes with no registered + * handler; it normally never gets executed. + * NOTE: control goes first to the debugger if one is present; + * see _xtos_unhandled_exception in exc-unhandled.S . + */ + .text + .align 4 + .global _xtos_p_none + .type _xtos_p_none,@function +_xtos_p_none: + abi_entry + // Do nothing. + abi_return + .size _xtos_p_none, . - _xtos_p_none + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-unhandled.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-unhandled.S new file mode 100755 index 0000000..29723ea --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exc-unhandled.S @@ -0,0 +1,84 @@ +// exc-unhandled.S - General Exception Handler for unhandled exceptions + +// Copyright (c) 2002-2004, 2006, 2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include +#include "xtos-internal.h" +#ifdef SIMULATOR +#include +#endif + +#if XCHAL_HAVE_EXCEPTIONS + +/* + * Assembly-level exception handler used when no handler was + * registered for the specific exception cause. + * + * The BREAK instruction is used to give control to the debugger, + * if one is present and active. (If none is present and active, + * the default debug exception handler will typically skip over + * this break instruction.) + * This code follows the convention documented in the ISA manual + * to use BREAK instructions to signal unhandled exceptions to the + * debugger. For the debugger to report or handle this condition + * in an OS-independent manner, all processor state (except PC) + * must be restored as it was when the unhandled exception just + * occurred (ie. as it was at the beginning of the vector). + * If execution continues after the BREAK instruction (in which + * case any register might have been modified by the debugger), + * just return. + */ + .text + .align 4 + + // If not pulled-in some other way, define it as unhandled: + .weak _xtos_cause3_handler + .global _xtos_cause3_handler +_xtos_cause3_handler: + + .global _xtos_unhandled_exception +_xtos_unhandled_exception: +#if XCHAL_HAVE_DEBUG || defined(SIMULATOR) + l32i a2, a1, UEXC_a2 // restore a2 + l32i a3, a1, UEXC_a3 // restore a3 + // Note: a4-a5 not clobbered, no need to restore. + addi a1, a1, ESF_TOTALSIZE // restore sp +# if XCHAL_HAVE_DEBUG + break 1, 1 // give control to the debugger (if any present) +# else + wsr a2, EXCSAVE1 // save a2 where simulator expects it + movi a2, SYS_unhandled_user_exc + simcall // let simulator/debugger report unhandled exception + rsr a2, EXCSAVE1 // restore a2 +# endif + rfe_rfue // if sim/debug resume, just return +#else /* DEBUG or SIMULATOR */ + j _xtos_unhandled_exception // just loop forever +#endif /* DEBUG or SIMULATOR */ + + .size _xtos_unhandled_exception, . - _xtos_unhandled_exception + + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exit.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exit.S new file mode 100755 index 0000000..2793edf --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/exit.S @@ -0,0 +1,72 @@ +// exit.S +// +// For hardware / boards, this is the default _exit routine called by the +// C library exit() function. If the program ever exits, we eventually +// end up here after all C library cleanup (such as closing open files, +// calling exit callbacks and C++ destructors, etc) is complete. + +// Copyright (c) 1998-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" + +// Macros to abstract away ABI differences +#if __XTENSA_CALL0_ABI__ +# define CALL call0 +#else +# define CALL call4 +#endif + + + .text + .align 4 + .global _exit + .type _exit, @function +_exit: + abi_entry 0, 4 + + // sync dirty data to memory before terminating +#if XCHAL_DCACHE_IS_COHERENT + CALL xthal_cache_coherence_optout +#elif XCHAL_DCACHE_IS_WRITEBACK + CALL xthal_dcache_all_writeback +#endif + + // sync queues (if any, only for LX and later): +#if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RA_2004_1 /* LX or later? */ + extw +#endif + // can break to debug monitor, go to sleep with waiti, or just spin in a loop +.L0: +#if XCHAL_HAVE_DEBUG + break 0, 0 // back to debugger, if one is attached +#elif XCHAL_HAVE_INTERRUPTS + waiti 15 +#elif XCHAL_HAVE_HALT + halt +#endif + j .L0 + //abi_exit + + .size _exit, . - _exit + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/init.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/init.c new file mode 100755 index 0000000..065fb08 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/init.c @@ -0,0 +1,64 @@ +/* init.c - context initialization */ + +/* + * Copyright (c) 1999-2006 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#if XCHAL_NUM_CONTEXTS > 1 +#include +#endif + + + +#if 0 /* XCHAL_NUM_CONTEXTS > 1 */ +extern void _xtos_setup_context(int context_num, SetupInfo *info); +extern void _xtos_start_context(void); + +/* + * Sets up a context for running code. + * + * Returns PC at which to set the new context, or 0 on error. + */ +unsigned _xtos_init_context(int context_num, int stack_size, + _xtos_handler_func *start_func, int arg1) +{ + SetupInfo info; + + /* Allocate stack: */ + char *sp; + char *stack = malloc(stack_size); + if (stack == NULL) + return 0; + + /* Setup stack for call8: */ + sp = stack + stack_size - 16; + *(unsigned*)(sp - 12) = (unsigned)(sp + 32); + + info.sp = (unsigned)sp; + info.funcpc = (unsigned)start_func; + info.arg1 = arg1; + _xtos_setup_context(context_num, &info); + return (unsigned) &_xtos_start_context; +} +#endif /* multiple contexts */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-handler.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-handler.S new file mode 100755 index 0000000..3c86252 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-handler.S @@ -0,0 +1,59 @@ +// int-handler.S - Interrupt Handler Template (for levels > 1) +// $Id: //depot/main/Xtensa/OS/xtos/inth-template.S#1 $ + +// Copyright (c) 2003-2004, 2006 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +// To use this template file, define a macro called _INTERRUPT_LEVEL +// to be the interrupt priority level of the vector, then include this file. +// The default Makefile defines _INTERRUPT_LEVEL when assembling this file +// for each medium and high priority interrupt level. + + +#include +#include "xtos-internal.h" + + +#if XCHAL_HAVE_INTERRUPTS + +# if INTERRUPT_IS_HI(_INTERRUPT_LEVEL) + +# if _INTERRUPT_LEVEL > XTOS_LOCKLEVEL + /* Not safe to dispatch interrupts in C above XTOS_LOCKLEVEL, + * so default to assembly high-priority interrupt handlers template + * in this case (with the default XTOS_LOCKLEVEL this never happens): + */ +# include "int-highpri-template.S" +# else + /* Dispatch high-priority interrupt handlers in C: */ +# include "int-highpri-dispatcher.S" +# endif + +# elif INTERRUPT_IS_MED(_INTERRUPT_LEVEL) + +# include "int-medpri-dispatcher.S" + +# elif (_INTERRUPT_LEVEL <= XCHAL_NUM_INTLEVELS) && (_INTERRUPT_LEVEL != XCHAL_DEBUGLEVEL) +# error INTERNAL ERROR: Interrupt priority levels > 1 must be either hi or medium priority! +# endif + +#endif /* XCHAL_HAVE_INTERRUPTS */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-highpri-dispatcher.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-highpri-dispatcher.S new file mode 100755 index 0000000..334caa2 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-highpri-dispatcher.S @@ -0,0 +1,464 @@ +// High-Priority Interrupt Dispatcher Template +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/int-highpri-dispatcher.S#4 $ + +// Copyright (c) 2004-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// +// This file allows writing high-priority interrupt handlers in C, +// providing convenience at a significant cost in performance. +// +// By default, this file is included by inth-template.S . +// The default Makefile defines _INTERRUPT_LEVEL when assembling +// inth-template.S for each medium and high priority interrupt level. +// +// To use this template file, define a macro called _INTERRUPT_LEVEL +// to be the interrupt priority level of the vector, then include this file. + + +#include +#include "xtos-internal.h" + + +#if XCHAL_HAVE_INTERRUPTS + +#define INTERRUPT_MASK XCHAL_INTLEVEL_MASK(_INTERRUPT_LEVEL) +#define SINGLE_INTERRUPT ((INTERRUPT_MASK & (INTERRUPT_MASK - 1)) == 0) +#define SINGLE_INT_NUM XCHAL_INTLEVEL_NUM(_INTERRUPT_LEVEL) + + +#define INTLEVEL_N_MASK INTERRUPT_MASK // mask of interrupts at this priority +#define INTLEVEL_N_NUM SINGLE_INT_NUM // interrupt number if there is only one +#define INTLEVEL_N_BELOW_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(_INTERRUPT_LEVEL) + +/* Indicates whether there are multiple interrupts at this interrupt + * priority, ie. mapped to this interrupt vector. + * If there is only one, its number is INTLEVEL_N_NUM + */ +#define MULTIPLE_INTERRUPTS (!SINGLE_INTERRUPT) + +/* + * High priority interrupt stack frame: + */ +STRUCT_BEGIN +STRUCT_FIELD (long,4,HESF_,SAR) +STRUCT_FIELD (long,4,HESF_,WINDOWSTART) +STRUCT_FIELD (long,4,HESF_,WINDOWBASE) +STRUCT_FIELD (long,4,HESF_,EPC1) +STRUCT_FIELD (long,4,HESF_,EXCCAUSE) +STRUCT_FIELD (long,4,HESF_,EXCVADDR) +STRUCT_FIELD (long,4,HESF_,EXCSAVE1) +STRUCT_FIELD (long,4,HESF_,VPRI) /* (XEA1 only) */ +#if XCHAL_HAVE_MAC16 +STRUCT_FIELD (long,4,HESF_,ACCLO) +STRUCT_FIELD (long,4,HESF_,ACCHI) +/*STRUCT_AFIELD(long,4,HESF_,MR, 4)*/ +#endif +#if XCHAL_HAVE_LOOPS +STRUCT_FIELD (long,4,HESF_,LCOUNT) +STRUCT_FIELD (long,4,HESF_,LBEG) +STRUCT_FIELD (long,4,HESF_,LEND) +#endif +STRUCT_AFIELD(long,4,HESF_,AREG, 64) /* address registers ar0..ar63 */ +#define HESF_AR(n) HESF_AREG+((n)*4) +STRUCT_END(HighPriFrame) +#define HESF_TOTALSIZE HighPriFrameSize+32 /* 32 bytes for interrupted code's save areas under SP */ + + +#if XCHAL_HAVE_XEA1 && HAVE_XSR /* could be made true for T1040 and T1050 */ +# error "high-priority interrupt stack frame needs adjustment if HAVE_XSR is allowed with XEA1" +#endif + + +#define PRI_N_STACK_SIZE 1024 /* default to 1 kB stack for each level-N handling */ + + + // Allocate save area and stack: + // (must use .bss, not .comm, because the subsequent .set does not work otherwise) + .section .bss, "aw" + .align 16 +LABEL(_Pri_,_Stack): .space PRI_N_STACK_SIZE + HESF_TOTALSIZE + +#if HAVE_XSR + .data + .global LABEL(_Pri_,_HandlerAddress) +LABEL(_Pri_,_HandlerAddress): .space 4 +#endif + + + .text + .align 4 + .global LABEL(_Level,FromVector) +LABEL(_Level,FromVector): + movi a2, LABEL(_Pri_,_Stack) + PRI_N_STACK_SIZE // get ptr to save area + // interlock + + // Save a few registers so we can do some work: + s32i a0, a2, HESF_AR(0) +#if HAVE_XSR + //movi a0, LABEL(_Level,FromVector) // this dispatcher's address + movi a0, LABEL(_Pri_,_HandlerAddress) // dispatcher address var. + s32i a1, a2, HESF_AR(1) + l32i a0, a0, 0 // get dispatcher address + s32i a3, a2, HESF_AR(3) + xsr a0, EXCSAVE_LEVEL // get saved a2, restore dispatcher address +#else + rsr a0, EXCSAVE_LEVEL // get saved a2 + s32i a1, a2, HESF_AR(1) + s32i a3, a2, HESF_AR(3) +#endif + s32i a4, a2, HESF_AR(4) + s32i a0, a2, HESF_AR(2) + + // Save/restore all exception state + // (IMPORTANT: this code assumes no general exceptions occur + // during the execution of this dispatcher until this state + // is completely saved and from the point it is restored.) + // + // Exceptions that may normally occur within the C handler + // include window exceptions (affecting EPC1), alloca exceptions + // (affecting EPC1/EXCCAUSE and its handling uses EXCSAVE1), + // and possibly others depending on the particular C handler + // (possibly needing save/restore of EXCVADDR; and EXCVADDR + // is also possibly corrupted by any access thru an auto-refill + // way on a processor with a full MMU). + // + rsr a3, EPC1 + rsr a4, EXCCAUSE + s32i a3, a2, HESF_EPC1 + s32i a4, a2, HESF_EXCCAUSE +#if !XCHAL_HAVE_XEA1 + rsr a3, EXCVADDR + s32i a3, a2, HESF_EXCVADDR +#endif + rsr a4, EXCSAVE1 + s32i a4, a2, HESF_EXCSAVE1 + +#ifdef __XTENSA_WINDOWED_ABI__ + // Save remainder of entire address register file (!): + movi a0, XCHAL_NUM_AREGS - 8 // how many saved so far +#endif + + s32i a5, a2, HESF_AR(5) + s32i a6, a2, HESF_AR(6) + s32i a7, a2, HESF_AR(7) + +1: s32i a8, a2, HESF_AR(8) + s32i a9, a2, HESF_AR(9) + s32i a10, a2, HESF_AR(10) + s32i a11, a2, HESF_AR(11) + s32i a12, a2, HESF_AR(12) + s32i a13, a2, HESF_AR(13) + s32i a14, a2, HESF_AR(14) + s32i a15, a2, HESF_AR(15) + +#ifdef __XTENSA_WINDOWED_ABI__ + addi a8, a0, -8 + addi a10, a2, 8*4 + rotw 2 + bnez a0, 1b // loop until done + + rotw 2 + // back to original a2 ... + + // Save a few other registers required for C: + rsr a3, WINDOWSTART + rsr a4, WINDOWBASE + s32i a3, a2, HESF_WINDOWSTART + s32i a4, a2, HESF_WINDOWBASE + + // Setup window registers for first caller: + movi a3, 1 + movi a4, 0 + wsr a3, WINDOWSTART + wsr a4, WINDOWBASE + rsync + + // Note: register window has rotated, ie. a0..a15 clobbered. + +#endif /* __XTENSA_WINDOWED_ABI__ */ + + movi a1, LABEL(_Pri_,_Stack) + PRI_N_STACK_SIZE // get ptr to save area (is also initial stack ptr) + movi a0, 0 // mark start of call frames in stack + + // Critical state saved, a bit more to do to allow window exceptions... + + // We now have a C-coherent stack and window state. + // Still have to fix PS while making sure interrupts stay disabled + // at the appropriate level (ie. level 2 and below are disabled in this case). + +#if XCHAL_HAVE_XEA1 + movi a7, _xtos_intstruct // address of interrupt management globals + rsilft a3, _INTERRUPT_LEVEL, XTOS_LOCKLEVEL // lockout + movi a4, ~INTLEVEL_N_BELOW_MASK // mask out all interrupts at this level or lower + l32i a3, a7, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled + l32i a5, a7, XTOS_ENABLED_OFS // read _xtos_enabled + s32i a4, a7, XTOS_VPRI_ENABLED_OFS // set new _xtos_vpri_enabled (mask interrupts as if at _INTERRUPT_LEVEL) + s32i a3, a1, HESF_VPRI // save previous vpri + movi a2, 0x50020 // WOE=1, UM=1, INTLEVEL=0 + and a3, a5, a4 // mask out selected interrupts + wsr a3, INTENABLE // disable all low-priority interrupts +#else + // Load PS for C code, clear EXCM (NOTE: this step is different for XEA1): +# ifdef __XTENSA_CALL0_ABI__ + movi a2, 0x00020 + _INTERRUPT_LEVEL // WOE=0, CALLINC=0, UM=1, INTLEVEL=N, EXCM=0, RING=0 +# else + movi a2, 0x50020 + _INTERRUPT_LEVEL // WOE=1, CALLINC=1, UM=1, INTLEVEL=N, EXCM=0, RING=0 +# endif + +#endif + wsr a2, PS // update PS to enable window exceptions, etc as per above + rsync + + // Okay, window exceptions can now happen (although we have to call + // deep before any will happen because we've reset WINDOWSTART). + + // Save other state that might get clobbered by C code: + +////////////////// COMMON DISPATCH CODE BEGIN + + rsr a14, SAR + s32i a14, a1, HESF_SAR +#if XCHAL_HAVE_LOOPS + rsr a14, LCOUNT + s32i a14, a1, HESF_LCOUNT + rsr a14, LBEG + s32i a14, a1, HESF_LBEG + rsr a14, LEND + s32i a14, a1, HESF_LEND +#endif +#if XCHAL_HAVE_MAC16 + rsr a14, ACCLO + s32i a14, a1, HESF_ACCLO + rsr a14, ACCHI + s32i a14, a1, HESF_ACCHI +#endif + +#if MULTIPLE_INTERRUPTS /* > 1 interrupts at this priority */ // _split_ multi_setup +#define TABLE_OFS 0 + + rsr a15, INTERRUPT // mask of pending interrupts +# if XCHAL_HAVE_XEA1 + l32i a12, a7, XTOS_ENABLED_OFS // mask of enabled interrupts +# else + rsr a12, INTENABLE // mask of enabled interrupts +# endif + movi a13, INTLEVEL_N_MASK // mask of interrupts at this priority level + and a15, a15, a12 + and a15, a15, a13 // enabled & pending interrupts at this priority + _beqz a15, LABEL(Pri_,_spurious) // handle spurious interrupts (eg. level-trig.) +LABEL(Pri_,_loop): // handle all enabled & pending interrupts + neg a14, a15 + and a14, a14, a15 // single-out least-significant bit set in mask + wsr a14, INTCLEAR // clear if edge-trig. or s/w or wr/err (else no effect) + + // Compute pointer to interrupt table entry, given mask a14 with single bit set: + +# if XCHAL_HAVE_NSA + movi a12, _xtos_interrupt_table - (32-XCHAL_NUM_INTERRUPTS)*8 + nsau a14, a14 // get index of bit in a14, numbered from msbit + addx8 a12, a14, a12 +# else /* XCHAL_HAVE_NSA */ + movi a12, _xtos_interrupt_table // pointer to interrupt table + bltui a14, 0x10000, 1f // in 16 lsbits? (if so, check them) + addi a12, a12, 16*8 // no, index is at least 16 entries further + // (the above ADDI expands to an ADDI+ADDMI sequence, +128 is outside its range) + extui a14, a14, 16,16 // shift right upper 16 bits +1: bltui a14, 0x100, 1f // in 8 lsbits? (if so, check them) + addi a12, a12, 8*8 // no, index is at least 8 entries further + srli a14, a14, 8 // shift right upper 8 bits +1: bltui a14, 0x10, 1f // in 4 lsbits? (if so, check them) + addi a12, a12, 4*8 // no, index is at least 4 entries further + srli a14, a14, 4 // shift right 4 bits +1: bltui a14, 0x4, 1f // in 2 lsbits? (if so, check them) + addi a12, a12, 2*8 // no, index is at least 2 entries further + srli a14, a14, 2 // shift right 2 bits +1: bltui a14, 0x2, 1f // is it the lsbit? + addi a12, a12, 1*8 // no, index is one entry further +1: // done! a12 points to interrupt's table entry +# endif /* XCHAL_HAVE_NSA */ + +#else /* !MULTIPLE_INTERRUPTS */ + +# if XCHAL_HAVE_NSA +# define TABLE_OFS 8 * (XCHAL_NUM_INTERRUPTS - 1 - INTLEVEL_N_NUM) +# else +# define TABLE_OFS 8 * INTLEVEL_N_NUM +# endif + + movi a13, INTLEVEL_N_MASK // (if interrupt is s/w or edge-triggered or write/err only) + movi a12, _xtos_interrupt_table // get pointer to its interrupt table entry + wsr a13, INTCLEAR // clear the interrupt (if s/w or edge or wr/err only) + +#endif /* ifdef MULTIPLE_INTERRUPTS */ + + l32i a13, a12, TABLE_OFS + 0 // get pointer to handler from table entry +#ifdef __XTENSA_CALL0_ABI__ + l32i a2, a12, TABLE_OFS + 4 // pass single argument to C handler + callx0 a13 // call interrupt's C handler +#else + l32i a6, a12, TABLE_OFS + 4 // pass single argument to C handler + callx4 a13 // call interrupt's C handler +#endif + +#if XCHAL_HAVE_XEA1 + movi a7, _xtos_intstruct // address of interrupt management globals +#endif +#if MULTIPLE_INTERRUPTS /* > 1 interrupts at this priority */ + rsr a15, INTERRUPT // get pending interrupts +# if XCHAL_HAVE_XEA1 + l32i a12, a7, XTOS_ENABLED_OFS // get enabled interrupts +# else + rsr a12, INTENABLE // get enabled interrupts +# endif + movi a13, INTLEVEL_N_MASK // get mask of interrupts at this priority level + and a15, a15, a12 + and a15, a15, a13 // pending+enabled interrupts at this priority + _bnez a15, LABEL(Pri_,_loop) // if any remain, dispatch one +LABEL(Pri_,_spurious): +#endif /* MULTIPLE_INTERRUPTS */ + + // Restore everything, and return. + + // Three temp registers are required for this code to be optimal (no interlocks) in + // T2xxx microarchitectures with 7-stage pipe; otherwise only two + // registers would be needed. + // +#if XCHAL_HAVE_LOOPS + l32i a13, a1, HESF_LCOUNT + l32i a14, a1, HESF_LBEG + l32i a15, a1, HESF_LEND + wsr a13, LCOUNT + wsr a14, LBEG + wsr a15, LEND +#endif + +#if XCHAL_HAVE_MAC16 + l32i a13, a1, HESF_ACCLO + l32i a14, a1, HESF_ACCHI + wsr a13, ACCLO + wsr a14, ACCHI +#endif + l32i a15, a1, HESF_SAR + wsr a15, SAR + +////////////////// COMMON DISPATCH CODE END + +#if XCHAL_HAVE_XEA1 + // Here, a7 = address of interrupt management globals + l32i a4, a1, HESF_VPRI // restore previous vpri + rsil a3, XTOS_LOCKLEVEL // lockout + l32i a5, a7, XTOS_ENABLED_OFS // read _xtos_enabled + s32i a4, a7, XTOS_VPRI_ENABLED_OFS // set new _xtos_vpri_enabled + movi a2, 0x00020 + _INTERRUPT_LEVEL // WOE=0, UM=1, INTLEVEL=N + and a3, a5, a4 // mask out selected interrupts + wsr a3, INTENABLE // disable all low-priority interrupts +#else + // Load PS for interrupt exit, set EXCM: + movi a2, 0x00030 + _INTERRUPT_LEVEL // WOE=0, CALLINC=0, UM=1, INTLEVEL=N, EXCM=1, RING=0 +#endif + wsr a2, PS // update PS to disable window exceptions, etc as per above + rsync + + // NOTE: here for XEA1, restore INTENABLE etc... + +#ifdef __XTENSA_WINDOWED_ABI__ + // Restore window registers: + l32i a2, a1, HESF_WINDOWSTART + l32i a3, a1, HESF_WINDOWBASE + wsr a2, WINDOWSTART + wsr a3, WINDOWBASE + rsync + // Note: register window has rotated, ie. a0..a15 clobbered. + + // Reload initial stack pointer: + movi a1, LABEL(_Pri_,_Stack) + PRI_N_STACK_SIZE // - 16 + movi a6, XCHAL_NUM_AREGS - 8 // how many saved so far + addi a7, a1, -8*4 + + // Restore entire register file (!): + +1: + addi a14, a6, -8 + addi a15, a7, 8*4 + l32i a4, a15, HESF_AR(4) + l32i a5, a15, HESF_AR(5) + l32i a6, a15, HESF_AR(6) + l32i a7, a15, HESF_AR(7) + l32i a8, a15, HESF_AR(8) + l32i a9, a15, HESF_AR(9) + l32i a10,a15, HESF_AR(10) + l32i a11,a15, HESF_AR(11) + rotw 2 + bnez a6, 1b // loop until done + + l32i a4, a7, HESF_AR(12) + l32i a5, a7, HESF_AR(13) + l32i a6, a7, HESF_AR(14) + l32i a7, a7, HESF_AR(15) + rotw 2 + + // back to original a1 ... + +#else /* Call0 ABI: */ + + l32i a4, a1, HESF_AR(4) // restore general registers + l32i a5, a1, HESF_AR(5) + l32i a6, a1, HESF_AR(6) + l32i a7, a1, HESF_AR(7) + l32i a8, a1, HESF_AR(8) + l32i a9, a1, HESF_AR(9) + l32i a10, a1, HESF_AR(10) + l32i a11, a1, HESF_AR(11) + l32i a12, a1, HESF_AR(12) + l32i a13, a1, HESF_AR(13) + l32i a14, a1, HESF_AR(14) + l32i a15, a1, HESF_AR(15) + +#endif /* __XTENSA_WINDOWED_ABI__ */ + + // Restore exception state: + l32i a2, a1, HESF_EPC1 + l32i a3, a1, HESF_EXCCAUSE + wsr a2, EPC1 + wsr a3, EXCCAUSE +#if !XCHAL_HAVE_XEA1 + l32i a2, a1, HESF_EXCVADDR + wsr a2, EXCVADDR +#endif + l32i a3, a1, HESF_EXCSAVE1 + wsr a3, EXCSAVE1 + + l32i a0, a1, HESF_AR(0) + l32i a2, a1, HESF_AR(2) + l32i a3, a1, HESF_AR(3) + l32i a1, a1, HESF_AR(1) + rfi _INTERRUPT_LEVEL + + .size LABEL(_Level,FromVector), . - LABEL(_Level,FromVector) + + // This symbol exists solely for the purpose of being able to pull-in this + // dispatcher using _xtos_dispatch_level() routines with the tiny-rt LSP: + .global LABEL(_Level,HandlerLabel) + .set LABEL(_Level,HandlerLabel), 0 + +#endif /* XCHAL_HAVE_INTERRUPTS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-highpri-template.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-highpri-template.S new file mode 100755 index 0000000..1f16b47 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-highpri-template.S @@ -0,0 +1,154 @@ +// High-Priority Interrupt Handler Template +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/int-highpri-template.S#3 $ + +// Copyright (c) 2004-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// +// This file provides skeleton code for writing high-priority interrupt +// handlers in assembler for performance. +// +// By default, this file is included by inth-template.S . +// The default Makefile defines _INTERRUPT_LEVEL when assembling +// inth-template.S for each medium and high priority interrupt level. +// +// To use this template file, define a macro called _INTERRUPT_LEVEL +// to be the interrupt priority level of the vector, then include this file. + + +#include +#include "xtos-internal.h" + + +#if XCHAL_HAVE_INTERRUPTS + +#define INTERRUPT_MASK XCHAL_INTLEVEL_MASK(_INTERRUPT_LEVEL) +#define SINGLE_INTERRUPT (INTERRUPT_MASK & (INTERRUPT_MASK - 1) == 0) +#define SINGLE_INT_NUM XCHAL_INTLEVEL_NUM(_INTERRUPT_LEVEL) + + +// NOTE: It is strongly recommended that high-priority +// interrupt handlers be written in assembly. +// +// High-priority interrupt handlers can be written in C, +// but only at the cost of an unreasonable amount of state +// save and restore (including the entire physical address +// register file and others, see int-highpri-dispatcher.S) +// that makes high-priority interrupt dispatching much slower +// than for low and medium priority interrupts. +// (Low and medium priority interrupts are masked by atomic +// register window operations, so they take advantage of a +// coherent window state for fast entry. High priority +// interrupts are not masked by window operations so they +// can interrupt them, leading to a potentially incoherent +// window state at the time of the interrupt. Given that +// high priority handlers must save and restore everything +// they touch, they end up needing to save and restore the +// entire window state [physical address register file etc.] +// and all exception state which they can also interrupt.) +// See also the Microprocessor Programmer's Guide. + +// High-priority interrupts are designed to be very fast and with +// very low latency. +// Typical high-priority interrupt service routines are kept +// relatively small and fast. Either there is little to do, +// or the routine handles only the necessary high priority +// activities related to a device and leaves the rest +// (other more complex and time-consuming activities) +// to be scheduled later, eg. by triggering a level-one +// (low-priority) or medium-priority software interrupt whose +// handler can be written in C for the more extensive processing. + +// NOTE: The following handler is just skeleton example +// code. It is NOT a functional handler. For software, edge- +// triggered and write-error interrupts, it simply does nothing +// and return. For other types (timer and level-triggered), +// this code does not clear the source(s) of interrupt, +// hence if any interrupt at this priority level are both enabled +// and triggered, the processor repeatedly takes the interrupt +// in a loop. This is all okay as a default, because +// XTOS (and other operating systems) clears the INTENABLE +// register at startup, requiring the application to +// enable specific interrupts before they can be taken. +// So as long as you don't enable any interrupt of this +// priority level, this example handler will never execute. + +// Exports +.global LABEL(_Level,FromVector) + + .data + .align 4 +LABEL(int,save): + .space 4 // save area + + .text + .align 4 +LABEL(_Level,FromVector): + // The vectoring code has already saved a2 in EXCSAVEn. + // Save any other registers we'll use: + movi a2, LABEL(int,save) + s32i a1, a2, 0 + // ... add more as needed (increase save area accordingly) ... + + // WRITE YOUR INTERRUPT HANDLING CODE HERE... + + // If multiple interrupts are mapped to this priority level, + // you'll probably need to distinguish which interrupt(s) + // occurred by reading the INTERRUPT (INTREAD) and + // INTENABLE registers, and'ing them together, and + // looking at what bits are set in both. + // If any of the interrupts are level-triggered, be ready + // to handle the case where no interrupts are to be handled + // -- this is called a spurious interrupt, and can happen + // when the level-triggered interrupt line goes inactive + // after the interrupt is taken but before the INTERRUPT + // register is read. + + // You'll also normally want to clear the source of + // the interrupt before returning, to avoid getting + // the same interrupt again immediately. For illustration, + // this code clears all software, edge-triggered, and + // write-error interrupts at this priority level (if any). + // NOTE: Timer interrupts must be cleared by writing to + // the corresponding CCOMPAREn register; and level-sensitive + // interrupts can only be cleared externally, usually by + // requesting the associated device to do so (in a + // device-specific manner). + // + movi a1, INTERRUPT_MASK + wsr a1, INTCLEAR + + // Restore registers: + l32i a1, a2, 0 +#if HAVE_XSR + movi a2, LABEL(_Level,FromVector) // restore handler address + xsr a2, EXCSAVE_LEVEL +#else + rsr a2, EXCSAVE_LEVEL +#endif + // ... add more if more are saved above ... + + // Return: + rfi _INTERRUPT_LEVEL + + .size LABEL(_Level,FromVector), . - LABEL(_Level,FromVector) + +#endif /* XCHAL_HAVE_INTERRUPTS */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-initlevel.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-initlevel.S new file mode 100755 index 0000000..6ded8c7 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-initlevel.S @@ -0,0 +1,59 @@ +// int-initlevel.S - Routines used to pull-in interrupt dispatch code +// in the tiny-rt LSP. +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/int-initlevel.S#3 $ + +// Copyright (c) 2006-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +// To assemble this template file, define a macro called _INTERRUPT_LEVEL +// to be the interrupt level of the vector. We use the same template for both +// high-level and medium-level interrupts, but not debug level. + + +#include +#include "xtos-internal.h" + + +#if XCHAL_HAVE_INTERRUPTS && (_INTERRUPT_LEVEL <= XCHAL_NUM_INTLEVELS) && (_INTERRUPT_LEVEL != XCHAL_DEBUGLEVEL) + + // Nothing to do at runtime. This function only has effect + // at link-time. + // + .text + .global LABEL(_xtos_dispatch_level,_interrupts) + .align 4 +LABEL(_xtos_dispatch_level,_interrupts): + abi_entry + abi_return + .size LABEL(_xtos_dispatch_level,_interrupts), . - LABEL(_xtos_dispatch_level,_interrupts) + + // This reference is what does the work of pulling-in the + // relevant interrupt vector at the specified level. + // This is only needed in the tiny-rt LSP. + // +# if _INTERRUPT_LEVEL == 1 + .global _need_level1int_ +# else + .global LABEL(_Level,Vector) +# endif + +#endif /* XCHAL_HAVE_INTERRUPTS */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-lowpri-dispatcher.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-lowpri-dispatcher.S new file mode 100755 index 0000000..d1d5f93 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-lowpri-dispatcher.S @@ -0,0 +1,787 @@ +// Level-one interrupt dispatcher (user vectored handler) + +// Copyright (c) 1999-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" +#include "interrupt-pri.h" + +#if XCHAL_HAVE_EXCEPTIONS && XCHAL_HAVE_INTERRUPTS + + + /* + * Macros to slightly reduce the number of #if statements in the code: + */ + +/* This is set (for #if only) if there is only ONE interrupt configured at level one: */ +# define XTOS_SINGLE_INT defined(XCHAL_INTLEVEL1_NUM) + +/* Simplify the #if's around saving and restoring of SAR ('#' is a comment char): */ +# if ((XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_LO) || (XTOS_INT_FAIRNESS && XTOS_SUBPRI)) && !XTOS_SINGLE_INT +# define NEEDSAR /* need SAR saved early w/ints locked */ +# define LATESAR # /* need SAR saved late w/ints unlocked */ +# else +# define NEEDSAR # /* need SAR saved early w/ints locked */ +# define LATESAR /* need SAR saved late w/ints unlocked */ +# endif + +/* Simplify the #if's around fairness-specific code ('#' is a comment char): */ +# if XTOS_INT_FAIRNESS +# define IFFAIR /* for code enabled only for fairness */ +# define NOFAIR # /* for code enabled only without fairness */ +# else +# define IFFAIR # /* for code enabled only for fairness */ +# define NOFAIR /* for code enabled only without fairness */ +# endif + + + // NOTE: something equivalent to the following vector is executed + // before entering this handler (see user-vector.S). +//_UserExceptionVector: +// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc. +// s32i a2, a1, UEXC_a2 +// s32i a3, a1, UEXC_a3 +// movi a3, _xtos_exc_handler_table +// rsr a2, EXCCAUSE +// addx4 a2, a2, a3 +// l32i a2, a2, 0 +// s32i a4, a1, UEXC_a4 +// jx a2 // jump to cause-specific handler + + .global _need_user_vector_ // pull-in real user vector (tiny LSP) + + .text + .align 4 + .global _xtos_l1int_handler +_xtos_l1int_handler: + // HERE: a2, a3, a4 have been saved to exception stack frame allocated with a1 (sp). + + s32i a5, a1, UEXC_a5 // a5 will get clobbered by ENTRY after pseudo-CALL4 + // (a4..a15 spilled as needed; save if modified) + +# if XCHAL_HAVE_XEA2 + + // Set PS fields: + // EXCM = 0 + // WOE = __XTENSA_CALL0_ABI__ ? 0 : 1 + // UM = 1 + // INTLEVEL = EXCM_LEVEL + // CALLINC = __XTENSA_CALL0_ABI__ ? 0 : 1 + // OWB = 0 (actual value is a don't care) + +# ifdef __XTENSA_CALL0_ABI__ + movi a2, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) +# else + movi a2, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL)|PS_WOE|PS_CALLINC(1) // CALL4 emulation +# endif + rsr a3, EPC_1 + xsr a2, PS + +# ifdef __XTENSA_WINDOWED_ABI__ + // HERE: window overflows enabled, but NOT SAFE because we're not quite + // in a valid windowed context (haven't restored a1 yet); + // so don't cause any (by accessing only a0..a3) until we've saved critical state + // and restored a1 (note: critical state already saved in a2 and a3): + // NOTE: saved EPC1 before causing any overflows, because overflows corrupt EPC1. +# endif + + s32i a3, a1, UEXC_pc + s32i a2, a1, UEXC_ps + +# else /*if XEA1:*/ + + // Would need to save & clear LCOUNT only with protection. None here. + // No need to save EXCVADDR or EXCCAUSE for low-priority interrupts. +# if 1 + rsr a2, INTERRUPT // read INTERRUPT while PS.INTLEVEL is 1 and INTENABLE is intact + rsilft a3, 1, XTOS_LOCKLEVEL // lockout + s32i a2, a1, UEXC_vpri // save for interrupt computation + rsr a2, INTENABLE + movi a3, XTOS_UNLOCKABLE_MASK // mask out level one, and high levels covered by XTOS_LOCKLEVEL if any, + // so we can run at PS.INTLEVEL=0 while manipulating INTENABLE + s32i a2, a1, UEXC_sar // save old INTENABLE, to handle the spurious interrupt case + and a3, a2, a3 // mask out selected interrupts + wsr a3, INTENABLE // disable all interrupts up to and including XTOS_LOCKLEVEL +# else + // Using this alternate code requires extensive changes elsewhere; + // its only advantage is potentially lowered latency of interrupts + // of priority levels 2 thru XTOS_LOCKLEVEL: + movi a2, _xtos_intstruct // address of interrupt management globals + rsilft a3, 1, XTOS_LOCKLEVEL // lockout + l32i a3, a2, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled + //interlock + s32i a3, a1, UEXC_vpri // save previous vpri + movi a3, ~XCHAL_EXCM_MASK // mask out all low-priority interrupts + // so we can run at PS.INTLEVEL=0 while ESF allocation not reflected in SP + //interlock + s32i a3, a2, XTOS_VPRI_ENABLED_OFS // set new _xtos_vpri_enabled (mask all low-priority interrupts) + l32i a2, a2, XTOS_ENABLED_OFS // read _xtos_enabled + //interlock + and a3, a2, a3 // mask out selected interrupts + wsr a3, INTENABLE // disable all low-priority interrupts +# endif + movi a3, PS_WOE|PS_CALLINC(1)|PS_UM // WOE=1, UM=1, INTLEVEL=0, CALLINC=1 (call4 emul), OWB=(dontcare)=0 + + // NOTE: could use XSR here if targeting T1040 or T1050 hardware (requiring slight sequence adjustment as for XEA2): + rsr a2, PS + rsync //NOT-ISA-DEFINED // wait for WSR to INTENABLE to complete before clearing PS.INTLEVEL + wsr a3, PS // PS.INTLEVEL=0, effective INTLEVEL (via INTENABLE) is XTOS_LOCKLEVEL (NOTA: LOWPRI_LEVELS) + + // HERE: window overflows enabled, but NOT SAFE because we're not quite + // in a valid windowed context (haven't restored a1 yet...); + // so don't cause any (keep to a0..a3) until we've saved critical state and restored a1: + + // NOTE: MUST SAVE EPC1 before causing any overflows, because overflows corrupt EPC1. + rsr a3, EPC_1 + s32i a2, a1, UEXC_ps + s32i a3, a1, UEXC_pc + +# endif /* XEA1 */ + + +# ifdef __XTENSA_CALL0_ABI__ + + s32i a0, a1, UEXC_a0 // save the rest of the registers + s32i a6, a1, UEXC_a6 + s32i a7, a1, UEXC_a7 + s32i a8, a1, UEXC_a8 + s32i a9, a1, UEXC_a9 + s32i a10, a1, UEXC_a10 + s32i a11, a1, UEXC_a11 + s32i a12, a1, UEXC_a12 + s32i a13, a1, UEXC_a13 + s32i a14, a1, UEXC_a14 + s32i a15, a1, UEXC_a15 +# if XTOS_DEBUG_PC + // TODO: setup return PC for call traceback through interrupt dispatch +# endif + + rsync // wait for WSR to PS to complete + +# else /* ! __XTENSA_CALL0_ABI__ */ + +# if XTOS_CNEST + l32i a2, a1, ESF_TOTALSIZE-20 // save nested-C-func call-chain ptr +# endif + addi a1, a1, ESF_TOTALSIZE // restore sp (dealloc ESF) for sane stack again + rsync // wait for WSR to PS to complete + + /* HERE: we can SAFELY get window overflows. + * + * From here, registers a4..a15 automatically get spilled if needed. + * They become a0..a11 after the ENTRY instruction. + * Currently, we don't check whether or not these registers + * get spilled, so we must save and restore any that we + * modify. We've already saved a4 and a5 + * which we modify as part of the pseudo-CALL. + * + * IMPLEMENTATION NOTE: + * + * The pseudo-CALL below effectively saves registers a2..a3 + * so that they are available again after the corresponding + * RETW when returning from the exception handling. We + * could choose to put something like EPC1 or PS in + * there, so they're available more quickly when + * restoring. HOWEVER, exception handlers may wish to + * change such values, or anything on the exception stack + * frame, and expect these to be restored as modified. + * + * NOTA: future: figure out what's the best thing to put + * in a2 and a3. (candidate: a4 and a5 below; but what + * if exception handler manipulates ARs, as in a syscall + * handler.... oh well) + * + * + * Now do the pseudo-CALL. + * Make it look as if the code that got the exception made a + * CALL4 to the exception handling code. (We call + * this the "pseudo-CALL".) + * + * This pseudo-CALL is important and done this way: + * + * 1. There are only three ways to safely update the stack pointer + * in the windowed ABI, such that window exceptions work correctly: + * (a) spill all live windows to stack then switch to a new stack + * (or, save the entire address register file and window + * registers, which is likely even more expensive) + * (b) use MOVSP (or equivalent) + * (c) use ENTRY/RETW + * Doing (a) is excessively expensive, and doing (b) here requires + * copying 16 bytes back and forth which is also time-consuming; + * whereas (c) is very efficient, so that's what we do here. + * + * 2. Normally we cannot do a pseudo-CALL8 or CALL12 here. + * According to the + * windowed ABI, a function must allocate enough space + * for the largest call that it makes. However, the + * pseudo-CALL is executed in the context of the + * function that happened to be executing at the time + * the interrupt was taken, and that function might or + * might not have allocated enough stack space for a + * CALL8 or a CALL12. If we try doing a pseudo-CALL8 + * or -CALL12 here, we corrupt the stack if the + * interrupted function happened to not have allocated + * space for such a call. + * + * 3. We set the return PC, but it's not strictly + * necessary for proper operation. It does make + * debugging, ie. stack tracebacks, much nicer if it + * can point to the interrupted code (not always + * possible, eg. if interrupted code is in a different + * GB than the interrupt handling code, which is + * unlikely in a system without protection where + * interrupt handlers and general application code are + * typically linked together). + * + * IMPORTANT: Interrupts must stay disabled while doing the pseudo-CALL, + * or at least until after the ENTRY instruction, because SP has been + * restored to its original value that does not reflect the exception + * stack frame's allocation. An interrupt taken here would + * corrupt the exception stack frame (ie. allocate another over it). + * (High priority interrupts can remain enabled, they save and restore + * all of their state and use their own stack or save area.) + * For the same reason, we mustn't get any exceptions in this code + * (other than window exceptions where noted) until ENTRY is done. + */ + + // HERE: may get a single window overflow (caused by the following instruction). + +# if XTOS_DEBUG_PC + movi a4, 0xC0000000 // [for debug] for return PC computation below + or a3, a4, a3 // [for debug] set upper two bits of return PC + addx2 a4, a4, a3 // [for debug] clear upper bit +# else + movi a4, 0 // entry cannot cause overflow, cause it here +# endif + + .global _LevelOneInterrupt +_LevelOneInterrupt: // this label makes tracebacks through interrupts look nicer + + _entry a1, ESF_TOTALSIZE // as if after a CALL4 (PS.CALLINC set to 1 above) + + /* + * The above ENTRY instruction does a number of things: + * + * 1. Because we're emulating CALL4, the ENTRY rotates windows + * forward by 4 registers (as per 'ROTW +1'), so that + * a4-a15 became a0-a11. So now: a0-a11 are part of + * the interrupted context to be preserved. a0-a1 + * were already saved above when they were a4-a5. + * a12-a15 are free to use as they're NOT part of the + * interrupted context. We don't need to save/restore + * them, and they will get spilled if needed. + * + * 2. Updates SP (new a1), allocating the exception stack + * frame in the new window, preserving the old a1 in + * the previous window. + * + * 3. The underscore prefix prevents the assembler from + * automatically aligning the ENTRY instruction on a + * 4-byte boundary, which could create a fatal gap in + * the instruction stream. + * + * At this point, ie. before we re-enable interrupts, we know the caller is + * always live so we can safely modify a1 without using MOVSP (we can use MOVSP + * but it will never cause an ALLOCA or underflow exception here). + * So this is a good point to modify the stack pointer if we want eg. to + * switch to an interrupt stack (if we do, we need to save the current SP + * because certain things have been saved to that exception stack frame). + * We couldn't do this easily before ENTRY, where the caller wasn't + * necessarily live. + */ + +# if 0 /*... non-nested interrupt ...*/ + mov ...some address register..., a1 // save ptr to original ESF + movi a1, _interrupt_stack // switch stack +# endif + +# endif /* __XTENSA_CALL0_ABI__ */ + + /* + * Now we can enable interrupts of higher virtual priority than the one(s) + * being dispatched/processed here. This may entail some software prioritization, + * if so configured. + * (Pseudo-CALL is complete, and SP reflects allocation of exception stack frame + * or switch to new stack.) + */ + +# if XCHAL_HAVE_XEA2 + rsilft a15, XCHAL_EXCM_LEVEL, 1 // INTERRUPT reg *must* be read at PS.INTLEVEL<=1 + // (otherwise it might get higher pri ints) +# define CUR_INTLEVEL 1 +# else +# define CUR_INTLEVEL 0 +# endif + /* At this point, PS.INTLEVEL is: 0 if XEA1, 1 if XEA2 (per CUR_INTLEVEL) */ + + + /***************** Dispatch low-priority interrupts to service *****************/ + + /* HERE: We may get up to 3 window overflows on the following instruction. + * + * The worst case is 3 overflows, two 4-register overflows and one + * 12-register overflow. + */ + + +# if XTOS_VIRTUAL_INTENABLE + /* + * The INTENABLE register is virtualized, because it serves two purposes: + * controlling which interrupts are active (eg. enabled once a handler + * is registered) as reflected in _xtos_enabled, and what is the current + * effective interrupt level as reflected in _xtos_vpri_enabled. + * + * The INTENABLE register always contains (_xtos_enabled & _xtos_vpri_enabled). + * NOTE: It is important that INTENABLE, _xtos_enabled and _xtos_vpri_enabled + * only be modified when interrupts at XTOS_LOCK_LEVEL and below are disabled, + * that they never be modified by interrupts at levels above XTOS_LOCK_LEVEL, + * and that they be consistent and never modified when the current interrupt + * level is below XTOS_LOCK_LEVEL. + * + * NOTE: Reading the INTERRUPT register *must* be done at PS.INTLEVEL <= 1 + * otherwise we might incorrectly see higher priority interrupts. + */ + + + movi a14, _xtos_intstruct // address of interrupt management globals +# if XCHAL_HAVE_XEA1 + l32i a15, a1, UEXC_vpri // read saved INTERRUPT register value + l32i a13, a14, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled + l32i a12, a14, XTOS_ENABLED_OFS // read _xtos_enabled + and a15, a15, a13 // don't handle ints already being handled +# else + rsr a15, INTERRUPT // interrupts pending + rsr a12, INTENABLE // interrupts enabled (already should equal _xtos_enabled & _xtos_vpri_enabled) + l32i a13, a14, XTOS_VPRI_ENABLED_OFS // read previous _xtos_vpri_enabled +# endif + and a15, a15, a12 // a15 = INTERRUPT & (interrupts we can consider processing) +NEEDSAR rsr a12, SAR + s32i a13, a1, UEXC_vpri // save previous vpri + + _beqz a15, spurious_int // no interrupt to handle (spurious interrupt) +NEEDSAR s32i a12, a1, UEXC_sar // note: in XEA1, UEXC_sar must be set *after* beqz above + +IFFAIR s32i a2, a1, UEXC_exccause // save a2 (interrupted code's a6) +IFFAIR movi a2, -1 // initial fairness mask + +.L1_loop0: + // a15 = non-zero mask of interrupt bits to consider handling + +# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI && !XTOS_INT_FAIRNESS && !XTOS_SUBPRI_GROUPS + // Special case that can be handled a bit more efficiently: + + neg a12, a15 // find lsbit in a15 ... + and a12, a12, a15 // ... + // a12 = single bit corresponding to interrupt to be processed (highest pri pending+enabled). + + // Compute a13 = new virtual priority based on this selected highest priority interrupt: + movi a15, ~XCHAL_LOWPRI_MASK // mask of all low-priority interrupts + addi a13, a12, -1 // mask of interrupts enabled at this new priority + or a13, a13, a15 // also leave medium- and high-priority interrupts enabled + +# else /* special case */ + + // Entry: + // a12 = (undefined) + // a13 = (undefined) + // a14 = &_xtos_intstruct --or-- interrupt table adjusted base + // a15 = non-zero mask of interrupt bits to consider handling + // Exit: + // a12 = index + // a13 = (clobbered) + // a14 = (preserved) + // a15 = single bit corresponding to index + // + indexmask_int a12, a15, a14, a13 + + // a12 = index of highest priority pending+enabled interrupt, to be processed. + // a15 = (1 << a12), ie. bit corresponding to interrupt to be processed. +IFFAIR xor a2, a2, a15 // update fairness mask - mask out this interrupt until recycling mask + movi a13, _xtos_interrupt_table - IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 ) + wsr a15, INTCLEAR // clear interrupt (if software or external edge-triggered or write-error) + addx8 a12, a12, a13 // a12 = address in interrupt table for given interrupt number + +.L1_loop1: + // a12 now contains pointer to interrupt table entry for interrupt to be processed + l32i a13, a12, XIE_VPRIMASK // a13 = new vpri (mask of interrupts enabled at this interrupt's priority) +# endif /* !special case */ + + // a13 = new virtual priority based on the selected highest priority interrupt + + rsilft a15, 1*XCHAL_HAVE_XEA2, XTOS_LOCKLEVEL // lockout + + // Now do the equivalent of: prev = _xtos_set_vpri( a13 ); + + l32i a15, a14, XTOS_ENABLED_OFS // a15 = _xtos_enabled + s32i a13, a14, XTOS_VPRI_ENABLED_OFS // update new _xtos_vpri_enabled + and a15, a15, a13 // a15 = _xtos_enabled & _xtos_vpri_enabled + //NOTE: Here, do: a15 &= ~_xtos_pending if XTOS_VIRTUAL_INTERRUPT is set. + wsr a15, INTENABLE + //interlock + //interlock + rsync // NOTA - not ISA defined // wait for INTENABLE write to complete before we set PS.INTLEVEL to zero + + + // Okay, we've updated INTENABLE to reflect the new virtual priority (vpri) + // according to the highest priority pending+enabled (low-priority) interrupt. + + // IMPLEMENTATION NOTE - Before we unlock (enable interrupts), we could + // switch stacks here, now that we have enough free registers through the unlock. + + // Now we can enable interrupts via PS.INTLEVEL. (Already done for XEA1.) + + rsil a15, 0 // unlock +# undef CUR_INTLEVEL +# define CUR_INTLEVEL 0 + + // HERE: interrupts are enabled again (those interrupts of + // higher virtual priority than the one we're currently processing). + + // HERE: + // a12 = pointer to interrupt entry in table, or + // mask of interrupt bit to process (special case only) + // a13, a15 = available for use + // a14 = available for use if virtual INTENABLE, else is pointer to interrupt table + +# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI && !XTOS_INT_FAIRNESS && !XTOS_SUBPRI_GROUPS + /* In this special case, we moved as much as possible where interrupts are enabled again: */ + // a12 is bit corresponding to interrupt, convert to ptr to interrupt table entry... + movi a14, _xtos_interrupt_table - IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 ) + wsr a12, INTCLEAR // clear interrupt (if software or external edge-triggered or write-error) +//IFFAIR xor a2, a2, a12 // update fairness mask - mask out this interrupt until recycling mask + msindex_int a15, a12 // a15 = index of msbit set in a12 (a12 clobbered) + addx8 a12, a15, a14 // a12 = address in interrupt table for given interrupt number +# endif /* special case */ + + + +# elif XTOS_SINGLE_INT + /* + * Only one interrupt is configured to map to this vector. + * This simplifies the code considerably -- no checking and resolving of INTERRUPT + * register required. Just call the handler and exit. + * + * (With INTENABLE register virtualization, the simplification is + * not as great, and not implemented separately above.) + */ + + +# define XTOS_SINGLE_INT_NUM XCHAL_INTLEVEL1_NUM +# define XTOS_SINGLE_INT_MASK XCHAL_INTLEVEL1_MASK +# define XTOS_SINGLE_INT_CLEAR ((XTOS_SINGLE_INT_MASK & XCHAL_INTCLEARABLE_MASK) != 0) +# if XTOS_SINGLE_INT_CLEAR + movi a13, XCHAL_LOWPRI_MASK // bit to clear in INTERRUPT register +# endif + // Get pointer to interrupt table entry for this vector's only interrupt: + movi a12, _xtos_interrupt_table + MAPINT(XTOS_SINGLE_INT_NUM)*XIE_SIZE +# if XTOS_SINGLE_INT_CLEAR + wsr a13, INTCLEAR // clear interrupt pending bit (if software or external-edge-triggered or write-error) +# endif + + + +# else /* ie. if !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */ + /* + * Here, the INTENABLE register is NOT virtualized. There are no _xtos_enabled + * or _xtos_vpri_enabled global variables to track. INTENABLE simply controls + * which interrupts are active (eg. enabled once a handler is registered). + * + * NOTE: To ensure its coherency, it is still important to only modify the + * INTENABLE register when interrupts at XTOS_LOCK_LEVEL and below are disabled, + * that it never be modified by interrupts at levels above XTOS_LOCK_LEVEL, + * and that it never be modified when the current interrupt level is below + * XTOS_LOCK_LEVEL. This is because modifications to INTENABLE generally + * require an RSR/modify/WSR sequence to modify only selected bits. + * + * NOTE: Reading the INTERRUPT register *must* be done at PS.INTLEVEL <= 1 + * otherwise we might incorrectly see higher priority interrupts. + * + * This option implies XEA2, because XEA1 always requires INTENABLE virtualization. + * This option also implies SUBPRI is zero (no interrupt sub-prioritization in software). + */ + + + rsr a15, INTERRUPT // interrupts pending + rsr a13, INTENABLE // interrupts enabled (directly; no virtualization) + movi a14, _xtos_interrupt_table - IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 ) +NEEDSAR rsr a12, SAR + and a15, a15, a13 // a15 = INTERRUPT & INTENABLE + + _beqz a15, spurious_int // no interrupt to handle (spurious interrupt) +NEEDSAR s32i a12, a1, UEXC_sar + +IFFAIR s32i a2, a1, UEXC_exccause // save a2 (interrupted code's a6) +IFFAIR movi a2, -1 // initial fairness mask + +.L1_loop0: + // Entry: + // a12 = (undefined) + // a13 = (undefined) + // a14 = interrupt table adjusted base (not used here) + // a15 = non-zero mask of interrupt bits to consider handling + // Exit: + // a12 = index + // a13 = (clobbered) + // a14 = (preserved) + // a15 = single bit corresponding to index + // + indexmask_int a12, a15, a14_UNUSED, a13 + + // a12 = index of highest priority pending+enabled interrupt, to be processed. + // a15 = (1 << a12), ie. bit corresponding to interrupt to be processed. +IFFAIR xor a2, a2, a15 // update fairness mask - mask out this interrupt until recycling mask + wsr a15, INTCLEAR // clear interrupt (if software or external edge-triggered or write-error) + + addx8 a12, a12, a14 // a12 = address in interrupt table for given interrupt number + +.L1_loop1: + // a12 now contains pointer to interrupt table entry for interrupt to be processed + + // HERE: + // a12 = pointer to interrupt entry in table + // a13, a15 = available for use + // a14 = available for use if virtual INTENABLE, else is pointer to interrupt table + + +# endif /* !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */ + /* At this point, PS.INTLEVEL is: 1 if XEA2 and (XTOS_SINGLE_INT || !XTOS_VIRTUAL_INTENABLE), 0 otherwise */ + + // HERE: a12 = pointer to interrupt entry in table + + // (Possible enhancement: do at higher-level, to avoid doing it all the time? !?!?!?) + save_loops_mac16 a1, a13, a15 // save LOOP & MAC16 regs, if configured + +LATESAR rsr a15, SAR + +# if 0 + /* ... alternate code to allow context-switching would go here ... */ +# else + l32i a13, a12, XIE_HANDLER // a13 = address of interrupt handler +LATESAR s32i a15, a1, UEXC_sar +# endif + +# ifdef __XTENSA_CALL0_ABI__ + l32i a2, a12, XIE_ARG // first arg + mov a3, a1 // second arg, exception stack frame + callx0 a13 // call interrupt handler +# else + mov a15, a1 // second arg, exception stack frame + l32i a14, a12, XIE_ARG // first argument passed to interrupt handler (relayed by context-dispatcher, if non-nested) + callx12 a13 // execute interrupt handler, directly or via context-dispatcher (clobbers a12-a15) +# endif + + // (Possible enhancement: do at higher-level, to avoid doing it all the time? !?!?!?) + restore_loops_mac16 a1, a13, a14, a15 // restore LOOP & MAC16 regs, if configured + +LATESAR l32i a12, a1, UEXC_sar + + +# if XTOS_VIRTUAL_INTENABLE + /* Here, INTENABLE register is virtualized. */ + + movi a14, _xtos_intstruct // address of interrupt management globals +LATESAR wsr a12, SAR +# if XCHAL_HAVE_XEA1 + movi a12, XTOS_UNLOCKABLE_MASK // mask out levels covered by XTOS_LOCKLEVEL + // so we can run at PS.INTLEVEL=0 (for the RETW below) + // while manipulating virtual INTENABLE +# endif + rsr a15, INTERRUPT + rsil a13, XTOS_LOCKLEVEL + l32i a13, a14, XTOS_ENABLED_OFS // a13 = _xtos_enabled +# if XCHAL_HAVE_XEA1 + and a12, a12, a13 // compute new INTENABLE + wsr a12, INTENABLE // mask out at XTOS_LOCKLEVEL via INTENABLE +# endif + l32i a12, a1, UEXC_vpri // read saved vpri + //interlock + and a13, a13, a12 // a13 = old-vpri & _xtos_enabled (INTENABLE value to restore) + and a15, a15, a13 // what's pending among what we can handle? + + + // a15 now contains the remaining pending+enabled interrupts. + // NOTE: we MUST NOT consider interrupts potentially already being handled + // by another interrupt handler that we pre-empted. + // So we masked with saved vpri, ie. the set of interrupts enabled when we entered + // this handler, ie. the set of interrupts that can pre-empt the previous context. +NOFAIR _bnez a15, .L1_loop0 // more interrupt(s) to handle +IFFAIR _bnez a15, preloop // more interrupt(s) to handle +IFFAIR l32i a2, a1, UEXC_exccause // restore a2 (interrupted code's a6) + + + // NOTE: + // Register allocation is why we didn't restore *HERE* the loop regs, MAC16, SAR, etc. + // (at least part of the reason) + // We only have one registers (a15), however with 7-stage pipe, three registers + // are required to avoid interlocks. We could get 2 more registers at 1 cycle each [now only one?], + // but it isn't obvious whether paying these extra cycles are worth it... + + // Restore vpri as it was before we handled the interrupt(s): + s32i a12, a14, XTOS_VPRI_ENABLED_OFS // restore _xtos_vpri_enabled +NEEDSAR l32i a12, a1, UEXC_sar +# if XCHAL_HAVE_XEA1 + s32i a13, a1, UEXC_sar // save new INTENABLE value across RETW +# else + wsr a13, INTENABLE // update INTENABLE per original vpri + + // NOTE: leave locked, disabling only the low- and medium-priority interrupts + rsilft a13, XTOS_LOCKLEVEL, XCHAL_EXCM_LEVEL // lockout +# undef CUR_INTLEVEL +# define CUR_INTLEVEL XCHAL_EXCM_LEVEL +# endif + +# elif XTOS_SINGLE_INT + +# undef NEEDSAR +# define NEEDSAR + +# else /* ie. if !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */ + /* Here, INTENABLE register is NOT virtualized (implies XEA2). */ + + rsr a15, INTERRUPT // interrupts pending + rsr a13, INTENABLE // interrupts enabled (directly; no virtualization) + movi a14, _xtos_interrupt_table - IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 ) +LATESAR wsr a12, SAR + and a15, a15, a13 // a15 = INTERRUPT & INTENABLE + + // a15 now contains the remaining pending+enabled interrupts. + // NOTE: we MUST NOT consider interrupts potentially already being handled + // by another interrupt handler that we pre-empted. + // So we masked with saved vpri, ie. the set of interrupts enabled when we entered + // this handler, ie. the set of interrupts that can pre-empt the previous context. +NOFAIR _bnez a15, .L1_loop0 // more interrupt(s) to handle +IFFAIR _bnez a15, preloop // more interrupt(s) to handle +IFFAIR l32i a2, a1, UEXC_exccause // restore a2 (interrupted code's a6) + + + // NOTE: + // Register allocation is why we didn't restore *HERE* the loop regs, MAC16, SAR, etc. + // (at least part of the reason) + // We only have one registers (a15), however with 7-stage pipe, three registers + // are required to avoid interlocks. We could get 2 more registers at 1 cycle each [now only one?], + // but it isn't obvious whether paying these extra cycles are worth it... + +NEEDSAR l32i a12, a1, UEXC_sar +# endif /* !XTOS_VIRTUAL_INTENABLE && !XTOS_SINGLE_INT */ + + + /***************************/ + + // Now exit the handler. + + /* + * Leave interrupts disabled while returning from the pseudo-CALL setup above, + * for the same reason they were disabled while doing the pseudo-CALL: + * this sequence restores SP such that it doesn't reflect the allocation + * of the exception stack frame, which is still needed to return from + * the exception. + */ + +spurious_int: + + movi a0, _xtos_return_from_exc +# ifdef __XTENSA_CALL0_ABI__ +NEEDSAR wsr a12, SAR + jx a0 +# else /* ! __XTENSA_CALL0_ABI__ */ + // Now return from the pseudo-CALL from the interrupted code, to rotate + // our windows back... + + movi a13, 0xC0000000 +NEEDSAR wsr a12, SAR + or a0, a0, a13 // set upper two bits + addx2 a0, a13, a0 // clear upper bit + +# if XCHAL_HAVE_XEA2 + // Disable ints during unalloc'ed live stack after RETW below. + rsil a13, XCHAL_EXCM_LEVEL // might come here via spurious_int, so always rsil +# endif + + retw +# endif /* __XTENSA_CALL0_ABI__ */ + + + +# if XTOS_INT_FAIRNESS +preloop: + // Lowering priority or recycling fairness-mask bits ... + // a14 = &_xtos_intstruct *or* interrupt table ptr + // a15 = non-zero mask of interrupt bits to consider handling + +# if !XTOS_SUBPRI + and a13, a15, a2 // a13 = interrupt bits to consider handling, masked for fairness + movi a12, -1 // (new fairness mask, all one's) + moveqz a2, a12, a13 // recycle fairness mask if all bits to consider are masked by fairness, and leave a15 intact + movnez a15, a13, a13 // otherwise set a15 = a13, ie. mask out bits for fairness (a15 is still non-zero) + j .L1_loop0 +# else /* XTOS_SUBPRI */ + // NOTE: In this case, with SUBPRI, XTOS_VIRTUAL_INTENABLE is always set. + // So: a14 = &_xtos_intstruct + + // Compute a13 = index of highest priority interrupt in a15 (a13 is reversed if NSA present) + // (a14, a15 preserved; a12 is a temporary): + index_int a13, a15, a14, a12 + + // a12 = (available) + // a13 = index + // a14 = &_xtos_intstruct + // a15 = mask of candidates + movi a12, _xtos_interrupt_table - IFNSA( (32-XCHAL_NUM_INTERRUPTS)*XIE_SIZE, 0 ) + //slot + addx8 a12, a13, a12 // a12 = address in interrupt table for given interrupt number + l32i a14, a12, XIE_LEVELMASK // a14 = mask of all interrupts at selected interrupt's level + and a15, a15, a2 // mask out for fairness + and a15, a15, a14 // only consider interrupts at highest pending level + movi a14, _xtos_intstruct // needed at loop0, and below + _bnez a15, .L1_loop0 // interrupts are allowed by current fairness mask, redo indexing with proper mask (a15, a14 = ...) + + // a12 = ptr to interrupt entry + // a13 = index + // a14 = &_xtos_intstruct + // a15 = (available) + + // Compute bitmask of interrupt to be processed... +# if XCHAL_HAVE_NSA + movi a15, 0x80000000 + ssr a13 + srl a13, a15 +# else + movi a15, 1 + ssl a13 + sll a13, a15 +# endif + // a13 = single bit set corresponding to interrupt to be processed... + l32i a15, a12, XIE_LEVELMASK // a15 = mask of all interrupts at selected interrupt's level + wsr a13, INTCLEAR // clear interrupt (if software or external edge-triggered or write-error) + or a2, a2, a15 // recycle fairness mask for selected interrupt level + xor a2, a2, a13 // update fairness mask - mask out this interrupt until recycling mask + j .L1_loop1 // handle selected interrupt (a12 = interrupt entry, a14 = &_xtos_intstruct) + +# endif /* XTOS_SUBPRI */ +# endif /* XTOS_INT_FAIRNESS */ + + /* FIXME: what about _LevelOneInterrupt ? */ + .size _xtos_l1int_handler, . - _xtos_l1int_handler + +#endif /* XCHAL_HAVE_EXCEPTIONS && XCHAL_HAVE_INTERRUPTS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-medpri-dispatcher.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-medpri-dispatcher.S new file mode 100755 index 0000000..d60d07e --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-medpri-dispatcher.S @@ -0,0 +1,254 @@ +// Medium-Priority Interrupt Dispatcher Template +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/int-medpri-dispatcher.S#4 $ + +// Copyright (c) 2004-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// +// By default, this file is included by inth-template.S . +// The default Makefile defines _INTERRUPT_LEVEL when assembling +// inth-template.S for each medium and high priority interrupt level. +// +// To use this template file, define a macro called _INTERRUPT_LEVEL +// to be the interrupt priority level of the vector, then include this file. + + +#include +#include "xtos-internal.h" + + +#if XCHAL_HAVE_INTERRUPTS + +#define INTERRUPT_MASK XCHAL_INTLEVEL_MASK(_INTERRUPT_LEVEL) +#define SINGLE_INTERRUPT ((INTERRUPT_MASK & (INTERRUPT_MASK - 1)) == 0) +#define SINGLE_INT_NUM XCHAL_INTLEVEL_NUM(_INTERRUPT_LEVEL) + + +// Strict non-preemptive prioritization + + + .text + .align 4 + .global LABEL(_Level,FromVector) +LABEL(_Level,FromVector): + +/* Allocate an exception stack frame, save a2, a4, and a5, and fix PS as: + * + * if not Call0 ABI + * - enable windowing for 'entry' (ps.woe=1, ps.excm=0) + * - setup ps.callinc to simulate call4 + * endif + * - preserve user mode + * - mask all interrupts at EXCM_LEVEL and lower + * + * Then deallocate the stack, 'rsync' for the write to PS, then use + * 'entry' to re-allocate the stack frame and rotate the register + * window (like a call4, preserving a0..a3). */ + +#if HAVE_XSR + xsr a2, EXCSAVE_LEVEL +#else + rsr a2, EXCSAVE_LEVEL +#endif + addi a1, a1, -ESF_TOTALSIZE + s32i a2, a1, UEXC_a2 +#ifdef __XTENSA_CALL0_ABI__ + movi a2, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) +#else + movi a2, PS_WOE|PS_CALLINC(1)|PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL) +#endif + s32i a4, a1, UEXC_a4 + s32i a5, a1, UEXC_a5 + wsr a2, PS + rsync + +#ifdef __XTENSA_CALL0_ABI__ + s32i a0, a1, UEXC_a0 + s32i a3, a1, UEXC_a3 + s32i a6, a1, UEXC_a6 + s32i a7, a1, UEXC_a7 + s32i a8, a1, UEXC_a8 + s32i a9, a1, UEXC_a9 + s32i a10, a1, UEXC_a10 + s32i a11, a1, UEXC_a11 + s32i a12, a1, UEXC_a12 + s32i a13, a1, UEXC_a13 + s32i a14, a1, UEXC_a14 + s32i a15, a1, UEXC_a15 + movi a0, 0 /* terminate stack frames */ +# if XTOS_DEBUG_PC + // TODO: setup return PC for call traceback through interrupt dispatch +# endif +#else +# if XTOS_CNEST + l32i a2, a1, ESF_TOTALSIZE-20 // save nested-C-func call-chain ptr +# endif + addi a1, a1, ESF_TOTALSIZE +# if XTOS_DEBUG_PC + rsr a4, EPC+_INTERRUPT_LEVEL // [for debug] get return PC + movi a5, 0xC0000000 // [for debug] setup call size... + or a4, a5, a4 // [for debug] set upper two bits of return PC + addx2 a4, a5, a4 // [for debug] clear upper bit +# else + movi a4, 0 /* terminate stack frames, overflow check */ +# endif + _entry a1, ESF_TOTALSIZE +#endif + +/* Reset the interrupt level to mask all interrupts at the current + * priority level and lower. Note the current priority level may be + * less than or equal to EXCM_LEVEL. */ + + rsil a15, _INTERRUPT_LEVEL + +#if SINGLE_INTERRUPT /* if only one interrupt at this priority level... */ + +/* Preserve the SAR, loop, and MAC16 regs. Also, clear the interrupt. */ + + rsr a14, SAR + movi a12, INTERRUPT_MASK + s32i a14, a1, UEXC_sar + wsr a12, INTCLEAR // clear if edge-trig or s/w or wr/err (else no effect) + save_loops_mac16 a1, a13, a14 + +/* Load the handler from the table, initialize two args (interrupt + * number and exception stack frame), then call the interrupt handler. + * Note: The callx12 preserves the original user task's a4..a15.*/ + + movi a12, _xtos_interrupt_table + MAPINT(SINGLE_INT_NUM)*XIE_SIZE + l32i a13, a12, XIE_HANDLER +# ifdef __XTENSA_CALL0_ABI__ + l32i a2, a12, XIE_ARG + mov a3, a1 + callx0 a13 +# else + l32i a14, a12, XIE_ARG + mov a15, a1 + callx12 a13 +# endif + +#else /* > 1 interrupts at this priority level */ + +/* Get bit list of pending interrupts at the current interrupt priority level. + * If bit list is empty, interrupt is spurious (can happen if a + * genuine interrupt brings control this direction, but the interrupt + * goes away before we read the INTERRUPT register). Also save off + * sar, loops, and mac16 registers. */ + + rsr a15, INTERRUPT + rsr a12, INTENABLE + movi a13, INTERRUPT_MASK + and a15, a15, a12 + and a15, a15, a13 + rsr a14, SAR + _beqz a15, LABEL(spurious,int) + s32i a14, a1, UEXC_sar + save_loops_mac16 a1, a13, a14 + +/* Loop to handle all pending interrupts. */ + +LABEL(.L1,_loop0): + neg a12, a15 + and a12, a12, a15 + wsr a12, INTCLEAR // clear if edge-trig or s/w or wr/err (else no effect) + movi a13, _xtos_interrupt_table + find_ms_setbit a15, a12, a14, 0 + mapint a15 + addx8 a12, a15, a13 + l32i a13, a12, XIE_HANDLER +# ifdef __XTENSA_CALL0_ABI__ + l32i a2, a12, XIE_ARG + mov a3, a1 + callx0 a13 +# else + l32i a14, a12, XIE_ARG + mov a15, a1 + callx12 a13 +# endif + rsr a15, INTERRUPT + rsr a12, INTENABLE + movi a13, INTERRUPT_MASK + and a15, a15, a12 + and a15, a15, a13 + _bnez a15, LABEL(.L1,_loop0) + +#endif /* SINGLE_INTERRUPT */ + +/* Restore everything, and return. */ + + restore_loops_mac16 a1, a13, a14, a15 + l32i a14, a1, UEXC_sar +LABEL(spurious,int): + +#ifdef __XTENSA_CALL0_ABI__ + wsr a14, SAR + l32i a0, a1, UEXC_a0 + l32i a2, a1, UEXC_a2 + l32i a3, a1, UEXC_a3 + l32i a4, a1, UEXC_a4 + l32i a5, a1, UEXC_a5 + l32i a6, a1, UEXC_a6 + l32i a7, a1, UEXC_a7 + l32i a8, a1, UEXC_a8 + l32i a9, a1, UEXC_a9 + l32i a10, a1, UEXC_a10 + l32i a11, a1, UEXC_a11 + l32i a12, a1, UEXC_a12 + l32i a13, a1, UEXC_a13 + l32i a14, a1, UEXC_a14 + l32i a15, a1, UEXC_a15 + addi a1, a1, ESF_TOTALSIZE // restore sp + rfi _INTERRUPT_LEVEL + +#else /* windowed ABI: */ + + movi a0, LABEL(return,from_exc) + movi a13, 0xC0000000 + wsr a14, SAR + or a0, a0, a13 + addx2 a0, a13, a0 +# if _INTERRUPT_LEVEL < XCHAL_EXCM_LEVEL +/* Raise the interrupt mask before + * returning to avoid a race condition where we deallocate the + * exception stack frame but still have more register values to + * restore from it. */ + rsil a14, XCHAL_EXCM_LEVEL +# endif + retw +LABEL(return,from_exc): +# if XTOS_CNEST + s32i a2, a5, ESF_TOTALSIZE-20 // restore nested-C-func call-chain ptr +# endif + l32i a2, a5, UEXC_a2 + l32i a4, a5, UEXC_a4 + l32i a5, a5, UEXC_a5 + rfi _INTERRUPT_LEVEL +#endif /* windowed ABI */ + + .size LABEL(_Level,FromVector), . - LABEL(_Level,FromVector) + + // This symbol exists solely for the purpose of being able to pull-in this + // dispatcher using _xtos_dispatch_level() routines with the tiny-rt LSP: + .global LABEL(_Level,HandlerLabel) + .set LABEL(_Level,HandlerLabel), 0 + +#endif /* XCHAL_HAVE_INTERRUPT */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-sethandler.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-sethandler.c new file mode 100755 index 0000000..98bdb39 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-sethandler.c @@ -0,0 +1,116 @@ +/* int-sethandler.c - register an interrupt handler in XTOS */ + +/* + * Copyright (c) 1999-2006 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "xtos-internal.h" + + +#if XCHAL_HAVE_INTERRUPTS +/* + * Table of interrupt handlers. + * NOTE: if the NSA/NSAU instructions are configured, then to save + * a few cycles in the interrupt dispatcher code, the + * _xtos_interrupt_table[] array is filled in reverse. + * IMPORTANT: Use the MAPINT() macro defined in xtos-internal.h to index entries in this array. + */ +extern XtosIntHandlerEntry _xtos_interrupt_table[XCHAL_NUM_INTERRUPTS]; +extern void _xtos_unhandled_interrupt(); +#endif + + +_xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg ) +{ +#if XCHAL_HAVE_INTERRUPTS + XtosIntHandlerEntry *entry; + _xtos_handler old; + + if( n < 0 || n >= XCHAL_NUM_INTERRUPTS ) + return 0; /* invalid interrupt number */ + if( Xthal_intlevel[n] > XTOS_LOCKLEVEL ) + return 0; /* priority level too high to safely handle in C */ + entry = _xtos_interrupt_table + MAPINT(n); + old = entry->handler; + if (f) { + entry->handler = f; + entry->arg = arg; + } else { + entry->handler = &_xtos_unhandled_interrupt; + entry->arg = (void*)n; + } + return ((old == &_xtos_unhandled_interrupt) ? 0 : old); +#else + return 0; +#endif +} + + +_xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f ) +{ + return _xtos_set_interrupt_handler_arg( n, f, (void*) n ); +} + + +#if 0 +/* + * User vector mode exception handler for the LEVEL1_INTERRUPT cause. + * NOTE: this is now implemented in assembler for performance. + * This C handler is left as an example interrupt dispatcher written in C. + * The actual handler in int-lowpri-dispatcher.S is more fully featured. + */ +UserFrame* _xtos_p_level1int_handler( UserFrame* uf /*, int cause */ ) +{ +#if XCHAL_HAVE_INTERRUPTS + unsigned int ints; + unsigned int index; + + ints = xthal_get_interrupt(); +# if XTOS_VIRTUAL_INTENABLE + ints &= _xtos_enabled; +# else + ints &= xthal_get_intenable(); +# endif + for( index = 0 ; ints != 0 ; ints >>= 1, index++ ) + { + if( ints & 1 ) + { + void (*f)(); + + /* + * Clear interrupt (in case it's edge-triggered or software or write-error). + * This must be done *before* processing the interrupt. + */ + xthal_set_intclear( 1 << index ); + + f = _xtos_interrupt_table[MAPINT(index)].handler; + if( f ) + f( _xtos_interrupt_table[MAPINT(index)].arg /*, uf, index*/ ); + } + } +#endif /*XCHAL_HAVE_INTERRUPTS*/ + return uf; +} +#endif + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-vector.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-vector.S new file mode 100755 index 0000000..cc2f85d --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/int-vector.S @@ -0,0 +1,68 @@ +// int-vector.S - Interrupt Vector Template (for levels > 1) +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/int-vector.S#3 $ + +// Copyright (c) 2003-2004, 2006, 2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +// To use this template file, define a macro called _INTERRUPT_LEVEL +// to be the interrupt level of the vector, include "xtos-internal.h", +// then include this file. We use the same template for both high-level +// and medium-level interrupts, but not debug level. + + +#define _ASMLANGUAGE +#include "xtos-internal.h" +#include + + +#if XCHAL_HAVE_INTERRUPTS && (_INTERRUPT_LEVEL <= XCHAL_NUM_INTLEVELS) && (_INTERRUPT_LEVEL != XCHAL_DEBUGLEVEL) + + .begin literal_prefix LABEL(.Level,InterruptVector) + .section LABEL(.Level,InterruptVector.text), "ax" + .align 4 + .global LABEL(_Level,Vector) +LABEL(_Level,Vector): + // Medium and high priority interrupt vector: + +# if HAVE_XSR + // With XSR, we can use this vector which has the advantage of being ROMable + // without requiring the handler to also be in ROM; however, it requires + // initializing the EXCSAVEn register (see ResetEpilog.S) and a slightly + // different save/restore sequence in the handler: + xsr a2, EXCSAVE_LEVEL + jx a2 + + // Pull-in the real handler by reference, to ensure the reset epilog gets it: + .global LABEL(_Level,FromVector) + +# else + wsr a2, EXCSAVE_LEVEL + movi a2, LABEL(_Level,FromVector) + jx a2 +# endif + + .size LABEL(_Level,Vector), . - LABEL(_Level,Vector) + .text + .end literal_prefix + +#endif /* interrupt at that level */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/interrupt-pri.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/interrupt-pri.h new file mode 100755 index 0000000..41116a5 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/interrupt-pri.h @@ -0,0 +1,178 @@ +/* interrupt-pri.h - Definitions and macros related to interrupt prioritization */ +/* + * Copyright (c) 2002-2004, 2006 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) +# error "The interrupt-pri.h header file is meant for inclusion by assembly source code only." +#endif + +#include +#include +#include "xtos-internal.h" + +/* + * The following macros are used by int-lowpri-dispatcher.S to + * implement prioritized interrupt dispatching and fairness. + * The prioritization scheme is set by XTOS parameters in xtos-params.h . + */ + + +#if XCHAL_HAVE_INTERRUPTS + + // msindex_int + // + // Return in register \aindex the index of the first (most significant) bit set + // in register \amask. + // Register \amask is clobbered (modified) by this macro. + // + // Note: this code is similar to the find_ms_setbit macro in . + // + .macro msindex_int aindex, amask +# if XCHAL_HAVE_NSA + nsau \aindex, \amask // \aindex = interrupt index, from 0 to 31, from left to right + //movi \amask, 31 + //sub \aindex, \amask, \aindex +# else + movi \aindex, 0 // start with result of 0 (point to lsbit of 32) +# if XCHAL_NUM_INTERRUPTS > 16 + bltui \amask, 0x10000, 2f // is it one of the 16 lsbits? (if so, check lower 16 bits) + addi \aindex, \aindex, 16 // no, increment result to upper 16 bits (of 32) + extui \amask, \amask, 16, 16 // check upper half (shift right 16 bits) +2: +# endif +# if XCHAL_NUM_INTERRUPTS > 8 + bltui \amask, 0x100, 2f // is it one of the 8 lsbits? (if so, check lower 8 bits) + addi \aindex, \aindex, 8 // no, increment result to upper 8 bits (of 16) + srli \amask, \amask, 8 // shift right to check upper 8 bits +2: +# endif +# if XCHAL_NUM_INTERRUPTS > 4 + bltui \amask, 0x10, 2f // is it one of the 4 lsbits? (if so, check lower 4 bits) + addi \aindex, \aindex, 4 // no, increment result to upper 4 bits (of 8) + srli \amask, \amask, 4 // shift right 4 bits to check upper half +2: +# endif + bltui \amask, 0x4, 2f // is it one of the 2 lsbits? (if so, check lower 2 bits) + addi \aindex, \aindex, 2 // no, increment result to upper 2 bits (of 4) + srli \amask, \amask, 2 // shift right 2 bits to check upper half +2: + bltui \amask, 0x2, 2f // is it the lsbit? + addi \aindex, \aindex, 1 // no, increment result to upper bit (of 2) +2: // done! +# endif /*!NSA*/ + // HERE: \aindex = index of interrupt to handle + // \amask is available + .endm + + + // msindex_int_nc + // + // Same as msindex_int, but does not clobber \amask. + // Uses extra register \atmp (a temporary register) if needed. + // + .macro msindex_int_nc aindex, amask, atmp +# if XCHAL_HAVE_NSA + msindex_int \aindex, \amask // does not clobber \amask in this case +# else + mov \atmp, \amask + msindex_int \aindex, \atmp +# endif + .endm + + + // indexmask_int + // + // Compute index of highest priority interrupt in given mask, + // and trim mask to single bit corresponding to that interrupt. + // This is used for interrupt dispatching. + // + // Entry: + // \index = (undefined) + // \mask = non-zero mask of interrupt bits to consider handling + // \intptr = &_xtos_intstruct if INTENABLE virtualized, else undefined + // \tmp = (undefined) + // Exit: + // \index = index of interrupt (reversed if NSA present) + // \mask = single bit corresponding to index + // \intptr = (preserved) + // \tmp = (clobbered) + // + .macro indexmask_int index, mask, intptr, tmp +# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_LO + + msindex_int \index, \mask // \index = index of msbit set in \mask (\tmp is tmp, \mask clobbered) + // \index now contains the index of the highest priority pending+enabled interrupt. +# if XCHAL_HAVE_NSA + movi \mask, 0x80000000 + ssr \index + srl \mask, \mask // \mask = single bit set corresponding to interrupt to be processed... +# else + movi \mask, 1 + ssl \index + sll \mask, \mask // \mask = single bit set corresponding to interrupt to be processed... +# endif + +# elif XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI + + neg \index, \mask // find lsbit in \mask ... + and \mask, \index, \mask // ... + msindex_int_nc \index, \mask, \tmp // \index = index of msbit set in \mask (\tmp is tmp, \mask not clobbered) + +# else +# error Unsupported priority ordering. +# endif /*SUBPRI_ORDER*/ + .endm + + + // index_int + // + // Compute index of highest priority interrupt in given mask. + // This is used for fairness computations. + // + // Entry: + // \index = (undefined) + // \mask = non-zero mask of interrupt bits to consider handling + // \intptr = &_xtos_intptr + // \tmp = (undefined) + // Exit: + // \index = index of interrupt (reversed if NSA present) + // \mask = (preserved) + // \intptr = (preserved) + // \tmp = (clobbered) + // + .macro index_int index, mask, intptr, tmp +# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_LO + msindex_int_nc \index, \mask, \tmp // \index = index of msbit set in \mask (\mask not clobbered) +# elif XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI + neg \tmp, \mask // find lsbit in \mask ... + and \tmp, \tmp, \mask // ... + msindex_int \index, \tmp // \index = index of msbit set in \tmp (\tmp is clobbered) +# else +# error oops +# endif + .endm // index_int + + +#endif /* XCHAL_HAVE_INTERRUPTS */ + + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/interrupt-table.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/interrupt-table.S new file mode 100755 index 0000000..f933fb5 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/interrupt-table.S @@ -0,0 +1,134 @@ +// interrupt-table.S - Interrupt handler table and default handler + +// Copyright (c) 2004-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" +#ifdef SIMULATOR +#include +#endif + + +#if XCHAL_HAVE_INTERRUPTS + + .data + + .global _xtos_intstruct + .align 8 +_xtos_intstruct: +# if XTOS_VIRTUAL_INTENABLE + .global _xtos_enabled + .type _xtos_enabled,@object + .size _xtos_enabled,4 + .global _xtos_vpri_enabled + .type _xtos_vpri_enabled,@object + .size _xtos_vpri_enabled,4 +_xtos_enabled: .word 0 +_xtos_vpri_enabled: .word 0xFFFFFFFF +# endif +# if XTOS_VIRTUAL_INTERRUPT +# error Virtualized INTERRUPT register not yet supported. + .global _xtos_pending + .type _xtos_pending,@object + .size _xtos_pending,4 +_xtos_pending: .word 0 +# endif + + /* + * Table of C-level interrupt handlers (and args, etc) for each interrupt. + * NOTE: if the NSA/NSAU instructions are configured, then to save a few + * cycles in the interrupt dispatcher code, this table is filled in reverse. + * C code uses the MAPINT() macro defined in xtos-internal.h to index entries. + * NOTE: Under some conditions (turned off by default in xtos-params.h), + * this table gets properly initialized by the _xtos_init() function in + * init.c . NOTA: A future enhancement may be to always configure + * and build this table at build-time rather than ever doing it at run-time. + */ +#define i .Li /* workaround a silly GDB testsuite regression */ + .data + .global _xtos_interrupt_table + .align 8 +_xtos_interrupt_table: + .set i, XCHAL_HAVE_NSA*(XCHAL_NUM_INTERRUPTS-1) + .rept XCHAL_NUM_INTERRUPTS + .word _xtos_unhandled_interrupt + .word i // parameter: interrupt number + .set i, i+1-(XCHAL_HAVE_NSA*2) + .endr + +# if XIE_EXTEND + /* MUST *IMMEDIATELY* follow _xtos_interrupt_table: */ + .global _xtos_interrupt_mask_table +_xtos_interrupt_mask_table: + .set i, XCHAL_HAVE_NSA*(XCHAL_NUM_INTERRUPTS-1) + .rept XCHAL_NUM_INTERRUPTS + /* Default to all low-priority (level-one) interrupts at their own virtual priority: */ +# if XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI + .word ((1< XCHAL_DEBUGLEVEL + rsil a3, XCHAL_DEBUGLEVEL-1 // ensure break takes effect +# endif + break 1, 15 // unhandled (unregistered) interrupt $a2 +//# elif defined(SIMULATOR) +// addmi a2, a2, SYS_unhandled_interrupt ... +// simcall // unhandled interrupt +# else +1: j 1b // unhandled interrupt - loop forever +# endif + abi_return + + .size _xtos_unhandled_interrupt, . - _xtos_unhandled_interrupt + +#endif /* XCHAL_HAVE_INTERRUPTS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/intlevel-restore.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/intlevel-restore.S new file mode 100755 index 0000000..a1490e8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/intlevel-restore.S @@ -0,0 +1,92 @@ +// intlevel-restore.S - Interrupt related assembler code - _xtos_restore_intlevel + +// Copyright (c) 2004-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" + + +/*************************************************************************** + * void _xtos_restore_intlevel(unsigned restoreval); + * + * _xtos_restore_intlevel() restores the current interrupt level + * according to a value returned by _xtos_set_intlevel() or + * _xtos_set_min_intlevel() (or one of the corresponding macros). + * + * NOTE: In XEA2, this function may restore the entire PS register, not + * just the PS.INTLEVEL field. If some other PS field(s) must be changed + * and kept intact across restoring PS.INTLEVEL (this is generally unlikely), + * use the XTOS_RESTORE_JUST_INTLEVEL() macro instead (which is slower). + * + * NOTE: In XEA1, this function is implemented further below, identically + * to _xtos_set_vpri(). + * + * NOTE: The macro form of this function (XTOS_RESTORE_INTLEVEL()) + * is recommended (for XEA2 configs or where the config is unknown) + * because it may be more efficient. + */ + + .text + .global _xtos_restore_intlevel + .type _xtos_restore_intlevel,@function +#if XCHAL_HAVE_XEA2 + .align 4 +_xtos_restore_intlevel: + abi_entry +# if XCHAL_HAVE_INTERRUPTS + wsr a2, PS // restore PS + rsync // wait for WSR to PS to complete +# endif + abi_return + .size _xtos_restore_intlevel, . - _xtos_restore_intlevel +#endif + + + +/*************************************************************************** + * _xtos_set_vpri() is used to set the current virtual priority from C code; + * it can be called from the application or from a C interrupt handler. + */ + + .global _xtos_set_vpri + .type _xtos_set_vpri,@function + .align 4 +_xtos_set_vpri: +#if XCHAL_HAVE_XEA1 +_xtos_restore_intlevel: +#endif + abi_entry +#if XCHAL_HAVE_INTERRUPTS && XTOS_VIRTUAL_INTENABLE + mov a3, a2 + movi a4, _xtos_intstruct + xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section + l32i a2, a4, XTOS_VPRI_ENABLED_OFS // return old xtos_vpri_enabled (current vpri) + l32i a5, a4, XTOS_ENABLED_OFS // a3 = xtos_enabled + s32i a3, a4, XTOS_VPRI_ENABLED_OFS // set new xtos_vpri_enabled (current vpri) + and a5, a5, a3 // a5 = xtos_enabled & xtos_vpri_enabled + wsr a5, INTENABLE + xtos_unlock a7 +#endif /*XCHAL_HAVE_INTERRUPTS*/ + abi_return + .size _xtos_set_vpri, . - _xtos_set_vpri + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/intlevel-set.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/intlevel-set.S new file mode 100755 index 0000000..33167a7 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/intlevel-set.S @@ -0,0 +1,79 @@ +// intlevel-set.S - Interrupt related assembler code - _xtos_set_intlevel + +// Copyright (c) 2004-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" + + +/*************************************************************************** + * unsigned _xtos_set_intlevel(int intlevel); + * + * _xtos_set_intlevel() is used to set the current priority from C code; + * it can be called from the application or from a C interrupt handler. + * + * NOTE: This version allows the 'intlevel' parameter to be computed + * at run-time, and thus is longer. It is much more efficient, and + * highly recommented, to use the XTOS_SET_INTLEVEL(intlevel) macro instead + * (which requires a constant intlevel). + */ + + .text + .align 4 + .global _xtos_set_intlevel + .type _xtos_set_intlevel,@function +_xtos_set_intlevel: + abi_entry +#if XCHAL_HAVE_INTERRUPTS +# if XCHAL_HAVE_XEA2 + /* In XEA2, we can simply safely set PS.INTLEVEL directly: */ + rsr a3, PS // get old (current) PS.INTLEVEL + movi a4, ~0xF + extui a2, a2, 0, 4 // keep only INTLEVEL bits of parameter + and a4, a4, a3 // mask out PS.INTLEVEL + or a4, a4, a2 // insert requested INTLEVEL + wsr a4, PS // update PS.INTLEVEL + extui a2, a3, 0, 4 // return only old PS.INTLEVEL field + rsync // wait for WSR to PS to complete +# else + /* In XEA1, we have to rely on INTENABLE register virtualization: */ + movi a4, Xthal_intlevel_andbelow_mask + extui a3, a2, 0, 4 // keep only INTLEVEL bits of parameter + addx4 a5, a3, a4 // index mask to use + l32i a3, a5, 0 // get mask of interrupts at requested intlevel and below + movi a5, -1 // all 1's + movi a4, _xtos_intstruct + xor a3, a3, a5 // mask of interrupts at intlevels above the requested one (to enable) + xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section + l32i a2, a4, XTOS_VPRI_ENABLED_OFS // return old xtos_vpri_enabled (current vpri) + l32i a5, a4, XTOS_ENABLED_OFS // a5 = xtos_enabled + s32i a3, a4, XTOS_VPRI_ENABLED_OFS // set new xtos_vpri_enabled (current vpri) + and a5, a5, a3 // a5 = xtos_enabled & xtos_vpri_enabled + wsr a5, INTENABLE + xtos_unlock a7 +# endif +#endif /*XCHAL_HAVE_INTERRUPTS*/ + abi_return + + .size _xtos_set_intlevel, . - _xtos_set_intlevel + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/intlevel-setmin.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/intlevel-setmin.S new file mode 100755 index 0000000..d65d8fe --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/intlevel-setmin.S @@ -0,0 +1,85 @@ +// intlevel-setmin.S - Interrupt related assembler code - _xtos_set_min_intlevel + +// Copyright (c) 2004-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" + + +/*************************************************************************** + * unsigned _xtos_set_min_intlevel(int intlevel); + * + * _xtos_set_min_intlevel() is identical to _xtos_set_intlevel() except + * that it will not lower the current interrupt level. Instead, + * it ensures that the current interrupt level is at least as high + * as specified. + * + * NOTE: This version allows the 'intlevel' parameter to be computed + * at run-time, and thus is longer. It is much more efficient, and + * highly recommented, to use the XTOS_SET_MIN_INTLEVEL(intlevel) macro instead + * (which requires a constant intlevel). + */ + + .text + .align 4 + .global _xtos_set_min_intlevel + .type _xtos_set_min_intlevel,@function +_xtos_set_min_intlevel: + abi_entry +#if XCHAL_HAVE_INTERRUPTS +# if XCHAL_HAVE_XEA2 + /* In XEA2, we can simply safely set PS.INTLEVEL directly: */ + rsr a3, PS // get old (current) PS.INTLEVEL + movi a4, ~0xF + extui a2, a2, 0, 4 // keep only INTLEVEL bits of parameter + extui a5, a3, 0, 4 // look at old PS.INTLEVEL + sub a5, a2, a5 // new.intlevel - old.intlevel + and a4, a4, a3 // mask out PS.INTLEVEL + or a4, a4, a2 // insert requested INTLEVEL + movltz a4, a3, a5 // keep same PS if already higher than requested + wsr a4, PS // update PS.INTLEVEL + extui a2, a3, 0, 4 // return only old PS.INTLEVEL field + rsync // wait for WSR to PS to complete +# else + /* In XEA1, we have to rely on INTENABLE register virtualization: */ + movi a4, Xthal_intlevel_andbelow_mask + extui a3, a2, 0, 4 // keep only INTLEVEL bits of parameter + addx4 a5, a3, a4 // index mask to use + l32i a3, a5, 0 // get mask of interrupts at requested intlevel and below + movi a5, -1 // all 1's + movi a4, _xtos_intstruct + xor a3, a3, a5 // mask of interrupts at intlevels above the requested one (to enable) + xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section + l32i a2, a4, XTOS_VPRI_ENABLED_OFS // return old xtos_vpri_enabled (current vpri) + l32i a5, a4, XTOS_ENABLED_OFS // a5 = xtos_enabled + and a3, a3, a2 // make sure we don't enable any new interrupts + s32i a3, a4, XTOS_VPRI_ENABLED_OFS // set new xtos_vpri_enabled (current vpri) + and a5, a5, a3 // a5 = xtos_enabled & xtos_vpri_enabled + wsr a5, INTENABLE + xtos_unlock a7 +# endif +#endif /*XCHAL_HAVE_INTERRUPTS*/ + abi_return + + .size _xtos_set_min_intlevel, . - _xtos_set_min_intlevel + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/ints-off.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/ints-off.S new file mode 100755 index 0000000..01cc32d --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/ints-off.S @@ -0,0 +1,74 @@ +// ints-off.S - Interrupt related assembler code - _xtos_ints_off + +// Copyright (c) 2004-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" + + +/*************************************************************************** + * _xtos_ints_on() and _xtos_ints_off() are used + * to enable and disable interrupts from C code; + * they can be called from the application or from a C interrupt handler. + */ + +// u32 _xtos_ints_off( u32 mask ); [T1050.0 docs this as returning old INTENABLE value] +// Disables a set of interrupts. See _xtos_ints_on(). +// +// MUST NOT be called when PS.INTLEVEL > XTOS_LOCKLEVEL +// (otherwise PS.INTLEVEL gets lowered; and operation may be inconsistent +// if this is called in the handler of an interrupt of level > LOCKLEVEL). +// + .text + .align 4 + .global _xtos_ints_off + .type _xtos_ints_off,@function +_xtos_ints_off: + abi_entry +#if XCHAL_HAVE_INTERRUPTS +# if XTOS_VIRTUAL_INTENABLE + movi a4, _xtos_intstruct + xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section + l32i a3, a4, XTOS_ENABLED_OFS // a3 = xtos_enabled + l32i a6, a4, XTOS_VPRI_ENABLED_OFS // a6 = xtos_vpri_enabled + or a5, a3, a2 // a5 = xtos_enabled | mask + xor a5, a5, a2 // a5 = xtos_enabled & ~mask + s32i a5, a4, XTOS_ENABLED_OFS // xtos_enabled &= ~mask + and a5, a5, a6 // a5 = xtos_enabled & xtos_vpri_enabled +# else + xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section + rsr a3, INTENABLE + //interlock + or a5, a3, a2 // a5 = INTENABLE | mask + xor a5, a5, a2 // a5 = INTENABLE & ~mask +# endif + wsr a5, INTENABLE + xtos_unlock a7 + mov a2, a3 // return previous (virtual or real) INTENABLE value +#else /*XCHAL_HAVE_INTERRUPTS*/ + movi a2, 0 // this config does not have interrupts, so return 0 +#endif /*XCHAL_HAVE_INTERRUPTS*/ + abi_return + + .size _xtos_ints_off, . - _xtos_ints_off + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/ints-on.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/ints-on.S new file mode 100755 index 0000000..1225e4b --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/ints-on.S @@ -0,0 +1,75 @@ +// ints-on.S - Interrupt related assembler code - _xtos_ints_on + +// Copyright (c) 2004-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" + + +/*************************************************************************** + * _xtos_ints_on() and _xtos_ints_off() are used + * to enable and disable interrupts from C code; + * they can be called from the application or from a C interrupt handler. + */ + + +// u32 _xtos_ints_on( u32 mask ); +// Enables a set of interrupts. +// With INTENABLE virtualizing, does not simply set INTENABLE directly, but rather +// computes it as a function of the current virtual priority. +// +// MUST NOT be called when PS.INTLEVEL > XTOS_LOCKLEVEL +// (otherwise PS.INTLEVEL gets lowered; and operation may be inconsistent +// if this is called in the handler of an interrupt of level > LOCKLEVEL). +// + .text + .align 4 + .global _xtos_ints_on + .type _xtos_ints_on,@function +_xtos_ints_on: + abi_entry +#if XCHAL_HAVE_INTERRUPTS +# if XTOS_VIRTUAL_INTENABLE + movi a4, _xtos_intstruct + xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section + l32i a3, a4, XTOS_ENABLED_OFS // a3 = xtos_enabled + l32i a6, a4, XTOS_VPRI_ENABLED_OFS // a6 = xtos_vpri_enabled + or a5, a3, a2 // xtos_enabled | mask + s32i a5, a4, XTOS_ENABLED_OFS // xtos_enabled |= mask + and a5, a5, a6 // a5 = xtos_enabled & xtos_vpri_enabled +# else + xtos_lock a7 // MUST USE highest address register of function to avoid window overflows in critical section + rsr a3, INTENABLE + //interlock + or a5, a3, a2 // INTENABLE | mask +# endif + wsr a5, INTENABLE + xtos_unlock a7 + mov a2, a3 // return previous (virtual or real) INTENABLE value +#else /*XCHAL_HAVE_INTERRUPTS*/ + movi a2, 0 // this config does not have interrupts, so return 0 +#endif /*XCHAL_HAVE_INTERRUPTS*/ + abi_return + + .size _xtos_ints_on, . - _xtos_ints_on + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/kernel-vector.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/kernel-vector.S new file mode 100755 index 0000000..0501821 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/kernel-vector.S @@ -0,0 +1,72 @@ +// kernel-vector.S - Kernel Vector for General Exceptions +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/kernel-vector.S#3 $ + +// Copyright (c) 1999-2002, 2004, 2006, 2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +/* + * General exceptions in kernel vector mode (PS.UM==0) go to this kernel + * vector. This kernel vector does very little. + * Under normal operation of the single-threaded runtime ("XTOS"), kernel + * vectored general exceptions do not occur, so nothing needs to be done. + * However when debugging, such as when writing exception and + * interrupt handlers, kernel vectored exceptions may occur. + * They are usually the sign of a bug, so here we take a breakpoint + * (if debug option enabled) or take drastic action (infinite loop) + * otherwise. + * + * XTOS does not allow exceptions in interrupt or exception handlers. + * If it did, a more elaborate kernel vector handler would be needed. + * See the Xtensa Microprocessor Programmer's Guide for an + * example of how to implement such a kernel vector handler. + */ + +#include +#include +#ifdef SIMULATOR +#include +#endif + +#if XCHAL_HAVE_EXCEPTIONS + + .begin literal_prefix .KernelExceptionVector + .section .KernelExceptionVector.text, "ax" + + .align 4 + .global _KernelExceptionVector +_KernelExceptionVector: +# if XCHAL_HAVE_DEBUG +1: break 1,0 // unexpected kernel exception +# elif defined(SIMULATOR) + wsr a2, EXCSAVE1 // save a2 where simulator expects it + movi a2, SYS_unhandled_kernel_exc +1: simcall // let simulator/debugger report unhandled exception +# else +1: +# endif + j 1b // infinite loop - unexpected kernel exception + + .size _KernelExceptionVector, . - _KernelExceptionVector + .text + .end literal_prefix + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/memep-enable.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/memep-enable.S new file mode 100755 index 0000000..6230336 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/memep-enable.S @@ -0,0 +1,63 @@ +// memep-enable.S -- Turn on local memory ECC/parity checking +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/memep-enable.S#3 $ + +// Copyright (c) 2006-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include + + + /* + * void _xtos_memep_enable(int flags); + * + * Turn on local memory ECC/parity checking, for both + * data access and instruction fetch. + * + * For now, flags are ignored. Caller is expected to pass zero. + * + * _xtos_memep_initrams() must have already been called, if necessary, + * to ensure all ECC/parity bits are valid in any local instruction + * or data RAM. The normal reset vector sequence already takes care + * of initializing any local cache ECC/parity bits. + */ + .text + .align 4 + .global _xtos_memep_enable +_xtos_memep_enable: + abi_entry + +#if XCHAL_HAVE_MEM_ECC_PARITY + + // Local Memory ECC/Parity option initialization + // + // NOTE: We turn on exceptions on correctable errors and correct + // them in the memory error handler. + movi a2, MESR_ERRENAB | MESR_DATEXC | MESR_INSEXC + wsr a2, MESR + isync + +#endif /* XCHAL_HAVE_MEM_ECC_PARITY */ + + movi a2, 0 // successfully turned on what we could + abi_return + + .size _xtos_memep_enable, . - _xtos_memep_enable + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/memep-initrams.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/memep-initrams.S new file mode 100755 index 0000000..fc1ba73 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/memep-initrams.S @@ -0,0 +1,91 @@ +// memep-initrams.S -- Initialize local memory ECC/parity +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/memep-initrams.S#3 $ + +// Copyright (c) 2006-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include + + + /* + * void _xtos_memep_initrams(void); + * + * Most reset vectors initialize caches, leaving only the local memories + * (instruction and data RAMs) with potentially some words that have + * not been written to and thus have uninitialized ECC/parity bits. + * Loading such a word after enabling ECC/parity checking would result + * in an exception (or memory error reported in MESR). To avoid this, + * an application must either carefully avoid loading from uninitialized + * words, or ensure it writes to every instruction and data RAM word. + * The latter is what this function does. It reads and writes every + * word of every local instruction and data RAM. It should normally + * be called with interrupts disabled. An interrupt might come in + * between a load and store, in which case any modification made by the + * interrupt handler to that local memory location is lost when this + * function resumes and does the store. If no interrupt handler makes + * any persistent modification to local memories, disabling them around + * a call to this function may be unnecessary. + * + * On the simulator (ISS), everything comes up zeroed, so no there is + * no need for this initialization. + */ + .text + .align 4 + .global _xtos_memep_initrams +_xtos_memep_initrams: + abi_entry + + // Local Memory ECC/Parity option initialization +#if XCHAL_HAVE_MEM_ECC_PARITY && (XCHAL_NUM_DATARAM || XCHAL_NUM_INSTRAM /*|| XCHAL_NUM_URAM || XCHAL_NUM_XLMI*/) && !defined(SIMULATOR) + .section .rodata, "a" + .align 4 +.L_locmemep_start: +# if XCHAL_NUM_DATARAM >= 1 && XCHAL_DATARAM0_ECC_PARITY + .long XCHAL_DATARAM0_VADDR, XCHAL_DATARAM0_VADDR+XCHAL_DATARAM0_SIZE +# endif +# if XCHAL_NUM_DATARAM >= 2 && XCHAL_DATARAM1_ECC_PARITY + .long XCHAL_DATARAM1_VADDR, XCHAL_DATARAM1_VADDR+XCHAL_DATARAM1_SIZE +# endif +# if XCHAL_NUM_INSTRAM >= 1 && XCHAL_INSTRAM0_ECC_PARITY + .long XCHAL_INSTRAM0_VADDR, XCHAL_INSTRAM0_VADDR+XCHAL_INSTRAM0_SIZE +# endif +# if XCHAL_NUM_INSTRAM >= 2 && XCHAL_INSTRAM1_ECC_PARITY + .long XCHAL_INSTRAM1_VADDR, XCHAL_INSTRAM1_VADDR+XCHAL_INSTRAM1_SIZE +# endif +.L_locmemep_end: + .text + movi a5, .L_locmemep_start // start of table of local memory ranges + movi a6, .L_locmemep_end // end of table ... +2: l32i a3, a5, 0 // start of local memory + l32i a4, a5, 4 // end of local memory + addi a5, a5, 8 // (next entry in table) +1: l32i a2, a3, 0 // load and store every word of local memory... + s32i a2, a3, 0 // ... to initialize all parity and/or ECC bits + addi a3, a3, 4 + bltu a3, a4, 1b // loop until whole memory initialized + bltu a5, a6, 2b // loop until all memories initialized + // ECC/parity bits are now initialized, checking can be turned on. +#endif /* ECC/parity on instruction or data RAM(s) */ + + abi_return + + .size _xtos_memep_initrams, . - _xtos_memep_initrams + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/memerror-vector.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/memerror-vector.S new file mode 100755 index 0000000..04f7c0d --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/memerror-vector.S @@ -0,0 +1,482 @@ +/* memerror-vector.S -- Memory Error Exception Vector and Handler */ + +/* $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/memerror-vector.S#3 $ */ + +/* + * Copyright (c) 2006-2010 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +//#include +#include +#include + +#if XCHAL_HAVE_MEM_ECC_PARITY +# if defined(__SPLIT__vector) + + // Place this code in the memory error exception vector: + .begin literal_prefix .MemoryExceptionVector + .section .MemoryExceptionVector.text, "ax" + + .global _MemErrorVector + .align 4 +_MemErrorVector: +# if 0 /* XCHAL_HAVE_DEBUG */ + // Memory errors raise PS.INTLEVEL above DEBUGLEVEL, so + // break instructions have no effect within them (debug + // exceptions are masked). So leave commented out for now. + break 1, 5 // unhandled memory error exception +# endif + wsr a0, MESAVE + movi a0, _MemErrorHandler + jx a0 + + .size _MemErrorVector, . - _MemErrorVector + .text + .end literal_prefix + + +# elif defined(__SPLIT__handler) + +/* + * Some rules and assumptions: + * + * Anything that can interrupt this handler (e.g. NMI): + * - must not lock or unlock cache lines + */ + + +#define ICACHE_WAYWIDTH (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) /* LICT's "iis" */ +#define DCACHE_WAYWIDTH (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) /* LDCT's "dis" */ +/* NOTE: Memory ECC/parity is not supported on XLMI or on local ROMs: */ +#define HAVE_LOCAL_RAM (XCHAL_NUM_DATARAM || XCHAL_NUM_INSTRAM /*|| XCHAL_NUM_URAM || XCHAL_NUM_XLMI*/) + + + //.lcomm _MemErrorSave, 8 + .comm _MemErrorSave, 8, 4 + + .text + .align 4 + .global _MemErrorHandler +_MemErrorHandler: + rsr a0, MESR + bbsi.l a0, MESR_DME_SHIFT, .L_fatal_dme +# if XCHAL_ICACHE_SIZE > 0 || XCHAL_DCACHE_SIZE > 0 + bbsi.l a0, MESR_MEMTYPE_SHIFT+1, .L_cache // branch if error on a cache +# endif + // Error in a local memory. +# if HAVE_LOCAL_RAM + bbsi.l a0, MESR_ERRTYPE_SHIFT, .L_uncorrectable_local + // Correctable error in a local memory (IRAM or DRAM). + // (MEVADDR has all 32 bits, so XSR preserves a register:) + xsr a2, MEVADDR + // Note: MEVADDR is always 4-byte aligned, + // so we can just do L32I/S32I to correct the error. + // However, that's not atomic, and NMI can store in between; + // that's usually a problem for D rather than I, avoid the + // issue using S32C1I if configured (else NMI must not write DataRAM!?!): +# if (XCHAL_HAVE_S32C1I && (XCHAL_NUM_DATARAM /*|| XCHAL_NUM_URAM || XCHAL_NUM_XLMI*/)) + bbci.l a0, MESR_MEMTYPE_SHIFT, .L_instram // branch if error on InstRAM + // Unfortunately we need 3 registers to do S32C1I (data,addr,SCOMPARE1) so + // we need to save to _MemErrorSave: + movi a0, _MemErrorSave + s32i a4, a0, 0 // save a4 + l32i a4, a2, 0 // load data (re-correct) + rsr a0, SCOMPARE1 // save SCOMPARE1 + wsr a4, SCOMPARE1 + s32c1i a4, a2, 0 // store if still contains same value (else other store corrected error) + movi a4, _MemErrorSave + wsr a0, SCOMPARE1 // restore SCOMPARE1 + l32i a4, a4, 0 // restore a4 + j 2f +.L_instram: +# endif + l32i a0, a2, 0 // load data (re-correct) + s32i a0, a2, 0 // store data to correct ECC bits +2: xsr a2, MEVADDR +# endif /* HAVE_LOCAL_RAM */ +.L_done: + rsr a0, MESAVE + rfme + + + // Weak reference: if unresolved, links okay but with zero value: + .weak _xtos_merr_hook_fatal_dme +.L_fatal_dme: + // Fatal (unrecoverable) error, double memory exception + movi a0, _xtos_merr_hook_fatal_dme +1: beqz a0, 1b // fatal double memory error, no hook, so infinite loop + jx a0 // jump to user hook, if present + + +# if HAVE_LOCAL_RAM + // Weak reference: if unresolved, links okay but with zero value: + .weak _xtos_merr_hook_uncorrectable_local +.L_uncorrectable_local: + // Fatal (unrecoverable) error in IRAM or DRAM: parity or uncorrectable ECC error + movi a0, _xtos_merr_hook_uncorrectable_local +1: beqz a0, 1b // fatal memory error, no hook provided, so infinite loop + jx a0 // jump to user hook, if present +# endif + + +# if XCHAL_ICACHE_SIZE > 0 || XCHAL_DCACHE_SIZE > 0 +.L_cache: + // Error in one of the caches. +# endif + +# if XCHAL_ICACHE_SIZE > 0 +# if XCHAL_DCACHE_SIZE > 0 + bbsi.l a0, MESR_MEMTYPE_SHIFT, .L_dcache // branch if data cache error +# endif + // Error in the instruction cache. + bbsi.l a0, MESR_ERRTYPE_SHIFT, .L_icache_noncorr // branch if uncorrectable + // Correctable error in the instruction cache. + xsr a2, MEVADDR + // TODO FIXME: remove these 5 lines if waynum is in MEVADDR!? by using III if tag and IHI otherwise!?!?!?: +# if XCHAL_ICACHE_WAYS > 1 + extui a0, a0, MESR_WAYNUM_SHIFT, 2 + slli a0, a0, ICACHE_WAYWIDTH + slli a2, a2, 32 - ICACHE_WAYWIDTH + srli a2, a2, 32 - ICACHE_WAYWIDTH + or a2, a2, a0 +# endif + iii a2, 0 // invalidate line (whole set!) if not locked +# if XCHAL_ICACHE_LINE_LOCKABLE + // III has no effect if the line is locked; for that case, need to do more: + lict a0, a2 + bbci.l a0, XCHAL_ICACHE_TAG_L_SHIFT, .L_icache_done // branch if unlocked + // Correctable error in a locked instruction cache line. + // Fix both tag and one word, quicker than figuring out whether error is in tag or data: + sict a0, a2 // fix tag + licw a0, a2 + sicw a0, a2 // fix data word +# endif +.L_icache_done: + xsr a2, MEVADDR + j .L_done + +.L_icache_noncorr: + // Non-correctable error in the instruction cache. + bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_icache_tag_noncorr // branch if tag error + // Non-correctable error in the instruction cache data. + // Just invalidate the line if we can. +# if XCHAL_ICACHE_LINE_LOCKABLE + // If locked, need a different fix sequence. + xsr a2, MEVADDR + +# if XCHAL_ICACHE_WAYS > 1 + // This sequence is shorter, but does not retain original MEVADDR so + // prevents subsequent use of instructions requiring a virtual address + // (such as LICW, IPFL, etc): +// extui a0, a0, MESR_WAYNUM_SHIFT, 2 +// slli a0, a0, ICACHE_WAYWIDTH +// slli a2, a2, 32 - ICACHE_WAYWIDTH +// srli a2, a2, 32 - ICACHE_WAYWIDTH +// or a2, a2, a0 + + extui a0, a0, MESR_WAYNUM_SHIFT, 2 // id of way with mem error + slli a0, a0, ICACHE_WAYWIDTH + xor a0, a2, a0 // xor corresponding bits of addr + extui a0, a0, ICACHE_WAYWIDTH, 2 // take 2 xor'ed way bits + or a2, a2, a0 // save them at bottom of addr + slli a0, a0, ICACHE_WAYWIDTH + xor a2, a2, a0 // and change 2 way bits of addr +# endif + lict a0, a2 + bbsi.l a0, XCHAL_ICACHE_TAG_L_SHIFT, .L_icache_locked_uncor // branch if locked + // Cache line is not locked, just invalidate: +# if XCHAL_ICACHE_WAYS > 1 + iii a2, 0 +# else + ihi a2, 0 +# endif + j .L_icache_done + + // NOTE: we don't use the LICW/SICW sequence below unless the line is locked, + // otherwise the i-cache line might get replaced between LICW and SICW + // (if we're not extremely careful), which would be disastrous. + // Also, for locked lines, LICW/SICW is much safer than IHU/IHI/IPFL + // because it doesn't leave a window where the line is unlocked; + // however, if the error is non-correctable, we have no choice. + +.L_icache_locked_uncor: + // If locked and uncorrectable however, the only recourse is relocking. + // So we need to recover the virtual address so we can do IPFL. + // Note: can't use MEPC instead of MEVADDR, because (a) it might not + // point to the correct cache line, and (b) it might be completely wrong + // in the case where the mem error happened e.g. during an LICW or IPFL. +# if XCHAL_ICACHE_WAYS > 1 + // Recover virtual address in a2: + extui a0, a2, 0, 2 // get saved xor'ed bits at bottom + slli a0, a0, ICACHE_WAYWIDTH // line them up + xor a2, a2, a0 // restore original MEVADDR +# endif + ihu a2, 0 // unlock line + ihi a2, 0 // invalidate line + ipfl a2, 0 // refetch-and-lock the line + j .L_icache_done +# else /* LOCKABLE */ + rsr a0, MEVADDR + ihi a0, 0 // invalidate that cache line + j .L_done +# endif /* LOCKABLE */ + +.L_icache_tag_noncorr: + // Non-correctable error in the instruction cache tag. + // Just invalidate the tag or the entire set. +# if XCHAL_ICACHE_LINE_LOCKABLE + // Note: can't use either IIU or III, as these don't write the entire tag, + // so they'll get the exception again. So, have to use SICT. +# if XCHAL_ICACHE_WAYS > 1 + // TODO FIXME: avoid this 8-line alternative if waynum is in MEVADDR!?: + xsr a2, MEVADDR + extui a0, a0, MESR_WAYNUM_SHIFT, 2 + slli a0, a0, ICACHE_WAYWIDTH + slli a2, a2, 32 - ICACHE_WAYWIDTH + srli a2, a2, 32 - ICACHE_WAYWIDTH + or a2, a2, a0 + iiu a2, 0 // unlock line ==> also invalidates! (I-side only) + xsr a2, MEVADDR +# else + rsr a0, MEVADDR + iiu a0, 0 // unlock line ==> also invalidates! (I-side only) +# endif + // If line was locked, can't recover lock state, need external info to recover. + // User can provide an assembler hook routine _xtos_merr_hook_icache_relock + // to relock the icache at the index in a2: + // - any number of lines might still be locked at that index, + // including all of them + // - no stack is provided, a0 must be used as starting point to + // load a save area and saved registers as necessary + // - unless routine just does ret (i.e. does not modify any + // register, only possible if it does nothing), it needs to + // return by restoring all registers it modified, ending with: + // rsr a0, MESAVE + // rfme + // CAVEAT EMPTOR: this hook mechanism is subject to change. + .weak _xtos_merr_hook_icache_relock // if unresolved, links with zero value + movi a0, _xtos_merr_hook_icache_relock +1: beqz a0, 1b // if no hook to recover lock state on icache tag mem error, loop forever + callx0 a0 // invoke user hook to relock i-cache (index in MEVADDR) +# else + rsr a0, MEVADDR + iii a0, 0 // invalidate entire set +# endif + j .L_done +# endif /* have ICACHE */ + + +# if XCHAL_DCACHE_SIZE > 0 +# if XCHAL_ICACHE_SIZE > 0 +.L_dcache: +# endif + // Error in the data cache. +# if XCHAL_DCACHE_IS_WRITEBACK || XCHAL_DCACHE_LINE_LOCKABLE + bbsi.l a0, MESR_ERRTYPE_SHIFT, .L_dcache_noncorr // branch if uncorrectable + // Uncorrectable error on a writeback dcache might be unrecoverable: +# endif + bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_dcache_tag // branch if tag error + // Error in the data cache data (correctable, or non-correctable in writethru+unlockable cache). + // MEVADDR always a real vaddr here; might point to cache-isolate mode area though. +# if XCHAL_DCACHE_LINE_LOCKABLE + // Correctable error on lockable dcache data. + // If locked, need to refetch the line (or load/store its contents, which is less safe): + xsr a2, MEVADDR +# if XCHAL_DCACHE_WAYS > 1 + // Need some extra computation to get the correct dcache way's tag: + movi a0, _MemErrorSave + s32i a4, a0, 0 // save a4 + s32i a5, a0, 4 // save a5 + rsr a4, MESR + extui a4, a4, MESR_WAYNUM_SHIFT, 2 + slli a4, a4, DCACHE_WAYWIDTH + slli a5, a2, 32 - DCACHE_WAYWIDTH + srli a5, a5, 32 - DCACHE_WAYWIDTH + add a4, a4, a5 + mov a5, a0 + ldct a0, a4 + l32i a4, a5, 0 // restore a4 + l32i a5, a5, 4 // restore a5 +# else + ldct a0, a2 +# endif + // FIXME: if castout, a2 is a physical address! doesn't work with any address translation. +# if 0 /* translation */ + movi a4, _xtos_vmap_vaddr // FIXME: do we need two variables for full MMU? +1: beqz a4, 1b // if no vaddr to use, loop forever (FIXME: caxlt: could assume V==P) + rdtlb1 a5, a4 // save current contents + ... clear lower bits of a4 ... + xx = some function of a2 + wdtlb xx, a4 + a2 = virtual address, i.e. some function of a2 and a4 ... + ... do the sequence below ... + ... + wdtlb a5, a4 // restore TLB entry +# endif + // NOTE: the following sequence leaves the line temporarily unlocked, if locked. + // We assume NMI handlers don't lock lines or rely on their being locked. + // We could have used "l32i a0,a2,0; s32i a0,a2,0" but that's not atomic on the data. + dhu a2, 0 // unlock the cache line, if locked + dhwbi a2, 0 // writeback and invalidate cache line + bbci.l a0, XCHAL_DCACHE_TAG_L_SHIFT, 1f + dpfl a2, 0 // re-prefetch-and-lock the cache line +1: xsr a2, MEVADDR +# else /* LOCKABLE */ + // Error in unlockable data cache data (correctable, or non-correctable in writethru cache). + rsr a0, MEVADDR + // USELESS NOTE: if writethru dcache and NMI handlers don't store to this, we could use DHI instead: + // FIXME: if castout, a0 is a physical address! doesn't work with any address translation. + dhwbi a0, 0 // writeback (if correctable) and invalidate that cache line +# endif /* LOCKABLE */ + j .L_done + +.L_dcache_tag: + // Error in data cache tag (correctable, or non-correctable in writethru+unlockable cache). + // MEVADDR only contains cache index here (not waynum), don't expect a vaddr (the ISA + // says upper bits are undefined; actual hw does put a vaddr, but in future might not). + // Whether or not correctable, just invalidate the particular way's line: + xsr a2, MEVADDR + // NOTE: could remove these 5 lines if hw were designed with waynum in MEVADDR (but is not): +# if XCHAL_DCACHE_WAYS > 1 + extui a0, a0, MESR_WAYNUM_SHIFT, 2 + slli a0, a0, DCACHE_WAYWIDTH + slli a2, a2, 32 - DCACHE_WAYWIDTH + srli a2, a2, 32 - DCACHE_WAYWIDTH + or a2, a2, a0 +# endif +# if XCHAL_DCACHE_LINE_LOCKABLE + ldct a0, a2 // invalidate and unlock that cache tag + bbci.l a0, XCHAL_DCACHE_TAG_L_SHIFT, 1f // branch if not locked + sdct a0, a2 // if locked, this safely writes whole tag +# endif +1: diwbi a2, 0 // writeback (if correctable) and invalidate the line + xsr a2, MEVADDR + j .L_done + + + +# if XCHAL_DCACHE_IS_WRITEBACK || XCHAL_DCACHE_LINE_LOCKABLE +.L_dcache_noncorr: + // Uncorrectable error on a (writeback and/or lockable) data cache. +# if XCHAL_DCACHE_IS_WRITEBACK + // On tag errors we don't know whether the line is dirty, so this is unrecoverable: + bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_uncorrectable_dtag // branch if tag error + // Castouts are by definition dirty, uncorrectable errors on these are unrecoverable: + bbsi.l a0, MESR_ACCTYPE_SHIFT, .L_uncorrectable_dirty // branch if castout + // Note: could still be an error on dirty dcache data, also unrecoverable. +# else + bbsi.l a0, MESR_MEMTYPE_SHIFT+2, .L_dcache_tag_noncorr // branch if tag error +# endif + // Uncorrectable error in dcache data. + // May be dirty or locked, so get tag to find out. + xsr a2, MEVADDR +# if XCHAL_DCACHE_WAYS > 1 + extui a0, a0, MESR_WAYNUM_SHIFT, 2 // id of way with mem error + slli a0, a0, DCACHE_WAYWIDTH + xor a0, a2, a0 // xor corresponding bits of addr + extui a0, a0, DCACHE_WAYWIDTH, 2 // take 2 xor'ed way bits + or a2, a2, a0 // save them at bottom of addr + slli a0, a0, DCACHE_WAYWIDTH + xor a2, a2, a0 // and change 2 way bits of addr +# endif + ldct a0, a2 // get dcache tag +# if XCHAL_DCACHE_IS_WRITEBACK + bbsi.l a0, XCHAL_DCACHE_TAG_D_SHIFT, .L_uncorrectable_dirty_2 // branch if dirty +# endif + // Data cache line is clean. +# if XCHAL_DCACHE_LINE_LOCKABLE + bbsi.l a0, XCHAL_DCACHE_TAG_L_SHIFT, .L_dcache_nc_locked +# endif + // Data cache line is clean and unlocked. Just invalidate it. + // FIXME: any stores to this line by an NMI handler will be lost. + // On the other hand, if we use DHWBI, any stores by an NMI handler + // that don't happen to fix the error result in an unrecoverable castout. + // +# if XCHAL_ICACHE_WAYS > 1 + // Recover virtual address in a2: + extui a0, a2, 0, 2 // get saved xor'ed bits at bottom + slli a0, a0, ICACHE_WAYWIDTH // line them up + xor a2, a2, a0 // restore original MEVADDR +# endif + dhi a2, 0 // invalidate that data cache line + xsr a2, MEVADDR + j .L_done + +# if XCHAL_DCACHE_LINE_LOCKABLE +.L_dcache_nc_locked: +# if XCHAL_ICACHE_WAYS > 1 + // Recover virtual address in a2: + extui a0, a2, 0, 2 // get saved xor'ed bits at bottom + slli a0, a0, ICACHE_WAYWIDTH // line them up + xor a2, a2, a0 // restore original MEVADDR +# endif + // Unlock, invalidate, and relock it: + dhu a2, 0 // unlock that data cache line + dhi a2, 0 // invalidate that data cache line + dpfl a2, 0 // prefetch-and-lock the line again + xsr a2, MEVADDR + j .L_done +# endif + +# if XCHAL_DCACHE_IS_WRITEBACK + // Weak reference: if unresolved, links okay but with zero value: + .weak _xtos_merr_hook_uncor_dtag +.L_uncorrectable_dtag: + // Fatal (unrecoverable) error in dcache tag (maybe dirty): parity or uncorrectable ECC error + movi a0, _xtos_merr_hook_uncor_dtag +1: beqz a0, 1b // fatal non-corr dcache tag, no hook, so infinite loop + jx a0 // jump to user hook, if present + + // Weak reference: if unresolved, links okay but with zero value: + .weak _xtos_merr_hook_uncor_dirty +.L_uncorrectable_dirty_2: + xsr a2, MEVADDR +.L_uncorrectable_dirty: + // Fatal (unrecoverable) error, parity or non-correctable ECC error on dirty cache data + movi a0, _xtos_merr_hook_uncor_dirty +1: beqz a0, 1b // fatal non-corr dirty cache line, no hook, so infinite loop + jx a0 // jump to user hook, if present +# else +.L_dcache_tag_noncorr: + // Uncorrectable error on a lockable writethru data cache tag. + // We have to invalidate the line, but that way we lose the lock bit. + // Provide a hook to relock if necessary (using knowledge outside this module + // about what needs to be locked). See _xtos_merr_hook_icache_relock for details. + // CAVEAT EMPTOR: this hook mechanism is subject to change. + .weak _xtos_merr_hook_dcache_relock // if unresolved, links with zero value + movi a0, _xtos_merr_hook_dcache_relock +1: beqz a0, 1b // if no hook to recover lock state on dcache tag mem error, loop forever + callx0 a0 // invoke user hook to relock d-cache (index in MEVADDR) + j .L_done +# endif + +# endif /* DCACHE IS WRITEBACK || LINE_LOCKABLE */ + +# endif /* have DCACHE */ + + .size _MemErrorHandler, . - _MemErrorHandler + + + +# endif /* splitting */ +#endif /* XCHAL_HAVE_MEM_ECC_PARITY */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/nmi-vector.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/nmi-vector.S new file mode 100755 index 0000000..69108bc --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/nmi-vector.S @@ -0,0 +1,61 @@ +// nmi-vector.S -- Standalone NMI Interrupt Vector/Handler +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/nmi-vector.S#3 $ + +// Copyright (c) 2003, 2006, 2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// The NMI exception vector handles non-maskable interrupts. + +#include +#include +#include + +#if XCHAL_HAVE_NMI + + .begin literal_prefix .NMIExceptionVector + .section .NMIExceptionVector.text, "ax" + + .align 4 + .global _NMIExceptionVector +_NMIExceptionVector: + +// Insert any custom NMI handling code here. +// For example: +// wsr a0, EXCSAVE+XCHAL_NMILEVEL +// movi a0, ...address of some save area specific to this code... +// s32i a1, a0, 0 // save whatever registers are needed +// : +// do something useful ... +// : +// l32i a1, a0, 0 // restore whatever registers were saved +// rsr a0, EXCSAVE+XCHAL_NMILEVEL +// +// This default NMI handler does not do anything. It just returns +// immediately upon any occurrence of a non-maskable interrupt. + + rfi XCHAL_NMILEVEL + + .size _NMIExceptionVector, . - _NMIExceptionVector + .text + .end literal_prefix + +#endif /* XCHAL_HAVE_NMI */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/null-alloca.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/null-alloca.S new file mode 100755 index 0000000..2524f1f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/null-alloca.S @@ -0,0 +1,38 @@ +// null-alloca.S - Stub for Unused Alloca (MOVSP) Handler +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/null-alloca.S#3 $ + +// Copyright (c) 2006-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + + // Redirect alloca (MOVSP) exceptions as not handled, when + // that functionality is not needed. Done this way, a user can + // just specify this small handler to override the default one. + + .text + .weak _xtos_unhandled_exception + .global _xtos_alloca_handler +_xtos_alloca_handler: + movi a3, _xtos_unhandled_exception +1: beqz a3, 1b + jx a3 + .size _xtos_alloca_handler, . - _xtos_alloca_handler + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/null-syscall.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/null-syscall.S new file mode 100755 index 0000000..108a2ab --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/null-syscall.S @@ -0,0 +1,38 @@ +// null-syscall.S - Stub for Unused SYSCALL Handler +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/null-syscall.S#3 $ + +// Copyright (c) 2006-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + + // Redirect SYSCALL exceptions as not handled, when + // that functionality is not needed. Done this way, a user can + // just specify this small handler to override the default one. + + .text + .weak _xtos_unhandled_exception + .global _xtos_syscall_handler +_xtos_syscall_handler: + movi a3, _xtos_unhandled_exception +1: beqz a3, 1b + jx a3 + .size _xtos_syscall_handler, . - _xtos_syscall_handler + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/null-vectors.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/null-vectors.S new file mode 100755 index 0000000..2869977 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/null-vectors.S @@ -0,0 +1,184 @@ +// null-vectors.S - Stubs for Unused Vectors and Handlers +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/null-vectors.S#3 $ + +// Copyright (c) 2006-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + +// NOTE: The simulator version of this file is currently not used, +// i.e. the SIMULATOR macro is never defined when assembling this file. +// The relevant simulator code is left here for illustrative purposes only. + + +#include +#include "xtos-internal.h" +#ifdef SIMULATOR +#include +#endif + + // These are just tiny non-functional vectors and handlers for when + // their functionality is not being used. They just try to signal + // the debugger that an unhandled exception or interrupt occurred, + // and otherwise just spin in a loop. + // + // For interrupts levels above DEBUGLEVEL, lowering PS.INTLEVEL + // for break to work is tricky, and not always possible in a + // generic fashion without interfering with normal program execution. + // So for now we don't do it. + + +#if defined(__SPLIT__user) + +# if XCHAL_HAVE_EXCEPTIONS + .begin literal_prefix .UserExceptionVector + .section .UserExceptionVector.text, "ax" + .align 4 + .global _UserExceptionVector +_UserExceptionVector: +# if XCHAL_HAVE_DEBUG + break 1, 1 // unexpected user-vectored general exception +# endif +1: j 1b // infinite loop - unexpected user-vectored exception + .size _UserExceptionVector, . - _UserExceptionVector + .end literal_prefix +# endif + +#elif defined(__SPLIT__level1int) + + .text + .global _xtos_l1int_handler +_xtos_l1int_handler: + movi a3, _xtos_unhandled_exception + jx a3 + .size _xtos_l1int_handler, . - _xtos_l1int_handler + +#elif defined(__SPLIT__level2) + +# if (XCHAL_NUM_INTLEVELS >= 2) && (XCHAL_DEBUGLEVEL != 2) + .begin literal_prefix .Level2InterruptVector + .section .Level2InterruptVector.text, "ax" + .align 4 + .global _Level2Vector +_Level2Vector: +# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 2) + break 1, 2 // unexpected high-priority interrupt +# elif defined(SIMULATOR) + wsr a2, EXCSAVE_2 + movi a2, SYS_unhandled_highpri_interrupt + simcall // let simulator/debugger report unhandled level-2 interrupt +# endif +1: j 1b // infinite loop - unexpected level-2 interrupt + .size _Level2Vector, . - _Level2Vector + .text + .end literal_prefix +# endif /* level 2 */ + + +#elif defined(__SPLIT__level3) + +# if (XCHAL_NUM_INTLEVELS >= 3) && (XCHAL_DEBUGLEVEL != 3) + .begin literal_prefix .Level3InterruptVector + .section .Level3InterruptVector.text, "ax" + .align 4 + .global _Level3Vector +_Level3Vector: +# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 3) + break 1, 2 // unexpected high-priority interrupt +# elif defined(SIMULATOR) + wsr a2, EXCSAVE_3 + movi a2, SYS_unhandled_highpri_interrupt + simcall // let simulator/debugger report unhandled level-3 interrupt +# endif +1: j 1b // infinite loop - unexpected level-3 interrupt + .size _Level3Vector, . - _Level3Vector + .text + .end literal_prefix +# endif /* level 3 */ + + +#elif defined(__SPLIT__level4) + +# if (XCHAL_NUM_INTLEVELS >= 4) && (XCHAL_DEBUGLEVEL != 4) + .begin literal_prefix .Level4InterruptVector + .section .Level4InterruptVector.text, "ax" + .align 4 + .global _Level4Vector +_Level4Vector: +# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 4) + break 1, 2 // unexpected high-priority interrupt +# elif defined(SIMULATOR) + wsr a2, EXCSAVE_4 + movi a2, SYS_unhandled_highpri_interrupt + simcall // let simulator/debugger report unhandled level-4 interrupt +# endif +1: j 1b // infinite loop - unexpected level-4 interrupt + .size _Level4Vector, . - _Level4Vector + .text + .end literal_prefix +# endif /* level 4 */ + + +#elif defined(__SPLIT__level5) + +# if (XCHAL_NUM_INTLEVELS >= 5) && (XCHAL_DEBUGLEVEL != 5) + .begin literal_prefix .Level5InterruptVector + .section .Level5InterruptVector.text, "ax" + .align 4 + .global _Level5Vector +_Level5Vector: +# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 5) + break 1, 2 // unexpected high-priority interrupt +# elif defined(SIMULATOR) + wsr a2, EXCSAVE_5 + movi a2, SYS_unhandled_highpri_interrupt + simcall // let simulator/debugger report unhandled level-5 interrupt +# endif +1: j 1b // infinite loop - unexpected level-5 interrupt + .size _Level5Vector, . - _Level5Vector + .text + .end literal_prefix +# endif /* level 5 */ + + +#elif defined(__SPLIT__level6) + +# if (XCHAL_NUM_INTLEVELS >= 6) && (XCHAL_DEBUGLEVEL != 6) + .begin literal_prefix .Level6InterruptVector + .section .Level6InterruptVector.text, "ax" + .align 4 + .global _Level6Vector +_Level6Vector: +# if XCHAL_HAVE_DEBUG && (XCHAL_DEBUGLEVEL > 6) + break 1, 2 // unexpected high-priority interrupt +# elif defined(SIMULATOR) + wsr a2, EXCSAVE_6 + movi a2, SYS_unhandled_highpri_interrupt + simcall // let simulator/debugger report unhandled level-6 interrupt +# endif +1: j 1b // infinite loop - unexpected level-6 interrupt + .size _Level6Vector, . - _Level6Vector + .text + .end literal_prefix +# endif /* level 6 */ + + +#endif /* split */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/reloc-vectors.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/reloc-vectors.S new file mode 100755 index 0000000..3a55628 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/reloc-vectors.S @@ -0,0 +1,119 @@ +// reloc-vector.S - Relocatable Vectors section +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/reloc-vectors.S#3 $ + +// Copyright (c) 2007-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +/* + * This file is only used if the relocatable vectors option is enabled. + */ + +#include +#include + +#if XCHAL_HAVE_VECBASE + + .section .RelocatableVectors.text, "ax" + + .global _RelocVectors +_RelocVectors: + +//if XCHAL_RESET_VECBASE_OVERLAP ... +# if XSHAL_VECTORS_PACKED \ + && (XCHAL_RESET_VECTOR0_VADDR == XCHAL_VECBASE_RESET_VADDR \ + || XCHAL_RESET_VECTOR1_VADDR == XCHAL_VECBASE_RESET_VADDR) +# define JUMP_TO_RESET 1 + j .Ljump_to_reset +# endif + +# if XCHAL_HAVE_WINDOWED +# define NO_SECTION_DIRECTIVES 1 +# define WINDOW_BASE_VECOFS 0 +# include "window-vectors.S" +# endif + +#if XCHAL_HAVE_DEBUG && XCHAL_HAVE_EXCEPTIONS +# if XCHAL_DEBUGLEVEL == 2 +# define _Level2Vector _DebugExceptionVector +# elif XCHAL_DEBUGLEVEL == 3 +# define _Level3Vector _DebugExceptionVector +# elif XCHAL_DEBUGLEVEL == 4 +# define _Level4Vector _DebugExceptionVector +# elif XCHAL_DEBUGLEVEL == 5 +# define _Level5Vector _DebugExceptionVector +# elif XCHAL_DEBUGLEVEL == 6 +# define _Level6Vector _DebugExceptionVector +# endif +#endif + +# if XCHAL_HAVE_INTERRUPTS +# if XCHAL_NUM_INTLEVELS >= 2 + .org XCHAL_INTLEVEL2_VECOFS + j _Level2Vector +# endif +# if XCHAL_NUM_INTLEVELS >= 3 + .org XCHAL_INTLEVEL3_VECOFS + j _Level3Vector +# endif +# if XCHAL_NUM_INTLEVELS >= 4 + .org XCHAL_INTLEVEL4_VECOFS + j _Level4Vector +# endif +# if XCHAL_NUM_INTLEVELS >= 5 + .org XCHAL_INTLEVEL5_VECOFS + j _Level5Vector +# endif +# if XCHAL_NUM_INTLEVELS >= 6 + .org XCHAL_INTLEVEL6_VECOFS + j _Level6Vector +# endif +# if XCHAL_HAVE_NMI + .org XCHAL_NMI_VECOFS + j _NMIExceptionVector +# endif +# endif +# if XCHAL_HAVE_EXCEPTIONS + .org XCHAL_KERNEL_VECOFS + j _KernelExceptionVector + .org XCHAL_USER_VECOFS + j _UserExceptionVector + .org XCHAL_DOUBLEEXC_VECOFS + j _DoubleExceptionVector +# endif + +// Put literals here. + +// Put actual handlers here. + +# if JUMP_TO_RESET + .align 4 + .literal rvec, _ResetVector +.Ljump_to_reset: + l32r a2, rvec + jx a2 +# endif + + .size _RelocVectors, . - _RelocVectors + + .text + +#endif /* XCHAL_HAVE_VECBASE */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/reset-unneeded.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/reset-unneeded.S new file mode 100755 index 0000000..c4f646e --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/reset-unneeded.S @@ -0,0 +1,156 @@ +// reset-unneeded.S -- Optional Extraneous Reset Code +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/reset-unneeded.S#2 $ + +// Copyright (c) 2002-2006 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +// This file is meant to be included by another, e.g. crt1-***.S . +// The code it contains is generally not needed, so is kept in a +// separate file for clarity of other code. + +#if XTOS_RESET_UNNEEDED + /* + * Reset registers that don't really need to be reset, + * but may provide more predictability when buggy code + * relies on uninitialized state. It might also clear + * "X"s a bit earlier in hardware simulations. + * + * NOTE: This code is by no means exhaustive. + * More processor registers/states could be reset if desired. + * This is just an example. + * + * ASSUMPTION: a0 is still zero at this point. + */ + + // Interrupt initialization. + // Because INTENABLE is cleared by the reset vector, clearing the + // interrupt-pending register should not be needed. This assumes + // that any application setting up an interrupt will register and + // clear it before enabling it, which is the recommended sequence. + // +#if XCHAL_HAVE_INTERRUPTS && (XCHAL_INTCLEARABLE_MASK != 0) && !XCHAL_HAVE_FULL_RESET + movi a2, XCHAL_INTCLEARABLE_MASK + wsr a2, INTCLEAR // clear software and edge-trig ints +#endif + + // Timer initialization (not strictly required, but sometimes helpful) + .macro reset_timer num + wsr a0, CCOMPARE_0 + \num + .endm + iterate 0, XCHAL_NUM_TIMERS-1, reset_timer + +# if XCHAL_HAVE_WINDOWED + // Windowed address register init -- initialize entire physical AR file + movi a0, XCHAL_NUM_AREGS/8 // number of 8-register chunks +arloop: + addi a8, a0, -1 // countdown into next chunk's a0 + movi a0, 0 + movi a1, 0 + movi a2, 0 + movi a3, 0 + movi a4, 0 + movi a5, 0 + movi a6, 0 + movi a7, 0 + rotw 2 // rotate to next chunk + bnez a0, arloop + // NOTE: WINDOWBASE is back to zero at this point. +# else /* XCHAL_HAVE_WINDOWED */ + // Non-windowed address register init + movi a1, 0 + movi a2, 0 + movi a3, 0 + movi a4, 0 + movi a5, 0 + movi a6, 0 + movi a7, 0 + movi a8, 0 + movi a9, 0 + movi a10, 0 + movi a11, 0 + movi a12, 0 + movi a13, 0 + movi a14, 0 + movi a15, 0 +# endif /* XCHAL_HAVE_WINDOWED */ + // Now all address registers are zero. + + // Initialize LBEG, LEND, and LCOUNT. +# if XCHAL_HAVE_LOOPS + wsr a0, LCOUNT // note: LCOUNT gets cleared by processor reset + wsr a0, LBEG + wsr a0, LEND +# endif + +# if XCHAL_HAVE_DEBUG + .macro reset_dbreaka num + wsr a0, DBREAKA + \num + .endm + .macro reset_ibreaka num + wsr a0, IBREAKA + \num + .endm + iterate 0, XCHAL_NUM_DBREAK-1, reset_dbreaka + iterate 0, XCHAL_NUM_IBREAK-1, reset_ibreaka +# endif + + // SAR initialization + ssai 0 + + // Exception initialization +# if XCHAL_HAVE_EXCEPTIONS + wsr a0, EPC+1 + wsr a0, EXCSAVE+1 + wsr a0, EXCCAUSE +# endif + +# if XCHAL_HAVE_HIGHLEVEL_INTERRUPTS + .macro reset_int num + wsr a0, EPC + \num + wsr a0, EPS + \num + wsr a0, EXCSAVE + \num + .endm + iterate 2, XCHAL_NUM_INTLEVELS, reset_int +# endif + + // Booleans initialization +# if XCHAL_HAVE_BOOLEANS + wsr a0, BR +# endif + + // MAC16 initialization +# if XCHAL_HAVE_MAC16 + wsr a0, ACCLO + wsr a0, ACCHI + wsr a0, M0 + wsr a0, M1 + wsr a0, M2 + wsr a0, M3 +# endif + + // OCD initialization +# if XCHAL_HAVE_OCD + wsr a0, DDR +# endif + + isync // wait for all the above to take effect + +#endif /* XTOS_RESET_UNNEEDED */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/reset-vector.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/reset-vector.S new file mode 100755 index 0000000..9bb0890 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/reset-vector.S @@ -0,0 +1,434 @@ +// reset-vector.S -- Xtensa Reset Vector +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/reset-vector.S#4 $ + +// Copyright (c) 1999-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include +#include +#include +#include /* for XSHAL_USE_ABSOLUTE_LITERALS only */ +#include "xtos-internal.h" + +// The following reset vector avoids initializing certain registers already +// initialized by processor reset. +// Some of the registers reset by the processor include: +// CACHEATTR or relevant TLB state +// IBREAKENABLE Debug +// LCOUNT Loops +// PC Core +// PS Core +// ICOUNT Debug +// ICOUNTLEVEL Debug +// VECBASE Relocatable vectors +// (and various others, depending on hardware version) + + + .begin literal_prefix .ResetVector + .section .ResetVector.text, "ax" + + .align 4 + .global _ResetVector +_ResetVector: + +# if 0 /* if XCHAL_HAVE_HALT */ + // In theory, minimal reset vector for Xtensa TX (assuming bootloader to clear BSS). + // In practice we let crt*.S decide whether to do more (e.g. for sim LSP) + // and we might unpack below for ROMing LSPs. + movi sp, __stack // setup the stack + call0 main // assume declared as "void main(void)" (no args) + halt // toodaloo +# endif + +#if (!XCHAL_HAVE_HALT || defined(XTOS_UNPACK)) && XCHAL_HAVE_IMEM_LOADSTORE + // NOTE: + // + // IMPORTANT: If you move the _ResetHandler portion to a section + // other than .ResetVector.text that is outside the range of + // the reset vector's 'j' instruction, the _ResetHandler symbol + // and a more elaborate j/movi/jx sequence are needed in + // .ResetVector.text to dispatch to the new location. + + j _ResetHandler + + .size _ResetVector, . - _ResetVector + +# if XCHAL_HAVE_HALT + // Xtensa TX: reset vector segment is only 4 bytes, so must place the + // unpacker code elsewhere in the memory that contains the reset vector. +# if XCHAL_RESET_VECTOR_VADDR == XCHAL_INSTRAM0_VADDR + .section .iram0.text, "ax" +# elif XCHAL_RESET_VECTOR_VADDR == XCHAL_INSTROM0_VADDR + .section .irom0.text, "ax" +# elif XCHAL_RESET_VECTOR_VADDR == XCHAL_URAM0_VADDR + .section .uram0.text, "ax" +# else +# warning "Xtensa TX reset vector not at start of iram0, irom0, or uram0 -- ROMing LSPs may not work" + .text +# endif +# endif + + .align 4 + .literal_position // tells the assembler/linker to place literals here + + .align 4 + .global _ResetHandler +_ResetHandler: +#endif + +#if !XCHAL_HAVE_HALT + + /* + * Even if the processor supports the non-PC-relative L32R option, + * it will always start up in PC-relative mode. We take advantage of + * this, and use PC-relative mode at least until we're sure the .lit4 + * section is in place (which is sometimes only after unpacking). + */ + .begin no-absolute-literals + + + movi a0, 0 // a0 is always 0 in this code, used to initialize lots of things + +#if XCHAL_HAVE_INTERRUPTS // technically this should be under !FULL_RESET, assuming hard reset + wsr a0, INTENABLE // make sure that interrupts are shut off (*before* we lower PS.INTLEVEL and PS.EXCM!) +#endif + +#if !XCHAL_HAVE_FULL_RESET + +#if XCHAL_HAVE_CCOUNT && (XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RB_2006_0) /* pre-LX2 cores only */ + wsr a0, CCOUNT // not really necessary, but nice; best done very early +#endif + + // For full MMU configs, put page table at an unmapped virtual address. + // This ensures that accesses outside the static maps result + // in miss exceptions rather than random behaviour. + // Assumes XCHAL_SEG_MAPPABLE_VADDR == 0 (true in released MMU). +#if XCHAL_ITLB_ARF_WAYS > 0 || XCHAL_DTLB_ARF_WAYS > 0 + wsr a0, PTEVADDR +#endif + + // Debug initialization + // + // NOTE: DBREAKCn must be initialized before the combination of these two things: + // any load/store, and a lowering of PS.INTLEVEL below DEBUG_LEVEL. + // The processor already resets IBREAKENABLE appropriately. + // +#if XCHAL_HAVE_DEBUG +# if XCHAL_NUM_DBREAK +# if XCHAL_NUM_DBREAK >= 2 + wsr a0, DBREAKC1 +# endif + wsr a0, DBREAKC0 + dsync // wait for WSRs to DBREAKCn to complete +# endif + +# if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RA_2004_1 /* pre-LX cores only */ + // Starting in Xtensa LX, ICOUNTLEVEL resets to zero (not 15), so no need to initialize it. + // Prior to that we do, otherwise we get an ICOUNT exception, 2^32 instructions after reset. + rsr a2, ICOUNTLEVEL // are we being debugged? (detected by ICOUNTLEVEL not 15, or dropped below 12) + bltui a2, 12, 1f // if so, avoid initializing ICOUNTLEVEL which drops single-steps through here + wsr a0, ICOUNTLEVEL // avoid ICOUNT exceptions + isync // wait for WSR to ICOUNTLEVEL to complete +1: +# endif +#endif + +#endif /* !XCHAL_HAVE_FULL_RESET */ + +#if XCHAL_HAVE_ABSOLUTE_LITERALS + // Technically, this only needs to be done under !FULL_RESET, assuming hard reset: + wsr a0, LITBASE + rsync +#endif + +#if XCHAL_HAVE_PRID && XCHAL_HAVE_S32C1I + /* Core 0 initializes the XMP synchronization variable, if present. This operation needs to + happen as early as possible in the startup sequence so that the other cores can be released + from reset. */ + .weak _ResetSync + movi a2, _ResetSync // address of sync variable + rsr.prid a3 // core and multiprocessor ID + extui a3, a3, 0, 8 // extract core ID (FIXME: need proper constants for PRID bits to extract) + beqz a2, 1f // skip if no sync variable + bnez a3, 1f // only do this on core 0 + s32i a0, a2, 0 // clear sync variable +1: +#endif +#if XCHAL_HAVE_EXTERN_REGS && XCHAL_HAVE_MP_RUNSTALL + /* On core 0, this releases other cores. On other cores this has no effect, because + runstall control is unconnected. */ + movi a2, XER_MPSCORE + wer a0, a2 +#endif + + /* + * For processors with relocatable vectors, apply any alternate + * vector base given to xt-genldscripts, which sets the + * _memmap_vecbase_reset symbol accordingly. + */ +#if XCHAL_HAVE_VECBASE + movi a2, _memmap_vecbase_reset /* note: absolute symbol, not a ptr */ + wsr a2, vecbase +#endif + +#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */ +# if XCHAL_DCACHE_IS_COHERENT + movi a3, 0x25 /* MX -- internal for writeback, RCW otherwise */ +# else + movi a3, 0x15 /* non-MX -- always RCW */ +# endif + wsr a3, ATOMCTL +#endif + +#if XCHAL_HAVE_INTERRUPTS && XCHAL_HAVE_DEBUG + rsil a2, 1 // lower PS.INTLEVEL here to make reset vector easier to debug +#endif + + /* + * Initialize the caches. + * We do this very early because performance can increase by + * an order of magnitude when we enable the caches, which + * greatly affects start up time, including the mini-loader below. + * This is also required before we jump into any cacheable region. + * Without caches, these macros expand to nothing (see cacheasm.h). + */ + icache_reset a2, a3 + dcache_reset a2, a3 + +#if XCHAL_HAVE_PREFETCH + /* Enable cache prefetch if present. */ + movi a2, XCHAL_CACHE_PREFCTL_DEFAULT + wsr a2, PREFCTL +#endif + + /* + * Now "enable" the caches, for unpacking to occur a bit more + * efficiently. Only relevant for region protection and XEA1. + * + * The _memmap_cacheattr_reset symbol's value (address) is defined + * by the LSP's linker script, as generated by xt-genldscripts. + * + * (NOTE: for configs that don't have CACHEATTR or region protection, + * ie. for full MMUs, there is no equivalent cache attribute layout, + * and the following code has no effect. We assume for now that the + * application restricts itself to the static TLB entries, i.e. to + * virtual addresses 0xD0000000 thru 0xFFFFFFFF.) + */ +#if XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \ + || (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY) + movi a2, _memmap_cacheattr_reset /* note: absolute symbol, not a ptr */ + cacheattr_set /* set CACHEATTR from a2 (clobbers a3-a8) */ +#endif + +#if XCHAL_HAVE_EXTERN_REGS && XCHAL_DCACHE_IS_COHERENT + /* Opt into coherence if present. */ + movi a3, 1 + movi a2, XER_CCON + wer a3, a2 +#endif + +#endif /* !XCHAL_HAVE_HALT */ + + /* + * Unpack code and data (eg. copy ROMed segments to RAM, vectors into + * their proper location, etc). + */ + +#if defined(XTOS_UNPACK) + movi a2, _rom_store_table + beqz a2, unpackdone +unpack: l32i a3, a2, 0 // start vaddr + l32i a4, a2, 4 // end vaddr + l32i a5, a2, 8 // store vaddr + addi a2, a2, 12 + bgeu a3, a4, upnext // skip unless start < end +uploop: l32i a6, a5, 0 + addi a5, a5, 4 + s32i a6, a3, 0 + addi a3, a3, 4 + bltu a3, a4, uploop + j unpack +upnext: bnez a3, unpack + bnez a5, unpack +#endif /* XTOS_UNPACK */ + +unpackdone: + +#if defined(XTOS_UNPACK) || defined(XTOS_MP) + /* + * If writeback caches are configured and enabled, unpacked data must be + * written out to memory before trying to execute it: + */ + dcache_writeback_all a2, a3, 0 + icache_sync a2 // ensure data written back is visible to i-fetch + /* + * Note: no need to invalidate the i-cache after the above, because we + * already invalidated it further above and did not execute anything within + * unpacked regions afterwards. [Strictly speaking, if an unpacked region + * follows this code very closely, it's possible for cache-ahead to have + * cached a bit of that unpacked region, so in the future we may need to + * invalidate the entire i-cache here again anyway.] + */ +#endif + + +#if !XCHAL_HAVE_HALT /* skip for TX */ + + /* + * Now that we know the .lit4 section is present (if got unpacked) + * (and if absolute literals are used), initialize LITBASE to use it. + */ +#if XCHAL_HAVE_ABSOLUTE_LITERALS && XSHAL_USE_ABSOLUTE_LITERALS + /* + * Switch from PC-relative to absolute (litbase-relative) L32R mode. + * Set LITBASE to 256 kB beyond the start of the literals in .lit4 + * (aligns to the nearest 4 kB boundary, LITBASE does not have bits 1..11) + * and set the enable bit (_lit4_start is assumed 4-byte aligned). + */ + movi a2, _lit4_start + 0x40001 + wsr a2, LITBASE + rsync +#endif /* have and use absolute literals */ + .end no-absolute-literals // we can now start using absolute literals + + +// Technically, this only needs to be done pre-LX2, assuming hard reset: +# if XCHAL_HAVE_WINDOWED && defined(__XTENSA_WINDOWED_ABI__) + // Windowed register init, so we can call windowed code (eg. C code). + movi a1, 1 + wsr a1, WINDOWSTART + // The processor always clears WINDOWBASE at reset, so no need to clear it here. + // It resets WINDOWSTART to 1 starting with LX2.0/X7.0 (RB-2006.0). + // However, assuming hard reset is not yet always practical, so do this anyway: + wsr a0, WINDOWBASE + rsync + movi a0, 0 // possibly a different a0, clear it +# endif + +#if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RB_2006_0 /* only pre-LX2 needs this */ + // Coprocessor option initialization +# if XCHAL_HAVE_CP + //movi a2, XCHAL_CP_MASK // enable existing CPs + // To allow creating new coprocessors using TC that are not known + // at GUI build time without having to explicitly enable them, + // all CPENABLE bits must be set, even though they may not always + // correspond to a coprocessor. + movi a2, 0xFF // enable *all* bits, to allow dynamic TIE + wsr a2, CPENABLE +# endif + + // Floating point coprocessor option initialization (at least + // rounding mode, so that floating point ops give predictable results) +# if XCHAL_HAVE_FP && !XCHAL_HAVE_VECTORFPU2005 +# define FCR 232 /* floating-point control register (user register number) */ +# define FSR 233 /* floating-point status register (user register number) */ + rsync /* wait for WSR to CPENABLE to complete before accessing FP coproc state */ + wur a0, FCR /* clear FCR (default rounding mode, round-nearest) */ + wur a0, FSR /* clear FSR */ +# endif +#endif /* pre-LX2 */ + + + /* + * Initialize medium and high priority interrupt dispatchers: + */ +#if HAVE_XSR + +/* For asm macros; works for positive a,b smaller than 1000: */ +# define GREATERTHAN(a,b) (((b)-(a)) & ~0xFFF) + +# ifndef XCHAL_DEBUGLEVEL /* debug option not selected? */ +# define XCHAL_DEBUGLEVEL 99 /* bogus value outside 2..6 */ +# endif + + .macro init_vector level + .if GREATERTHAN(XCHAL_NUM_INTLEVELS+1,\level) + .if XCHAL_DEBUGLEVEL-\level + .weak _Level&level&FromVector + movi a4, _Level&level&FromVector + wsr a4, EXCSAVE+\level + .if GREATERTHAN(\level,XCHAL_EXCM_LEVEL) + movi a5, _Pri_&level&_HandlerAddress + s32i a4, a5, 0 + /* If user provides their own handler, that handler might + * not provide its own _Pri__HandlerAddress variable for + * linking handlers. In that case, the reference below + * would pull in the XTOS handler anyway, causing a conflict. + * To avoid that, provide a weak version of it here: + */ + .pushsection .data, "aw" + .global _Pri_&level&_HandlerAddress + .weak _Pri_&level&_HandlerAddress + .align 4 + _Pri_&level&_HandlerAddress: .space 4 + .popsection + .endif + .endif + .endif + .endm + + init_vector 2 + init_vector 3 + init_vector 4 + init_vector 5 + init_vector 6 + +#endif /*HAVE_XSR*/ + + + /* + * Complete reset initialization outside the vector, + * to avoid requiring a vector that is larger than necessary. + * This 2nd-stage startup code sets up the C Run-Time (CRT) and calls main(). + * + * Here we use call0 not because we expect any return, but + * because the assembler/linker dynamically sizes call0 as + * needed (with -mlongcalls) which it doesn't with j or jx. + * Note: This needs to be call0 regardless of the selected ABI. + */ + call0 _start // jump to _start (in crt1-*.S) + /* does not return */ + +#else /* XCHAL_HAVE_HALT */ + + j _start // jump to _start (in crt1-*.S) + // (TX has max 64kB IRAM, so J always in range) + + // Paranoia -- double-check requirements / assumptions of this Xtensa TX code: +# if !defined(__XTENSA_CALL0_ABI__) || !XCHAL_HAVE_FULL_RESET || XCHAL_HAVE_INTERRUPTS || XCHAL_HAVE_CCOUNT || XCHAL_DTLB_ARF_WAYS || XCHAL_HAVE_DEBUG || XCHAL_HAVE_S32C1I || XCHAL_HAVE_ABSOLUTE_LITERALS || XCHAL_DCACHE_SIZE || XCHAL_ICACHE_SIZE || XCHAL_HAVE_PIF || XCHAL_HAVE_WINDOWED +# error "Halt architecture (Xtensa TX) requires: call0 ABI, all flops reset, no exceptions or interrupts, no TLBs, no debug, no S32C1I, no LITBASE, no cache, no PIF, no windowed regs" +# endif + +#endif /* XCHAL_HAVE_HALT */ + + +#if (!XCHAL_HAVE_HALT || defined(XTOS_UNPACK)) && XCHAL_HAVE_IMEM_LOADSTORE + .size _ResetHandler, . - _ResetHandler +#else + .size _ResetVector, . - _ResetVector +#endif + + .text + .global xthals_hw_configid0, xthals_hw_configid1 + .global xthals_release_major, xthals_release_minor + .end literal_prefix diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/shared-reset-vector.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/shared-reset-vector.S new file mode 100644 index 0000000..4b156c2 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/shared-reset-vector.S @@ -0,0 +1,64 @@ +// shared-reset-vector.S -- Sharable Reset Vector (requires PRID option) + +// Copyright (c) 1999-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include + + // Populate this processor's entry in the reset table. + // The core instance specific LSP should put this section + // in the correct location within the table. + // + .section .ResetTable.rodata, "a" + .word _ResetHandler + + // This sharable reset code assumes RC-2009.0 or later hardware, + // to guarantee that no processor state initialization is required + // prior to doing loads etc. + // Total size is 28 bytes (or 27 with density option). + // By necessity, none of these bytes vary by core instance; + // the appropriate reset table entry is selected using PRID. + // +#if XCHAL_HAVE_PRID + .section .SharedResetVector.text, "ax" + .begin no-absolute-literals + + .align 4 + .global _SharedResetVector +_SharedResetVector: + j .LSharedResetHandler + + .align 4 + .literal_position + + .align 4 +.LSharedResetHandler: + rsr.prid a0 // get processor ID (16 bits) + movi a1, _ResetTable_base + extui a0, a0, 0, 4 // ID of core within the multiprocessor (FIXME: need proper constant...) + addx4 a1, a0, a1 + l32i a1, a1, 0 + jx a1 // jump to core-specific initialization + + .size _SharedResetVector, . - _SharedResetVector + .end no-absolute-literals +#endif + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/switch_context.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/switch_context.S new file mode 100755 index 0000000..c70c0c8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/switch_context.S @@ -0,0 +1,94 @@ +/* switch_contexts.S - setup for multiple contexts */ + +/* + * Copyright (c) 2003-2010 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#if XCHAL_NUM_CONTEXTS > 1 + + +/* + * void _xtos_setup_context(int context_num, StartInfo *info); + */ + .align 4 + .global _xtos_setup_context + .type _xtos_setup_context,@function +_xtos_setup_context: + abi_entry +#if XCHAL_HAVE_INTERRUPTS + rsil a5, 15 /* disable interrupts so we can use EXCSAVE_1 */ +#else + rsr a5, PS /* just read PS */ +#endif + wsr a3, EXCSAVE_1 /* save pointer to new context info */ + s32i a5, a3, INFO_prevps /* save previous PS */ + movi a4, ~0x01F00000 /* mask out PS.CTXT */ + slli a2, a2, 20 /* shift up new PS.CTXT value */ + and a4, a5, a4 + or a4, a4, a2 /* new PS value */ + wsr a4, PS + rsync + /* We're now in the new context! */ + movi a0, 0 + movi a1, 1 + wsr a1, WINDOWSTART + wsr a0, WINDOWBASE + rsync + rsr a9, EXCSAVE_1 /* get pointer to context info */ + movi a0, 0 /* terminate call frames */ + l32i a1, a9, INFO_sp /* get stack pointer */ + l32i a10, a9, INFO_arg1 /* get start function's arguments... */ + l32i a8, a9, INFO_funcpc /* get start function's address */ + /* Okay, now switch back to context zero: */ + l32i a9, a9, INFO_prevps /* retrieve previous PS */ + wsr a9, PS + rsync + /* Back to original context! */ + abi_return + + .size _xtos_setup_context, . - _xtos_setup_context + + + + /* + * This is the first thing to be executed in the new context + * by explicit setting of PC: + */ + .align 4 + .global _xtos_start_context +_xtos_start_context: +#ifdef __XTENSA_CALL0_ABI__ + Crash the assembler here: I think this is wrong. + callx0 a8 +#else + callx8 a8 +#endif +1: nop + j 1b /* do nothing until context 0 exits */ + .size _xtos_start_context, . - _xtos_start_context + + +#endif /* XCHAL_NUM_CONTEXTS > 1 */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/textaddr b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/textaddr new file mode 100755 index 0000000..be4e301 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/textaddr @@ -0,0 +1,59 @@ +# Program to determine -Ttext parameter for ld +# $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/textaddr#2 $ + +# Copyright (c) 2001 Tensilica Inc. +# +# Permission is hereby granted, free of charge, to any person obtaining +# a copy of this software and associated documentation files (the +# "Software"), to deal in the Software without restriction, including +# without limitation the rights to use, copy, modify, merge, publish, +# distribute, sublicense, and/or sell copies of the Software, and to +# permit persons to whom the Software is furnished to do so, subject to +# the following conditions: +# +# The above copyright notice and this permission notice shall be included +# in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +package textaddr; + +use strict; +use FileHandle; + +{ + $::myname = 'textaddr'; + + die("Usage is: $::myname objfile label address\n") + unless @ARGV == 3; + my($objfile, $label, $address) = @ARGV; + + + my $nm = new FileHandle "xt-nm $objfile|"; + die("$::myname: $!, opening pipe to xt-nm $objfile.\n") + unless $nm; + while (<$nm>) { + if (/^([0-9a-f]{8}) . (\w+)$/) { + my $oaddress = $1; + my $olabel = $2; + if ($olabel eq $label) { + printf ("0x%x\n", hex($address) - hex($oaddress)); + exit(0); + } + } + } + die ("$::myname: $label not found in $objfile.\n"); +} + +# +# Local Variables: +# mode:perl +# perl-indent-level:2 +# cperl-indent-level:2 +# End: diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/tiny-refs-min.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/tiny-refs-min.S new file mode 100755 index 0000000..453001c --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/tiny-refs-min.S @@ -0,0 +1,28 @@ +// tiny-refs-min.S - References to pull-in selected modules into tiny LSPs + +// Copyright (c) 2006 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + + .global _need_user_vector_ + .set _need_user_vector_, 0 // define this, so if referenced... + .global _UserExceptionVector // ... we pull-in this + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/tiny-refs.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/tiny-refs.S new file mode 100755 index 0000000..d89407e --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/tiny-refs.S @@ -0,0 +1,33 @@ +// tiny-refs.S - References to pull-in selected modules into tiny LSPs + +// Copyright (c) 2006 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#if defined(__SPLIT__level1int) + + .global _need_level1int_ + .set _need_level1int_, 0 // define this, so if referenced... + .global _need_user_vector_ // ... we pull-in this + .global _xtos_l1int_handler // and this + +#endif + + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/user-vector-min.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/user-vector-min.S new file mode 100755 index 0000000..3ec0f36 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/user-vector-min.S @@ -0,0 +1,105 @@ +// user-vector-min.S - Minimal User Vector for General Exceptions +// Takes less table space, but does not allow registering new handlers. +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/user-vector-min.S#3 $ + +// Copyright (c) 2003-2004, 2006-2007, 2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" + +#if XCHAL_HAVE_EXCEPTIONS + + // Vector code + .begin literal_prefix .UserExceptionVector + .section .UserExceptionVector.text, "ax" + .align 4 + .global _UserExceptionVector +_UserExceptionVector: +# if ((XSHAL_USER_VECTOR_SIZE >= 28) && XCHAL_HAVE_DENSITY) || XSHAL_VECTORS_PACKED + + addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc. + s32i a2, a1, UEXC_a2 + s32i a3, a1, UEXC_a3 + rsr a2, EXCCAUSE // get exception cause + movi a3, _xtos_min_handler_table + bgeui a2, 6, 1f // causes 6 and above map to zero + addx4 a3, a2, a3 // index by cause if 1 .. 5 +1: l32i a3, a3, 0 + s32i a4, a1, UEXC_a4 + jx a3 // jump to cause-specific handler + + .size _UserExceptionVector, . - _UserExceptionVector + .end literal_prefix + +# else /*vector as small as 12 bytes:*/ + + addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc. + s32i a2, a1, UEXC_a2 + movi a2, _UserExceptionFromVector // load user exception handler address + //interlock + jx a2 // jump to handler + + .size _UserExceptionVector, . - _UserExceptionVector + .end literal_prefix + + // Dispatch outside vector: + .text + .align 4 + .global _UserExceptionFromVector +_UserExceptionFromVector: + rsr a2, EXCCAUSE // get exception cause + s32i a3, a1, UEXC_a3 + movi a3, _xtos_min_handler_table + bgeui a2, 6, 1f // causes 6 and above map to zero + addx4 a3, a2, a3 // index by cause if 1 .. 5 +1: l32i a3, a3, 0 + s32i a4, a1, UEXC_a4 + jx a3 // jump to cause-specific handler + .size _UserExceptionFromVector, . - _UserExceptionFromVector + +# endif /*XEA2*/ + + + /* + * Read-only minimal table of assembly-level exception handlers + * for user vectored exceptions. + * Only provides entries for SYSCALL, MOVSP, and level-1 interrupt causes. + */ + .section .rodata, "a" + .global _xtos_min_handler_table + .align 4 +_xtos_min_handler_table: + .word _xtos_unhandled_exception // 0 Illegal Instruction, and causes > 5 + .word _xtos_syscall_handler // 1 SYSCALL Instruction + .word _xtos_unhandled_exception // 2 Instruction Fetch Error + .word _xtos_unhandled_exception // 3 Load/Store Error +# if XCHAL_HAVE_INTERRUPTS + .word _xtos_l1int_handler // 4 Level-1 Interrupt +# else + .word _xtos_unhandled_exception // 4 Level-1 Interrupt (not configured) +# endif + .word _xtos_alloca_handler // 5 Alloca (MOVSP Instruction) + .text + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/user-vector.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/user-vector.S new file mode 100755 index 0000000..60671b3 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/user-vector.S @@ -0,0 +1,180 @@ +// user-vector.S - User Vector for General Exceptions +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/user-vector.S#3 $ + +// Copyright (c) 1998-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include +#include +#include "xtos-internal.h" + +#if XCHAL_HAVE_EXCEPTIONS + + // Vector code + .section .UserExceptionVector.text, "ax" + .align 4 + .global _UserExceptionVector +_UserExceptionVector: +# if ((XSHAL_USER_VECTOR_SIZE >= 28) && XCHAL_HAVE_ADDX) || (XSHAL_USER_VECTOR_SIZE >= 36) || XSHAL_VECTORS_PACKED + // There is space to dispatch right at the vector: + + addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc. + s32i a2, a1, UEXC_a2 + s32i a3, a1, UEXC_a3 + movi a3, _xtos_exc_handler_table + rsr a2, EXCCAUSE // get exception cause + //interlock + addx4 a3, a2, a3 + l32i a3, a3, 0 + s32i a4, a1, UEXC_a4 + jx a3 // jump to cause-specific handler + + .size _UserExceptionVector, . - _UserExceptionVector + +# else + // The vector may be as small as 12 bytes: + + addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc. + s32i a2, a1, UEXC_a2 + movi a2, _UserExceptionFromVector // load user exception handler address + //interlock + jx a2 // jump to handler + + .size _UserExceptionVector, . - _UserExceptionVector + + // Dispatch outside vector: + .text + //.subsection 2 + .align 4 + .global _UserExceptionFromVector +_UserExceptionFromVector: + s32i a3, a1, UEXC_a3 + movi a3, _xtos_exc_handler_table + rsr a2, EXCCAUSE // get exception cause + s32i a4, a1, UEXC_a4 + addx4 a3, a2, a3 + l32i a3, a3, 0 + jx a3 // jump to cause-specific handler + + .size _UserExceptionFromVector, . - _UserExceptionFromVector + +# endif /*XEA2*/ + + + .weak _xtos_cause3_handler + + /* + * Table of assembly-level general-exception handlers + * (quickly entered) for user vectored exceptions. + * Provides entries for all possible 64 exception causes + * currently allowed for in the EXCCAUSE register. + * + * NOTE: entries that have a corresponding C handler + * (registered at run-time) point to _xtos_c_wrapper_handler; + * entries that have no handler point to _xtos_unhandled_exception. + */ + .data + .global _xtos_exc_handler_table + .align 4 +_xtos_exc_handler_table: + .word _xtos_unhandled_exception // 0 IllegalInstruction + .word _xtos_syscall_handler // 1 Syscall + .word _xtos_unhandled_exception // 2 InstructionFetchError + .word _xtos_unhandled_exception // 3 LoadStoreError +# if XCHAL_HAVE_INTERRUPTS + .word _xtos_l1int_handler // 4 Level1Interrupt +# else + .word _xtos_unhandled_exception // 4 Level1Interrupt (not configured) +# endif + .word _xtos_alloca_handler // 5 Alloca (MOVSP) + .word _xtos_unhandled_exception // 6 IntegerDivideByZero + .word _xtos_unhandled_exception // 7 Speculation + .word _xtos_unhandled_exception // 8 Privileged + .word _xtos_unhandled_exception // 9 Unaligned + .word _xtos_unhandled_exception //10 (reserved for Tensilica) + .word _xtos_unhandled_exception //11 (reserved for Tensilica) + .word _xtos_cause3_handler //12 PIF data error on fetch + .word _xtos_cause3_handler //13 PIF data error on ld/st + .word _xtos_cause3_handler //14 PIF address error on fetch + .word _xtos_cause3_handler //15 PIF address error on ld/st + .word _xtos_unhandled_exception //16 InstTLBMiss + .word _xtos_unhandled_exception //17 InstTLBMultiHit + .word _xtos_unhandled_exception //18 InstFetchPrivilege + .word _xtos_unhandled_exception //19 (reserved for Tensilica) + .word _xtos_unhandled_exception //20 InstFetchProhibited + .word _xtos_unhandled_exception //21 (reserved for Tensilica) + .word _xtos_unhandled_exception //22 (reserved for Tensilica) + .word _xtos_unhandled_exception //23 (reserved for Tensilica) + .word _xtos_unhandled_exception //24 LoadStoreTLBMiss + .word _xtos_unhandled_exception //25 LoadStoreTLBMultiHit + .word _xtos_unhandled_exception //26 LoadStorePrivilege + .word _xtos_unhandled_exception //27 (reserved for Tensilica) + .word _xtos_unhandled_exception //28 LoadProhibited + .word _xtos_unhandled_exception //29 StoreProhibited + .word _xtos_unhandled_exception //30 (reserved for Tensilica) + .word _xtos_unhandled_exception //31 (reserved for Tensilica) + .rept 8 + .word _xtos_unhandled_exception //32-39 CoprocessorDisabled (n = 0..7) + .endr + + .rept XCHAL_EXCCAUSE_NUM-40 + .word _xtos_unhandled_exception //40-63 (reserved for TIE) + .endr + + .text + + + // NOTES: + // + // Here are alternative vectors. They will NOT work with + // the handlers currently provided with XTOS. However they + // might be useful to someone writing their own handlers + // from scratch. Note that XSR is only available on T1040 + // and later hardware. + // +//*** The typical tiny 9-byte vector: *** +// wsr a3, EXCSAVE_1 // save user a3 +// movi a3, _UserExceptionFromVector // load user exception handler address +// jx a3 +// +//*** Minimizing EXCCAUSE-dispatch delay, not assuming valid SP: *** +// wsr a0, DEPC // save a0 (double exceptions fatal here, so not expected) +// rsr a0, EXCCAUSE +// xsr a1, EXCSAVE_1 // EXCSAVE_1 always contains &exception_handlers[0] +// //interlock +// addx4 a0, a0, a1 +// l32i a0, a0, TABLE_OFS + EXC_CODE_KERNEL*4 +// xsr a1, EXCSAVE_1 // restore a1 (DEPC contains original a0) +// jx a0 // jump to cause-specific handler +// +//*** Doing EXCCAUSE-dispatch with table in EXCSAVE_1: *** +// addi a1, a1, -ESF_TOTALSIZE // allocate exception stack frame, etc. +// s32i a2, a1, UEXC_a2 +// rsr a2, EXCCAUSE +// xsr a4, EXCSAVE_1 // EXCSAVE_1 always contains &exception_handlers[0] +// s32i a3, a1, UEXC_a3 +// addx4 a2, a2, a4 +// l32i a2, a2, TABLE_OFS + EXC_CODE_KERNEL*4 +// xsr a4, EXCSAVE_1 // restore a1 (DEPC contains original a0) +// jx a2 // jump to cause-specific handler + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/window-vectors.S b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/window-vectors.S new file mode 100755 index 0000000..62ba1cd --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/window-vectors.S @@ -0,0 +1,358 @@ +// window-vectors.S - Register Window Overflow/Underflow Handlers +// $Id: //depot/rel/Cottonwood/Xtensa/OS/xtos/window-vectors.S#3 $ + +// Copyright (c) 1999-2010 Tensilica Inc. +// +// Permission is hereby granted, free of charge, to any person obtaining +// a copy of this software and associated documentation files (the +// "Software"), to deal in the Software without restriction, including +// without limitation the rights to use, copy, modify, merge, publish, +// distribute, sublicense, and/or sell copies of the Software, and to +// permit persons to whom the Software is furnished to do so, subject to +// the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +#include + +#if XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__) + +# ifndef NO_SECTION_DIRECTIVES +// Exports +.global _WindowOverflow4 +.global _WindowUnderflow4 +.global _WindowOverflow8 +.global _WindowUnderflow8 +.global _WindowOverflow12 +.global _WindowUnderflow12 + + // Note: the current window exception vectors do not generate any + // literals. Hence the literal_prefix directive is not necessary. + // Specifying it "just in case" creates an empty section (named + // ".WindowVectors.literal") which can in some cases cause linking + // problems (the linker scripts don't place it anywhere). + // So leave it commented out: + // + //.begin literal_prefix .WindowVectors + + .section .WindowVectors.text, "ax" +# endif + + +// +// GENERAL NOTES: +// +// These window exception handlers need not be modified. +// They are specific to the windowed call ABI only. +// +// Underflow Handlers: +// +// The underflow handler for returning from call[i+1] to call[i] +// must preserve all the registers from call[i+1]'s window. +// In particular, a0 and a1 must be preserved because the RETW instruction +// will be reexecuted (and may even underflow again if an intervening +// exception has flushed call[i]'s registers). +// Registers a2 and up may contain return values. +// +// The caller could also potentially assume that the callee's a0 and a1 +// (its own a4&a5 if call4, a8&a9 if call8, a12&a13 if call12) +// are correct for whatever reason (not a clean thing to do in general, +// but if it's possible, unless the ABI explicitly prohibits it, +// it will eventually be done :) -- whether the the ABI needs to +// prohibit this is a different question). +// +// Timing of Handlers: +// +// Here is an overview of the overhead of taking a window exception, +// ie. the number of additional cycles taken relative to case where +// an exception is not taken. +// NOTE: these numbers do not take into account any cache misses, +// write buffer stalls, or other external stalls, if they occur. +// The totals consist of 5 cycles to enter the handler (or 6 or 7 +// for optional longer pipelines in Xtensa LX), the number of instructions +// and interlocks (2nd and 3rd columns below), and 2 cycles jump delay +// on return (3 cycles for optional longer I-side pipeline in Xtensa LX): +// +// Instruction+bubbles Totals (5-stage) +// XEA1 XEA2 XEA1 XEA2 +// Overflow-4 7 5 14 12 +// Overflow-8 14 10 21 17 +// Overflow-12 18 14 25 21 +// Underflow-4 6 5 13 12 +// Underflow-8 14 10 21 17 +// Underflow-12 18 14 25 21 +// +// Underflow-8 15 12 25 22 (7-stage; could be made 1 less) +// Underflow-12 19 16 29 26 (7-stage; could be made 1 less) + +#ifndef WINDOW_BASE_VECOFS +#define WINDOW_BASE_VECOFS XCHAL_WINDOW_OF4_VECOFS +#endif + + +// 4-Register Window Overflow Vector (Handler) +// +// Invoked if a call[i] referenced a register (a4-a15) +// that contains data from ancestor call[j]; +// call[j] had done a call4 to call[j+1]. +// On entry here: +// window rotated to call[j] start point; +// a0-a3 are registers to be saved; +// a4-a15 must be preserved; +// a5 is call[j+1]'s stack pointer. + + .org XCHAL_WINDOW_OF4_VECOFS - WINDOW_BASE_VECOFS +_WindowOverflow4: +#if XCHAL_HAVE_XEA1 + addi a5, a5, -16 // to make store offsets positive + s32i a0, a5, 0 // save a0 to call[j+1]'s stack frame + s32i a1, a5, 4 // save a1 to call[j+1]'s stack frame + s32i a2, a5, 8 // save a2 to call[j+1]'s stack frame + s32i a3, a5, 12 // save a3 to call[j+1]'s stack frame + addi a5, a5, 16 // restore a5 +#else + s32e a0, a5, -16 // save a0 to call[j+1]'s stack frame + s32e a1, a5, -12 // save a1 to call[j+1]'s stack frame + s32e a2, a5, -8 // save a2 to call[j+1]'s stack frame + s32e a3, a5, -4 // save a3 to call[j+1]'s stack frame +#endif + rfwo // rotates back to call[i] position + + .size _WindowOverflow4, . - _WindowOverflow4 + + +// 4-Register Window Underflow Vector (Handler) +// +// Invoked by RETW returning from call[i+1] to call[i] +// where call[i]'s registers must be reloaded (not live in ARs); +// call[i] had done a call4 to call[i+1]. +// On entry here: +// window rotated to call[i] start point; +// a0-a3 are undefined, must be reloaded with call[i].reg[0..3]; +// a4-a15 must be preserved (they are call[i+1].reg[0..11]); +// a5 is call[i+1]'s stack pointer. + + .org XCHAL_WINDOW_UF4_VECOFS - WINDOW_BASE_VECOFS +_WindowUnderflow4: +#if XCHAL_HAVE_XEA1 + addi a3, a5, -16 // to make load offsets positive + l32i a0, a3, 0 // restore a0 from call[i+1]'s stack frame + l32i a1, a3, 4 // restore a1 from call[i+1]'s stack frame + l32i a2, a3, 8 // restore a2 from call[i+1]'s stack frame + l32i a3, a3, 12 // restore a3 from call[i+1]'s stack frame +#else + l32e a0, a5, -16 // restore a0 from call[i+1]'s stack frame + l32e a1, a5, -12 // restore a1 from call[i+1]'s stack frame + l32e a2, a5, -8 // restore a2 from call[i+1]'s stack frame + l32e a3, a5, -4 // restore a3 from call[i+1]'s stack frame +#endif + rfwu + + .size _WindowUnderflow4, . - _WindowUnderflow4 + + +// 8-Register Window Overflow Vector (Handler) +// +// Invoked if a call[i] referenced a register (a4-a15) +// that contains data from ancestor call[j]; +// call[j] had done a call8 to call[j+1]. +// On entry here: +// window rotated to call[j] start point; +// a0-a7 are registers to be saved; +// a8-a15 must be preserved; +// a9 is call[j+1]'s stack pointer. + + .org XCHAL_WINDOW_OF8_VECOFS - WINDOW_BASE_VECOFS +_WindowOverflow8: +#if XCHAL_HAVE_XEA1 + addi a9, a9, -16 // to make store offsets positive + s32i a0, a9, 0 // save a0 to call[j+1]'s stack frame + addi a0, a1, -16 // a0 <- call[j-1]'s sp + s32i a1, a9, 4 // save a1 to call[j+1]'s stack frame + l32i a0, a0, 4 // (used to find end of call[j]'s frame) + s32i a2, a9, 8 // save a2 to call[j+1]'s stack frame + s32i a3, a9, 12 // save a3 to call[j+1]'s stack frame + addi a9, a9, 16 // restore a9 + addi a0, a0, -32 // to make load offsets positive + s32i a4, a0, 0 // save a4 to call[j]'s stack frame + s32i a5, a0, 4 // save a5 to call[j]'s stack frame + s32i a6, a0, 8 // save a6 to call[j]'s stack frame + s32i a7, a0, 12 // save a7 to call[j]'s stack frame +#else + s32e a0, a9, -16 // save a0 to call[j+1]'s stack frame + l32e a0, a1, -12 // a0 <- call[j-1]'s sp (used to find end of call[j]'s frame) + s32e a1, a9, -12 // save a1 to call[j+1]'s stack frame + s32e a2, a9, -8 // save a2 to call[j+1]'s stack frame + s32e a3, a9, -4 // save a3 to call[j+1]'s stack frame + s32e a4, a0, -32 // save a4 to call[j]'s stack frame + s32e a5, a0, -28 // save a5 to call[j]'s stack frame + s32e a6, a0, -24 // save a6 to call[j]'s stack frame + s32e a7, a0, -20 // save a7 to call[j]'s stack frame +#endif + rfwo // rotates back to call[i] position + + .size _WindowOverflow8, . - _WindowOverflow8 + + +// 8-Register Window Underflow Vector (Handler) +// +// Invoked by RETW returning from call[i+1] to call[i] +// where call[i]'s registers must be reloaded (not live in ARs); +// call[i] had done a call8 to call[i+1]. +// On entry here: +// window rotated to call[i] start point; +// a0-a7 are undefined, must be reloaded with call[i].reg[0..7]; +// a8-a15 must be preserved (they are call[i+1].reg[0..7]); +// a9 is call[i+1]'s stack pointer. + + .org XCHAL_WINDOW_UF8_VECOFS - WINDOW_BASE_VECOFS +_WindowUnderflow8: +#if XCHAL_HAVE_XEA1 + addi a9, a9, -16 // to make load offsets positive + l32i a0, a9, 0 // restore a0 from call[i+1]'s stack frame + l32i a1, a9, 4 // restore a1 from call[i+1]'s stack frame + l32i a2, a9, 8 // restore a2 from call[i+1]'s stack frame + addi a7, a1, -16 // a7 <- call[i-1]'s sp + l32i a7, a7, 4 // (used to find end of call[i]'s frame) + l32i a3, a9, 12 // restore a3 from call[i+1]'s stack frame + addi a9, a9, 16 // restore a9 + addi a7, a7, -32 // to make load offsets positive + l32i a4, a7, 0 // restore a4 from call[i]'s stack frame + l32i a5, a7, 4 // restore a5 from call[i]'s stack frame + l32i a6, a7, 8 // restore a6 from call[i]'s stack frame + l32i a7, a7, 12 // restore a7 from call[i]'s stack frame +#else + l32e a0, a9, -16 // restore a0 from call[i+1]'s stack frame + l32e a1, a9, -12 // restore a1 from call[i+1]'s stack frame + l32e a2, a9, -8 // restore a2 from call[i+1]'s stack frame + l32e a7, a1, -12 // a7 <- call[i-1]'s sp (used to find end of call[i]'s frame) + l32e a3, a9, -4 // restore a3 from call[i+1]'s stack frame + l32e a4, a7, -32 // restore a4 from call[i]'s stack frame + l32e a5, a7, -28 // restore a5 from call[i]'s stack frame + l32e a6, a7, -24 // restore a6 from call[i]'s stack frame + l32e a7, a7, -20 // restore a7 from call[i]'s stack frame +#endif + rfwu + + .size _WindowUnderflow8, . - _WindowUnderflow8 + + +// 12-Register Window Overflow Vector (Handler) +// +// Invoked if a call[i] referenced a register (a4-a15) +// that contains data from ancestor call[j]; +// call[j] had done a call12 to call[j+1]. +// On entry here: +// window rotated to call[j] start point; +// a0-a11 are registers to be saved; +// a12-a15 must be preserved; +// a13 is call[j+1]'s stack pointer. + + .org XCHAL_WINDOW_OF12_VECOFS - WINDOW_BASE_VECOFS +_WindowOverflow12: +#if XCHAL_HAVE_XEA1 + addi a13, a13, -16 // to make store offsets positive + s32i a0, a13, 0 // save a0 to call[j+1]'s stack frame + addi a0, a1, -16 // a0 <- call[j-1]'s sp + s32i a1, a13, 4 // save a1 to call[j+1]'s stack frame + l32i a0, a0, 4 // (used to find end of call[j]'s frame) + s32i a2, a13, 8 // save a2 to call[j+1]'s stack frame + s32i a3, a13, 12 // save a3 to call[j+1]'s stack frame + addi a13, a13, 16 // restore a13 + addi a0, a0, -48 // to make load offsets positive + s32i a4, a0, 0 // save a4 to end of call[j]'s stack frame + s32i a5, a0, 4 // save a5 to end of call[j]'s stack frame + s32i a6, a0, 8 // save a6 to end of call[j]'s stack frame + s32i a7, a0, 12 // save a7 to end of call[j]'s stack frame + s32i a8, a0, 16 // save a8 to end of call[j]'s stack frame + s32i a9, a0, 20 // save a9 to end of call[j]'s stack frame + s32i a10, a0, 24 // save a10 to end of call[j]'s stack frame + s32i a11, a0, 28 // save a11 to end of call[j]'s stack frame +#else + s32e a0, a13, -16 // save a0 to call[j+1]'s stack frame + l32e a0, a1, -12 // a0 <- call[j-1]'s sp (used to find end of call[j]'s frame) + s32e a1, a13, -12 // save a1 to call[j+1]'s stack frame + s32e a2, a13, -8 // save a2 to call[j+1]'s stack frame + s32e a3, a13, -4 // save a3 to call[j+1]'s stack frame + s32e a4, a0, -48 // save a4 to end of call[j]'s stack frame + s32e a5, a0, -44 // save a5 to end of call[j]'s stack frame + s32e a6, a0, -40 // save a6 to end of call[j]'s stack frame + s32e a7, a0, -36 // save a7 to end of call[j]'s stack frame + s32e a8, a0, -32 // save a8 to end of call[j]'s stack frame + s32e a9, a0, -28 // save a9 to end of call[j]'s stack frame + s32e a10, a0, -24 // save a10 to end of call[j]'s stack frame + s32e a11, a0, -20 // save a11 to end of call[j]'s stack frame +#endif + rfwo // rotates back to call[i] position + + .size _WindowOverflow12, . - _WindowOverflow12 + + +// 12-Register Window Underflow Vector (Handler) +// +// Invoked by RETW returning from call[i+1] to call[i] +// where call[i]'s registers must be reloaded (not live in ARs); +// call[i] had done a call12 to call[i+1]. +// On entry here: +// window rotated to call[i] start point; +// a0-a11 are undefined, must be reloaded with call[i].reg[0..11]; +// a12-a15 must be preserved (they are call[i+1].reg[0..3]); +// a13 is call[i+1]'s stack pointer. + + .org XCHAL_WINDOW_UF12_VECOFS - WINDOW_BASE_VECOFS +_WindowUnderflow12: +#if XCHAL_HAVE_XEA1 + addi a13, a13, -16 // to make load offsets positive + l32i a0, a13, 0 // restore a0 from call[i+1]'s stack frame + l32i a1, a13, 4 // restore a1 from call[i+1]'s stack frame + l32i a2, a13, 8 // restore a2 from call[i+1]'s stack frame + addi a11, a1, -16 // a11 <- call[i-1]'s sp + l32i a11, a11, 4 // (used to find end of call[i]'s frame) + l32i a3, a13, 12 // restore a3 from call[i+1]'s stack frame + addi a13, a13, 16 // restore a13 + addi a11, a11, -48 // to make load offsets positive + l32i a4, a11, 0 // restore a4 from end of call[i]'s stack frame + l32i a5, a11, 4 // restore a5 from end of call[i]'s stack frame + l32i a6, a11, 8 // restore a6 from end of call[i]'s stack frame + l32i a7, a11, 12 // restore a7 from end of call[i]'s stack frame + l32i a8, a11, 16 // restore a8 from end of call[i]'s stack frame + l32i a9, a11, 20 // restore a9 from end of call[i]'s stack frame + l32i a10, a11, 24 // restore a10 from end of call[i]'s stack frame + l32i a11, a11, 28 // restore a11 from end of call[i]'s stack frame +#else + l32e a0, a13, -16 // restore a0 from call[i+1]'s stack frame + l32e a1, a13, -12 // restore a1 from call[i+1]'s stack frame + l32e a2, a13, -8 // restore a2 from call[i+1]'s stack frame + l32e a11, a1, -12 // a11 <- call[i-1]'s sp (used to find end of call[i]'s frame) + l32e a3, a13, -4 // restore a3 from call[i+1]'s stack frame + l32e a4, a11, -48 // restore a4 from end of call[i]'s stack frame + l32e a5, a11, -44 // restore a5 from end of call[i]'s stack frame + l32e a6, a11, -40 // restore a6 from end of call[i]'s stack frame + l32e a7, a11, -36 // restore a7 from end of call[i]'s stack frame + l32e a8, a11, -32 // restore a8 from end of call[i]'s stack frame + l32e a9, a11, -28 // restore a9 from end of call[i]'s stack frame + l32e a10, a11, -24 // restore a10 from end of call[i]'s stack frame + l32e a11, a11, -20 // restore a11 from end of call[i]'s stack frame +#endif + rfwu + + .size _WindowUnderflow12, . - _WindowUnderflow12 + + +# ifndef NO_SECTION_DIRECTIVES + //.end literal_prefix + .text +# endif + + +#endif /* XCHAL_HAVE_WINDOWED && !defined(__XTENSA_CALL0_ABI__) */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/xtos-internal.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/xtos-internal.h new file mode 100755 index 0000000..c6f1185 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/xtos-internal.h @@ -0,0 +1,401 @@ +/* + * xtos-internal.h -- internal definitions for single-threaded run-time + * + * Copyright (c) 2003-2010 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTOS_INTERNAL_H +#define XTOS_INTERNAL_H + +#include +#include +#include +#include +#ifndef XTOS_PARAMS_H /* this to allow indirect inclusion of this header from the outside */ +#include "xtos-params.h" +#endif + +/* Relative ordering of subpriorities within an interrupt level (or vector): */ +#define XTOS_SPO_ZERO_LO 0 /* lower (eg. zero) numbered interrupts are lower priority than higher numbered interrupts */ +#define XTOS_SPO_ZERO_HI 1 /* lower (eg. zero) numbered interrupts are higher priority than higher numbered interrupts */ + + +/* Sanity check some parameters from xtos-params.h: */ +#if XTOS_LOCKLEVEL < XCHAL_EXCM_LEVEL || XTOS_LOCKLEVEL > 15 +# error Invalid XTOS_LOCKLEVEL value, must be >= EXCM_LEVEL and <= 15, please fix xtos-params.h +#endif + +/* Mask of interrupts locked out at XTOS_LOCKLEVEL: */ +#define XTOS_LOCKOUT_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XTOS_LOCKLEVEL) +/* Mask of interrupts that can still be enabled at XTOS_LOCKLEVEL: */ +#define XTOS_UNLOCKABLE_MASK (0xFFFFFFFF-XTOS_LOCKOUT_MASK) + +/* Don't set this: */ +#define XTOS_HIGHINT_TRAMP 0 /* mapping high-pri ints to low-pri not auto-supported */ +#define XTOS_VIRTUAL_INTERRUPT XTOS_HIGHINT_TRAMP /* partially-virtualized INTERRUPT register not currently supported */ +#if XTOS_HIGHINT_TRAMP +# error Automatically-generated high-level interrupt trampolines are not presently supported. +#endif + +/* + * If single interrupt at level-one, sub-prioritization is irrelevant: + */ +#if defined(XCHAL_INTLEVEL1_NUM) +# undef XTOS_SUBPRI +# define XTOS_SUBPRI 0 /* override - only one interrupt */ +#endif + +/* + * In XEA1, the INTENABLE special register must be virtualized to provide + * standard XTOS functionality. + * In XEA2, this is only needed for software interrupt prioritization. + */ +#if XTOS_SUBPRI || XCHAL_HAVE_XEA1 +#define XTOS_VIRTUAL_INTENABLE 1 +#else +#define XTOS_VIRTUAL_INTENABLE 0 +#endif + +/* + * If single interrupt per priority, then fairness is irrelevant: + */ +#if (XTOS_SUBPRI && !XTOS_SUBPRI_GROUPS) || defined(XCHAL_INTLEVEL1_NUM) +# undef XTOS_INT_FAIRNESS +# define XTOS_INT_FAIRNESS 0 +#endif + +/* Identify special case interrupt handling code in int-lowpri-dispatcher.S: */ +#define XTOS_INT_SPECIALCASE (XTOS_SUBPRI_ORDER == XTOS_SPO_ZERO_HI && XTOS_INT_FAIRNESS == 0 && XTOS_SUBPRI_GROUPS == 0) + +/* + * Determine whether to extend the interrupt entry array: + */ +#define XIE_EXTEND (XTOS_VIRTUAL_INTENABLE && !XTOS_INT_SPECIALCASE) + +/* If we have the NSAU instruction, ordering of interrupts is reversed in _xtos_interrupt_table[]: */ +#if XCHAL_HAVE_NSA +# define MAPINT(n) ((XCHAL_NUM_INTERRUPTS-1)-(n)) +# ifdef _ASMLANGUAGE + .macro mapint an + neg \an, \an + addi \an, \an, XCHAL_NUM_INTERRUPTS-1 + .endm +# endif +#else /* no NSA */ +# define MAPINT(n) (n) +# ifdef _ASMLANGUAGE + .macro mapint an + .endm +# endif +#endif + + +#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__) + +/*********** Useful macros ***********/ + +/* + * A useful looping macro: + * 'iterate' invokes 'what' (an instruction, pseudo-op or other macro) + * multiple times, passing it a numbered parameter from 'from' to 'to' + * inclusively. Does not invoke 'what' at all if from > to. + * Maximum difference between 'from' and 'to' is 99 minus nesting depth + * (GNU 'as' doesn't allow nesting deeper than 100). + */ + .macro iterate from, to, what + .ifeq ((\to-\from) & ~0xFFF) + \what \from + iterate "(\from+1)", \to, \what + .endif + .endm // iterate + + + + // rsilft + // + // Execute RSIL \ar, \tolevel if \tolevel is different than \fromlevel. + // This way the RSIL is avoided if we know at assembly time that + // it will not change the level. Typically, this means the \ar register + // is ignored, ie. RSIL is used only to change PS.INTLEVEL. + // + .macro rsilft ar, fromlevel, tolevel +#if XCHAL_HAVE_INTERRUPTS + .if \fromlevel - \tolevel + rsil \ar, \tolevel + .endif +#endif + .endm + + + // Save LOOP and MAC16 registers, if configured, to the exception stack + // frame pointed to by address register \esf, using \aa and \ab as temporaries. + // + // This macro essentially saves optional registers that the compiler uses by + // default when present. + // Note that the acclo/acchi subset of MAC16 may be used even if others + // multipliers are present (e.g. mul16, mul32). + // + // Only two temp registers required for this code to be optimal (no interlocks) in both + // T10xx (Athens) and Xtensa LX microarchitectures (both 5 and 7 stage pipes): + // + .macro save_loops_mac16 esf, aa, ab +#if XCHAL_HAVE_LOOPS + rsr \aa, LCOUNT + rsr \ab, LBEG + s32i \aa, \esf, UEXC_lcount + rsr \aa, LEND + s32i \ab, \esf, UEXC_lbeg + s32i \aa, \esf, UEXC_lend +#endif +#if XCHAL_HAVE_MAC16 + rsr \aa, ACCLO + rsr \ab, ACCHI + s32i \aa, \esf, UEXC_acclo + s32i \ab, \esf, UEXC_acchi +# if XTOS_SAVE_ALL_MAC16 + rsr \aa, M0 + rsr \ab, M1 + s32i \aa, \esf, UEXC_mr + 0 + s32i \ab, \esf, UEXC_mr + 4 + rsr \aa, M2 + rsr \ab, M3 + s32i \aa, \esf, UEXC_mr + 8 + s32i \ab, \esf, UEXC_mr + 12 +# endif +#endif + .endm + + // Restore LOOP and MAC16 registers, if configured, from the exception stack + // frame pointed to by address register \esf, using \aa, \ab and \ac as temporaries. + // + // Three temp registers are required for this code to be optimal (no interlocks) in + // Xtensa LX microarchitectures with 7-stage pipe; otherwise only two + // registers would be needed. + // + .macro restore_loops_mac16 esf, aa, ab, ac +#if XCHAL_HAVE_LOOPS + l32i \aa, \esf, UEXC_lcount + l32i \ab, \esf, UEXC_lbeg + l32i \ac, \esf, UEXC_lend + wsr \aa, LCOUNT + wsr \ab, LBEG + wsr \ac, LEND +#endif +#if XCHAL_HAVE_MAC16 + l32i \aa, \esf, UEXC_acclo + l32i \ab, \esf, UEXC_acchi +# if XTOS_SAVE_ALL_MAC16 + l32i \ac, \esf, UEXC_mr + 0 + wsr \aa, ACCLO + wsr \ab, ACCHI + wsr \ac, M0 + l32i \aa, \esf, UEXC_mr + 4 + l32i \ab, \esf, UEXC_mr + 8 + l32i \ac, \esf, UEXC_mr + 12 + wsr \aa, M1 + wsr \ab, M2 + wsr \ac, M3 +# else + wsr \aa, ACCLO + wsr \ab, ACCHI +# endif +#endif + .endm + + +/* Offsets from _xtos_intstruct structure: */ + .struct 0 +#if XTOS_VIRTUAL_INTENABLE +XTOS_ENABLED_OFS: .space 4 /* _xtos_enabled variable */ +XTOS_VPRI_ENABLED_OFS: .space 4 /* _xtos_vpri_enabled variable */ +#endif +#if XTOS_VIRTUAL_INTERRUPT +XTOS_PENDING_OFS: .space 4 /* _xtos_pending variable */ +#endif + .text + + +#if XTOS_VIRTUAL_INTENABLE + // Update INTENABLE register, computing it as follows: + // INTENABLE = _xtos_enabled & _xtos_vpri_enabled + // [ & ~_xtos_pending ] + // + // Entry: + // register ax = &_xtos_intstruct + // register ay, az undefined (temporaries) + // PS.INTLEVEL set to XTOS_LOCKLEVEL or higher (eg. via xtos_lock) + // window overflows prevented (PS.WOE=0, PS.EXCM=1, or overflows + // already done for registers ax, ay, az) + // + // Exit: + // registers ax, ay, az clobbered + // PS unchanged + // caller needs to SYNC (?) for INTENABLE changes to take effect + // + // Note: in other software prioritization schemes/implementations, + // the term <_xtos_vpri_enabled> in the above expression is often + // replaced with another expression that computes the set of + // interrupts allowed to be enabled at the current software virtualized + // interrupt priority. + // + // For example, a simple alternative implementation of software + // prioritization for XTOS might have been the following: + // INTENABLE = _xtos_enabled & (vpri_enabled | UNLOCKABLE_MASK) + // which removes the need for the interrupt dispatcher to 'or' the + // UNLOCKABLE_MASK bits into _xtos_vpri_enabled, and lets other code + // disable all lockout level interrupts by just clearing _xtos_vpri_enabled + // rather than setting it to UNLOCKABLE_MASK. + // Other implementations sometimes use a table, eg: + // INTENABLE = _xtos_enabled & enable_table[current_vpri] + // The HAL (used by some 3rd party OSes) uses essentially a table-driven + // version, with other tables enabling run-time changing of priorities. + // + .macro xtos_update_intenable ax, ay, az + //movi \ax, _xtos_intstruct + l32i \ay, \ax, XTOS_VPRI_ENABLED_OFS // ay = _xtos_vpri_enabled + l32i \az, \ax, XTOS_ENABLED_OFS // az = _xtos_enabled + //interlock + and \az, \az, \ay // az = _xtos_enabled & _xtos_vpri_enabled +# if XTOS_VIRTUAL_INTERRUPT + l32i \ay, \ax, XTOS_PENDING_OFS // ay = _xtos_pending + movi \ax, -1 + xor \ay, \ay, \ax // ay = ~_xtos_pending + and \az, \az, \ay // az &= ~_xtos_pending +# endif + wsr \az, INTENABLE + .endm +#endif /* VIRTUAL_INTENABLE */ + + .macro xtos_lock ax + rsil \ax, XTOS_LOCKLEVEL // lockout + .endm + + .macro xtos_unlock ax + wsr \ax, PS // unlock + rsync + .endm + +/* Offsets to XtosIntHandlerEntry structure fields (see below): */ +# define XIE_HANDLER 0 +# define XIE_ARG 4 +# define XIE_SIZE 8 +# if XIE_EXTEND +# define XIE_VPRIMASK (XIE_SIZE*XCHAL_NUM_INTERRUPTS+0) /* if VIRTUAL_INTENABLE [SUBPRI||XEA1] && !SPECIALCASE */ +# define XIE_LEVELMASK (XIE_SIZE*XCHAL_NUM_INTERRUPTS+4) /* [fairness preloop] if FAIRNESS && SUBPRI [&& SUBPRI_GROUPS] */ +# endif + +/* To simplify code: */ +# if XCHAL_HAVE_NSA +# define IFNSA(a,b) a +# else +# define IFNSA(a,b) b +# endif + +#else /* !_ASMLANGUAGE && !__ASSEMBLER__ */ + +/* + * Interrupt handler table entry. + * Unregistered entries have 'handler' point to _xtos_unhandled_interrupt(). + */ +typedef struct XtosIntHandlerEntry { + _xtos_handler handler; + void * arg; +} XtosIntHandlerEntry; +# if XIE_EXTEND +typedef struct XtosIntMaskEntry { + unsigned vpri_mask; /* mask of interrupts enabled when this interrupt is taken */ + unsigned level_mask; /* mask of interrupts at this interrupt's level */ +} XtosIntMaskEntry; +# endif + +#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */ + +/* + * Notes... + * + * XEA1 and interrupt-SUBPRIoritization both imply virtualization of INTENABLE. + * Synchronous trampoloines imply partial virtualization of the INTERRUPT + * register, which in turn also implies virtualization of INTENABLE register. + * High-level interrupts manipulating the set of enabled interrupts implies + * at least a high XTOS_LOCK_LEVEL, although not necessarily INTENABLE virtualization. + * + * With INTENABLE register virtualization, at all times the INTENABLE + * register reflects the expression: + * (set of interrupts enabled) & (set of interrupts enabled by current + * virtual priority) + * + * Unrelated (DBREAK semantics): + * + * A[31-6] = DBA[3-6] + * --------------------- + * A[5-0] & DBC[5-C] & szmask + * + * = DBA[5-0] & szmask + * ^___ ??? + */ + + +/* Report whether the XSR instruction is available (conservative): */ +#define HAVE_XSR (XCHAL_HAVE_XEA2 || !XCHAL_HAVE_EXCEPTIONS) +/* + * This is more accurate, but not a reliable test in software releases prior to 6.0 + * (where the targeted hardware parameter was not explicit in the XPG): + * + *#define HAVE_XSR (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_T1040_0) + */ + + + +/* Macros for supporting hi-level and medium-level interrupt handling. */ + +#if XCHAL_NUM_INTLEVELS > 6 +#error Template files (*-template.S) limit support to interrupt levels <= 6 +#endif + +#if defined(__XTENSA_WINDOWED_ABI__) && XCHAL_HAVE_CALL4AND12 == 0 +#error CALL8-only is not supported! +#endif + +#define INTERRUPT_IS_HI(level) \ + ( XCHAL_HAVE_INTERRUPTS && \ + (XCHAL_EXCM_LEVEL < level) && \ + (XCHAL_NUM_INTLEVELS >= level) && \ + (XCHAL_HAVE_DEBUG ? XCHAL_DEBUGLEVEL != level : 1)) + +#define INTERRUPT_IS_MED(level) \ + (XCHAL_HAVE_INTERRUPTS && (XCHAL_EXCM_LEVEL >= level)) + + +#define _JOIN(x,y) x ## y +#define JOIN(x,y) _JOIN(x,y) + +#define _JOIN3(a,b,c) a ## b ## c +#define JOIN3(a,b,c) _JOIN3(a,b,c) + +#define LABEL(x,y) JOIN3(x,_INTERRUPT_LEVEL,y) +#define EXCSAVE_LEVEL JOIN(EXCSAVE_,_INTERRUPT_LEVEL) +#define INTLEVEL_VSIZE JOIN3(XSHAL_INTLEVEL,_INTERRUPT_LEVEL,_VECTOR_SIZE) + + + +#endif /* XTOS_INTERNAL_H */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/xtos-params.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/xtos-params.h new file mode 100755 index 0000000..96af261 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/athos/src/xtos/xtos-params.h @@ -0,0 +1,123 @@ +/* + * xtos-params.h -- user-settable parameters for XTOS single-threaded run-time + * + * Copyright (c) 2002, 2004, 2006-2007 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTOS_PARAMS_H +#define XTOS_PARAMS_H + +/* + * IMPORTANT NOTE. + * This file contains XTOS parameters that may be modified + * according to needs. HOWEVER, any modifications are NOT + * supported. Handling of parameters other than the defaults + * provided in the original version of this file are for + * illustrative and educational purposes only. If you do + * change the parameters here-in (which requires rebuilding + * XTOS), please verify the resulting code extensively + * before even considering its use in production code. + * + * To rebuild XTOS, see instructions in the Xtensa System Software + * Reference Manual. The following sequence is no longer supported. + * + * cd /xtensa-elf/src/handlers + * xt-make clean + * xt-make + * xt-make install + * + * (Note: the last step installs the modified XTOS in *ALL* + * LSPs that normally include XTOS. You may prefer copying + * the generated files to your own custom LSP instead. Or + * better yet, also make a copy of all source files and maintain + * them somewhere completely separate -- which may require + * minor adjustments to the makefile.) + * + * PERFORMANCE TUNING: + * To slightly improve performance of interrupt dispatching, + * you can do some combination of the following: + * - change XTOS_SUBPRI to zero + * - change XTOS_SUBPRI_GROUPS to zero + * - change XTOS_SUBPRI_ORDER to XTOS_SPO_ZERO_HI + * - change XTOS_DEBUG_PC to zero + * - change XTOS_INT_FAIRNESS to zero + * - change XTOS_CNEST to zero + * There are non-trivial trade-offs in making such changes however, + * such as loss of support (see important note above), loss of + * interrupt scheduling fairness, loss of ability to traceback + * interrupt handlers across interrupted code when debugging them, + * loss of supported for nested C functions, etc. + */ + + +/* + * Lower LOCKLEVEL to XCHAL_EXCM_LEVEL for improved interrupt latency + * if you don't register C handlers for high-priority interrupts and your + * high-priority handlers don't touch INTENABLE nor virtual priorities. + * + * XTOS_LOCKLEVEL is less meaningful but still relevant if XEA2 and SUBPRI is zero, + * ie. if INTENABLE doesn't get virtualized (XTOS_VIRTUAL_INTENABLE not set); + * in this case, it is the interrupt level at which INTENABLE accesses are guarded, + * so that interrupt handlers up to this level can safely manipulate INTENABLE. + */ +#define XTOS_LOCKLEVEL XCHAL_NUM_INTLEVELS /* intlevel of INTENABLE register virtualization + (minimum is EXCM_LEVEL) */ + +/* + * NOTE: the following four parameters (SUBPRI, SUBPRI_GROUPS, SUBPRI_ORDER, INT_FAIRNESS) + * are irrelevant and ignored for interrupt vectors to which only one interrupt is mapped. + */ + +#define XTOS_SUBPRI 1 /* set to 0 if you don't need sub-prioritization + within level-one interrupts via software; + for XEA2 configs, this might improve performance of + certain sections of code, because INTENABLE register + virtualization becomes unnecessary in this case */ + +/* Ignored unless SUBPRI set: */ +#define XTOS_SUBPRI_GROUPS 1 /* support selective grouping of interrupts at the same priority */ + +#define XTOS_SUBPRI_ORDER XTOS_SPO_ZERO_LO /* one of XTOS_SPO_ZERO_LO, XTOS_SPO_ZERO_HI */ + +/* Ignored if SUBPRI set but SUBPRI_GROUPS is not (single interrupt per subpri), + * or if single interrupt configured at level/vector: */ +#define XTOS_INT_FAIRNESS 1 /* disable round-robin/fifo scheduling of interrupt + handlers of a given level or sub-priority */ + + +#define XTOS_DEBUG_PC 1 /* enable nice stack traceback showing interrupted code + when debugging interrupt or exception handler; + not implemented for high-priority handlers, or + for call0 ABI */ + +#define XTOS_CNEST 1 /* enable support for nested C functions + (save/restore nested C function call-chain pointer) */ + +/* Current compilers only use ACC (not MRn) when MAC16 is enabled, so you can leave this 0 for performance: */ +#define XTOS_SAVE_ALL_MAC16 0 /* set to save/restore MAC16 MRn registers */ + +/* Setting this might be useful to clear X's in hardware simulation a bit earlier, but + * should not be needed in production code: */ +#define XTOS_RESET_UNNEEDED 0 /* set to reset more registers than are really needed */ + +#endif /* XTOS_PARAMS_H */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/Makefile new file mode 100755 index 0000000..b3cecf1 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/Makefile @@ -0,0 +1,60 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export SSNAME = buf_pool + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libbuf_pool.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/Makefile.ss new file mode 100755 index 0000000..2db0004 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/buf_pool_static.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/inc/buf_pool_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/inc/buf_pool_api.h new file mode 100755 index 0000000..c69e1b7 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/inc/buf_pool_api.h @@ -0,0 +1,50 @@ +/* + * @File: buf_pool_api.h + * + * @Abstract: BUF Pool api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _BUF_POOL_API_H +#define _BUF_POOL_API_H + +#include + +/* endpoint defines */ +typedef enum +{ + POOL_ID_HTC_CONTROL = 0, + POOL_ID_WMI_SVC_CMD_REPLY = 1, + POOL_ID_WMI_SVC_EVENT = 2, + POOL_ID_WLAN_RX_BUF = 3, + POOL_ID_MAX = 10 +} BUF_POOL_ID; + +typedef void* pool_handle_t; + +/* hardware API table structure (API descriptions below) */ +struct buf_pool_api { + pool_handle_t (*_init)(adf_os_handle_t handle); + + void (*_shutdown)(pool_handle_t handle); + + void (*_create_pool)(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize); + + adf_nbuf_t (*_alloc_buf)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve); + + adf_nbuf_t (*_alloc_buf_align)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align); + + void (*_free_buf)(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void buf_pool_module_install(struct buf_pool_api *apis); + +#endif /* #ifndef _BUF_POOL_API_H */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/src/buf_pool_static.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/src/buf_pool_static.c new file mode 100755 index 0000000..8365a60 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/src/buf_pool_static.c @@ -0,0 +1,128 @@ +/* + * @File: + * + * @Abstract: Buf pool implementation: static version + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "buf_pool_static.h" + +LOCAL htc_handle_t _buf_pool_static_init(adf_net_handle_t handle); +LOCAL void _buf_pool_static_create_pool(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize); +LOCAL adf_nbuf_t _buf_pool_static_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve); +LOCAL adf_nbuf_t _buf_pool_static_alloc_buf_align(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align); +LOCAL void _buf_pool_static_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf); +LOCAL void _buf_pool_static_shutdown(pool_handle_t handle); + +BUF_POOL_STATIC_CONTEXT g_poolCtx; + +void buf_pool_module_install(struct buf_pool_api *pAPIs) +{ + pAPIs->_init = _buf_pool_static_init; + pAPIs->_create_pool = _buf_pool_static_create_pool; + pAPIs->_alloc_buf = _buf_pool_static_alloc_buf; + pAPIs->_alloc_buf_align = _buf_pool_static_alloc_buf_align; + pAPIs->_free_buf = _buf_pool_static_free_buf; + pAPIs->_shutdown = _buf_pool_static_shutdown; +} + +LOCAL pool_handle_t _buf_pool_static_init(adf_os_handle_t handle) +{ +#if 1 + int i; + + for(i=0; i < POOL_ID_MAX; i++) { + g_poolCtx.bufQ[i] = NULL; + } + + return &g_poolCtx; +#else + BUF_POOL_STATIC_CONTEXT *ctx; + + //ctx = (BUF_POOL_static_CONTEXT *)A_ALLOCRAM(sizeof(BUF_POOL_static_CONTEXT)); + ctx = (BUF_POOL_STATIC_CONTEXT *)adf_os_mem_alloc(sizeof(BUF_POOL_STATIC_CONTEXT)); + ctx->NetHandle = handle; + + return ctx; +#endif +} + +LOCAL void _buf_pool_static_shutdown(pool_handle_t handle) +{ + // SHALL NOT BE USED in FW +} + +LOCAL void _buf_pool_static_create_pool(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize) +{ + int i; + VBUF *buf; + VDESC *desc; + + //BUF_POOL_STATIC_CONTEXT *ctx = (BUF_POOL_STATIC_CONTEXT *)handle; + + for ( i = 0; i < nItems; i++) { + buf = VBUF_alloc_vbuf(); + desc = VDESC_alloc_vdesc(); + + desc->buf_addr = (A_UINT8 *)adf_os_mem_alloc(nSize); + desc->buf_size = nSize; + desc->data_offset = 0; + desc->data_size = 0; + + buf->buf_length = 0; + buf->desc_list = desc; + + if ( g_poolCtx.bufQ[poolId] == NULL ) { + g_poolCtx.bufQ[poolId] = buf; + } else { + buf->next_buf = g_poolCtx.bufQ[poolId]; + g_poolCtx.bufQ[poolId] = buf; + } + } +} + +LOCAL adf_nbuf_t _buf_pool_static_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve) +{ + VBUF *buf; + + buf = g_poolCtx.bufQ[poolId]; + if ( buf != NULL ) { + g_poolCtx.bufQ[poolId] = buf->next_buf; + + buf->next_buf = NULL; + buf->desc_list->data_offset = reserve; + buf->desc_list->data_size = 0; + buf->buf_length = 0; + } + + return buf; +} + +LOCAL adf_nbuf_t _buf_pool_static_alloc_buf_align(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align) +{ + return _buf_pool_static_alloc_buf(handle, poolId, reserve); +} + +LOCAL void _buf_pool_static_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf) +{ + if ( g_poolCtx.bufQ[poolId] == NULL ) { + g_poolCtx.bufQ[poolId] = buf; + } else { + buf->next_buf = g_poolCtx.bufQ[poolId]; + g_poolCtx.bufQ[poolId] = buf; + } +} diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/src/buf_pool_static.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/src/buf_pool_static.h new file mode 100755 index 0000000..32feb19 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/buf_pool/src/buf_pool_static.h @@ -0,0 +1,24 @@ +/* + * @File: + * + * @Abstract: + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef BUF_POOL_STATIC_H_ +#define BUF_POOL_STATIC_H_ + +typedef struct _BUF_POOL_STATIC_CONTEXT { + VBUF *bufQ[POOL_ID_MAX]; + + // Left a door for extension the structure + void *pReserved; +} BUF_POOL_STATIC_CONTEXT; + +#endif /*BUF_POOL_STATIC_H_*/ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/Makefile new file mode 100755 index 0000000..89d4b5f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/Makefile @@ -0,0 +1,62 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = cmnos + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +#export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +DIRS = allocram clock eeprom intr mem misc printf rompatch string tasklet timer wdt uart sflash +#DIRS = allocram + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: +# for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + for i in $(DIRS) ; do $(MAKE) -C $$i all || exit $? ; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(DIRS) ; do $(MAKE) -C $$i dep || exit $? ; done + +clean: + for i in $(DIRS) ; do $(MAKE) -C $$i clean; done + +init: + for i in $(DIRS) ; do $(MAKE) -C $$i init; done + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/Makefile new file mode 100755 index 0000000..2327209 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/Makefile @@ -0,0 +1,60 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = allocram + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +#export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/Makefile.ss new file mode 100755 index 0000000..a4e6247 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_allocram.o + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/inc/allocram_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/inc/allocram_api.h new file mode 100755 index 0000000..f86d34f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/inc/allocram_api.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2007 Atheros Communications, Inc. All rights reserved. + */ + +#ifndef __ALLOCRAM_API_H__ +#define __ALLOCRAM_API_H__ + +/* API for Target-side startup-time RAM allocations */ + +struct allocram_api { + /* + * Initialize allocram, providing it with a block of RAM + * (an "arena") from which to allocate. + * + * If arena_start is 0, a default start -- the end of + * the application's text & data -- is used. + * + * If arena_sz is 0, a default size -- which uses most + * of physical RAM beyond arena_start -- is used. + * + * Return value is reserved for future use -- it's an arena handle. + */ + void *(* cmnos_allocram_init)(void *arena_start, A_UINT32 arena_sz); + + /* + * Allocate nbytes of memory, returning a pointer to the start + * of the allocated block. Allocation size is rounded up to the + * nearest A_CACHE_LINE_SIZE and the returned address similarly + * aligned. + * + * There is no need to check the return value from this function. + * A failure to satisfy a RAM allocation request is treated as a + * fatal error. + * + * Allocations are expected to occur only during startup; this + * API does not, for instance, guarantee atomicity with respect + * to allocations that might (foolishly) be attempted from + * interrupt handlers. + * + * The "which_arena" parameter is currently unused, and should + * be set to 0 -- only a single arena is currently supported. + */ + void *(* cmnos_allocram)(void *which_arena, A_UINT32 nbytes); + + void (* cmnos_allocram_debug)(void); +}; + +extern void allocram_module_install(struct allocram_api *api); + + +#endif /* __ALLOCRAM_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/src/cmnos_allocram.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/src/cmnos_allocram.c new file mode 100755 index 0000000..ac40c64 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/allocram/src/cmnos_allocram.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + */ + +#include "sys_cfg.h" +#include "athos_api.h" + +#if SYSTEM_MODULE_ALLOCRAM + +/* + * Startup time RAM allocation. + * + * Oddly enough, we allow allocation, but not free. + * The central idea is to restrict compile-time RAM demands + * of modules to a minimum so that if a module is replaced + * at run-time large amounts of RAM are not wasted. + * + * Addresses returned are A_CACHE_LINE_SIZE aligned. + */ + +LOCAL A_UINT32 allocram_current_addr; +LOCAL A_UINT32 allocram_remaining_bytes; + +LOCAL void * +cmnos_allocram_init(void *arena_start, A_UINT32 arena_sz) +{ + A_UINT32 astart = (A_UINT32)arena_start; + +#if defined(__XTENSA__) + /* + * This hacky line converts from a text or data RAM address + * into a data RAM address. (It's all the same on MIPS, but + * text and data are different address spaces on Xtensa.) + */ + //astart = TARG_RAM_ADDRS(TARG_RAM_OFFSET(astart)); +#endif + +#if 0 + if (arena_sz == 0) { + /* Default arena_sz to most of available RAM */ + arena_sz = TARG_RAM_SZ - (A_UINT32)TARG_RAM_OFFSET(astart); + arena_sz -= HOST_INTEREST->hi_end_RAM_reserve_sz; + } +#endif + + /* Clear entire area */ +// A_MEMSET(astart, 0, arena_sz); + + /* Adjust for cache line alignment */ +#if 0 + allocram_current_addr = A_ROUND_UP(astart, A_CACHE_LINE_SIZE); + arena_sz -= (allocram_current_addr-astart); +#else + allocram_current_addr = astart; +#endif + allocram_remaining_bytes = arena_sz; + + //A_DCACHE_FLUSH(); + + //A_PRINTF("cmnos_allocram_init: start=0x%x size=%d\n", + // allocram_current_addr, allocram_remaining_bytes); + + return NULL; /* Future implementation may return an arena handle */ +} + +/* + * Allocate nbytes from the arena. At this point, which_arena should + * be set to 0 for the default (and only) arena. A future allocation + * module may support multiple separate arenas. + */ +LOCAL void * +cmnos_allocram(void * which_arena, A_UINT32 nbytes) +{ + void *ptr = (void *)allocram_current_addr; + //nbytes = A_ROUND_UP(nbytes, A_CACHE_LINE_SIZE); + nbytes = A_ROUND_UP(nbytes, 4); + if (nbytes <= allocram_remaining_bytes) { + allocram_remaining_bytes -= nbytes; + allocram_current_addr += nbytes; + } else { + A_PRINTF("RAM allocation (%d bytes) failed!\n", nbytes); + //A_ASSERT(0); + adf_os_assert(0); + } + + return ptr; +} + +void +cmnos_allocram_debug(void) +{ + A_PRINTF("ALLOCRAM Current Addr 0x%x\n", allocram_current_addr); + A_PRINTF("ALLOCRAM Remaining Bytes %d\n", allocram_remaining_bytes); +} + +void +cmnos_allocram_module_install(struct allocram_api *tbl) +{ + tbl->cmnos_allocram_init = cmnos_allocram_init; + tbl->cmnos_allocram = cmnos_allocram; + tbl->cmnos_allocram_debug = cmnos_allocram_debug; +} + +#endif /* SYSTEM_MODULE_ALLOCRAM */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/Makefile new file mode 100755 index 0000000..daa1851 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = clock + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/Makefile.ss new file mode 100755 index 0000000..ab83dfa --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_clock.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/inc/clock_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/inc/clock_api.h new file mode 100755 index 0000000..e4c9b27 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/inc/clock_api.h @@ -0,0 +1,21 @@ +#ifndef __CLOCK_API_H__ +#define __CLOCK_API_H__ + +#define TICK_MSEC_RATIO 1 +#define TICK_TO_MSEC(tick) ((tick)/TICK_MSEC_RATIO) +#define MSEC_TO_TICK(msec) ((msec)* TICK_MSEC_RATIO) + +struct clock_api { + void (* _clock_init)(A_UINT32 ref_clk); + void (* _clockregs_init)(void); + A_UINT32 (* _uart_frequency)(void); + void (* _delay_us)(int); + void (* _wlan_band_set)(int); + A_UINT32 (* _refclk_speed_get)(void); + A_UINT32 (* _milliseconds)(void); + void (* _sysclk_change)(void); + + void (* _clock_tick)(void); +}; + +#endif /* __CLOCK_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/src/cmnos_clock.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/src/cmnos_clock.c new file mode 100755 index 0000000..ae34bf8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/clock/src/cmnos_clock.c @@ -0,0 +1,290 @@ +#include "sys_cfg.h" + +#if SYSTEM_MODULE_CLOCK +#include "athos_api.h" + +LOCAL A_UINT32 cticks = 0; + +#define A_BAND_DEFAULT 0 // not ust now, avoiding compile error/warning, Ryan + +LOCAL int curr_band = A_BAND_DEFAULT; +LOCAL void cmnos_pll_init(void); + +/* We accept frequencies within this deviation from an expected frequency. */ +#define A_REFCLK_DEVIATION 800000 + +#define A_REFCLK_UNKNOWN SYS_CFG_REFCLK_UNKNOWN +#define A_REFCLK_10_MHZ SYS_CFG_REFCLK_10_MHZ +#define A_REFCLK_20_MHZ SYS_CFG_REFCLK_20_MHZ +#define A_REFCLK_40_MHZ SYS_CFG_REFCLK_40_MHZ + +LOCAL const struct cmnos_clock_s { + A_refclk_speed_t refclk_speed; + A_UINT32 ticks_per_sec; + // below are useless so far, ryan + A_UINT32 pll_ctrl_5ghz; + A_UINT32 pll_ctrl_24ghz; + A_UINT32 pll_settling_time; /* 50us */ +} cmnos_clocking_table[] = { + {A_REFCLK_10_MHZ, + //10485760, + 10000000, + 0x0, + 0x0, + 0x0}, + + {A_REFCLK_20_MHZ, + //20971520, + 20000000, + 0x0, + 0x0, + 0x0}, + + {A_REFCLK_40_MHZ, + //41943040, + 40000000, + 0x0, + 0x0, + 0x0}, + + {A_REFCLK_UNKNOWN, + 0, + 0x0, + 0x0, + 0x0}, +}; + + +#define CMNOS_CLOCKING_TABLE_NUM_ENTRIES \ + (sizeof(cmnos_clocking_table)/sizeof(cmnos_clocking_table[0])) + +LOCAL struct cmnos_clock_s *clock_info; + + +LOCAL void cmnos_tick(void); + +/* + * In case we have PLL initialization problems, software can arrange + * (e.g. through BMI) to skip PLL initialization, and other software + * can handle it. + */ +int cmnos_skip_pll_init = 0; +A_UINT32 pll_ctrl_setting_24ghz = 0; +A_UINT32 pll_ctrl_setting_5ghz = 0; + +/* + * Use default hardware values for clock-related registers. + * The defaults can be overridden through BMI, EJTAG, or patches. + * + * CPU clock frequencies depend on what mode we're in (2.4GHz or 5GHz): + * NB: AR6001 has a "reduced power" mode, but we don't use it. + * + * AR6001/AR6002 FPGA CPU clock is always at 40MHz + * + * AR6001 Rev 2.x supports 4 CPU speed selections: + * selector: 0 1 2 3 + * 2.4GHz: 44, 88, 141, refclk + * 5 GHz: 40, 80, 128, refclk + * + * AR6002 supports 7 CPU/SoC speed selections via CORE_CLK: + * CORE_CLK.DIV setting: 6,7 5 4 3 2 1 0 + * divisor: 16 14 12 10 8 6 4 + * 2.4GHz (pll at 352MHz): 22 25.1, 29.3, 35.2, 44, 58.7, 88 + * 5 GHz (pll at 320MHz): 20 22.9, 26.7, 32, 40, 53.3, 80 + */ + +#if defined(DISABLE_SYNC_DURING_PLL_UPDATE_WAR) +A_UINT32 cpu_clock_setting; +#endif + +//A_COMPILE_TIME_ASSERT(verify_host_interest_small_enough, +// (sizeof(struct host_interest_s) <= HOST_INTEREST_MAX_SIZE)) + +//A_COMPILE_TIME_ASSERT(verify_flash_is_present_addr, +// ((A_UINT32)&HOST_INTEREST->hi_flash_is_present) == FLASH_IS_PRESENT_TARGADDR) + + +LOCAL void +cmnos_delay_us(int us) +{ +// A_UINT32 start_time = A_RTC_REG_READ(LF_TIMER_COUNT0_ADDRESS); +// unsigned int num_LF_ticks = (us+29) / 30 + 1; /* ~30.5us per LF tick */ + //A_UINT32 ref_clk = (clock_info->ticks_per_sec)/1000/1000; + A_UINT32 ref_clk = (clock_info->ticks_per_sec) >> 20; + A_UINT32 start_time = NOW(); + unsigned int num_ticks = us*ref_clk; // system_freq == number of ticks per 1us + + while ( (NOW() - start_time) < num_ticks) { + /* busy spin */; + } +} + +/* + * Return the number of milliseconds since startup. + * For this purpose, a "millisecond" is approximated by + * 1/32 of a 32KHz clock. + */ +LOCAL A_UINT32 +cmnos_milliseconds(void) +{ + //unsigned int lowfreq_timer; + + //lowfreq_timer = A_RTC_REG_READ(LF_TIMER_COUNT0_ADDRESS); + //lowfreq_timer = NOW(); + + /* LF0 timer counts at 32KHz, so adjust to approximate Ms with >> 5. */ + //lowfreq_timer = lowfreq_timer; + + /* + * NB: We do not account for wrap, which occurs every 36 + * hours when the 32768Hz low frequency timer wraps the + * 32 bit counter. + */ + cmnos_tick(); + + return cticks; +} + + +/* Expect 40MHz on AR6001 and 26MHz on AR6002 */ +//LOCAL A_refclk_speed_t cmnos_refclk_speed; + +LOCAL A_UINT32 +cmnos_refclk_speed_get(void) +{ + return clock_info->ticks_per_sec; +} + +/* The UART is clocked at the reference clock frequency. */ +LOCAL A_UINT32 +cmnos_uart_frequency(void) +{ +#if 0 +#if defined(FPGA) + return clock_info->ticks_per_sec; +#else + return clock_info->ticks_per_sec; +#endif +#else + /* TBD */ + /* do we need keep a struct to hold the data ?*/ +#endif +} + + +/* + * Adjust any state that needs adjusting when the clock + * speed changes. + */ +LOCAL void +cmnos_sysclk_change(void) +{ + /* OS may override this function */ +} + + +LOCAL void +cmnos_clockregs_init(void) +{ + /* TBD */ + /* we might don't need this init() */ +} + +/* + * Make whatever system-level changes are needed in order to operate + * in the specified wireless band. + * + * For AR6K, we just need to set the PLL appropriately. + */ +LOCAL void +cmnos_wlan_band_set(int which_band) +{ + /* TBD */ + /* we don't have wlan need to config */ +} + +LOCAL void +cmnos_pll_init(void) +{ + /* TBD */ + /* we don't have pll now, */ +} + +LOCAL void +cmnos_clock_init(A_UINT32 ref_clk) +{ +#if 1 + unsigned int i; + + /* Look up the nearest supported frequency. */ + for (i = 0; + i < CMNOS_CLOCKING_TABLE_NUM_ENTRIES-1; + i++) + { + A_UINT32 ticks_per_sec; + + ticks_per_sec = cmnos_clocking_table[i].ticks_per_sec; + if ((ref_clk > ticks_per_sec - A_REFCLK_DEVIATION) && + (ref_clk < ticks_per_sec + A_REFCLK_DEVIATION)) + { + break; + } + } + + clock_info = (struct cmnos_clock_s *)&cmnos_clocking_table[i]; +// HOST_INTEREST->hi_clock_info = (A_UINT32)clock_info; + +#endif +} + +//////////////////////////////////////////////////////////////////////// +// software emulate ticks on millisecond based +LOCAL void +cmnos_tick(void) +{ +#if 0 + + set_ccompare0(xthal_get_ccompare(XTENSA_TIMER_0)+ONE_MSEC); + + cticks++; + +#else + static A_UINT32 last_tick = 0; + A_UINT32 current_tick = NOW(); + A_UINT32 delta_tick; + + // tick is 32 bit register, will overflow soon + if( current_tick < last_tick ) + { + delta_tick = (A_UINT32 )((0xffffffff-last_tick)+current_tick+1)/(1000); + } + else + { + delta_tick = (A_UINT32 ) (current_tick - last_tick)/(1000); + } + + if( delta_tick > 0 ) + last_tick = current_tick; + + cticks += delta_tick; +#endif +} + +//////////////////////////////////////////////////////////////////////// + +void +cmnos_clock_module_install(struct clock_api *tbl) +{ + tbl->_clock_init = cmnos_clock_init; + tbl->_clockregs_init = cmnos_clockregs_init; + tbl->_delay_us = cmnos_delay_us; + tbl->_wlan_band_set = cmnos_wlan_band_set; + tbl->_refclk_speed_get = cmnos_refclk_speed_get; + tbl->_milliseconds = cmnos_milliseconds; + tbl->_uart_frequency = cmnos_uart_frequency; + tbl->_sysclk_change = cmnos_sysclk_change; + + tbl->_clock_tick = cmnos_tick; +} +#endif /* SYSTEM_MODULE_CLOCK */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/Makefile new file mode 100755 index 0000000..f403548 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = eeprom + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/Makefile.ss new file mode 100755 index 0000000..9fe6e31 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_eeprom.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/inc/eeprom_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/inc/eeprom_api.h new file mode 100755 index 0000000..deab32a --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/inc/eeprom_api.h @@ -0,0 +1,32 @@ +#ifndef __EEPROM_API_H__ +#define __EEPROM_API_H__ +/* + * + */ + + +typedef enum { + RET_SUCCESS = 0, + RET_NOT_INIT, + RET_NOT_EXIST, + RET_EEP_CORRUPT, + RET_EEP_OVERFLOW, + + // add return code from here + RET_UNKNOWN +}T_EEP_RET; + + +/*!- interface of eeprom access + * + */ +struct eep_api { + void (* _eep_init)(void); + T_EEP_RET (* _eep_read)(uint16_t, uint16_t, uint16_t *); + T_EEP_RET (* _eep_write)(uint16_t, uint16_t, uint16_t *); + T_EEP_RET (*_eep_is_exist)(void); + +}; + +#endif /* __EEPROM_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/src/cmnos_eeprom.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/src/cmnos_eeprom.c new file mode 100755 index 0000000..8429306 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/eeprom/src/cmnos_eeprom.c @@ -0,0 +1,422 @@ +#include "athos_api.h" + + +#if SYSTEM_MODULE_EEPROM + +// DEBUG DELAY OF RC ACCESS!!!!!! SHOULD BE FIXED! +#define PCIE_RC_ACCESS_DELAY 20 + +#define PCI_RC_RESET_BIT BIT6 +#define PCI_RC_PHY_RESET_BIT BIT7 +#define PCI_RC_PLL_RESET_BIT BIT8 +#define PCI_RC_PHY_SHIFT_RESET_BIT BIT10 + +#define H_EEPROM_CTRL 0x401c + #define B_EEP_CTRL_CLKDIV (BIT2|BIT3|BIT4|BIT5|BIT6|BIT7) + #define B_EEP_CTRL_NOT_PRESENT (BIT8) + #define B_EEP_CTRL_CORRUPT (BIT9) + +#define H_EEPROM_STS_DATA 0x407c + #define B_EEP_STS_STATE_BUSY (BIT16) + #define B_EEP_STS_IS_BUSY (BIT17) + #define B_EEP_STS_PROTECTED (BIT18) + #define B_EEP_STS_DATA_NOT_EXIST (BIT19) + +#define CMD_PCI_RC_RESET_ON() HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)| \ + (PCI_RC_PHY_SHIFT_RESET_BIT|PCI_RC_PLL_RESET_BIT|PCI_RC_PHY_RESET_BIT|PCI_RC_RESET_BIT))) + +#define CMD_PCI_RC_RESET_CLR() HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)& \ + (~(PCI_RC_PHY_SHIFT_RESET_BIT|PCI_RC_PLL_RESET_BIT|PCI_RC_PHY_RESET_BIT|PCI_RC_RESET_BIT)))) + + +//////////////////////////////////////////////////////////////////////////////////////////////// + + +/*! eep write half word + * + * offset: is the offset address you want to do the write operation + * data: is the data to write to eeprom + * + * return: TRUE/FALSE + */ +LOCAL BOOLEAN cmnos_eeprom_write_hword(uint16_t offset, uint16_t data) +{ + /*! - Livy sugguest not use the retry, since it'll be huge retry count + * so that, supposed that if the apb or pcie_rc is working fine, + * we should always could see the NOT_BUSY, otherwise, + * it should have something worng!, put a little delay in there, + * + * - debug string here will be noisy!! + */ + //uint16_t retryCnt = 1000; + +#if defined(PROJECT_MAGPIE) + //gpio configuration, set GPIOs output to value set in output reg + HAL_WORD_REG_WRITE((EEPROM_CTRL_BASE+0x4054), (HAL_WORD_REG_READ((EEPROM_CTRL_BASE+0x4054)) | 0x20000)); + HAL_WORD_REG_WRITE((EEPROM_CTRL_BASE+0x4060), 0); + HAL_WORD_REG_WRITE((EEPROM_CTRL_BASE+0x4064), 0); + + //GPIO3 always drive output + HAL_WORD_REG_WRITE((EEPROM_CTRL_BASE+0x404c), 0xc0); + + //Set 0 on GPIO3 + HAL_WORD_REG_WRITE((EEPROM_CTRL_BASE+0x4048), 0x0); +#endif + + HAL_WORD_REG_WRITE(EEPROM_ADDR_BASE + offset*4, (uint32_t)data); + + //while( retryCnt-- > 0 ) + while(1) + { + if( (HAL_WORD_REG_READ((EEPROM_CTRL_BASE+H_EEPROM_STS_DATA))&(B_EEP_STS_STATE_BUSY | B_EEP_STS_IS_BUSY)) == 0 ) + { + return(TRUE); + } +// A_DELAY_USECS(100); + } + + return FALSE; +} + +/*! eep read half word + * + * offset: is the offset address you want to do the read operation + * + * return: the data we read from eeprom + */ +LOCAL BOOLEAN cmnos_eeprom_read_hword(uint16_t offset, uint16_t *mData) +{ + uint32_t mStsData; + //uint16_t retryCnt = 1000; + + HAL_WORD_REG_READ(EEPROM_ADDR_BASE + offset*4); + + //while( retryCnt-- > 0 ) + while(1) + { + mStsData = HAL_WORD_REG_READ((EEPROM_CTRL_BASE+H_EEPROM_STS_DATA)); + + if( (mStsData&(B_EEP_STS_STATE_BUSY | B_EEP_STS_IS_BUSY)) == 0 ) + { + *mData = (uint16_t)(mStsData & 0xffff); + return TRUE; + } +// A_DELAY_USECS(100); + } + + return FALSE; +} +////////////////////////////////////////////////////////////////////////////////////////////////////// + +LOCAL BOOLEAN eep_state = FALSE; +LOCAL BOOLEAN eep_exist = FALSE; + + +/*!- Initialize eeprom, actually we link up the pcie_rc for accessing the eeprom in client card + * + */ +LOCAL T_EEP_RET +cmnos_eep_is_exist(void) +{ + if( FALSE != eep_state ) + { + if( FALSE == eep_exist ) + { + uint16_t mData = HAL_WORD_REG_READ((EEPROM_CTRL_BASE+H_EEPROM_CTRL)); + + if( mData&B_EEP_CTRL_NOT_PRESENT ) + return RET_NOT_EXIST; + else if ( mData&B_EEP_CTRL_CORRUPT ) + return RET_EEP_CORRUPT; + else { + eep_exist = TRUE; + return RET_SUCCESS; + } + } + else // already done the checking, fast response + return RET_SUCCESS; + } + + return RET_NOT_INIT; +} + +/*!- eeprom write + * + * offset: where to write + * len: number of half-word of the pBuf + * pBuf: data buffer to write + */ +LOCAL T_EEP_RET +cmnos_eep_write(uint16_t offset, uint16_t len, uint16_t *pBuf) +{ + T_EEP_RET retVal; + uint16_t *pData = (uint16_t*)pBuf; + uint16_t i, j; + + uint16_t eep_start_ofst = EEPROM_START_OFFSET; + uint16_t eep_end_ofst = EEPROM_END_OFFSET; + + + if( FALSE != eep_state ) + { + if( (offset < eep_start_ofst) || (offset > eep_end_ofst) || ((offset+len) > eep_end_ofst) ) + { + A_PUTS("-E10-"); + retVal = RET_EEP_OVERFLOW; + } + else + { + for(i=offset, j=0; i eep_end_ofst) || ((offset+len) > eep_end_ofst) ) + { + A_PUTS("-E13-"); + retVal = RET_EEP_OVERFLOW; + } + else + { + for(i=(offset); i0) + { + reg_value = HAL_WORD_REG_READ(0x00040018); + if( reg_value & BIT0 ) + break; + A_DELAY_USECS(PCIE_RC_ACCESS_DELAY); + } + + /* init fail, can't detect PCI_RC LINK UP, give up the init */ + if( i<=0 ) + { + DEBUG_SYSTEM_STATE |= BIT26; + goto ERR_DONE; + } + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x47; + HAL_WORD_REG_WRITE(0x14000004, (HAL_WORD_REG_READ(0x14000004)|0x116)); + A_DELAY_USECS(PCIE_RC_ACCESS_DELAY); + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x48; + HAL_WORD_REG_WRITE(0x14000010, (HAL_WORD_REG_READ(0x14000010)|EEPROM_CTRL_BASE)); + eep_state = TRUE; + } + +#elif defined(PROJECT_K2) + eep_state = TRUE; +#endif /* End of #if defined(PROJECT_MAGPIE) */ + if (TRUE == eep_state) + { + /* Read offset 1 location to determine if this EEPROM is protected somewhere */ + HAL_WORD_REG_READ(EEPROM_ADDR_BASE + 4); + + while(1) + { + mStsData = HAL_WORD_REG_READ((EEPROM_CTRL_BASE+H_EEPROM_STS_DATA)); + + /* If this location is protected or EEPROM does not exist, return immediately */ + if ( mStsData & (B_EEP_STS_PROTECTED | B_EEP_STS_DATA_NOT_EXIST) ) + { + eep_state = FALSE; + break; + } + + if ( ( mStsData & (B_EEP_STS_STATE_BUSY | B_EEP_STS_IS_BUSY) ) == 0 ) + { + if (mStsData & 0xffff) + cmnos_eeprom_write_hword( (uint16_t)1, (uint16_t)0 ); + + break; + } + + A_DELAY_USECS(100); + } + } +ERR_DONE: + +} + + +void +cmnos_eep_module_install(struct eep_api *tbl) +{ + tbl->_eep_init = cmnos_eep_init; + tbl->_eep_read = cmnos_eep_read; + tbl->_eep_write = cmnos_eep_write; + tbl->_eep_is_exist = cmnos_eep_is_exist; +} + +#endif /* SYSTEM_MODULE_EEPROM */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/inc/cmnos_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/inc/cmnos_api.h new file mode 100755 index 0000000..ff75603 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/inc/cmnos_api.h @@ -0,0 +1,638 @@ +#ifndef __CMNOS_API_H__ +#define __CMNOS_API_H__ + +/* + * This file contains wrappers to OS operating system functions + * that are available in all versions of the operating system. + * + * Target software must always use these wrappers to access OS + * services -- it may not access any OS services directly. + */ + +#include "sys_cfg.h" + +#include "xtensa/config/core.h" +#include "xtensa/hal.h" +#include "xtensa/xtruntime.h" + +/* cmnos interface */ +#include "printf_api.h" +#include "uart_api.h" +#include "dbg_api.h" +#include "mem_api.h" +#include "misc_api.h" +#include "string_api.h" +#include "timer_api.h" +#include "romp_api.h" +#include "allocram_api.h" +#include "tasklet_api.h" +#include "clock_api.h" +#include "intr_api.h" +#include "wdt_api.h" +#include "eeprom_api.h" +#include "usb_api.h" +#include +#include + +#if defined(PROJECT_K2) +#if SYSTEM_MODULE_SFLASH +#include "cmnos/sflash_api.h" +#endif +#endif + +#define AR6K_ROM_START 0x004e0000 +#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) +#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) + +#define IML_SIGNAL_UNUSED0_ADDR TARG_ROM_ADDRS(0) /* Cannot be used -- aligned */ +#define IML_SIGNAL_ASSERT_ADDR TARG_ROM_ADDRS(1) /* Signal an assertion failure */ +#define IML_SIGNAL_PRINTF_ADDR TARG_ROM_ADDRS(2) /* Signal a printf request */ +#define IML_SIGNAL_UNUSED4_ADDR TARG_ROM_ADDRS(4) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSED8_ADDR TARG_ROM_ADDRS(8) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSEDC_ADDR TARG_ROM_ADDRS(0xc) /* Cannot be used -- aligned */ +#define IML_SIGNAL_MASK 0xfffe000f +#define IML_LINENUM_SHIFT 4 + +#define NOW() xthal_get_ccount() + +#if defined(__XTENSA__) +#define _A_BARRIER asm volatile("memw") +#else +#define _A_BARRIER +#endif + +#define A_ASSERT( __bool ) \ + do { \ + if (0 == (__bool)) { \ + (void)*((volatile int *)(IML_SIGNAL_ASSERT_ADDR+(__LINE__<<4)));\ + _A_BARRIER; \ + } \ + } while (0) + + +#define A_IML_IS_ASSERT(vaddr) \ + (((vaddr) & IML_SIGNAL_MASK) == (IML_SIGNAL_ASSERT_ADDR & IML_SIGNAL_MASK)) + + +#define PRINT_FAILURE_STATE() \ +do { \ + uint32_t epc1, epc2, epc3, epc4; \ + \ + asm volatile("rsr %0,%1" : "=r" (epc1) : "n" (EPC_1)); \ + asm volatile("rsr %0,%1" : "=r" (epc2) : "n" (EPC_2)); \ + asm volatile("rsr %0,%1" : "=r" (epc3) : "n" (EPC_3)); \ + asm volatile("rsr %0,%1" : "=r" (epc4) : "n" (EPC_4)); \ + \ + A_PRINTF("\tepc1=0x%x, epc2=0x%x, epc3=0x%x, epc4=0x%x\n", \ + epc1, epc2, epc3, epc4); \ + A_PRINTF("0x%08x, 0x%08x, 0x%08x, \n\r", \ + DEBUG_SYSTEM_STATE, WATCH_DOG_RESET_COUNTER, \ + WATCH_DOG_MAGIC_PATTERN); \ +} while(0) +//////////////////////////////////////////////////////////////////////////////////// + + +//#define A_CMN(sym) _A_OS_INDIRECTION_TABLE->cmnos.sym +#define A_CMN(sym) _A_MAGPIE_INDIRECTION_TABLE->cmnos.sym + +#if SYSTEM_MODULE_MEM +/* Mem interfaces */ +#define A_MEMSET(addr, value, size) \ + A_CMN(mem._memset((char *)(addr), (int)(value), (int)(size))) + +#define A_MEMZERO(addr, size) \ + A_CMN(mem._memset((char *)(addr), (int)0, (int)(size))) + +#define A_MEMCPY(dst, src, size) \ + A_CMN(mem._memcpy((char *)(dst), (char *)(src), (int)(size))) + +#define A_MEMMOVE(dst, src, size) \ + A_CMN(mem._memmove((char *)(dst), (char *)(src), (int)(size))) + +#define A_MEMCMP(p1, p2, nbytes) \ + A_CMN(mem._memcmp)((void *)(p1), (void *)(p2), (int)(nbytes)) +#else +/* Mem interfaces */ +#define A_MEMSET(addr, value, size) + +#define A_MEMZERO(addr, size) + +#define A_MEMCPY(dst, src, size) + +#define A_MEMMOVE(dst, src, size) + +#define A_MEMCMP(p1, p2, nbytes) +#endif + + +#if 1 + /* String interfaces */ + #define A_STRCPY(dst, src) A_CMN(string._strcpy((dst), (src))) + #define A_STRNCPY(dst, src, n) A_CMN(string._strncpy((dst), (src), (n))) + #define A_STRLEN(str) A_CMN(string._strlen(str)) + #define A_STRCMP(str1, str2) A_CMN(string._strcmp((str1), (str2))) + #define A_STRNCMP(str1, str2, n) A_CMN(string._strncmp((str1), (str2), (n))) +#endif + +#if SYSTEM_MODULE_PRINT +/* Printf support */ +#define A_PRINTF_INIT() A_CMN(printf._printf_init()) +#define A_PRINTF A_CMN(printf._printf) +#else +#define A_PRINTF_INIT() +#define A_PRINTF +#endif /* SYSTEM_MODULE_PRINT */ + +#if SYSTEM_MODULE_UART +/* Serial port support */ +#define A_UART_INIT() A_CMN(uart._uart_init()) + +#define A_UART_HWINIT(freq, baud) \ + A_CMN(uart._uart_hwinit((freq), (baud))) + +#define A_UART_ENABLED() (HOST_INTEREST->hi_uart_enable) + +#define A_PUTS(str) A_CMN(uart._uart_str_out(str)) + +#define A_PUTC(ch) A_CMN(uart._uart_char_put(ch)) +#define A_GETC(pCh) A_CMN(uart._uart_char_get(pCh)) + +#define A_UART_TASK() A_CMN(uart._uart_task()) +#define A_UART_CONFIG(x) A_CMN(uart._uart_config(x)) + +#else + +#define A_UART_INIT() + +#define A_UART_HWINIT(freq, baud) + +#define A_UART_ENABLED() + +#define A_PUTS(str) + +#define A_PUTC(ch) +#define A_GETC(pCh) + +#define A_UART_TASK() +#define A_UART_CONFIG(x) + +#endif + +#if SYSTEM_MODULE_MISC +/* Reset Support */ +#define A_RESET() A_CMN(misc._system_reset()) +#define A_RESET_MAC() A_CMN(misc._mac_reset()) + +/* Assertion failure */ +#define A_ASSFAIL(regdump) A_CMN(misc._assfail((regdump))) + +/* Report a failure to the Host */ +#define A_REPORT_FAILURE(data, len) \ + A_CMN(misc._report_failure_to_host((data), (len))) + +/* UNALIGNED references are used for ASSERTs */ +#define A_MISALIGNED_LOAD_HANDLER(dump) A_CMN(misc._misaligned_load_handler(dump)) + +/* reture the host interface type */ +#define A_IS_HOST_PRESENT() A_CMN(misc._is_host_present()) +#define A_KBHIT(delay) A_CMN(misc._kbhit(delay)) +#define A_GET_ROM_VER() A_CMN(misc._rom_version_get()) +#else +/* Reset Support */ +#define A_RESET() +#define A_RESET_MAC() + +/* Assertion failure */ +#define A_ASSFAIL(regdump) + +#define A_MISALIGNED_LOAD_HANDLER(dump) + +/* Report a failure to the Host */ +#define A_REPORT_FAILURE(data, len) + +#define A_IS_HOST_PRESENT() +#define A_KBHIT(delay) +#define A_GET_ROM_VER() +#endif + +//#if SYSTEM_MODULE_DBG +/* debug Support */ +//#define A_DBG_INIT() A_CMN(dbg._dbg_init()) +//#define A_DBG_TASK() A_CMN(dbg._dbg_task()) +//#else +//#define A_DBG_INIT() +//#define A_DBG_TASK() +//#endif + +#if SYSTEM_MODULE_USB +/* debug Support */ +#define A_USB_INIT() A_CMN(usb._usb_init()) +#define A_USB_ROM_TASK() A_CMN(usb._usb_rom_task()) +#define A_USB_FW_TASK() A_CMN(usb._usb_fw_task()) +#define A_USB_INIT_PHY() A_CMN(usb._usb_init_phy()) + +#define A_USB_EP0_SETUP() A_CMN(usb._usb_ep0_setup()) +#define A_USB_EP0_TX_DATA() A_CMN(usb._usb_ep0_tx_data()) +#define A_USB_EP0_RX_DATA() A_CMN(usb._usb_ep0_rx_data()) + +#define A_USB_GET_CONFIG() A_CMN(usb._usb_get_configuration()) +#define A_USB_SET_CONFIG() A_CMN(usb._usb_set_configuration()) + +#define A_USB_GET_INTERFACE() A_CMN(usb._usb_get_interface()) +#define A_USB_SET_INTERFACE() A_CMN(usb._usb_set_interface()) + +#define A_USB_STANDARD_CMD() A_CMN(usb._usb_standard_cmd()) +#define A_USB_VENDOR_CMD() A_CMN(usb._usb_vendor_cmd()) + +#define A_USB_POWER_OFF() A_CMN(usb._usb_power_off()) +#define A_USB_RESET_FIFO() A_CMN(usb._usb_reset_fifo()) +#define A_USB_GEN_WDT() A_CMN(usb._usb_gen_wdt()) +#define A_USB_JUMP_BOOT() A_CMN(usb._usb_jump_boot()) + +#define A_USB_GET_DESCRIPTOR() A_CMN(usb._usb_get_descriptor()) +#define A_USB_SET_ADDRESS() A_CMN(usb._usb_set_address()) +#define A_USB_SET_FEATURE() A_CMN(usb._usb_set_feature()) +#define A_USB_CLEAR_FEATURE() A_CMN(usb._usb_clr_feature()) + +#define A_USB_GET_STATUS() A_CMN(usb._usb_get_status()) +#define A_USB_SETUP_DESC() A_CMN(usb._usb_setup_desc()) +#define A_USB_STATUS_IN() A_CMN(usb._usb_status_in()) +#define A_USB_REG_OUT() A_CMN(usb._usb_reg_out()) + +#define A_USB_EP0_TX() A_CMN(usb._usb_ep0_tx()) +#define A_USB_EP0_RX() A_CMN(usb._usb_ep0_rx()) +#define A_USB_CLK_INIT() A_CMN(usb._usb_clk_init()) + +#else +#define A_USB_INIT() +#define A_USB_TASK() +#define A_USB_INIT_PHY() + +#define A_USB_EP0_SETUP() +#define A_USB_EP0_TX() +#define A_USB_EP0_RX() + +#define A_USB_GET_CONFIG() +#define A_USB_SET_CONFIG() + +#define A_USB_GET_INTERFACE() +#define A_USB_SET_INTERFACE() + +#define A_USB_STANDARD_CMD() +#define A_USB_VENDOR_CMD() + +#define A_USB_POWER_OFF() +#define A_USB_RESET_FIFO() +#define A_USB_GEN_WDT() +#define A_USB_JUMP_BOOT() + +#define A_USB_GET_DESCRIPTOR() +#define A_USB_SET_ADDRESS() +#define A_USB_SET_FEATURE() +#define A_USB_CLEAR_FEATURE() + +#define A_USB_GET_STATUS() +#define A_USB_SETUP_DESC() + + +#define A_USB_STATUS_IN() +#define A_USB_REG_OUT() + +#define A_USB_EP0_TX() +#define A_USB_EP0_RX() + +#define A_USB_CLK_INIT() +#endif + +#if SYSTEM_MODULE_INTR +/* Low-level interrupt support intended for use by OS modules */ +#define A_INTR_GET_INTRENABLE() A_CMN(intr._get_intrenable()) +#define A_INTR_SET_INTRENABLE(val) A_CMN(intr._set_intrenable(val)) +#define A_INTR_GET_INTRPENDING() A_CMN(intr._get_intrpending()) +#define A_INTR_UNBLOCK_ALL_INTRLVL() A_CMN(intr._unblock_all_intrlvl()) + +/* Interrupt support */ +#define A_INTR_INIT() A_CMN(intr._intr_init()) + +#define A_INTR_DISABLE(pOld) \ + do { \ + *(pOld) = A_CMN(intr._intr_disable()); \ + } while (0) + +#define A_INTR_RESTORE(old) A_CMN(intr._intr_restore((old))) + +#define A_INVOKE_ISR(inum) A_CMN(intr._intr_invoke_isr(inum)) + +#define A_INTR_MASK(inum) A_CMN(intr._intr_mask_inum(inum)) +#define A_INTR_UNMASK(inum) A_CMN(intr._intr_unmask_inum(inum)) + +#define A_ATTACH_ISR(inum, isr, arg) A_CMN(intr._intr_attach_isr(inum, isr, arg)) +#else +#define A_INTR_INIT() +#define A_INTR_DISABLE(pOld) +#define A_INTR_RESTORE(old) + +#define A_INTR_GET_INTRENABLE() +#define A_INTR_SET_INTRENABLE(val) +#define A_INTR_GET_INTRPENDING() +#define A_INTR_UNBLOCK_ALL_INTRLVL() +#define A_INVOKE_ISR(inum) +#define A_INTR_MASK(inum) +#define A_INTR_UNMASK(inum) +#define A_ATTACH_ISR(inum, isr, arg) + +#endif + +/* Tasklet Support */ +#define A_TASKLET_INIT() A_CMN(tasklet._tasklet_init()) +#define A_TASKLET_INIT_TASK(f, arg, t) A_CMN(tasklet._tasklet_init_task(f, arg, t)) +#define A_TASKLET_DISABLE(t) A_CMN(tasklet._tasklet_disable(t)) +#define A_TASKLET_SCHEDULE(t) A_CMN(tasklet._tasklet_schedule(t)) +#define A_TASKLET_RUN() A_CMN(tasklet._tasklet_run()) + + +/* RAM Allocation Support */ +#if defined(__mips__) +#define alloc_arena_start _end +#endif +#if defined(__XTENSA__) +#define alloc_arena_start _end +#endif + +#if SYSTEM_MODULE_CLOCK + +#define A_CLOCK_INIT(refclk_guess) A_CMN(clock._clock_init(refclk_guess)) +#define A_CLOCK_TICK() A_CMN(clock._clock_tick()) +#define A_CLOCK_GET_TICK() A_CMN(clock._clock_get_tick()) + +/* + * Get the number of millisecond ticks since the system was started. + * Note that this only approximates 1Ms. It's actually 32 ticks of + * a 32KHz clock. + * + * Returns a A_UINT32 value. + */ +#define A_MILLISECONDS() A_CMN(clock._milliseconds()) + +/* + * Get the frequency of the reference clock, expressed as + * an A_refclk_speed_t. + */ +#define A_REFCLK_SPEED_GET() A_CMN(clock._refclk_speed_get()) + +/* Spin delay */ +#define A_DELAY_USECS(us) A_CMN(clock._delay_us(us)) + +#define A_UART_FREQUENCY() A_CMN(clock._uart_frequency()) + +#define A_CLOCKREGS_INIT() A_CMN(clock._clockregs_init()) + +/* which_band is either A_BAND_24GHZ or A_BAND_5GHZ */ +#define A_WLAN_BAND_SET(which_band) \ + A_CMN(clock._wlan_band_set(which_band)) + +/* Called whenever the system clock changes speed */ +#define A_SYSCLK_CHANGE() A_CMN(clock._sysclk_change()) + +#else + +#define A_CLOCK_INIT(refclk_guess) +#define A_CLOCK_TICK() +#define A_CLOCK_GET_TICK() +#define A_MILLISECONDS() +#define A_REFCLK_SPEED_GET() +#define A_DELAY_USECS(us) +#define A_UART_FREQUENCY() +#define A_CLOCKREGS_INIT() +#define A_WLAN_BAND_SET(which_band) +#define A_SYSCLK_CHANGE() + +#endif + +// Timer +#define A_INIT_TIMER(pTimer, pFunction, pArg) \ + A_CMN(timer._timer_setfn((pTimer), (pFunction), (pArg))) + +/* Set a (possibly periodic) timer for "period" Milliseconds. */ +#define A_TIMEOUT_MS(pTimer, period) \ + A_CMN(timer._timer_arm((pTimer), (period))) + +#define A_UNTIMEOUT(pTimer) \ + A_CMN(timer._timer_disarm(pTimer)) + +#define A_TIMER_RUN() \ + A_CMN(timer._timer_run()) + +#define A_PCI_BOOT_INIT() \ + A_CMN(pci.pci_boot_init()) + +#define A_GMAC_BOOT_INIT() \ + A_CMN(gmac.gmac_boot_init()) + +#if SYSTEM_MODULE_ALLOCRAM +/* Default size of ALLOCRAM area */ +#define ARENA_SZ_DEFAULT 12000 + +#define A_ALLOCRAM_INIT(arena_start, arena_size) \ +do { \ + extern unsigned int alloc_arena_start; \ + void *astart; \ + int asize; \ + astart = (arena_start) ? (void *)(arena_start) : &alloc_arena_start; \ + asize = (arena_size) ? (arena_size) : (ARENA_SZ_DEFAULT); \ + A_CMN(allocram.cmnos_allocram_init((astart), (asize))); \ +} while (0) + +#define A_ALLOCRAM(nbytes) A_CMN(allocram.cmnos_allocram(0, (nbytes))) + +#define A_ALLOCRAM_DEBUG() A_CMN(allocram.cmnos_allocram_debug()) + +#else +#define A_ALLOCRAM_INIT(arena_start, arena_size) +#define A_ALLOCRAM(nbytes) +#define A_ALLOCRAM_DEBUG() +#endif + +#if SYSTEM_MODULE_ROM_PATCH + +#define A_ROMP_INIT() A_CMN(romp._romp_init()) +#define A_ROMP_DOWNLOAD(x) A_CMN(romp._romp_download(x)) +#define A_ROMP_DECODE(addr) A_CMN(romp._romp_decode(addr)) +#define A_ROMP_INSTALL() A_CMN(romp._romp_install()) +#else +#define A_ROMP_INIT() +#define A_ROMP_DOWNLOAD(x) +#define A_ROMP_DECODE(addr) +#define A_ROMP_INSTALL() +#endif + +#if SYSTEM_MODULE_WDT + +#define A_WDT_INIT() A_CMN(wdt_timer._wdt_init()) +#define A_WDT_ENABLE() A_CMN(wdt_timer._wdt_enable()) +#define A_WDT_DISABLE() A_CMN(wdt_timer._wdt_disable()) +#define A_WDT_SET(t) A_CMN(wdt_timer._wdt_set(t)) +#define A_WDT_TASK() A_CMN(wdt_timer._wdt_task()) +#define A_WDT_LASTBOOT() A_CMN(wdt_timer._wdt_last_boot()) +#define A_WDT_RESET() A_CMN(wdt_timer._wdt_reset()) + +#else +#define A_WDT_INIT() +#define A_WDT_ENABLE() +#define A_WDT_DISABLE() +#define A_WDT_SET(t) +#define A_WDT_TASK() +#define A_WDT_LASTBOOT() +#define A_WDT_RESET() +#endif + + +#if SYSTEM_MODULE_EEPROM +#define A_EEP_INIT() A_CMN(eep._eep_init()) +#define A_EEP_READ(off, len, buf) A_CMN(eep._eep_read(off, len, buf)) +#define A_EEP_WRITE(off, len, buf) A_CMN(eep._eep_write(off, len, buf)) +#define A_EEP_IS_EXIST() A_CMN(eep._eep_is_exist()) +#else +#define A_EEP_INIT() +#define A_EEP_READ(off, len, buf) +#define A_EEP_WRITE(off, len, buf) +#define A_EEP_IS_EXIST() +#endif + + + +struct _A_os_linkage_check; /* OS-dependent */ + +typedef struct _A_cmnos_indirection_table { + int (* hal_linkage_check)(int sz, struct _A_os_linkage_check *); + unsigned int *start_bss; + void (* app_start)(void); + +#if SYSTEM_MODULE_MEM + struct mem_api mem; +#endif + +#if SYSTEM_MODULE_MISC + struct misc_api misc; +#endif + +#if SYSTEM_MODULE_PRINT + struct printf_api printf; +#endif + +#if SYSTEM_MODULE_UART + struct uart_api uart; +#endif + +//#if SYSTEM_MODULE_DBG +// struct dbg_api dbg; +//#endif + +#if SYSTEM_MODULE_PCI + struct pci_api pci; +#endif + +#if SYSTEM_MODULE_GMAC + struct gmac_api gmac; +#endif + +#if SYSTEM_MODULE_USB + struct usb_api usb; +#endif + +#if SYSTEM_MODULE_CLOCK + struct clock_api clock; +#endif + +#if SYSTEM_MODULE_TIMER + struct timer_api timer; +#endif + +#if SYSTEM_MODULE_INTR + struct intr_api intr; +#endif + +#if SYSTEM_MODULE_ALLOCRAM + struct allocram_api allocram; +#endif + +#if SYSTEM_MODULE_ROM_PATCH + struct romp_api romp; +#endif + +#if SYSTEM_MODULE_WDT + struct wdt_api wdt_timer; +#endif + +#if SYSTEM_MODULE_EEPROM + struct eep_api eep; +#endif + + struct string_api string; + struct tasklet_api tasklet; + +} _A_cmnos_indirection_table_t; + +/* Module installation for cmnos modules */ + +#if SYSTEM_MODULE_MEM +extern void cmnos_mem_module_install(struct mem_api *); +#endif + +#if SYSTEM_MODULE_MISC +extern void cmnos_misc_module_install(struct misc_api *); +#endif + +#if SYSTEM_MODULE_PRINT +extern void cmnos_printf_module_install(struct printf_api *); +#endif + +#if SYSTEM_MODULE_UART +extern void cmnos_uart_module_install(struct uart_api *); +#endif + +//#if SYSTEM_MODULE_DBG +//extern void cmnos_dbg_module_install(struct dbg_api *); +//#endif + +#if SYSTEM_MODULE_USB +extern void cmnos_usb_module_install(struct usb_api *); +#endif + +#if SYSTEM_MODULE_INTR +extern void cmnos_intr_module_install(struct intr_api *); +#endif + +#if SYSTEM_MODULE_CLOCK +extern void cmnos_clock_module_install(struct clock_api *); +#endif + +#if SYSTEM_MODULE_TIMER +extern void cmnos_timer_module_install(struct timer_api *); +#endif + +#if SYSTEM_MODULE_ALLOCRAM +extern void cmnos_allocram_module_install(struct allocram_api *); +#endif + +#if SYSTEM_MODULE_ROM_PATCH +extern void cmnos_romp_module_install(struct romp_api *); +#endif + +#if SYSTEM_MODULE_WDT +extern void cmnos_wdt_module_install(struct wdt_api *); +#endif + +#if SYSTEM_MODULE_EEPROM +extern void cmnos_eep_module_install(struct eep_api *); +#endif + +#if SYSTEM_MODULE_PCI +extern void cmnos_pci_module_install(struct pci_api *); +#endif + +extern void cmnos_tasklet_module_install(struct tasklet_api *); + +extern void cmnos_string_module_install(struct string_api *tbl); + +#endif /* __CMNOS_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/intr/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/intr/Makefile new file mode 100755 index 0000000..98d2b64 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/intr/Makefile @@ -0,0 +1,60 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = intr + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/intr/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/intr/Makefile.ss new file mode 100755 index 0000000..d173391 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/intr/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_intr.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/intr/inc/intr_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/intr/inc/intr_api.h new file mode 100755 index 0000000..3755241 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/intr/inc/intr_api.h @@ -0,0 +1,150 @@ +#ifndef __INTR_API_H__ +#define __INTR_API_H__ + +/* + * Interrupt handler, for application-managed interrupts. + * When an interrupt occurs, it is automatically disabled. + * See A_WMAC_INTR_ATTACH() and A_MBOX_INTR_ATTACH(). + * + * If a handler returns A_HANDLER_DONE, the interrupt is + * re-enabled. The OS calls the handler next time service + * is required. This is the normal case for a handler. + * + * If a handler returns A_HANDLER_YIELD, the interrupt + * remains masked. The handler is called again when + * it is "convenient". This gives the OS an opportunity + * to run other code/handlers. A handler should return + * A_HANDLER_YIELD if it might dominate the CPU for too + * long. + * + * If a handler returns A_HANDLER_NOENABLE, the interrupt + * remains disabled. It is up to the application to re-enable + * the interrupt (via A_*_INTR_UNMASK) when it's appropriate. + * + * Note that many combinations of interrupt functions and + * interrupt vectors are NOT supported: Callers should use + * only the macros defined in cmnos_api.h to access the + * interrupt API. + */ +#include "cmnos_api.h" + +typedef uint32_t A_old_intr_t; + +////////////////////////////////////////////////////////////////// +// this is copied from mercury/cmnos_xtensa.h +/* + * These are CMNOS interrupt manifest constants. + * They have specially-chosen values that align with hardware and or + * operating system values (see cmnos_interrupt_info). + */ +#if defined(__XTENSA__) +/* + * Enumeration of low and medium priority interrupt numbers + * which match the CPU hardware configuration: + */ + +/* XTensa Level 1 interrupt */ +#define A_INUM_SOFTWARE 0 /* currently unused */ + +/* XTensa Level2 interrupts */ +#define A_INUM_XTTIMER 1 /* currently unused */ + +#define A_INUM_TBD_0 2 /* TBD */ +#define A_INUM_CPU_WDT 3 /* RST_CPU watchodg interrupt */ +#define A_INUM_GMAC_DMA 4 /* GMAC DMA interrupt */ +#define A_INUM_GMAC_MDIO 5 /* GMAC MDIO interrupt */ +#define A_INUM_HOST_DMA 6 /* HOST DMA */ +#define A_INUM_CPU_GEN_TIMER 7 /* CPU general timer */ +#define A_INUM_TBD_8 8 /* TBD */ +#define A_INUM_TBD_9 9 /* TBD */ +#define A_INUM_USB_CTRL 10 /* USB core control */ +#define A_INUM_USB_DMA 11 /* USB DMA */ +#define A_INUM_TBD_12 12 /* TBD */ +#define A_INUM_TBD_13 13 /* TBD */ +#define A_INUM_EMUX_CPU 14 /* EMUX CPU */ +#define A_INUM_GPIO_CPU 15 /* GPIO CPU interrupt */ +#define A_INUM_TBD_16 16 /* TBD */ +#define A_INUM_PCIE_CPU 17 /* CPU PCIE interrupt */ +#define A_INUM_RST_CPU_NMI 18 /* RST CPU nmi interrupt */ + +/* Number of interrupts that map directly into CPU/hal interrupt bits. */ +#define NUM_DIRECT_INTR 19 + +#endif +////////////////////////////////////////////////////////////////// + +#define CMNOS_IMASK_XTTIMER (1<_intr_init = cmnos_intr_init; + tbl->_intr_invoke_isr = cmnos_intr_invoke_isr; + tbl->_intr_attach_isr = cmnos_intr_attach_isr; + tbl->_intr_mask_inum = cmnos_intr_mask_inum; + tbl->_intr_unmask_inum = cmnos_intr_unmask_inum; + + /* + * Note: These are all supplied elsewhere with platform-specific functions: + * tbl->_get_intrenable + * tbl->_set_intrenable + * tbl->_get_intrpending + * tbl->_unblock_all_intrlvl + * tbl->_intr_disable + * tbl->_intr_restore + */ +} +#endif /* SYSTEM_MODULE_INTR */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/Makefile new file mode 100755 index 0000000..b3f185b --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = mem + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/Makefile.ss new file mode 100755 index 0000000..3d01df5 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_mem.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/inc/mem_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/inc/mem_api.h new file mode 100755 index 0000000..e3197dc --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/inc/mem_api.h @@ -0,0 +1,10 @@ +#ifndef __MEM_API_H__ +#define __MEM_API_H__ +struct mem_api { + void (* _mem_init)(void); + void *(* _memset)(void *, int, unsigned int); + void *(* _memcpy)(void *, const void *, unsigned int); + void *(* _memmove)(void *, const void *, unsigned int); + int (* _memcmp)(const void *, const void *, unsigned int); +}; +#endif /* __MEM_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/src/cmnos_mem.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/src/cmnos_mem.c new file mode 100755 index 0000000..c9d01fc --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/mem/src/cmnos_mem.c @@ -0,0 +1,30 @@ + +#include "sys_cfg.h" + +#if SYSTEM_MODULE_MEM + +#include "athos_api.h" + +LOCAL void +cmnos_mem_init(void) +{ +} + +/* Memory operations are provided by toolchain libraries. */ + +extern void *memset(void *dest, int val, unsigned int nbyte); +extern void *memcpy(void *dest, const void *src, unsigned int nbyte); +extern void *memmove(void *dest, const void *src, unsigned int nbyte); +extern int memcmp(const void *string1, const void *string2, unsigned int nbyte); + +void +cmnos_mem_module_install(struct mem_api *tbl) +{ + tbl->_mem_init = cmnos_mem_init; + tbl->_memset = memset; + tbl->_memcpy = memcpy; + tbl->_memmove = memmove; + tbl->_memcmp = memcmp; +} +#endif + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/Makefile new file mode 100755 index 0000000..6f27a83 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/Makefile @@ -0,0 +1,62 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = misc + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# + +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/Makefile.ss new file mode 100755 index 0000000..b790dff --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_misc.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/inc/misc_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/inc/misc_api.h new file mode 100755 index 0000000..3b5da6d --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/inc/misc_api.h @@ -0,0 +1,34 @@ +#ifndef __MISC_API_H__ +#define __MISC_API_H__ + +enum hostif_s{ + HIF_USB = 0, + HIF_PCIE, + HIF_GMAC, + HIF_PCI, + + // HIF should be added above here + HIF_NUM, + HIF_NONE + +}; + +typedef enum hostif_s A_HOSTIF; + +struct register_dump_s; + +struct misc_api { + void (* _system_reset)(void); + void (* _mac_reset)(void); + void (* _assfail)(struct register_dump_s *); + void (* _misaligned_load_handler)(struct register_dump_s *); + + void (* _report_failure_to_host)(struct register_dump_s *, int); + int (* _target_id_get)(void); + A_HOSTIF (* _is_host_present)(void); + + uint8_t (*_kbhit)(uint8_t); + + uint16_t (* _rom_version_get)(void); +}; +#endif /* __MISC_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/src/cmnos_misc.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/src/cmnos_misc.c new file mode 100755 index 0000000..d5c0580 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/misc/src/cmnos_misc.c @@ -0,0 +1,248 @@ + +#include "sys_cfg.h" + +#if SYSTEM_MODULE_MISC + +#include "athos_api.h" +#include "regdump.h" + +#if SYSTEM_MODULE_USB +extern uint16_t UsbDeviceDescriptor[]; +#endif + +/* This number gets bumped on each official build. */ +// uint32_t cmnos_target_software_id = AR6K_SW_VERSION; + +/*! + * system reset + */ +LOCAL void +cmnos_system_reset(void) +{ + /* TBD: to be finished */ + /*! + * sytem reset backdoor + */ + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, (0x1<<24)); +} + +#if 0 +/*! + * wdt reset + */ +#LOCAL void cmnos_wdt_reset(void) +{ + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, (0x1<<24)); +} +#endif + +/*! + * mac reset + */ +LOCAL void +cmnos_mac_reset(void) +{ + /* TBD: to be finished */ + /*! + * mac reset backdoor + */ +} + +volatile int assloop = 1; +int assprint = 1; + +//A_COMPILE_TIME_ASSERT(verify_RD_SIZE, (RD_SIZE == sizeof(CPU_exception_frame_t))) + +LOCAL void +cmnos_misaligned_load_handler(struct register_dump_s *dump) +{ + /* TBD: to be finished */ + if (A_IML_IS_ASSERT(dump->badvaddr)) { + /* + * Probably an Intentional Misaligned Load, used to + * signal an assertion failure + */ + dump->assline = A_IML_ASSLINE(dump->badvaddr); + A_ASSFAIL(dump); + } else { + /* A genuine misaligned load */ + A_PRINTF("Misaligned load: pc=0x%x badvaddr=0x%x dump area=0x%x\n", + dump->pc, dump->badvaddr, dump); + dump->assline = 0; + A_ASSFAIL(dump); /* Not really an assertion failure, but we'll treat it similarly. */ + } + + // trigger wdt, in case hang + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR, 0x03); + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_ADDR, 0x10); + + while(1); +} + +struct register_dump_s *current_dump = NULL; + +/*! + * A convenient place to set a breakpoint. + * Whenever an A_ASSERT triggers, it comes here. + */ +LOCAL void +cmnos_assfail(struct register_dump_s *dump) +{ + if (current_dump == NULL ) { + A_UINT32 target_id; + + current_dump = dump; + //A_TARGET_ID_GET(&target_id); + dump->target_id = target_id; + + if (assprint) { + unsigned int i; + + A_PRINTF("assertion failed? pc=0x%x, line=%d, dump area=0x%x\n", + dump->pc, dump->assline, dump); +// INF_DBG2_LOG(INF_ASSERTION_FAILED, dump->pc, +// A_IML_ASSLINE(dump->badvaddr)); +// INF_DBG1_LOG(INF_ASSERTION_FAILED, (A_UINT32)dump); + + A_PRINTF("Target ID: 0x%x (%d)\n", target_id, target_id); +// INF_DBG1_LOG(INF_TARGET_ID, target_id); + + A_PRINTF("Debug Info:"); + for (i=0; i<(sizeof(struct register_dump_s)/sizeof(A_UINT32)); i++) { + if ((i%4) == 0) { + A_PRINTF("\n"); + } + A_PRINTF("0x%08x ", ((A_UINT32 *)dump)[i]); +// INF_DBG1_LOG(INF_ASSERTION_FAILED, ((A_UINT32 *)dump)[i]); + } + A_PRINTF("\n"); + } + } else { + /* + * We must have assfail'ed again while processing the first assfail. + * Don't try to print anything -- keep it very simple. + */ + + } +} + +/*! + * failure state report + */ +LOCAL void +cmnos_report_failure_to_host(struct register_dump_s *dump, int len) +{ + /* TBD: to be removed! */ +} + +/*! + * get target id + */ +LOCAL int +cmnos_target_id_get(void) +{ + /* TBD: to be removed! */ +} + +/*! + * get keyboard hit with delay + */ +LOCAL uint8_t +cmnos_get_kbhit(uint8_t delay) +{ + uint32_t last_ccount; + uint8_t kbhit; + + last_ccount = xthal_get_ccount(); + while (1) + { + if( A_GETC(&kbhit) != 0 ) + break; + + if((xthal_get_ccount() - last_ccount)>=delay*1000*ONE_MSEC) + { + break; + } + } + + return kbhit; +} + +/*! + * host alive & return the hostif type + */ +LOCAL A_HOSTIF +cmnos_is_host_present(void) +{ + /*! + * TODO: check the hostif and return the type of host interface + */ + A_HOSTIF mHif = HIF_USB; +#if defined(PROJECT_K2) + A_PRINTF("5. usb only!!\n"); + return mHif; +#elif defined(PROJECT_MAGPIE) + uint32_t mData; + + mData = MAGPIE_REG_RST_BOOTSTRAP; + + //@RYAN@TODO - this one is somehow not working on L5, need to turn on!!! +#if 1 + /* 4:3 of BOOTSTRAP could distinguish the host interfce + * + * 2'b11 -> gmac + * 2'b10 -> pci + * 2'b01 -> pcie + * 2'b00 -> usb + * + */ + if( mData & BIT3 ) + { + if ( mData & BIT2 ) + mHif = HIF_GMAC; + else + mHif = HIF_PCI; + } + else + { + if ( mData & BIT2 ) + mHif = HIF_PCIE; + else + mHif = HIF_USB; + } +#endif + //A_PRINTF("5. hif (0x%08x) is read!!\n", mData); + return mHif; +#endif +} + +/*! + * get ROM code version + */ +LOCAL uint16_t +cmnos_rom_version_get(void) +{ +#if SYSTEM_MODULE_USB + /* USB Device Descriptor : byte 12, 13 Device BCD -> Device release number in binary-coded decimal. */ + return UsbDeviceDescriptor[6]; +#else + return 0; +#endif +} + +void +cmnos_misc_module_install(struct misc_api *tbl) +{ + tbl->_system_reset = cmnos_system_reset; + tbl->_mac_reset = cmnos_mac_reset; + tbl->_assfail = cmnos_assfail; + tbl->_misaligned_load_handler= cmnos_misaligned_load_handler; + tbl->_report_failure_to_host = cmnos_report_failure_to_host; + //tbl->_target_id_get = cmnos_target_id_get; + tbl->_is_host_present = cmnos_is_host_present; + tbl->_kbhit = cmnos_get_kbhit; + tbl->_rom_version_get = cmnos_rom_version_get; +} + +#endif + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/Makefile new file mode 100755 index 0000000..bf34f4e --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = printf + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/Makefile.ss new file mode 100755 index 0000000..ad186f2 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_printf.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/inc/printf_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/inc/printf_api.h new file mode 100755 index 0000000..afcb837 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/inc/printf_api.h @@ -0,0 +1,15 @@ +#ifndef __PRINTF_API_H__ +#define __PRINTF_API_H__ + +struct printf_api { + void (* _printf_init)(void); + int (* _printf)(const char * fmt, ...); +}; + +/* NB: The printf module requires the serial module. */ +void cmnos_printf_module_install(struct printf_api *tbl); +int cmnos_printf(const char *fmt, ...); + + + +#endif /* __PRINTF_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/src/cmnos_printf.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/src/cmnos_printf.c new file mode 100755 index 0000000..0737e02 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/printf/src/cmnos_printf.c @@ -0,0 +1,322 @@ +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### + +#include "dt_defs.h" +#include "sys_cfg.h" + +#if SYSTEM_MODULE_PRINT + +#include "athos_api.h" + +#define is_digit(c) ((c >= '0') && (c <= '9')) + +#if defined(__GNUC__) && defined(__mips__) +#define va_list __builtin_va_list +#define va_arg __builtin_va_arg +#define va_start __builtin_va_start +#define va_end __builtin_va_end +#define va_copy __builtin_va_copy +#endif + +#if defined(__XCC__) +#include "stdarg.h" +#define va_list __gnuc_va_list +#endif + +void +cmnos_write_char(char c) +{ + if (c == '\n') { + A_PUTC('\r'); + A_PUTC('\n'); + } else if (c == '\r') { + } else { + A_PUTC(c); + } +} + +void (*_putc)(char c) = cmnos_write_char; + +static int _cvt(unsigned long val, char *buf, long radix, char *digits) +{ + char temp[80]; + char *cp = temp; + int length = 0; + + if (val == 0) { + /* Special case */ + *cp++ = '0'; + } else { + while (val) { + *cp++ = digits[val % radix]; + val /= radix; + } + } + while (cp != temp) { + *buf++ = *--cp; + length++; + } + *buf = '\0'; + return (length); +} + + +static int cmnos_vprintf(void (*putc)(char c), const char *fmt, va_list ap) +{ + char buf[sizeof(long)*8]; + char c, sign, *cp=buf; + int left_prec, right_prec, zero_fill, pad, pad_on_right, + i, islong, islonglong; + long val = 0; + int res = 0, length = 0; + + while ((c = *fmt++) != '\0') { + if (c == '%') { + c = *fmt++; + left_prec = right_prec = pad_on_right = islong = islonglong = 0; + if (c == '-') { + c = *fmt++; + pad_on_right++; + } + if (c == '0') { + zero_fill = TRUE; + c = *fmt++; + } else { + zero_fill = FALSE; + } + while (is_digit(c)) { + left_prec = (left_prec * 10) + (c - '0'); + c = *fmt++; + } + if (c == '.') { + c = *fmt++; + zero_fill++; + while (is_digit(c)) { + right_prec = (right_prec * 10) + (c - '0'); + c = *fmt++; + } + } else { + right_prec = left_prec; + } + sign = '\0'; + if (c == 'l') { + // 'long' qualifier + c = *fmt++; + islong = 1; + if (c == 'l') { + // long long qualifier + c = *fmt++; + islonglong = 1; + } + } + // Fetch value [numeric descriptors only] + switch (c) { + case 'p': + islong = 1; + case 'd': + case 'D': + case 'x': + case 'X': + case 'u': + case 'U': + case 'b': + case 'B': + if (islonglong) { + val = va_arg(ap, long); + } else if (islong) { + val = (long)va_arg(ap, long); + } else{ + val = (long)va_arg(ap, int); + } + if ((c == 'd') || (c == 'D')) { + if (val < 0) { + sign = '-'; + val = -val; + } + } else { + // Mask to unsigned, sized quantity + if (islong) { + val &= ((long)1 << (sizeof(long) * 8)) - 1; + } else{ + val &= ((long)1 << (sizeof(int) * 8)) - 1; + } + } + break; + default: + break; + } + // Process output + switch (c) { + case 'p': // Pointer + (*putc)('0'); + (*putc)('x'); + zero_fill = TRUE; + left_prec = sizeof(unsigned long)*2; + case 'd': + case 'D': + case 'u': + case 'U': + case 'x': + case 'X': + switch (c) { + case 'd': + case 'D': + case 'u': + case 'U': + length = _cvt(val, buf, 10, "0123456789"); + break; + case 'p': + case 'x': + length = _cvt(val, buf, 16, "0123456789abcdef"); + break; + case 'X': + length = _cvt(val, buf, 16, "0123456789ABCDEF"); + break; + } + cp = buf; + break; + case 's': + case 'S': + cp = va_arg(ap, char *); + if (cp == NULL) { + cp = ""; + } + length = 0; + while (cp[length] != '\0') length++; + break; + case 'c': + case 'C': + c = va_arg(ap, int /*char*/); + (*putc)(c); + res++; + continue; + case 'b': + case 'B': + length = left_prec; + if (left_prec == 0) { + if (islonglong) + length = sizeof(long)*8; + else if (islong) + length = sizeof(long)*8; + else + length = sizeof(int)*8; + } + for (i = 0; i < length-1; i++) { + buf[i] = ((val & ((long)1< 0) { + (*putc)(c); + res++; + } + } + if (sign != '\0') { + (*putc)(sign); + res++; + } + while (length-- > 0) { + c = *cp++; + (*putc)(c); + res++; + } + if (pad_on_right) { + while (pad-- > 0) { + (*putc)(' '); + res++; + } + } + } else { + (*putc)(c); + res++; + } + } + return (res); +} + +int cmnos_printf(const char *fmt, ...) +{ + va_list ap; + int ret; + + va_start(ap, fmt); + + //if (A_SERIAL_ENABLED()) { + if (1) { + ret = cmnos_vprintf(_putc, fmt, ap); + } else { + ret = 0; + } + + va_end(ap); + + return (ret); +} + +void +cmnos_printf_init(void) +{ +} + +void cmnos_printf_module_install(struct printf_api *tbl) +{ + tbl->_printf_init = cmnos_printf_init; + tbl->_printf = cmnos_printf; +} + +#endif /* SYSTEM_MODULE_PRINT */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/Makefile new file mode 100755 index 0000000..ea61668 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = rompatch + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/Makefile.ss new file mode 100755 index 0000000..0b04a1f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_rompatch.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/inc/romp_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/inc/romp_api.h new file mode 100755 index 0000000..ee476f3 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/inc/romp_api.h @@ -0,0 +1,48 @@ +/*************************************************************************/ +/* Copyright (c) 2008 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : romp_api.h */ +/* */ +/* Abstract */ +/* This file contains definition of data structure and interface */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _ROMP_API_H_ +#define _ROMP_API_H_ + +#include "dt_defs.h" + +/******** hardware API table structure (API descriptions below) *************/ +struct romp_api { + void (*_romp_init)(void); + BOOLEAN (*_romp_download)(uint16_t ); + BOOLEAN (*_romp_install)(void); + BOOLEAN (*_romp_decode)(uint32_t ); +}; + +#define _ROMP_MAGIC_ "[PaTcH]" + +struct rom_patch_st { + uint16_t crc16; // crc filed to maintain the integrity + uint16_t len; // length of the patch code + uint32_t ld_addr; // load address of the patch code + uint32_t fun_addr; // entry address of the patch code + uint8_t *pfun; // patch code +}; + + +struct eep_redir_addr { + uint16_t offset; + uint16_t size; +}; + + +/************************* EXPORT function ***************************/ +uint16_t cal_crc16(uint32_t sz, uint8_t *p); + +#endif // end of _UART_API_H_ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/src/cmnos_rompatch.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/src/cmnos_rompatch.c new file mode 100755 index 0000000..79d59f1 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/rompatch/src/cmnos_rompatch.c @@ -0,0 +1,249 @@ +/*************************************************************************/ +/* Copyright (c) 2008 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : cmnos_rompatch.c */ +/* */ +/* Abstract */ +/* This file contains rom code patch mechanism, patch code is */ +/* offline generated, and replace the indirect table function as we */ +/* need to patch. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#include "sys_cfg.h" + +#include "athos_api.h" + +#if SYSTEM_MODULE_ROM_PATCH + + +LOCAL BOOLEAN _patch_dump( struct rom_patch_st *patch); +LOCAL BOOLEAN _read_rom_patch(struct rom_patch_st *patch); + + +// the patch install entry +void (*patch_start)(void); + +// the eep redirect addr +struct eep_redir_addr patch_addr = {0x0, 0x0}; + + +LOCAL +BOOLEAN _patch_dump( struct rom_patch_st *patch) +{ +// A_PRINTF("\tCRC: 0x%04x\n\r", patch->crc16); + A_PRINTF("\tsize: %d bytes\n\r", patch->len); + A_PRINTF("\tld_addr: 0x%08x\n\r", (uint32_t)patch->ld_addr); + A_PRINTF("\tfun_addr: 0x%08x\n\r", (uint32_t)patch->fun_addr); +} + + + +LOCAL +BOOLEAN _read_rom_patch(struct rom_patch_st *patch) +{ + BOOLEAN retVal = FALSE; + uint8_t *addr; + uint16_t i; + uint8_t *buf = ((uint8_t*)(patch)+(sizeof(struct rom_patch_st)-4)); //assign the patch code buffer, last 4 bytes is the data + + /*! assign the load address of the patch + * + * - convert the address to dport address 0x4exxxx or 0x5xxxxx + */ + //addr = (uint32_t *)((patch->ld_addr&(~0xc00000))|(0x400000)); + addr = (uint8_t *)(patch->ld_addr); + if( (uint32_t)addr < SYS_D_RAM_REGION_0_BASE || (uint32_t)addr >= (SYS_D_RAM_REGION_0_BASE + SYS_RAM_SZIE) ) + { + A_PRINTF("!address should be dport in ram's address, 0x%08x\n\r", (uint32_t)addr); + goto ERR_DONE; + } + + _patch_dump(patch); + + A_PRINTF("copy %d bytes from 0x%08x to 0x%08x", patch->len, (uint32_t)buf, (uint32_t)addr); + for(i=0; ilen; i+=4) // word access + { + addr[i+3] = buf[i]; + addr[i+2] = buf[i+1]; + addr[i+1] = buf[i+2]; + addr[i] = buf[i+3]; + } + + retVal = TRUE; +ERR_DONE: + return retVal; + +} + + +/*! + * decode and parse the rompatch code + * + * addr: the buffer in ram stored the downloaded buffer + */ +LOCAL +BOOLEAN cmnos_romp_decode(uint32_t addr) +{ + int i; + BOOLEAN retVal = FALSE; + struct rom_patch_st *patch; + uint8_t *func_addr; + + A_PRINTF("[%s+]\n\r", __FUNCTION__ ); + { + /* + * check the integrity of the buffer + */ + uint32_t *mData = (uint32_t *)addr; + uint32_t CheckSum = 0; + + // size at here is a half-word based, divide by 2 set it to a word + for(i=0; i<(patch_addr.size/2); i++, mData++) + CheckSum = CheckSum ^ *mData; + + A_PRINTF("CheckSum: 0x%08x\n\r", CheckSum); + + if( CheckSum != 0 ) + goto ERR_DONE; + + /*********************************************/ + + patch = (struct rom_patch_st *)addr; + + func_addr = (uint8_t *)patch->fun_addr; + + if( _read_rom_patch(patch) ) + { + //A_PRINTF("\n\r patch to 0x%08x, func at 0x%08x\n\r", (uint32_t)patch->ld_addr, (uint32_t)func_addr); + + // the patch function entry, call install later + patch_start = (void *)func_addr; + + // install the patch here + //patch_start(); + } + else + { + A_PRINTF("patch decode fail!\n\r"); + goto ERR_DONE; + } + } + + retVal = TRUE; + +ERR_DONE: + A_PRINTF("[%s-]\n\r", __FUNCTION__ ); + + return retVal; + // + // if crc checking is ok, move code the where it belong according to it's ld_addr + // + +} + + +/*! + * install + */ +LOCAL BOOLEAN cmnos_romp_install(void) +{ + /* TBD: to be removed! */ + + /*! call the patch function, + * + * - left the patch install did by the patch code, + * so that we sould build the patch code with entry function is the install process + * e.g void install_patch(void), which update the function table + */ + + //A_PRINTF("[%s+]\n\r", __FUNCTION__); + patch_start(); + //A_PRINTF("[%s-]\n\r", __FUNCTION__); +} + +/*! + * download + * + * offset: the offset of the eeprom redirect header(offset, size) + * + */ +LOCAL BOOLEAN cmnos_romp_download(uint16_t offset) +{ + BOOLEAN retVal = FALSE; + uint16_t buf[2]; + + uint16_t eep_start_ofst = EEPROM_START_OFFSET; + uint16_t eep_end_ofst = EEPROM_END_OFFSET; + + A_PRINTF("[%s+]\n\r", __FUNCTION__ ); + + /* TBD: to be removed! */ + /* read the patch from EEPROM, if there is an EEPROM exist and patch code stored inside */ + + /* + * 1. read the fixed offset address of 0xfc and find the exactly patch code is + * 2. read the patch code from eeprom and write to buffer ram + * ------------------- leave it to decode operation ------------------ + * 3. and check the integrity of it, if the integrity is ok, goto 4 + * 4. decode the patch pack and decode each patch code and write them to the RAM + * + */ + + /* + * read the eep redirect(offset, size) from the offset + */ + if( RET_SUCCESS != A_EEP_READ(offset, sizeof(struct eep_redir_addr)/sizeof(uint16_t), buf) ) + goto ERR_DONE; + + A_PRINTF("patch.offset: 0x%04x, patch.size : 0x%04x\n\r", buf[0], buf[1]); + + patch_addr.offset = buf[0]; + patch_addr.size = buf[1]; + + // ATHR : 0x41544852, ((uint32_t)patch_addr == 0x41544852) || + // size == 0, offset > 0x3fff or offset < 0x2000, eeprom offset is between 0x2000~0x3fff + if( (patch_addr.size == 0x0) ||(patch_addr.offset < eep_start_ofst ) \ + || (patch_addr.offset > eep_end_ofst) || ((patch_addr.offset+patch_addr.size) > eep_end_ofst)) + goto ERR_DONE; + + // read the patch code to ROM_PATCH_BUF_ADDR: 0x51E000, + A_EEP_READ(patch_addr.offset, patch_addr.size, (uint16_t *)ROM_PATCH_BUF_ADDR); + + if( A_ROMP_DECODE(ROM_PATCH_BUF_ADDR) ) + { + A_ROMP_INSTALL(); + } + else + goto ERR_DONE; + + retVal = TRUE; +ERR_DONE: + A_PRINTF("[%s-]\n\r", __FUNCTION__ ); + return retVal; + +} + +/*! + * init + */ +LOCAL void cmnos_romp_init(void) +{ + /* TBD: to be removed! */ + //A_PRINTF("CMNOS_ROMP_INIT!\n\r"); +} + +void +cmnos_romp_module_install(struct romp_api *tbl) +{ + tbl->_romp_init = cmnos_romp_init; + tbl->_romp_download = cmnos_romp_download; + tbl->_romp_install = cmnos_romp_install; + tbl->_romp_decode = cmnos_romp_decode; + +} + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/Makefile new file mode 100755 index 0000000..3ac132e --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = sflash + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/Makefile.ss new file mode 100755 index 0000000..446054b --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_sflash.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/inc/sflash_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/inc/sflash_api.h new file mode 100755 index 0000000..e6d21a8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/inc/sflash_api.h @@ -0,0 +1,24 @@ +#ifndef __SFLASH_API_H__ +#define __SFLASH_API_H__ + +/* Constant definition */ +#define ZM_SFLASH_SECTOR_ERASE 1 +#define ZM_SFLASH_BLOCK_ERASE 2 +#define ZM_SFLASH_CHIP_ERASE 0 + +/*!- interface of eeprom access + * + */ +struct sflash_api { + /* Indispensable functions */ + void (* _sflash_init)(void); + void (* _sflash_erase)(A_UINT32 erase_type, A_UINT32 addr); /* 1. erase_type : chip/block/sector, 2. addr : no use for chip erase */ + void (* _sflash_program)(A_UINT32 addr, A_UINT32 len, A_UINT8 *buf); /* 1. addr : spi flash address(start from 0x0), 2. len : bite number to write , 3. *buf : source memory address */ + void (* _sflash_read)(A_UINT32 fast, A_UINT32 addr, A_UINT32 len, A_UINT8 *buf); /* 1. fast : 1 for fast read, 0 for read, 2. addr : spi flash address(start from 0x0), 3. len : bite number to read , 3. *buf : destination memory address */ + + /* Dispensable functions */ + A_UINT32 (* _sflash_rdsr)(void); /* return the value of status register */ +}; + +#endif /* __SFLASH_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/src/cmnos_sflash.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/src/cmnos_sflash.c new file mode 100755 index 0000000..01a7067 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/sflash/src/cmnos_sflash.c @@ -0,0 +1,600 @@ +#include "sys_cfg.h" +#include "athos_api.h" + +#if SYSTEM_MODULE_SFLASH + +#include "reg_defs.h" +#include "sflash_api.h" + +/******************************************* + * Definitions of module internal constant * + *******************************************/ + +/* Definitions of base address and Flash sise -> Project dependent */ +#define ZM_SPI_REGISTER_BASE SPI_REG_BASE_ADDRESS /* 0x0005B000 */ +#define ZM_SPI_FLASH_BASE SPI_FLASH_BASE /* 0x0F000000 */ +#define ZM_SPI_FLASH_MAX_ADDR SPI_FLASH_MAX_ADDR /* 0x0FFFFFFF */ +#define ZM_SPI_FLASH_MAX_SIZE SPI_FLASH_MAX_SIZE /* 0x01000000 */ + +/* + * Base address of Clock and Reset Control Registers is 0x00050000 + * Offset of Clock Control Register is 0x40 + * SPI_SEL (bit 8) : Switch the function of I/O pin 19~22 between GPIO and SPI. + * 0 -> act as GPIO5~8; + * 1 -> act as SPI pins. + */ +#define ZM_SPI_CLK_CTRL_ADDR 0x00050040 +#define ZM_SPI_SPI_SEL_BIT 0x100 + +/* Definitions of Serial Flash constants -> According to standard or vendor dependent */ +#define ZM_SFLASH_PAGE_SIZE 256 + +/* Definitions of OP Code -> According to standard or vendor dependent */ +#define ZM_SFLASH_OP_READ 0x03 /* Read Data Bytes */ +#define ZM_SFLASH_OP_FAST_READ 0x0B /* Read Data Bytes at Higher Speed */ +/* + * For MXIC, sector erase : Command 0x20, size 4K bytes + * block erase : Command 0xD8, size 64K bytes + * chip earse : command 0x60 or 0xC7 + * For Spansion, sector erase : Command 0x20 or 0xD8, size 64K bytes (For 64 KB sector devices, either command is valid and performs the same function.) + * block erase : Command 0xD8, size 256K bytes + * chip earse : command 0x60 or 0xC7, Uniform 64 KB Sector Product (For 64 KB sector devices, either command is valid and performs the same function.) + * 0xC7, Uniform 256 KB Sector Product + */ +#define ZM_SFLASH_OP_SE 0x20 /* Sector Erase */ +#define ZM_SFLASH_OP_BE 0xD8 /* Block Erase */ +#define ZM_SFLASH_OP_CE 0xC7 /* Chip Erase */ +#define ZM_SFLASH_OP_PP 0x02 /* Page Program */ +#define ZM_SFLASH_OP_RDSR 0x05 /* Read from Status Register */ +#define ZM_SFLASH_OP_WRSR 0x01 /* Write to Status Register */ +#define ZM_SFLASH_OP_WREN 0x06 /* Write Enable */ +#define ZM_SFLASH_OP_WRDI 0x04 /* Write Disable */ +#define ZM_SFLASH_OP_RDID 0x9F /* Read Identification */ +#define ZM_SFLASH_OP_DP 0xB9 /* Deep Power Down */ +#define ZM_SFLASH_OP_RES 0xAB /* Release from Deep Power Down, Release from Deep Power Down and Read Electronic Signature */ + +/* Definitions of Status Register -> According to standard or vendor dependent */ +/* Write in progress bit + * 1 = Device Busy. A Write Status Register, program, or erase operation is in progress + * 0 = Ready. Device is in standby mode and can accept commands. + */ +#define ZM_SFLASH_STATUS_REG_WIP (1<<0) +/* Write enable latch bit + * 1 = Device accepts Write Status Register, program, or erase commands + * 0 = Ignores Write Status Register, program, or erase commands + */ +#define ZM_SFLASH_STATUS_REG_WEL (1<<1) +/* Status register write disable bit + * 1 = Protects when WP#/ACC is low + * 0 = No protection, even when WP#/ACC is low + */ +#define ZM_SFLASH_STATUS_REG_SRWD (1<<7) + +/* Definitions of SPI Flash Controller -> SPI Flash Controller dependent */ +/* SPI Flash Controller used in K2 project is part of Falcon's "Driver Support Logic" (DSL) block */ +/* + * Offset Register + * ====== ========================================================== + * 0x0000 SPI control/status register (SPI_CS) + * 0x0004 SPI address/opcode register (SPI_AO) + * 0x0008 SPI data register (SPI_D) + */ + +/* + * SPI control/status register (SPI_CS) + * Access: R/W + * Cold reset: (See field descriptions) + * Warm reset: (Same as cold reset) + * Notes: + * + * 3:0 - Transmit byte count. Determines the number of bytes + * transmitted from Falcon to the SPI device. Values of 1-8 are + * valid; other values are illegal. See the 'Notes' section below + * for details on how to use this field. Resets to an undefined + * value. + * 7:4 - Receive byte count. Determines the number of bytes received + * from the SPI device into Falcon. Values of 0-8 are valid; + * other values are illegal. See the 'Notes' section below for + * details on how to use this field. Resets to an undefined + * value. + * 8 - SPI transaction start. Only writes to this field are + * meaningful; reads always return 0. Resets to 0x0. For writes: + * * A write of '1' starts the SPI transaction defined by the + * transmit byte count, receive byte count, SPI_AO, and SPI_D + * registers. + * * A write of '0' has no effect + * 9 - SPI chip select 1 enable. Resets to 0x0. See bug 12540. + * 0 - SP0 is enabled and SP1 is forced inactive. + * 1 - SP1 is enabled and SP0 is forced inactive. + * 15:10 - Reserved + * 16 - Transaction busy indication. Read-only; writes to this bit are + * ignored. Resets to 0x0. + * 0 - No SPI transaction is ongoing. Software may start a new + * SPI transaction by writing to the 'SPI transaction start' + * bit within this register. + * 1 - An SPI transaction presently is underway. Software must + * not try to start a new SPI transaction, nor may software + * alter the value of any field of the SPI_CS, SPI_AO, or + * SPI_D registers. + * 18:17 - Automatically-determined SPI address size. Read-only; writes + * to this bit are ignored. Resets to an undefined value, but + * then is updated after the autosizing process completes. + * 0 - SPI address size was determined to be 16 bits + * 1 - SPI address size was determined to be 24 bits + * 2 - Reserved + * 3 - Automatic SPI address size determination failed. Typical + * causes of this result: + * * The SPI device is missing + * * The SPI device is unprogrammed + * * The SPI device is programmed with an incorrect + * SPI_MAGIC value + * 20:19 - SPI autosize override. Resets to 0x0. + * 0 - Use automatically-determined SPI address size (see bits + * [18:17] of this register) + * 1 - Force SPI address size to 16 bits + * 2 - Force SPI address size to 24 bits + * 3 - Reserved + * 31:21 - Reserved + */ + +#define SPI_CS_ADDRESS MAGPIE_REG_SPI_CS_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000000) +/* 3:0 - Transmit byte count, values of 1-8 are valid */ +#define SPI_CS_TXBCNT_MSB 3 +#define SPI_CS_TXBCNT_LSB 0 +#define SPI_CS_TXBCNT_MASK 0x0000000f +#define SPI_CS_TXBCNT_GET(x) (((x) & SPI_CS_TXBCNT_MASK) >> SPI_CS_TXBCNT_LSB) +#define SPI_CS_TXBCNT_SET(x) (((0x0 | (x)) << SPI_CS_TXBCNT_LSB) & SPI_CS_TXBCNT_MASK) + +/* 7:4 - Receive byte count, values of 1-8 are valid */ +#define SPI_CS_RXBCNT_MSB 7 +#define SPI_CS_RXBCNT_LSB 4 +#define SPI_CS_RXBCNT_MASK 0x000000f0 +#define SPI_CS_RXBCNT_GET(x) (((x) & SPI_CS_RXBCNT_MASK) >> SPI_CS_RXBCNT_LSB) +#define SPI_CS_RXBCNT_SET(x) (((0x0 | (x)) << SPI_CS_RXBCNT_LSB) & SPI_CS_RXBCNT_MASK) + +/* 8 - SPI transaction start */ +#define SPI_CS_XCNSTART_MSB 8 +#define SPI_CS_XCNSTART_LSB 8 +#define SPI_CS_XCNSTART_MASK 0x00000100 +#define SPI_CS_XCNSTART_GET(x) 0x0 +#define SPI_CS_XCNSTART_SET(x) (((0x0 | (x)) << SPI_CS_XCNSTART_LSB) & SPI_CS_XCNSTART_MASK) +#define SPI_CS_XCNSTART_RESET 0x0 + +/* 9 - SPI chip select */ +#define SPI_CS_CS_MSB 9 +#define SPI_CS_CS_LSB 9 +#define SPI_CS_CS_MASK 0x00000200 +#define SPI_CS_CS_GET(x) (((x) & SPI_CS_CS_MASK) >> SPI_CS_CS_LSB) +#define SPI_CS_CS_SET(x) (((0x0 | (x)) << SPI_CS_CS_LSB) & SPI_CS_CS_MASK) +#define SPI_CS_CS_RESET 0x0 + +/* 16 - Transaction busy indication */ +#define SPI_CS_BUSY_MSB 16 +#define SPI_CS_BUSY_LSB 16 +#define SPI_CS_BUSY_MASK 0x00010000 +#define SPI_CS_BUSY_GET(x) (((x) & SPI_CS_BUSY_MASK) >> SPI_CS_BUSY_LSB) +#define SPI_CS_BUSY_SET(x) (((0x0 | (x)) << SPI_CS_BUSY_LSB) & SPI_CS_BUSY_MASK) +#define SPI_CS_BUSY_RESET 0x0 + +/* 18:17 - Automatically-determined SPI address size */ +#define SPI_CS_AUTOSIZ_MSB 18 +#define SPI_CS_AUTOSIZ_LSB 17 +#define SPI_CS_AUTOSIZ_MASK 0x00060000 +#define SPI_CS_AUTOSIZ_GET(x) (((x) & SPI_CS_AUTOSIZ_MASK) >> SPI_CS_AUTOSIZ_LSB) +#define SPI_CS_AUTOSIZ_SET(x) (((0x0 | (x)) << SPI_CS_AUTOSIZ_LSB) & SPI_CS_AUTOSIZ_MASK) + +/* 20:19 - SPI autosize override */ +#define SPI_CS_AUTOSIZ_OVR_MSB 20 +#define SPI_CS_AUTOSIZ_OVR_LSB 19 +#define SPI_CS_AUTOSIZ_OVR_MASK 0x00180000 +#define SPI_CS_AUTOSIZ_OVR_GET(x) (((x) & SPI_CS_AUTOSIZ_OVR_MASK) >> SPI_CS_AUTOSIZ_OVR_LSB) +#define SPI_CS_AUTOSIZ_OVR_SET(x) (((0x0 | (x)) << SPI_CS_AUTOSIZ_OVR_LSB) & SPI_CS_AUTOSIZ_OVR_MASK) +#define SPI_CS_AUTOSIZ_OVR_RESET 0x0 + +#define SPI_CS_RESET (0x0 | \ + SPI_CS_AUTOSIZ_OVR_SET(SPI_CS_AUTOSIZ_OVR_RESET) | \ + SPI_CS_BUSY_SET(SPI_CS_BUSY_RESET) | \ + SPI_CS_CS_SET(SPI_CS_CS_RESET) | \ + SPI_CS_XCNSTART_SET(SPI_CS_XCNSTART_RESET)) + +/* + * SPI address/opcode register (SPI_AO) + * Access: R/W + * Cold reset: (See field descriptions) + * Warm reset: (Same as cold reset) + * Notes: + * + * 7:0 - SPI opcode. Usually this field specifies the 8-bit opcode + * (aka "instruction") to transmit to the SPI device as the first + * part of an SPI transaction. See the 'Notes' section below for + * more details. Resets to an undefined value. + * 31:8 - Address. Usually this field specifies the 24-bit address to + * transmit to the SPI device. See the 'Notes' section below for + * more details. Resets to an undefined value. + */ + +#define SPI_AO_ADDRESS MAGPIE_REG_SPI_AO_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000004) +/* 7:0 - SPI opcode */ +#define SPI_AO_OPC_MSB 7 +#define SPI_AO_OPC_LSB 0 +#define SPI_AO_OPC_MASK 0x000000ff +#define SPI_AO_OPC_GET(x) (((x) & SPI_AO_OPC_MASK) >> SPI_AO_OPC_LSB) +#define SPI_AO_OPC_SET(x) (((0x0 | (x)) << SPI_AO_OPC_LSB) & SPI_AO_OPC_MASK) +/* 31:8 - Address */ +#define SPI_AO_ADDR_MSB 31 +#define SPI_AO_ADDR_LSB 8 +#define SPI_AO_ADDR_MASK 0xffffff00 +#define SPI_AO_ADDR_GET(x) (((x) & SPI_AO_ADDR_MASK) >> SPI_AO_ADDR_LSB) +#define SPI_AO_ADDR_SET(x) (((0x0 | (x)) << SPI_AO_ADDR_LSB)& SPI_AO_ADDR_MASK) + +/* + * SPI data register (SPI_D) + * Access: R/W + * Cold reset: (See field descriptions) + * Warm reset: (Same as cold reset) + * Notes: + * + * 31:0 - SPI data. Usually this register specifies a series of up to + * four data bytes to transmit to or receive from the SPI device. + * See the 'Notes' section below for more details. Resets to an + * undefined value. + */ + +#define SPI_D_ADDRESS MAGPIE_REG_SPI_D_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000008) +/* 31:0 - SPI data */ +#define SPI_D_DATA_MSB 31 +#define SPI_D_DATA_LSB 0 +#define SPI_D_DATA_MASK 0xffffffff +#define SPI_D_DATA_GET(x) (((x) & SPI_D_DATA_MASK) >> SPI_D_DATA_LSB) +#define SPI_D_DATA_SET(x) (((0x0 | (x)) << SPI_D_DATA_LSB) & SPI_D_DATA_MASK) + +/* + * SPI clock division register (SPI_CLKDIV) + * Access: R/W + * Cold reset: (See field descriptions) + * Warm reset: (Same as cold reset) + * Notes: + * + * 17:16 - 0b00(fastest), 0b01, 0b10, 0b11(slowest) + */ +#define SPI_CLKDIV_ADDRESS MAGPIE_REG_SPI_CLKDIV_ADDR //SPI_BASE_ADDRESS + 0x0000001c +#define SPI_CLKDIV_MSB 17 +#define SPI_CLKDIV_LSB 16 +#define SPI_CLKDIV_MASK 0x00030000 +#define SPI_CLKDIV_GET(x) (((x) & SPI_CLKDIV_MASK) >> SPI_CLKDIV_LSB) +#define SPI_CLKDIV_SET(x) (((0x0 | (x)) << SPI_CLKDIV_LSB) & SPI_CLKDIV_MASK) // read-then-write +#define SPI_CLKDIV_RESET 0x3 + +/* + * Notes + * ----- + * * Background + * An SPI transaction consists of three phases: an opcode transmit + * phase (always a single byte), followed by an optional address + * transmit phase of 0-3 bytes, followed by an optional data transmit + * or receive phase of 0-4 bytes. + * + * Combined, then, an SPI transaction consists of a 1- to 8-byte + * transmit phase from Falcon to the SPI device, followed by a 0- to + * 8-byte receive phase from the SPI device into Falcon. + * + * The 'transmit byte count' field in the SPI_CS register controls the + * size (number of bytes) of the transmit phase. The source of each + * of the bytes transmitted is fixed: + * + * Byte Source + * ---- ----------------------------------------------------------- + * 0 SPI_AO[7:0] (the 'SPI opcode' field) + * 1 SPI_AO[31:24] (the high byte of the 'SPI address' field) + * 2 SPI_AO[23:16] (the middle byte of the 'SPI address' field) + * 3 SPI_AO[15:8] (the low byte of the 'SPI address' field) + * 4 SPI_D[7:0] (the low byte of the 'SPI data' register) + * 5 SPI_D[15:8] (the next byte of the 'SPI data' register) + * 6 SPI_D[23:16] (the next byte of the 'SPI data' register) + * 7 SPI_D[31:24] (the high byte of the 'SPI data' register) + * + * + * The 'receive byte count' field in the SPI_CS register controls the + * size (number of bytes) of the receive phase. The destination of + * each of the bytes received is fixed: + * + * Byte Destination + * ---- ----------------------------------------------------------- + * 0 SPI_D[7:0] (the low byte of the 'SPI data' register) + * 1 SPI_D[15:8] (the next byte of the 'SPI data' register) + * 2 SPI_D[23:16] (the next byte of the 'SPI data' register) + * 3 SPI_D[31:24] (the high byte of the 'SPI data' register) + * 4 SPI_AO[7:0] (the 'SPI opcode' field) + * 5 SPI_AO[15:8] (the low byte of the 'SPI address' field) + * 6 SPI_AO[23:16] (the middle byte of the 'SPI address' field) + * 7 SPI_AO[31:24] (the high byte of the 'SPI address' field) + * + * + * * To perform an SPI transaction: + * Write the appropriate values into the SPI_AO and SPI_D registers + * * Write the appropriate values into the 'transmit byte count' and + * 'received byte count' fields of the SPI_CS register. + * * Write a '1' to the 'SPI transaction start' bit of the SPI_CS + * register (this step can be combined with the one above if desired + * so that only a single SPI_CS write is needed). + * * Poll the 'transaction busy indication' bit in the SPI_CS register + * until it is clear, indicating that the SPI transaction has + * completed. + * * If the transaction included a receive phase, then retrieve the + * received data by reading the appropriate bytes from the SPI_D and + * SPI_AO registers. + * + * + * * Examples: + * * A "write disable" (WRDI) transaction: + * * Opcode (SPI_AO[7:0]): 0x04 (for STMicro; varies by + * manufacturer and device type) + * * Address (SPI_AO[31:8]): don't care (not used) + * * Data (SPI_D[31:0]): don't care (not used) + * * Transmission byte count: 1 + * * Receive byte count: 0 + * + * * A "read status register" (RDSR) transaction: + * * Opcode (SPI_AO[7:0]): 0x05 (for STMicro; varies by + * manufacturer and device type) + * * Address (SPI_AO[31:8]): don't care (not used) + * * Data (SPI_D[31:0]): don't care (not used) + * * Transmission byte count: 1 + * * Receive byte count: 1 + * * Read SPI_D[7:0] to retrieve status register value + * + * * A "page program" (PP) transaction to write a value of 0xdeadbeef + * to address 0x123456: + * * Opcode (SPI_AO[7:0]): 0x02 (for STMicro; varies by + * manufacturer and device type) + * * Address (SPI_AO[31:8]): 0x123456 + * * Data (SPI_D[31:0]): 0xdeadbeef + * * Transmission byte count: 8 + * * Receive byte count: 0 + */ + +/* Wait till Transaction busy indication bit in SPI control/status register of Falcon's SPI Flash Controller is clear */ +LOCAL void +_cmnos_sflash_WaitTillTransactionOver(void) +{ + A_UINT32 poldata; + A_UINT32 flg; + + do + { + poldata = HAL_WORD_REG_READ(SPI_CS_ADDRESS); + + flg = SPI_CS_BUSY_GET(poldata); + } while (flg != 0x0); +} + +/* Wait till Write In Progress bit in Status Register of Serial Flash is clear */ +LOCAL void +_cmnos_sflash_WaitTillNotWriteInProcess(void) +{ + A_UINT32 poldata; + A_UINT32 flg; + + do + { + _cmnos_sflash_WaitTillTransactionOver(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1) ); + + _cmnos_sflash_WaitTillTransactionOver(); + + poldata = HAL_WORD_REG_READ(SPI_D_ADDRESS); + flg = poldata & ZM_SFLASH_STATUS_REG_WIP; + + } while (flg != 0x0); +} + +/************************************************************************/ +/* Function to Send WREN(Write Enable) Operation */ +/************************************************************************/ +LOCAL void +_cmnos_sflash_WriteEnable() +{ + _cmnos_sflash_WaitTillNotWriteInProcess(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_WREN) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) ); + + _cmnos_sflash_WaitTillTransactionOver(); +} + +/************************************************************************/ +/* Function to In itialize SPI Flash Controller */ +/************************************************************************/ +LOCAL void +cmnos_sflash_init(void) +{ +#if defined(PROJECT_K2) + /* Switch the function of I/O pin 19~22 to act as SPI pins */ + HAL_WORD_REG_WRITE( MAGPIE_REG_CLOCK_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_CLOCK_CTRL_ADDR)|BIT8 ); +#endif + + /* "Autosize-determination of the address size of serial flash" is obsolete according to Brian Yang's mail : + * The designers reached an conclusion that the spi master (the apb_spi interface control) will be + * modified as ¡§presuming the attached flash model to be 24-bit addressing¡¨, i.e., no more + * auto-size detection! + * Hence you are free to force the 24-bit addressing in the *.c test code. + */ + + /* Force SPI address size to 24 bits */ + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_AUTOSIZ_OVR_SET(2) ); +} + +/************************************************************************/ +/* Function to Send Sector/Block/Chip Erase Operation */ +/************************************************************************/ +LOCAL void +cmnos_sflash_erase(A_UINT32 erase_type, A_UINT32 addr) +{ + A_UINT32 erase_opcode; + A_UINT32 tx_len; + + if (erase_type == ZM_SFLASH_SECTOR_ERASE) + { + erase_opcode = ZM_SFLASH_OP_SE; + tx_len = 4; + } + else if (erase_type == ZM_SFLASH_BLOCK_ERASE) + { + erase_opcode = ZM_SFLASH_OP_BE; + tx_len = 4; + } + else + { + erase_opcode = ZM_SFLASH_OP_CE; + tx_len = 1; + } + + _cmnos_sflash_WriteEnable(); + _cmnos_sflash_WaitTillNotWriteInProcess(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(erase_opcode) | SPI_AO_ADDR_SET(addr) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(tx_len) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) ); + +#if 0 + /* Do not wait(let it be completed in background) */ + _cmnos_sflash_WaitTillTransactionOver(); +#else + /* Wait till completion */ + _cmnos_sflash_WaitTillNotWriteInProcess(); /* Chip Erase takes 80 - 200 seconds to complete */ +#endif +} + +/************************************************************************/ +/* Function to Perform Page Program Operation */ +/* Notes: */ +/* Serial Flash has the following characteristics : */ +/* 1) In datasheet, 1-256 data bytes can be sent at a time, but */ +/* Falcon supports only 4 bytes at a time. */ +/* 2) If the eight least significant address bits(A7-A0) are not */ +/* all 0, all transmitted data which goes beyond the end of the */ +/* current page are programmed from the start address in the */ +/* same page. */ +/* This API hides the complexity of the above. */ +/************************************************************************/ +LOCAL void +cmnos_sflash_program(A_UINT32 addr, A_UINT32 len, A_UINT8 *buf) +{ + A_UINT32 s_addr, e_addr; + A_UINT32 reminder, write_byte; + A_UINT32 data_offset; + A_UINT32 next_page_base; + A_UINT32 t_word_data; + + e_addr = addr + len; + for (s_addr = addr; s_addr < e_addr; ) + { + next_page_base = (s_addr - s_addr%ZM_SFLASH_PAGE_SIZE) + ZM_SFLASH_PAGE_SIZE; + + reminder = e_addr - s_addr; + + write_byte = next_page_base - s_addr; + + if (write_byte >= 4) + write_byte = 4; + + if (write_byte > reminder) + write_byte = reminder; + + data_offset = s_addr - addr; + + A_MEMCPY(&t_word_data, buf + data_offset, write_byte); + + _cmnos_sflash_WriteEnable(); + _cmnos_sflash_WaitTillNotWriteInProcess(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_PP) | SPI_AO_ADDR_SET(s_addr) ); + HAL_WORD_REG_WRITE( SPI_D_ADDRESS, SPI_D_DATA_SET(t_word_data) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(4 + write_byte) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) ); + + _cmnos_sflash_WaitTillTransactionOver(); + + s_addr += write_byte; + } +} + +/************************************************************************/ +/* Function to Send Read/Fast Read Data Operation */ +/************************************************************************/ +LOCAL void +cmnos_sflash_read(A_UINT32 fast, A_UINT32 addr, A_UINT32 len, A_UINT8 *buf) +{ + A_UINT32 read_opcode; + A_UINT32 i; + A_UINT32 read_cnt, remainder; + A_UINT32 write_byte, read_byte; + + if (fast) + { + read_opcode = ZM_SFLASH_OP_FAST_READ; + write_byte = 5; + } + else + { + read_opcode = ZM_SFLASH_OP_READ; + write_byte = 4; + } + + read_cnt = len/4; + remainder = len%4; + if (remainder) + read_cnt++; + + read_byte = 4; + for (i = 0; i < read_cnt; i ++) + { + if (i == read_cnt-1 && remainder) + read_byte = remainder; + + _cmnos_sflash_WaitTillNotWriteInProcess(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(read_opcode) | SPI_AO_ADDR_SET(addr + i*4) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(write_byte) | SPI_CS_RXBCNT_SET(read_byte) | SPI_CS_XCNSTART_SET(1) ); + + _cmnos_sflash_WaitTillTransactionOver(); + + A_MEMCPY(buf + i*4, (A_UINT8 *)(SPI_D_ADDRESS), read_byte); + } +} + +/************************************************************************/ +/* Function to Read Flash Status Register */ +/************************************************************************/ +LOCAL A_UINT32 +cmnos_sflash_rdsr(void) +{ + A_UINT32 word_data; + + _cmnos_sflash_WaitTillTransactionOver(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1) ); + + _cmnos_sflash_WaitTillTransactionOver(); + + word_data = HAL_WORD_REG_READ(SPI_D_ADDRESS) & 0x000000FF; + + return word_data; +} + +void +cmnos_sflash_module_install(struct sflash_api *tbl) +{ + /* Indispensable functions */ + tbl->_sflash_init = cmnos_sflash_init; + tbl->_sflash_erase = cmnos_sflash_erase; + tbl->_sflash_program = cmnos_sflash_program; + tbl->_sflash_read = cmnos_sflash_read; + + /* Dispensable functions */ + tbl->_sflash_rdsr = cmnos_sflash_rdsr; +} + +#endif /* SYSTEM_MODULE_SFLASH */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/Makefile new file mode 100755 index 0000000..7c9f177 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = string + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/Makefile.ss new file mode 100755 index 0000000..19ccf8a --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_string.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/inc/string_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/inc/string_api.h new file mode 100755 index 0000000..9a15021 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/inc/string_api.h @@ -0,0 +1,11 @@ +#ifndef __STRING_API_H__ +#define __STRING_API_H__ +struct string_api { + void (* _string_init)(void); + char *(* _strcpy)(char *, const char *); + char *(* _strncpy)(char *, const char *, unsigned int); + int (* _strlen)(const char *); + int (* _strcmp)(const char *, const char *); + int (* _strncmp)(const char *, const char *, unsigned int); +}; +#endif /* __STRING_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/src/cmnos_string.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/src/cmnos_string.c new file mode 100755 index 0000000..634a5de --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/string/src/cmnos_string.c @@ -0,0 +1,25 @@ +#include "athos_api.h" + +/* Common string functions, provided by toolchain libraries. */ + +extern char *strcpy(char *s1, const char *s2); +extern char *strncpy(char *s1, const char *s2, unsigned int n); +extern int strcmp(const char *s1, const char *s2); +extern int strncmp(const char *s1, const char *s2, unsigned int n); +extern int strlen(const char *s); + +LOCAL void +cmnos_string_init(void) +{ +} + +void +cmnos_string_module_install(struct string_api *tbl) +{ + tbl->_string_init = cmnos_string_init; + tbl->_strcpy = strcpy; + tbl->_strncpy = strncpy; + tbl->_strlen = strlen; + tbl->_strcmp = strcmp; + tbl->_strncmp = strncmp; +} diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/Makefile new file mode 100755 index 0000000..ee83361 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = tasklet + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/Makefile.ss new file mode 100755 index 0000000..e11d708 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/Makefile.ss @@ -0,0 +1,204 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_tasklet.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + +/root/Workspace/0211/tgt/build/magpie_1_0/image/magpie_flash_boot/../../../..//build/magpie_1_0/rom/cmnos/tasklet/obj/cmnos_tasklet.o: \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/tasklet/src/cmnos_tasklet.c \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/sys_cfg.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/magpie/rom_cfg.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/magpie_mem.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/athos_api.h \ + /root/Workspace/0211/tgt/target/inc/osapi.h \ + /root/Workspace/0211/tgt/target/inc/OTUS/OTUS_soc.h \ + /root/Workspace/0211/tgt/target/inc/dt_defs.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/inc/cmnos_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/printf/inc/printf_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/uart/inc/uart_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/magpie/reg_defs.h \ + /root/Workspace/0211/tgt/target/cmnos/dbg/inc/dbg_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/mem/inc/mem_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/misc/inc/misc_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/string/inc/string_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/timer/inc/timer_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/rompatch/inc/romp_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/allocram/inc/allocram_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/tasklet/inc/tasklet_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/clock/inc/clock_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/intr/inc/intr_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/wdt/inc/wdt_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/eeprom/inc/eeprom_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/usb_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/hif_pci.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/hif_api.h \ + /root/Workspace/0211/tgt/adf/include/nbuf/adf_nbuf.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_util.h \ + /root/Workspace/0211/tgt/target/adf/os/inc/adf_os_util_pvt.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_types.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_stdtypes.h \ + /root/Workspace/0211/tgt/target/adf/os/inc/adf_os_types_pvt.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/vbuf/inc/vbuf_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/vdesc/inc/vdesc_api.h \ + /root/Workspace/0211/tgt/target/inc/stdarg.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_dma.h \ + /root/Workspace/0211/tgt/target/adf/os/inc/adf_os_dma_pvt.h \ + /root/Workspace/0211/tgt/adf/include/net/adf_net_types.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/adf/nbuf/inc/adf_nbuf_pvt.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/hif_gmac.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/Magpie_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/usbfifo_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/htc/inc/htc_api.h \ + /root/Workspace/0211/wlan/include/htc.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/buf_pool/inc/buf_pool_api.h \ + /root/Workspace/0211/tgt/target/wmi/inc/wmi_svc_api.h \ + /root/Workspace/0211/wlan/include/wmi.h \ + /root/Workspace/0211/wlan/include/athdefs.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/dma_engine/inc/dma_engine_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/dma_lib.h \ + /root/Workspace/0211/tgt/target/cmnos/sflash/inc/sflash_api.h +/root/Workspace/0211/tgt/build/magpie_1_0/image/magpie_flash_boot/../../../..//build/magpie_1_0/rom/cmnos/tasklet/obj/cmnos_tasklet.o: \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/tasklet/src/cmnos_tasklet.c \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/sys_cfg.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/magpie/rom_cfg.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/magpie_mem.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/athos_api.h \ + /root/Workspace/0211/tgt/target/inc/osapi.h \ + /root/Workspace/0211/tgt/target/inc/OTUS/OTUS_soc.h \ + /root/Workspace/0211/tgt/target/inc/dt_defs.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/inc/cmnos_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/printf/inc/printf_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/uart/inc/uart_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/magpie/reg_defs.h \ + /root/Workspace/0211/tgt/target/cmnos/dbg/inc/dbg_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/mem/inc/mem_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/misc/inc/misc_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/string/inc/string_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/timer/inc/timer_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/rompatch/inc/romp_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/allocram/inc/allocram_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/tasklet/inc/tasklet_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/clock/inc/clock_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/intr/inc/intr_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/wdt/inc/wdt_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/cmnos/eeprom/inc/eeprom_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/usb_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/hif_pci.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/hif_api.h \ + /root/Workspace/0211/tgt/adf/include/nbuf/adf_nbuf.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_util.h \ + /root/Workspace/0211/tgt/target/adf/os/inc/adf_os_util_pvt.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_types.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_stdtypes.h \ + /root/Workspace/0211/tgt/target/adf/os/inc/adf_os_types_pvt.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/vbuf/inc/vbuf_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/vdesc/inc/vdesc_api.h \ + /root/Workspace/0211/tgt/target/inc/stdarg.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_dma.h \ + /root/Workspace/0211/tgt/target/adf/os/inc/adf_os_dma_pvt.h \ + /root/Workspace/0211/tgt/adf/include/net/adf_net_types.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/adf/nbuf/inc/adf_nbuf_pvt.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/hif_gmac.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/inc/Magpie_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/usbfifo_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/htc/inc/htc_api.h \ + /root/Workspace/0211/wlan/include/htc.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/buf_pool/inc/buf_pool_api.h \ + /root/Workspace/0211/tgt/target/wmi/inc/wmi_svc_api.h \ + /root/Workspace/0211/wlan/include/wmi.h \ + /root/Workspace/0211/wlan/include/athdefs.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/dma_engine/inc/dma_engine_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/rom/hif/inc/dma_lib.h \ + /root/Workspace/0211/tgt/target/cmnos/sflash/inc/sflash_api.h +/root/Workspace/0211/tgt/build/magpie_1_0/image/magpie_flash_boot/../../../..//build/magpie_1_0/sflash_boot/cmnos/tasklet/obj/cmnos_tasklet.o: \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/tasklet/src/cmnos_tasklet.c \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/inc/sys_cfg.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/inc/magpie/rom_cfg.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/inc/magpie_mem.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/inc/athos_api.h \ + /root/Workspace/0211/tgt/target/inc/osapi.h \ + /root/Workspace/0211/tgt/target/inc/OTUS/OTUS_soc.h \ + /root/Workspace/0211/tgt/target/inc/dt_defs.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/inc/cmnos_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/printf/inc/printf_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/uart/inc/uart_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/inc/magpie/reg_defs.h \ + /root/Workspace/0211/tgt/target/cmnos/dbg/inc/dbg_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/mem/inc/mem_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/misc/inc/misc_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/string/inc/string_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/timer/inc/timer_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/rompatch/inc/romp_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/allocram/inc/allocram_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/tasklet/inc/tasklet_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/clock/inc/clock_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/intr/inc/intr_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/wdt/inc/wdt_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/cmnos/eeprom/inc/eeprom_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/hif/inc/usb_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/hif/inc/hif_pci.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/hif/inc/hif_api.h \ + /root/Workspace/0211/tgt/adf/include/nbuf/adf_nbuf.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_util.h \ + /root/Workspace/0211/tgt/target/adf/os/inc/adf_os_util_pvt.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_types.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_stdtypes.h \ + /root/Workspace/0211/tgt/target/adf/os/inc/adf_os_types_pvt.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/vbuf/inc/vbuf_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/vdesc/inc/vdesc_api.h \ + /root/Workspace/0211/tgt/target/inc/stdarg.h \ + /root/Workspace/0211/tgt/adf/include/os/adf_os_dma.h \ + /root/Workspace/0211/tgt/target/adf/os/inc/adf_os_dma_pvt.h \ + /root/Workspace/0211/tgt/adf/include/net/adf_net_types.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/adf/nbuf/inc/adf_nbuf_pvt.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/hif/inc/hif_gmac.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/inc/Magpie_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/hif/inc/usbfifo_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/htc/inc/htc_api.h \ + /root/Workspace/0211/wlan/include/htc.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/buf_pool/inc/buf_pool_api.h \ + /root/Workspace/0211/tgt/target/wmi/inc/wmi_svc_api.h \ + /root/Workspace/0211/wlan/include/wmi.h \ + /root/Workspace/0211/wlan/include/athdefs.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/dma_engine/inc/dma_engine_api.h \ + /root/Workspace/0211/tgt/build/magpie_1_0/sflash_boot/hif/inc/dma_lib.h \ + /root/Workspace/0211/tgt/target/cmnos/sflash/inc/sflash_api.h diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/inc/tasklet_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/inc/tasklet_api.h new file mode 100755 index 0000000..8ba85f1 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/inc/tasklet_api.h @@ -0,0 +1,28 @@ +#ifndef __TASKLET_API_H__ +#define __TASKLET_API_H__ + +//typedef int A_tasklet_t; + +typedef void (*A_TASKLET_FUNC)(void *arg); + +#define A_TASKLET_STATE_DISABLE 0 +#define A_TASKLET_STATE_SCHEDULED 1 +#define A_TASKLET_STATE_RUNNING 2 + +struct _tasklet { + A_TASKLET_FUNC func; + void *arg; + int state; + struct _tasklet *next; +}; + +typedef struct _tasklet A_tasklet_t; + +struct tasklet_api { + void (* _tasklet_init)(void); + void (* _tasklet_init_task)(A_TASKLET_FUNC, void * arg, A_tasklet_t *); + void (* _tasklet_disable)(A_tasklet_t *); + void (* _tasklet_schedule)(A_tasklet_t *); + void (* _tasklet_run)(void); +}; +#endif /* __TASKLET_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/src/cmnos_tasklet.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/src/cmnos_tasklet.c new file mode 100755 index 0000000..053cd27 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/tasklet/src/cmnos_tasklet.c @@ -0,0 +1,136 @@ +#include "sys_cfg.h" + +#include "athos_api.h" +#include "tasklet_api.h" + +//////////////////////////////////////////// + +typedef struct _tasklet_context { + A_tasklet_t *schedule_tasks; +} tasklet_context; + +static tasklet_context g_tasklet_ctx; + +/* Initialize timer software. Called once during initialization. */ +LOCAL void +cmnos_tasklet_init(void) +{ + //timer_list = NULL; + g_tasklet_ctx.schedule_tasks = NULL; +} + +LOCAL void +cmnos_tasklet_init_task(A_TASKLET_FUNC fn, void * arg, A_tasklet_t *tasklet) +{ + tasklet->func = fn; + tasklet->arg = arg; + tasklet->next = NULL; + tasklet->state = A_TASKLET_STATE_DISABLE; +} + +LOCAL void +cmnos_tasklet_schedule(A_tasklet_t *tasklet) +{ + if ( tasklet->state == A_TASKLET_STATE_SCHEDULED ) { + return; + } + + tasklet->state = A_TASKLET_STATE_SCHEDULED; + if ( g_tasklet_ctx.schedule_tasks == NULL ) { + g_tasklet_ctx.schedule_tasks = tasklet; + } else { + tasklet->next = g_tasklet_ctx.schedule_tasks; + g_tasklet_ctx.schedule_tasks = tasklet; + } +} + +LOCAL void +cmnos_tasklet_disable(A_tasklet_t *tasklet) +{ + A_tasklet_t *tmp; + A_tasklet_t *prev = NULL; + + if ( tasklet->state != A_TASKLET_STATE_SCHEDULED ) { + return; + } + + tmp = g_tasklet_ctx.schedule_tasks; + while ( tmp != NULL ) { + if ( tmp == tasklet ) { + if ( prev == NULL ) { + g_tasklet_ctx.schedule_tasks = NULL; + } else { + prev->next = tmp->next; + } + + tasklet->state = A_TASKLET_STATE_DISABLE; + break; + } else { + prev = tmp; + tmp = tmp->next; + } + } +} + +LOCAL void +cmnos_tasklet_run(void) +{ + A_tasklet_t *tmp; + + tmp = g_tasklet_ctx.schedule_tasks; + while ( tmp != NULL ) { + g_tasklet_ctx.schedule_tasks = tmp->next; + tmp->next = NULL; + + tmp->state = A_TASKLET_STATE_RUNNING; + tmp->func(tmp->arg); + tmp->state = A_TASKLET_STATE_DISABLE; + + tmp = g_tasklet_ctx.schedule_tasks; + } + + g_tasklet_ctx.schedule_tasks = NULL; +} + +void +cmnos_tasklet_module_install(struct tasklet_api *tbl) +{ + tbl->_tasklet_init = cmnos_tasklet_init; + tbl->_tasklet_init_task = cmnos_tasklet_init_task; + tbl->_tasklet_disable = cmnos_tasklet_disable; + tbl->_tasklet_schedule = cmnos_tasklet_schedule; + tbl->_tasklet_run = cmnos_tasklet_run; +} + +//#define CMNOS_TASKLET_UT +#ifdef CMNOS_TASKLET_UT + +#include + +adf_os_bh_t bh; +adf_os_bh_t bh2; + +void test_tasklet(void *arg) +{ + adf_os_bh_t *tmpBH = (adf_os_bh_t *)arg; + + if ( tmpBH == &bh ) + adf_os_print("Tasklet1 running...\n"); + else if ( tmpBH == &bh2 ) + adf_os_print("Tasklet2 running...\n"); +} + +void +cmnos_tasklet_test() +{ + adf_os_init_bh(NULL, &bh, test_tasklet, &bh); + adf_os_init_bh(NULL, &bh2, test_tasklet, &bh2); + + adf_os_sched_bh(NULL, &bh); + adf_os_sched_bh(NULL, &bh2); +} + +#endif + + + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/Makefile new file mode 100755 index 0000000..cb9c709 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = timer + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/Makefile.ss new file mode 100755 index 0000000..8b42f12 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/Makefile.ss @@ -0,0 +1,46 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_timer.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/inc/timer_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/inc/timer_api.h new file mode 100755 index 0000000..025a8e8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/inc/timer_api.h @@ -0,0 +1,23 @@ +#ifndef __TIMER_API_H__ +#define __TIMER_API_H__ +/* + * In order to remain completely independent of OS header files, + * "_SPACE" structures are declared with sufficient room to hold + * corresponding OS structures. + */ +typedef unsigned int _A_TIMER_SPACE[5]; +typedef _A_TIMER_SPACE A_timer_t; +#define A_TIMER A_timer_t /* historical */ + +typedef unsigned int A_HANDLE; /* historical */ +typedef void A_TIMER_FUNC(A_HANDLE timer_handle, void *arg); + +struct timer_api { + void (* _timer_init)(void); + void (* _timer_arm)(A_timer_t *, unsigned int); + void (* _timer_disarm)(A_timer_t *); + void (* _timer_setfn)(A_timer_t *, A_TIMER_FUNC, void *); + void (* _timer_run)(void); +}; +#endif /* __TIMER_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/src/cmnos_timer.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/src/cmnos_timer.c new file mode 100755 index 0000000..b9b49b0 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/timer/src/cmnos_timer.c @@ -0,0 +1,178 @@ + +#include "sys_cfg.h" +#include "athos_api.h" + +#if SYSTEM_MODULE_TIMER + +//#define TIMER_NOT_IN_USE ((cmnos_timer_t *)-1) +#define TIMER_NOT_IN_USE NULL + +/* convert milliseconds to ticks */ +#define MILLIS_TO_TIMER_TICKS(ms) (ms*ONE_MSEC) + +/* Current tick time */ +//#define NOW() xthal_get_ccount() + +#define TIMER_IS_EARLIER(t1, t2) ((A_INT32)((A_UINT32)t1-(A_UINT32)t2)<=0) + + +typedef struct cmnos_timer_s { + struct cmnos_timer_s *timer_next; + A_UINT32 timer_expire; + A_UINT32 timer_period; + A_TIMER_FUNC *timer_function; + void *timer_arg; +} cmnos_timer_t; /* A_timer_t */ + +LOCAL cmnos_timer_t *timer_list = NULL; + + +/* Initialize a timer. Initially, it is unarmed. */ +LOCAL void +cmnos_timer_setfn(A_timer_t *A_timer, A_TIMER_FUNC *pfunction, void *parg) +{ + cmnos_timer_t *ptimer = (cmnos_timer_t *)A_timer; + + ptimer->timer_next = TIMER_NOT_IN_USE; + ptimer->timer_expire = 0; /* sanity */ + ptimer->timer_function = pfunction; + ptimer->timer_arg = parg; +} + +/* Arm a timer to trigger after the specified time */ +LOCAL void +cmnos_timer_arm(A_timer_t *A_timer, + unsigned int milliseconds) +{ + cmnos_timer_t *ptimer = (cmnos_timer_t *)A_timer; + A_UINT32 timer_expire; + A_UINT32 timer_ticks; + cmnos_timer_t *curr, *prev = NULL; + + /* Convert milliseconds to ticks */ + timer_ticks = MILLIS_TO_TIMER_TICKS(milliseconds); + + /* Calculate expiring tick time */ + timer_expire = NOW() + timer_ticks; + + /* Find the right place to insert */ + for (curr = timer_list; + curr; + prev=curr, curr = curr->timer_next) + { + if (TIMER_IS_EARLIER(timer_expire, curr->timer_expire)) + break; + } + + /* Inster timer to the list */ + ptimer->timer_next = curr; + ptimer->timer_expire = timer_expire; + if (prev) { + prev->timer_next = ptimer; + } else { + /* Insert at head of the timer list */ + timer_list = ptimer; + } + + return; +} + +/* Disarm a timer, if it is currently armed. */ +LOCAL void +cmnos_timer_disarm(A_timer_t *A_timer) +{ + cmnos_timer_t *ptimer = (cmnos_timer_t *)A_timer; + cmnos_timer_t *curr, *prev = NULL; + + /* Find desired timer */ + for (curr = timer_list; + curr; + prev=curr, curr = curr->timer_next) + { + if (ptimer == curr) { + break; + } + } + + /* Remove it from the timer list */ + if (curr) { + if (prev) { + prev->timer_next = curr->timer_next; + } else { + timer_list = curr->timer_next; + } + } + + /* Clear timer parameters */ + ptimer->timer_next = TIMER_NOT_IN_USE; + ptimer->timer_period = 0; +} + +/* Initialize timer software. Called once during initialization. */ +LOCAL void +cmnos_timer_init(void) +{ + timer_list = NULL; +} + +/* Handler for LF0 Timer. */ +LOCAL void +cmnos_timer_handler(void) +{ + cmnos_timer_t *ptimer; + + while (timer_list && + TIMER_IS_EARLIER(timer_list->timer_expire, NOW())) + { + ptimer = timer_list; + timer_list = timer_list->timer_next; + ptimer->timer_next = TIMER_NOT_IN_USE; + ptimer->timer_function((A_HANDLE)ptimer, ptimer->timer_arg); + } + return; +} + +void +cmnos_timer_module_install(struct timer_api *tbl) +{ + tbl->_timer_init = cmnos_timer_init; + tbl->_timer_arm = cmnos_timer_arm; + tbl->_timer_disarm = cmnos_timer_disarm; + tbl->_timer_setfn = cmnos_timer_setfn; + tbl->_timer_run = cmnos_timer_handler; +} + +//#define CMNOS_TIMER_UT +#ifdef CMNOS_TIMER_UT + +#include + +adf_os_timer_t timer1; +adf_os_timer_t timer2; + +void test_timer(void *arg) +{ + adf_os_timer_t *tmp = (adf_os_timer_t *) arg; + + if ( tmp == &timer1 ) { + adf_os_print("Timer1 is fired\n"); + adf_os_timer_start(&timer1, 1000); + } else { + adf_os_print("Timer2 is fired\n"); + adf_os_timer_start(&timer2, 3000); + } +} + +void +cmnos_timer_test() +{ + adf_os_timer_init(NULL, &timer1, test_timer, &timer1); + adf_os_timer_init(NULL, &timer2, test_timer, &timer2); + adf_os_timer_start(&timer1, 1000); + adf_os_timer_start(&timer2, 3000); +} + +#endif + +#endif /* end SYSTEM_MODULE_TIMER */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/Makefile new file mode 100755 index 0000000..897d1d1 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = uart + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/Makefile.ss new file mode 100755 index 0000000..a155bd8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/uart_api.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/inc/uart_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/inc/uart_api.h new file mode 100755 index 0000000..392e513 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/inc/uart_api.h @@ -0,0 +1,309 @@ +/*************************************************************************/ +/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : uart.h */ +/* */ +/* Abstract */ +/* This file contains definition of uart registers, marco and api. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _UART_API_H_ +#define _UART_API_H_ + +#include "reg_defs.h" + +/************************* Register Process marco ************************/ +#define UART_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(UART_BASE_ADDRESS|(uint32_t)(addr), (val)) +#define UART_REG_READ(addr) HAL_WORD_REG_READ(UART_BASE_ADDRESS|(uint32_t)(addr)) + +/************************** Register deinition ***************************/ +#define RBR_ADDRESS 0x00051000 +#define RBR_OFFSET 0x00000000 +#define RBR_RBR_MSB 7 +#define RBR_RBR_LSB 0 +#define RBR_RBR_MASK 0x000000ff +#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) +#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) + +#define THR_ADDRESS 0x00051000 +#define THR_OFFSET 0x00000000 +#define THR_THR_MSB 7 +#define THR_THR_LSB 0 +#define THR_THR_MASK 0x000000ff +#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) +#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) + +#define DLL_ADDRESS 0x00051000 +#define DLL_OFFSET 0x00000000 +#define DLL_DLL_MSB 7 +#define DLL_DLL_LSB 0 +#define DLL_DLL_MASK 0x000000ff +#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) +#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) + +#define DLH_ADDRESS 0x00051004 +#define DLH_OFFSET 0x00000004 +#define DLH_DLH_MSB 7 +#define DLH_DLH_LSB 0 +#define DLH_DLH_MASK 0x000000ff +#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) +#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) + +#define IER_ADDRESS 0x00051004 +#define IER_OFFSET 0x00000004 +#define IER_EDDSI_MSB 3 +#define IER_EDDSI_LSB 3 +#define IER_EDDSI_MASK 0x00000008 +#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) +#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) +#define IER_ELSI_MSB 2 +#define IER_ELSI_LSB 2 +#define IER_ELSI_MASK 0x00000004 +#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) +#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) +#define IER_ETBEI_MSB 1 +#define IER_ETBEI_LSB 1 +#define IER_ETBEI_MASK 0x00000002 +#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) +#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) +#define IER_ERBFI_MSB 0 +#define IER_ERBFI_LSB 0 +#define IER_ERBFI_MASK 0x00000001 +#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) +#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) + +#define IIR_ADDRESS 0x00051008 +#define IIR_OFFSET 0x00000008 +#define IIR_FIFO_STATUS_MSB 7 +#define IIR_FIFO_STATUS_LSB 6 +#define IIR_FIFO_STATUS_MASK 0x000000c0 +#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) +#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) +#define IIR_IID_MSB 3 +#define IIR_IID_LSB 0 +#define IIR_IID_MASK 0x0000000f +#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) +#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) + +#define FCR_ADDRESS 0x00051008 +#define FCR_OFFSET 0x00000008 +#define FCR_RCVR_TRIG_MSB 7 +#define FCR_RCVR_TRIG_LSB 6 +#define FCR_RCVR_TRIG_MASK 0x000000c0 +#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) +#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) +#define FCR_DMA_MODE_MSB 3 +#define FCR_DMA_MODE_LSB 3 +#define FCR_DMA_MODE_MASK 0x00000008 +#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) +#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) +#define FCR_XMIT_FIFO_RST_MSB 2 +#define FCR_XMIT_FIFO_RST_LSB 2 +#define FCR_XMIT_FIFO_RST_MASK 0x00000004 +#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) +#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) +#define FCR_RCVR_FIFO_RST_MSB 1 +#define FCR_RCVR_FIFO_RST_LSB 1 +#define FCR_RCVR_FIFO_RST_MASK 0x00000002 +#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) +#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) +#define FCR_FIFO_EN_MSB 0 +#define FCR_FIFO_EN_LSB 0 +#define FCR_FIFO_EN_MASK 0x00000001 +#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) +#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) + +#define LCR_ADDRESS 0x0005100c +#define LCR_OFFSET 0x0000000c +#define LCR_DLAB_MSB 7 +#define LCR_DLAB_LSB 7 +#define LCR_DLAB_MASK 0x00000080 +#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) +#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) +#define LCR_BREAK_MSB 6 +#define LCR_BREAK_LSB 6 +#define LCR_BREAK_MASK 0x00000040 +#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) +#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) +#define LCR_EPS_MSB 4 +#define LCR_EPS_LSB 4 +#define LCR_EPS_MASK 0x00000010 +#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) +#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) +#define LCR_PEN_MSB 3 +#define LCR_PEN_LSB 3 +#define LCR_PEN_MASK 0x00000008 +#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) +#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) +#define LCR_STOP_MSB 2 +#define LCR_STOP_LSB 2 +#define LCR_STOP_MASK 0x00000004 +#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) +#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) +#define LCR_CLS_MSB 1 +#define LCR_CLS_LSB 0 +#define LCR_CLS_MASK 0x00000003 +#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) +#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) + +#define MCR_ADDRESS 0x00051010 +#define MCR_OFFSET 0x00000010 +#define MCR_LOOPBACK_MSB 5 +#define MCR_LOOPBACK_LSB 5 +#define MCR_LOOPBACK_MASK 0x00000020 +#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) +#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) +#define MCR_OUT2_MSB 3 +#define MCR_OUT2_LSB 3 +#define MCR_OUT2_MASK 0x00000008 +#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) +#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) +#define MCR_OUT1_MSB 2 +#define MCR_OUT1_LSB 2 +#define MCR_OUT1_MASK 0x00000004 +#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) +#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) +#define MCR_RTS_MSB 1 +#define MCR_RTS_LSB 1 +#define MCR_RTS_MASK 0x00000002 +#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) +#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) +#define MCR_DTR_MSB 0 +#define MCR_DTR_LSB 0 +#define MCR_DTR_MASK 0x00000001 +#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) +#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) + +#define LSR_ADDRESS 0x00051014 +#define LSR_OFFSET 0x00000014 +#define LSR_FERR_MSB 7 +#define LSR_FERR_LSB 7 +#define LSR_FERR_MASK 0x00000080 +#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) +#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) +#define LSR_TEMT_MSB 6 +#define LSR_TEMT_LSB 6 +#define LSR_TEMT_MASK 0x00000040 +#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) +#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) +#define LSR_THRE_MSB 5 +#define LSR_THRE_LSB 5 +#define LSR_THRE_MASK 0x00000020 +#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) +#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) +#define LSR_BI_MSB 4 +#define LSR_BI_LSB 4 +#define LSR_BI_MASK 0x00000010 +#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) +#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) +#define LSR_FE_MSB 3 +#define LSR_FE_LSB 3 +#define LSR_FE_MASK 0x00000008 +#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) +#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) +#define LSR_PE_MSB 2 +#define LSR_PE_LSB 2 +#define LSR_PE_MASK 0x00000004 +#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) +#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) +#define LSR_OE_MSB 1 +#define LSR_OE_LSB 1 +#define LSR_OE_MASK 0x00000002 +#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) +#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) +#define LSR_DR_MSB 0 +#define LSR_DR_LSB 0 +#define LSR_DR_MASK 0x00000001 +#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) +#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) + +#define MSR_ADDRESS 0x00051018 +#define MSR_OFFSET 0x00000018 +#define MSR_DCD_MSB 7 +#define MSR_DCD_LSB 7 +#define MSR_DCD_MASK 0x00000080 +#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) +#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) +#define MSR_RI_MSB 6 +#define MSR_RI_LSB 6 +#define MSR_RI_MASK 0x00000040 +#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) +#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) +#define MSR_DSR_MSB 5 +#define MSR_DSR_LSB 5 +#define MSR_DSR_MASK 0x00000020 +#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) +#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) +#define MSR_CTS_MSB 4 +#define MSR_CTS_LSB 4 +#define MSR_CTS_MASK 0x00000010 +#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) +#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) +#define MSR_DDCD_MSB 3 +#define MSR_DDCD_LSB 3 +#define MSR_DDCD_MASK 0x00000008 +#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) +#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) +#define MSR_TERI_MSB 2 +#define MSR_TERI_LSB 2 +#define MSR_TERI_MASK 0x00000004 +#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) +#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) +#define MSR_DDSR_MSB 1 +#define MSR_DDSR_LSB 1 +#define MSR_DDSR_MASK 0x00000002 +#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) +#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) +#define MSR_DCTS_MSB 0 +#define MSR_DCTS_LSB 0 +#define MSR_DCTS_MASK 0x00000001 +#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) +#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) + + +/************************** config definition ***************************/ +#define UART_FIFO_SIZE 512 //Must be 2^N + +#define USE_POST_BUFFER 0 // ENABLE a tx buffer for post processing, +/*********************** data struction definition ************************/ +// data struction definition +struct uart_fifo { +#if USE_POST_BUFFER + uint8_t buf[UART_FIFO_SIZE]; +#endif + uint16_t start_index; + uint16_t end_index; + uint32_t overrun_err; +}; + + +struct uart_blk { + uint16_t debug_mode; + uint16_t baud; + struct uart_api *_uart; + struct uart_fifo _tx; +}; + + +/******** hardware API table structure (API descriptions below) *************/ +struct uart_api { + uint32_t (*_uart_init)(void); + void (*_uart_char_put)(uint8_t ch); + uint16_t (*_uart_char_get)(uint8_t* ch); + void (*_uart_str_out)(uint8_t* str); + void (*_uart_task)(void); + uint32_t (*_uart_status)(void); + void (*_uart_config)(uint16_t flag); + void (*_uart_hwinit)(uint32_t freq, uint32_t baud); + //void (*_uart_config)(uint8_t cmd, void *pData); +}; + +/************************* EXPORT function ***************************/ + + +#endif // end of _UART_API_H_ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/src/uart_api.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/src/uart_api.c new file mode 100755 index 0000000..1086985 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/src/uart_api.c @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2000-2008 Atheros Communications, Inc., All Rights Reserved + * + * $Id: //depot/sw/branches/fusion_usb/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/uart/src/uart_api.c#1 $ + * + * This file contains UART functions + */ +#include "sys_cfg.h" + +#if SYSTEM_MODULE_UART + +#include "athos_api.h" + +//static global control block +// +static struct uart_blk uart_ctl_blk; + +static void _uart_hwinit(uint32_t freq, uint32_t baud); + +/*!- Initialize UART + * + */ +uint32_t +_uart_init(void) +{ + /*! Initialize UART hardware */ + uint32_t _lcr; + + /* Disable port interrupts while changing hardware */ + UART_REG_WRITE(IER_OFFSET, 0); + + /* Set databits, stopbits and parity. */ + _lcr = LCR_CLS_SET(3) | LCR_STOP_SET(0) | LCR_PEN_SET(0); + UART_REG_WRITE(LCR_OFFSET, _lcr); + + /* Set baud rate. */ + _uart_hwinit(A_REFCLK_SPEED_GET(), UART_DEFAULT_BAUD); +// _uart_hwinit(A_REFCLK_SPEED_GET(), 115200); + //_uart_hwinit(SYSTEM_CLK, UART_DEFAULT_BAUD); + + /* Don't allow interrupts. */ + UART_REG_WRITE(IER_OFFSET, 0); + + /* + * Enable and clear FIFO. + * We don't really use the FIFO for output, but it might still + * be useful for input. + */ + UART_REG_WRITE(FCR_OFFSET, + (FCR_FIFO_EN_SET(1) | + FCR_RCVR_FIFO_RST_SET(1) | + FCR_XMIT_FIFO_RST_SET(1))); + + /*! Initialize UART software buffer */ + uart_ctl_blk._tx.start_index = 0; + uart_ctl_blk._tx.end_index = 0; +} + + +/*!- dummy put character + * + */ +void +_uart_char_put_nothing(uint8_t ch) +{ + // do nothing +} + + +/*!- dummy get character + * + */ +uint16_t +_uart_char_get_nothing(uint8_t* ch) +{ + return 0; //return FALSE; +} + + +/*!- Put a character + * + */ +void +_uart_char_put(uint8_t ch) +{ +#if USE_POST_BUFFER + uint16_t index; + uint32_t count = 0; + + index = (uart_ctl_blk._tx.end_index+1) & (UART_FIFO_SIZE-1); + if(index == uart_ctl_blk._tx.start_index) { + while (1) { + _uart_task(); + index = (uart_ctl_blk._tx.end_index+1) & (UART_FIFO_SIZE-1); + if (index != uart_ctl_blk._tx.start_index) { + break; + } + if (count++ > 100000) { + /*! If Tx buffer is full, uart_underrun_t++, return FALSE */ + uart_ctl_blk._tx.overrun_err++; + return; + } + } + } + uart_ctl_blk._tx.buf[uart_ctl_blk._tx.end_index] = ch; + uart_ctl_blk._tx.end_index = index; +#else + /*! If Tx buffer is full, uart_underrun_t++, return FALSE */ + uint32_t lsr; + int i; + + for (i=0; i_uart_char_put = _uart_char_put; + else + // debug mode enable + uart_ctl_blk._uart->_uart_char_put = _uart_char_put_nothing; + } +} + +/*!- Set baudrate + * + */ +void +_uart_hwinit(uint32_t freq, uint32_t baud) +{ + uint32_t _lcr; + uint32_t baud_divisor = freq/16/baud; + + _lcr = UART_REG_READ(LCR_OFFSET); + _lcr |= LCR_DLAB_SET(1); + UART_REG_WRITE(LCR_OFFSET, _lcr); + + UART_REG_WRITE(DLH_OFFSET, baud_divisor >> 8); + UART_REG_WRITE(DLL_OFFSET, baud_divisor & 0xff); + + _lcr &= ~LCR_DLAB_SET(1); + UART_REG_WRITE(LCR_OFFSET, _lcr); +} + +/********** EXPORT function ***********/ + +/*!- Install the function table + * + */ +void cmnos_uart_module_install(struct uart_api *apis) +{ + /* hook in APIs */ + apis->_uart_init = _uart_init; + apis->_uart_char_put = _uart_char_put; + apis->_uart_char_get = _uart_char_get; + apis->_uart_str_out = _uart_str_out; + apis->_uart_task = _uart_task; + apis->_uart_config = _uart_config; + apis->_uart_status = _uart_status; + apis->_uart_hwinit = _uart_hwinit; + + uart_ctl_blk._uart = apis; + uart_ctl_blk.debug_mode = TRUE; + return; +} + +#endif /* SYSTEM_MODULE_UART */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/Makefile new file mode 100755 index 0000000..f3c6c7d --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = wdt + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/cmnos/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libcmnos.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/Makefile.ss new file mode 100755 index 0000000..d80e327 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/cmnos_wdt.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/inc/wdt_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/inc/wdt_api.h new file mode 100755 index 0000000..f480590 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/inc/wdt_api.h @@ -0,0 +1,56 @@ +#ifndef __WDT_API_H__ +#define __WDT_API_H__ +/* + * + */ + +typedef enum { + WDT_ACTION_NO = 0, // bit1, bit0: 00 + WDT_ACTION_INTR, // bit1, bit0: 01 + WDT_ACTION_NMI, // bit1, bit0: 10 + WDT_ACTION_RESET, // bit1, bit0: 11 + + WDT_ACTION_UNKNOWN +}T_WDT_ACTION_TYPE; + + +typedef enum { + WDT_TIMEOUT = 1, + WDT_ACTION, + + WDT_UNKNOWN +}T_WDT_CMD_TYPE; + +typedef struct { + uint32_t cmd; + union { + uint32_t timeout; + uint32_t action; + }; +}T_WDT_CMD; + + +typedef enum{ + ENUM_WDT_BOOT = 1, + ENUM_COLD_BOOT, + ENUM_SUSP_BOOT, + + // add above here + ENUM_UNKNOWN_BOOT +}T_BOOT_TYPE; + + +/*!- interface of watchdog timer + * + */ +struct wdt_api { + void (* _wdt_init)(void); + void (* _wdt_enable)(void); + void (* _wdt_disable)(void); + void (* _wdt_set)(T_WDT_CMD); + void (* _wdt_task)(void); + void (* _wdt_reset)(void); + T_BOOT_TYPE (*_wdt_last_boot)(void); +}; +#endif /* __WDT_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/src/cmnos_wdt.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/src/cmnos_wdt.c new file mode 100755 index 0000000..03dd02e --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/cmnos/wdt/src/cmnos_wdt.c @@ -0,0 +1,170 @@ + +#include "sys_cfg.h" + +#include "athos_api.h" + +#if SYSTEM_MODULE_WDT + + +typedef struct { + BOOLEAN state; + T_WDT_ACTION_TYPE action; + uint32_t timeout; +}T_WDT_CTRL; + + +LOCAL T_WDT_CTRL wdt_ctrl; + +/*!- Initialize watchdog timer + * + */ +LOCAL T_BOOT_TYPE +cmnos_wdt_last_boot(void) +{ +#if 0 + if (HAL_WORD_REG_READ(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR) & 0x80000000 ) + return ENUM_WDT_BOOT; + else + return ENUM_COLD_BOOT; +#endif + +#if defined(PROJECT_MAGPIE) + if ( *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) == WDT_MAGIC_PATTERN ) + return ENUM_WDT_BOOT; + else if ( *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) == SUS_MAGIC_PATTERN ) + return ENUM_SUSP_BOOT; + else + return ENUM_COLD_BOOT; +#elif defined(PROJECT_K2) + //if (HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR) == WDT_MAGIC_PATTERN || HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR) == SUS_MAGIC_PATTERN) + if ( HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR) == WDT_MAGIC_PATTERN ) + return ENUM_WDT_BOOT; + else if ( HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR) == SUS_MAGIC_PATTERN ) + return ENUM_SUSP_BOOT; + else + return ENUM_COLD_BOOT; +#endif /* #if defined(PROJECT_MAGPIE) */ +} + + +/*!- trigger a wdt reset. + * + */ +LOCAL void +cmnos_wdt_reset() +{ + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR, WDT_ACTION_RESET); + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_ADDR, 0x100); + while(1); // never return; +} + + +/*!- setup the timeout value. + * + */ +LOCAL void +cmnos_wdt_set(T_WDT_CMD wdt_cmd) +{ + switch(wdt_cmd.cmd) + { + case WDT_TIMEOUT: + if( wdt_cmd.timeout>0 ) //dummy check + { + wdt_ctrl.timeout = wdt_cmd.timeout; + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_ADDR, wdt_ctrl.timeout); + } + break; + + case WDT_ACTION: + if( wdt_cmd.action < WDT_ACTION_UNKNOWN ) + { + wdt_ctrl.action = wdt_cmd.action; + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR, wdt_ctrl.action); + } + } +} + + +/*!- Enable watchdog timer. + * + */ +LOCAL void +cmnos_wdt_enable() +{ + T_WDT_CMD wdt_cmd; + wdt_ctrl.state = TRUE; + + wdt_cmd.cmd = WDT_ACTION; + wdt_cmd.action = WDT_ACTION_RESET; + cmnos_wdt_set(wdt_cmd); + //HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR)|(BIT0|BIT1)); +} + +/*!- Disable watchdog timer. + * + */ +LOCAL void +cmnos_wdt_disable() +{ + T_WDT_CMD wdt_cmd; + + wdt_ctrl.state = FALSE; + + wdt_cmd.cmd = WDT_ACTION; + wdt_cmd.action = WDT_ACTION_NO; + cmnos_wdt_set(wdt_cmd); +// HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR)&(~(BIT0|BIT1)))); +// MAGPIE_REG_RST_WDT_TIMER_CTRL &= ~(BIT0|BIT1); +} + + +/*!- Initialize watchdog timer + * + */ +LOCAL void +cmnos_wdt_init(void) +{ + T_WDT_CMD wdt_cmd; + + //wdt_init_done = TRUE; + wdt_ctrl.state = FALSE; + wdt_ctrl.action = WDT_ACTION_NO; + wdt_ctrl.timeout = WDT_DEFAULT_TIMEOUT_VALUE; + + // should be init outside but just kick it ticking at here for workaround + cmnos_wdt_enable(); + + wdt_cmd.cmd = WDT_TIMEOUT; + wdt_cmd.timeout= wdt_ctrl.timeout; + cmnos_wdt_set(wdt_cmd); +} + + +/*!- update the watchdog timer timerout value. + * + */ +LOCAL void +cmnos_wdt_task() +{ + // if wdt is not enable, just skip the update + if( wdt_ctrl.state ) + { + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_WDT_TIMER_ADDR, wdt_ctrl.timeout); + } + +} + +void +cmnos_wdt_module_install(struct wdt_api *tbl) +{ + tbl->_wdt_init = cmnos_wdt_init; + tbl->_wdt_enable = cmnos_wdt_enable; + tbl->_wdt_disable = cmnos_wdt_disable; + tbl->_wdt_set = cmnos_wdt_set; + tbl->_wdt_task = cmnos_wdt_task; + tbl->_wdt_reset = cmnos_wdt_reset; + tbl->_wdt_last_boot = cmnos_wdt_last_boot; +} + +#endif /* SYSTEM_MODULE_WDT */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/Makefile new file mode 100755 index 0000000..c229d74 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/Makefile @@ -0,0 +1,61 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +#export LAYERNAME = rom +export SSNAME = dma_engine + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libdma.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/Makefile.ss new file mode 100755 index 0000000..2f1e7ef --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/dma_engine.o \ + $(SSOBJPATH)/desc.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/inc/dma_engine_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/inc/dma_engine_api.h new file mode 100755 index 0000000..6996cb8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/inc/dma_engine_api.h @@ -0,0 +1,92 @@ +/* + * @File: dma_engine_api.h + * + * @Abstract: DMA Engine api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _DMA_ENGINE_API_H +#define _DMA_ENGINE_API_H + +#include +#include + +struct zsDmaDesc +{ +#if 1 // BIG_ENDIAN + volatile u16_t ctrl; // Descriptor control + volatile u16_t status; // Descriptor status + volatile u16_t totalLen; // Total length + volatile u16_t dataSize; // Data size +#else + volatile u16_t status; // Descriptor status + volatile u16_t ctrl; // Descriptor control + volatile u16_t dataSize; // Data size + volatile u16_t totalLen; // Total length +#endif + struct zsDmaDesc* lastAddr; // Last address of this chain + volatile u32_t dataAddr; // Data buffer address + struct zsDmaDesc* nextAddr; // Next TD address +}; + +struct zsDmaQueue +{ + struct zsDmaDesc* head; + struct zsDmaDesc* terminator; +}; + +// Subclass of zsDmaQueue for TX +struct zsTxDmaQueue +{ + struct zsDmaDesc* head; + struct zsDmaDesc* terminator; + + /* Below are fields specific to TX */ + VBUF *xmited_buf_head; + VBUF *xmited_buf_tail; +}; + +/* hardware API table structure (API descriptions below) */ +struct dma_engine_api +{ + void (*_init)(); + + void (*_init_rx_queue)(struct zsDmaQueue *q); + + void (*_init_tx_queue)(struct zsTxDmaQueue *q); + + void (*_config_rx_queue)(struct zsDmaQueue *q, int num_desc, int buf_size); + + void (*_xmit_buf)(struct zsTxDmaQueue *q, VBUF *buf); + + void (*_flush_xmit)(struct zsDmaQueue *q); + + VBUF* (*_reap_recv_buf)(struct zsDmaQueue *q); + + void (*_return_recv_buf)(struct zsDmaQueue *q, VBUF *buf); + + VBUF* (*_reap_xmited_buf)(struct zsTxDmaQueue *q); + + void (*_swap_data)(struct zsDmaDesc* desc); + + int (*_has_compl_packets)(struct zsDmaQueue *q); + + void (*_desc_dump)(struct zsDmaQueue *q); + + /* The functions below are for patchable */ + struct zsDmaDesc* (*_get_packet)(struct zsDmaQueue* q); + void (*_reclaim_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc); + void (*_put_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void dma_engine_module_install(struct dma_engine_api *apis); + +#endif /* #ifndef _DMA_ENGINE_API_H */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/src/desc.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/src/desc.c new file mode 100755 index 0000000..40425a8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/src/desc.c @@ -0,0 +1,236 @@ +/************************************************************************/ +/* Copyright (c) 2013 Qualcomm Atheros, All Rights Reserved. */ +/* */ +/* Module Name : desc.c */ +/* */ +/* Abstract */ +/* This module contains DMA descriptors handle functions. */ +/* */ +/* ROUTINES */ +/* */ +/* zfDmaInitDescriptor */ +/* zfDmaGetPacket */ +/* zfDmaReclaimPacket */ +/* zfDmaPutPacket */ +/* */ +/* NOTES */ +/* None */ +/* */ +/************************************************************************/ +#include "dt_defs.h" +#include "string.h" +//#include "gv_extr.h" +#include "reg_defs.h" +//#include "uart_extr.h" +#include +//#include +//#include "HIF_usb.h" +#include +#include +#include "desc.h" + +/* Function prototypes */ +//void zfDmaInitDescriptor(void); +struct zsDmaDesc* zfDmaGetPacket(struct zsDmaQueue* q); +void zfDmaReclaimPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc); +void zfDmaPutPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc); + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfDmaGetPacket */ +/* Get a completed packet with # descriptors. Return the first */ +/* descriptor and pointer the head directly by lastAddr->nextAddr */ +/* */ +/* ROUTINES CALLED */ +/* */ +/* INPUTS */ +/* struct zsDmaQueue* q */ +/* */ +/* OUTPUTS */ +/* struct zsDmaDesc* desc */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Communication Corporation 2005.10 */ +/* */ +/* NOTES */ +/* */ +/************************************************************************/ +struct zsDmaDesc* zfDmaGetPacket(struct zsDmaQueue* q) +{ + struct zsDmaDesc* desc = NULL; + + if(q->head == q->terminator) + return NULL; + + if (((q->head->status & ZM_OWN_BITS_MASK) == ZM_OWN_BITS_SW) + || ((q->head->status & ZM_OWN_BITS_MASK) == ZM_OWN_BITS_SE)) + + //if ( (((q->head->status & ZM_OWN_BITS_MASK) == ZM_OWN_BITS_SW) && ((u32_t)q != (u32_t)&zgDnQ)) + // || (((q->head->status & ZM_OWN_BITS_MASK) == ZM_OWN_BITS_SE) && ((u32_t)q == (u32_t)&zgDnQ)) ) + + { + desc = q->head; + + q->head = desc->lastAddr->nextAddr; + } + return desc; +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfDmaReclaimPacket */ +/* Free descriptor. */ +/* Exchange the terminator and the first descriptor of the packet */ +/* for hardware ascy... . */ +/* */ +/* ROUTINES CALLED */ +/* */ +/* INPUTS */ +/* struct zsDmaQueue* q */ +/* struct zsDmaDesc* desc */ +/* */ +/* OUTPUTS */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Communication Corporation 2005.10 */ +/* */ +/* NOTES */ +/* */ +/************************************************************************/ +void zfDmaReclaimPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc) +{ + struct zsDmaDesc* tmpDesc; + struct zsDmaDesc tdesc; + VDESC *vdesc; + VDESC *vtermdesc; + //int tmp; + //u8_t *tmpAddr; + + /* 1. Set OWN bit to 1 for all TDs to be added, clear ctrl and size */ + tmpDesc = desc; + while (1) + { + tmpDesc->status = ZM_OWN_BITS_HW; + tmpDesc->ctrl = 0; + tmpDesc->totalLen = 0; + +#if ZM_FM_LOOPBACK == 1 + vdesc = VDESC_HW_TO_VDESC(tmpDesc); + tmpDesc->dataSize = vdesc->buf_size; +#endif + + //A_PRINTF("tmpDesc->dataSize = %d\n", (u32_t)tmpDesc->dataSize); + + /* TODO : Exception handle */ + if (desc->lastAddr == tmpDesc) + { + break; + } + tmpDesc = tmpDesc->nextAddr; + } + + /* 3. Next address of Last TD to be added = first TD */ + desc->lastAddr->nextAddr = desc; + + /* 2. Copy first TD to be added to TTD */ + //zfMemoryCopyInWord(&tdesc, desc, sizeof(struct zsDmaDesc)); + A_MEMCPY(&tdesc, desc, sizeof(struct zsDmaDesc)); + + /* 4. set first TD OWN bit to 0 */ + desc->status &= (~ZM_OWN_BITS_MASK); + + /* 5. Copy TTD to last TD */ + tdesc.status &= (~ZM_OWN_BITS_MASK); + + vdesc = VDESC_HW_TO_VDESC(desc); + vtermdesc = VDESC_HW_TO_VDESC(q->terminator); + + VDESC_swap_vdesc(vtermdesc, vdesc); + + //zfMemoryCopyInWord((void*)q->terminator, (void*)&tdesc, sizeof(struct zsDmaDesc)); + A_MEMCPY((void*)q->terminator, (void*)&tdesc, sizeof(struct zsDmaDesc)); + + //desc->dataSize = 0; + //desc->dataAddr = 0; + q->terminator->status |= ZM_OWN_BITS_HW; + + /* Update terminator pointer */ + q->terminator = desc; +} + +/************************************************************************/ +/* */ +/* FUNCTION DESCRIPTION zfDmaPutPacket */ +/* Put a complete packet into the tail of the Queue q. */ +/* Exchange the terminator and the first descriptor of the packet */ +/* for hardware ascy... . */ +/* */ +/* ROUTINES CALLED */ +/* */ +/* INPUTS */ +/* struct zsDmaQueue* q */ +/* struct zsDmaDesc* desc */ +/* */ +/* OUTPUTS */ +/* */ +/* AUTHOR */ +/* Stephen Chen ZyDAS Communication Corporation 2005.10 */ +/* */ +/* NOTES */ +/* */ +/************************************************************************/ +void zfDmaPutPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc) +{ + struct zsDmaDesc* tmpDesc; + struct zsDmaDesc tdesc; + VDESC *vdesc; + VDESC *vtermdesc; + //u32_t tmp; + //u8_t *tmpAddr; + + /* 1. Set OWN bit to 1 for all TDs to be added */ + tmpDesc = desc; + while (1) + { + tmpDesc->status = + ((tmpDesc->status & (~ZM_OWN_BITS_MASK)) | ZM_OWN_BITS_HW); + /* TODO : Exception handle */ + + if (desc->lastAddr == tmpDesc) + { + break; + } + tmpDesc = tmpDesc->nextAddr; + } + + /* 3. Next address of Last TD to be added = first TD */ + desc->lastAddr->nextAddr = desc; + + /* If there is only one descriptor, update pointer of last descriptor */ + if (desc->lastAddr == desc) + { + desc->lastAddr = q->terminator; + } + + /* 2. Copy first TD to be added to TTD */ + A_MEMCPY(&tdesc, desc, sizeof(struct zsDmaDesc)); + //tdesc.dataSize = 0; + //tdesc.dataAddr = 0; + + /* 4. set first TD OWN bit to 0 */ + desc->status &= (~ZM_OWN_BITS_MASK); + + /* 5. Copy TTD to last TD */ + tdesc.status &= (~ZM_OWN_BITS_MASK); + + vdesc = VDESC_HW_TO_VDESC(desc); + vtermdesc = VDESC_HW_TO_VDESC(q->terminator); + + VDESC_swap_vdesc(vtermdesc, vdesc); + + A_MEMCPY((void*)q->terminator, (void*)&tdesc, sizeof(struct zsDmaDesc)); + q->terminator->status |= ZM_OWN_BITS_HW; + /* Update terminator pointer */ + q->terminator = desc; +} + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/src/desc.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/src/desc.h new file mode 100755 index 0000000..989eca6 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/src/desc.h @@ -0,0 +1,144 @@ +/************************************************************************/ +/* Copyright (c) 2013 Qualcomm Atheros, All Rights Reserved. */ +/* */ +/* Module Name : desc_def.h */ +/* */ +/* Abstract */ +/* This module contains DMA descriptor related definitions. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/************************************************************************/ + +#ifndef _DESC_DEFS_H +#define _DESC_DEFS_H + +#if 0 +#define BIG_ENDIAN + +struct zsDmaDesc +{ +#ifdef BIG_ENDIAN + + volatile u16_t ctrl; // Descriptor control + volatile u16_t status; // Descriptor status + + volatile u16_t totalLen; // Total length + volatile u16_t dataSize; // Data size + +#else + volatile u16_t status; // Descriptor status + volatile u16_t ctrl; // Descriptor control + volatile u16_t dataSize; // Data size + volatile u16_t totalLen; // Total length +#endif + struct zsDmaDesc* lastAddr; // Last address of this chain + volatile u32_t dataAddr; // Data buffer address + struct zsDmaDesc* nextAddr; // Next TD address +}; +#endif + +/* Tx5 Dn Rx Up Int */ +#if 0 +#define ZM_TERMINATOR_NUMBER_B 8 + +#if ZM_BAR_AUTO_BA == 1 +#define ZM_TERMINATOR_NUMBER_BAR 1 +#else +#define ZM_TERMINATOR_NUMBER_BAR 0 +#endif + +#if ZM_INT_USE_EP2 == 1 +#define ZM_TERMINATOR_NUMBER_INT 1 +#else +#define ZM_TERMINATOR_NUMBER_INT 0 +#endif + +#define ZM_TX_DELAY_DESC_NUM 16 +#define ZM_TERMINATOR_NUMBER (8 + ZM_TERMINATOR_NUMBER_BAR + \ + ZM_TERMINATOR_NUMBER_INT + \ + ZM_TX_DELAY_DESC_NUM) + + +#define ZM_BLOCK_SIZE (256+64) +#define ZM_DESCRIPTOR_SIZE (sizeof(struct zsDmaDesc)) +#endif + +//#define ZM_FRAME_MEMORY_BASE 0x100000 +#if 0 +#if 1 +/* 64k */ +//#define ZM_FRAME_MEMROY_SIZE 0xf000 +/* 96k */ +//#define ZM_FRAME_MEMROY_SIZE 0x17000 + +#else +/* fake phy */ +/* 128k / 96k */ +#define ZM_FRAME_MEMROY_SIZE (ZM_BLOCK_SIZE+ZM_DESCRIPTOR_SIZE)*(160+60) + \ + (ZM_DESCRIPTOR_SIZE*ZM_TERMINATOR_NUMBER)+64 +#endif + +#define ZM_BLOCK_NUMBER ((ZM_FRAME_MEMROY_SIZE-(ZM_DESCRIPTOR_SIZE* \ + ZM_TERMINATOR_NUMBER)-64)/(ZM_BLOCK_SIZE \ + +ZM_DESCRIPTOR_SIZE)) +#define ZM_DESC_NUMBER (ZM_BLOCK_NUMBER + ZM_TERMINATOR_NUMBER) + +#define ZM_DESCRIPTOR_BASE ZM_FRAME_MEMORY_BASE +#define ZM_BLOCK_BUFFER_BASE (((((ZM_BLOCK_NUMBER+ZM_TERMINATOR_NUMBER) \ + *ZM_DESCRIPTOR_SIZE) >> 6) << 6) + 0x40 \ + + ZM_FRAME_MEMORY_BASE) + +#define ZM_DOWN_BLOCK_RATIO 2 +#define ZM_RX_BLOCK_RATIO 1 +/* Tx 16*2 = 32 packets => 32*(5*320) */ +#define ZM_TX_BLOCK_NUMBER ZM_BLOCK_NUMBER * ZM_DOWN_BLOCK_RATIO / \ + (ZM_RX_BLOCK_RATIO + ZM_DOWN_BLOCK_RATIO) +#define ZM_RX_BLOCK_NUMBER ZM_BLOCK_NUMBER-ZM_TX_BLOCK_NUMBER + //ZM_BLOCK_NUMBER * ZM_RX_BLOCK_RATIO / \ + //(ZM_RX_BLOCK_RATIO + ZM_DOWN_BLOCK_RATIO) + + +#define ZM_TX_DELAY_DESC_BASE ZM_FRAME_MEMORY_BASE + ZM_DESCRIPTOR_SIZE*(ZM_TERMINATOR_NUMBER-ZM_TX_DELAY_DESC_NUM) +#endif + +/* Erro code */ +#define ZM_ERR_FS_BIT 1 +#define ZM_ERR_LS_BIT 2 +#define ZM_ERR_OWN_BITS 3 +#define ZM_ERR_DATA_SIZE 4 +#define ZM_ERR_TOTAL_LEN 5 +#define ZM_ERR_DATA 6 +#define ZM_ERR_SEQ 7 +#define ZM_ERR_LEN 8 + +/* Status bits definitions */ +/* Own bits definitions */ +#define ZM_OWN_BITS_MASK 0x3 +#define ZM_OWN_BITS_SW 0x0 +#define ZM_OWN_BITS_HW 0x1 +#define ZM_OWN_BITS_SE 0x2 + +/* Control bits definitions */ +/* First segament bit */ +#define ZM_LS_BIT 0x100 +/* Last segament bit */ +#define ZM_FS_BIT 0x200 + +#if 0 +struct zsDmaQueue +{ + struct zsDmaDesc* head; + struct zsDmaDesc* terminator; +}; +#endif + +struct zsDmaQueue; +struct szDmaDesc; + +extern struct zsDmaDesc* zfDmaGetPacket(struct zsDmaQueue* q); +extern void zfDmaReclaimPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc); +extern void zfDmaPutPacket(struct zsDmaQueue* q, struct zsDmaDesc* desc); + +#endif /* #ifndef _DESC_DEFS_H */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/src/dma_engine.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/src/dma_engine.c new file mode 100755 index 0000000..e068b6c --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/dma_engine/src/dma_engine.c @@ -0,0 +1,386 @@ +/* + * @File: dma_engine.c + * + * @Abstract: DMA engine for Magpie + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ +#include "sys_cfg.h" +#include "dt_defs.h" +#include "reg_defs.h" +#include "desc.h" + +#include +//#include +#include +#include +#include +#include +#include + +//#include "HIF_usb.h" + +//HIF_USB_CONTEXT g_hifUSBCtx; + +#define VDESC_TO_USBDESC(vdesc) (struct zsDmaDesc *)((vdesc)->hw_desc_buf) + +static void relinkUSBDescToVdesc(VBUF *buf, struct zsDmaDesc* desc); +static void config_queue(struct zsDmaQueue *q, VDESC *desc_list); + +#if ENABLE_SW_SWAP_DATA_MODE +static void swapData(struct zsDmaDesc* usbDesc); +#endif + +static void init_usb_desc(struct zsDmaDesc *usbDesc) +{ + usbDesc->status = ZM_OWN_BITS_SW; + usbDesc->ctrl = 0; + usbDesc->dataSize = 0; + usbDesc->totalLen = 0; + usbDesc->lastAddr = 0; + usbDesc->dataAddr = 0; + usbDesc->nextAddr = 0; +} + +void _DMAengine_init() +{ + +} + +void _DMAengine_init_rx_queue(struct zsDmaQueue *q) +{ + VDESC *desc; + struct zsDmaDesc *usbDesc; + + desc = VDESC_alloc_vdesc(); + if ( desc != NULL ) { + usbDesc = VDESC_TO_USBDESC(desc); + init_usb_desc(usbDesc); + + q->head = q->terminator = usbDesc; + } +} + +void _DMAengine_init_tx_queue(struct zsTxDmaQueue *q) +{ + _DMAengine_init_rx_queue((struct zsDmaQueue *)q); + q->xmited_buf_head = NULL; + q->xmited_buf_tail = NULL; +} + +#if ENABLE_SW_SWAP_DATA_MODE + +static void swapData(struct zsDmaDesc* usbDesc) +{ + int len = (usbDesc->dataSize & 0xfffffffc) >> 2; + int i; + A_UINT32 *dataAddr = (A_UINT32 *)usbDesc->dataAddr; + A_UINT32 data; + + if ( ( usbDesc->dataSize & 3 ) != 0 ) { + len += 1; + } + + for ( i = 0; i < len; i++ ) { + data = dataAddr[i]; + + dataAddr[i] = __bswap32(data); + } +} + +#endif + +void _DMAengine_return_recv_buf(struct zsDmaQueue *q, VBUF *buf) +{ + /* Re-link the VDESC of buf into USB descriptor list & queue the descriptors + into downQ + */ + config_queue(q, buf->desc_list); + VBUF_free_vbuf(buf); +} + +static void config_queue(struct zsDmaQueue *q, VDESC *desc_list) +{ + VDESC *theDesc; + struct zsDmaDesc *usbDesc; + struct zsDmaDesc* prevUsbDesc = NULL; + struct zsDmaDesc* headUsbDesc; + + theDesc = desc_list; + while ( theDesc != NULL ) { + usbDesc = (struct zsDmaDesc *)VDESC_get_hw_desc(theDesc); + init_usb_desc(usbDesc); + + theDesc->data_offset = 0; //RAY 0723 + usbDesc->dataAddr = (volatile u32_t)(theDesc->buf_addr + theDesc->data_offset); + usbDesc->dataSize = theDesc->buf_size; + + if ( prevUsbDesc == NULL ) { + headUsbDesc = usbDesc; + prevUsbDesc = usbDesc; + } else { + prevUsbDesc->nextAddr = usbDesc; + prevUsbDesc = usbDesc; + } + + theDesc = theDesc->next_desc; + } + + headUsbDesc->lastAddr = prevUsbDesc; + DMA_Engine_reclaim_packet(q, headUsbDesc); + + return; +} + +//#define MAX_TX_BUF_SIZE ZM_BLOCK_SIZE +//#define MAX_TX_BUF_SIZE 1600 + +void _DMAengine_config_rx_queue(struct zsDmaQueue *q, int num_desc, int buf_size) +{ + int i; + VDESC *desc; + VDESC *head = NULL; + + for(i=0; i < num_desc; i++) + { + desc = VDESC_alloc_vdesc(); + + adf_os_assert(desc != NULL); + + desc->buf_addr = (A_UINT8 *)adf_os_mem_alloc(buf_size); + desc->buf_size = buf_size; + desc->next_desc = NULL; + desc->data_offset = 0; + desc->data_size = 0; + desc->control = 0; + + if ( head == NULL ) + { + head = desc; + } + else + { + desc->next_desc = head; + head = desc; + } + } + + config_queue(q, head); +} + +void _DMAengine_xmit_buf(struct zsTxDmaQueue *q, VBUF *buf) +{ + VDESC *currVdesc; + struct zsDmaDesc* usbDesc; + struct zsDmaDesc* prevUsbDesc = NULL; + struct zsDmaDesc* headUsbDesc; + + /* Re-link the VDESC of buf into USB descriptor list & queue the descriptors + into upQ + */ + currVdesc = (VDESC *)buf->desc_list; + while(currVdesc != NULL) { + + usbDesc = (struct zsDmaDesc *)currVdesc->hw_desc_buf; + + init_usb_desc(usbDesc); + usbDesc->dataSize = currVdesc->data_size; + usbDesc->dataAddr = (volatile u32_t)(currVdesc->buf_addr + currVdesc->data_offset); + usbDesc->ctrl = 0; + usbDesc->status = 0; + +#if ENABLE_SW_SWAP_DATA_MODE && ENABLE_SWAP_DATA_MODE == 0 + swapData(usbDesc); +#endif + + if ( prevUsbDesc == NULL ) { + headUsbDesc = usbDesc; + + usbDesc->ctrl |= ZM_FS_BIT; + + // how to get the total len??? + usbDesc->totalLen = buf->buf_length; + prevUsbDesc = usbDesc; + } + else { + prevUsbDesc->nextAddr = usbDesc; + prevUsbDesc = usbDesc; + } + + currVdesc = currVdesc->next_desc; + } + + usbDesc->ctrl |= ZM_LS_BIT; + headUsbDesc->lastAddr = usbDesc; + + if ( q->xmited_buf_head == NULL && q->xmited_buf_tail == NULL ) { + q->xmited_buf_head = buf; + q->xmited_buf_tail = buf; + q->xmited_buf_head->next_buf = q->xmited_buf_tail; + } + else { + q->xmited_buf_tail->next_buf = buf; + q->xmited_buf_tail = buf; + } + + DMA_Engine_put_packet((struct zsDmaQueue *)q, headUsbDesc); +} + +void _DMAengine_flush_xmit(struct zsDmaQueue *q) +{ +} + +int _DMAengine_has_compl_packets(struct zsDmaQueue *q) +{ + int has_compl_pkts = 0; + + if ((q->head != q->terminator) && + ((q->head->status & ZM_OWN_BITS_MASK) != ZM_OWN_BITS_HW)) { + has_compl_pkts = 1; + } + + return has_compl_pkts; +} + +VBUF* _DMAengine_reap_recv_buf(struct zsDmaQueue *q) +{ + struct zsDmaDesc* desc; + VBUF *buf; + //int i; + //u8_t *tbuf = (u8_t *)desc->dataAddr; + + desc = DMA_Engine_get_packet(q); + + if(!desc) + return NULL; + +#if ENABLE_SW_SWAP_DATA_MODE && ENABLE_SWAP_DATA_MODE == 0 + swapData(desc); +#endif + + buf = VBUF_alloc_vbuf(); + adf_os_assert(buf != NULL); + + relinkUSBDescToVdesc(buf, desc); + return buf; +} + +VBUF* _DMAengine_reap_xmited_buf(struct zsTxDmaQueue *q) +{ + struct zsDmaDesc* desc; + VBUF *sentBuf; + + desc = DMA_Engine_get_packet((struct zsDmaQueue *)q); + + if(!desc) + return NULL; + + // assert g_hifUSBCtx.upVbufQ.head is not null + // assert g_hifUSBCtx.upVbufQ.tail is not null + sentBuf = q->xmited_buf_head; + if ( q->xmited_buf_head == q->xmited_buf_tail ) { + q->xmited_buf_head = NULL; + q->xmited_buf_tail = NULL; + } else { + q->xmited_buf_head = q->xmited_buf_head->next_buf; + } + + sentBuf->next_buf = NULL; + relinkUSBDescToVdesc(sentBuf, desc); + return sentBuf; +} + +void _DMAengine_desc_dump(struct zsDmaQueue *q) +{ + u32_t i=0; + struct zsDmaDesc* tmpDesc; + + tmpDesc = q->head; + + do { + if( tmpDesc == q->terminator ) + { +#ifdef DESC_DUMP_BOTH_DESCnDATA + A_PRINTF("0x%08x(0x%08x,T)]", tmpDesc, tmpDesc->dataAddr); +#else + A_PRINTF("0x%08x(T)]", tmpDesc); +#endif + break; + } + else +#ifdef DESC_DUMP_BOTH_DESCnDATA + A_PRINTF("0x%08x(0x%08x,%c)->", tmpDesc, tmpDesc->dataAddr, (tmpDesc->status&ZM_OWN_BITS_HW)?'H':'S'); +#else + A_PRINTF("0x%08x(%c)->", tmpDesc, (tmpDesc->status&ZM_OWN_BITS_HW)?'H':'S'); +#endif + + if( (++i%5)==0 ) + { + A_PRINTF("\n\r "); + } + + tmpDesc = tmpDesc->nextAddr; + }while(1); + A_PRINTF("\n\r"); +} + +/* the exported entry point into this module. All apis are accessed through + * function pointers */ +void dma_engine_module_install(struct dma_engine_api *apis) +{ + /* hook in APIs */ + apis->_init = _DMAengine_init; + apis->_config_rx_queue = _DMAengine_config_rx_queue; + apis->_xmit_buf = _DMAengine_xmit_buf; + apis->_flush_xmit = _DMAengine_flush_xmit; + apis->_reap_recv_buf = _DMAengine_reap_recv_buf; + apis->_return_recv_buf = _DMAengine_return_recv_buf; + apis->_reap_xmited_buf = _DMAengine_reap_xmited_buf; + apis->_swap_data = swapData; + apis->_has_compl_packets = _DMAengine_has_compl_packets; + apis->_init_rx_queue = _DMAengine_init_rx_queue; + apis->_init_tx_queue = _DMAengine_init_tx_queue; + apis->_desc_dump = _DMAengine_desc_dump; + apis->_get_packet = zfDmaGetPacket; + apis->_reclaim_packet = zfDmaReclaimPacket; + apis->_put_packet = zfDmaPutPacket; + + /* save ptr to the ptr to the context for external code to inspect/modify internal module state */ + //apis->pReserved = &g_pMboxHWContext; +} + +static void relinkUSBDescToVdesc(VBUF *buf, struct zsDmaDesc* desc) +{ + VDESC *vdesc; + VDESC *prevVdesc = NULL; + struct zsDmaDesc *currDesc = desc; + + vdesc = VDESC_HW_TO_VDESC(currDesc); + buf->desc_list = vdesc; + buf->buf_length = currDesc->totalLen; + + while(currDesc != NULL) { + vdesc->data_size = currDesc->dataSize; + //vdesc->data_offset = 0; // TODO: bad!! + + if ( prevVdesc == NULL ) { + prevVdesc = vdesc; + } else { + prevVdesc->next_desc = vdesc; + prevVdesc = vdesc; + } + + if ( currDesc->ctrl & ZM_LS_BIT ) { + vdesc->next_desc = NULL; + currDesc = NULL; + break; + } else { + currDesc = currDesc->nextAddr; + vdesc = VDESC_HW_TO_VDESC(currDesc); + } + } +} diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/Makefile new file mode 100755 index 0000000..7ac4980 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/Makefile @@ -0,0 +1,60 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export SSNAME = fwd + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libfwd.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/Makefile.ss new file mode 100755 index 0000000..0942974 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/ + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/fwd.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/fwd.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/fwd.c new file mode 100755 index 0000000..f01efb1 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/fwd.c @@ -0,0 +1,133 @@ +#include +#include +#include +#include +#include +#include +#include + +#include "fwd.h" + +fwd_tgt_softc_t fwd_sc; + +void fwd_tgt_recv(VBUF *hdr_buf, VBUF *buf, void *ctx ); +void fwd_retbuf_handler(VBUF *buf, void *ServiceCtx); + +hif_handle_t fwd_init() + { + HIF_CALLBACK hifconfig; + A_UINT32 size, res_headroom; + + hifconfig.send_buf_done = fwd_retbuf_handler; + hifconfig.recv_buf = fwd_tgt_recv; + hifconfig.context = &fwd_sc; + + res_headroom = HIF_get_reserved_headroom(NULL); + + size = sizeof(fwd_rsp_t) + res_headroom; + + HIF_register_callback(NULL, &hifconfig); + + HIF_get_default_pipe(NULL, &fwd_sc.rx_pipe, &fwd_sc.tx_pipe); + + return NULL; + } + +void +fwd_retbuf_handler(VBUF *buf, void *ServiceCtx) +{ + HIF_return_recv_buf(fwd_sc.hif_handle, fwd_sc.rx_pipe, buf); +} + +a_status_t +fwd_tgt_process_last(A_UINT32 size, A_UINT32 cksum) +{ + int i, checksum = 0; + A_UINT32 *image = (A_UINT32 *)fwd_sc.addr; + + for (i = 0 ; i < size; i += 4, image++) + checksum = checksum ^ *image; + + if (checksum == cksum) + return A_STATUS_OK; + else + return A_STATUS_FAILED; +} + + + +void +fwd_tgt_recv(VBUF *hdr_buf, VBUF *buf, void *ctx ) +{ + volatile a_uint8_t *data; + A_UINT32 len, seglen, offset, i, more, eloc; + volatile A_UINT32 *image, *daddr; + volatile fwd_cmd_t *c; + volatile fwd_rsp_t *r; + jmp_func funcptr; + a_status_t status; + VDESC *desc = NULL; + + data = buf->desc_list->buf_addr + buf->desc_list->data_offset; + seglen = buf->desc_list->data_size; + + c = (fwd_cmd_t *)data; + len = c->len; + offset = c->offset; + more = c->more_data; + image = (A_UINT32 *)(c + 1); + + if (offset == 0) { + fwd_sc.addr = (A_UINT32)(*image); + image ++; + } + + daddr = (A_UINT32 *)(fwd_sc.addr + offset); + + if (!more) { + len -= 4; + } + + for (i = 0 ; i < len; i += 4) { + *daddr = *image; + image ++; + daddr ++; + } + + desc = buf->desc_list; + while(desc->next_desc != NULL) + desc = desc->next_desc; + desc->data_size -= seglen; + buf->buf_length -= seglen; + + r = (fwd_rsp_t *)(desc->buf_addr + desc->data_offset + desc->data_size); + desc->data_size += sizeof(fwd_rsp_t); + buf->buf_length += sizeof(fwd_rsp_t); + + r->offset = c->offset; + + if (more) { + r->rsp = FWD_RSP_ACK; + goto done; + } + + status = fwd_tgt_process_last(offset + len, *image); + + /* reach to the jump location */ + image++; + eloc = *image; + + if (status == A_STATUS_OK) + r->rsp = FWD_RSP_SUCCESS; + else + r->rsp = FWD_RSP_FAILED; + + +done: + HIF_send_buffer(fwd_sc.hif_handle, fwd_sc.tx_pipe, buf); + + if (!more && (status == A_STATUS_OK)) { + funcptr = (jmp_func)eloc; + funcptr(); + } +} diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/fwd.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/fwd.h new file mode 100755 index 0000000..37d5e97 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/fwd/fwd.h @@ -0,0 +1,42 @@ +#ifndef __FWD_H +#define __FWD_H + +#define FWD_TGT_RX_BUFS 5 + +typedef void (*jmp_func)(void); +/* + * XXX Pack 'em + */ +typedef struct { + a_uint16_t more_data; /* Is there more data? */ + a_uint16_t len; /* Len this segment */ + a_uint32_t offset; /* Offset in the file */ +} fwd_cmd_t; +/* + * No enums across platforms + */ +#define FWD_RSP_ACK 0x1 +#define FWD_RSP_SUCCESS 0x2 +#define FWD_RSP_FAILED 0x3 + +typedef struct { + a_uint32_t rsp; /* ACK/SUCCESS/FAILURE */ + a_uint32_t offset; /* rsp for this ofset */ +}fwd_rsp_t; + +typedef struct { + a_uint32_t addr; + hif_handle_t hif_handle; + a_uint8_t rx_pipe; + a_uint8_t tx_pipe; +} fwd_tgt_softc_t; + + +hif_handle_t fwd_init(); + +void +fwd_retbuf_handler(VBUF *buf, void *ServiceCtx); +void +fwd_hifrecv_handler(VBUF *hdr_buf, VBUF *buf, void *ServiceCtx ); + +#endif //__FWD_H diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/Makefile new file mode 100755 index 0000000..0a41561 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/Makefile @@ -0,0 +1,63 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = hif + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/ + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +DIRS = pci \ + usb \ + gmac \ + dma_lib + + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libhif.a + + +# +# Targets +# + +all : + for i in $(DIRS) ; do $(MAKE) -C $$i all || exit $? ; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + +dep: + for i in $(DIRS) ; do $(MAKE) -C $$i dep || exit $? ; done + +clean: + for i in $(DIRS) ; do $(MAKE) -C $$i clean; done + +init: + for i in $(DIRS) ; do $(MAKE) -C $$i init; done + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/dma_lib/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/dma_lib/Makefile new file mode 100755 index 0000000..44e27e2 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/dma_lib/Makefile @@ -0,0 +1,51 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = hif +export SSNAME = dma_lib + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/dma_lib/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/dma_lib/Makefile.ss new file mode 100755 index 0000000..a563897 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/dma_lib/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/ + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/dma_lib.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/dma_lib/dma_lib.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/dma_lib/dma_lib.c new file mode 100755 index 0000000..05dc49f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/dma_lib/dma_lib.c @@ -0,0 +1,421 @@ +#include +#include +#include +#include +#include +#include + +#include "dma_lib.h" +/***********************Constants***************************/ + +/** + * @brief Descriptor specific bitmaps + */ +enum __dma_desc_status{ + DMA_STATUS_OWN_DRV = 0x0, + DMA_STATUS_OWN_DMA = 0x1, + DMA_STATUS_OWN_MSK = 0x3 +}; + +enum __dma_bit_op{ + DMA_BIT_CLEAR = 0x0, + DMA_BIT_SET = 0x1 +}; + +enum __dma_burst_size{ + DMA_BURST_4W = 0x00, + DMA_BURST_8W = 0x01, + DMA_BURST_16W = 0x02 +}; +enum __dma_byte_swap{ + DMA_BYTE_SWAP_OFF = 0x00, + DMA_BYTE_SWAP_ON = 0x01 +}; +/** +* @brief Interrupt status bits + */ +typedef enum __dma_intr_bits{ + DMA_INTR_TX1_END = (1 << 25),/*TX1 reached the end or Under run*/ + DMA_INTR_TX0_END = (1 << 24),/*TX0 reached the end or Under run*/ + DMA_INTR_TX1_DONE = (1 << 17),/*TX1 has transmitted a packet*/ + DMA_INTR_TX0_DONE = (1 << 16),/*TX1 has transmitted a packet*/ + DMA_INTR_RX3_END = (1 << 11),/*RX3 reached the end or Under run*/ + DMA_INTR_RX2_END = (1 << 10),/*RX2 reached the end or Under run*/ + DMA_INTR_RX1_END = (1 << 9), /*RX1 reached the end or Under run*/ + DMA_INTR_RX0_END = (1 << 8), /*RX0 reached the end or Under run*/ + DMA_INTR_RX3_DONE = (1 << 3), /*RX3 received a packet*/ + DMA_INTR_RX2_DONE = (1 << 2), /*RX2 received a packet*/ + DMA_INTR_RX1_DONE = (1 << 1), /*RX1 received a packet*/ + DMA_INTR_RX0_DONE = 1, /*RX0 received a packet*/ +}__dma_intr_bits_t; +/** + * @brief Base addresses for various HIF + */ +typedef enum __dma_base_off{ + DMA_BASE_OFF_HST = 0x00053000, + DMA_BASE_OFF_GMAC = 0x00054000, + DMA_BASE_OFF_PCI = DMA_BASE_OFF_HST, + DMA_BASE_OFF_PCIE = DMA_BASE_OFF_HST +}__dma_base_off_t; +/** + * @brief Engine offset to add for per engine register reads or + * writes + */ +typedef enum __dma_eng_off{ + DMA_ENG_OFF_RX0 = 0x800, + DMA_ENG_OFF_RX1 = 0x900, + DMA_ENG_OFF_RX2 = 0xa00, + DMA_ENG_OFF_RX3 = 0xb00, + DMA_ENG_OFF_TX0 = 0xc00, + DMA_ENG_OFF_TX1 = 0xd00 +}__dma_eng_off_t; +/** + *@brief DMA registers + */ +typedef enum __dma_reg_off{ + /** + * Common or Non Engine specific + */ + DMA_REG_IFTYPE = 0x00,/*XXX*/ + DMA_REG_ISR = 0x00,/*Interrupt Status Register*/ + DMA_REG_IMR = 0x04,/*Interrupt Mask Register*/ + /** + * Transmit + */ + DMA_REG_TXDESC = 0x00,/*TX DP*/ + DMA_REG_TXSTART = 0x04,/*TX start*/ + DMA_REG_INTRLIM = 0x08,/*TX Interrupt limit*/ + DMA_REG_TXBURST = 0x0c,/*TX Burst Size*/ + DMA_REG_TXSWAP = 0x18, + /** + * Receive + */ + DMA_REG_RXDESC = 0x00,/*RX DP*/ + DMA_REG_RXSTART = 0x04,/*RX Start*/ + DMA_REG_RXBURST = 0x08,/*RX Burst Size*/ + DMA_REG_RXPKTOFF = 0x0c,/*RX Packet Offset*/ + DMA_REG_RXSWAP = 0x1c +}__dma_reg_off_t; + +/*******************************Data types******************************/ + +typedef struct zsDmaDesc __dma_desc_t; + +typedef struct zsDmaQueue __dma_rxq_t; + +typedef struct zsTxDmaQueue __dma_txq_t; + +/** + * @brief Register Address + */ +typedef struct __dma_reg_addr{ + __dma_base_off_t base;/*Base address, Fixed*/ + __dma_eng_off_t eng;/*Engine offset, Fixed*/ +}__dma_reg_addr_t; + +/** + * @brief DMA engine's Queue + */ +typedef struct __dma_eng_q{ + __dma_reg_addr_t addr; + union{ + __dma_rxq_t rx_q; + __dma_txq_t tx_q; + }u; +}__dma_eng_q_t; + +#define rxq u.rx_q +#define txq u.tx_q + +/***********************Defines*****************************/ + +#define DMA_ADDR_INIT(_eng) { \ + .base = DMA_BASE_OFF_HST, \ + .eng = DMA_ENG_OFF_##_eng \ +} +/** + * @brief check if the val doesn't lie between the low & high of + * the engine numbers + */ +#define DMA_ENG_CHECK(_val, _low, _high) \ + ((_val) < DMA_ENGINE_##_low || (_val) > DMA_ENGINE_##_high) + + +/********************************Globals*************************************/ + +__dma_eng_q_t eng_q[DMA_ENGINE_MAX] = { + {.addr = DMA_ADDR_INIT(RX0)}, + {.addr = DMA_ADDR_INIT(RX1)}, + {.addr = DMA_ADDR_INIT(RX2)}, + {.addr = DMA_ADDR_INIT(RX3)}, + {.addr = DMA_ADDR_INIT(TX0)}, + {.addr = DMA_ADDR_INIT(TX1)}, +}; + +/**********************************API's*************************************/ + +/** + * @brief Read the register + * + * @param addr + * + * @return A_UINT32 + */ +A_UINT32 +__dma_reg_read(A_UINT32 addr) +{ + return *((volatile A_UINT32 *)addr); +} +/** + * @brief Write into the register + * + * @param addr + * @param val + */ +void +__dma_reg_write(A_UINT32 addr, A_UINT32 val) +{ + *((volatile A_UINT32 *)addr) = val; +} +/** + * @brief Set the base address + * + * @param eng_no + * @param if_type + */ +void +__dma_set_base(dma_engine_t eng_no, dma_iftype_t if_type) +{ + switch (if_type) { + case DMA_IF_GMAC: + eng_q[eng_no].addr.base = DMA_BASE_OFF_GMAC; + break; + case DMA_IF_PCI: + eng_q[eng_no].addr.base = DMA_BASE_OFF_PCI; + break; + case DMA_IF_PCIE: + eng_q[eng_no].addr.base = DMA_BASE_OFF_PCIE; + break; + default: + return; + } +} +/** + * @brief init the Transmit queue + * + * @param eng_no + * @param if_type + * + * @return A_UINT16 + */ +A_UINT16 +__dma_lib_tx_init(dma_engine_t eng_no, dma_iftype_t if_type) +{ + __dma_desc_t *head = NULL; + A_UINT32 addr; + + if(DMA_ENG_CHECK(eng_no, TX0, TX1)) + return 1; + + DMA_Engine_init_tx_queue(&eng_q[eng_no].txq); + + __dma_set_base(eng_no, if_type); + + addr = eng_q[eng_no].addr.base + eng_q[eng_no].addr.eng; + + head = eng_q[eng_no].txq.head; + + __dma_reg_write(addr + DMA_REG_TXDESC,(A_UINT32)head); + __dma_reg_write(addr + DMA_REG_TXBURST, DMA_BURST_16W); + __dma_reg_write(addr + DMA_REG_TXSWAP, DMA_BYTE_SWAP_ON); + + return 0; +} + +void +__dma_lib_rx_config(dma_engine_t eng_no, A_UINT16 num_desc, + A_UINT16 gran) +{ + __dma_desc_t *desc = NULL; + A_UINT32 addr = 0; + + /** + * Allocate the Receive Queue + */ + DMA_Engine_config_rx_queue(&eng_q[eng_no].rxq, num_desc, gran); + + desc = eng_q[eng_no].rxq.head; + addr = eng_q[eng_no].addr.base + eng_q[eng_no].addr.eng; + /** + * Update RX queue head in the H/W, set the burst & say go + */ + __dma_reg_write(addr + DMA_REG_RXDESC, (A_UINT32)desc); + __dma_reg_write(addr + DMA_REG_RXBURST, DMA_BURST_8W); + __dma_reg_write(addr + DMA_REG_RXSWAP, DMA_BYTE_SWAP_ON); + __dma_reg_write(addr + DMA_REG_RXSTART, DMA_BIT_SET); + +} + +/** + * @brief Initialize the DMA engine + * + * @param rx_desc + * + * @return A_UINT16 + */ +A_UINT16 +__dma_lib_rx_init(dma_engine_t eng_no, dma_iftype_t if_type) +{ + if(DMA_ENG_CHECK(eng_no, RX0, RX3)) + return 1; + + /** + * XXX:The init can be called multiple times to setup different + * geometries of descriptors + */ + DMA_Engine_init_rx_queue(&eng_q[eng_no].rxq); + + __dma_set_base(eng_no, if_type); + + return 0; +} +/** + * @brief Transmit VBUF for the specified engine number + * + * @param VBUF + * + * @return A_UINT16 + */ +A_UINT16 +__dma_hard_xmit(dma_engine_t eng_no, VBUF *vbuf) +{ + A_UINT32 addr; + + addr = eng_q[eng_no].addr.base + eng_q[eng_no].addr.eng; + + DMA_Engine_xmit_buf(&eng_q[eng_no].txq, vbuf); + /** + * Say go + */ + __dma_reg_write(addr + DMA_REG_TXSTART, DMA_BIT_SET); +} +/** + * @brief return a VBUF for the specified engine number + * + * @param eng_no + * + * @return VBUF* + */ +VBUF * +__dma_reap_xmitted(dma_engine_t eng_no) +{ + return DMA_Engine_reap_xmited_buf(&eng_q[eng_no].txq); +} +/** + * @brief flush all xmitted & to be xmitted (if you have the + * window) dudes from H/W + * + * @param eng_no + */ +void +__dma_flush_xmit(dma_engine_t eng_no) +{ + A_UINT32 addr; + __dma_desc_t *desc, *term; + + addr = eng_q[eng_no].addr.base + eng_q[eng_no].addr.eng; + + desc = eng_q[eng_no].txq.head; + term = eng_q[eng_no].txq.terminator; + + /** + * XXX: I don't know how to kick the all dudes out, Ideally + * there should be a DMA reset button (the red one) + */ + __dma_reg_write(addr + DMA_REG_TXSTART, DMA_BIT_CLEAR); + __dma_reg_write(addr + DMA_REG_TXDESC,(A_UINT32)term); + + /** + * Make the H/W queue ready for TX reap + */ + for(;desc != term; desc = desc->nextAddr) + desc->status = DMA_STATUS_OWN_DRV; + +// DMA_Engine_flush_xmit(&eng_q[eng_no].txq); +} +/** + * @brief check if there are xmitted vbufs (dudes) hanging + * around + * + * @param eng_no + * + * @return A_UINT16 + */ +A_UINT16 +__dma_xmit_done(dma_engine_t eng_no) +{ + if(DMA_ENG_CHECK(eng_no, TX0, TX1)) + return 0; + + return DMA_Engine_has_compl_packets(&eng_q[eng_no].txq); +} +/** + * @brief Reap VBUF's from the specified engine number + * + * @param eng + * + * @return VBUF* + */ +VBUF * +__dma_reap_recv(dma_engine_t eng) +{ + return DMA_Engine_reap_recv_buf(&eng_q[eng].rxq); +} +/** + * @brief return to source, put the vbuf back into the queue, In + * case the Engine is stopped so start it again + * + * @param eng_no + * @param vbuf + */ +void +__dma_return_recv(dma_engine_t eng_no, VBUF *vbuf) +{ + A_UINT32 addr; + + addr = eng_q[eng_no].addr.base + eng_q[eng_no].addr.eng; + + DMA_Engine_return_recv_buf(&eng_q[eng_no].rxq, vbuf); + + __dma_reg_write(addr + DMA_REG_RXSTART, DMA_BIT_SET); +} +/** + * @brief check if there are freshly arrived vbufs (dudes) + * + * @param eng_no + * + * @return A_UINT16 + */ +A_UINT16 +__dma_recv_pkt(dma_engine_t eng_no) +{ + if(DMA_ENG_CHECK(eng_no, RX0, RX3)) + return 0; + + return DMA_Engine_has_compl_packets(&eng_q[eng_no].rxq); +} + +void +dma_lib_module_install(struct dma_lib_api *apis) +{ + apis->tx_init = __dma_lib_tx_init; + apis->rx_init = __dma_lib_rx_init; + apis->rx_config = __dma_lib_rx_config; + apis->hard_xmit = __dma_hard_xmit; + apis->flush_xmit = __dma_flush_xmit; + apis->xmit_done = __dma_xmit_done; + apis->reap_recv = __dma_reap_recv; + apis->reap_xmitted = __dma_reap_xmitted; + apis->return_recv = __dma_return_recv; + apis->recv_pkt = __dma_recv_pkt; +} diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/gmac/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/gmac/Makefile new file mode 100755 index 0000000..5b4b872 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/gmac/Makefile @@ -0,0 +1,51 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = hif +export SSNAME = gmac + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SSNAME)/ + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/gmac/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/gmac/Makefile.ss new file mode 100755 index 0000000..cc817a4 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/gmac/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/ + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/hif_gmac.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/gmac/hif_gmac.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/gmac/hif_gmac.c new file mode 100755 index 0000000..9dbc93b --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/gmac/hif_gmac.c @@ -0,0 +1,1103 @@ +#include +#include + +//#include +#include + +#include + +#include +#include +#include +#include +#include "hif_gmac.h" + + + +/**************************Constants******************************/ +enum __gmac_msg_type{ + GMAC_HST_QUERY = 0x0001, + GMAC_HST_REPLY = 0x0002, + GMAC_TGT_QUERY = 0x0003, + GMAC_TGT_REPLY = 0x0004 +}; + +enum __magpie_regs{ + MAG_REG_GPIO_OE = 0x00052000,/*GPIO Output Enable*/ + MAG_REG_RST = 0x00050010,/*Magpie reset reg*/ + MAG_REG_RST_AHB = 0x00050018,/*Magpie AHB_ARB reset reg*/ + MAG_REG_MII0_CTRL = 0x00054100,/*Magpie MII0 Control reg*/ + MAG_REG_STAT_CTRL = 0x00054104,/*Magpie Status reg*/ + MAG_REG_MDIO = 0x00054200,/*Mapie MDIO register*/ + MAG_REG_MDIO_CMD = 0x00 + MAG_REG_MDIO,/*CMD register (0)*/ + MAG_REG_MDIO_OWN = 0x02 + MAG_REG_MDIO,/*OWN register (1)*/ + /** + * XXX: Endianess inside the word & between words + */ + MAG_REG_MDIO_ADDR0 = 0x04 + MAG_REG_MDIO,/*ADDR0 register (2)*/ + MAG_REG_MDIO_ADDR1 = 0x06 + MAG_REG_MDIO,/*ADDR1 register (3)*/ + MAG_REG_MDIO_WRITE0 = 0x08 + MAG_REG_MDIO,/*Data WRITE0 register (4)*/ + MAG_REG_MDIO_WRITE1 = 0x0a + MAG_REG_MDIO,/*Data WRITE1 register (5)*/ + MAG_REG_MDIO_READ0 = 0x0c + MAG_REG_MDIO,/*Data READ0 register (6)*/ + MAG_REG_MDIO_READ1 = 0x0e + MAG_REG_MDIO,/*Data READ1 register (7)*/ +}; + +enum __gmac_regs{ + GMAC_REG_BASE = 0x00060000, + GMAC_REG_MAC_CFG1 = 0x00 + GMAC_REG_BASE,/*MAC config 1*/ + GMAC_REG_MAC_CFG2 = 0x04 + GMAC_REG_BASE,/*MAC config 2*/ + GMAC_REG_IPG_IFG = 0x08 + GMAC_REG_BASE,/*Inter-packet-gap*/ + GMAC_REG_HALF_DPLX = 0x0c + GMAC_REG_BASE,/*Half duplex*/ + GMAC_REG_MAX_FRAME = 0x10 + GMAC_REG_BASE,/*Max frame length*/ + GMAC_REG_MII_CFG = 0x20 + GMAC_REG_BASE,/*MII mgmt config*/ + GMAC_REG_MII_CMD = 0x24 + GMAC_REG_BASE,/*MII mgmt command*/ + GMAC_REG_MII_ADDR = 0x28 + GMAC_REG_BASE,/*MII mgmt address*/ + GMAC_REG_MII_CTRL = 0x2c + GMAC_REG_BASE,/*MII mgmt control*/ + GMAC_REG_MII_STAT = 0x30 + GMAC_REG_BASE,/*MII mgmt status*/ + GMAC_REG_MII_PSTAT = 0x34 + GMAC_REG_BASE,/*MII mgmt Phy status/ind*/ + GMAC_REG_IF_CTRL = 0x38 + GMAC_REG_BASE,/*Interface control*/ + GMAC_REG_IF_STAT = 0x3c + GMAC_REG_BASE,/*Interface status*/ + GMAC_REG_MAC_ADDR1 = 0x40 + GMAC_REG_BASE,/*MAC address 1*/ + GMAC_REG_MAC_ADDR2 = 0x44 + GMAC_REG_BASE,/*MAC address 2*/ + GMAC_REG_FIFO_CFG0 = 0x48 + GMAC_REG_BASE,/*FIFO config reg0*/ + GMAC_REG_FIFO_CFG1 = 0x4c + GMAC_REG_BASE,/*FIFO config reg1*/ + GMAC_REG_FIFO_CFG2 = 0x50 + GMAC_REG_BASE,/*FIFO config reg2*/ + GMAC_REG_FIFO_CFG3 = 0x54 + GMAC_REG_BASE,/*FIFO config reg3*/ + GMAC_REG_FIFO_CFG4 = 0x58 + GMAC_REG_BASE,/*FIFO config reg4*/ + GMAC_REG_FIFO_CFG5 = 0x5c + GMAC_REG_BASE,/*FIFO config reg5*/ + GMAC_REG_FIFO_RAM0 = 0x60 + GMAC_REG_BASE,/*FIFO RAM access reg0*/ + GMAC_REG_FIFO_RAM1 = 0x64 + GMAC_REG_BASE,/*FIFO RAM access reg1*/ + GMAC_REG_FIFO_RAM2 = 0x68 + GMAC_REG_BASE,/*FIFO RAM access reg2*/ + GMAC_REG_FIFO_RAM3 = 0x6c + GMAC_REG_BASE,/*FIFO RAM access reg3*/ + GMAC_REG_FIFO_RAM4 = 0x70 + GMAC_REG_BASE,/*FIFO RAM access reg4*/ + GMAC_REG_FIFO_RAM5 = 0x74 + GMAC_REG_BASE,/*FIFO RAM access reg5*/ + GMAC_REG_FIFO_RAM6 = 0x78 + GMAC_REG_BASE,/*FIFO RAM access reg6*/ + GMAC_REG_FIFO_RAM7 = 0x7c + GMAC_REG_BASE,/*FIFO RAM access reg7*/ +}; + +enum __mag_reg_rst{ + RST_GMAC = (1 << 9),/*Reset the GMAC */ + RST_MII = (3 << 11),/*Reset the MII*/ + RST_OTHERS = 0x5df,/*Reset everybody other than GMAC & MII*/ +}; + +enum __mag_reg_rst_ahb{ + RST_AHB_GMAC = 0x1 +}; +enum __mag_mii0_ctrl{ + MII0_CTRL_MODE = (1 << 0),/*MII mode*/ + MII0_CTRL_100 = (1 << 4),/*MII control address 100 Mbps*/ +}; + +enum __mag_mdio_cmd{ + MDIO_CMD_DONE = 0x01,/*Operation over*/ + MDIO_CMD_WRITE = 0x02,/*Write data*/ + MDIO_CMD_READ = 0x03 /*Read data*/ +}; +enum __mag_mdio_own{ + MDIO_OWN_HST = 0x00,/*Host can use CMD & Data Regs*/ + MDIO_OWN_TGT = 0x01 /*Tgt can use CMD & Data Regs*/ +}; + +enum __gmac_reg_mac_cfg1{ + MAC_CFG1_TX_EN = (1 << 0),/*TX enable*/ + MAC_CFG1_RX_EN = (1 << 2),/*RX enable*/ + MAC_CFG1_TX_FLOW = (1 << 4),/*TX Flow control enable*/ + MAC_CFG1_RX_FLOW = (1 << 5),/*RX Flow control enable*/ + MAC_CFG1_LOOP_EN = (1 << 8),/*Enable loopback*/ +}; +enum __gmac_reg_mac_cfg2{ + MAC_CFG2_FULL_DUP = (1 << 0),/*Enable Full Duplex*/ + MAC_CFG2_PAD_CRC = (1 << 2),/*Enable MAC based CRC insertion*/ + MAC_CFG2_CHK_LEN = (1 << 4),/*Check Length field*/ + MAC_CFG2_HUGE_FRM = (1 << 5),/*Allow sending huge frames*/ + MAC_CFG2_MII = (1 << 8),/*MAC is MII in mode*/ + MAC_CFG2_GMII = (1 << 9),/*MAC is in GMII mode*/ + MAC_CFG2_PREAMBLE = (7 << 12),/*Default Preamble Length*/ +}; +enum __gmac_reg_mii_cfg{ + MII_CFG_CLK_2MHZ = 0x0006,/*Clock is 2Mhz*/ +}; +enum __gmac_reg_mii_addr{ + MII_ADDR_RESET = 0x000,/*Flush the MII address register*/ + MII_ADDR_PHY_REG = 0x011,/*Phy Status Reg*/ +}; +enum __gmac_reg_mii_ctrl{ + MII_CTRL_FULL_DPLX = 0x0100,/*Full Duplex mode*/ + MII_CTRL_SPEED_100 = 0x2000,/*Link Speed 100 Mbps*/ + MII_CTRL_LOOPBACK = 0x4000,/*Enable Loopback mode at PHY*/ + MII_CTRL_RESET = 0x8000,/*BMCR reset*/ +}; +enum __gma_reg_mii_cmd{ + MII_CMD_WRITE = 0x0, + MII_CMD_READ = 0x1,/*Perform a Read cycle*/ +}; +enum __gmac_reg_fifo_cfg0{ + FIFO_CFG0_EN = 0x1f00,/*Enable all the Fifo module*/ +}; +enum __gmac_reg_fifo_cfg1{ + FIFO_CFG1_SIZE_2K = (0x7ff << 16),/*Fifo size is 2K*/ +}; +enum __gmac_reg_fifo_cfg4{ + FIFO_CFG4_RX_ALL = 0x3ffff,/*receive all frames*/ +}; +enum __gmac_reg_if_ctrl{ + IF_CTRL_SPEED_100 = (1 << 16),/*Interface speed 100 Mbps for MII*/ +}; + +/*************************GMAC Data types*******************************/ +typedef enum __gmac_pkt_type{ + GMAC_PKT_IS_BCAST, + GMAC_PKT_IS_UCAST +}__gmac_pkt_type_t; + +struct __ethhdr{ + unsigned char dst[ETH_ALEN];/*destination eth addr */ + unsigned char src[ETH_ALEN]; /*source ether addr*/ + A_UINT16 etype;/*ether type*/ +}__attribute__((packed)); +/** + * @brief this is will be in big endian format + */ +struct __athhdr{ +#ifdef LITTLE_ENDIAN + A_UINT8 proto:6, + res:2; +#else + A_UINT8 res:2, + proto:6; +#endif + A_UINT8 res_lo; + A_UINT16 res_hi; +}__attribute__((packed)); + +typedef struct __gmac_hdr{ + struct __ethhdr eth; + struct __athhdr ath; + A_UINT16 align_pad;/*pad it for 4 byte boundary*/ +}__attribute__((packed)) __gmac_hdr_t; + +/*********************************GMAC softC************************/ + +typedef struct __gmac_softc{ + __gmac_hdr_t hdr; + A_UINT16 gran; + HIF_CALLBACK sw; +}__gmac_softc_t; + + +#define ret_pkt sw.send_buf_done +#define indicate_pkt sw.recv_buf +#define htc_ctx sw.context +/*********************************DEFINES**********************************/ +#define hif_gmac_sc(_hdl) (__gmac_softc_t *)(_hdl) +#define gmac_hdr(_vbuf) (__gmac_hdr_t *)(_vbuf)->desc_list->buf_addr +#define GMAC_HLEN (sizeof(struct __gmac_hdr)) + +#define __gmac_mdelay(_msecs) A_DELAY_USECS((_msecs) * 1000) + +int __gmac_xmit_buf(hif_handle_t hdl, int pipe, VBUF *vbuf); +void __gmac_reap_recv(__gmac_softc_t *sc, dma_engine_t eng_no); + +/***********************************Globals********************************/ +/** + * @brief Engines are fixed + */ +__gmac_softc_t gmac_sc = { + .gran = GMAC_MAX_PKT_LEN +}; +A_UINT8 gmac_addr[ETH_ALEN] = {0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}; +A_UINT8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + +/**************************************APIs********************************/ + +/** + * @brief This a replica of the ADF_NBUF_ALLOC + * + * @param size + * @param reserve + * @param align + * + * @return VBUF* + */ +VBUF * +__gmac_vbuf_alloc(A_UINT32 size, A_UINT32 reserve, A_UINT32 align) +{ + VBUF *buf = NULL; + VDESC *desc; + + buf = VBUF_alloc_vbuf(); + if ( buf != NULL ) { + desc = VDESC_alloc_vdesc(); + desc->buf_addr = (A_UINT8 *)A_ALLOCRAM(size); + desc->buf_size = size; + desc->next_desc = NULL; + desc->data_offset = reserve; + desc->data_size = 0; + desc->control = 0; + + buf->desc_list = desc; + buf->buf_length = 0; + } + + return buf; +} +/** + * @brief This is a replica of ADF_NBUF_PULL_HEAD + * + * @param buf + * @param size + * + * @return A_UINT8* + */ +A_UINT8 * +__gmac_vbuf_pull_head(VBUF *buf, A_UINT32 len) +{ + A_UINT8 *ptr = NULL; + VDESC *desc = buf->desc_list; + + desc->data_offset += len; + desc->data_size -= len; + buf->buf_length -= len; + ptr = desc->buf_addr + desc->data_offset; + + return ptr; +} +/** + * @brief This is a replica of ADF_NBUF_PUSH_HEAD + * + * @param buf + * @param size + * + * @return A_UINT8* + */ +A_UINT8 * +__gmac_vbuf_push_head(VBUF *buf, A_UINT32 len) +{ + A_UINT8 *ptr = NULL; + VDESC *desc = buf->desc_list; + + desc->data_offset -= len; + desc->data_size += len; + buf->buf_length += len; + ptr = desc->buf_addr + desc->data_offset; + return(ptr); +} +/** + * @brief This is a replica ADF_NBUF_LAST + * + * @param buf + * + * @return VDESC* + */ +VDESC * +__gmac_vbuf_last(VBUF *buf) +{ + VDESC *desc = buf->desc_list; + + while(desc->next_desc != NULL) + desc = desc->next_desc; + + return desc; +} +/** + * @brief This is a replica of ADF_NBUF_PUT_TAIL + * + * @param buf + * @param size + * + * @return A_UINT8* + */ +A_UINT8 * +__gmac_vbuf_put_tail(VBUF *buf, A_UINT32 len) +{ + A_UINT8 *tail = NULL; + VDESC *last_desc = __gmac_vbuf_last(buf); + + tail = ( last_desc->buf_addr + last_desc->data_offset + + last_desc->data_size ); + + last_desc->data_size += len; + buf->buf_length += len; + + return tail; +} + +/************************************GMAC**********************************/ +A_UINT16 +__gmac_reg_read16(A_UINT32 addr) +{ + return *((volatile A_UINT16 *)addr); +} + +void +__gmac_reg_write16(A_UINT32 addr, A_UINT16 val) +{ + *((volatile A_UINT16 *)addr) = val; +} + + +A_UINT32 +__gmac_reg_read32(A_UINT32 addr) +{ + return *((volatile A_UINT32 *)addr); +} + +void +__gmac_reg_write32(A_UINT32 addr, A_UINT32 val) +{ + *((volatile A_UINT32 *)addr) = val; +} +/** + * @brief Read the MAC address from EEPROM + * XXX: read from real EEPROM + * + * @param mac (pointer to fill the mac address) + */ +void +__gmac_rom_read_mac(A_UINT8 mac_addr[]) +{ + A_MEMCPY(mac_addr, gmac_addr, ETH_ALEN); +} +/** + * @brief Write the MAC address into the Station address + * register + * + * @param mac + */ +void +__gmac_reg_write_mac(A_UINT8 mac_addr[]) +{ + A_UINT32 mac_lo = 0, mac_hi = 0; + + A_MEMCPY(&mac_lo, mac_addr, 4); + A_MEMCPY(&mac_hi, mac_addr + 4, 2); + + A_PRINTF("mac address = %x:%x:%x:%x:%x:%x\n", + mac_addr[0], mac_addr[1], mac_addr[2], + mac_addr[3], mac_addr[4], mac_addr[5]); + + __gmac_reg_write32(GMAC_REG_MAC_ADDR1, mac_lo); + __gmac_reg_write32(GMAC_REG_MAC_ADDR2, mac_hi); +} + +/** + * @brief Wait for the MII operation to complete + */ +void +__gmac_mii_op_wait(void) +{ + A_UINT32 r_data; + + r_data = __gmac_reg_read32(GMAC_REG_MII_PSTAT) & 0x1; + while(r_data) + r_data = (__gmac_reg_read32(GMAC_REG_MII_PSTAT) & 0x1); + +} +void +__gmac_reset(void) +{ + volatile A_UINT32 r_data; + volatile A_UINT32 w_data; + + /** + * Reset the GMAC controller from Magpie Reset Register + */ + r_data = __gmac_reg_read32(MAG_REG_RST); + r_data |= RST_GMAC; + __gmac_reg_write32(MAG_REG_RST, r_data); + + __gmac_mdelay(1); + + /** + * Pull it out from the Reset State + */ + r_data = __gmac_reg_read32(MAG_REG_RST); + r_data &= ~RST_GMAC; + __gmac_reg_write32(MAG_REG_RST, r_data); + + /** + * Reset the MII + */ + r_data = __gmac_reg_read32(MAG_REG_RST); + r_data |= (RST_MII | RST_GMAC); + __gmac_reg_write32(MAG_REG_RST, r_data); + + __gmac_mdelay(1); + /** + * Pull the MII out of reset + */ + r_data = __gmac_reg_read32(MAG_REG_RST); + r_data &= ~( RST_MII | RST_GMAC); + __gmac_reg_write32(MAG_REG_RST, r_data); + + __gmac_mdelay(1); + + /** + * Reset other modules PCI, PCIE, USB & Eth PLL + * XXX:why??? + */ +// __gmac_reg_write32(MAG_REG_RST, RST_OTHERS); + + __gmac_mdelay(1); + + /** + * Reset the AHB Arb. Unit + */ + r_data = __gmac_reg_read32(MAG_REG_RST_AHB); + r_data |= RST_AHB_GMAC; + __gmac_reg_write32(MAG_REG_RST_AHB, r_data); + + /** + * MII mode initialization + */ + w_data = ( MAC_CFG2_FULL_DUP | MAC_CFG2_PAD_CRC | MAC_CFG2_CHK_LEN | + MAC_CFG2_HUGE_FRM | MAC_CFG2_MII | MAC_CFG2_PREAMBLE ); + + __gmac_reg_write32(GMAC_REG_MAC_CFG2, w_data); + + /** + * Enable FIFO modules + */ + __gmac_reg_write32(GMAC_REG_FIFO_CFG0, FIFO_CFG0_EN); + + /** + * Mode = MII & Speed = 100 Mbps + */ + w_data = ( MII0_CTRL_100 | MII0_CTRL_MODE ); + __gmac_reg_write32(MAG_REG_MII0_CTRL, w_data); + + /** + * Set the interface speed to 100 Mbps + */ + __gmac_reg_write32(GMAC_REG_IF_CTRL, IF_CTRL_SPEED_100); + + /** + * Fifo size set to 2K bytes + */ + r_data = __gmac_reg_read32(GMAC_REG_FIFO_CFG1); + r_data |= FIFO_CFG1_SIZE_2K; + __gmac_reg_write32(GMAC_REG_FIFO_CFG1, r_data); + + /** + * Enable the transceiver + */ + w_data = MAC_CFG1_RX_EN | MAC_CFG1_TX_EN; + __gmac_reg_write32(GMAC_REG_MAC_CFG1, w_data); + + /** + * Set the MII Clock to 2Mhz + */ + __gmac_reg_write32(GMAC_REG_MII_CFG, MII_CFG_CLK_2MHZ); + + /** + * Programming the phy registers + */ + __gmac_reg_write32(GMAC_REG_MII_ADDR, MII_ADDR_RESET); + + /** + * BMCR reset for the PHY + */ + __gmac_reg_write32(GMAC_REG_MII_CTRL, MII_CTRL_RESET); + + /** + * Wait until the MII Reg write has been flushed + */ + __gmac_mii_op_wait(); + + /** + * PHY register 0x000 , BMCR + */ + __gmac_reg_write32(GMAC_REG_MII_ADDR, MII_ADDR_RESET); + + /** + * Write the value in the register + */ + w_data = ( MII_CTRL_FULL_DPLX | MII_CTRL_SPEED_100 | MII_CTRL_RESET); + __gmac_reg_write32(GMAC_REG_MII_CTRL, w_data); + + __gmac_mii_op_wait(); + + /** + * Pull the BMCR out of the reset state + */ + __gmac_reg_write32(GMAC_REG_MII_ADDR, MII_ADDR_RESET); + + w_data = (MII_CTRL_FULL_DPLX | MII_CTRL_SPEED_100); + __gmac_reg_write32(GMAC_REG_MII_ADDR, w_data); + + __gmac_mii_op_wait(); + + /** + * XXX: This should be for some debugging purpose, don't know + * why we should write into the GPIO Output Enable the value + * returned from PHY status register Read + */ + __gmac_reg_write32(GMAC_REG_MII_CMD, MII_CMD_WRITE); + __gmac_reg_write32(GMAC_REG_MII_ADDR, MII_ADDR_PHY_REG); + __gmac_reg_write32(GMAC_REG_MII_CMD, MII_CMD_READ); + + __gmac_mii_op_wait(); + + r_data = __gmac_reg_read32(GMAC_REG_MII_STAT); + + __gmac_reg_write32(MAG_REG_GPIO_OE, r_data); + + /** + * Enable Receive Fifo + */ + r_data = __gmac_reg_read32(GMAC_REG_FIFO_CFG4); + r_data |= FIFO_CFG4_RX_ALL; + __gmac_reg_write32(GMAC_REG_FIFO_CFG4, r_data); + +} +/** + * @brief return if the pipe is supported + * + * @param pipe + * + * @return a_bool_t + */ +static inline a_bool_t +__gmac_chk_pipe(hif_gmac_pipe_t pipe) +{ + switch (pipe) { + case HIF_GMAC_PIPE_TX: + case HIF_GMAC_PIPE_RX: + return A_TRUE; + default: + return A_FALSE; + } +} + +VBUF * +__gmac_pkt_alloc(A_UINT32 size) +{ + VBUF * buf; + A_UINT16 fill_size; + A_UINT8 *data; + + if(size < GMAC_HLEN) + return NULL; + + buf = __gmac_vbuf_alloc(size, GMAC_HLEN, 0); + if(!buf) + return NULL; + + fill_size = size - GMAC_HLEN; + + data = __gmac_vbuf_put_tail(buf, fill_size); + + A_MEMSET(data, 0xaa, fill_size); + + return buf; +} +/** + * @brief Slap the header + * + * @param buf + * @param hdr + */ +void +__gmac_put_hdr(VBUF * buf, __gmac_hdr_t *hdr) +{ + A_UINT8 *data; + + data = __gmac_vbuf_push_head(buf, GMAC_HLEN); + + A_MEMCPY(data, hdr, GMAC_HLEN); +} +/** + * @brief + * + * @param hdr + * @param src + */ +void +__gmac_prep_ethhdr(__gmac_hdr_t *hdr, A_UINT8 *dst) +{ + A_MEMCPY(hdr->eth.dst, dst, ETH_ALEN); + hdr->eth.etype = ETH_P_ATH; +} + + +a_bool_t +__is_ath_header(__gmac_softc_t *sc, VBUF *vbuf) +{ + __gmac_hdr_t *hdr = gmac_hdr(vbuf); + + if(hdr->ath.proto != sc->hdr.ath.proto) + return A_FALSE; + + return A_TRUE; +} + +a_status_t +__gmac_process_discv(__gmac_softc_t *sc) +{ + a_status_t err = A_STATUS_OK; + VBUF *vbuf; + __gmac_hdr_t *buf_hdr ; + + + vbuf = dma_lib_reap_recv(DMA_ENGINE_RX0); + + if(!__is_ath_header(sc, vbuf)) + goto fail; + + buf_hdr = gmac_hdr(vbuf); + + A_MEMCPY(sc->hdr.eth.dst, buf_hdr->eth.src, ETH_ALEN); + + __gmac_vbuf_pull_head(vbuf, GMAC_HLEN); + + /** + * Application should do the return_recv + */ + sc->indicate_pkt(NULL, vbuf, sc->htc_ctx); + + + return A_STATUS_OK; + + /** + * This is not our packet + */ +fail: + + dma_lib_return_recv(DMA_ENGINE_RX0, vbuf); + + return err; +} +/** + * @brief The GMAC host discovery loop + */ +void +__gmac_discover(void) +{ + a_status_t err = A_STATUS_FAILED; + VBUF * buf; + __gmac_softc_t *sc = &gmac_sc; + + + /** + * Get a packet + */ + buf = __gmac_pkt_alloc(GMAC_DISCV_PKT_SZ); + + /** + * Prepare the broadcast packet + */ + __gmac_prep_ethhdr(&sc->hdr, bcast_addr); + __gmac_put_hdr(buf, &sc->hdr); + + while(1){ + + if(buf) + dma_lib_hard_xmit(DMA_ENGINE_TX0, buf); + + buf = NULL; + __gmac_mdelay(GMAC_DISCV_WAIT); + + if(dma_lib_xmit_done(DMA_ENGINE_TX0)) + buf = dma_lib_reap_xmitted(DMA_ENGINE_TX0); + + + while(dma_lib_recv_pkt(DMA_ENGINE_RX0) && err) + err = __gmac_process_discv(sc); + + if(!err) + break; + } + + adf_os_assert(buf); +} + +void +__gmac_mdio_check(void) +{ + A_UINT16 own; + + /*Read the Ownership register*/ + do { + own = __gmac_reg_read16(MAG_REG_MDIO_OWN); + } while ( own == MDIO_OWN_TGT ); + +} + +void +__gmac_mdio_load_exec(void) +{ + volatile A_UINT16 cmd, more = 1 ; + volatile A_UINT16 *addr[2]; + void ( *exec_fn)(void) = NULL; + + do { + /** + * Read the Command register + */ + cmd = __gmac_reg_read16(MAG_REG_MDIO_CMD); + + switch (cmd) { + + case MDIO_CMD_WRITE: + + /** + * 1. Read the address from Address register + * 2. Write the data from Data register into the address + */ + (A_UINT16 *)addr[0] = __gmac_reg_read16(MAG_REG_MDIO_ADDR0); + *addr[0] = __gmac_reg_read16(MAG_REG_MDIO_WRITE0); + + (A_UINT16 *)addr[1] = __gmac_reg_read16(MAG_REG_MDIO_ADDR1); + *addr[1] = __gmac_reg_read16(MAG_REG_MDIO_WRITE1); + + if ( exec_fn ) + break; + + exec_fn = (A_UINT32 *)addr; + break; + + case MDIO_CMD_DONE: + + more = 0; + break; + + case MDIO_CMD_READ: + + /** + * 1. Read the address from Address register + * 2. Write the data into the Data register from the address + */ + addr[0] = (A_UINT16 *)__gmac_reg_read16(MAG_REG_MDIO_ADDR0); + __gmac_reg_write16(MAG_REG_MDIO_READ0, *addr[0]); + + addr[1] = (A_UINT16 *)__gmac_reg_read16(MAG_REG_MDIO_ADDR1); + __gmac_reg_write16(MAG_REG_MDIO_READ1, *addr[1]); + + break; + default: + + A_PRINTF("Command not implemmented\n"); + adf_os_assert(0); + break; + } + + } while ( more ); + + /** + * Change the Ownership + */ + __gmac_reg_write16(MAG_REG_MDIO_OWN, MDIO_OWN_HST); + + if ( exec_fn ) + exec_fn(); + +} + +void +__gmac_mdio_init(void) +{ + +more_exec: + + /** + * Check for Targets turn + */ + __gmac_mdio_check(); + + /** + * Load & execute or Read data, if this returns then keep + * repeating + */ + __gmac_mdio_load_exec(); + + /** + * If we are here then Host wants some more function execs or + * reads + */ + goto more_exec; + +} +void +__gmac_boot_init(void) +{ + __gmac_softc_t *sc = &gmac_sc; + + + __gmac_reset(); + + /** + * Magpie is Booting + */ + sc->hdr.ath.proto = ATH_P_MAGBOOT; + + dma_lib_tx_init(DMA_ENGINE_TX0, DMA_IF_GMAC); + dma_lib_rx_init(DMA_ENGINE_RX0, DMA_IF_GMAC); + + dma_lib_rx_config(DMA_ENGINE_RX0, GMAC_MAX_DESC, GMAC_MAX_PKT_LEN); + + /** + * Read the MAC address from the ROM & Write it into the + * Register + */ + __gmac_rom_read_mac(sc->hdr.eth.src); + __gmac_reg_write_mac(sc->hdr.eth.src); + + /** + * Discover the Host + */ + __gmac_discover(); +} +/** + * @brief + * + * @param pConfig + * + * @return hif_handle_t + */ +hif_handle_t +__gmac_init(HIF_CONFIG *pConfig) +{ + __gmac_softc_t *sc = &gmac_sc; + + sc->hdr.ath.proto = ATH_P_MAGNORM; + + dma_lib_tx_init(DMA_ENGINE_TX0, DMA_IF_GMAC); + dma_lib_rx_init(DMA_ENGINE_RX0, DMA_IF_GMAC); + + return &gmac_sc; +} +/** + * @brief Configure the receive pipe + * + * @param hdl + * @param pipe + * @param num_desc + */ +void +__gmac_cfg_pipe(hif_handle_t hdl, int pipe, int num_desc) +{ + __gmac_softc_t *sc = &gmac_sc; + + if(pipe == HIF_GMAC_PIPE_RX) + dma_lib_rx_config(DMA_ENGINE_RX0, num_desc, sc->gran); +} +/** + * @brief Start the interface + * + * @param hdl + */ +void +__gmac_start(hif_handle_t hdl) +{ + return; +} +/** + * @brief Register callback of thre HTC + * + * @param hdl + * @param sw + */ +void +__gmac_reg_callback(hif_handle_t hdl, HIF_CALLBACK *sw) +{ + __gmac_softc_t *sc = &gmac_sc; + + sc->htc_ctx = sw->context; + sc->indicate_pkt = sw->recv_buf; + sc->ret_pkt = sw->send_buf_done; +} +/** + * @brief reap the transmit queue for trasnmitted packets + * + * @param sc + * @param eng_no + */ +void +__gmac_reap_xmitted(__gmac_softc_t *sc, dma_engine_t eng_no) +{ + VBUF *vbuf = NULL; + /** + * Walk through the all your TX engines + */ + do { + + vbuf = dma_lib_reap_xmitted(eng_no); + if(!vbuf) + break; + + __gmac_vbuf_pull_head(vbuf, GMAC_HLEN); + sc->ret_pkt(vbuf, sc->htc_ctx); + + } while ( vbuf ); +} +/** + * @brief reap the receive queue for vbuf's on the specified + * engine number + * + * @param sc + * @param eng_no + */ +void +__gmac_reap_recv(__gmac_softc_t *sc, dma_engine_t eng_no) +{ + VBUF *vbuf = NULL; + + do { + vbuf = dma_lib_reap_recv(eng_no); + + if(!vbuf) + break; + + if(!__is_ath_header(sc, vbuf)){ + dma_lib_return_recv(eng_no, vbuf); + continue; + } + + __gmac_vbuf_pull_head(vbuf, GMAC_HLEN); + + sc->indicate_pkt(NULL, vbuf, sc->htc_ctx); + + } while ( vbuf ); +} +/** + * @brief The interrupt handler + * + * @param hdl + */ +void +__gmac_isr_handler(hif_handle_t hdl) +{ + __gmac_softc_t *sc = &gmac_sc; + + if(dma_lib_xmit_done(DMA_ENGINE_TX0)) + __gmac_reap_xmitted(sc, DMA_ENGINE_TX0); + + if(dma_lib_recv_pkt(DMA_ENGINE_RX0)) + __gmac_reap_recv(sc, DMA_ENGINE_RX0); +} +/** + * @brief transmit the vbuf from the specified pipe + * + * @param hdl + * @param pipe + * @param buf + * + * @return int + */ +int +__gmac_xmit_buf(hif_handle_t hdl, int pipe, VBUF *vbuf) +{ + __gmac_softc_t *sc = &gmac_sc; + + if (pipe != HIF_GMAC_PIPE_TX) + return -1; + +#if 0 + adf_os_assert( vbuf->desc_list->data_offset >= GMAC_HLEN) +#endif + + __gmac_put_hdr(vbuf, &sc->hdr); + + return dma_lib_hard_xmit(DMA_ENGINE_TX0, vbuf); +} +/** + * @brief Submit the receive vbuf into the receive queue + * + * @param handle + * @param pipe + * @param buf + */ +void +__gmac_return_recv(hif_handle_t hdl, int pipe, VBUF *vbuf) +{ + if (pipe == HIF_GMAC_PIPE_RX) + dma_lib_return_recv(DMA_ENGINE_RX0, vbuf); +} +/** + * @brief Is this pipe number supported + * + * @param handle + * @param pipe + * + * @return int + */ +int +__gmac_is_pipe_supported(hif_handle_t hdl, int pipe) +{ + return __gmac_chk_pipe(pipe); +} +/** + * @brief maximum message length this pipe can support + * + * @param handle + * @param pipe + * + * @return int + */ +int +__gmac_get_max_msg_len(hif_handle_t hdl, int pipe) +{ + if(__gmac_chk_pipe(pipe)) + return GMAC_MAX_PKT_LEN; + + return 0; +} +/** + * @brief return the header room required by this HIF + * + * @param hdl + * + * @return int + */ +int +__gmac_get_reserved_headroom(hif_handle_t hdl) +{ + return (GMAC_HLEN); +} +/** + * @brief Device shutdown, HIF reset required + * + * @param hdl + */ +void +__gmac_shutdown(hif_handle_t hdl) +{ + return; +} +void +__gmac_get_def_pipe(hif_handle_t handle, A_UINT8 *pipe_uplink, + A_UINT8 *pipe_downlink) +{ + *pipe_uplink = HIF_GMAC_PIPE_RX; + *pipe_downlink = HIF_GMAC_PIPE_TX; +} + +/** + * @brief This install the API's of the HIF + * + * @param apis + */ +void +hif_gmac_module_install(struct hif_api *apis) +{ + /* hook in APIs */ + apis->_init = __gmac_init; + apis->_start = __gmac_start; + apis->_config_pipe = __gmac_cfg_pipe; + apis->_isr_handler = __gmac_isr_handler; + apis->_send_buffer = __gmac_xmit_buf; + apis->_return_recv_buf = __gmac_return_recv; + apis->_is_pipe_supported = __gmac_is_pipe_supported; + apis->_get_max_msg_len = __gmac_get_max_msg_len; + apis->_register_callback = __gmac_reg_callback; + apis->_shutdown = __gmac_shutdown;/*XXX*/ + apis->_get_reserved_headroom = __gmac_get_reserved_headroom; + apis->_get_default_pipe = __gmac_get_def_pipe; +} + +void +cmnos_gmac_module_install(struct gmac_api *boot_apis) +{ + boot_apis->gmac_boot_init = __gmac_boot_init; +} diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/dma_lib.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/dma_lib.h new file mode 100755 index 0000000..7b44c56 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/dma_lib.h @@ -0,0 +1,57 @@ +#ifndef __DMA_LIB_H +#define __DMA_LIB_H + + +/***********************External***************************/ + +/** + * @brief DMA engine numbers, HIF need to map them to there + * respective order + */ +typedef enum dma_engine{ + DMA_ENGINE_RX0, + DMA_ENGINE_RX1, + DMA_ENGINE_RX2, + DMA_ENGINE_RX3, + DMA_ENGINE_TX0, + DMA_ENGINE_TX1, + DMA_ENGINE_MAX +}dma_engine_t; + +/** + * @brief Interface type, each HIF should call with its own interface type + */ +typedef enum dma_iftype{ + DMA_IF_GMAC = 0x0,/* GMAC */ + DMA_IF_PCI = 0x1,/*PCI */ + DMA_IF_PCIE = 0x2 /*PCI Express */ +}dma_iftype_t; + + +struct dma_lib_api{ + A_UINT16 (*tx_init)(dma_engine_t eng_no, dma_iftype_t if_type); + void (*tx_start)(dma_engine_t eng_no); + A_UINT16 (*rx_init)(dma_engine_t eng_no, dma_iftype_t if_type); + void (*rx_config)(dma_engine_t eng_no, a_uint16_t num_desc, + a_uint16_t gran); + void (*rx_start)(dma_engine_t eng_no); + A_UINT32 (*intr_status)(dma_iftype_t if_type); + A_UINT16 (*hard_xmit)(dma_engine_t eng_no, VBUF *buf); + void (*flush_xmit)(dma_engine_t eng_no); + A_UINT16 (*xmit_done)(dma_engine_t eng_no); + VBUF * (*reap_xmitted)(dma_engine_t eng_no); + VBUF * (*reap_recv)(dma_engine_t eng_no); + void (*return_recv)(dma_engine_t eng_no, VBUF *buf); + A_UINT16 (*recv_pkt)(dma_engine_t eng_no); +}; + + +/** + * @brief Install the DMA lib api's this for ROM patching + * support + * + * @param apis + */ +void dma_lib_module_install(struct dma_lib_api *apis); + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_api.h new file mode 100755 index 0000000..33dde31 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_api.h @@ -0,0 +1,70 @@ +/* + * @File: HIF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _HIF_API_H +#define _HIF_API_H + +#include + +/* mailbox hw module configuration structure */ +typedef struct _HIF_CONFIG { + int dummy; +} HIF_CONFIG; + +typedef struct _HIF_CALLBACK { + /* callback when a buffer has be sent to the host*/ + void (*send_buf_done)(adf_nbuf_t buf, void *context); + /* callback when a receive message is received */ + void (*recv_buf)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); + /* context used for all callbacks */ + void *context; +} HIF_CALLBACK; + +typedef void* hif_handle_t; + +/* hardware API table structure (API descriptions below) */ +struct hif_api { + hif_handle_t (*_init)(HIF_CONFIG *pConfig); + + void (* _shutdown)(hif_handle_t); + + void (*_register_callback)(hif_handle_t, HIF_CALLBACK *); + + int (*_get_total_credit_count)(hif_handle_t); + + void (*_start)(hif_handle_t); + + void (*_config_pipe)(hif_handle_t handle, int pipe, int creditCount); + + int (*_send_buffer)(hif_handle_t handle, int pipe, adf_nbuf_t buf); + + void (*_return_recv_buf)(hif_handle_t handle, int pipe, adf_nbuf_t buf); + //void (*_set_recv_bufsz)(int pipe, int bufsz); + //void (*_pause_recv)(int pipe); + //void (*_resume_recv)(int pipe); + int (*_is_pipe_supported)(hif_handle_t handle, int pipe); + + int (*_get_max_msg_len)(hif_handle_t handle, int pipe); + + int (*_get_reserved_headroom)(hif_handle_t handle); + + void (*_isr_handler)(hif_handle_t handle); + + void (*_get_default_pipe)(hif_handle_t handle, A_UINT8 *pipe_uplink, A_UINT8 *pipe_downlink); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void generic_hif_module_install(struct hif_api *apis); + +#endif /* #ifndef _HIF_API_H */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_gmac.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_gmac.h new file mode 100755 index 0000000..71229bf --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_gmac.h @@ -0,0 +1,35 @@ + +#ifndef __HIF_GMAC_H +#define __HIF_GMAC_H + +#include +#include + + +#define ETH_ALEN 6 +#define GMAC_MAX_PKT_LEN 1600 +#define GMAC_MAX_DESC 5 + +#define GMAC_DISCV_PKT_SZ 60 +#define GMAC_DISCV_WAIT 2000 + +#define ATH_P_MAGBOOT 0x12 /*Magpie GMAC 18 for boot downloader*/ +#define ATH_P_MAGNORM 0x13 /*Magpie GMAC 19 for HTC & others*/ + +#define ETH_P_ATH 0x88bd + +typedef enum hif_gmac_pipe{ + HIF_GMAC_PIPE_RX = 1, /*Normal Priority RX*/ + HIF_GMAC_PIPE_TX = 2, /*Normal Priority TX*/ +}hif_gmac_pipe_t; + +struct gmac_api{ + void (*gmac_boot_init)(void); +}; + +void cmnos_gmac_module_install(struct gmac_api *boot_apis); +void hif_gmac_module_install(struct hif_api *apis); + + +#endif + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_pci.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_pci.h new file mode 100755 index 0000000..848c104 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_pci.h @@ -0,0 +1,34 @@ + +#ifndef __HIF_PCI_H +#define __HIF_PCI_H + +#include + + +#define PCI_MAX_DATA_PKT_LEN 1600 +#define PCI_MAX_CMD_PKT_LEN 64 +#define PCI_MAX_BOOT_DESC 2 + +typedef enum hif_pci_pipe_rx{ + HIF_PCI_PIPE_RX0, /*Normal Priority RX*/ + HIF_PCI_PIPE_RX1, + HIF_PCI_PIPE_RX2, + HIF_PCI_PIPE_RX3, + HIF_PCI_PIPE_RX_MAX +}hif_pci_pipe_rx_t; + +typedef enum hif_pci_pipe_tx{ + HIF_PCI_PIPE_TX0, /*Normal Priority TX*/ + HIF_PCI_PIPE_TX1, + HIF_PCI_PIPE_TX_MAX +}hif_pci_pipe_tx_t; + +struct pci_api{ + void (*pci_boot_init)(void); +}; + +void cmnos_pci_module_install(struct pci_api *apis); +void hif_pci_module_install(struct hif_api *apis); +#endif + + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_usb.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_usb.h new file mode 100755 index 0000000..addc17e --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/hif_usb.h @@ -0,0 +1,58 @@ +/* + * @File: mbox_hw.h + * + * @Abstract: mailbox hardware definitions + * + * @Notes: + * * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef __HIF_USB_H__ +#define __HIF_USB_H__ + +#include + +#include +#include +#include +//#include +//#include + +#define HIF_USB_PIPE_TX 1 +#define HIF_USB_PIPE_RX 2 +#define HIF_USB_PIPE_INTERRUPT 3 +#define HIF_USB_PIPE_COMMAND 4 +#define HIF_USB_PIPE_HP_TX 5 +#define HIF_USB_PIPE_MP_TX 6 + +struct VBUF_QUEUE +{ + VBUF *head; + VBUF *tail; +}; + + /* the mailbox hardware layer context */ +typedef struct _HIF_USB_CONTEXT { + HIF_CALLBACK hifCb; + struct zsDmaQueue dnQ; + struct zsTxDmaQueue upQ; +#if SYSTEM_MODULE_HP_EP5 + struct zsDmaQueue hpdnQ; // high priority +#endif +#if SYSTEM_MODULE_HP_EP6 + struct zsDmaQueue mpdnQ; // medium priority +#endif + //struct VBUF_QUEUE upVbufQ; + VBUF *cmdQueue; + struct VBUF_QUEUE eventBufQ; + + // Left a door for extension the structure + void *pReserved; +} HIF_USB_CONTEXT; + +void hif_usb_module_install(struct hif_api *apis); + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/usb_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/usb_api.h new file mode 100755 index 0000000..a9c3168 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/usb_api.h @@ -0,0 +1,52 @@ +#ifndef USB_API_H +#define USB_API_H + +#include "dt_defs.h" + +/******** hardware API table structure (API descriptions below) *************/ +struct usb_api { + void (*_usb_init)(void); + void (*_usb_rom_task)(void); + void (*_usb_fw_task)(void); + void (*_usb_init_phy)(void); + + // ep0 operation + void (*_usb_ep0_setup)(void); + + void (*_usb_ep0_tx)(void); + void (*_usb_ep0_rx)(void); + + // get/set interface + BOOLEAN (*_usb_get_interface)(void); + BOOLEAN (*_usb_set_interface)(void); + + // get/set configuration + BOOLEAN (*_usb_get_configuration)(void); + BOOLEAN (*_usb_set_configuration)(void); + + // standard/vendor command + BOOLEAN (*_usb_standard_cmd)(void); + void (*_usb_vendor_cmd)(void); + + void (*_usb_power_off)(void); + void (*_usb_reset_fifo)(void); + void (*_usb_gen_wdt)(void); + void (*_usb_jump_boot)(void); + + BOOLEAN (*_usb_clr_feature)(void); + BOOLEAN (*_usb_set_feature)(void); + BOOLEAN (*_usb_set_address)(void); + BOOLEAN (*_usb_get_descriptor)(void); + + BOOLEAN (*_usb_get_status)(void); + void (*_usb_setup_desc)(void); + void (*_usb_reg_out)(void); + void (*_usb_status_in)(void); + + void (*_usb_ep0_tx_data)(void); + void (*_usb_ep0_rx_data)(void); + + void (*_usb_clk_init)(void); +}; + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/usbfifo_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/usbfifo_api.h new file mode 100755 index 0000000..08c4644 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/inc/usbfifo_api.h @@ -0,0 +1,43 @@ +/* + * @File: HIF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _USB_FIFO_API_H +#define _USB_FIFO_API_H + +#include "vbuf_api.h" + +typedef struct _USB_FIFO_CONFIG { + /* callback to get the buf for receiving commands from USB FIFO */ + VBUF* (*get_command_buf)(void); + /* callback when receiving a command */ + void (*recv_command)(VBUF *cmd); + /* callback to get the buf for event to send to the host */ + VBUF* (*get_event_buf)(void); + /* callback to indicate the event has been sent to the host */ + void (*send_event_done)(VBUF *buf); + + /* context used for all callbacks */ + //void *context; +} USB_FIFO_CONFIG; + +/* hardware API table structure (API descriptions below) */ +struct usbfifo_api { + void (*_init)(USB_FIFO_CONFIG *pConfig); + void (*_enable_event_isr)(void); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void usbfifo_module_install(struct usbfifo_api *apis); + +#endif /* #ifndef _USB_FIFO_API_H */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/pci/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/pci/Makefile new file mode 100755 index 0000000..4d26a7a --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/pci/Makefile @@ -0,0 +1,51 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = hif +export SSNAME = pci + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/pci/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/pci/Makefile.ss new file mode 100755 index 0000000..ce80f76 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/pci/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/ + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/hif_pci.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/pci/hif_pci.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/pci/hif_pci.c new file mode 100755 index 0000000..937172b --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/pci/hif_pci.c @@ -0,0 +1,545 @@ +#include +#include +#include + +#include +#include "hif_pci.h" + + +/**************************Constants******************************/ + +/*************************Data types*******************************/ +enum pci_regs{ + MAG_REG_AHB_RESET = 0x00050010, + MAG_REG_AHB_ARB = 0x00050018 +}; + +#define PCI_AHB_ARB_ENB (1 << 3) +#define PCI_AHB_RESET_DMA (1 << 13) +#define PCI_AHB_RESET_DMA_HST_RAW (1 << 14) +#define PCI_AHB_RESET_DMA_HST (1 << 15) + +/*********************************softC************************/ +typedef struct __pci_softc{ + HIF_CALLBACK sw; +}__pci_softc_t; + + +#define ret_pkt sw.send_buf_done +#define indicate_pkt sw.recv_buf +#define htc_ctx sw.context +/*********************************DEFINES**********************************/ +#define hdl_to_softc(_hdl) (__pci_softc_t *)(_hdl) + +#define PCI_ENG_NUM(_eng) HIF_PCI_PIPE_##_eng + +#define PCI_INIT_PIPE { \ + PCI_ENG_NUM(RX0), \ + PCI_ENG_NUM(RX1), \ + PCI_ENG_NUM(RX2), \ + PCI_ENG_NUM(RX3), \ + PCI_ENG_NUM(TX0), \ + PCI_ENG_NUM(TX1), \ +} + +#define rx_pipe0 DMA_ENGINE_RX0 +#define rx_pipe1 DMA_ENGINE_RX1 +#define tx_pipe0 DMA_ENGINE_TX0 +#define tx_pipe1 DMA_ENGINE_TX1 +#define dbg_pci 0 +#define dbg_pci_loopback 0 + +#define PCI_DBG_MODE 0 + +void __pci_cfg_pipe(hif_handle_t hdl, int pipe, int num_desc); +int __pci_get_max_msg_len(hif_handle_t hdl, int pipe); +void __pci_return_recv(hif_handle_t hdl, int pipe, VBUF *buf); +void __pci_reset(void); +void __pci_enable(void); + + +/***********************************Globals********************************/ +/** + * @brief Engines are fixed + */ +__pci_softc_t pci_sc = {0}; + + +/**************************************APIs********************************/ + +A_UINT32 +__pci_reg_read(A_UINT32 addr) +{ + return *((volatile A_UINT32 *)addr); +} + +void +__pci_reg_write(A_UINT32 addr, A_UINT32 val) +{ + *((volatile A_UINT32 *)addr) = val; +} + +A_UINT8 +__pci_get_pipe(dma_engine_t eng) +{ + switch (eng) { + case DMA_ENGINE_RX0: + return HIF_PCI_PIPE_RX0; + case DMA_ENGINE_RX1: + return HIF_PCI_PIPE_RX1; + case DMA_ENGINE_RX2: + return HIF_PCI_PIPE_RX2; + case DMA_ENGINE_RX3: + return HIF_PCI_PIPE_RX3; + case DMA_ENGINE_TX0: + return HIF_PCI_PIPE_TX0; + case DMA_ENGINE_TX1: + return HIF_PCI_PIPE_TX1; + default: + adf_os_assert(0); + } +} + +dma_engine_t +__pci_get_tx_eng(hif_pci_pipe_tx_t pipe) +{ + switch (pipe) { + case HIF_PCI_PIPE_TX0: + return DMA_ENGINE_TX0; + + case HIF_PCI_PIPE_TX1: + return DMA_ENGINE_TX1; + + default: + return DMA_ENGINE_MAX; + } +} +dma_engine_t +__pci_get_rx_eng(hif_pci_pipe_rx_t pipe) +{ + switch (pipe) { + case HIF_PCI_PIPE_RX0: + return DMA_ENGINE_RX0; + + case HIF_PCI_PIPE_RX1: + return DMA_ENGINE_RX1; + + case HIF_PCI_PIPE_RX2: + return DMA_ENGINE_RX2; + + case HIF_PCI_PIPE_RX3: + return DMA_ENGINE_RX3; + + default: + return DMA_ENGINE_MAX; + } +} + + + +void +__pci_enable(void) +{ + A_UINT32 r_data; + /** + * Grant access to the internal memory for PCI DMA + */ + + r_data = __pci_reg_read(MAG_REG_AHB_ARB); + r_data |= PCI_AHB_ARB_ENB; + __pci_reg_write(MAG_REG_AHB_ARB, r_data); +} + +/** + * @brief PCI reset + * XXX: Move this to RAM + */ +void +__pci_reset(void) +{ + volatile A_UINT32 r_data; + + /** + * Poll until the Host has reset + */ + A_PRINTF("Waiting for host reset.."); + for (;;) { + r_data = __pci_reg_read(MAG_REG_AHB_RESET); + + if ( r_data & PCI_AHB_RESET_DMA_HST_RAW) + break; + } + A_PRINTF("received.\n"); + + /** + * Pull the AHB out of reset + */ + + r_data = __pci_reg_read(MAG_REG_AHB_RESET); + r_data &= ~PCI_AHB_RESET_DMA; + __pci_reg_write(MAG_REG_AHB_RESET, r_data); + + A_DELAY_USECS(10); + + /** + * Put the AHB into reset + */ + + r_data = __pci_reg_read(MAG_REG_AHB_RESET); + r_data |= PCI_AHB_RESET_DMA; + __pci_reg_write(MAG_REG_AHB_RESET, r_data); + + A_DELAY_USECS(10); + + /** + * Pull the AHB out of reset + */ + + r_data = __pci_reg_read(MAG_REG_AHB_RESET); + r_data &= ~PCI_AHB_RESET_DMA; + __pci_reg_write(MAG_REG_AHB_RESET, r_data); + + A_DELAY_USECS(10); +} +/** + * @brief Boot init + */ +void +__pci_boot_init(void) +{ + __pci_reset(); + __pci_enable(); + + dma_lib_tx_init(DMA_ENGINE_TX0, DMA_IF_PCI); + dma_lib_rx_init(DMA_ENGINE_RX0, DMA_IF_PCI); + + dma_lib_rx_config(DMA_ENGINE_RX0, PCI_MAX_BOOT_DESC, + PCI_MAX_DATA_PKT_LEN); + +} +/** + * @brief + * + * @param pConfig + * + * @return hif_handle_t + */ +hif_handle_t +__pci_init(HIF_CONFIG *pConfig) +{ + __pci_reset(); + __pci_enable(); + + /** + * Initializing the other TX engines + */ + dma_lib_tx_init(DMA_ENGINE_TX0, DMA_IF_PCI); + dma_lib_tx_init(DMA_ENGINE_TX1, DMA_IF_PCI); + + /** + * Initializing the other RX engines + */ + dma_lib_rx_init(DMA_ENGINE_RX0, DMA_IF_PCI); + dma_lib_rx_init(DMA_ENGINE_RX1, DMA_IF_PCI); + dma_lib_rx_init(DMA_ENGINE_RX2, DMA_IF_PCI); + dma_lib_rx_init(DMA_ENGINE_RX3, DMA_IF_PCI); + + return &pci_sc; +} +/** + * @brief Configure the receive pipe + * + * @param hdl + * @param pipe + * @param num_desc + */ +void +__pci_cfg_pipe(hif_handle_t hdl, int pipe, int num_desc) +{ + dma_engine_t eng; + A_UINT16 desc_len; + + eng = __pci_get_rx_eng(pipe); + + if (eng == DMA_ENGINE_MAX) { + A_PRINTF("Bad Engine number\n"); + return; + } + + desc_len = __pci_get_max_msg_len(hdl, pipe); + + dma_lib_rx_config(eng, num_desc, desc_len); +} +/** + * @brief Start the interface + * + * @param hdl + */ +void +__pci_start(hif_handle_t hdl) +{ + return; +} +/** + * @brief Register callback of thre HTC + * + * @param hdl + * @param sw + */ +void +__pci_reg_callback(hif_handle_t hdl, HIF_CALLBACK *sw) +{ + __pci_softc_t *sc = &pci_sc; + + sc->htc_ctx = sw->context; + sc->indicate_pkt = sw->recv_buf; + sc->ret_pkt = sw->send_buf_done; +} + +/** + * @brief reap the transmit queue for trasnmitted packets + * + * @param sc + * @param eng_no + */ +void +__pci_reap_xmitted(__pci_softc_t *sc, dma_engine_t eng_no) +{ + VBUF *vbuf = NULL; + A_UINT8 pipe; + + pipe = __pci_get_pipe(eng_no); + + vbuf = dma_lib_reap_xmitted(eng_no); + + if ( vbuf ) + sc->ret_pkt(vbuf, sc->htc_ctx); + else + A_PRINTF("Empty RX Reap\n"); + + +} + +/** + * @brief reap the receive queue for vbuf's on the specified + * engine number + * + * @param sc + * @param eng_no + */ +void +__pci_reap_recv(__pci_softc_t *sc, dma_engine_t eng_no) +{ + VBUF *vbuf = NULL; + + vbuf = dma_lib_reap_recv(eng_no); + + if(vbuf) + sc->indicate_pkt(NULL, vbuf, sc->htc_ctx); + else + A_PRINTF("Empty TX Reap \n"); +} +/** + * @brief The interrupt handler + * + * @param hdl + */ +void +__pci_isr_handler(hif_handle_t hdl) +{ + __pci_softc_t *sc = &pci_sc; + A_UINT16 more = 0; + + do { + + more = 0; + + if( dma_lib_xmit_done(DMA_ENGINE_TX1) ) { + __pci_reap_xmitted(sc,DMA_ENGINE_TX1); + more = 1; + } + if( dma_lib_recv_pkt(DMA_ENGINE_RX3) ) { + __pci_reap_recv(sc, DMA_ENGINE_RX3); + more = 1; + } + + } while( more ); + + do { + + more = 0; + + if( dma_lib_xmit_done(DMA_ENGINE_TX1) ) { + __pci_reap_xmitted(sc,DMA_ENGINE_TX1); + more = 1; + } + if( dma_lib_recv_pkt(DMA_ENGINE_RX2) ) { + __pci_reap_recv(sc, DMA_ENGINE_RX2); + more = 1; + } + + } while( more ); + + do { + + more = 0; + + if( dma_lib_xmit_done(DMA_ENGINE_TX1) ) { + __pci_reap_xmitted(sc,DMA_ENGINE_TX1); + more = 1; + } + if( dma_lib_recv_pkt(DMA_ENGINE_RX1) ) { + __pci_reap_recv(sc, DMA_ENGINE_RX1); + more = 1; + } + + } while( more ); + + do { + + more = 0; + + if( dma_lib_xmit_done(DMA_ENGINE_TX0) ) { + __pci_reap_xmitted(sc,DMA_ENGINE_TX0); + more = 1; + } + + if( dma_lib_recv_pkt(DMA_ENGINE_RX0) ) { + __pci_reap_recv(sc, DMA_ENGINE_RX0); + more = 1; + } + + } while( more ); + +} +/** + * @brief transmit the vbuf from the specified pipe + * + * @param hdl + * @param pipe + * @param buf + * + * @return int + */ +int +__pci_xmit_buf(hif_handle_t hdl, int pipe, VBUF *vbuf) +{ + dma_engine_t eng; + + eng = __pci_get_tx_eng(pipe); + + if (eng == DMA_ENGINE_MAX) { + A_PRINTF("Invalid Pipe number\n"); + return -1; + } + + return dma_lib_hard_xmit(eng, vbuf); +} +/** + * @brief Submit the receive vbuf into the receive queue + * + * @param handle + * @param pipe + * @param buf + */ +void +__pci_return_recv(hif_handle_t hdl, int pipe, VBUF *buf) +{ + dma_engine_t eng; + + eng = __pci_get_rx_eng(pipe); + + if (eng == DMA_ENGINE_MAX) + return; + + dma_lib_return_recv(eng, buf); +} +/** + * @brief Is this pipe number supported + * + * @param handle + * @param pipe + * + * @return int + */ +int +__pci_is_pipe_supported(hif_handle_t hdl, int pipe) +{ + if (pipe >= 0 && pipe <= 4) + return 1; + else + return 0; +} +/** + * @brief maximum message length this pipe can support + * + * @param handle + * @param pipe + * + * @return int + */ +int +__pci_get_max_msg_len(hif_handle_t hdl, int pipe) +{ + if( pipe == HIF_PCI_PIPE_TX0 || pipe == HIF_PCI_PIPE_RX0) + return PCI_MAX_CMD_PKT_LEN; + + return PCI_MAX_DATA_PKT_LEN; +} +/** + * @brief return the header room required by this HIF + * + * @param hdl + * + * @return int + */ +int +__pci_get_reserved_headroom(hif_handle_t hdl) +{ + return 0; +} +/** + * @brief Device shutdown, HIF reset required + * + * @param hdl + */ +void +__pci_shutdown(hif_handle_t hdl) +{ + return; +} + +void +__pci_get_def_pipe(hif_handle_t handle, A_UINT8 *pipe_rx, A_UINT8 *pipe_tx) +{ + *pipe_rx = HIF_PCI_PIPE_RX0; + *pipe_tx = HIF_PCI_PIPE_TX0; +} +/** + * @brief This install the API's of the HIF + * + * @param apis + */ +void +hif_pci_module_install(struct hif_api *apis) +{ + /* hook in APIs */ + apis->_init = __pci_init; + apis->_start = __pci_start; + apis->_config_pipe = __pci_cfg_pipe; + apis->_isr_handler = __pci_isr_handler; + apis->_send_buffer = __pci_xmit_buf; + apis->_return_recv_buf = __pci_return_recv; + apis->_is_pipe_supported = __pci_is_pipe_supported; + apis->_get_max_msg_len = __pci_get_max_msg_len; + apis->_register_callback = __pci_reg_callback; + apis->_shutdown = __pci_shutdown; + apis->_get_reserved_headroom = __pci_get_reserved_headroom; + apis->_get_default_pipe = __pci_get_def_pipe; +} + +void +cmnos_pci_module_install(struct pci_api *apis) +{ + apis->pci_boot_init = __pci_boot_init; +} diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/Makefile new file mode 100755 index 0000000..9c79567 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/Makefile @@ -0,0 +1,51 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export LAYERNAME = hif +export SSNAME = usb + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(LAYERNAME)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/Makefile.ss new file mode 100755 index 0000000..d769958 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/Makefile.ss @@ -0,0 +1,47 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/HIF_usb.o \ + $(SSOBJPATH)/usb_api.o \ + $(SSOBJPATH)/usb_table.o \ + $(SSOBJPATH)/usb_fifo.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/HIF_usb.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/HIF_usb.c new file mode 100755 index 0000000..5d48a7c --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/HIF_usb.c @@ -0,0 +1,645 @@ +/* + * @File: HIF_usb.c + * + * @Abstract: USB implementation of HIF + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ +#include "sys_cfg.h" +#include "dt_defs.h" +#include "reg_defs.h" + +#include +//#include +#include +#include +#include +#include +//#include +#include + +#include "hif_usb.h" + +HIF_USB_CONTEXT g_hifUSBCtx; + + +static void send_buffer_via_fifo(VBUF *buf); +static int _HIFusb_get_reserved_headroom(hif_handle_t handle); +static struct zsDmaQueue* get_queue_from_pipe(int pipe); + +int _HIFusb_get_max_msg_len(hif_handle_t handle, int pipe); + +//#define OTUS_USB + +static VBUF* usbfifo_get_command_buf() +{ + VBUF *buf; + + buf = g_hifUSBCtx.cmdQueue; + g_hifUSBCtx.cmdQueue = buf->next_buf; + buf->next_buf = NULL; + return buf; +} + +static void usbfifo_recv_command(VBUF *buf) +{ +#if ENABLE_SW_SWAP_DATA_MODE + VDESC *currVdesc; + struct zsDmaDesc* usbDesc; +#endif + + #if ZM_FM_LOOPBACK == 1 + send_buffer_via_fifo(buf); + #else + +#if ENABLE_SW_SWAP_DATA_MODE + currVdesc = (VDESC *)buf->desc_list; + usbDesc = (struct zsDmaDesc *)currVdesc->hw_desc_buf; + usbDesc->dataSize = currVdesc->data_size; + usbDesc->dataAddr = (volatile u32_t)(currVdesc->buf_addr + currVdesc->data_offset); + + DMA_Engine_swap_data(usbDesc); +#endif + g_hifUSBCtx.hifCb.recv_buf(NULL, buf, g_hifUSBCtx.hifCb.context); + #endif +} + +static VBUF* usbfifo_get_event_buf() +{ + VBUF *buf; + + buf = g_hifUSBCtx.eventBufQ.head; + if ( g_hifUSBCtx.eventBufQ.head == g_hifUSBCtx.eventBufQ.tail ) { + g_hifUSBCtx.eventBufQ.head = NULL; + g_hifUSBCtx.eventBufQ.tail = NULL; + } else { + g_hifUSBCtx.eventBufQ.head = buf->next_buf; + } + + buf->next_buf = NULL; + return buf; +} + +static void usbfifo_send_event_done(VBUF *buf) +{ + #if ZM_FM_LOOPBACK == 1 + ; // LOOPBACK? + _HIFusb_return_recv_buf(NULL, HIF_USB_PIPE_COMMAND, buf); + #else + g_hifUSBCtx.hifCb.send_buf_done(buf, g_hifUSBCtx.hifCb.context); + #endif +} + +#define MAGPIE_ENABLE_USBFIFO + +hif_handle_t _HIFusb_init(HIF_CONFIG *pConfig) +{ + USB_FIFO_CONFIG usbfifo; + +#ifdef MAGPIE_ENABLE_USBFIFO + usbfifo.get_command_buf = usbfifo_get_command_buf; + usbfifo.recv_command = usbfifo_recv_command; + usbfifo.get_event_buf = usbfifo_get_event_buf; + usbfifo.send_event_done = usbfifo_send_event_done; + USBFIFO_init(&usbfifo); +#endif + + // Initialize the terminator descriptor for dnQ & upQ + DMA_Engine_init_rx_queue(&g_hifUSBCtx.dnQ); + DMA_Engine_init_tx_queue(&g_hifUSBCtx.upQ); + +#if SYSTEM_MODULE_HP_EP5 + DMA_Engine_init_rx_queue(&g_hifUSBCtx.hpdnQ); +#endif + +#if SYSTEM_MODULE_HP_EP6 + DMA_Engine_init_rx_queue(&g_hifUSBCtx.mpdnQ); +#endif + + g_hifUSBCtx.eventBufQ.head = NULL; + g_hifUSBCtx.eventBufQ.tail = NULL; + g_hifUSBCtx.cmdQueue = NULL; + + return NULL; +} + +void _HIFusb_shutdown(hif_handle_t handle) +{ + // nothing to do in FW +} + +void _HIFusb_register_callback(hif_handle_t handle, HIF_CALLBACK *pConfig) +{ + //HIF_INPROC_CONTEXT *hifInprocCtx = (HIF_INPROC_CONTEXT *)handle; + + g_hifUSBCtx.hifCb.send_buf_done = pConfig->send_buf_done; + g_hifUSBCtx.hifCb.recv_buf = pConfig->recv_buf; + g_hifUSBCtx.hifCb.context = pConfig->context; + + return; +} + +//#define MAGPIE_REG_USB_ +void _HIFusb_start(hif_handle_t handle) +{ +#ifdef OTUS_USB + ZM_PTA_DN_DMA_ADDRH_REG = (u32_t)g_hifUSBCtx.dnQ.head >> 16; + ZM_PTA_DN_DMA_ADDRL_REG = (u32_t)g_hifUSBCtx.dnQ.head & 0xffff; + + ZM_PTA_UP_DMA_ADDRH_REG = (u32_t)g_hifUSBCtx.upQ.head >> 16; + ZM_PTA_UP_DMA_ADDRL_REG = (u32_t)g_hifUSBCtx.upQ.head & 0xffff; +#else + A_PRINTF("\n\r\t=>[dnQ] 0x%08x \n[", (u32_t)g_hifUSBCtx.dnQ.head); + A_PRINTF("\t=>[upQ] 0x%08x \n[", (u32_t)g_hifUSBCtx.upQ.head); + + MAGPIE_REG_USB_RX0_DESC_START = (u32_t)g_hifUSBCtx.dnQ.head; + MAGPIE_REG_USB_TX0_DESC_START = (u32_t)g_hifUSBCtx.upQ.head; +#if SYSTEM_MODULE_HP_EP5 + A_PRINTF("\t=>[hp dnQ] 0x%08x \n[", (u32_t)g_hifUSBCtx.hpdnQ.head); + MAGPIE_REG_USB_RX1_DESC_START = (u32_t)g_hifUSBCtx.hpdnQ.head; +#endif + +#if SYSTEM_MODULE_HP_EP6 + A_PRINTF("\t=>[mp dnQ] 0x%08x \n[", (u32_t)g_hifUSBCtx.mpdnQ.head); + MAGPIE_REG_USB_RX2_DESC_START = (u32_t)g_hifUSBCtx.mpdnQ.head; +#endif + + MAGPIE_REG_USB_INTERRUPT_MASK = 0xffffffff; // enable all interrupt, refer to 7-34, Ryan + MAGPIE_REG_USB_RX0_DMA_START = 1; + +#if SYSTEM_MODULE_HP_EP5 + MAGPIE_REG_USB_RX1_DMA_START = 1; + #endif + +#if SYSTEM_MODULE_HP_EP6 + MAGPIE_REG_USB_RX2_DMA_START = 1; +#endif +#endif +} + +static int _HIFusb_get_reserved_headroom(hif_handle_t handle) +{ + return 0; +} + +static void config_command_pipe(VDESC *desc_list) +{ + VDESC *theDesc; + VBUF *buf; + + theDesc = desc_list; + while ( theDesc != NULL ) { + buf = VBUF_alloc_vbuf(); + + buf->desc_list = theDesc; + theDesc = theDesc->next_desc; + buf->desc_list->next_desc = NULL; + + if ( g_hifUSBCtx.cmdQueue == NULL ) { + g_hifUSBCtx.cmdQueue = buf; + } else { + buf->next_buf = g_hifUSBCtx.cmdQueue; + g_hifUSBCtx.cmdQueue = buf; + } + } +} + +static void enable_rx(int pipe) +{ + if ( pipe == HIF_USB_PIPE_TX ) { + #ifdef OTUS_USB + ZM_PTA_DN_DMA_TRIGGER_REG = 1; + #else + MAGPIE_REG_USB_RX0_DMA_START = 1; + #endif + } +#if SYSTEM_MODULE_HP_EP5 + else if ( pipe == HIF_USB_PIPE_HP_TX ) { + MAGPIE_REG_USB_RX1_DMA_START = 1; + } +#endif +#if SYSTEM_MODULE_HP_EP6 + else if ( pipe == HIF_USB_PIPE_MP_TX ) { + MAGPIE_REG_USB_RX2_DMA_START = 1; + } +#endif +} + +static struct zsDmaQueue* get_queue_from_pipe(int pipe) +{ + struct zsDmaQueue* q = NULL; + + if ( pipe == HIF_USB_PIPE_TX ) { + q = &g_hifUSBCtx.dnQ; + } +#if SYSTEM_MODULE_HP_EP5 + else if ( pipe == HIF_USB_PIPE_HP_TX ) + { + q = &g_hifUSBCtx.hpdnQ; + } +#endif +#if SYSTEM_MODULE_HP_EP6 + else if ( pipe == HIF_USB_PIPE_MP_TX ) + { + q = &g_hifUSBCtx.mpdnQ; + } +#endif + else { + adf_os_assert(0); + } + + return q; +} + +//#define MAX_TX_BUF_SIZE ZM_BLOCK_SIZE +//#define MAX_TX_BUF_SIZE 1600 + +//void _HIFusb_config_pipe(hif_handle_t handle, int pipe, VDESC *desc_list) +void _HIFusb_config_pipe(hif_handle_t handle, int pipe, int creditCount) +{ + int i; + VDESC *desc; + VDESC *head = NULL; + struct zsDmaQueue *q; + + if ( pipe != HIF_USB_PIPE_COMMAND ) { + goto config_pipe; + } + + // USB command pipe doesn't use FIFO + for(i=0; i < creditCount; i++) + { + desc = VDESC_alloc_vdesc(); + + adf_os_assert(desc != NULL); + + desc->buf_addr = (A_UINT8 *)adf_os_mem_alloc(HIF_get_max_msg_len(handle, pipe)); + desc->buf_size = HIF_get_max_msg_len(handle, pipe); + desc->next_desc = NULL; + desc->data_offset = 0; + desc->data_size = 0; + desc->control = 0; + + if ( head == NULL ) + { + head = desc; + } + else + { + desc->next_desc = head; + head = desc; + } + } + + config_command_pipe(head); + return; + +config_pipe: + q = get_queue_from_pipe(pipe); + DMA_Engine_config_rx_queue(q, creditCount, HIF_get_max_msg_len(handle, pipe)); + enable_rx(pipe); + return; +} + +static void send_buffer_via_fifo(VBUF *buf) +{ +#if ENABLE_SW_SWAP_DATA_MODE + VDESC *currVdesc; + struct zsDmaDesc* usbDesc; + + //A_PRINTF("send_buffer_via_fifo buf len %d\n", buf->buf_length); + currVdesc = (VDESC *)buf->desc_list; + usbDesc = (struct zsDmaDesc *)currVdesc->hw_desc_buf; + usbDesc->dataSize = currVdesc->data_size; + usbDesc->dataAddr = (volatile u32_t)(currVdesc->buf_addr + currVdesc->data_offset); + + DMA_Engine_swap_data(usbDesc); +#endif + + if ( g_hifUSBCtx.eventBufQ.head == NULL ) { + g_hifUSBCtx.eventBufQ.head = buf; + g_hifUSBCtx.eventBufQ.tail = buf; + } else { + g_hifUSBCtx.eventBufQ.tail->next_buf = buf; + g_hifUSBCtx.eventBufQ.tail = buf; + } + + USBFIFO_enable_event_isr(); +} + +int _HIFusb_send_buffer(hif_handle_t handle, int pipe, VBUF *buf) +{ + if ( pipe == HIF_USB_PIPE_INTERRUPT ) { + send_buffer_via_fifo(buf); + } else { + DMA_Engine_xmit_buf(&g_hifUSBCtx.upQ, buf); +#ifdef OTUS_USB + ZM_PTA_UP_DMA_TRIGGER_REG = 1; +#else + MAGPIE_REG_USB_TX0_DMA_START = 1; +#endif + } + + return 0; +} + + +void _HIFusb_return_recv_buf(hif_handle_t handle, int pipe, VBUF *buf) +{ + struct zsDmaQueue *q; + + if ( pipe == HIF_USB_PIPE_COMMAND ) { + if ( g_hifUSBCtx.cmdQueue == NULL ) { + g_hifUSBCtx.cmdQueue = buf; + } else { + buf->next_buf = g_hifUSBCtx.cmdQueue; + g_hifUSBCtx.cmdQueue = buf; + } + } else { + q = get_queue_from_pipe(pipe); + DMA_Engine_return_recv_buf(q, buf); + enable_rx(pipe); + } +} + +void _HIFusb_set_recv_bufsz(hif_handle_t handle, int pipe, int bufsz) +{ + (void)pipe; + (void)bufsz; +} + +void _HIFusb_pause_recv(hif_handle_t handle, int pipe) +{ + (void)pipe; +} + +void _HIFusb_resume_recv(hif_handle_t handle, int pipe) +{ + (void)pipe; +} + +int _HIFusb_is_pipe_supported(hif_handle_t handle, int pipe) +{ + if ( pipe < HIF_USB_PIPE_TX || pipe > HIF_USB_PIPE_MP_TX ) { + return 0; + } else { + return 1; + } +} + +int _HIFusb_get_max_msg_len(hif_handle_t handle, int pipe) +{ + switch(pipe) { + case HIF_USB_PIPE_INTERRUPT: + case HIF_USB_PIPE_COMMAND: + return 64; + + default: + return 1600; + } +} + +static void handle_tx_complete_isr() +{ + VBUF *buf; + + //A_PRINTF("USB Tx complete\n\r"); + #if ZM_FM_LOOPBACK == 1 + VDESC *vdesc; + struct zsDmaDesc* desc; + + desc = DMA_Engine_get_packet(&g_hifUSBCtx.upQ); + vdesc = VDESC_HW_TO_VDESC(desc); + + if ( vdesc->control == HIF_USB_PIPE_TX ) { + DMA_Engine_reclaim_packet(&g_hifUSBCtx.dnQ, desc); + } + #if SYSTEM_MODULE_HP_EP5 + else if ( vdesc->control == HIF_USB_PIPE_HP_TX ) { + DMA_Engine_reclaim_packet(&g_hifUSBCtx.hpdnQ, desc); + } + #endif + #if SYSTEM_MODULE_HP_EP6 + else if ( vdesc->control == HIF_USB_PIPE_MP_TX ) { + DMA_Engine_reclaim_packet(&g_hifUSBCtx.mpdnQ, desc); + } + #endif + + #ifdef OTUS_USB + ZM_PTA_DN_DMA_TRIGGER_REG = 1; + #else + MAGPIE_REG_USB_RX0_DMA_START = 1; + #endif + + #else + buf = DMA_Engine_reap_xmited_buf(&g_hifUSBCtx.upQ); + g_hifUSBCtx.hifCb.send_buf_done(buf, g_hifUSBCtx.hifCb.context); + #endif /* ZM_FM_LOOPBACK == 1 */ +} + +static void handle_rx_complete_isr() +{ + VBUF *buf; + + #if ZM_FM_LOOPBACK == 1 + VDESC *vdesc; + struct zsDmaDesc* desc; + + //A_PRINTF("USB Rx complete\n\r"); + desc = DMA_Engine_get_packet(&g_hifUSBCtx.dnQ); + vdesc = VDESC_HW_TO_VDESC(desc); + vdesc->control = HIF_USB_PIPE_TX; + + DMA_Engine_put_packet(&g_hifUSBCtx.upQ, desc); + + #ifdef OTUS_USB + ZM_PTA_UP_DMA_TRIGGER_REG = 1; + #else + MAGPIE_REG_USB_TX0_DMA_START = 1; + #endif + + #else + buf = DMA_Engine_reap_recv_buf(&g_hifUSBCtx.dnQ); + g_hifUSBCtx.hifCb.recv_buf(NULL, buf, g_hifUSBCtx.hifCb.context); + #endif +} + +#if SYSTEM_MODULE_HP_EP5 +static void handle_hp_rx_complete_isr() +{ + VBUF *buf; + + #if ZM_FM_LOOPBACK == 1 + VDESC *vdesc; + struct zsDmaDesc* desc; + + desc = DMA_Engine_get_packet(&g_hifUSBCtx.hpdnQ); + vdesc = VDESC_HW_TO_VDESC(desc); + vdesc->control = HIF_USB_PIPE_HP_TX; + + DMA_Engine_put_packet(&g_hifUSBCtx.upQ, desc); + MAGPIE_REG_USB_TX0_DMA_START = 1; + + #else + buf = DMA_Engine_reap_recv_buf(&g_hifUSBCtx.hpdnQ); + g_hifUSBCtx.hifCb.recv_buf(NULL, buf, g_hifUSBCtx.hifCb.context); + #endif +} +#endif + +#if SYSTEM_MODULE_HP_EP6 +static void handle_mp_rx_complete_isr() +{ + VBUF *buf; + + #if ZM_FM_LOOPBACK == 1 + VDESC *vdesc; + struct zsDmaDesc* desc; + + desc = DMA_Engine_get_packet(&g_hifUSBCtx.mpdnQ); + vdesc = VDESC_HW_TO_VDESC(desc); + vdesc->control = HIF_USB_PIPE_MP_TX; + + DMA_Engine_put_packet(&g_hifUSBCtx.upQ, desc); + MAGPIE_REG_USB_TX0_DMA_START = 1; + + #else + buf = DMA_Engine_reap_recv_buf(&g_hifUSBCtx.mpdnQ); + g_hifUSBCtx.hifCb.recv_buf(NULL, buf, g_hifUSBCtx.hifCb.context); + #endif +} +#endif + +void _HIFusb_isr_handler(hif_handle_t h) +{ + //struct zsDmaDesc* desc; + u32_t intr; + +#ifdef OTUS_USB + intr = ZM_PTA_INT_FLAG_REG; +#else + intr = MAGPIE_REG_USB_INTERRUPT; +#endif + +#ifdef OTUS_USB + if ((intr & (ZM_PTA_DOWN_INT_BIT|ZM_PTA_UP_INT_BIT))!=0) +#else + if ((intr & (MAGPIE_REG_USB_INTERRUPT_TX0_COMPL|MAGPIE_REG_USB_INTERRUPT_RX0_COMPL| + MAGPIE_REG_USB_INTERRUPT_RX1_COMPL|MAGPIE_REG_USB_INTERRUPT_RX2_COMPL)) != 0) +#endif + { +#if SYSTEM_MODULE_HP_EP5 + do + { + if ( DMA_Engine_has_compl_packets(&g_hifUSBCtx.hpdnQ) ) + { + handle_hp_rx_complete_isr(); + } + else + { + break; + } + } + while(1); +#endif // endif SYSTEM_MODULE_HP_EP5 + +#if SYSTEM_MODULE_HP_EP6 + do + { + if ( DMA_Engine_has_compl_packets(&g_hifUSBCtx.mpdnQ) ) + { + handle_mp_rx_complete_isr(); + } + else + { + break; + } + } + while(1); +#endif // endif SYSTEM_MODULE_HP_EP5 + + do + { + int check = 0; + + /* zgUpQ own bits changed */ + if ( DMA_Engine_has_compl_packets((struct zsDmaQueue *)&g_hifUSBCtx.upQ) ) + { + handle_tx_complete_isr(); + check = 1; + }/* end of while */ + + /* zgDnQ own bits changed */ + if ( DMA_Engine_has_compl_packets(&g_hifUSBCtx.dnQ) ) + { + handle_rx_complete_isr(); + check = 1; + } + + if ( check == 0 ) + { + break; + } + } + while(1); + } +} + +void _HIFusb_get_default_pipe(hif_handle_t handle, A_UINT8 *pipe_uplink, A_UINT8 *pipe_downlink) +{ + *pipe_uplink = HIF_USB_PIPE_COMMAND; // Host -> Target + *pipe_downlink = HIF_USB_PIPE_INTERRUPT; // Target -> Host +} + +/* the exported entry point into this module. All apis are accessed through + * function pointers */ +void hif_usb_module_install(struct hif_api *apis) +{ + /* hook in APIs */ + apis->_init = _HIFusb_init; + apis->_start = _HIFusb_start; + apis->_config_pipe = _HIFusb_config_pipe; + apis->_isr_handler = _HIFusb_isr_handler; + apis->_send_buffer = _HIFusb_send_buffer; + apis->_return_recv_buf = _HIFusb_return_recv_buf; + apis->_is_pipe_supported = _HIFusb_is_pipe_supported; + apis->_get_max_msg_len = _HIFusb_get_max_msg_len; + apis->_register_callback = _HIFusb_register_callback; + apis->_shutdown = _HIFusb_shutdown; + apis->_get_reserved_headroom = _HIFusb_get_reserved_headroom; + apis->_get_default_pipe = _HIFusb_get_default_pipe; + + /* save ptr to the ptr to the context for external code to inspect/modify internal module state */ + //apis->pReserved = &g_pMboxHWContext; +} + +void HIFusb_DescTraceDump(void ) +{ +#if SYSTEM_MODULE_HP_EP5 + A_PRINTF("\n\r[hp dnQ] 0x%08x, ", (u32_t)g_hifUSBCtx.hpdnQ.head); + A_PRINTF("DMA TRACE 0x%08x\n\r [", HAL_WORD_REG_READ(MAGPIE_REG_USB_RX1_CUR_TRACE_ADDR)); + + DMA_Engine_desc_dump(&g_hifUSBCtx.hpdnQ); +#endif + +#if SYSTEM_MODULE_HP_EP6 + A_PRINTF("\n\r[mp dnQ] 0x%08x, ", (u32_t)g_hifUSBCtx.mpdnQ.head); + A_PRINTF("DMA TRACE 0x%08x\n\r [", HAL_WORD_REG_READ(MAGPIE_REG_USB_RX2_CUR_TRACE_ADDR)); + + DMA_Engine_desc_dump(&g_hifUSBCtx.mpdnQ); +#endif + + A_PRINTF("\n\r[dnQ] 0x%08x, ", (u32_t)g_hifUSBCtx.dnQ.head); + A_PRINTF("DMA TRACE 0x%08x\n\r [", HAL_WORD_REG_READ(MAGPIE_REG_USB_RX0_CUR_TRACE_ADDR)); + DMA_Engine_desc_dump(&g_hifUSBCtx.dnQ); + + A_PRINTF("\n\n\r[upQ] 0x%08x, ", (u32_t)g_hifUSBCtx.upQ.head); + A_PRINTF("DMA TRACE 0x%08x\n\r [", HAL_WORD_REG_READ(MAGPIE_REG_USB_TX0_CUR_TRACE_ADDR)); + DMA_Engine_desc_dump((struct zsDmaQueue *)&g_hifUSBCtx.upQ); +} + + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_api.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_api.c new file mode 100755 index 0000000..897bcfa --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_api.c @@ -0,0 +1,2499 @@ +#include "usb_defs.h" +#include "usb_type.h" +#include "usb_pre.h" +#include "usb_extr.h" +#include "usb_std.h" +#include "reg_defs.h" +#include "athos_api.h" +#include "usbfifo_api.h" + +#include "sys_cfg.h" + +#if SYSTEM_MODULE_USB + +#define CMD_GET_CUSTOM_DATA 4 +LOCAL void flash_read(uint16_t len, uint16_t ofset); + +SetupPacket ControlCmd; +USB_FIFO_CONFIG usbFifoConf; +uint32_t fwCheckSum = 0; + +#define fBUS_POWER 1 +uint16_t UsbStatus[3]; + +/* Variable for USB EP0 pipe (USB.c) */ +uint16_t *pu8DescriptorEX; +uint16_t u16TxRxCounter; +uint16_t *u8ConfigDescriptorEX; +//extern BOOLEAN bUsbEP0HaltSt; +Action eUsbCxFinishAction; +CommandType eUsbCxCommand; +BOOLEAN UsbChirpFinish; + +uint16_t u8UsbConfigValue; +uint16_t u8UsbInterfaceValue; +uint16_t u8UsbInterfaceAlternateSetting; +uint16_t u16FirmwareComplete; + +extern uint16_t *UsbDeviceDescriptor; +extern uint16_t *String00Descriptor; +extern uint16_t *String10Descriptor; +extern uint16_t *String20Descriptor; +extern uint16_t *String30Descriptor; + +///////////////////////////////////////////////// +// should be declared as extern array not pointer +extern uint16_t u8DeviceQualifierDescriptorEX[]; +extern uint16_t u8OtherSpeedConfigDescriptorEX[]; + +uint16_t *u8UsbDeviceDescriptor; +uint16_t *u8String00Descriptor; +uint16_t *u8String10Descriptor; +uint16_t *u8String20Descriptor; +uint16_t *u8String30Descriptor; + + +#if 0 // use macro instead of function +void mUsbEPinRsTgSet(uint8_t u8ep) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)); + //*reg |= BIT4; + USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4)); + +} + +void mUsbEPinRsTgClr(uint8_t u8ep) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)); + //*reg &= ~BIT4; + USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT4))); +} + +void mUsbEPoutRsTgSet(uint8_t u8ep) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)); + //*reg |= BIT4; + USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4)); +} + +void mUsbEPoutRsTgClr(uint8_t u8ep) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)); + //*reg &= ~BIT4; + USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT4))); +} + +void mUsbEPinStallSet(uint8_t u8ep) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)); + //*reg |= BIT3; + USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3); +} + +void mUsbEPinStallClr(uint8_t u8ep) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)); + //*reg &= ~BIT3; + + USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT3))); +} + +void mUsbEPoutStallSet(uint8_t u8ep) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)); + //*reg |= BIT3; + USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3)); +} + +void mUsbEPoutStallClr(uint8_t u8ep) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)); + //*reg &= ~BIT3; + USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + (USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&(~BIT3))); +} + +uint8_t mUsbEPinStallST(uint8_t u8ep) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)); + //return ((*reg & BIT3) >> 3); + return ((USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3); +} + +uint8_t mUsbEPoutStallST(uint8_t u8ep) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)); + //return ((*reg & BIT3) >> 3); + return ((USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3); +} + +uint8_t mUsbEPMapRd(uint8_t EPn) +{ + //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x30+(EPn-1)); + //return *reg; + return (USB_BYTE_REG_READ((0x30+(EPn-1)))); +} + +uint8_t mUsbFIFOCfgRd(uint8_t FIFOn) +{ + //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x90+FIFOn); + //return *reg; + return (USB_BYTE_REG_READ((0x90+FIFOn))); +} + +void vUsb_Data_Out0Byte(void) +{ + //ZM_INTR_SOURCE_7_REG &= ~BIT7; + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&(~BIT7)))); +} + + +void vUsb_Data_In0Byte(void) +{ + //ZM_INTR_SOURCE_7_REG &= ~BIT6; + + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&(~BIT6)))); +} + + +/***********************************************************************/ +// vUsb_ep0end() +// Description: +// 1. End this transfer. +// input: none +// output: none +/***********************************************************************/ +void vUsb_ep0end(void) +{ + eUsbCxCommand = CMD_VOID; + //ZM_CX_CONFIG_STATUS_REG = 0x01; + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); + //mUsbEP0DoneSet(); // Return EP0_Done flag +} + +/***********************************************************************/ +// vUsb_ep0fail() +// Description: +// 1. Stall this transfer. +// input: none +// output: none +/***********************************************************************/ +void vUsb_ep0fail(void) +{ + //ZM_CX_CONFIG_STATUS_REG = 0x04; + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04); + //mUsbEP0StallSet(); // Return EP0_Stall +} + + +/***********************************************************************/ +// vUsb_rst() +// Description: +// 1. Change descriptor table (High or Full speed). +// input: none +// output: none +/***********************************************************************/ +void vUsb_rst(void) +{ +// zfUartSendStr((uint8_t *) "vUsb_rst\r\n"); + //ZM_INTR_SOURCE_7_REG &= ~0x02; + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&(~BIT1))); + UsbChirpFinish = FALSE; +} + +/***********************************************************************/ +// vUsb_suspend() +// Description: +// 1. . +// input: none +// output: none +/***********************************************************************/ +void vUsb_suspend(void) +{ +// uP must do-over everything it should handle +// and do before into the suspend mode + //mUsbIntSuspClr(); // Go Suspend status + //ZM_INTR_SOURCE_7_REG &= ~0x04; + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&(~BIT2))); +} + +/***********************************************************************/ +// vUsb_resm() +// Description: +// 1. Change descriptor table (High or Full speed). +// input: none +// output: none +/***********************************************************************/ +void vUsb_resm(void) +{ +// uP must do-over everything it should handle +// and do before into the suspend mode + +// mUsbIntResmClr(); // uP must wakeup immediately + //ZM_INTR_SOURCE_7_REG &= ~0x08; + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&(~BIT3))); +} + +#else + +#define mUsbEPinRsTgSet(u8ep) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4) + +#define mUsbEPinRsTgClr(u8ep) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT4) + +#define mUsbEPoutRsTgSet(u8ep) USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT4) + +#define mUsbEPoutRsTgClr(u8ep) USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT4) + +#define mUsbEPinStallSet(u8ep) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3) + +#define mUsbEPinStallClr(u8ep) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT3) + +#define mUsbEPoutStallSet(u8ep) USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))|BIT3) + +#define mUsbEPoutStallClr(u8ep) USB_BYTE_REG_WRITE((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)), \ + USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))&~BIT3) + +#define mUsbEPinStallST(u8ep) ((USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3) + +#define mUsbEPoutStallST(u8ep) ((USB_BYTE_REG_READ((ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET+(u8ep << 1)))& BIT3) >> 3) + +#define mUsbEPMapRd(EPn) (USB_BYTE_REG_READ((0x30+(EPn-1)))) + +#define mUsbFIFOCfgRd(FIFOn) (USB_BYTE_REG_READ((0x90+FIFOn))) + +#define vUsb_Data_Out0Byte(void) USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \ + USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&~BIT7)) + + +#define vUsb_Data_In0Byte(void) USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, \ + USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_REG&~BIT6)) + +#define vUsb_ep0end(void) \ +{ \ + eUsbCxCommand = CMD_VOID; \ + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); \ +} + +#define vUsb_ep0fail(void) USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04) + +#define vUsb_rst() \ +{ \ + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT1)); \ + UsbChirpFinish = FALSE; \ +} + +#define vUsb_suspend() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT2)) + +#define vUsb_resm() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT3)) + + +#endif + +LOCAL void flash_read_data(void) +{ + uint8_t u8temp; + + // to keep tracking the txrx fifo + // max 64 bytes for transmission one time, + if (u16TxRxCounter < EP0MAXPACKETSIZE) + u8temp = (uint8_t) u16TxRxCounter; + else + u8temp = EP0MAXPACKETSIZE; + + u16TxRxCounter -= (uint16_t) u8temp; + + { + register uint8_t u8count; + uint8_t remainder; + + for (u8count = 0; u8count < (u8temp/4); u8count ++) + { + uint32_t ep0_data; + uint16_t ep0_low; + uint16_t ep0_high; + + // pack data into word size + ep0_low = *pu8DescriptorEX++; + ep0_high = *pu8DescriptorEX++; + + // composed the data as a word + ep0_data = (ep0_high << 16) + ep0_low; + + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data); + } + + remainder = u8temp % 4; + + // Check whether there are data needed to be filled into the FIFO + if (remainder == 3) + { + uint32_t ep0_data; + uint16_t ep0_low; + uint16_t ep0_high; + + // pack data into word size + ep0_low = *pu8DescriptorEX++; + ep0_high = *pu8DescriptorEX++; + + ep0_data = (ep0_high << 16) + ep0_low; + + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data); + } + else if (remainder == 2) + { + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX); + } + else if (remainder == 1) + { + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX); + } + + // Restore CBus FIFO size to word size + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf); + } + + // end of the data stage + if (u16TxRxCounter == 0) + { + eUsbCxCommand = CMD_VOID; + eUsbCxFinishAction = ACT_DONE; + } +} + +/***********************************************************************/ +// vUsb_ep0tx() +// Description: +// 1. Transmit data to EP0 FIFO. +// input: none +// output: none +/***********************************************************************/ +LOCAL void vUsb_ep0tx(void) +{ + switch (eUsbCxCommand) + { + case CMD_GET_DESCRIPTOR: + A_USB_EP0_TX_DATA(); + break; + + default: + /* Mark endpoint STALL */ + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT6); + + break; + } + +// eUsbCxFinishAction = ACT_IDLE; +} + + +/***********************************************************************/ +// vUsb_ep0rx() +// Description: +// 1. Receive data from EP0 FIFO. +// input: none +// output: none +/***********************************************************************/ +LOCAL void vUsb_ep0rx(void) +{ + + switch (eUsbCxCommand) + { + case CMD_SET_DESCRIPTOR: + A_USB_EP0_RX_DATA(); + break; + default: + //mUsbEP0StallSet(); + break; + } + + if (u16TxRxCounter != 0) + eUsbCxFinishAction = ACT_IDLE; +} + + +LOCAL void vUsbClrEPx(void) +{ + uint8_t u8ep; + + // Clear All EPx Toggle Bit + for (u8ep = 1; u8ep <= FUSB200_MAX_EP; u8ep ++) + { + mUsbEPinRsTgSet(u8ep); + mUsbEPinRsTgClr(u8ep); + } + for (u8ep = 1; u8ep <= FUSB200_MAX_EP; u8ep ++) + { + mUsbEPoutRsTgSet(u8ep); + mUsbEPoutRsTgClr(u8ep); + } +} + + +/***********************************************************************/ +// bGet_status() +// Description: +// 1. Send 2 bytes status to host. +// input: none +// output: TRUE or FALSE (BOOLEAN) +/***********************************************************************/ +LOCAL BOOLEAN bGet_status(void) +{ + uint8_t RecipientStatusLow; + + RecipientStatusLow = UsbStatus[mDEV_REQ_REQ_RECI() & 0x0F]; + + //ZM_CBUS_FIFO_SIZE_REG = 0x3; + //ZM_EP0_DATA_REG = RecipientStatusLow; + + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, RecipientStatusLow); + + // Restore CBus FIFO size to word size + //ZM_CBUS_FIFO_SIZE_REG = 0xf; + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf); + + eUsbCxFinishAction = ACT_DONE; + return TRUE; +} + +/***********************************************************************/ +// bClear_feature() +// Description: +// 1. Send 2 bytes status to host. +// input: none +// output: TRUE or FALSE (BOOLEAN) +/***********************************************************************/ +LOCAL BOOLEAN bClear_feature(void) +{ + if (mDEV_REQ_VALUE() > cUSB_FEATSEL_END) + return FALSE; + + if ((mDEV_REQ_VALUE() == 0) && (mDEV_REQ_REQ_RECI() != cUSB_REQTYPE_ENDPOINT)) + return FALSE; + + UsbStatus[2] = 0; + eUsbCxFinishAction = ACT_DONE; + + return TRUE; +} + +/***********************************************************************/ +// bSet_feature() +// Description: +// 1. Send 2 bytes status to host. +// input: none +// output: TRUE or FALSE (BOOLEAN) +/***********************************************************************/ +#if ZM_SELF_TEST_MODE + +#define TEST_J 0x02 +#define TEST_K 0x04 +#define TEST_SE0_NAK 0x08 +#define TEST_PKY 0x10 + +uint16_t TestPatn0[] = { TEST_J, TEST_K, TEST_SE0_NAK }; +uint32_t TestPatn1[] = { + 0x00000000, 0x00000000, 0xAA00AA00, // JKJKJKJK x 9 + 0xAAAAAAAA, 0xEEAAAAAA, // AA x 8 + 0xEEEEEEEE, 0xFEEEEEEE, // EE x 8 + 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF, // FF x 11 + 0xF7EFDFBF, 0x7EFCFDFB, 0xFDFBDFBF}; + +#endif +LOCAL BOOLEAN bSet_feature(void) +{ + + //A_PRINTF("bSet_feature...\n\r"); + + switch (mDEV_REQ_VALUE()) // FeatureSelector + { + case 0: // ENDPOINT_HALE + // AVM Patch: + // always check RECEIPIENT + if (mDEV_REQ_REQ_RECI() == cUSB_REQTYPE_ENDPOINT) + { + eUsbCxFinishAction = ACT_DONE; + } + else + { + return FALSE; + } + + break; + + case 1 : // Device Remote Wakeup + // Set "Device_Remote_Wakeup", Turn on the"RMWKUP" bit in Mode Register + mUsbRmWkupSet(); + //USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0); + eUsbCxFinishAction = ACT_DONE; + break; + + #if ZM_SELF_TEST_MODE + case 2 : // Test Mode + // ii = mDEV_REQ_INDEX() >> 8; + // switch (ii) // TestSelector + switch (mDEV_REQ_INDEX() >> 8) // TestSelector + { + case 0x1: // Test_J + case 0x2: // Test_K + case 0x3: // TEST_SE0_NAK + // mUsbTsMdWr(TestPatn0[(mDEV_REQ_INDEX() >> 8) - 1]); + //ZM_PHY_TEST_SELECT_REG = TestPatn0[(mDEV_REQ_INDEX() >> 8) - 1]; + USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, (TestPatn0[(mDEV_REQ_INDEX() >> 8) - 1])); + eUsbCxFinishAction = ACT_DONE; + break; + + case 0x4: // Test_Packet + // mUsbTsMdWr(TEST_PKY); + // mUsbEP0DoneSet(); // special case: follow the test sequence + //ZM_PHY_TEST_SELECT_REG = TEST_PKY; + //ZM_CX_CONFIG_STATUS_REG = 0x01; + USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, TEST_PKY); + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0); + /***********************************************************************/////// + // Jay ask to modify, 91-6-5 (Begin) // + /***********************************************************************/////// + // mUsbTsMdWr(TEST_PKY); + // mUsbEP0DoneSet(); // special case: follow the test sequence + //ZM_PHY_TEST_SELECT_REG = TEST_PKY; + USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, TEST_PKY); + + //ZM_CX_CONFIG_STATUS_REG = 0x01; + /***********************************************************************/////// + // Jay ask to modify, 91-6-5 (Begin) // + /***********************************************************************/////// + { + uint16_t ii; + + /* Set to two bytes mode */ + //ZM_CBUS_FIFO_SIZE_REG = 0x0f; + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f); + + for (ii = 0; ii < sizeof(TestPatn1)/sizeof(uint32_t); ii++) + { + //ZM_EP0_DATA_REG = TestPatn1[ii]; + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, TestPatn1[ii]); + } + + /* Set to one byte mode */ + //ZM_CBUS_FIFO_SIZE_REG = 0x07; + //ZM_EP0_DATA_REG = 0x007EFDFB; + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x07); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, 0x007EFDFB); + + /* Set to four bytes mode */ + //ZM_CBUS_FIFO_SIZE_REG = 0x0f; + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f); + } + /***********************************************************************/////// + // Jay ask to modify, 91-6-5 (End) // + /***********************************************************************/////// + + // Turn on "r_test_packet_done" bit(flag) (Bit 5) + //mUsbTsPkDoneSet(); + //ZM_CX_CONFIG_STATUS_REG = 0x02; + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT1); + break; + + case 0x5: // Test_Force_Enable + //FUSBPort[0x08] = 0x20; //Start Test_Force_Enable + break; + + default: + return FALSE; + } + break; + #endif + default : + return FALSE; + } + + if (eUsbCxFinishAction == ACT_DONE) + UsbStatus[2] = 1; + + return TRUE; +} + + +/***********************************************************************/ +// bSet_address() +// Description: +// 1. Set addr to FUSB200 register. +// input: none +// output: TRUE or FALSE (BOOLEAN) +/***********************************************************************/ +LOCAL BOOLEAN bSet_address(void) +{ + + //A_PRINTF("bSet_feature...\n\r"); + + if (mDEV_REQ_VALUE() >= 0x0100) + return FALSE; + else + { +// zfUartSendStrAndHex((uint8_t *) "USB_SET_ADDRESS=", mDEV_REQ_VALUE()); + //ZM_DEVICE_ADDRESS_REG = mDEV_REQ_VALUE(); + USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, mDEV_REQ_VALUE()); + + eUsbCxFinishAction = ACT_DONE; + return TRUE; + } +} + +/***********************************************************************/ +// bGet_descriptor() +// Description: +// 1. Point to the start location of the correct descriptor. +// 2. set the transfer length +// input: none +// output: TRUE or FALSE (BOOLEAN) +/***********************************************************************/ +LOCAL BOOLEAN bGet_descriptor(void) +{ + //A_PRINTF("bGet_descriptor...\n\r"); + +// Change Descriptor type +#if 0 + u8ConfigDescriptorEX[mTABLE_IDX(1)] = + m2BYTE(CONFIG_LENGTH, DT_CONFIGURATION); + u8OtherSpeedConfigDescriptorEX[mTABLE_IDX(1)] = + m2BYTE(CONFIG_LENGTH, DT_OTHER_SPEED_CONFIGURATION); +#endif + + //*(volatile uint32_t*)0x1c0004 = 'G'; + + switch (mDEV_REQ_VALUE_HIGH()) + { + case 1: // device descriptor + pu8DescriptorEX = u8UsbDeviceDescriptor; + u16TxRxCounter = mTABLE_LEN(u8UsbDeviceDescriptor[0]); + //u16TxRxCounter = 18; + break; + + case 2: // configuration descriptor + // It includes Configuration, Interface and Endpoint Table +// zfUartSendStr((uint8_t *)"Configuration Descriptor\r\n"); + switch (mDEV_REQ_VALUE_LOW()) + { + case 0x00: // configuration no: 0 + pu8DescriptorEX = u8ConfigDescriptorEX; + u16TxRxCounter = u8ConfigDescriptorEX[1]; + //u16TxRxCounter = 46; + break; + default: + return FALSE; + } + break; + + case 3: // string descriptor + // DescriptorIndex = low_byte of wValue +// zfUartSendStr((uint8_t *)"String Descriptor\r\n"); + switch (mDEV_REQ_VALUE_LOW()) + { + case 0x00: + pu8DescriptorEX = u8String00Descriptor; + //u16TxRxCounter = 4; + break; + + case 0x10: + pu8DescriptorEX = u8String10Descriptor; + //u16TxRxCounter = 12; + break; + + case 0x20: + pu8DescriptorEX = u8String20Descriptor; + //u16TxRxCounter = 24; + break; + + case 0x30: + pu8DescriptorEX = u8String30Descriptor; + break; + + default: + return FALSE; + } + u16TxRxCounter = mTABLE_LEN(pu8DescriptorEX[0]); + break; + + case 6: // Device_Qualifier descritor +// zfUartSendStr((uint8_t *) "Device_Qualifier Descriptor\r\n"); + pu8DescriptorEX = u8DeviceQualifierDescriptorEX; + u16TxRxCounter = mTABLE_LEN(u8DeviceQualifierDescriptorEX[0]); + //u16TxRxCounter = 10; + break; + + case 7: // Other_Speed_Configuration +// zfUartSendStr((uint8_t *)"Other_Speed Descriptor\r\n"); + // It includes Configuration, Interface and Endpoint Table + pu8DescriptorEX = u8OtherSpeedConfigDescriptorEX; + u16TxRxCounter = u8OtherSpeedConfigDescriptorEX[1]; + //u16TxRxCounter = 46; + break; + + default: +// zfUartSendStrAndHex((uint8_t *) "Descriptor error=", mDEV_REQ_VALUE_HIGH()); + return FALSE; + } + + if (u16TxRxCounter > mDEV_REQ_LENGTH()) + u16TxRxCounter = mDEV_REQ_LENGTH(); + +// vUsbEP0TxData(); + A_USB_EP0_TX_DATA(); + + // somehow if there is still data need to send out, we shouldn't set CX_DONE + // wait for another EP0_IN + if( u16TxRxCounter > 0 ) + { + eUsbCxCommand = CMD_GET_DESCRIPTOR; + } + + return TRUE; +} + + +/***********************************************************************/ +// bGet_configuration() +// Description: +// 1. Send 1 bytes configuration value to host. +// input: none +// output: none +/***********************************************************************/ +LOCAL BOOLEAN bGet_configuration(void) +{ + + //A_PRINTF("bGet_configuration...\n\r"); + + //ZM_CBUS_FIFO_SIZE_REG = 0x1; + //ZM_EP0_DATA_REG = u8UsbConfigValue; + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, u8UsbConfigValue); + + // Restore CBus FIFO size to word size + //ZM_CBUS_FIFO_SIZE_REG = 0xf; + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf); + + eUsbCxFinishAction = ACT_DONE; + + return TRUE; +} + +/***********************************************************************/ +// bSet_configuration() +// Description: +// 1. Get 1 bytes configuration value from host. +// 2-1. if (value == 0) then device return to address state +// 2-2. if (value match descriptor table) +// then config success & Clear all EP toggle bit +// 2-3 else stall this command +// input: none +// output: TRUE or FALSE +/***********************************************************************/ +LOCAL BOOLEAN bSet_configuration(void) +{ +void vUsbClrEPx(void); + + //A_PRINTF("bSet_configuration...\n\r"); + + if (mLOW_BYTE(mDEV_REQ_VALUE()) == 0) + { + u8UsbConfigValue = 0; + //mUsbCfgClr(); + //ZM_DEVICE_ADDRESS_REG &= ~BIT7; + USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET)&~BIT7)); + } + else + { + if (mUsbHighSpeedST()) // First judge HS or FS?? + { + if (mLOW_BYTE(mDEV_REQ_VALUE()) > HS_CONFIGURATION_NUMBER) + return FALSE; + + u8UsbConfigValue = mLOW_BYTE(mDEV_REQ_VALUE()); + vUsbFIFO_EPxCfg_HS(); + + // Set into 512 byte mode */ + //ZM_SOC_USB_MODE_CTRL_REG |= BIT2; + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT2)); + // mUsbSOFMaskHS(); + } + else + { + if (mLOW_BYTE(mDEV_REQ_VALUE()) > FS_CONFIGURATION_NUMBER) + return FALSE; + + u8UsbConfigValue = mLOW_BYTE(mDEV_REQ_VALUE()); + vUsbFIFO_EPxCfg_FS(); + + // Set into 64 byte mode */ + //M_SOC_USB_MODE_CTRL_REG &= ~BIT2; + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&~BIT2)); + // mUsbSOFMaskFS(); + } + //mUsbCfgSet(); + //ZM_DEVICE_ADDRESS_REG |= BIT7; + USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, \ + (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET)|BIT7)); + + vUsbClrEPx(); + + mUsbGlobIntEnable(); + mUSB_REG_OUT_INT_ENABLE(); + + } + + eUsbCxFinishAction = ACT_DONE; + return TRUE; +} + + +/***********************************************************************/ +// bGet_interface() +// Description: +// Getting interface +// input: none +// output: TRUE or FALSE +/***********************************************************************/ +LOCAL BOOLEAN bGet_interface(void) +{ + +// A_PRINTF("bGet_interface...\n\r"); + if (mUsbCfgST() == 0) + return FALSE; + + // If there exists many interfaces, Interface0,1,2,...N, + // You must check & select the specific one + switch (u8UsbConfigValue) + { + #if (HS_CONFIGURATION_NUMBER >= 1) + // Configuration 1 + case 1: + if (mDEV_REQ_INDEX() > HS_C1_INTERFACE_NUMBER) + return FALSE; + break; + #endif + #if (HS_CONFIGURATION_NUMBER >= 2) + // Configuration 2 + case 2: + if (mDEV_REQ_INDEX2() > HS_C2_INTERFACE_NUMBER) + return FALSE; + break; + #endif + default: + return FALSE; + } + + //ZM_CBUS_FIFO_SIZE_REG = 0x1; + //ZM_EP0_DATA_REG = u8UsbInterfaceAlternateSetting; + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, u8UsbInterfaceAlternateSetting); + + // Restore CBus FIFO size to word size + //ZM_CBUS_FIFO_SIZE_REG = 0xf; + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f); + + u16TxRxCounter = 1; //sizeof(u8UsbInterfaceAlternateSetting); + eUsbCxFinishAction = ACT_DONE; + return TRUE; +} + +/***********************************************************************/ +// bSet_interface() +// Description: +// 1-1. If (the device stays in Configured state) +// &(command match the alternate setting) +// then change the interface +// 1-2. else stall it +// input: none +// output: TRUE or FALSE +/***********************************************************************/ +LOCAL BOOLEAN bSet_interface(void) +{ +void vUsbClrEPx(void); + + //A_PRINTF("bSet_interface...\n\r"); + + if (mUsbCfgST()) + { + + // If there exists many interfaces, Interface0,1,2,...N, + // You must check & select the specific one + switch (mDEV_REQ_INDEX()) + { + case 0: // Interface0 + + if (mLOW_BYTE(mDEV_REQ_VALUE()) == mLOW_BYTE(u8ConfigDescriptorEX[mTABLE_IDX(12)])) + { + u8UsbInterfaceValue = (uint8_t) mDEV_REQ_INDEX(); + u8UsbInterfaceAlternateSetting = mLOW_BYTE(mDEV_REQ_VALUE()); + if (mUsbHighSpeedST()) // First judge HS or FS?? + { + vUsbFIFO_EPxCfg_HS(); + + // Set into 512 byte mode */ + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT2)); + } + else + { + vUsbFIFO_EPxCfg_FS(); + + // Set into 64 byte mode */ + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&~BIT2)); + } + vUsbClrEPx(); + eUsbCxFinishAction = ACT_DONE; + + mUsbGlobIntEnable(); + mUSB_REG_OUT_INT_ENABLE(); + return TRUE; + } + // case 1: // Interface1 + // case 2: // Interface2 + // default: + // break; + } + } + return FALSE; +} + +/***********************************************************************/ +// vUsbEP0TxData() +// Description: +// 1. Send data(max or short packet) to host. +// input: none +// output: none +/***********************************************************************/ +LOCAL void vUsbEP0TxData(void) +{ + uint8_t u8temp; + uint32_t idx=0; + + //wait a little to make sure ep0 fifo is empty before sending data out + while(1) + { + if(idx++>0xffff) { + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, USB_BYTE_REG_READ(ZM_CX_CONFIG_STATUS_OFFSET)|BIT3); + break; + } + + if(USB_BYTE_REG_READ(ZM_CX_CONFIG_STATUS_OFFSET)&BIT5) + { + break; + } + } + // to keep tracking the txrx fifo + // max 64 bytes for transmission one time, + if (u16TxRxCounter < EP0MAXPACKETSIZE) + u8temp = (uint8_t) u16TxRxCounter; + else + u8temp = EP0MAXPACKETSIZE; + + u16TxRxCounter -= (uint16_t) u8temp; + + { + register uint8_t u8count; + uint8_t remainder; + + for (u8count = 0; u8count < (u8temp/4); u8count ++) + { + uint32_t ep0_data; + uint16_t ep0_low; + uint16_t ep0_high; + + // pack data into word size + ep0_low = *pu8DescriptorEX++; + ep0_high = *pu8DescriptorEX++; + + // composed the data as a word + ep0_data = (ep0_high << 16) + ep0_low; + + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data); + } + + remainder = u8temp % 4; + + // Check whether there are data needed to be filled into the FIFO + if (remainder == 3) + { + uint32_t ep0_data; + uint16_t ep0_low; + uint16_t ep0_high; + + // pack data into word size + ep0_low = *pu8DescriptorEX++; + ep0_high = *pu8DescriptorEX++; + + ep0_data = (ep0_high << 16) + ep0_low; + + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, ep0_data); + } + else if (remainder == 2) + { + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX); + } + else if (remainder == 1) + { + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *pu8DescriptorEX); + } + + // Restore CBus FIFO size to word size + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xf); + } + + // end of the data stage + if (u16TxRxCounter == 0) + { + eUsbCxCommand = CMD_VOID; + eUsbCxFinishAction = ACT_DONE; + } +} + +/***********************************************************************/ +// vUsbEP0RxData() +// Description: +// 1. Receive data(max or short packet) from host. +// input: none +// output: none +/***********************************************************************/ +LOCAL void vUsbEP0RxData(void) +{ + uint8_t u8temp; + + if (u16TxRxCounter < EP0MAXPACKETSIZE) + u8temp = (uint8_t) u16TxRxCounter; + else + u8temp = EP0MAXPACKETSIZE; + + u16TxRxCounter -= (uint16_t) u8temp; + + // Receive u8Temp bytes data + { + register uint8_t u8count; + uint8_t *p = (uint8_t *) pu8DescriptorEX; + + for (u8count = 0; u8count < ((u8temp+3) >> 2); u8count ++) + { + uint32_t ep0_data; + + ep0_data = USB_WORD_REG_READ(ZM_EP0_DATA_OFFSET); //read usb ep0 fifo data, + + { +// skip the writing to ram if not build for rom code +#if 0 //1 defined(_ROM_) + *p++ = mGetByte0(ep0_data); + *p++ = mGetByte1(ep0_data); + *p++ = mGetByte2(ep0_data); + *p++ = mGetByte3(ep0_data); +#endif + fwCheckSum = fwCheckSum ^ ep0_data; + } + } + + pu8DescriptorEX += (u8count << 1); + } + + // end of the data stage + if (u16TxRxCounter == 0) + { + eUsbCxCommand = CMD_VOID; + eUsbCxFinishAction = ACT_DONE; + } +} + + +/***********************************************************************/ +// vUsb_SetupDescriptor() +// Description: +// Setup the pointer to the descriptor in the SRAM and EEPROM +// +/***********************************************************************/ +LOCAL void vUsb_SetupDescriptor(void) +{ +// eeprom exist the usb configuration is only supportted in rom version +#if defined(_ROM_) + // + // check the offset of PID's value is correct or not, need to be defined!!, ryan + // + + if( *((uint32_t*)USB_DESC_IN_EEPROM_FLAG_ADDR) == USB_DESC_IN_EEP_PATTERN) + { + A_PRINTF("- custom usb config\n"); + + u8UsbDeviceDescriptor = (uint16_t *) USB_DEVICE_DESCRIPTOR_ADDR; + u8String00Descriptor = (uint16_t *) USB_STRING00_DESCRIPTOR_ADDR; + u8String10Descriptor = (uint16_t *) USB_STRING10_DESCRIPTOR_ADDR; + u8String20Descriptor = (uint16_t *) USB_STRING20_DESCRIPTOR_ADDR; + u8String30Descriptor = (uint16_t *) USB_STRING30_DESCRIPTOR_ADDR; + } + else +#endif + { + u8UsbDeviceDescriptor = (uint16_t *) &UsbDeviceDescriptor; + u8String00Descriptor = (uint16_t *) &String00Descriptor; + u8String10Descriptor = (uint16_t *) &String10Descriptor; + u8String20Descriptor = (uint16_t *) &String20Descriptor; + u8String30Descriptor = (uint16_t *) &String30Descriptor; + } + + /* Point Device Qualifierdescriptors and Other Speed Descriptor + * - Device Qualifierdescriptor is located in RAM segment, extern these + * symbol at the beginning of this file + */ +} + + +/***********************************************************************/ +// bStandardCommand() +// Description: +// 1. Process standard command. +// input: none +// output: TRUE or FALSE +/***********************************************************************/ +LOCAL BOOLEAN bStandardCommand(void) +{ + switch (mDEV_REQ_REQ()) // by Standard Request codes + { + case USB_GET_STATUS: + return (A_USB_GET_STATUS()); + + case USB_CLEAR_FEATURE: + return (A_USB_CLEAR_FEATURE()); + + case USB_SET_FEATURE: + return (A_USB_SET_FEATURE()); + + case USB_SET_ADDRESS: + return (A_USB_SET_ADDRESS()); + + case USB_GET_DESCRIPTOR: + return (A_USB_GET_DESCRIPTOR()); + +#if 0 + case USB_SET_DESCRIPTOR: +// if (!bUsbEP0HaltSt) + return (bSet_descriptor()); +#endif + + case USB_GET_CONFIGURATION: + return (A_USB_GET_CONFIG()); + + case USB_SET_CONFIGURATION: + //A_PRINTF(" \n--> SET_CONFIGURATION\r\n"); +// if (!bUsbEP0HaltSt) +// return (A_USB_SET_CONFIG()); + + { + A_USB_SET_CONFIG(); + +#if ENABLE_SWAP_DATA_MODE + // SWAP FUNCTION should be enabled while DMA engine is not working, + // the best place to enable it is before we trigger the DMA + MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; + + #if SYSTEM_MODULE_HP_EP5 + MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; + #endif + + #if SYSTEM_MODULE_HP_EP6 + MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; + #endif + +#endif //ENABLE_SWAP_DATA_MODE + + +#if !ENABLE_STREAM_MODE + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3); + + /* + // ryan: + // 04/01: bit0 could disable lpdn dma, which is good at debugging while async_fifo have problem, + // we could disable this and check the fifo_rcv_size to see if we have correct at fifo or not + */ + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1))); // upstream DMA enable + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0))); // downstream DMA enable + + #if SYSTEM_MODULE_HP_EP5 + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8))); + #endif + + #if SYSTEM_MODULE_HP_EP6 + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9))); + #endif + +#else +/////////////ENABLE_STREAM_MODE///////////////// + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))); // disable upstream DMA mode + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))); // enable upstream stream mode + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT1))); // enable upstream DMA mode + + #if SYSTEM_MODULE_HP_EP1 + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))); // diable LP downstream DMA mode + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT6))); // enable LP downstream stream mode + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT0))); // enable LP downstream DMA mode + #endif + + #if SYSTEM_MODULE_HP_EP5 + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))); // disable HP downstream DMA mode + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT7))); // enable HP downstream stream mode + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)); // enable HP downstream DMA mode + #endif + + + #if SYSTEM_MODULE_HP_EP6 + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))); // disable MP downstream DMA mode + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10)); // enable MP downstream stream mode + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)); // enable MP downstream DMA mode + #endif + + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT4))); // define the host dma buffer size - 4096(00) 8192 (01) 16384(10) 32768(11) bytes + + USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, USB_STREAM_MODE_TIMEOUT_CTRL); // set stream mode timeout critirea + + USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, USB_STREAM_MODE_AGG_CNT); // set stream mode packet buffer critirea +#endif //!ENABLE_STREAM_MODE + + + +//extern void Magpie_init(void); +//Magpie_init(); + + return TRUE; + } + + case USB_GET_INTERFACE: +// A_PRINTF(" \n--> GET_INTERFACE\r\n"); +// if (!bUsbEP0HaltSt) + //return (bGet_interface()); + return (A_USB_GET_INTERFACE()); + + case USB_SET_INTERFACE: +// A_PRINTF(" \n--> SET_INTERFACE\r\n"); +// if (!bUsbEP0HaltSt) +// return (bSet_interface()); +// return (A_USB_SET_INTERFACE()); + A_USB_SET_INTERFACE(); + return TRUE; + } + return FALSE; +} + + +LOCAL void flash_read(uint16_t len, uint16_t ofset) +{ + uint16_t i=0; + + uint8_t buf[64]; + uint16_t end_addr = 0x0; + uint16_t start_addr = 0x0; + uint32_t ep0_data = 0x0; + +#if 0 + //sanity check, just in case + if(u16TxRxCounter < EP0MAXPACKETSIZE) + u8temp = (uint8_t) u16TxRxCounter; + else + + if( u16TxRxCounter > 64 ) + len = EP0MAXPACKETSIZE; + else + len = u16TxRxCounter + 4-(u16TxRxCounter%4); +#endif + + start_addr = ofset; + end_addr = start_addr + len; + + A_PRINTF("read flash from %x to %x\n", ofset, end_addr); + + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF); + + for (i = 0; start_addr < end_addr; i++, start_addr+=4) + { +// A_SFLASH_READ(1, ofset, 4, buf + i*4); +// *((volatile uint32_t *)(buf+i*4)) = *(uint32_t *)(0xf000000+start_addr); +// A_PRINTF(" %08x ", *(uint32_t *)(0xf000000+start_addr)); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, *(uint32_t *)(0xf000000+start_addr)); + } + +// A_PRINTF("\n\n\r"); + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0); + + + + +#if 0 + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF); + + for(i=0; i[cUSB_REQ_COMP]: 0x%08x\n\r", text_addr); +#if 0 + if (fwCheckSum != 0) + { + A_PRINTF("cksum=%x", fwCheckSum); + fwCheckSum = 0; + //Return fail + DEBUG_SYSTEM_STATE |= BIT27; + + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, 1); + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF); + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0); + } + else +#endif + { + /* Set EP0 Done */ + //ZM_CX_CONFIG_STATUS_REG = 0x01; + fwCheckSum = 0; + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1); + USB_WORD_REG_WRITE(ZM_EP0_DATA_OFFSET, 0); + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF); + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, BIT0); + + A_PRINTF("VendorCmd: DownloadComplete!\n"); + + DEBUG_SYSTEM_STATE &= ~BIT27; + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x3f; + + // this value should be assign from host along with the DOWNLOAD_COMP in wValue + if( text_addr != 0 ) + funcPtr = (void *)(text_addr); + + download_enable = TRUE; + + // only jump to text address in ROM version + #if defined(_ROM_) + // funcPtr(); // jump to the firmware and never return + #endif + //app_start(); + } +// else +// A_PRINTF("Integrity is not fine!\n\r"); + + break; + } +} + + +/***********************************************************************/ +// vUsb_ep0setup() +// Description: +// 1. Read 8-byte setup packet. +// 2. Decode command as Standard, Class, Vendor or NOT support command +// input: none +// output: none +/***********************************************************************/ +extern uint16_t u8HSConfigDescriptor01[]; +extern uint16_t u8FSConfigDescriptor01[]; + +LOCAL void vUsb_ep0setup(void) +{ +register uint8_t ii; +volatile uint32_t ep0_data; +//BOOLEAN bStandardCommand(void); +//BOOLEAN bClassCommand(void); +//void VendorCommand(void); + + //zcPrint._printf("\t---> %s <---\n\r", __FUNCTION__); + if (UsbChirpFinish != TRUE) + { + UsbChirpFinish = TRUE; + + // Setup Descriptor pointer + //vUsb_SetupDescriptor(); + A_USB_SETUP_DESC(); + + u8OtherSpeedConfigDescriptorEX[0] = 0x0709; + + if (mUsbHighSpeedST()) // Judge HS or FS?? + { + u8ConfigDescriptorEX = u8HSConfigDescriptor01; + + // copy Device Qualifierdescriptors (from rom to sram) + for (ii = 1; ii < 4; ii++) + { + u8DeviceQualifierDescriptorEX[ii] = u8UsbDeviceDescriptor[ii]; + } + + // Number of Other-speed Configurations + // byte 9 Reserved for future use, must be zero + u8DeviceQualifierDescriptorEX[4] = (u8UsbDeviceDescriptor[8] >> 8) & 0x00ff; + + // copy Other Speed Descriptor + for (ii = 1; ii < (USB_TOTAL_DESC_LEN/2); ii++) + { + u8OtherSpeedConfigDescriptorEX[ii] = u8FSConfigDescriptor01[ii]; + } + +#if 0 + MaxPktSize = HS_C1_I0_A0_EP1_MAX_PACKET; + // Device stays in High Speed + u8DeviceDescriptorEX = u8HSDeviceDescriptor; + + // copy Device Qualifierdescriptors (from rom to sram) + for (ii = mTABLE_WID(2) ; ii < mTABLE_WID(8); ii ++) + u8DeviceQualifierDescriptorEX[ii] = u8FSDeviceDescriptor[ii]; + + // Number of Other-speed Configurations + // byte 9 Reserved for future use, must be zero + u8DeviceQualifierDescriptorEX[mTABLE_IDX(8)] + = mHIGH_BYTE(u8FSDeviceDescriptor[mTABLE_IDX(17)]); + u8ConfigDescriptorEX = u8HSConfigDescriptor01; + u8OtherSpeedConfigDescriptorEX = u8FSConfigDescriptor01; +#endif + } + else + { + u8ConfigDescriptorEX = u8FSConfigDescriptor01; + + // copy Device Qualifierdescriptors (from rom to sram) + for (ii = 1; ii < 4; ii++) + { + u8DeviceQualifierDescriptorEX[ii] = u8UsbDeviceDescriptor[ii]; + } + + // Number of Other-speed Configurations + // byte 9 Reserved for future use, must be zero + u8DeviceQualifierDescriptorEX[4] = (u8UsbDeviceDescriptor[8] >> 8) & 0x00ff; + + // copy Other Speed Descriptor + for (ii = 1; ii < (USB_TOTAL_DESC_LEN/2); ii++) + { + u8OtherSpeedConfigDescriptorEX[ii] = u8HSConfigDescriptor01[ii]; + } + +#if 0 + MaxPktSize = FS_C1_I0_A0_EP1_MAX_PACKET; + // Device stays in Full Speed + u8DeviceDescriptorEX = u8FSDeviceDescriptor; + + // copy Device Qualifierdescriptors (from rom to sram) + for (ii = mTABLE_WID(2) ; ii < mTABLE_WID(8); ii ++) + u8DeviceQualifierDescriptorEX[ii] = u8HSDeviceDescriptor[ii]; + + // Number of Other-speed Configurations + // byte 9 Reserved for future use, must be zero + u8DeviceQualifierDescriptorEX[mTABLE_IDX(8)] + = mHIGH_BYTE(u8HSDeviceDescriptor[mTABLE_IDX(17)]); + u8ConfigDescriptorEX = u8FSConfigDescriptor01; + u8OtherSpeedConfigDescriptorEX = u8HSConfigDescriptor01; +#endif + } + //Change bLength + u8DeviceQualifierDescriptorEX[0] = 0x060A; + } + + if( USB_BYTE_REG_READ(ZM_CX_CONFIG_STATUS_OFFSET) & BIT5) + { + int kkk=0; + kkk++; + } + //ep0_data = ZM_EP0_DATA_REG; + ep0_data = USB_WORD_REG_READ(ZM_EP0_DATA_OFFSET); + + ii = mGetByte0(ep0_data); + + ControlCmd.Direction = (uint8_t)(ii & 0x80);// xfer Direction(IN, OUT) + ControlCmd.Type = (uint8_t)(ii & 0x60); // type(Standard, Class, Vendor) + ControlCmd.Object = (uint8_t)(ii & 0x03); // Device, Interface, Endpoint + + ControlCmd.Request = mGetByte1(ep0_data); + ControlCmd.Value = mGetByte2(ep0_data) + (mGetByte3(ep0_data) << 8); + + //ep0_data = ZM_EP0_DATA_REG; + ep0_data = USB_WORD_REG_READ(ZM_EP0_DATA_OFFSET); + + ControlCmd.Index = mGetByte0(ep0_data) + (mGetByte1(ep0_data) << 8); + ControlCmd.Length = mGetByte2(ep0_data) + (mGetByte3(ep0_data) << 8); + +// Command Decode + if (mDEV_REQ_REQ_TYPE() == (cUSB_REQTYPE_STD << bmREQ_TYPE)) + { // standard command + //if (bStandardCommand() == FALSE) + if (A_USB_STANDARD_CMD() == FALSE) + { + eUsbCxFinishAction = ACT_STALL; + } + } + else if (mDEV_REQ_REQ_TYPE() == (cUSB_REQTYPE_VENDOR << bmREQ_TYPE)) + { // vendor command + //VendorCommand(); + A_USB_VENDOR_CMD(); + } + else + { + // Invalid(bad) command, Return EP0_STALL flag + A_PRINTF("request not support.. stall", __FUNCTION__); + eUsbCxFinishAction = ACT_STALL; + } + + //zcPrint._printf("\t<--- %s --->\n\r", __FUNCTION__); +} + + +/*! - init FUSB phy + * + */ +LOCAL void cFUSB200Init(void) +{ + /* Clear USB reset interrupt */ + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&0xfd)); + + // Disable all fifo interrupt + /* Clear all USB OUT FIFO */ + USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_1_OFFSET, 0xff); + USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_2_OFFSET, 0xff); + USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_3_OFFSET, 0xff); + + /* Clear all USB IN FIFO */ + USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_5_OFFSET, 0xff); + USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, 0xff); + + // Soft Reset + //ZM_MAIN_CTRL_REG = 0x10; + //ZM_MAIN_CTRL_REG &= ~0x10; + + // Soft Reset + USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, 0x10); + USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, 0x0); + + // Clear all fifo + USB_BYTE_REG_WRITE(ZM_TEST_OFFSET, BIT0); // will be cleared after one cycle. + USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_0_OFFSET, 0); //BIT6); // Mask out INT status + + // reset the specific mode + USB_BYTE_REG_WRITE(ZM_VDR_SPECIFIC_MODE_OFFSET, 0x0); + + // reset the zero-length fifo indication ? workaround... + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, 0x0); + + // Enable Chip + USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, (BIT5|BIT2)); + + USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_1_OFFSET, 0x0); + USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_2_OFFSET, 0x0); + USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_3_OFFSET, 0x0); + +// USB_WORD_REG_WRITE(0x104, 0x000000C0); + +} + + +LOCAL void _usbfifo_enable_event_isr(void) +{ + mUSB_STATUS_IN_INT_ENABLE(); +} + +LOCAL void _usbfifo_init(USB_FIFO_CONFIG *pConfig) +{ + usbFifoConf.get_command_buf = pConfig->get_command_buf; + usbFifoConf.recv_command = pConfig->recv_command; + usbFifoConf.get_event_buf = pConfig->get_event_buf; + usbFifoConf.send_event_done = pConfig->send_event_done; +} + +LOCAL void vUsb_Reg_Out(void) +{ + uint16_t usbfifolen; + uint16_t ii; + volatile uint32_t *regaddr; // = (volatile uint32_t *) ZM_CMD_BUFFER; + uint16_t cmdLen; + uint32_t ep4_data; + VBUF *buf; + + //mUSB_REG_OUT_INT_DISABLE(); + + buf = usbFifoConf.get_command_buf(); + + if ( buf != NULL ) // copy free + regaddr = (uint32_t *)buf->desc_list->buf_addr; + else + goto ERR; + + // read fifo size of the current packet. + usbfifolen = USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_LOW_OFFSET); + + cmdLen = usbfifolen; + + if(usbfifolen % 4) + usbfifolen = (usbfifolen >> 2) + 1; + else + usbfifolen = usbfifolen >> 2; + + for(ii = 0; ii < usbfifolen; ii++) + { + ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out + *regaddr = ep4_data; + regaddr++; + } + + if ( buf != NULL ) + { +// zfUartSendStrAndHex((u8_t *) "cmdLen=", cmdLen); +// zfMemoryCopyInWord(buf->desc_list->buf_addr, ZM_CMD_BUFFER, usbfifolen*4); + buf->desc_list->next_desc = NULL; + buf->desc_list->data_offset = 0; + buf->desc_list->data_size = cmdLen; + buf->desc_list->control = 0; + buf->next_buf = NULL; + buf->buf_length = cmdLen; + + usbFifoConf.recv_command(buf); + } + goto DONE; +ERR: +// we might get no command buffer here? +// but if we return here, the ep4 fifo will be lock out, +// so that we still read them out but just drop it ? + for(ii = 0; ii < usbfifolen; ii++) + { + ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out + } + +DONE: + //mUSB_STATUS_IN_INT_ENABLE(); + +} + +LOCAL void vUsb_Status_In(void) +{ + uint16_t count; + uint16_t remainder; + volatile u32_t *regaddr; + u16_t RegBufLen; + VBUF *evntbuf = NULL; + + //regaddr = (volatile uint32_t *) ZM_CMD_BUFFER; + + //mUSB_STATUS_IN_INT_DISABLE(); + + evntbuf = usbFifoConf.get_event_buf(); + if ( evntbuf != NULL ) + { +//zfUartSendStr((u8_t *) "#G1\r\n"); +// A_PRINTF("#G1\n\r"); + regaddr = VBUF_GET_DATA_ADDR(evntbuf); + RegBufLen = evntbuf->buf_length; +// A_PRINTF("RegBufLen=%d\n\r", RegBufLen); +//zfUartSendStrAndHex((u8_t *) "RegBufLen=", RegBufLen); + } + else + { + mUSB_STATUS_IN_INT_DISABLE(); +// A_PRINTF("#G2\n\r"); + goto ERR_DONE; + } + + /* INT use EP3 */ + for(count = 0; count < (RegBufLen / 4); count++) + { +//zfUartSendStrAndHex((u8_t *) "data=", *regaddr); + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr); + regaddr++; + } + + remainder = RegBufLen % 4; + + if (remainder) + { + switch(remainder) + { + case 3: + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7); + break; + case 2: + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3); + break; + case 1: + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1); + break; + } + + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr); + } + + // Restore CBus FIFO size to word size + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF); + + mUSB_EP3_XFER_DONE(); + + if ( evntbuf != NULL ) + { + usbFifoConf.send_event_done(evntbuf); + } + +ERR_DONE: + //mUSB_REG_OUT_INT_ENABLE(); +} + +///////////////////////////////////////////////////////// +/***********************************************************************/ +// zfResetUSBFIFO() +// Description: +// 1. Reset all the USB FIFO used for WLAN +// input: none +// output: none +/***********************************************************************/ +LOCAL void zfResetUSBFIFO(void) +{ + A_PUTS("zfResetUSBFIFO\n\r"); + +} + +/***********************************************************************/ +// zfTurnOffPower() +// Description: +// 1. Function to turn off ADDA/RF power, PLL +// input: none +// output: none +/***********************************************************************/ +LOCAL void zfTurnOffPower(void) +{ + A_PUTS("zfTurnOffPower\n\r"); +#if defined(MAGPIE_ASIC) +/* + * 1. set CPU bypass + * 2. turn off CPU PLL + * 3. turn off ETH PLL + * 4. disable ETH PLL bypass and update + * 5. set SUSPEND_ENABLE + */ + + /*HAL_WORD_REG_WRITE(MAGPIE_REG_USB_DIVIDE_ADDR,((0x8<<8)|0x8)); */ + /* 1. */ HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_CPU_PLL_BYPASS_ADDR)|(BIT0|BIT4))); + A_DELAY_USECS(100); // wait for stable + + /* 2. */ HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_CPU_PLL_ADDR)|(BIT16))); + + /* 3. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)|(BIT16))); + + /* 4. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)|(BIT16|BIT0))); + + /* 5. */ HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(BIT0))); +#endif + +} + + +LOCAL void zfGenWatchDogEvent(void) +{ + uint32_t event= 0x0000C600; + + mUSB_STATUS_IN_INT_DISABLE(); + + //ZM_CBUS_FIFO_SIZE_REG = 0xf; + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f); + + //ZM_EP3_DATA_REG = event; + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, event); + + mUSB_EP3_XFER_DONE(); +} + +LOCAL void zfJumpToBootCode(void) +{ + extern int _start(void); + + /* Jump to the boot code */ + _start(); +} + +LOCAL void _usb_rom_task(void) +{ + register uint8_t usb_interrupt_level1; + register uint8_t usb_interrupt_level2; + register uint8_t usb_ctrl_err_indication; + + usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET); + + if (usb_interrupt_level1 & BIT6) + { + A_USB_GEN_WDT(); + A_PRINTF("Generate Event\n"); + } + + if (usb_interrupt_level1 & BIT0) //Group Byte 0 + { + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET); + + // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!? + if (usb_interrupt_level2 & BIT7) + { + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7)); + } + + if (usb_interrupt_level2 & BIT1) + { + A_PRINTF("![USB] ep0 IN in \n\r"); + A_USB_EP0_TX(); // USB EP0 tx interrupt + } + if (usb_interrupt_level2 & BIT2) + { + //A_PRINTF("![USB] ep0 OUT in\n\r"); + A_USB_EP0_RX(); // USB EP0 rx interrupt + } + if (usb_interrupt_level2 & BIT0) + { + //A_PRINTF("![USB] ep0 SETUP in\n\r"); + A_USB_EP0_SETUP(); + } + + if (eUsbCxFinishAction == ACT_STALL) + { + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04); +// A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r"); + } + else if (eUsbCxFinishAction == ACT_DONE) + { + // set CX_DONE to indicate the transmistion of control frame + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); + } + eUsbCxFinishAction = ACT_IDLE; + } + + if (usb_interrupt_level1 & BIT7) //Group Byte 7 + { + //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG; + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET); + + if (usb_interrupt_level2 & BIT1) + { + vUsb_rst(); + } + if (usb_interrupt_level2 & BIT2) + { + vUsb_suspend(); + } + if (usb_interrupt_level2 & BIT3) + { + vUsb_resm(); + } + } + +} + + +LOCAL void _usb_fw_task(void) +{ + register uint8_t usb_interrupt_level1; + register uint8_t usb_interrupt_level2; + register uint8_t usb_ctrl_err_indication; + + usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET); + +#if 0 // these endpoints are handled by DMA + if (usb_interrupt_level1 & BIT5) //Group Byte 5 + { + vUsb_Data_In(); + } +#endif + if (usb_interrupt_level1 & BIT4) + { + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_4_OFFSET); + if( usb_interrupt_level2 & BIT6) + A_USB_REG_OUT();//vUsb_Reg_Out(); + } + + if (usb_interrupt_level1 & BIT6) + { + //zfGenWatchDogEvent(); + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_6_OFFSET); + if( usb_interrupt_level2 & BIT6) + A_USB_STATUS_IN();//vUsb_Status_In(); + } + + if (usb_interrupt_level1 & BIT0) //Group Byte 0 + { + //usb_interrupt_level2 = ZM_INTR_SOURCE_0_REG; + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET); + + // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!? + if (usb_interrupt_level2 & BIT7) + { + //ZM_INTR_SOURCE_0_REG &= 0x7f; // Handle command abort + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7)); + A_PRINTF("![SOURCE_0] bit7 on\n\r"); + } + + if (usb_interrupt_level2 & BIT1) + { + //A_PRINTF("![USB] ep0 IN in \n\r"); + A_USB_EP0_TX(); // USB EP0 tx interrupt + } + if (usb_interrupt_level2 & BIT2) + { + //A_PRINTF("![USB] ep0 OUT in\n\r"); + A_USB_EP0_RX(); // USB EP0 rx interrupt + } + if (usb_interrupt_level2 & BIT0) + { + //A_PRINTF("![USB] ep0 SETUP in\n\r"); + A_USB_EP0_SETUP(); + //vWriteUSBFakeData(); + } +// else if (usb_interrupt_level2 & BIT3) + if (usb_interrupt_level2 & BIT3) + { + vUsb_ep0end(); +// A_PRINTF("![SOURCE_0] ep0 CMD_END\n\r"); + } + if (usb_interrupt_level2 & BIT4) + { + vUsb_ep0fail(); +// A_PRINTF("![SOURCE_0] ep0 CMD_FAIL\n\r"); + } + if (eUsbCxFinishAction == ACT_STALL) + { + // set CX_STL to stall Endpoint0 & will also clear FIFO0 + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04); +// A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r"); + } + else if (eUsbCxFinishAction == ACT_DONE) + { + // set CX_DONE to indicate the transmistion of control frame + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); + } + eUsbCxFinishAction = ACT_IDLE; + } + + if (usb_interrupt_level1 & BIT7) //Group Byte 7 + { + //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG; + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET); + +#if 0 + if (usb_interrupt_level2 & BIT7) + { + vUsb_Data_Out0Byte(); +// A_PRINTF("![SOURCE_7] bit7 on, clear it\n\r"); + } + if (usb_interrupt_level2 & BIT6) + { + vUsb_Data_In0Byte(); +// A_PRINTF("![SOURCE_7] bit6 on, clear it\n\r"); + } +#endif + + if (usb_interrupt_level2 & BIT1) + { + vUsb_rst(); + //USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~0x2)); + A_PRINTF("!USB reset\n\r"); +// A_PRINTF("![0x1012c]: %\n\r", USB_WORD_REG_READ(0x12c)); + } + if (usb_interrupt_level2 & BIT2) + { + // TBD: the suspend resume code should put here, Ryan, 07/18 + // + // issue, jump back to rom code and what peripherals should we reset here? + // + + /* Set GO_TO_SUSPEND bit to USB main control register */ + vUsb_suspend(); + A_PRINTF("!USB suspend\n\r"); + + // keep the record of suspend +#if defined(PROJECT_MAGPIE) + *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = SUS_MAGIC_PATTERN; +#elif defined(PROJECT_K2) + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN); +#endif /* #if defined(PROJECT_MAGPIE) */ + + /* Reset USB FIFO */ + A_USB_RESET_FIFO(); + + /* Turn off power */ + A_USB_POWER_OFF(); + +// DON'T restart when not in ASIC +#if defined(MAGPIE_ASIC) + /* Jump to boot code */ + A_USB_JUMP_BOOT(); +#endif + + } + if (usb_interrupt_level2 & BIT3) + { + vUsb_resm(); + A_PRINTF("!USB resume\n\r"); + } + } + +} + +#if 0 // old + +void _usb_init(void) +{ + +// init variables +// u16TxRxCounter = 0; +// eUsbCxCommand = CMD_VOID; +// u8UsbConfigValue = 0; + u8UsbInterfaceValue = 0; + u8UsbInterfaceAlternateSetting = 0; +// bUsbEP0HaltSt = FALSE; +// u16FirmwareComplete = 0; +// eUsbCxFinishAction = ACT_IDLE; + UsbStatus[0] = !fBUS_POWER; + +// init hardware + +// cFUSB200Init(); + A_USB_INIT_PHY(); + + //ZM_PHY_TEST_SELECT_REG = 0; // Plug In + USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, 0x0); + + // reset the address, just in case... + //USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, 0x0); + +} + +#else // new + +#if defined(PROJECT_MAGPIE) + +/* - spec, ch11, reset + * + * 1. turn on ETH PLL and set ETH PLL to 384Mhz + * 2. set "USB_DMA, USB_CORE, ETH_PLL, CPU_PLL, USB_POR reset" bit + * 3. clear "ETH_PLL, CPU_PLL" reset bit + * 4. set USB divider to 48, 192/16=12 + * 5. disable ETH PLL bypass + * 6. clear USB_POR + * 7. clear USB_DMA, USB_CORE + * 8. enable USB_AHB_ARB + * + * note: don't know why bit3, bit4 should deassert? here especially bit4? + * since if we don't deassert this, clk won't come up + * + */ +#if defined(MAGPIE_ASIC) +#define RST_USB_COLD_INIT() \ +{ \ + /********* number of PLLDIV_LOW and PLLDIV_HIGH ***********/ \ + /*HAL_WORD_REG_WRITE(MAGPIE_REG_USB_DIVIDE_ADDR,((0x8<<8)|0x8)); */ \ + /* 1. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR, 0x305); \ + /* 2. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|(BIT0|BIT1|BIT2|BIT3|BIT4))); \ + /* 3. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT1|BIT2)))); \ + /* 4. */ HAL_WORD_REG_WRITE(MAGPIE_REG_USB_DIVIDE_ADDR, 0x1010); \ + /* 5. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, 0x0); \ + A_DELAY_USECS(100); /* wait for clock source stable */ \ + /* 6. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT0)))); \ + /* 7. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT3|BIT4)))); \ + /* 8. */ HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT2)); \ + /* HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, ); */ \ + /* HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|((BIT0|BIT3|BIT4)))); */ \ + /* HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT0|BIT3|BIT4)))); */ \ +} + +/* - back from suspend + * + * 1. turn on ETH PLL , 0x5600c, ~bit0 + * 2. clear USB SUSPEND_ENABLE, 0x56030, ~bit0 + * + */ +#define RST_USB_SUSP_INIT() \ +{ \ + /* 1. */ HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)&(~BIT0))); \ + /* 2. */ HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)&(~BIT0))); \ +} + +/* - back from watchdog + * + */ +#define RST_USB_WDT_INIT() + + +#elif defined(MAGPIE_FPGA) +// fpag don't have PLL, skip 1~5 +#define RST_USB_COLD_INIT() \ +{ \ + /* 6. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT0)))); \ + /* 7. */ HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT3|BIT4)))); \ + /* 8. */ HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|BIT2)); \ + A_DELAY_USECS(100); /* wait for clock source stable */ \ +} + +/* - back from suspend + * + */ +#define RST_USB_SUSP_INIT() + +/* - back from watchdog + * + */ +#define RST_USB_WDT_INIT() + + +#endif + + +#elif defined(PROJECT_K2) +#define RST_USB_INIT() \ +{ \ + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT12); \ + A_DELAY_USECS(10); \ + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)&(~BIT12)); \ +} +#endif +/* + @ToDo: this is used to enable usb access internal memory, dma need this + HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)&(~(BIT2)))); \ + A_DELAY_USECS(20); \ + HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|(BIT2))); \ + A_DELAY_USECS(20); \ +*/ + + +LOCAL void _usb_clk_init(void) +{ + T_BOOT_TYPE mBootMode; + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x31; + + mBootMode = A_WDT_LASTBOOT(); + +#if defined(PROJECT_MAGPIE) + + if( mBootMode == ENUM_WDT_BOOT ) + { + RST_USB_WDT_INIT(); + } + else if ( mBootMode == ENUM_SUSP_BOOT ) + { + RST_USB_SUSP_INIT(); + } + else + { + RST_USB_COLD_INIT(); + } + +#elif defined(PROJECT_K2) + if( mBootMode == ENUM_COLD_BOOT ) + { + RST_USB_INIT(); + } +#endif + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x32; + + //A_DELAY_USECS(300); // delay 300 micro seconds, wait for clock stable! +} + + +void _usb_init(void) +{ + u32_t cold_start; + +// A_PUTS("\n - _usb_init - \n\r"); + +#if defined(PROJECT_MAGPIE) + //if ( *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) == WDT_MAGIC_PATTERN || *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) == SUS_MAGIC_PATTERN ) + if( A_WDT_LASTBOOT()!= ENUM_COLD_BOOT) +#elif defined(PROJECT_K2) + if (HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR) == WDT_MAGIC_PATTERN || HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR) == SUS_MAGIC_PATTERN) +#endif /* #if defined(PROJECT_MAGPIE) */ + cold_start = 0; + else + cold_start = 1; + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x30; +// init variables +// u16TxRxCounter = 0; +// eUsbCxCommand = CMD_VOID; +// u8UsbConfigValue = 0; + u8UsbInterfaceValue = 0; + u8UsbInterfaceAlternateSetting = 0; +// bUsbEP0HaltSt = FALSE; +// u16FirmwareComplete = 0; +// eUsbCxFinishAction = ACT_IDLE; + UsbStatus[0] = !fBUS_POWER; + + +/*! + * move the setting to A_USB_CLK_INIT(), so that we could patch these things + */ +#if 1 + A_USB_CLK_INIT(); + +#else + +#if defined(PROJECT_MAGPIE) + +//#if defined(MAGPIE_ASIC) + // + // @Bug 36267 - wdt reset or other reset will reset usb phy, we need to init again here + // - this won't work at FPGA, skip this checking if build for FPGA + // + // @Bug 36947 - L3 fpga's reset behavior of usb is not as what I expect!, need to confirm + // + // ToBeNote: if (Bug36947), skip the checking and reset usb anyway, but will see the connection broken +// if (cold_start) +//#endif + A_USB_CLK_INIT(); +#elif defined(PROJECT_K2) + if (cold_start) + { + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x31; + RST_USB_INIT(); + } +#endif /* #if defined(PROJECT_MAGPIE) */ + +#endif + + A_DELAY_USECS(300); // delay 300 usecs, wait for clock stable! + + while( 1 ) + { + /* + * wait for USBSOC_HCLK_RDY tight high, indicate the 30Mhz is ready for use + */ + if(HAL_WORD_REG_READ(0x10128)& BIT8) + break; + + //A_DELAY_USECS(200); // delay 200 micro seconds, wait for clock stable! + } + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x33; + A_PUTS("6. usb_hclk rdy\n\r"); + + // + // @Bug 36267 - wdt reset or other reset will reset usb phy, we need to init again here + // + // @Bug 36947 - L3 fpga's reset behavior of usb is not as what I expect!, need to confirm +#if defined(PROJECT_MAGPIE) + + // in cold or suspend boot, we do reinit the USB_PHY, skip only when watchdog start + // + // +#if defined(MAGPIE_ASIC) + if (cold_start) +#endif +#elif defined(PROJECT_K2) + if (cold_start) +#endif /* #if defined(PROJECT_MAGPIE) */ + { + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x34; + A_USB_INIT_PHY(); + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xff)) | 0x35; + //ZM_PHY_TEST_SELECT_REG = 0; // Plug In + USB_BYTE_REG_WRITE(ZM_PHY_TEST_SELECT_OFFSET, 0x0); + + // reset the address, just in case... + //USB_BYTE_REG_WRITE(ZM_DEVICE_ADDRESS_OFFSET, 0x0); + } + + /* If watchdog reset happens, target needs to send a message to host through EP3 */ + if ( A_WDT_LASTBOOT() == ENUM_WDT_BOOT ) + mUSB_STATUS_IN_INT_ENABLE(); + else + mUSB_STATUS_IN_INT_DISABLE(); + +} + +#endif + +//////////////////////////////////////////////////////// +void usbfifo_module_install(struct usbfifo_api *apis) +{ + /* hook in APIs */ + apis->_init = _usbfifo_init; + apis->_enable_event_isr = _usbfifo_enable_event_isr; +} + + +void cmnos_usb_module_install(struct usb_api *apis) +{ + apis->_usb_init = _usb_init; + apis->_usb_rom_task = _usb_rom_task; + apis->_usb_fw_task = _usb_fw_task; + apis->_usb_init_phy = cFUSB200Init; + + apis->_usb_ep0_setup = vUsb_ep0setup; + apis->_usb_ep0_tx_data = vUsbEP0TxData; + apis->_usb_ep0_rx_data = vUsbEP0RxData; + + apis->_usb_get_configuration = bGet_configuration; + apis->_usb_set_configuration = bSet_configuration; + + apis->_usb_get_interface = bGet_interface; + apis->_usb_set_interface = bSet_interface; + + apis->_usb_standard_cmd = bStandardCommand; + apis->_usb_vendor_cmd = VendorCommand; + + apis->_usb_reset_fifo= zfResetUSBFIFO; + apis->_usb_power_off = zfTurnOffPower; + apis->_usb_gen_wdt = zfGenWatchDogEvent; + apis->_usb_jump_boot = zfJumpToBootCode; + + apis->_usb_get_descriptor = bGet_descriptor; + apis->_usb_set_address = bSet_address; + apis->_usb_set_feature = bSet_feature; + apis->_usb_clr_feature = bClear_feature; + + apis->_usb_get_status = bGet_status; + apis->_usb_setup_desc = vUsb_SetupDescriptor; + + apis->_usb_reg_out = vUsb_Reg_Out; + apis->_usb_status_in = vUsb_Status_In; + + apis->_usb_ep0_tx = vUsb_ep0tx; + apis->_usb_ep0_rx = vUsb_ep0rx; + + apis->_usb_clk_init = _usb_clk_init; +} + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_defs.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_defs.h new file mode 100755 index 0000000..bef0190 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_defs.h @@ -0,0 +1,904 @@ +#ifndef USB_DEFS_H +#define USB_DEFS_H + +#include "usb_table.h" +#include "dt_defs.h" +#include "reg_defs.h" + +#define CHECK_SWITCH_BY_BOOTCODE 1 //to be verified for ZD1215, OK for ZD1211 +#define VERIFY_CHECKSUM_BY_BOOTCODE 1 + +/***********************************************************************/ +/* for SEEPROM Boot */ +/***********************************************************************/ +#define WLAN_BOOT_SIGNATURE (0x19710303) + +#define WLAN_SIGNATURE_ADDR (0x102000) + +#define cMAX_ADDR 0x10000 + +#define cEEPROM_SIZE 0x800 // 2k word (4k byte) + +#define cRESERVE_LOAD_SPACE 0 + +// start addr. of boot code +#define cBOOT_CODE_ADDR (cMAX_ADDR - cEEPROM_SIZE) // 0xF800 + +/************************** Register Addr Process *********************/ +#define mpADDR(addr) ((volatile uint16_t*) (addr)) +#define mADDR(addr) (*mpADDR(addr)) +#define muADDR(addr) ((uint16_t) (&(addr))) + +#define USB_BYTE_REG_WRITE(addr, val) HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val)) +#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3)) +//#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr)) + +#define USB_HALF_WORD_REG_WRITE(addr, val) HAL_HALF_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr), (val)) +#define USB_HALF_WORD_REG_READ(addr) HAL_HALF_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr)) + +#define USB_WORD_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val)) +#define USB_WORD_REG_READ(addr) HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr)) + + +/************************** Register Deinition ***************************/ +//#define USB_BASE_ADDR_SOC 0x8000 + +//#define SOC_Reg mpADDR(USB_BASE_ADDR_SOC) + +#define cSOC_USB_OFST (0x100) + +#define ZM_CBUS_FIFO_SIZE_OFFSET (cSOC_USB_OFST) //OFFSET 0 + +#define cSOC_CBUS_CTL_OFFSET 0xF0 + +#define ZM_FUSB_BASE USB_CTRL_BASE_ADDRESS + +#define ZM_MAIN_CTRL_OFFSET 0x00 +#define ZM_DEVICE_ADDRESS_OFFSET 0x01 +#define ZM_TEST_OFFSET 0x02 +#define ZM_PHY_TEST_SELECT_OFFSET 0x08 +#define ZM_VDR_SPECIFIC_MODE_OFFSET 0x0A +#define ZM_CX_CONFIG_STATUS_OFFSET 0x0B +#define ZM_EP0_DATA1_OFFSET 0x0C +#define ZM_EP0_DATA2_OFFSET 0x0D +#define ZM_EP0_DATA_OFFSET 0x0C + +#define ZM_INTR_MASK_BYTE_0_OFFSET 0x11 +#define ZM_INTR_MASK_BYTE_1_OFFSET 0x12 +#define ZM_INTR_MASK_BYTE_2_OFFSET 0x13 +#define ZM_INTR_MASK_BYTE_3_OFFSET 0x14 +#define ZM_INTR_MASK_BYTE_4_OFFSET 0x15 +#define ZM_INTR_MASK_BYTE_5_OFFSET 0x16 +#define ZM_INTR_MASK_BYTE_6_OFFSET 0x17 +#define ZM_INTR_MASK_BYTE_7_OFFSET 0x18 + +#define ZM_INTR_GROUP_OFFSET 0x20 +#define ZM_INTR_SOURCE_0_OFFSET 0x21 +#define ZM_INTR_SOURCE_1_OFFSET 0x22 +#define ZM_INTR_SOURCE_2_OFFSET 0x23 +#define ZM_INTR_SOURCE_3_OFFSET 0x24 +#define ZM_INTR_SOURCE_4_OFFSET 0x25 +#define ZM_INTR_SOURCE_5_OFFSET 0x26 +#define ZM_INTR_SOURCE_6_OFFSET 0x27 +#define ZM_INTR_SOURCE_7_OFFSET 0x28 + +#define ZM_EP_IN_MAX_SIZE_HIGH_OFFSET 0x3F +#define ZM_EP_IN_MAX_SIZE_LOW_OFFSET 0x3E + +#define ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET 0x5F +#define ZM_EP_OUT_MAX_SIZE_LOW_OFFSET 0x5E + +#define ZM_EP3_BYTE_COUNT_HIGH_OFFSET 0xAE +#define ZM_EP3_BYTE_COUNT_LOW_OFFSET 0xBE +#define ZM_EP4_BYTE_COUNT_HIGH_OFFSET 0xAF +#define ZM_EP4_BYTE_COUNT_LOW_OFFSET 0xBF + +#define ZM_EP3_DATA_OFFSET 0xF8 +#define ZM_EP4_DATA_OFFSET 0xFC + +#define ZM_SOC_USB_MODE_CTRL_OFFSET 0x108 +#define ZM_SOC_USB_MAX_AGGREGATE_OFFSET 0x110 +#define ZM_SOC_USB_TIME_CTRL_OFFSET 0x114 + +#define ZM_ADDR_CONV 0x0 + +#define ZM_CBUS_FIFO_SIZE_REG (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV) + +#define ZM_CBUS_CTRL_REG (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV) + +#define ZM_MAIN_CTRL_REG (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV) + +#define ZM_DEVICE_ADDRESS_REG (ZM_DEVICE_ADDRESS_OFFSET^ZM_ADDR_CONV) + +#define ZM_TEST_REG (ZM_TEST_OFFSET^ZM_ADDR_CONV) + +#define ZM_PHY_TEST_SELECT_REG (ZM_PHY_TEST_SELECT_OFFSET^ZM_ADDR_CONV))) + +#define ZM_CX_CONFIG_STATUS_REG (ZM_CX_CONFIG_STATUS_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP0_DATA1_REG (ZM_EP0_DATA1_OFFSET^ZM_ADDR_CONV))) + +#define ZM_EP0_DATA2_REG (ZM_EP0_DATA2_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP0_DATA_REG (ZM_EP0_DATA_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_0_REG (ZM_INTR_MASK_BYTE_0_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_1_REG (ZM_INTR_MASK_BYTE_1_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_2_REG (ZM_INTR_MASK_BYTE_2_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_3_REG (ZM_INTR_MASK_BYTE_3_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_4_REG (ZM_INTR_MASK_BYTE_4_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_5_REG (ZM_INTR_MASK_BYTE_5_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_6_REG (ZM_INTR_MASK_BYTE_6_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_7_REG (ZM_INTR_MASK_BYTE_7_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_0_REG (ZM_INTR_SOURCE_0_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_1_REG (ZM_INTR_SOURCE_1_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_2_REG (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_3_REG (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_4_REG (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_5_REG (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_6_REG (ZM_INTR_SOURCE_6_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_7_REG (ZM_INTR_SOURCE_7_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_GROUP_REG (ZM_INTR_GROUP_OFFSET^ZM_ADDR_CONV))) + +#define ZM_EP3_BYTE_COUNT_HIGH_REG (ZM_EP3_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP3_BYTE_COUNT_LOW_REG (ZM_EP3_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP4_BYTE_COUNT_HIGH_REG (ZM_EP4_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP4_BYTE_COUNT_LOW_REG (ZM_EP4_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP3_DATA_REG (ZM_EP3_DATA_OFFSET) + +#define ZM_EP4_DATA_REG (ZM_EP4_DATA_OFFSET) + +#define ZM_SOC_USB_MODE_CTRL_REG (ZM_SOC_USB_MODE_CTRL_OFFSET) + +#define ZM_SOC_USB_MAX_AGGREGATE_REG (ZM_SOC_USB_MAX_AGGREGATE_OFFSET) + +#define ZM_SOC_USB_TIME_CTRL_REG (ZM_SOC_USB_TIME_CTRL_OFFSET) + +#define bmHIGH_SPEED BIT6 +#define bmCWR_BUF_END BIT1 + +#define mUsbEP0DataRd1() (USB_BYTE_REG_READ(ZM_EP0_DATA1_OFFSET)) +//#define mUsbEP0DataRd2() ZM_EP0_DATA2_REG +//#define mUsbEP0DataRd3() ZM_EP0_DATA3_REG +//#define mUsbEP0DataRd4() ZM_EP0_DATA4_REG +#define mUsbEP0DataWr1(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA1_OFFSET, data)) +#define mUsbEP0DataWr2(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA2_OFFSET, data)) + +#define mGetByte0(data) ( data & 0xff ) +#define mGetByte1(data) ( (data >> 8) & 0xff ) +#define mGetByte2(data) ( (data >> 16) & 0xff ) +#define mGetByte3(data) ( (data >> 24) & 0xff ) + +//#define mUsbHighSpeedST() (ZM_MAIN_CTRL_REG & BIT6) +//#define mUsbCfgST() (ZM_DEVICE_ADDRESS_REG & BIT7) +//#define mUsbApWrEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END) +//#define mUsbApRdEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END) + +#define mUsbHighSpeedST() (USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET) & BIT6) +#define mUsbCfgST() (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET) & BIT7) +#define mUsbApWrEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END) +#define mUsbApRdEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END) + +#define mUsbRmWkupST() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT0) +#define mUsbRmWkupClr() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0) +#define mUsbRmWkupSet() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0) + +#define mUsbGlobIntEnable() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2) + +#define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f) +#define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)|0xc0) +#define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf) +#define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0) +// USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0x40) + +#define mUSB_EP3_XFER_DONE() USB_BYTE_REG_WRITE(ZM_EP3_BYTE_COUNT_HIGH_OFFSET, \ + USB_BYTE_REG_READ(ZM_EP3_BYTE_COUNT_HIGH_OFFSET)|0x08) + + + +#define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512 +#define HS_C1_I0_A0_EP1_bInterval 00 + +#define HS_C1_I0_A0_EP_NUMBER 0x06 +#define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER) +#define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH) +#define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH) + +#define HS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + HS_C1_INTERFACE_LENGTH) +#define FS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + FS_C1_INTERFACE_LENGTH) + +#define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64 +//#define FS_C1_I0_A0_EP1_bInterval HS_C1_I0_A0_EP1_bInterval + +#define HS_CONFIGURATION_NUMBER 1 +#define FS_CONFIGURATION_NUMBER 1 + +#define fDOUBLE_BUF 1 +#define fDOUBLE_BUF_IN 1 + +#define fFLASH_DISK 0 +#define fENABLE_ISO 0 + +#if (HS_CONFIGURATION_NUMBER >= 1) + // Configuration 0X01 + #define HS_C1_INTERFACE_NUMBER 0x01 + #define HS_C1 0x01 + #define HS_C1_iConfiguration 0x00 + #define HS_C1_bmAttribute 0x80 + #if !(fFLASH_DISK && !fFLASH_BOOT) + #define HS_C1_iMaxPower 0xFA + #else + #define HS_C1_iMaxPower 0x32 + #endif + + #if (HS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #define HS_C1_I0_ALT_NUMBER 0X01 + #if (HS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0X00 + #define HS_C1_I0_A0_bInterfaceNumber 0X00 + #define HS_C1_I0_A0_bAlternateSetting 0X00 + //JWEI 2003/07/14 + //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT) + #define HS_C1_I0_A0_EP_NUMBER 0x06 + //#else + //#define HS_C1_I0_A0_EP_NUMBER 0X03 + //#endif + #if !(fFLASH_DISK && !fFLASH_BOOT) + #define HS_C1_I0_A0_bInterfaceClass 0XFF + #define HS_C1_I0_A0_bInterfaceSubClass 0X00 + #define HS_C1_I0_A0_bInterfaceProtocol 0X00 + #else + #define HS_C1_I0_A0_bInterfaceClass 0X08 + #define HS_C1_I0_A0_bInterfaceSubClass 0X06 + #define HS_C1_I0_A0_bInterfaceProtocol 0X50 + #endif + #define HS_C1_I0_A0_iInterface 0X00 + + #if (HS_C1_I0_A0_EP_NUMBER >= 1) + //EP0X01 + #define HS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE + //JWEI 2003/05/19 + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP1_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK + //JWEI 2003/05/07 + #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP1_bInterval 00 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 2) + //EP0X02 + #define HS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE + //JWEI 2003/08/20 + #if fDOUBLE_BUF_IN + #define HS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP2_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN + #define HS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK + #define HS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP2_bInterval 00 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 3) + //EP0X03 + #define HS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE + #define HS_C1_I0_A0_EP3_BLKNO SINGLE_BLK + #define HS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN + #define HS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT + #define HS_C1_I0_A0_EP3_MAX_PACKET 0x0040 + #define HS_C1_I0_A0_EP3_bInterval 01 + #endif + // Note: HS Bulk type require max pkt size = 512 + // ==> must use Interrupt type for max pkt size = 64 + #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + //EP0X04 + #define HS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE + #define HS_C1_I0_A0_EP4_BLKNO SINGLE_BLK + #define HS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP4_TYPE TF_TYPE_INTERRUPT + #define HS_C1_I0_A0_EP4_MAX_PACKET 0x0040 + #define HS_C1_I0_A0_EP4_bInterval 01 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 5) + //EP0X04 + #define HS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP5_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK + #define HS_C1_I0_A0_EP5_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP5_bInterval 00 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 6) + //EP0X04 + #define HS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP6_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK + #define HS_C1_I0_A0_EP6_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP6_bInterval 00 + #endif + #endif + #endif +#endif + +#if (HS_CONFIGURATION_NUMBER >= 1) + // Configuration 1 + #if (HS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #if (HS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER) + #if (HS_C1_I0_A0_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I0_A0_EP1_FIFO_START FIFO0 + #define HS_C1_I0_A0_EP1_FIFO_NO (HS_C1_I0_A0_EP1_BLKNO * HS_C1_I0_A0_EP1_BLKSIZE) + #define HS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP1_BLKNO - 1) << 2) | HS_C1_I0_A0_EP1_TYPE) + #define HS_C1_I0_A0_EP1_FIFO_MAP (((1 - HS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I0_A0_EP1_MAP (HS_C1_I0_A0_EP1_FIFO_START | (HS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP1_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 2) + // EP2 + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP2_FIFO_START (HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO) + #else + #define HS_C1_I0_A0_EP2_FIFO_START FIFO2 + #endif + #define HS_C1_I0_A0_EP2_FIFO_NO (HS_C1_I0_A0_EP2_BLKNO * HS_C1_I0_A0_EP2_BLKSIZE) + #define HS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP2_BLKNO - 1) << 2) | HS_C1_I0_A0_EP2_TYPE) + #define HS_C1_I0_A0_EP2_FIFO_MAP (((1 - HS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I0_A0_EP2_MAP (HS_C1_I0_A0_EP2_FIFO_START | (HS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP2_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 3) + // EP3 + //JWEI 2003/07/15 + // #define HS_C1_I0_A0_EP3_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO) + #define HS_C1_I0_A0_EP3_FIFO_START FIFO14 + #define HS_C1_I0_A0_EP3_FIFO_NO (HS_C1_I0_A0_EP3_BLKNO * HS_C1_I0_A0_EP3_BLKSIZE) + #define HS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP3_BLKNO - 1) << 2) | HS_C1_I0_A0_EP3_TYPE) + #define HS_C1_I0_A0_EP3_FIFO_MAP (((1 - HS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I0_A0_EP3_MAP (HS_C1_I0_A0_EP3_FIFO_START | (HS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP3_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + // EP4 + #define HS_C1_I0_A0_EP4_FIFO_START (HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO) + #define HS_C1_I0_A0_EP4_FIFO_NO (HS_C1_I0_A0_EP4_BLKNO * HS_C1_I0_A0_EP4_BLKSIZE) + #define HS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP4_BLKNO - 1) << 2) | HS_C1_I0_A0_EP4_TYPE) + #define HS_C1_I0_A0_EP4_FIFO_MAP (((1 - HS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4) + #define HS_C1_I0_A0_EP4_MAP (HS_C1_I0_A0_EP4_FIFO_START | (HS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP4_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 5) + // EP5 + #define HS_C1_I0_A0_EP5_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO) + #define HS_C1_I0_A0_EP5_FIFO_NO (HS_C1_I0_A0_EP5_BLKNO * HS_C1_I0_A0_EP5_BLKSIZE) + #define HS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP5_BLKNO - 1) << 2) | HS_C1_I0_A0_EP5_TYPE) + #define HS_C1_I0_A0_EP5_FIFO_MAP (((1 - HS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5) + #define HS_C1_I0_A0_EP5_MAP (HS_C1_I0_A0_EP5_FIFO_START | (HS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP5_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 6) + // EP5 + #define HS_C1_I0_A0_EP6_FIFO_START (HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO) + #define HS_C1_I0_A0_EP6_FIFO_NO (HS_C1_I0_A0_EP6_BLKNO * HS_C1_I0_A0_EP6_BLKSIZE) + #define HS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP6_BLKNO - 1) << 2) | HS_C1_I0_A0_EP6_TYPE) + #define HS_C1_I0_A0_EP6_FIFO_MAP (((1 - HS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6) + #define HS_C1_I0_A0_EP6_MAP (HS_C1_I0_A0_EP6_FIFO_START | (HS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP6_DIRECTION))) + #endif + #endif + + #if (HS_C1_I0_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define HS_C1_I0_A1_EP_LENGTH (EP_LENGTH * HS_C1_I0_A1_EP_NUMBER) + #if (HS_C1_I0_A1_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I0_A1_EP1_FIFO_START FIFO0 + #define HS_C1_I0_A1_EP1_FIFO_NO (HS_C1_I0_A1_EP1_BLKNO * HS_C1_I0_A1_EP1_BLKSIZE) + #define HS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP1_BLKNO - 1) << 2) | HS_C1_I0_A1_EP1_TYPE) + #define HS_C1_I0_A1_EP1_FIFO_MAP (((1 - HS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I0_A1_EP1_MAP (HS_C1_I0_A1_EP1_FIFO_START | (HS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP1_DIRECTION))) + #endif + #if (HS_C1_I0_A1_EP_NUMBER >= 2) + // EP2 + #define HS_C1_I0_A1_EP2_FIFO_START (HS_C1_I0_A1_EP1_FIFO_START + HS_C1_I0_A1_EP1_FIFO_NO) + #define HS_C1_I0_A1_EP2_FIFO_NO (HS_C1_I0_A1_EP2_BLKNO * HS_C1_I0_A1_EP2_BLKSIZE) + #define HS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP2_BLKNO - 1) << 2) | HS_C1_I0_A1_EP2_TYPE) + #define HS_C1_I0_A1_EP2_FIFO_MAP (((1 - HS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I0_A1_EP2_MAP (HS_C1_I0_A1_EP2_FIFO_START | (HS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP2_DIRECTION))) + #endif + #if (HS_C1_I0_A1_EP_NUMBER >= 3) + // EP3 + #define HS_C1_I0_A1_EP3_FIFO_START (HS_C1_I0_A1_EP2_FIFO_START + HS_C1_I0_A1_EP2_FIFO_NO) + #define HS_C1_I0_A1_EP3_FIFO_NO (HS_C1_I0_A1_EP3_BLKNO * HS_C1_I0_A1_EP3_BLKSIZE) + #define HS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP3_BLKNO - 1) << 2) | HS_C1_I0_A1_EP3_TYPE) + #define HS_C1_I0_A1_EP3_FIFO_MAP (((1 - HS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I0_A1_EP3_MAP (HS_C1_I0_A1_EP3_FIFO_START | (HS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP3_DIRECTION))) + #endif + #endif + + #if (HS_C1_I0_ALT_NUMBER == 1) + #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH) + #elif (HS_C1_I0_ALT_NUMBER == 2) + #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH + HS_C1_I0_A1_EP_LENGTH) + #endif + #endif + + #if (HS_C1_INTERFACE_NUMBER >= 2) + // Interface 1 + #if (HS_C1_I1_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define HS_C1_I1_A0_EP_LENGTH (EP_LENGTH * HS_C1_I1_A0_EP_NUMBER) + #if (HS_C1_I1_A0_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I1_A0_EP1_FIFO_START FIFO0 + #define HS_C1_I1_A0_EP1_FIFO_NO (HS_C1_I1_A0_EP1_BLKNO * HS_C1_I1_A0_EP1_BLKSIZE) + #define HS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP1_BLKNO - 1) << 2) | HS_C1_I1_A0_EP1_TYPE) + #define HS_C1_I1_A0_EP1_FIFO_MAP (((1 - HS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I1_A0_EP1_MAP (HS_C1_I1_A0_EP1_FIFO_START | (HS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP1_DIRECTION))) + #endif + #if (HS_C1_I1_A0_EP_NUMBER >= 2) + // EP2 + #define HS_C1_I1_A0_EP2_FIFO_START (HS_C1_I1_A0_EP1_FIFO_START + HS_C1_I1_A0_EP1_FIFO_NO) + #define HS_C1_I1_A0_EP2_FIFO_NO (HS_C1_I1_A0_EP2_BLKNO * HS_C1_I1_A0_EP2_BLKSIZE) + #define HS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP2_BLKNO - 1) << 2) | HS_C1_I1_A0_EP2_TYPE) + #define HS_C1_I1_A0_EP2_FIFO_MAP (((1 - HS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I1_A0_EP2_MAP (HS_C1_I1_A0_EP2_FIFO_START | (HS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP2_DIRECTION))) + #endif + #if (HS_C1_I1_A0_EP_NUMBER >= 3) + // EP3 + #define HS_C1_I1_A0_EP3_FIFO_START (HS_C1_I1_A0_EP2_FIFO_START + HS_C1_I1_A0_EP2_FIFO_NO) + #define HS_C1_I1_A0_EP3_FIFO_NO (HS_C1_I1_A0_EP3_BLKNO * HS_C1_I1_A0_EP3_BLKSIZE) + #define HS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP3_BLKNO - 1) << 2) | HS_C1_I1_A0_EP3_TYPE) + #define HS_C1_I1_A0_EP3_FIFO_MAP (((1 - HS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I1_A0_EP3_MAP (HS_C1_I1_A0_EP3_FIFO_START | (HS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP3_DIRECTION))) + #endif + #endif + + #if (HS_C1_I1_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define HS_C1_I1_A1_EP_LENGTH (EP_LENGTH * HS_C1_I1_A1_EP_NUMBER) + #if (HS_C1_I1_A1_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I1_A1_EP1_FIFO_START FIFO0 + #define HS_C1_I1_A1_EP1_FIFO_NO (HS_C1_I1_A1_EP1_BLKNO * HS_C1_I1_A1_EP1_BLKSIZE) + #define HS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP1_BLKNO - 1) << 2) | HS_C1_I1_A1_EP1_TYPE) + #define HS_C1_I1_A1_EP1_FIFO_MAP (((1 - HS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I1_A1_EP1_MAP (HS_C1_I1_A1_EP1_FIFO_START | (HS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP1_DIRECTION))) + #endif + #if (HS_C1_I1_A1_EP_NUMBER >= 2) + // EP2 + #define HS_C1_I1_A1_EP2_FIFO_START (HS_C1_I1_A1_EP1_FIFO_START + HS_C1_I1_A1_EP1_FIFO_NO) + #define HS_C1_I1_A1_EP2_FIFO_NO (HS_C1_I1_A1_EP2_BLKNO * HS_C1_I1_A1_EP2_BLKSIZE) + #define HS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP2_BLKNO - 1) << 2) | HS_C1_I1_A1_EP2_TYPE) + #define HS_C1_I1_A1_EP2_FIFO_MAP (((1 - HS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I1_A1_EP2_MAP (HS_C1_I1_A1_EP2_FIFO_START | (HS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP2_DIRECTION))) + #endif + #if (HS_C1_I1_A1_EP_NUMBER >= 3) + // EP3 + #define HS_C1_I1_A1_EP3_FIFO_START (HS_C1_I1_A1_EP2_FIFO_START + HS_C1_I1_A1_EP2_FIFO_NO) + #define HS_C1_I1_A1_EP3_FIFO_NO (HS_C1_I1_A1_EP3_BLKNO * HS_C1_I1_A1_EP3_BLKSIZE) + #define HS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP3_BLKNO - 1) << 2) | HS_C1_I1_A1_EP3_TYPE) + #define HS_C1_I1_A1_EP3_FIFO_MAP (((1 - HS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I1_A1_EP3_MAP (HS_C1_I1_A1_EP3_FIFO_START | (HS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP3_DIRECTION))) + #endif + #endif + + #if (HS_C1_I1_ALT_NUMBER == 1) + #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH) + #elif (HS_C1_I1_ALT_NUMBER == 2) + #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH + HS_C1_I1_A1_EP_LENGTH) + #endif + #endif + + #if (HS_C1_INTERFACE_NUMBER == 1) + #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH) + #elif (HS_C1_INTERFACE_NUMBER == 2) + #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH + HS_C1_I1_ALT_LENGTH) + #endif +#endif + +#if (FS_CONFIGURATION_NUMBER >= 1) + // Configuration 0X01 + #define FS_C1_INTERFACE_NUMBER 0X01 + #define FS_C1 0X01 + #define FS_C1_iConfiguration 0X00 + #define FS_C1_bmAttribute 0X80 + #define FS_C1_iMaxPower 0XFA + + #if (FS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #define FS_C1_I0_ALT_NUMBER 0X01 + #if (FS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0X00 + #define FS_C1_I0_A0_bInterfaceNumber 0X00 + #define FS_C1_I0_A0_bAlternateSetting 0X00 + //JWEI 2003/07/14 + //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT) + #define FS_C1_I0_A0_EP_NUMBER 0x05 + //#else + //#define FS_C1_I0_A0_EP_NUMBER 0X03 + //#endif + #if !(fFLASH_DISK && !fFLASH_BOOT) + #define FS_C1_I0_A0_bInterfaceClass 0XFF + #define FS_C1_I0_A0_bInterfaceSubClass 0X00 + #define FS_C1_I0_A0_bInterfaceProtocol 0X00 + #else + #define FS_C1_I0_A0_bInterfaceClass 0X08 + #define FS_C1_I0_A0_bInterfaceSubClass 0X06 + #define FS_C1_I0_A0_bInterfaceProtocol 0X50 + #endif + #define FS_C1_I0_A0_iInterface 0X00 + + #if (FS_C1_I0_A0_EP_NUMBER >= 1) + //EP0X01 + #define FS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE + //JWEI 2003/05/19 + #if fDOUBLE_BUF + #define FS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP1_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK + //JWEI 2003/05/07 + #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64 + #define FS_C1_I0_A0_EP1_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 2) + //EP0X02 + #define FS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE + //JWEI 2003/08/20 + #if fDOUBLE_BUF_IN + #define FS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP2_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN + #define FS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_64 + #define FS_C1_I0_A0_EP2_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 3) + //EP0X03 + #define FS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE + #define FS_C1_I0_A0_EP3_BLKNO SINGLE_BLK + #define FS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN + #define FS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT + #define FS_C1_I0_A0_EP3_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP3_bInterval 01 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + //EP0X04 + #define FS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE + #define FS_C1_I0_A0_EP4_BLKNO SINGLE_BLK + #define FS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP4_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP4_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP4_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 5) + //EP0X04 + #define FS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF_IN + #define FS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP5_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP5_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP5_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 6) + //EP0X04 + #define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF_IN + #define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP6_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP6_bInterval 00 + #endif + #endif + #endif +#endif + +#if (FS_CONFIGURATION_NUMBER >= 1) + // Configuration 1 + #if (FS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #if (FS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define FS_C1_I0_A0_EP_LENGTH (EP_LENGTH * FS_C1_I0_A0_EP_NUMBER) + #if (FS_C1_I0_A0_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I0_A0_EP1_FIFO_START FIFO0 + #define FS_C1_I0_A0_EP1_FIFO_NO (FS_C1_I0_A0_EP1_BLKNO * FS_C1_I0_A0_EP1_BLKSIZE) + #define FS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP1_BLKNO - 1) << 2) | FS_C1_I0_A0_EP1_TYPE) + #define FS_C1_I0_A0_EP1_FIFO_MAP (((1 - FS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I0_A0_EP1_MAP (FS_C1_I0_A0_EP1_FIFO_START | (FS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP1_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I0_A0_EP2_FIFO_START (FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO) + #define FS_C1_I0_A0_EP2_FIFO_NO (FS_C1_I0_A0_EP2_BLKNO * FS_C1_I0_A0_EP2_BLKSIZE) + #define FS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP2_BLKNO - 1) << 2) | FS_C1_I0_A0_EP2_TYPE) + #define FS_C1_I0_A0_EP2_FIFO_MAP (((1 - FS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I0_A0_EP2_MAP (FS_C1_I0_A0_EP2_FIFO_START | (FS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP2_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 3) + // EP3 + //JWEI 2003/07/15 + // #define FS_C1_I0_A0_EP3_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO) + #define FS_C1_I0_A0_EP3_FIFO_START FIFO14 + #define FS_C1_I0_A0_EP3_FIFO_NO (FS_C1_I0_A0_EP3_BLKNO * FS_C1_I0_A0_EP3_BLKSIZE) + #define FS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP3_BLKNO - 1) << 2) | FS_C1_I0_A0_EP3_TYPE) + #define FS_C1_I0_A0_EP3_FIFO_MAP (((1 - FS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I0_A0_EP3_MAP (FS_C1_I0_A0_EP3_FIFO_START | (FS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP3_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + // EP4 + #define FS_C1_I0_A0_EP4_FIFO_START (FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO) + #define FS_C1_I0_A0_EP4_FIFO_NO (FS_C1_I0_A0_EP4_BLKNO * FS_C1_I0_A0_EP4_BLKSIZE) + #define FS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP4_BLKNO - 1) << 2) | FS_C1_I0_A0_EP4_TYPE) + #define FS_C1_I0_A0_EP4_FIFO_MAP (((1 - FS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4) + #define FS_C1_I0_A0_EP4_MAP (FS_C1_I0_A0_EP4_FIFO_START | (FS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP4_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 5) + // EP5 + #define FS_C1_I0_A0_EP5_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO) + #define FS_C1_I0_A0_EP5_FIFO_NO (FS_C1_I0_A0_EP5_BLKNO * FS_C1_I0_A0_EP5_BLKSIZE) + #define FS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP5_BLKNO - 1) << 2) | FS_C1_I0_A0_EP5_TYPE) + #define FS_C1_I0_A0_EP5_FIFO_MAP (((1 - FS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5) + #define FS_C1_I0_A0_EP5_MAP (FS_C1_I0_A0_EP5_FIFO_START | (FS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP5_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 6) + // EP5 + #define FS_C1_I0_A0_EP6_FIFO_START (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO) + #define FS_C1_I0_A0_EP6_FIFO_NO (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE) + #define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE) + #define FS_C1_I0_A0_EP6_FIFO_MAP (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6) + #define FS_C1_I0_A0_EP6_MAP (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION))) + #endif + #endif + + #if (FS_C1_I0_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define FS_C1_I0_A1_EP_LENGTH (EP_LENGTH * FS_C1_I0_A1_EP_NUMBER) + #if (FS_C1_I0_A1_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I0_A1_EP1_FIFO_START FIFO0 + #define FS_C1_I0_A1_EP1_FIFO_NO (FS_C1_I0_A1_EP1_BLKNO * FS_C1_I0_A1_EP1_BLKSIZE) + #define FS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP1_BLKNO - 1) << 2) | FS_C1_I0_A1_EP1_TYPE) + #define FS_C1_I0_A1_EP1_FIFO_MAP (((1 - FS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I0_A1_EP1_MAP (FS_C1_I0_A1_EP1_FIFO_START | (FS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP1_DIRECTION))) + #endif + #if (FS_C1_I0_A1_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I0_A1_EP2_FIFO_START (FS_C1_I0_A1_EP1_FIFO_START + FS_C1_I0_A1_EP1_FIFO_NO) + #define FS_C1_I0_A1_EP2_FIFO_NO (FS_C1_I0_A1_EP2_BLKNO * FS_C1_I0_A1_EP2_BLKSIZE) + #define FS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP2_BLKNO - 1) << 2) | FS_C1_I0_A1_EP2_TYPE) + #define FS_C1_I0_A1_EP2_FIFO_MAP (((1 - FS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I0_A1_EP2_MAP (FS_C1_I0_A1_EP2_FIFO_START | (FS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP2_DIRECTION))) + #endif + #if (FS_C1_I0_A1_EP_NUMBER >= 3) + // EP3 + #define FS_C1_I0_A1_EP3_FIFO_START (FS_C1_I0_A1_EP2_FIFO_START + FS_C1_I0_A1_EP2_FIFO_NO) + #define FS_C1_I0_A1_EP3_FIFO_NO (FS_C1_I0_A1_EP3_BLKNO * FS_C1_I0_A1_EP3_BLKSIZE) + #define FS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP3_BLKNO - 1) << 2) | FS_C1_I0_A1_EP3_TYPE) + #define FS_C1_I0_A1_EP3_FIFO_MAP (((1 - FS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I0_A1_EP3_MAP (FS_C1_I0_A1_EP3_FIFO_START | (FS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP3_DIRECTION))) + #endif + #endif + + #if (FS_C1_I0_ALT_NUMBER == 1) + #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH) + #elif (FS_C1_I0_ALT_NUMBER == 2) + #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH + FS_C1_I0_A1_EP_LENGTH) + #endif + #endif + + #if (FS_C1_INTERFACE_NUMBER >= 2) + // Interface 1 + #if (FS_C1_I1_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define FS_C1_I1_A0_EP_LENGTH (EP_LENGTH * FS_C1_I1_A0_EP_NUMBER) + #if (FS_C1_I1_A0_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I1_A0_EP1_FIFO_START FIFO0 + #define FS_C1_I1_A0_EP1_FIFO_NO (FS_C1_I1_A0_EP1_BLKNO * FS_C1_I1_A0_EP1_BLKSIZE) + #define FS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP1_BLKNO - 1) << 2) | FS_C1_I1_A0_EP1_TYPE) + #define FS_C1_I1_A0_EP1_FIFO_MAP (((1 - FS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I1_A0_EP1_MAP (FS_C1_I1_A0_EP1_FIFO_START | (FS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP1_DIRECTION))) + #endif + #if (FS_C1_I1_A0_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I1_A0_EP2_FIFO_START (FS_C1_I1_A0_EP1_FIFO_START + FS_C1_I1_A0_EP1_FIFO_NO) + #define FS_C1_I1_A0_EP2_FIFO_NO (FS_C1_I1_A0_EP2_BLKNO * FS_C1_I1_A0_EP2_BLKSIZE) + #define FS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP2_BLKNO - 1) << 2) | FS_C1_I1_A0_EP2_TYPE) + #define FS_C1_I1_A0_EP2_FIFO_MAP (((1 - FS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I1_A0_EP2_MAP (FS_C1_I1_A0_EP2_FIFO_START | (FS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP2_DIRECTION))) + #endif + #if (FS_C1_I1_A0_EP_NUMBER >= 3) + // EP3 + #define FS_C1_I1_A0_EP3_FIFO_START (FS_C1_I1_A0_EP2_FIFO_START + FS_C1_I1_A0_EP2_FIFO_NO) + #define FS_C1_I1_A0_EP3_FIFO_NO (FS_C1_I1_A0_EP3_BLKNO * FS_C1_I1_A0_EP3_BLKSIZE) + #define FS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP3_BLKNO - 1) << 2) | FS_C1_I1_A0_EP3_TYPE) + #define FS_C1_I1_A0_EP3_FIFO_MAP (((1 - FS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I1_A0_EP3_MAP (FS_C1_I1_A0_EP3_FIFO_START | (FS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP3_DIRECTION))) + #endif + #endif + + #if (FS_C1_I1_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define FS_C1_I1_A1_EP_LENGTH (EP_LENGTH * FS_C1_I1_A1_EP_NUMBER) + #if (FS_C1_I1_A1_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I1_A1_EP1_FIFO_START FIFO0 + #define FS_C1_I1_A1_EP1_FIFO_NO (FS_C1_I1_A1_EP1_BLKNO * FS_C1_I1_A1_EP1_BLKSIZE) + #define FS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP1_BLKNO - 1) << 2) | FS_C1_I1_A1_EP1_TYPE) + #define FS_C1_I1_A1_EP1_FIFO_MAP (((1 - FS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I1_A1_EP1_MAP (FS_C1_I1_A1_EP1_FIFO_START | (FS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP1_DIRECTION))) + #endif + #if (FS_C1_I1_A1_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I1_A1_EP2_FIFO_START (FS_C1_I1_A1_EP1_FIFO_START + FS_C1_I1_A1_EP1_FIFO_NO) + #define FS_C1_I1_A1_EP2_FIFO_NO (FS_C1_I1_A1_EP2_BLKNO * FS_C1_I1_A1_EP2_BLKSIZE) + #define FS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP2_BLKNO - 1) << 2) | FS_C1_I1_A1_EP2_TYPE) + #define FS_C1_I1_A1_EP2_FIFO_MAP (((1 - FS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I1_A1_EP2_MAP (FS_C1_I1_A1_EP2_FIFO_START | (FS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP2_DIRECTION))) + #endif + #if (FS_C1_I1_A1_EP_NUMBER >= 3) + // EP3 + #define FS_C1_I1_A1_EP3_FIFO_START (FS_C1_I1_A1_EP2_FIFO_START + FS_C1_I1_A1_EP2_FIFO_NO) + #define FS_C1_I1_A1_EP3_FIFO_NO (FS_C1_I1_A1_EP3_BLKNO * FS_C1_I1_A1_EP3_BLKSIZE) + #define FS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP3_BLKNO - 1) << 2) | FS_C1_I1_A1_EP3_TYPE) + #define FS_C1_I1_A1_EP3_FIFO_MAP (((1 - FS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I1_A1_EP3_MAP (FS_C1_I1_A1_EP3_FIFO_START | (FS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP3_DIRECTION))) + #endif + #endif + + #if (FS_C1_I1_ALT_NUMBER == 1) + #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH) + #elif (FS_C1_I1_ALT_NUMBER == 2) + #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH + FS_C1_I1_A1_EP_LENGTH) + #endif + #endif + + #if (FS_C1_INTERFACE_NUMBER == 1) + #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH) + #elif (FS_C1_INTERFACE_NUMBER == 2) + #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH + HS_FS_C1_I1_ALT_LENGTH) + #endif +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable + +#define USB_DISABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable + +#define USB_UP_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))) // upQ stream mode + +#define USB_UP_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3)) // upQ packet mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1)) // lp downstream DMA enable + +#define USB_DISABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))) // lp downstream DMA disable + +#define USB_LP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT6))) // lpQ packet mode + +#define USB_LP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)) // lpQ stream mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable + +#define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable + +#define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7))) // hpQ packet mode + +#define USB_HP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7)) // hpQ stream mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable + +#define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable + +#define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10))) // hpQ packet mode + +#define USB_MP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10)) // hpQ stream mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define USB_ENABLE_UP_PACKET_MODE() USB_DISABLE_UP_DMA(); \ + USB_UP_PACKET_MODE(); \ + USB_ENABLE_UP_DMA(); + +#define USB_ENABLE_LP_DN_PACKET_MODE() USB_DISABLE_LP_DN_DMA(); \ + USB_LP_DN_PACKET_MODE(); \ + USB_ENABLE_LP_DN_DMA() + +#define USB_ENABLE_MP_DN_PACKET_MODE() USB_DISABLE_MP_DN_DMA(); \ + USB_MP_DN_PACKET_MODE(); \ + USB_ENABLE_MP_DN_DMA(); + +#define USB_ENABLE_HP_DN_PACKET_MODE() USB_DISABLE_HP_DN_DMA(); \ + USB_HP_DN_PACKET_MODE(); \ + USB_ENABLE_HP_DN_DMA(); + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_UP_STREAM_MODE() USB_DISABLE_UP_DMA(); \ + USB_UP_STREAM_MODE(); \ + USB_ENABLE_UP_DMA(); + +#define USB_ENABLE_LP_DN_STREAM_MODE() USB_DISABLE_LP_DN_DMA(); \ + USB_LP_DN_STREAM_MODE(); \ + USB_ENABLE_LP_DN_DMA() + +#define USB_ENABLE_MP_DN_STREAM_MODE() USB_DISABLE_MP_DN_DMA(); \ + USB_MP_DN_STREAM_MODE(); \ + USB_ENABLE_MP_DN_DMA(); + +#define USB_ENABLE_HP_DN_STREAM_MODE() USB_DISABLE_HP_DN_DMA(); \ + USB_HP_DN_STREAM_MODE(); \ + USB_ENABLE_HP_DN_DMA(); + +#define USB_STREAM_HOST_BUF_SIZE(size) USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size))); +#define USB_STREAM_TIMEOUT(time_cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt); // set stream mode timeout critirea +#define USB_STREAM_AGG_PKT_CNT(cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_extr.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_extr.h new file mode 100755 index 0000000..1886800 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_extr.h @@ -0,0 +1,34 @@ +#ifndef USB_EXTR_H +#define USB_EXTR_H + +#if 0 +#include "dt_defs.h" +#include "usb_type.h" + +/* Variable for USB EP0 pipe (USB.c) */ +uint16_t *pu8DescriptorEX; +uint16_t u16TxRxCounter; +uint16_t *u8ConfigDescriptorEX; +//extern BOOLEAN bUsbEP0HaltSt; +Action eUsbCxFinishAction; +CommandType eUsbCxCommand; +BOOLEAN UsbChirpFinish; +uint16_t u8UsbConfigValue; +uint16_t u8UsbInterfaceValue; +uint16_t u8UsbInterfaceAlternateSetting; +uint16_t u16FirmwareComplete; + +uint16_t *UsbDeviceDescriptor; +uint16_t *String00Descriptor; +uint16_t *String10Descriptor; +uint16_t *String20Descriptor; +uint16_t *String30Descriptor; +uint16_t *u8DeviceQualifierDescriptorEX; +uint16_t *u8OtherSpeedConfigDescriptorEX; +uint16_t *u8UsbDeviceDescriptor; +uint16_t *u8String00Descriptor; +uint16_t *u8String10Descriptor; +uint16_t *u8String20Descriptor; +uint16_t *u8String30Descriptor; +#endif +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_fifo.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_fifo.c new file mode 100755 index 0000000..4b77cc4 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_fifo.c @@ -0,0 +1,435 @@ +#include "usb_defs.h" +#include "usb_type.h" +#include "usb_pre.h" +#include "usb_extr.h" +#include "usb_std.h" +#include "dt_defs.h" +#include "sys_cfg.h" + +#include "athos_api.h" + +#if SYSTEM_MODULE_USB + +extern uint16_t u8UsbConfigValue; +extern uint16_t u8UsbInterfaceValue; +extern uint16_t u8UsbInterfaceAlternateSetting; + +#if 1 + +void mUsbEPMap(uint8_t EPn, uint8_t MAP) +{ + //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x30+(EPn-1)); + //*reg = MAP; + uint8_t reg = (0x30+(EPn-1)); + +// A_PRINTF("=>mUsbEPMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg)); + USB_BYTE_REG_WRITE(reg, MAP ); + +// A_PRINTF("<=mUsbEPMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg)); + + //zfUartSendStr("mUsbEPMap\r\n"); + //zfUartSendStrAndHex("EPn=", EPn); + //zfUartSendStrAndHex("MAP=", MAP); +} + +void mUsbFIFOMap(uint8_t FIFOn, uint8_t MAP) +{ + //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x80+FIFOn); + //*reg = MAP; + + uint8_t reg = (0x80+FIFOn); + + reg = reg; + +// A_PRINTF("=>mUsbFIFOMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg)); + USB_BYTE_REG_WRITE( reg, MAP ); + +// A_PRINTF("<=mUsbFIFOMap: write: %02x to %02x (0x%08x)\n\r", MAP , reg, USB_WORD_REG_READ(reg)); + //zfUartSendStr("mUsbFIFOMap\r\n"); + //zfUartSendStrAndHex("FIFOn=", FIFOn); + //zfUartSendStrAndHex("MAP=", MAP); +} + +void mUsbFIFOConfig(uint8_t FIFOn, uint8_t cfg) +{ + //uint8_t *reg = (uint8_t*) (ZM_FUSB_BASE+0x90+FIFOn); + //*reg = cfg; + uint8_t reg = (0x90+FIFOn); + +// A_PRINTF("=>mUsbFIFOConfig: write: %02x to %02x (0x%08x)\n\r", cfg , reg, USB_WORD_REG_READ(reg)); + USB_BYTE_REG_WRITE( reg, cfg ); + +// A_PRINTF("<=mUsbFIFOConfig: write: %02x to %02x (0x%08x)\n\r", cfg , reg, USB_WORD_REG_READ(reg)); + //zfUartSendStr((uint8_t *)"mUsbFIFOConfig\r\n"); + //zfUartSendStrAndHex((uint8_t *)"FIFOn=", FIFOn); + //zfUartSendStrAndHex((uint8_t *)"cfg=", cfg); +} + +void mUsbEPMxPtSzHigh(uint8_t EPn, uint8_t dir, uint16_t size) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1)); + //*reg = (size >> 8) & 0xf; + uint8_t reg = (ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+(EPn << 1))); + +// A_PRINTF("=>mUsbEPMxPtSzHigh: write: %02x to %02x (0x%08x)\n\r", ((size >> 8) & 0xff), reg, USB_WORD_REG_READ(reg)); + USB_BYTE_REG_WRITE(reg, ((size >> 8) & 0xff)); + +// A_PRINTF("<=mUsbEPMxPtSzHigh: write: %02x to %02x (0x%08x)\n\r", ((size >> 8) & 0xff), reg, USB_WORD_REG_READ(reg)); + //USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1)), ((size >> 8) & 0xf)); +} + +void mUsbEPMxPtSzLow(uint8_t EPn, uint8_t dir, uint16_t size) +{ + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+EPn << 1)); + //*reg = (size & 0xff); + + uint8_t reg = (ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+(EPn << 1))); +// A_PRINTF("=>mUsbEPMxPtSzLow: write: %02x to %02x (0x%08x)\n\r", (size & 0xff), reg, USB_WORD_REG_READ(reg)); + USB_BYTE_REG_WRITE(reg, (size & 0xff)); + +// A_PRINTF("<=mUsbEPMxPtSzLow: write: %02x to %02x (0x%08x)\n\r", (size & 0xff), reg, USB_WORD_REG_READ(reg)); +} + +void mUsbEPinHighBandSet(uint8_t EPn, uint8_t dir, uint16_t size) +{ +#if 1 + //uint8_t* reg = (uint8_t*) (ZM_FUSB_BASE+ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)); + + //*reg &= ~(BIT6 | BIT5); + //*reg |= (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir)); + + uint8_t reg = (ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)); +// uint8_t reg2 = (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir)); + uint8_t reg2 = (((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir)); + +// A_PRINTF("=>mUsbEPinHighBandSet(%d)(size:%d)(dir:%d): write: %02x to %02x (0x%08x)\n\r", EPn, size, dir, (USB_BYTE_REG_READ(reg)|reg2), reg, USB_WORD_REG_READ(reg)); + USB_BYTE_REG_WRITE(reg, (USB_BYTE_REG_READ(reg)&~(BIT6 | BIT5))); + USB_BYTE_REG_WRITE(reg, (USB_BYTE_REG_READ(reg)|reg2)); + +// A_PRINTF("=>mUsbEPinHighBandSet(%d)(size:%d)(dir:%d): write: %02x to %02x (0x%08x)\n\r", EPn, size, dir, (USB_BYTE_REG_READ(reg)|reg2), reg, USB_WORD_REG_READ(reg)); +#endif +} + +#else + +#define mUsbEPMap( EPn, MAP) USB_BYTE_REG_WRITE( (0x30+(EPn-1)), MAP ) + +#define mUsbFIFOMap( FIFOn, MAP) USB_BYTE_REG_WRITE( (0x80+FIFOn), MAP ) + +#define mUsbFIFOConfig(FIFOn, cfg) USB_BYTE_REG_WRITE( (0x90+FIFOn), cfg ) + +#define mUsbEPMxPtSzHigh(EPn, dir, size) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(((dir) * 0x20)+EPn << 1)), ((size >> 8) & 0xf)) + +#define mUsbEPMxPtSzLow(EPn, dir, size) USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_LOW_OFFSET+(((dir) * 0x20)+EPn << 1)), (size & 0xff)) + +#define mUsbEPinHighBandSet( EPn, dir, size) \ +{ \ + USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)), \ + (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1))&(~(BIT6 | BIT5))))); \ + USB_BYTE_REG_WRITE((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)), \ + (USB_BYTE_REG_READ((ZM_EP_IN_MAX_SIZE_HIGH_OFFSET+(EPn << 1)|((uint8_t)((size) >> 11) + 1) << 5) * (1 - (dir))))); \ +} + +#endif + +///////////////////////////////////////////////////// +// vUsbFIFO_EPxCfg_HS(void) +// Description: +// 1. Configure the FIFO and EPx map +// input: none +// output: none +///////////////////////////////////////////////////// +void vUsbFIFO_EPxCfg_HS(void) +{ + + int i; + + switch (u8UsbConfigValue) + { + #if (HS_CONFIGURATION_NUMBER >= 1) + // Configuration 0X01 + case 0X01: + switch (u8UsbInterfaceValue) + { + #if (HS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + case 0: + switch (u8UsbInterfaceAlternateSetting) + { + #if (HS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0 + case 0: + #if (HS_C1_I0_A0_EP_NUMBER >= 1) + //EP0X01 + mUsbEPMap(EP1, HS_C1_I0_A0_EP1_MAP); + mUsbFIFOMap(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_MAP); + + mUsbFIFOMap(HS_C1_I0_A0_EP1_FIFO_START+1, HS_C1_I0_A0_EP1_FIFO_MAP); //ryan + + mUsbFIFOConfig(HS_C1_I0_A0_EP1_FIFO_START, HS_C1_I0_A0_EP1_FIFO_CONFIG); + + for(i = HS_C1_I0_A0_EP1_FIFO_START + 1 ; + i < HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO ; + i ++) + { + mUsbFIFOConfig(i, (HS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP1, HS_C1_I0_A0_EP1_DIRECTION, (HS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff) ); + mUsbEPMxPtSzLow(EP1, HS_C1_I0_A0_EP1_DIRECTION, (HS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff) ); + mUsbEPinHighBandSet(EP1 , HS_C1_I0_A0_EP1_DIRECTION , HS_C1_I0_A0_EP1_MAX_PACKET); + + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 2) + //EP0X02 + mUsbEPMap(EP2, HS_C1_I0_A0_EP2_MAP); + mUsbFIFOMap(HS_C1_I0_A0_EP2_FIFO_START, HS_C1_I0_A0_EP2_FIFO_MAP); + + mUsbFIFOMap(HS_C1_I0_A0_EP2_FIFO_START+1, HS_C1_I0_A0_EP2_FIFO_MAP);//ryan + + mUsbFIFOConfig(HS_C1_I0_A0_EP2_FIFO_START, HS_C1_I0_A0_EP2_FIFO_CONFIG); + + for(i = HS_C1_I0_A0_EP2_FIFO_START + 1 ; + i < HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO ; + i ++) + { + mUsbFIFOConfig(i, (HS_C1_I0_A0_EP2_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP2, HS_C1_I0_A0_EP2_DIRECTION, (HS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff) ); + mUsbEPMxPtSzLow(EP2, HS_C1_I0_A0_EP2_DIRECTION, (HS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff) ); + mUsbEPinHighBandSet(EP2 , HS_C1_I0_A0_EP2_DIRECTION , HS_C1_I0_A0_EP2_MAX_PACKET); + + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 3) + //EP0X03 + mUsbEPMap(EP3, HS_C1_I0_A0_EP3_MAP); + mUsbFIFOMap(HS_C1_I0_A0_EP3_FIFO_START, HS_C1_I0_A0_EP3_FIFO_MAP); + mUsbFIFOConfig(HS_C1_I0_A0_EP3_FIFO_START, HS_C1_I0_A0_EP3_FIFO_CONFIG); + + for(i = HS_C1_I0_A0_EP3_FIFO_START + 1 ; + i < HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO ; + i ++) + { + mUsbFIFOConfig(i, (HS_C1_I0_A0_EP3_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP3, HS_C1_I0_A0_EP3_DIRECTION, (HS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff) ); + mUsbEPMxPtSzLow(EP3, HS_C1_I0_A0_EP3_DIRECTION, (HS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff) ); + mUsbEPinHighBandSet(EP3 , HS_C1_I0_A0_EP3_DIRECTION , HS_C1_I0_A0_EP3_MAX_PACKET); + + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + //EP0X04 + mUsbEPMap(EP4, HS_C1_I0_A0_EP4_MAP); + mUsbFIFOMap(HS_C1_I0_A0_EP4_FIFO_START, HS_C1_I0_A0_EP4_FIFO_MAP); + mUsbFIFOConfig(HS_C1_I0_A0_EP4_FIFO_START, HS_C1_I0_A0_EP4_FIFO_CONFIG); + + for(i = HS_C1_I0_A0_EP4_FIFO_START + 1 ; + i < HS_C1_I0_A0_EP4_FIFO_START + HS_C1_I0_A0_EP4_FIFO_NO ; + i ++) + { + mUsbFIFOConfig(i, (HS_C1_I0_A0_EP4_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP4, HS_C1_I0_A0_EP4_DIRECTION, (HS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff) ); + mUsbEPMxPtSzLow(EP4, HS_C1_I0_A0_EP4_DIRECTION, (HS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff) ); + mUsbEPinHighBandSet(EP4 , HS_C1_I0_A0_EP4_DIRECTION , HS_C1_I0_A0_EP4_MAX_PACKET); + + #endif +////////////////////////////////////////////////////////////// +#if SYSTEM_MODULE_HP_EP5 + #if (HS_C1_I0_A0_EP_NUMBER >= 5) + //EP0X05 + mUsbEPMap(EP5, HS_C1_I0_A0_EP5_MAP); + mUsbFIFOMap(HS_C1_I0_A0_EP5_FIFO_START, HS_C1_I0_A0_EP5_FIFO_MAP); + + mUsbFIFOMap(HS_C1_I0_A0_EP5_FIFO_START+1, HS_C1_I0_A0_EP5_FIFO_MAP); //ryan + + mUsbFIFOConfig(HS_C1_I0_A0_EP5_FIFO_START, HS_C1_I0_A0_EP5_FIFO_CONFIG); + + for(i = HS_C1_I0_A0_EP5_FIFO_START + 1 ; + i < HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO ; + i ++) + { + mUsbFIFOConfig(i, (HS_C1_I0_A0_EP5_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP5, HS_C1_I0_A0_EP5_DIRECTION, (HS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff) ); + mUsbEPMxPtSzLow(EP5, HS_C1_I0_A0_EP5_DIRECTION, (HS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff) ); + mUsbEPinHighBandSet(EP5 , HS_C1_I0_A0_EP5_DIRECTION , HS_C1_I0_A0_EP5_MAX_PACKET); + #endif +#endif //SYSTEM_MODULE_HP_EP5 + +////////////////////////////////////////////////////////////// +#if SYSTEM_MODULE_HP_EP6 + #if (HS_C1_I0_A0_EP_NUMBER >= 6) + //EP0X06 + mUsbEPMap(EP6, HS_C1_I0_A0_EP6_MAP); + mUsbFIFOMap(HS_C1_I0_A0_EP6_FIFO_START, HS_C1_I0_A0_EP6_FIFO_MAP); + + mUsbFIFOMap(HS_C1_I0_A0_EP6_FIFO_START+1, HS_C1_I0_A0_EP6_FIFO_MAP); //ryan + + mUsbFIFOConfig(HS_C1_I0_A0_EP6_FIFO_START, HS_C1_I0_A0_EP6_FIFO_CONFIG); + + for(i = HS_C1_I0_A0_EP6_FIFO_START + 1 ; + i < HS_C1_I0_A0_EP6_FIFO_START + HS_C1_I0_A0_EP6_FIFO_NO ; + i ++) + { + mUsbFIFOConfig(i, (HS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP6, HS_C1_I0_A0_EP6_DIRECTION, (HS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff) ); + mUsbEPMxPtSzLow(EP6, HS_C1_I0_A0_EP6_DIRECTION, (HS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff) ); + mUsbEPinHighBandSet(EP6 , HS_C1_I0_A0_EP6_DIRECTION , HS_C1_I0_A0_EP6_MAX_PACKET); + #endif + break; +#endif //SYSTEM_MODULE_HP_EP6 + + #endif + default: + break; + } + break; + #endif + default: + break; + } + break; + #endif + default: + break; + } + //mCHECK_STACK(); + +} + +void vUsbFIFO_EPxCfg_FS(void) +{ + +int i; + + switch (u8UsbConfigValue) + { + #if (FS_CONFIGURATION_NUMBER >= 1) + // Configuration 0X01 + case 0X01: + switch (u8UsbInterfaceValue) + { + #if (FS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + case 0: + switch (u8UsbInterfaceAlternateSetting) + { + #if (FS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0 + case 0: + #if (FS_C1_I0_A0_EP_NUMBER >= 1) + //EP0X01 + mUsbEPMap(EP1, FS_C1_I0_A0_EP1_MAP); + mUsbFIFOMap(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_MAP); + mUsbFIFOConfig(FS_C1_I0_A0_EP1_FIFO_START, FS_C1_I0_A0_EP1_FIFO_CONFIG); + + for(i = FS_C1_I0_A0_EP1_FIFO_START + 1 ; + i < FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO ; + i ++) + { + mUsbFIFOConfig(i, (FS_C1_I0_A0_EP1_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP1, FS_C1_I0_A0_EP1_DIRECTION, (FS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff)); + mUsbEPMxPtSzLow(EP1, FS_C1_I0_A0_EP1_DIRECTION, (FS_C1_I0_A0_EP1_MAX_PACKET & 0x7ff)); + //``.JWEI 2003/04/29 + mUsbEPinHighBandSet(EP1 , FS_C1_I0_A0_EP1_DIRECTION, FS_C1_I0_A0_EP1_MAX_PACKET); + + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 2) + //EP0X02 + mUsbEPMap(EP2, FS_C1_I0_A0_EP2_MAP); + mUsbFIFOMap(FS_C1_I0_A0_EP2_FIFO_START, FS_C1_I0_A0_EP2_FIFO_MAP); + mUsbFIFOConfig(FS_C1_I0_A0_EP2_FIFO_START, FS_C1_I0_A0_EP2_FIFO_CONFIG); + + for(i = FS_C1_I0_A0_EP2_FIFO_START + 1 ; + i < FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO ; + i ++) + { + mUsbFIFOConfig(i, (FS_C1_I0_A0_EP2_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP2, FS_C1_I0_A0_EP2_DIRECTION, (FS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff)); + mUsbEPMxPtSzLow(EP2, FS_C1_I0_A0_EP2_DIRECTION, (FS_C1_I0_A0_EP2_MAX_PACKET & 0x7ff)); + mUsbEPinHighBandSet(EP2 , FS_C1_I0_A0_EP2_DIRECTION, FS_C1_I0_A0_EP2_MAX_PACKET); + + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 3) + //EP0X03 + mUsbEPMap(EP3, FS_C1_I0_A0_EP3_MAP); + mUsbFIFOMap(FS_C1_I0_A0_EP3_FIFO_START, FS_C1_I0_A0_EP3_FIFO_MAP); + mUsbFIFOConfig(FS_C1_I0_A0_EP3_FIFO_START, FS_C1_I0_A0_EP3_FIFO_CONFIG); + + for(i = FS_C1_I0_A0_EP3_FIFO_START + 1 ; + i < FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO ; + i ++) + { + mUsbFIFOConfig(i, (FS_C1_I0_A0_EP3_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP3, FS_C1_I0_A0_EP3_DIRECTION, (FS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff)); + mUsbEPMxPtSzLow(EP3, FS_C1_I0_A0_EP3_DIRECTION, (FS_C1_I0_A0_EP3_MAX_PACKET & 0x7ff)); + mUsbEPinHighBandSet(EP3 , FS_C1_I0_A0_EP3_DIRECTION, FS_C1_I0_A0_EP3_MAX_PACKET); + + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + //EP0X04 + mUsbEPMap(EP4, FS_C1_I0_A0_EP4_MAP); + mUsbFIFOMap(FS_C1_I0_A0_EP4_FIFO_START, FS_C1_I0_A0_EP4_FIFO_MAP); + mUsbFIFOConfig(FS_C1_I0_A0_EP4_FIFO_START, FS_C1_I0_A0_EP4_FIFO_CONFIG); + + for(i = FS_C1_I0_A0_EP4_FIFO_START + 1 ; + i < FS_C1_I0_A0_EP4_FIFO_START + FS_C1_I0_A0_EP4_FIFO_NO ; + i ++) + { + mUsbFIFOConfig(i, (FS_C1_I0_A0_EP4_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP4, FS_C1_I0_A0_EP4_DIRECTION, (FS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff)); + mUsbEPMxPtSzLow(EP4, FS_C1_I0_A0_EP4_DIRECTION, (FS_C1_I0_A0_EP4_MAX_PACKET & 0x7ff)); + mUsbEPinHighBandSet(EP4 , FS_C1_I0_A0_EP4_DIRECTION, FS_C1_I0_A0_EP4_MAX_PACKET); + + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 5) + //EP0X05 + mUsbEPMap(EP5, FS_C1_I0_A0_EP5_MAP); + mUsbFIFOMap(FS_C1_I0_A0_EP5_FIFO_START, FS_C1_I0_A0_EP5_FIFO_MAP); + mUsbFIFOConfig(FS_C1_I0_A0_EP5_FIFO_START, FS_C1_I0_A0_EP5_FIFO_CONFIG); + + for(i = FS_C1_I0_A0_EP5_FIFO_START + 1 ; + i < FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO ; + i ++) + { + mUsbFIFOConfig(i, (FS_C1_I0_A0_EP5_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP5, FS_C1_I0_A0_EP5_DIRECTION, (FS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff)); + mUsbEPMxPtSzLow(EP5, FS_C1_I0_A0_EP5_DIRECTION, (FS_C1_I0_A0_EP5_MAX_PACKET & 0x7ff)); + mUsbEPinHighBandSet(EP5 , FS_C1_I0_A0_EP5_DIRECTION, FS_C1_I0_A0_EP5_MAX_PACKET); + #endif + break; + #endif + default: + break; + } + break; + #endif + default: + break; + } + break; + #endif + default: + break; + } + //mCHECK_STACK(); +} + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_pre.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_pre.h new file mode 100755 index 0000000..b63e3a9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_pre.h @@ -0,0 +1,99 @@ +#ifndef __USB_USER_PRE_H +#define __USB_USER_PRE_H + +#define FUSB200_MAX_EP 10 // 1..10 +#define FUSB200_MAX_FIFO 10 // 0.. 9 +#define EP0MAXPACKETSIZE 0x40 +// #define EP0FIFOSIZE 64 // EP0_FIFO +//JWEI 2003/04/29 +//#define EP0MAXPACKETSIZE 0x08 + +// Max. Packet Size define +#define MX_PA_SZ_8 8 +#define MX_PA_SZ_16 16 +#define MX_PA_SZ_32 32 +#define MX_PA_SZ_64 64 +#define MX_PA_SZ_128 128 +#define MX_PA_SZ_256 256 +#define MX_PA_SZ_512 512 +#define MX_PA_SZ_1024 1024 + +#define MASK_F0 0xF0 + +// Block Size define +#define BLK512BYTE 1 +#define BLK1024BYTE 2 + +#define BLK64BYTE 1 +#define BLK128BYTE 2 + +// Block toggle number define +#define SINGLE_BLK 1 +#define DOUBLE_BLK 2 +#define TRIBLE_BLK 3 + +// Endpoint transfer type +#define TF_TYPE_ISOCHRONOUS 1 +#define TF_TYPE_BULK 2 +#define TF_TYPE_INTERRUPT 3 + +// Endpoint or FIFO direction define +#define DIRECTION_IN 0 +#define DIRECTION_OUT 1 + +// FIFO number define +#define FIFO0 0x0 +#define FIFO1 0x1 +#define FIFO2 0x2 +#define FIFO3 0x3 +#define FIFO4 0x4 +#define FIFO5 0x5 +#define FIFO6 0x6 +#define FIFO7 0x7 +#define FIFO8 0x8 +#define FIFO9 0x9 +#define FIFO10 10 +#define FIFO11 11 +#define FIFO12 12 +#define FIFO13 13 +#define FIFO14 14 +#define FIFO15 15 + +// Descriptor Table uses the following parameters : fixed +#define DEVICE_LENGTH 0x12 +#define CONFIG_LENGTH 0x09 +#define INTERFACE_LENGTH 0x09 +#define EP_LENGTH 0x07 +#define DEVICE_QUALIFIER_LENGTH 0x0A + +//JWEI 2003/04/29 +// Endpoint number define +#define EP0 0 +#define EP1 1 +#define EP2 2 +#define EP3 3 +#define EP4 4 +#define EP5 5 +#define EP6 6 +#define EP7 7 +#define EP8 8 +#define EP9 9 +#define EP10 10 +#define EP11 11 +#define EP12 12 +#define EP13 13 +#define EP14 14 +#define EP15 15 + +#define STRING_00_LENGTH 0x04 +#define STRING_10_LENGTH 0x0c +#define STRING_20_LENGTH 0x18 +#define STRING_30_LENGTH 0x18 +#define STRING_40_LENGTH 0x04 +#define STRING_50_LENGTH 0x04 +#define STRING_60_LENGTH 0x04 +#define STRING_70_LENGTH 0x04 +#define STRING_80_LENGTH 0x04 +#define STRING_90_LENGTH 0x00 + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_std.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_std.h new file mode 100755 index 0000000..7272eaf --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_std.h @@ -0,0 +1,106 @@ +#ifndef USB_STD_H +#define USB_STD_H + +#define mDEV_REQ_REQ_DIR() (ControlCmd.Direction) +#define mDEV_REQ_REQ_TYPE() (ControlCmd.Type) +#define mDEV_REQ_REQ_RECI() (ControlCmd.Object) +#define mDEV_REQ_REQ() (ControlCmd.Request) +#define mDEV_REQ_VALUE() (ControlCmd.Value) +#define mDEV_REQ_VALUE_LOW() (mLOW_BYTE(mDEV_REQ_VALUE())) +#define mDEV_REQ_VALUE_HIGH() (mHIGH_BYTE(mDEV_REQ_VALUE())) +#define mDEV_REQ_INDEX() (ControlCmd.Index) +#define mDEV_REQ_LENGTH() (ControlCmd.Length) + +/******************** USB Protocol Definition *************************/ +/* Standard Request Code (Table 9-4) */ +#define USB_GET_STATUS 0 +#define USB_CLEAR_FEATURE 1 +#define USB_SET_FEATURE 3 +#define USB_SET_ADDRESS 5 +#define USB_GET_DESCRIPTOR 6 +#define USB_SET_DESCRIPTOR 7 +#define USB_GET_CONFIGURATION 8 +#define USB_SET_CONFIGURATION 9 +#define USB_GET_INTERFACE 10 +#define USB_SET_INTERFACE 11 +#define USB_SYNCH_FRAME 12 + +/* Descriptor Type (Table 9-5) */ +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIG 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 + +/* Endpoint Attribute (Table 9-10) */ +#define USB_EP_ATTR_CTRL 0 +#define USB_EP_ATTR_ISOCH 1 +#define USB_EP_ATTR_BULK 2 +#define USB_EP_ATTR_INTRPT 3 + +/*********************** for USB 2.0 **********************************/ +// Table 9-5. Descriptor Types +#define DT_DEVICE 1 +#define DT_CONFIGURATION 2 +#define DT_STRING 3 +#define DT_INTERFACE 4 +#define DT_ENDPOINT 5 +#define DT_DEVICE_QUALIFIER 6 +#define DT_OTHER_SPEED_CONFIGURATION 7 +#define DT_INTERFACE_POWER 8 + +/**********************************************************************/ +// Values for bmAttributes Field in USB_CONFIGURATION_DESCRIPTOR +#define USB_BUS_POWERED 0x80 +#define USB_SELF_POWERED 0x40 +#define USB_REMOTE_WAKEUP 0x20 + +#define cUSB_REQTYPE_DIR_POS 7 +#define cUSB_REQTYPE_DIR_LEN 1 +#define cUSB_REQTYPE_TYPE_POS 5 +#define cUSB_REQTYPE_TYPE_LEN 2 +#define cUSB_REQTYPE_RX_POS 0 +#define cUSB_REQTYPE_RX_LEN 5 + +/* for USB State */ +#define cUSB_DEFAULT_STATE 0 +#define cUSB_ADDRESS_STATE 1 +#define cUSB_CONFIG_STATE 2 + +/* for Data transfer direction */ +#define bmUSB_HOST_DIR 7 /* Bit 7 */ +#define cUSB_DIR_HOST_OUT 0 +#define cUSB_DIR_HOST_IN 1 + +/* for Type */ +#define cUSB_REQTYPE_STD 0 +#define cUSB_REQTYPE_CLASS 1 +#define cUSB_REQTYPE_VENDOR 2 + +/* for Recipient */ +#define cUSB_REQTYPE_DEVICE 0 +#define cUSB_REQTYPE_INTERFACE 1 +#define cUSB_REQTYPE_ENDPOINT 2 +#define cUSB_REQTYPE_OTHER 3 + +/* for Descriptor Type */ +#define cUSB_DESTYPE_DEVICE 1 +#define cUSB_DESTYPE_CONFIG 2 +#define cUSB_DESTYPE_STRING 3 +#define cUSB_DESTYPE_INTERFACE 4 +#define cUSB_DESTYPE_ENDPOINT 5 +#define cUSB_DESTYPE_END cUSB_DESTYPE_ENDPOINT // for range check + +/* for Feature selector */ +#define cUSB_FEATSEL_RMWAKEUP 0 +#define cUSB_FEATSEL_EPHAL 1 +#define cUSB_FEATSEL_END cUSB_FEATSEL_EPHAL // for range check + +#define bmREQ_RECI 0 +#define bmwREQ_RECI 5 // mMASKS(bmwREQ_RECI, bmREQ_RECI) +#define bmREQ_TYPE 5 +#define bmwREQ_TYPE 2 // mMASKS(bmwREQ_TYPE, bmREQ_TYPE) +#define bmREQ_DIR 7 +#define bmwREQ_DIR 1 + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_table.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_table.c new file mode 100755 index 0000000..b8388a5 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_table.c @@ -0,0 +1,244 @@ +#include "usb_type.h" +#include "usb_table.h" +#include "sys_cfg.h" + +#if SYSTEM_MODULE_USB + +//#if defined(_ROM_) +//const uint16_t UsbDeviceDescriptor[] __attribute__ ((section(".dport0.usb_in_rom"))) = +//#else +uint16_t UsbDeviceDescriptor[] = +//#endif +{ + m2BYTE(USB_DEVICE_DESC_LEN, USB_DEVICE_DESC_TYPE), + USB_SPEC_VERSION, + m2BYTE(USB_DEVICE_CLASS, USB_DEVICE_SUB_CLASS), + m2BYTE(USB_DEVICE_PROTOCOL, USB_MAX_PKT_SIZE), + USB_VENDOR_ID, + USB_PRODUCT_ID, + USB_DEVICE_BCD, + m2BYTE(USB_MANUFACTURER_INDEX, USB_PRODUCT_INDEX), + m2BYTE(USB_SERIAL_INDEX, USB_CONFIGURATION_NUM) +}; + +//#if defined(_ROM_) +//const uint16_t u8HSConfigDescriptor01[] __attribute__ ((section(".dport0.usb_in_rom"))) = +//#else +uint16_t u8HSConfigDescriptor01[] = +//#endif +{ + m2BYTE(USB_CONFIG_DESC_LEN, USB_CONFIG_DESC_TYPE), + USB_TOTAL_DESC_LEN, + m2BYTE(USB_INTERFACE_NUM, USB_CONFIG_NUM), + m2BYTE(USB_STRING_INDEX, USB_ATTRIBUTE), + m2BYTE(USB_MAX_POWER, USB_INTERFACE_DESC_LEN), + m2BYTE(USB_INTERFACE_DESC_TYPE, USB_INTERFACE_INDEX_NUM), + m2BYTE(USB_INTERFACE_ALT_SETTING, USB_INTERFACE_EP_NUM), + m2BYTE(USB_INTERFACE_CLASS, USB_INTERFACE_SUB_CLASS), + m2BYTE(USB_INTERFACE_PROTOCOL, USB_INTERFACE_STRING_INDEX), + m2BYTE(USB_EP_DESC_LEN, USB_EP_DESC_TYPE), // EP 1 + m2BYTE(USB_HS_EP1_ADDRESS, USB_HS_EP1_ATTRIBUTE), + USB_HS_EP1_MAX_PACKET_SIZE, + m2BYTE(USB_HS_EP1_INTERVAL, USB_EP_DESC_LEN), // EP 2 + m2BYTE(USB_EP_DESC_TYPE, USB_HS_EP2_ADDRESS), + m2BYTE(USB_HS_EP2_ATTRIBUTE, USB_HS_EP2_MAX_PACKET_SIZE), + m2BYTE(mHIGH_BYTE(USB_HS_EP2_MAX_PACKET_SIZE), USB_HS_EP2_INTERVAL), + m2BYTE(USB_EP_DESC_LEN, USB_EP_DESC_TYPE), // EP 3 + m2BYTE(USB_HS_EP3_ADDRESS, USB_HS_EP3_ATTRIBUTE), + USB_HS_EP3_MAX_PACKET_SIZE, + m2BYTE(USB_HS_EP3_INTERVAL, USB_EP_DESC_LEN), // EP 4 + m2BYTE(USB_EP_DESC_TYPE, USB_HS_EP4_ADDRESS), + m2BYTE(USB_HS_EP4_ATTRIBUTE, USB_HS_EP4_MAX_PACKET_SIZE), + m2BYTE(mHIGH_BYTE(USB_HS_EP4_MAX_PACKET_SIZE), USB_HS_EP4_INTERVAL), + m2BYTE(USB_EP_DESC_LEN, USB_EP_DESC_TYPE), // EP 5 + m2BYTE(USB_HS_EP5_ADDRESS, USB_HS_EP5_ATTRIBUTE), + USB_HS_EP5_MAX_PACKET_SIZE, + m2BYTE(USB_HS_EP5_INTERVAL, USB_EP_DESC_LEN), // EP 6 + m2BYTE(USB_EP_DESC_TYPE, USB_HS_EP6_ADDRESS), + m2BYTE(USB_HS_EP6_ATTRIBUTE, USB_HS_EP6_MAX_PACKET_SIZE), + m2BYTE(mHIGH_BYTE(USB_HS_EP6_MAX_PACKET_SIZE), USB_HS_EP6_INTERVAL) +}; + + +//#if defined(_ROM_) +//const uint16_t u8FSConfigDescriptor01[] __attribute__ ((section(".dport0.usb_in_rom"))) = +//#else +uint16_t u8FSConfigDescriptor01[] = +//#endif +{ + m2BYTE(USB_CONFIG_DESC_LEN, USB_CONFIG_DESC_TYPE), + USB_TOTAL_DESC_LEN, + m2BYTE(USB_INTERFACE_NUM, USB_CONFIG_NUM), + m2BYTE(USB_STRING_INDEX, USB_ATTRIBUTE), + m2BYTE(USB_MAX_POWER, USB_INTERFACE_DESC_LEN), + m2BYTE(USB_INTERFACE_DESC_TYPE, USB_INTERFACE_INDEX_NUM), + m2BYTE(USB_INTERFACE_ALT_SETTING, USB_INTERFACE_EP_NUM), + m2BYTE(USB_INTERFACE_CLASS, USB_INTERFACE_SUB_CLASS), + m2BYTE(USB_INTERFACE_PROTOCOL, USB_INTERFACE_STRING_INDEX), + m2BYTE(USB_EP_DESC_LEN, USB_EP_DESC_TYPE), // EP 1 + m2BYTE(USB_FS_EP1_ADDRESS, USB_FS_EP1_ATTRIBUTE), + USB_FS_EP1_MAX_PACKET_SIZE, + m2BYTE(USB_FS_EP1_INTERVAL, USB_EP_DESC_LEN), // EP 2 + m2BYTE(USB_EP_DESC_TYPE, USB_FS_EP2_ADDRESS), + m2BYTE(USB_FS_EP2_ATTRIBUTE, USB_FS_EP2_MAX_PACKET_SIZE), + m2BYTE(mHIGH_BYTE(USB_FS_EP2_MAX_PACKET_SIZE), USB_FS_EP2_INTERVAL), + m2BYTE(USB_EP_DESC_LEN, USB_EP_DESC_TYPE), // EP 3 + m2BYTE(USB_FS_EP3_ADDRESS, USB_FS_EP3_ATTRIBUTE), + USB_FS_EP3_MAX_PACKET_SIZE, + m2BYTE(USB_FS_EP3_INTERVAL, USB_EP_DESC_LEN), // EP 4 + m2BYTE(USB_EP_DESC_TYPE, USB_FS_EP4_ADDRESS), + m2BYTE(USB_FS_EP4_ATTRIBUTE, USB_FS_EP4_MAX_PACKET_SIZE), + m2BYTE(mHIGH_BYTE(USB_FS_EP4_MAX_PACKET_SIZE), USB_FS_EP4_INTERVAL), + m2BYTE(USB_EP_DESC_LEN, USB_EP_DESC_TYPE), // EP 5 + m2BYTE(USB_FS_EP5_ADDRESS, USB_FS_EP5_ATTRIBUTE), + USB_FS_EP5_MAX_PACKET_SIZE, + m2BYTE(USB_FS_EP5_INTERVAL, USB_EP_DESC_LEN), // EP 6 + m2BYTE(USB_EP_DESC_TYPE, USB_FS_EP6_ADDRESS), + m2BYTE(USB_FS_EP6_ATTRIBUTE, USB_FS_EP6_MAX_PACKET_SIZE), + m2BYTE(mHIGH_BYTE(USB_FS_EP6_MAX_PACKET_SIZE), USB_FS_EP6_INTERVAL) +}; + +uint16_t u8DeviceQualifierDescriptorEX[] = +{ + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000 +}; + +uint16_t u8OtherSpeedConfigDescriptorEX[] = +{ + 0x0709, // 0 + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, // 5 + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, // 10 + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, // 15 + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, // 20 + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, // 25 + 0x0000, + 0x0000, + 0x0000, + 0x0000 +}; + +//#if defined(_ROM_) +//const uint16_t String00Descriptor[] __attribute__ ((section(".dport0.usb_in_rom"))) = +//#else +uint16_t String00Descriptor[] = +//#endif +{ + 0x0304, + 0x0409 +}; + +//#if defined(_ROM_) +//const uint16_t String10Descriptor[] __attribute__ ((section(".dport0.usb_in_rom"))) = +//#else +uint16_t String10Descriptor[] = +//#endif +{ + 0x0360, //length + 0x0041, //A + 0x0054, //T + 0x0048, //H + 0x0045, //E + 0x0052, //R + 0x004f, //O + 0x0053, //S + 0x002c, //, + 0x0041, //A + 0x0054, //T + 0x0048, //H + 0x0045, //E + 0x0052, //R + 0x004f, //O + 0x0053, //S + 0x002c, //, + 0x0041, //A + 0x0054, //T + 0x0048, //H + 0x0045, //E + 0x0052, //R + 0x004f, //O + 0x0053, //S + 0x002c, //, + 0x0041, //A + 0x0054, //T + 0x0048, //H + 0x0045, //E + 0x0052, //R + 0x004f, //O + 0x0053, //S + 0x002c, //, + 0x0041, //A + 0x0054, //T + 0x0048, //H + 0x0045, //E + 0x0052, //R + 0x004f, //O + 0x0053, //S + 0x002c, //, + 0x0041, //A + 0x0054, //T + 0x0048, //H + 0x0045, //E + 0x0052, //R + 0x004f, //O + 0x0053, //S +}; + +//#if defined(_ROM_) +//const uint16_t String20Descriptor[] __attribute__ ((section(".dport0.usb_in_rom"))) = +//#else +uint16_t String20Descriptor[] = +//#endif +{ + 0x0318, //length + 0x0055, //'U' + 0x0053, //'S' + 0x0042, //'B' + 0x0032, //'2' + 0x002E, //'.' + 0x0030, //'0' + 0x0020, //' ' + 0x0057, //'W' + 0x004C, //'L' + 0x0041, //'A' + 0x004E, //'N' +}; + +//#if defined(_ROM_) +//const uint16_t String30Descriptor[] __attribute__ ((section(".dport0.usb_in_rom"))) = +//#else +uint16_t String30Descriptor[] = +//#endif +{ + 0x030c, //length + 0x0031, //;'1' + 0x0032, //;'2' + 0x0033, //;'3' + 0x0034, //;'4' + 0x0035, //;'5' +}; + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_table.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_table.h new file mode 100755 index 0000000..31fe7e4 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_table.h @@ -0,0 +1,131 @@ +#ifndef _USB_TABLE_H_ +#define _USB_TABLE_H_ + +// UsbDeviceDescriptor +#define USB_DEVICE_DESC_TYPE 0x01 +#define USB_DEVICE_DESC_LEN 0x12 +#define USB_SPEC_VERSION 0x0200 +#define USB_DEVICE_CLASS 0xFF +#define USB_DEVICE_SUB_CLASS 0xFF +#define USB_DEVICE_PROTOCOL 0xFF +#define USB_MAX_PKT_SIZE 0x40 +#define USB_VENDOR_ID 0x0CF3 +#define USB_PRODUCT_ID 0x7010 +#define USB_DEVICE_BCD BOOTROM_VER +#define USB_MANUFACTURER_INDEX 0x10 +#define USB_PRODUCT_INDEX 0x20 +#define USB_SERIAL_INDEX 0x30 +#define USB_CONFIGURATION_NUM 0x01 +// end UsbDeviceDescriptor + +#define USB_CONFIG_DESC_TYPE 0x02 +#define USB_CONFIG_DESC_LEN 0x09 +//#define USB_TOTAL_DESC_LEN 0x002E // 4 ep +//#define USB_TOTAL_DESC_LEN 0x0035 // 5 ep +#define USB_TOTAL_DESC_LEN 0x003C // 6 ep +#define USB_INTERFACE_NUM 0x01 +#define USB_CONFIG_NUM 0x01 +#define USB_STRING_INDEX 0x00 +#define USB_ATTRIBUTE 0x80 +#define USB_MAX_POWER 0xFA + +#define USB_INTERFACE_DESC_TYPE 0x04 +#define USB_INTERFACE_DESC_LEN 0x09 +#define USB_INTERFACE_INDEX_NUM 0x00 +#define USB_INTERFACE_ALT_SETTING 0x00 +//#define USB_INTERFACE_EP_NUM 0x04 +//#define USB_INTERFACE_EP_NUM 0x05 +#define USB_INTERFACE_EP_NUM 0x06 +#define USB_INTERFACE_CLASS 0xFF +#define USB_INTERFACE_SUB_CLASS 0x00 +#define USB_INTERFACE_PROTOCOL 0x00 +#define USB_INTERFACE_STRING_INDEX 0x00 + +#define USB_EP_DESC_TYPE 0x05 +#define USB_EP_DESC_LEN 0x07 + +/* USB Endpoint attribute */ +#define bUSB_EP1_NUM 0x01 +#define bUSB_EP2_NUM 0x02 +#define bUSB_EP3_NUM 0x03 +#define bUSB_EP4_NUM 0x04 +#define bUSB_EP5_NUM 0x05 +#define bUSB_EP6_NUM 0x06 + +#define bUSB_EP_DIRECTION_IN 0x80 +#define bUSB_EP_DIRECTION_OUT 0x00 + +#define bUSB_EP_TYPE_CONTROL 0x00 +#define bUSB_EP_TYPE_ISOCHRONOUS 0x01 +#define bUSB_EP_TYPE_BULK 0x02 +#define bUSB_EP_TYPE_INTERRUPT 0x03 + +#define bUSB_EP_MAX_PKT_SIZE_64 0x0040 +#define bUSB_EP_MAX_PKT_SIZE_512 0x0200 + +/* High Speed Endpoint */ +#define USB_HS_EP1_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP1_NUM) +#define USB_HS_EP1_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP1_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP1_INTERVAL 0x00 + +#define USB_HS_EP2_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP2_NUM) +#define USB_HS_EP2_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP2_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP2_INTERVAL 0x00 + +#define USB_HS_EP3_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP3_NUM) +#define USB_HS_EP3_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT +#define USB_HS_EP3_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_HS_EP3_INTERVAL 0x01 + +#define USB_HS_EP4_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP4_NUM) +#define USB_HS_EP4_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT //bUSB_EP_TYPE_BULK +#define USB_HS_EP4_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_HS_EP4_INTERVAL 0x01 //0x00 + +#define USB_HS_EP5_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP5_NUM) +#define USB_HS_EP5_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP5_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP5_INTERVAL 0x00 + +#define USB_HS_EP6_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP6_NUM) +#define USB_HS_EP6_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP6_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP6_INTERVAL 0x00 + +/* Full Speed Endpoint */ +#define USB_FS_EP1_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP1_NUM) +#define USB_FS_EP1_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP1_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP1_INTERVAL 0x00 + +#define USB_FS_EP2_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP2_NUM) +#define USB_FS_EP2_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP2_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP2_INTERVAL 0x00 + +#define USB_FS_EP3_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP3_NUM) +#define USB_FS_EP3_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT +#define USB_FS_EP3_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP3_INTERVAL 0x01 + +#define USB_FS_EP4_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP4_NUM) +#define USB_FS_EP4_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP4_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP4_INTERVAL 0x00 + +#define USB_FS_EP5_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP5_NUM) +#define USB_FS_EP5_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP5_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP5_INTERVAL 0x00 + +#define USB_FS_EP6_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP6_NUM) +#define USB_FS_EP6_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP6_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP6_INTERVAL 0x00 + +//#define USB_QUALIFIER_DESC_ADDR 0x8cff00 +//#define USB_OTHER_SPEED_DESC_ADDR 0x8cffA + +#endif // end of _USB_TABLE_H_ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_type.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_type.h new file mode 100755 index 0000000..7e31478 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/hif/usb/src/usb_type.h @@ -0,0 +1,60 @@ +#ifndef USB_TYPE_H +#define USB_TYPE_H + +#include "dt_defs.h" + +/*********************** for Faraday USB controller *******************/ +typedef enum +{ + CMD_VOID, // No command + CMD_GET_DESCRIPTOR, // Get_Descriptor command + CMD_SET_DESCRIPTOR // Set_Descriptor command +} CommandType; + +typedef enum +{ + ACT_IDLE, + ACT_DONE, + ACT_STALL +} Action; + +typedef struct Setup_Packet +{ + uint8_t Direction; /* Data transfer direction: IN, OUT */ + uint8_t Type; /* Request Type: Standard, Class, Vendor */ + uint8_t Object; /* Recipient: Device, Interface, Endpoint,other */ + uint16_t Request; /* Refer to Table 9-3 */ + uint16_t Value; + uint16_t Index; + uint16_t Length; +} SetupPacket; + +#define mBIT(b) (1 << (b)) +#define mMASK(w) (mBIT(w) - 1) + +#define mWORD_IDX(bsize) ((bsize) >> 1) +#define mWORD_SIZE(bsize) (((bsize) + 1) >> 1) + +#define mTABLE_WID mWORD_SIZE +#define mTABLE_IDX mWORD_IDX +#define mTABLE_LEN mLOW_BYTE + +#define mLOW_MASK(u16) ((uint8_t) ((u16) & mMASK(8))) +#define mHIGH_MASK(u16) ((uint8_t) ((u16) & ~mMASK(8))) +#define mLOW2HIGH(u16) (((uint8_t) (u16)) << 8) + +/* (1234) -> 0034 */ +//#define mLOW_BYTE(u16) ((U_8)(u16)) +#define mLOW_BYTE(u16) mLOW_MASK(u16) +/* (1234) -> 0012 */ +#define mHIGH_BYTE(u16) ((uint8_t) (((uint16_t) (u16)) >> 8)) + +#define mGET_REG1(var0, reg0) { var0 = reg0; } + +/* (1234, 5678) -> 7834 */ +#define m2BYTE(ch1L, ch2H) (mLOW_MASK(ch1L) | mLOW2HIGH(ch2H)) + +#define mREAD_WORD(var0, reg0, reg1) \ + { var0 = reg0; var0 += mLOW2HIGH(reg1); } + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/Makefile new file mode 100755 index 0000000..57358cb --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/Makefile @@ -0,0 +1,60 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export SSNAME = htc + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libhtc.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/Makefile.ss new file mode 100755 index 0000000..4406726 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/htc.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/inc/htc_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/inc/htc_api.h new file mode 100755 index 0000000..ac053c0 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/inc/htc_api.h @@ -0,0 +1,126 @@ +/* + * @File: htc_api.h + * + * @Abstract: host-target communications API + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef __HTC_API_H__ +#define __HTC_API_H__ + +#include +#include +//#include +//#include +#include +#include + +#define HTC_HDR_SZ HTC_HDR_LENGTH +#define HTC_BUFSZ_MAX_SEND 2048 + +typedef void (* HTC_SERVICE_ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx); +typedef void (* HTC_SERVICE_ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx); + +/* HTC service structure : + * the caller is required to allocate storage for the service structure and register the + * structure using HTC_RegisterService() The service must set the following fields: + * ProcessRecvMsg + * ProcessSendBufferComplete + * ProcessConnect + * ServiceID + * MaxSvcMsgSize (for message validation) + * */ +typedef struct _HTC_SERVICE { + struct _HTC_SERVICE *pNext; + /* Callback for processing receive messages. HTC calls this callback whenever a + * message arrives on the endpoint assigned to this service. + * HTC_BUFFER is a chain of buffers containing a full application message. + * HTC_BUFFER->buffer points to the start of the msg buffer (past the HTC header) */ + //void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, HTC_BUFFER *); + void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx); + /* callback to process completed send buffers */ + //void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, HTC_BUFFER *); + void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx); + /* optional callback when a connection request occurs. + * The EndpointID is the assigned endpoint, the callback returns a connect + * response status code to allow or disallow the connection. + * pDataIn points to the optional meta data supplied in the connection request + * pDataOut points to a buffer to send back meta data + * If no callback is supplied, HTC assumes the connect is allowed */ + A_UINT8 (* ProcessConnect)(struct _HTC_SERVICE *pService, + HTC_ENDPOINT_ID EndpointID, + A_UINT8 *pDataIn, + int LengthIn, + A_UINT8 *pDataOut, + int *pLengthOut); + A_UINT16 ServiceID; /* service ID to match connection requests */ + A_UINT16 ServiceFlags; /* service flags */ + A_UINT16 MaxSvcMsgSize; /* maximum length of service-specific messages exchanged on the endpoint */ + A_UINT16 TrailerSpcCheckLimit; /* amount of space in each send buffer that HTC can check for trailer + data. This should be set to the smallest HTC buffer that can be sent + through the service. The service can disable trailer data insertion + by setting this value to 0. */ + void *ServiceCtx; +} HTC_SERVICE; + +#define HTC_SERVICE_FLAGS_CONNECTED (1 << 0) /* service has at least 1 connection */ + +#define IS_SERVICE_CONNECTED(s) ((s)->ServiceFlags & HTC_SERVICE_FLAGS_CONNECTED) + + /* configuration settings for the WMI service */ +typedef struct _HTC_CONFIG { + int CreditSize; /* */ + int CreditNumber; + //int ControlDownLinkPipeID; + //int ControlUpLinkPipeID; + adf_os_handle_t OSHandle; + hif_handle_t HIFHandle; + pool_handle_t PoolHandle; +} HTC_CONFIG; + +typedef struct _HTC_BUF_CONTEXT { + A_UINT8 end_point; + A_UINT8 htc_flags; /* htc flags (used by HTC layer only) */ +} HTC_BUF_CONTEXT; + +typedef void* htc_handle_t; + +/* + * setup complete function, supplied by HTC caller at HTC_init time. + * HTC calls this function after the host has indicated that the service connection + * phase is complete. + * + */ +typedef void (* HTC_SETUP_COMPLETE_CB)(void); + +struct htc_apis { + htc_handle_t (* _HTC_Init)(HTC_SETUP_COMPLETE_CB, HTC_CONFIG *pConfig); + void (* _HTC_Shutdown)(htc_handle_t); + void (* _HTC_RegisterService)(htc_handle_t, HTC_SERVICE *); + void (* _HTC_Ready)(htc_handle_t); + void (* _HTC_ReturnBuffers)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t); + void (* _HTC_ReturnBuffersList)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t); + void (* _HTC_SendMsg)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t); + int (* _HTC_GetReservedHeadroom)(htc_handle_t handle); + + //void (* _HTC_PauseRecv)(HTC_ENDPOINT_ID EndpointID); + //void (* _HTC_ResumeRecv)(HTC_ENDPOINT_ID EndpointID); + //void (* _HTC_AddBufferResources)(int buffers); + + /* These APIs below are for patch purpose only */ + void (*_HTC_MsgRecvHandler)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); + void (*_HTC_SendDoneHandler)(adf_nbuf_t buf, void *context); + void (*_HTC_ControlSvcProcessMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *arg); + void (*_HTC_ControlSvcProcessSendComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg); + + void *pReserved; /* for expansion if need be */ +}; + +extern void htc_module_install(struct htc_apis *pAPIs); + +#endif /* _HTC_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/src/htc.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/src/htc.c new file mode 100755 index 0000000..223d269 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/src/htc.c @@ -0,0 +1,1009 @@ +/* + * @File: + * + * @Abstract: host target communications + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include "htc_internal.h" + +//#define A_ASSERT(m) +#define A_UNCACHED_ADDR(addr) addr +//#define A_MEMZERO(v, size) + +/*** statics vars ****/ +//HTC_CONTEXT g_htcCtx; +//HTC_CONTEXT *g_pHTC = NULL; + +/* prototypes */ +LOCAL void HTCControlSvcProcessMsg(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t pBuffers, void *arg); +LOCAL void HTCControlSvcProcessSendComplete(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg); +LOCAL void HTCMsgRecvHandler(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); +LOCAL void HTCSendDoneHandler(adf_nbuf_t buf, void *context); +LOCAL void HTCFreeMsgBuffer(HTC_CONTEXT *pHTC, adf_nbuf_t pBuffer); +LOCAL adf_nbuf_t HTCAllocMsgBuffer(HTC_CONTEXT *pHTC); +//LOCAL void HTC_EnqueuePausedRecv(HTC_ENDPOINT *pEndpoint, +// VBUF *pFirstBuf, +// VBUF *pLastBuf); +//LOCAL VBUF* HTC_DequeuePausedRecv(HTC_ENDPOINT *pEndpoint); +LOCAL void HTCCheckAndSendCreditReport(HTC_CONTEXT *pHTC, A_UINT32 EpMask, HTC_ENDPOINT *pEndpoint, HTC_ENDPOINT_ID Id); +LOCAL void AdjustCreditThreshold(HTC_ENDPOINT *pEndpoint); +//LOCAL void _HTC_AddBufferResources(int buffers); +LOCAL void HTC_AssembleBuffers(HTC_CONTEXT *pHTC, int Count, int Size); +LOCAL htc_handle_t _HTC_Init(/*A_UINT32 dataAddr,*/ + HTC_SETUP_COMPLETE_CB SetupComplete, + HTC_CONFIG *pConfig); +LOCAL void _HTC_RegisterService(htc_handle_t handle, HTC_SERVICE *pService); +LOCAL void _HTC_Ready(htc_handle_t handle); +LOCAL void ReturnBuffers(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, A_BOOL sendCreditFlag); +LOCAL void _HTC_ReturnBuffers(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers); +LOCAL void _HTC_ReturnBuffersList(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t bufHead); +LOCAL void _HTC_SendMsg(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers); +void _HTC_PauseRecv(HTC_ENDPOINT_ID EndpointID); +void _HTC_ResumeRecv(HTC_ENDPOINT_ID EndpointID); +LOCAL void HTCProcessConnectMsg(HTC_CONTEXT *pHTC, HTC_CONNECT_SERVICE_MSG *pMsg); +LOCAL void HTCProcessConfigPipeMsg(HTC_CONTEXT *pHTC, HTC_CONFIG_PIPE_MSG *pMsg); +LOCAL void RedistributeCredit(adf_nbuf_t buf, int toPipeId); +LOCAL void _HTC_Shutdown(htc_handle_t htcHandle); + + /* macro to check if the service wants to prevent credit dribbling by using + a dynamic threshold */ +#define CHECK_AND_ADJUST_CREDIT_THRESHOLD(pEndpoint) \ + if ((pEndpoint)->ConnectionFlags & HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE) { \ + AdjustCreditThreshold((pEndpoint)); \ + } + +/***********************************************************************************************/ +/************************ MODULE API implementation *******************************************/ +#if 0 +LOCAL void _HTC_AddBufferResources(int buffers) +{ + (void)buffers; + //MboxHW_AddDMAResources(buffers); +} +#endif + +LOCAL void HTC_AssembleBuffers(HTC_CONTEXT *pHTC, int Count, int Size) +{ + BUF_Pool_create_pool(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, Count, Size); +} + + +LOCAL htc_handle_t _HTC_Init(HTC_SETUP_COMPLETE_CB SetupComplete, + HTC_CONFIG *pConfig) +{ + HIF_CALLBACK hifCBConfig; + HTC_CONTEXT *pHTC; + + //if (NULL == g_pHTC) + { + pHTC = (HTC_CONTEXT *)adf_os_mem_alloc(sizeof(HTC_CONTEXT)); + //g_pHTC = &g_htcCtx; + } + + adf_os_mem_zero(pHTC, sizeof(HTC_CONTEXT)); + + pHTC->OSHandle = pConfig->OSHandle; + pHTC->PoolHandle = pConfig->PoolHandle; + pHTC->hifHandle = pConfig->HIFHandle; + + //A_MEMZERO(&hwConfig,sizeof(hwConfig)); + hifCBConfig.send_buf_done = A_INDIR(htc._HTC_SendDoneHandler); + hifCBConfig.recv_buf = A_INDIR(htc._HTC_MsgRecvHandler); + hifCBConfig.context = pHTC; + + /* initialize hardware layer */ + HIF_register_callback(pConfig->HIFHandle, &hifCBConfig); + + /* see if the host wants us to override the number of ctrl buffers */ + //g_pHTC->NumBuffersForCreditRpts = (HOST_INTEREST->hi_mbox_io_block_sz >> 16) & 0xF; + pHTC->NumBuffersForCreditRpts = 0; + + if (0 == pHTC->NumBuffersForCreditRpts) { + /* nothing to override, simply set default */ + pHTC->NumBuffersForCreditRpts = HTC_DEFAULT_NUM_CTRL_BUFFERS; + } + + //g_pHTC->MaxEpPendingCreditRpts = (HOST_INTEREST->hi_mbox_io_block_sz >> 20) & 0xF; + pHTC->MaxEpPendingCreditRpts = 0; + + if (0 == pHTC->MaxEpPendingCreditRpts) { + pHTC->MaxEpPendingCreditRpts = HTC_DEFAULT_MAX_EP_PENDING_CREDIT_REPORTS; + } + /* calculate the total allocation size based on the number of credit report buffers */ + pHTC->CtrlBufferAllocSize = MIN_CREDIT_BUFFER_ALLOC_SIZE * pHTC->NumBuffersForCreditRpts; + /* we need at least enough buffer space for 1 ctrl message */ + pHTC->CtrlBufferAllocSize = A_MAX(pHTC->CtrlBufferAllocSize,MAX_HTC_SETUP_MSG_SIZE); + + //A_PRINTF("%d, %d, (%d, %d) %s-%s \n",g_pHTC->NumBuffersForCreditRpts,g_pHTC->CtrlBufferAllocSize, + // MIN_BUF_SIZE_FOR_RPTS, MIN_CREDIT_BUFFER_ALLOC_SIZE,__DATE__, __TIME__); + + /* save the size of each buffer/credit we will receive */ + pHTC->RecvBufferSize = pConfig->CreditSize; //RecvBufferSize; + pHTC->TotalCredits = pConfig->CreditNumber; + //g_pHTC->FreeCreditList = pConfig->CreditList; + pHTC->TotalCreditsAssigned = 0; + + /* setup the pseudo service that handles HTC control messages */ + pHTC->HTCControlService.ProcessRecvMsg = A_INDIR(htc._HTC_ControlSvcProcessMsg); + pHTC->HTCControlService.ProcessSendBufferComplete = A_INDIR(htc._HTC_ControlSvcProcessSendComplete); + pHTC->HTCControlService.TrailerSpcCheckLimit = HTC_CTRL_BUFFER_CHECK_SIZE; + pHTC->HTCControlService.MaxSvcMsgSize = MAX_HTC_SETUP_MSG_SIZE; + pHTC->HTCControlService.ServiceCtx = pHTC; + + /* automatically register this pseudo service to endpoint 1 */ + pHTC->Endpoints[ENDPOINT0].pService = &pHTC->HTCControlService; + HIF_get_default_pipe(pHTC->hifHandle, &pHTC->Endpoints[ENDPOINT0].UpLinkPipeID, + &pHTC->Endpoints[ENDPOINT0].DownLinkPipeID); + + /* Initialize control pipe so we could receive the HTC control packets */ + // @TODO: msg size! + HIF_config_pipe(pHTC->hifHandle, pHTC->Endpoints[ENDPOINT0].UpLinkPipeID, 1); + + /* set the first free endpoint */ + pHTC->CurrentEpIndex = ENDPOINT1; + pHTC->SetupCompleteCb = SetupComplete; + + /* setup buffers for just the setup phase, we only need 1 buffer to handle + * setup */ + HTC_AssembleBuffers(pHTC, 4, MAX_HTC_SETUP_MSG_SIZE); + + /* start hardware layer so that we can queue buffers */ + HIF_start(pHTC->hifHandle); + + return pHTC; +} + +LOCAL void _HTC_Shutdown(htc_handle_t htcHandle) +{ + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + + adf_os_mem_free(pHTC); +} + +LOCAL void _HTC_RegisterService(htc_handle_t htcHandle, HTC_SERVICE *pService) +{ + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + + /* add it to the list */ + pService->pNext = pHTC->pServiceList; + pHTC->pServiceList = pService; +} + +LOCAL void _HTC_Ready(htc_handle_t htcHandle) +{ + adf_nbuf_t pBuffer; + HTC_READY_MSG *pReady; + a_uint8_t *addr; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + + pBuffer = HTCAllocMsgBuffer(pHTC); + //A_ASSERT(pBuffer != NULL); + + /* an optimization... the header length is chosen to + * be aligned on a 16 bit bounday, the fields in the message are designed to + * be aligned */ + addr = adf_nbuf_put_tail(pBuffer, sizeof(HTC_READY_MSG)); + pReady = (HTC_READY_MSG *)addr; + A_MEMZERO(pReady,sizeof(HTC_READY_MSG)); + pReady->MessageID = adf_os_htons(HTC_MSG_READY_ID); + pReady->CreditSize = adf_os_htons((A_UINT16)pHTC->RecvBufferSize); + //A_ASSERT(g_pHTC->TotalCredits <= MAX_HTC_CREDITS); + pReady->CreditCount = adf_os_htons((A_UINT16)pHTC->TotalCredits); + pReady->MaxEndpoints = ENDPOINT_MAX; + + /* send out the message */ + //A_DATA_CACHE_FLUSH(pBuffer->buffer, pBuffer->actual_length); + HTC_SendMsg(pHTC, ENDPOINT0, pBuffer); + /* now we need to wait for service connection requests */ +} + +LOCAL void ReturnBuffers(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, A_BOOL sendCreditFlag) +{ + int nbufs = 1; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + + //A_ASSERT(EndpointID < ENDPOINT_MAX); + + /* supply some head-room again */ + adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH); + //A_DATA_CACHE_INVAL(pBuffers->buffer, pBuffers->actual_length + HTC_HDR_SZ); + + /* enqueue all buffers to the single mailbox */ + HIF_return_recv_buf(pHTC->hifHandle, pHTC->Endpoints[EndpointID].UpLinkPipeID, pBuffers); + //A_ASSERT(nbufs != 0); + + if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) { + A_UINT32 epCreditMask = (1 << EndpointID); + /* we are running normally */ + /* update pending credit counts with the number of buffers that were added */ + pHTC->Endpoints[EndpointID].CreditsToReturn += (A_INT16)nbufs; + pHTC->Endpoints[EndpointID].CreditsConsumed -= (A_INT16)nbufs; + //A_ASSERT(g_pHTC->Endpoints[EndpointID].CreditsConsumed >= 0); + /* update bit map that this endpoint has non-zero credits */ + pHTC->EpCreditPendingMap |= epCreditMask; + + if (sendCreditFlag) { + HTCCheckAndSendCreditReport(pHTC, epCreditMask,&pHTC->Endpoints[EndpointID],EndpointID); + } + + } else { + /* we have not started yet so all return operations are simply adding buffers + * to the interface at startup, so we can keep track of how many total + * credits we get */ + /* update global count that will be returned to the host */ + pHTC->TotalCredits += nbufs; + } +} + +LOCAL void _HTC_ReturnBuffersList(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t bufHead) +{ + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + adf_nbuf_t netbuf, tmpNbuf; + + /* retrieve each nbuf in the queue */ + netbuf = adf_nbuf_queue_first(&bufHead); + + while (netbuf) { + + tmpNbuf = netbuf; + netbuf = adf_nbuf_queue_next(netbuf); + + ReturnBuffers(htcHandle, EndpointID, tmpNbuf, FALSE); + } + + HTCCheckAndSendCreditReport(pHTC, (1 << EndpointID),&pHTC->Endpoints[EndpointID],EndpointID); +} + +LOCAL void _HTC_ReturnBuffers(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers) +{ + ReturnBuffers(htcHandle, EndpointID, pBuffers, TRUE); +} + +LOCAL void _HTC_SendMsg(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers) +{ + HTC_FRAME_HDR *pHTCHdr; + int totsz; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + HTC_BUF_CONTEXT *ctx; + + ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pBuffers); + + /* init total size (this does not include the space we will put in for the HTC header) */ + totsz = adf_nbuf_len(pBuffers); + + /* the first buffer stores the header */ + /* back up buffer by a header size when we pass it down, by agreed upon convention the caller + * points the buffer to it's payload and leaves head room for the HTC header + * Note: in HTCSendDoneHandler(), we undo this so that the caller get's it's buffer + * back untainted */ + pHTCHdr = (HTC_FRAME_HDR *)adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH); + + /* flag that this is the header buffer that was modified */ + ctx->htc_flags |= HTC_FLAGS_BUF_HDR; + /* mark where this buffer came from */ + ctx->end_point = EndpointID; + /* the header start is ALWAYS aligned since we DMA it directly */ + //pHTCHdr = (HTC_FRAME_HDR *)A_UNCACHED_ADDR(VBUF_GET_DATA_ADDR(pBuffers)); + /* set some fields, the rest of them will be filled below when we check for + * trailer space */ + pHTCHdr->Flags = 0; + pHTCHdr->EndpointID = EndpointID; + + //A_ASSERT(totsz <= g_pHTC->Endpoints[EndpointID].pService->MaxSvcMsgSize); + /* check opportunistically if we can return any reports via a trailer */ + do { + int room,i,totalReportBytes; + A_UINT32 creditsPendingMap, compareMask; + HTC_CREDIT_REPORT *pCreditRpt; + HTC_RECORD_HDR *pRecHdr; + int pipeMaxLen; + A_UINT32 roomForPipeMaxLen; + + /* figure out how much room the last buffer can spare */ + pipeMaxLen = HIF_get_max_msg_len(pHTC->hifHandle, pHTC->Endpoints[EndpointID].DownLinkPipeID); + roomForPipeMaxLen = pipeMaxLen - adf_nbuf_headroom(pBuffers) - adf_nbuf_len(pBuffers); + if ( roomForPipeMaxLen < 0 ) { + roomForPipeMaxLen = 0; + } + + room = adf_os_min( adf_nbuf_tailroom(pBuffers), roomForPipeMaxLen); + if (room < (int)(sizeof(HTC_CREDIT_REPORT) + sizeof(HTC_RECORD_HDR))) { + /* no room for any reports */ + break; + } + /* note, a record header only has 8 bit fields, so this is safe. + * we need an uncached pointer here too */ + totalReportBytes = 0; + + /* get a copy */ + creditsPendingMap = pHTC->EpCreditPendingMap; + + /* test pending map to see if we can send a report , if any + * credits are available, we might as well send them on the + * unused space in the buffer */ + if (creditsPendingMap) { + + pRecHdr = (HTC_RECORD_HDR *)adf_nbuf_put_tail(pBuffers, sizeof(HTC_RECORD_HDR)); + + /* set the ID, the length will be updated with the number of credit reports we + * can fit (see below) */ + pRecHdr->RecordID = HTC_RECORD_CREDITS; + pRecHdr->Length = 0; + /* the credit report follows the record header */ + totalReportBytes += sizeof(HTC_RECORD_HDR); + room -= sizeof(HTC_RECORD_HDR); + + /* walkthrough pending credits map and build the records */ + for (i = 0; + (creditsPendingMap != 0) && (room >= (int)sizeof(HTC_CREDIT_REPORT)); + i++) { + compareMask = (1 << i); + if (compareMask & creditsPendingMap) { + + pCreditRpt = (HTC_CREDIT_REPORT *)adf_nbuf_put_tail(pBuffers, sizeof(HTC_CREDIT_REPORT)); + + /* clear pending mask, we are going to return all these credits */ + creditsPendingMap &= ~(compareMask); + /* add this record */ + pCreditRpt->EndpointID = i; + pCreditRpt->Credits = (A_UINT8)pHTC->Endpoints[i].CreditsToReturn; + /* remove pending credits, we always send deltas */ + pHTC->Endpoints[i].CreditsToReturn = 0; + /* adjust new threshold for this endpoint if needed */ + CHECK_AND_ADJUST_CREDIT_THRESHOLD(&pHTC->Endpoints[i]); + /* update this record length */ + pRecHdr->Length += sizeof(HTC_CREDIT_REPORT); + room -= sizeof(HTC_CREDIT_REPORT); + totalReportBytes += sizeof(HTC_CREDIT_REPORT); + + if ( room < sizeof(HTC_CREDIT_REPORT) ) { + break; + } + } + } + + /* update new pending credits map */ + pHTC->EpCreditPendingMap = creditsPendingMap; + } + + if (totalReportBytes <= 0) { + break; + } + + /* must fit into a byte, this should never actually happen since + * the maximum possible number of endpoints is 32. + * The trailer can have at most 1 credit record with up to 32 reports in the record. + * The trailer can have at most 1 lookahead record with only 1 lookahead report in the record. + * + * */ + //A_ASSERT(totalReportBytes <= 255); + + /* set header option bytes */ + pHTCHdr->ControlBytes[0] = totalReportBytes; + /* HTC frame contains a trailer */ + pHTCHdr->Flags |= HTC_FLAGS_RECV_TRAILER; + /* increment total size by the reports we added */ + totsz += totalReportBytes; + /* adjust the last buffer we used for adding on the trailer */ + } while (FALSE); + + if (totsz == 0) { + //A_ASSERT(FALSE); + } + + /* set length for message (this includes any reports that were added above) */ + pHTCHdr->PayloadLen = adf_os_htons(totsz); + HIF_send_buffer(pHTC->hifHandle, pHTC->Endpoints[EndpointID].DownLinkPipeID, pBuffers); +} + +void _HTC_PauseRecv(HTC_ENDPOINT_ID EndpointID) +{ +#if 0 // Disable first. Ray +#ifdef HTC_PAUSE_RESUME_REF_COUNTING + g_pHTC->Endpoints[EndpointID].PauseRefCount++; +#endif + /* we are now paused */ + g_pHTC->EpRecvPausedMap |= (1 << EndpointID); +#endif +} + +void _HTC_ResumeRecv(HTC_ENDPOINT_ID EndpointID) +{ +#if 0 // Disable first. Ray + HTC_BUFFER *buffer; + HTC_ENDPOINT *pEndpoint; + + pEndpoint = &g_pHTC->Endpoints[EndpointID]; + +/* TODO: we can't quite use referencing counting yet until we clean up the WLAN + * app, there are some un-matched pause/resume cases that need to be fixed */ +#ifdef HTC_PAUSE_RESUME_REF_COUNTING + pEndpoint->PauseRefCount--; + //A_ASSERT(pEndpoint->PauseRefCount >= 0); + + /* check reference count and unpause if it is zero */ + if (pEndpoint->PauseRefCount > 0) { + return; + } +#endif + + g_pHTC->EpRecvPausedMap &= ~(1 << EndpointID); + /* unload the paused receive queue */ + while ((buffer = HTC_DequeuePausedRecv(pEndpoint)) != NULL) { + /* note that the paused messages have already been processed at the HTC layer, + * we can simply indicate the buffers to the service */ + pEndpoint->pService->ProcessRecvMsg(EndpointID,buffer); + } +#endif +} + +int _HTC_GetReservedHeadroom(htc_handle_t htcHandle) +{ + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + + return HTC_HDR_LENGTH + HIF_get_reserved_headroom(pHTC->hifHandle); +} + +void htc_module_install(struct htc_apis *pAPIs) +{ + pAPIs->_HTC_Init = _HTC_Init; + pAPIs->_HTC_ReturnBuffers = _HTC_ReturnBuffers; + pAPIs->_HTC_ReturnBuffersList = _HTC_ReturnBuffersList; + pAPIs->_HTC_Ready = _HTC_Ready; + pAPIs->_HTC_RegisterService = _HTC_RegisterService; + pAPIs->_HTC_SendMsg = _HTC_SendMsg; + pAPIs->_HTC_Shutdown = _HTC_Shutdown; + pAPIs->_HTC_GetReservedHeadroom = _HTC_GetReservedHeadroom; + pAPIs->_HTC_MsgRecvHandler = HTCMsgRecvHandler; + pAPIs->_HTC_SendDoneHandler = HTCSendDoneHandler; + pAPIs->_HTC_ControlSvcProcessMsg = HTCControlSvcProcessMsg; + pAPIs->_HTC_ControlSvcProcessSendComplete = HTCControlSvcProcessSendComplete; + + //pAPIs->_HTC_PauseRecv = _HTC_PauseRecv; + //pAPIs->_HTC_ResumeRecv = _HTC_ResumeRecv; + //pAPIs->_HTC_AddBufferResources = _HTC_AddBufferResources; + /* save ptr to the ptr to the context for external code to inspect/modify internal module state */ + //pAPIs->pReserved = &g_pHTC; +} + +/*******************************************************************************************/ +/**************** INTERNAL ROUTINES to this MODULE ***************************************/ + +/* free message to the free list */ +//LOCAL void HTCFreeMsgBuffer(HTC_BUFFER *pBuffer) +LOCAL void HTCFreeMsgBuffer(HTC_CONTEXT *pHTC, adf_nbuf_t buf) +{ + BUF_Pool_free_buf(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, buf); +} + +/* HTC control message allocator (also used for empty frames to send trailer options) */ +//LOCAL HTC_BUFFER *HTCAllocMsgBuffer(void) +LOCAL adf_nbuf_t HTCAllocMsgBuffer(HTC_CONTEXT *pHTC) +{ + return BUF_Pool_alloc_buf(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, HTC_GetReservedHeadroom(pHTC)); +} + +LOCAL void HTCCheckAndSendCreditReport(HTC_CONTEXT *pHTC, A_UINT32 EpMask, HTC_ENDPOINT *pEndpoint, HTC_ENDPOINT_ID Eid) +{ + adf_nbuf_t pCredBuffer; + HTC_BUF_CONTEXT *ctx; + + do { + /* check if host needs credits */ + if (!(pHTC->EpHostNeedsCreditMap & EpMask)) { + /* host does not need any credits for this set */ + break; + } + /* check if any are pending */ + if (!(pHTC->EpCreditPendingMap & EpMask)) { + /* nothing to send up */ + break; + } + /* was an endpoint specified? */ + if (pEndpoint != NULL) { + /* see if a threshold is in effect for this endpoint */ + if (pEndpoint->CreditReturnThreshhold != 0) { + if (pEndpoint->CreditsToReturn < pEndpoint->CreditReturnThreshhold) { + /* this endpoint is using a threshold to prevent credits from dribbling + * back to the host */ + break; + } + } + + if (pEndpoint->PendingCreditReports >= pHTC->MaxEpPendingCreditRpts) { + /* this endpoint already has some reports outstanding */ + /* flag that as soon as a buffer is reaped, we issue a credit update to + * pick up this credit that is being held up because the endpoint has already + * exceeded the max outstanding credit report limit */ + pHTC->StateFlags |= HTC_SEND_CREDIT_UPDATE_SOON; + break; + } + } + + /* if we get here we have some credits to send up */ + + /* allocate a message buffer for the trailer */ + pCredBuffer = HTCAllocMsgBuffer(pHTC); + if (NULL == pCredBuffer) { + /* no buffers left to send an empty message with trailers, host will just + * have to wait until we get our endpoint 0 messages back.. */ + /* mark that we need to send an update as soon as we can get a buffer back */ + pHTC->StateFlags |= HTC_SEND_CREDIT_UPDATE_SOON; + break; + } + + ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pCredBuffer); + if (pEndpoint != NULL) { + /* keep track of pending reports */ + pEndpoint->PendingCreditReports++; + /* save the endpoint in order to decrement the count when the send completes */ + ctx->htc_flags = Eid | HTC_FLAGS_CREDIT_RPT; + } + + /* this is an empty message, the HTC_SendMsg will tack on a trailer in the remaining + * space, NOTE: no need to flush the cache, the header and trailers are assembled + * using uncached addresses */ + HTC_SendMsg(pHTC, ENDPOINT0, pCredBuffer); + + } while (FALSE); +} + +/* called in response to the arrival of a service connection message */ +LOCAL void HTCProcessConnectMsg(HTC_CONTEXT *pHTC, HTC_CONNECT_SERVICE_MSG *pMsg) +{ + HTC_SERVICE *pService = pHTC->pServiceList; + A_UINT8 connectStatus = HTC_SERVICE_NOT_FOUND; + //HTC_BUFFER *pBuffer; + adf_nbuf_t pBuffer; + HTC_CONNECT_SERVICE_RESPONSE_MSG *pRspMsg; + int metaDataOutLen = 0; + A_UINT16 serviceId = adf_os_ntohs(pMsg->ServiceID); + + pBuffer = HTCAllocMsgBuffer(pHTC); + //A_ASSERT(pBuffer != NULL); + /* note : this will be aligned */ + pRspMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *) + adf_nbuf_put_tail(pBuffer, sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG)); + + A_MEMZERO(pRspMsg,sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG)); + pRspMsg->MessageID = adf_os_htons(HTC_MSG_CONNECT_SERVICE_RESPONSE_ID); + /* reflect the service ID for this connect attempt */ + pRspMsg->ServiceID = adf_os_htons(serviceId); + + while (pService) { + + if (pHTC->CurrentEpIndex >= ENDPOINT_MAX) { + /* no more endpoints */ + connectStatus = HTC_SERVICE_NO_RESOURCES; + break; + } + + if (serviceId == pService->ServiceID) { + /* we found a match */ + A_UINT8 *pMetaDataIN = NULL; + A_UINT8 *pMetaDataOut; + + /* outgoing meta data resides in the space after the response message */ + pMetaDataOut = ((A_UINT8 *)pRspMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG); + + if (pMsg->ServiceMetaLength != 0) { + //A_ASSERT(pMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH); + /* the meta data follows the connect service message */ + pMetaDataIN = ((A_UINT8 *)pMsg) + sizeof(HTC_CONNECT_SERVICE_MSG); + } + + //A_ASSERT(pService->ProcessConnect != NULL); + /* call the connect callback with the endpoint to use and pointers to meta data */ + connectStatus = pService->ProcessConnect(pService, + pHTC->CurrentEpIndex, + pMetaDataIN, + pMsg->ServiceMetaLength, + pMetaDataOut, + &metaDataOutLen); + + /* check if the service accepted this connection request */ + if (HTC_SERVICE_SUCCESS == connectStatus) { + //A_ASSERT(metaDataOutLen <= HTC_SERVICE_META_DATA_MAX_LENGTH); + /* set the length of the response meta data going back to the host */ + pRspMsg->ServiceMetaLength = (A_UINT8)metaDataOutLen; + /* set the endpoint ID the host will now communicate over */ + pRspMsg->EndpointID = pHTC->CurrentEpIndex; + /* return the maximum message size for this service */ + pRspMsg->MaxMsgSize = adf_os_htons((A_UINT16)pService->MaxSvcMsgSize); + /* assign this endpoint to this service, this will be used in routing messages */ + pHTC->Endpoints[pHTC->CurrentEpIndex].pService = pService; + /* set connection flags */ + pHTC->Endpoints[pHTC->CurrentEpIndex].ConnectionFlags = pMsg->ConnectionFlags; + + pHTC->Endpoints[pHTC->CurrentEpIndex].DownLinkPipeID = pMsg->DownLinkPipeID; + pHTC->Endpoints[pHTC->CurrentEpIndex].UpLinkPipeID = pMsg->UpLinkPipeID; + + /* mark that we are now connected */ + pService->ServiceFlags |= HTC_SERVICE_FLAGS_CONNECTED; + /* bump up our index, this EP is now in use */ + pHTC->CurrentEpIndex++; + } + + break; + } + + pService = pService->pNext; + } + + pRspMsg->Status = connectStatus; + + /* send out the response message */ + //A_DATA_CACHE_FLUSH(pBuffer->buffer, pBuffer->actual_length); + HTC_SendMsg(pHTC, ENDPOINT0, pBuffer); +} + +LOCAL void HTCProcessConfigPipeMsg(HTC_CONTEXT *pHTC, HTC_CONFIG_PIPE_MSG *pMsg) +{ + //HTC_SERVICE *pService = g_pHTC->pServiceList; + //A_UINT8 connectStatus = HTC_SERVICE_NOT_FOUND; + adf_nbuf_t pBuffer; + HTC_CONFIG_PIPE_RESPONSE_MSG *pRspMsg; + + pBuffer = HTCAllocMsgBuffer(pHTC); + + //A_ASSERT(pBuffer != NULL); + /* note : this will be aligned */ + pRspMsg = (HTC_CONFIG_PIPE_RESPONSE_MSG *) + adf_nbuf_put_tail(pBuffer, sizeof(HTC_CONFIG_PIPE_RESPONSE_MSG)); + + A_MEMZERO(pRspMsg,sizeof(HTC_CONFIG_PIPE_RESPONSE_MSG)); + + pRspMsg->MessageID = adf_os_htons(HTC_MSG_CONFIG_PIPE_RESPONSE_ID); + /* reflect the service ID for this connect attempt */ + pRspMsg->PipeID = pMsg->PipeID; + + if ( HIF_is_pipe_supported(pHTC->hifHandle, pMsg->PipeID) ) { + pRspMsg->Status = 0; + } else { + pRspMsg->Status = 1; + goto config_done; + } + + if ( (pHTC->TotalCreditsAssigned + pMsg->CreditCount) <= pHTC->TotalCredits ) { + pHTC->TotalCreditsAssigned += pMsg->CreditCount; + } else { + pRspMsg->Status = 2; + goto config_done; + } + + HIF_config_pipe(pHTC->hifHandle, pMsg->PipeID, pMsg->CreditCount); + +config_done: + /* send out the response message */ + //A_DATA_CACHE_FLUSH(pBuffer->buffer, pBuffer->actual_length); + HTC_SendMsg(pHTC, ENDPOINT0, pBuffer); +} + +/* process an incomming control message from the host */ +LOCAL void HTCControlSvcProcessMsg(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t pBuffers, void *arg) +{ + A_BOOL setupComplete = FALSE; + a_uint8_t *anbdata; + a_uint32_t anblen; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)arg; + HTC_UNKNOWN_MSG *pMsg; + + adf_os_assert(hdr_buf == ADF_NBUF_NULL); + + /* we assume buffers are aligned such that we can access the message + * parameters directly*/ + adf_nbuf_peek_header(pBuffers, &anbdata, &anblen); + pMsg = (HTC_UNKNOWN_MSG *)anbdata; + + /* we cannot handle fragmented messages across buffers */ + //A_ASSERT(pBuffers->next == NULL); + + switch ( adf_os_ntohs(pMsg->MessageID) ) { + case HTC_MSG_CONNECT_SERVICE_ID: + //A_ASSERT(pBuffers->actual_length >= sizeof(HTC_CONNECT_SERVICE_MSG)); + HTCProcessConnectMsg(pHTC, (HTC_CONNECT_SERVICE_MSG *)pMsg); + break; + case HTC_MSG_CONFIG_PIPE_ID: + HTCProcessConfigPipeMsg(pHTC, (HTC_CONFIG_PIPE_MSG *)pMsg); + break; + case HTC_MSG_SETUP_COMPLETE_ID: + /* the host has indicated that it has completed all + setup tasks and we can now let the services take over to + run the rest of the application */ + setupComplete = TRUE; + /* can't get this more than once */ + //A_ASSERT(!(g_pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE)); + break; + default: + ; + //A_ASSERT(FALSE); + } + + if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) { + /* recycle buffer only if we are fully running */ + HTC_ReturnBuffers(pHTC, ENDPOINT0,pBuffers); + } else { + /* supply some head-room again */ + //A_DATA_CACHE_INVAL(pBuffers->buffer, pBuffers->actual_length + HTC_HDR_SZ); + adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH); + + /* otherwise return the packet back to mbox */ + HIF_return_recv_buf(pHTC->hifHandle, pHTC->Endpoints[EndpointID].UpLinkPipeID, pBuffers); + } + + if (setupComplete) { + /* mark that setup has completed */ + pHTC->StateFlags |= HTC_STATE_SETUP_COMPLETE; + if (pHTC->SetupCompleteCb != NULL) { + pHTC->SetupCompleteCb(); + } + } +} + +/* callback when endpoint 0 send buffers are completed */ +LOCAL void HTCControlSvcProcessSendComplete(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg) +{ + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)arg; + HTC_BUF_CONTEXT *ctx; + HTC_ENDPOINT_ID creditRptEndpoint; + + ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pBuffers); + + //A_ASSERT(EndpointID == ENDPOINT0); + + /* put them back into the pool */ +#if 0 + while (pBuffers != NULL) { + pNext = pBuffers->next_buf; + pBuffers->next_buf = NULL; + /* note: HTC does not send fragmented control messages, so each buffer + * represents 1 full HTC control message */ + if (pBuffers->desc_list->control & HTC_FLAGS_CREDIT_RPT) { + /* extract the endpoint number that requested this credit report */ + creditRptEndpoint = pBuffers->desc_list->control & HTC_FLAGS_CRPT_EP_MASK; + pBuffers->desc_list->control = 0; + g_pHTC->Endpoints[creditRptEndpoint].PendingCreditReports--; + //A_ASSERT(g_pHTC->Endpoints[creditRptEndpoint].PendingCreditReports >= 0); + } + /* free this one */ + HTCFreeMsgBuffer(pBuffers); + pBuffers = pNext; + } +#else + if ( ctx->htc_flags & HTC_FLAGS_CREDIT_RPT ) { + /* extract the endpoint number that requested this credit report */ + creditRptEndpoint = ctx->htc_flags & HTC_FLAGS_CRPT_EP_MASK; + pHTC->Endpoints[creditRptEndpoint].PendingCreditReports--; + //A_ASSERT(g_pHTC->Endpoints[creditRptEndpoint].PendingCreditReports >= 0); + } + + HTCFreeMsgBuffer(pHTC, pBuffers); +#endif + + if (pHTC->StateFlags & HTC_SEND_CREDIT_UPDATE_SOON) { + /* this flag is set when the host could not send a credit report + * because we ran out of HTC control buffers */ + pHTC->StateFlags &= ~HTC_SEND_CREDIT_UPDATE_SOON; + /* send out a report if anything is pending */ + HTCCheckAndSendCreditReport(pHTC, HTC_ANY_ENDPOINT_MASK,NULL,ENDPOINT_MAX); + } +} + +LOCAL void HTCSendDoneHandler(adf_nbuf_t buf, void *context) +{ + A_UINT8 current_eid; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)context; + HTC_BUF_CONTEXT *ctx; + + ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(buf); + current_eid = ctx->end_point; + + /* Walk through the buffers and fixup the ones we used for HTC headers. + * The buffer list may contain more than one string of HTC buffers comprising of an + * HTC message so we need to check every buffer */ + adf_nbuf_pull_head(buf, HTC_HDR_LENGTH); + + pHTC->Endpoints[current_eid].pService-> + ProcessSendBufferComplete(current_eid, + buf, + pHTC->Endpoints[current_eid].pService->ServiceCtx); +} + +#if 0 +LOCAL void HTC_EnqueuePausedRecv(HTC_ENDPOINT *pEndpoint, + HTC_BUFFER *pFirstBuf, + HTC_BUFFER *pLastBuf) +{ + //A_ASSERT(pLastBuf->next == NULL); + + if (NULL == pEndpoint->pRcvPausedQueueTail) { + pEndpoint->pRcvPausedQueueTail = pLastBuf; + pEndpoint->pRcvPausedQueueHead = pFirstBuf; + } else { + /* queue to the tail */ + pEndpoint->pRcvPausedQueueTail->next = pFirstBuf; + pEndpoint->pRcvPausedQueueTail = pLastBuf; + } + +} +#endif + +#if 0 +LOCAL HTC_BUFFER *HTC_DequeuePausedRecv(HTC_ENDPOINT *pEndpoint) +{ + HTC_BUFFER *pHead; + HTC_BUFFER *pCur; + + if (pEndpoint->pRcvPausedQueueHead != NULL) { + /* there is a message in the queue */ + pHead = pEndpoint->pRcvPausedQueueHead; + pCur = pHead; + + while (pCur != NULL) { + /* check for end marker on this buffer */ + if (pCur->htc_flags & HTC_FLAGS_RECV_END_MSG) { + pCur->htc_flags &= ~HTC_FLAGS_RECV_END_MSG; + /* advance the head */ + pEndpoint->pRcvPausedQueueHead = pCur->next; + + if (NULL == pEndpoint->pRcvPausedQueueHead) { + /* list is now empty */ + pEndpoint->pRcvPausedQueueTail = NULL; + } + /* cut this message out */ + pCur->next = NULL; + break; + } + pCur = pCur->next; + } + /* we should always find complete messages with the marker present */ + //A_ASSERT(pCur != NULL); + return pHead; + } else { + //A_ASSERT(pEndpoint->pRcvPausedQueueTail == NULL); + return NULL; + } +} +#endif + +LOCAL void AdjustCreditThreshold(HTC_ENDPOINT *pEndpoint) +{ + + A_INT16 creditsOutstanding = pEndpoint->CreditsToReturn + pEndpoint->CreditsConsumed; + /* set the new threshold based on the number of credits that have been consumed + * and which have not been returned by the app. + * Note: it is okay for this threshold to be zero which indicates no threshold + * is in use */ + switch (pEndpoint->ConnectionFlags & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK) { + case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH : + creditsOutstanding >>= 2; + break; + case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF : + creditsOutstanding >>= 1; + break; + case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS : + creditsOutstanding = (creditsOutstanding * 3) >> 2; + break; + /* default case is unity */ + } + + pEndpoint->CreditReturnThreshhold = creditsOutstanding; + +} + +LOCAL void RedistributeCredit(adf_nbuf_t buf, int toPipeId) +{ + +} + +/* callback from the mailbox hardware layer when a full message arrives */ +LOCAL void HTCMsgRecvHandler(adf_nbuf_t hdr_buf, adf_nbuf_t buffer, void *context) +{ + A_UINT16 totsz; + HTC_ENDPOINT *pEndpoint; + A_UINT32 eidMask; + int eid; + a_uint8_t *anbdata; + a_uint32_t anblen; + HTC_FRAME_HDR *pHTCHdr; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)context; + adf_nbuf_t tmp_nbuf; + + if (hdr_buf == ADF_NBUF_NULL) { + /* HTC hdr is not in the hdr_buf */ + tmp_nbuf = buffer; + } + else { + tmp_nbuf = hdr_buf; + } + + adf_nbuf_peek_header(tmp_nbuf, &anbdata, &anblen); + pHTCHdr = (HTC_FRAME_HDR *)anbdata; + + totsz = adf_os_ntohs(pHTCHdr->PayloadLen); + + //A_ASSERT(pHTCHdr->EndpointID < ENDPOINT_MAX); + eid = pHTCHdr->EndpointID; + + pEndpoint = &pHTC->Endpoints[eid]; + eidMask = 1 << eid; + + if (pHTCHdr->Flags & HTC_FLAGS_CREDIT_REDISTRIBUTION) { + /* The pipe id where the credit is redistributed to is carried in Control + * Byte 0 */ + RedistributeCredit(tmp_nbuf, pHTCHdr->ControlBytes[0]); + return; + } + + if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) { + /* after setup we keep track of credit consumption to allow us to + * adjust thresholds to reduce credit dribbling */ + pEndpoint->CreditsConsumed ++; + } + + /* from the design document, we put the endpoint into a "host-needs-credit" state + * when we receive a frame with the NEED_CREDIT_UPDATE flag set . + * if the host received credits through an opportunistic path, then it can + * issue a another frame with this bit cleared, this signals the target to clear + * the "host-needs-credit" state */ + if (pHTCHdr->Flags & HTC_FLAGS_NEED_CREDIT_UPDATE) { + /* the host is running low (or is out) of credits on this + * endpoint, update mask */ + pHTC->EpHostNeedsCreditMap |= eidMask; + /* check and set new threshold since host has reached a low credit situation */ + CHECK_AND_ADJUST_CREDIT_THRESHOLD(pEndpoint); + } else { + /* clear the flag */ + pHTC->EpHostNeedsCreditMap &= ~(eidMask); + pEndpoint->CreditReturnThreshhold = 0; + } + + /* Adjust the first buffer to point to the start of the actual + payload, the first buffer contains the header */ + adf_nbuf_pull_head(tmp_nbuf, HTC_HDR_LENGTH); + + /* NOTE : This callback could re-queue the recv buffers within this calling context. + * The callback could also send a response message within the context of this callback + * as the result of parsing this message. In either case, if there are + * pending credits and the host needs them, a credit report will be sent either through + * the response message trailer or a NULL message through HTC_ReturnBuffers(). + */ + + //A_ASSERT(totsz <= pEndpoint->pService->MaxSvcMsgSize); + +#if 0 + /* is this endpoint paused? */ + if (g_pHTC->EpRecvPausedMap & eidMask) { + /* note that curr_buf is the last buffer */ + /* mark the last buffer so that it indicates the end of this message */ + //curr_buf->htc_flags |= HTC_FLAGS_RECV_END_MSG; + /* enqueue this message to our pause queues */ + //HTC_EnqueuePausedRecv(pEndpoint,bufinfo,curr_buf); + } else { + /* pass the message to the service */ + pEndpoint->pService->ProcessRecvMsg(eid, buffer, pEndpoint->pService->ServiceCtx); + } +#else + pEndpoint->pService->ProcessRecvMsg(eid, hdr_buf, buffer, pEndpoint->pService->ServiceCtx); +#endif + + /* Calls to HTC_ReturnBuffers drives the endpoint credit reporting state machine. + * We do not want to delay credits for too long in the event that the application is + * holding onto buffers for excessive periods of time. This gives us "some" better + * opportunities to send up credits. */ + HTCCheckAndSendCreditReport(pHTC, eidMask, pEndpoint, eid); +} diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/src/htc_internal.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/src/htc_internal.h new file mode 100755 index 0000000..6716d24 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/htc/src/htc_internal.h @@ -0,0 +1,97 @@ +/* + * @File: + * + * @Abstract: internal data and structure definitions for HTC + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef HTC_INTERNAL_H_ +#define HTC_INTERNAL_H_ + +/* minimum buffer size to hold up to 8 endpoint reports, lookahead and the HTC header */ +#define MIN_BUF_SIZE_FOR_RPTS (A_ROUND_UP((sizeof(HTC_LOOKAHEAD_REPORT) + \ + (sizeof(HTC_CREDIT_REPORT)) * 8 + \ + (sizeof(HTC_RECORD_HDR)) * 2 ) + \ + HTC_HDR_LENGTH, \ + sizeof(A_UINT32))) +/* minimum allocation for a credit message */ +//#define MIN_CREDIT_BUFFER_ALLOC_SIZE (A_ROUND_UP(MIN_BUF_SIZE_FOR_RPTS, A_CACHE_LINE_SIZE)) +#define MIN_CREDIT_BUFFER_ALLOC_SIZE (MIN_BUF_SIZE_FOR_RPTS) +/* max ctrl buffers size for a setup message */ +//#define MAX_HTC_SETUP_MSG_SIZE (128 + 64) /* meta data + 64 byte response message */ +#define MAX_HTC_SETUP_MSG_SIZE 64 /* The max size of USB command/event pipe is 64 bytes */ + +/* check size for trailer space */ +#define HTC_CTRL_BUFFER_CHECK_SIZE (MIN_BUF_SIZE_FOR_RPTS - HTC_HDR_LENGTH) + +#define HTC_DEFAULT_NUM_CTRL_BUFFERS 6 + +#define HTC_DEFAULT_MAX_EP_PENDING_CREDIT_REPORTS 3 /* an EP should not have more than this many outstanding reports */ + +#define HTC_FLAGS_CRPT_EP_MASK 0x1F /* if the message is a credit report this is the endpoint + that issued it */ + +#define HTC_FLAGS_CREDIT_RPT (1 << 5) /* the buffer was a credit report */ +#define HTC_FLAGS_BUF_HDR (1 << 6) /* the buffer was manipulated and a header added */ +#define HTC_FLAGS_RECV_END_MSG (1 << 7) /* this buffer is the last buffer for the recev + message (used for recv pause logic) */ + +#define HTC_MAILBOX 0 /* we use mailbox 0 for all communications */ +#define HTC_ANY_ENDPOINT_MASK 0xFFFFFFFF +#define HTC_LOOKAHEAD_POST_VALID 0x55 +#define HTC_LOOKAHEAD_PRE_VALID 0xAA +#define MAX_HTC_CREDITS 255 + +typedef struct _HTC_ENDPOINT { + A_INT16 CreditsToReturn; /* credits that are ready to be returned to the host */ + HTC_SERVICE *pService; /* service that is bound to this endpoint */ + //VBUF *pRcvPausedQueueHead; /* paused queue head and tail */ + //VBUF *pRcvPausedQueueTail; +#ifdef HTC_PAUSE_RESUME_REF_COUNTING + int PauseRefCount; /* reference count */ +#endif + A_INT16 CreditReturnThreshhold; /* threshold before credits are returned via NULL pkts, + this reduces dribbling effect */ + A_INT16 CreditsConsumed; /* number of credits consumed (outstanding) on the endpoint */ + A_UINT16 ConnectionFlags; /* HTC connection flags */ + int PendingCreditReports; /* no. of pending credit reports issued by this endpoint */ + A_UINT8 DownLinkPipeID; /* The pipe ID to be use for the direction: target -> host */ + A_UINT8 UpLinkPipeID; /* The pipe ID to be use for the direction: host -> target */ +} HTC_ENDPOINT; + +typedef struct _HTC_CONTEXT { + adf_os_handle_t OSHandle; + HTC_ENDPOINT Endpoints[ENDPOINT_MAX]; /* endpoint state structs */ + A_UINT32 EpHostNeedsCreditMap; /* credit update bit map for all EPs */ + A_UINT32 EpCreditPendingMap; /* credits pending bit map for all EPs */ + A_UINT32 EpRecvPausedMap; /* recv pause state bit map for all EPs */ + HTC_ENDPOINT_ID CurrentEpIndex; /* current unused endpoint index */ + HTC_SERVICE HTCControlService; /* the pseudo service that handles EP0 traffic */ + HTC_SERVICE *pServiceList; /* the service list */ + int RecvBufferSize; /* the length of each recv buffer that HTC is given */ + A_UINT32 StateFlags; /* state flags */ + HTC_SETUP_COMPLETE_CB SetupCompleteCb; /* caller supplied setup completion routine */ + int TotalCredits; /* total credits in system */ + int TotalCreditsAssigned; + int NumBuffersForCreditRpts; /* number of control buffers for credit reports */ + int CtrlBufferAllocSize; /* length of allocation */ + A_UINT8 *pCtrlBuffer; /* control buffer to be carved up for messages */ + int MaxEpPendingCreditRpts; /* maximum number of pending credit reports that any 1 EP can have */ + hif_handle_t hifHandle; + pool_handle_t PoolHandle; + + // Left a door for extension the structure + void *pReserved; +} HTC_CONTEXT; + +#define HTC_STATE_SETUP_COMPLETE (1 << 0) /* HTC host-target setup is complete */ +#define HTC_SEND_CREDIT_UPDATE_SOON (1 << 1) /* Credit update message needs to be sent */ +#define HTC_STATE_BUFF_REALLOC (1 << 2) /* buffers have been reallocated for credit messages */ + +#endif /*HTC_INTERNAL_H_*/ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/Magpie_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/Magpie_api.h new file mode 100755 index 0000000..e725fff --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/Magpie_api.h @@ -0,0 +1,201 @@ +/* + * @File: Magpie_api.h + * + * @Abstract: Magpie FW api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _MAGPIE_API_H +#define _MAGPIE_API_H + +#define MAGPIE_FW_BUILD + +#include "cmnos_api.h" +#ifdef MAGPIE_FW_BUILD +#include "vbuf_api.h" +#include "vdesc_api.h" +#include "usbfifo_api.h" +//#include "allocram_api.h" +#endif + +#include "hif_api.h" +#include "htc_api.h" +#include "wmi_svc_api.h" +#include "buf_pool_api.h" +#include "dma_engine_api.h" +#include "dma_lib.h" +#if SYSTEM_MODULE_SFLASH +#include "sflash_api.h" +#endif + +#define A_INDIR(sym) _A_MAGPIE_INDIRECTION_TABLE->sym + +#if SYSTEM_MODULE_DBG +/* debug Support */ +#define DBG_MODULE_INSTALL() cmnos_dbg_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dbg) +#define A_DBG_INIT() A_INDIR(dbg._dbg_init()) +#define A_DBG_TASK() A_INDIR(dbg._dbg_task()) +#else +#define A_DBG_INIT() +#define A_DBG_TASK() +#endif + +/* Serial Flash support */ +#define SFLASH_MODULE_INSTALL() cmnos_sflash_module_install(&_A_MAGPIE_INDIRECTION_TABLE->sflash) +#define A_SFLASH_INIT() A_INDIR(sflash._sflash_init()) +#define A_SFLASH_ERASE(erase_type, addr) A_INDIR(sflash._sflash_erase(erase_type, addr)) +#define A_SFLASH_PROG(addr, len, buf) A_INDIR(sflash._sflash_program(addr, len, buf)) +#define A_SFLASH_READ(fast, addr, len, buf) A_INDIR(sflash._sflash_read(fast, addr, len, buf)) +#define A_SFLASH_RDSR() A_INDIR(sflash._sflash_rdsr()) + + +/* DMA Engine Interface */ +#define DMA_ENGINE_MODULE_INSTALL() dma_engine_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_engine); +#define DMA_Engine_init() A_INDIR(dma_engine._init()) +#define DMA_Engine_config_rx_queue(q, nDesc, size) A_INDIR(dma_engine._config_rx_queue(q, nDesc, size)) +#define DMA_Engine_xmit_buf(q, buf) A_INDIR(dma_engine._xmit_buf(q, buf)) +#define DMA_Engine_flush_xmit(q) A_INDIR(dma_engine._flush_xmit(q)) +#define DMA_Engine_reap_recv_buf(q) A_INDIR(dma_engine._reap_recv_buf(q)) +#define DMA_Engine_return_recv_buf(q,buf) A_INDIR(dma_engine._return_recv_buf(q, buf)) +#define DMA_Engine_reap_xmited_buf(q) A_INDIR(dma_engine._reap_xmited_buf(q)) +#define DMA_Engine_swap_data(desc) A_INDIR(dma_engine._swap_data(desc)) +#define DMA_Engine_init_rx_queue(q) A_INDIR(dma_engine._init_rx_queue(q)) +#define DMA_Engine_init_tx_queue(q) A_INDIR(dma_engine._init_tx_queue(q)) +#define DMA_Engine_has_compl_packets(q) A_INDIR(dma_engine._has_compl_packets(q)) +#define DMA_Engine_desc_dump(q) A_INDIR(dma_engine._desc_dump(q)) +#define DMA_Engine_get_packet(q) A_INDIR(dma_engine._get_packet(q)) +#define DMA_Engine_reclaim_packet(q,desc) A_INDIR(dma_engine._reclaim_packet(q,desc)) +#define DMA_Engine_put_packet(q,desc) A_INDIR(dma_engine._put_packet(q,desc)) + +/*DMA Library support for GMAC & PCI(E)*/ +#define DMA_LIB_MODULE_INSTALL() dma_lib_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_lib) +#define dma_lib_tx_init(eng_no, if_type) A_INDIR(dma_lib.tx_init(eng_no, if_type)) +#define dma_lib_rx_init(eng_no, if_type) A_INDIR(dma_lib.rx_init(eng_no, if_type)) +#define dma_lib_rx_config(eng_no, desc, gran) A_INDIR(dma_lib.rx_config(eng_no, desc, gran)) +#define dma_lib_tx_start(eng_no) A_INDIR(dma_lib.tx_start(eng_no)) +#define dma_lib_rx_start(eng_no) A_INDIR(dma_lib.rx_start(eng_no)) +#define dma_lib_intr_status(if_type) A_INDIR(dma_lib.intr_status(if_type)) +#define dma_lib_hard_xmit(eng_no, buf) A_INDIR(dma_lib.hard_xmit(eng_no, buf)) +#define dma_lib_flush_xmit(eng_no) A_INDIR(dma_lib.flush_xmit(eng_no)) +#define dma_lib_xmit_done(eng_no) A_INDIR(dma_lib.xmit_done(eng_no)) +#define dma_lib_reap_xmitted(eng_no) A_INDIR(dma_lib.reap_xmitted(eng_no)) +#define dma_lib_reap_recv(eng_no) A_INDIR(dma_lib.reap_recv(eng_no)) +#define dma_lib_return_recv(eng_no, buf) A_INDIR(dma_lib.return_recv(eng_no, buf)) +#define dma_lib_recv_pkt(eng_no) A_INDIR(dma_lib.recv_pkt(eng_no)) + +/* HIF support */ +#define HIF_MODULE_INSTALL() generic_hif_module_install(&_A_MAGPIE_INDIRECTION_TABLE->hif) +#define HIF_init(pConfig) A_INDIR(hif._init(pConfig)) +#define HIF_shutdown(h) A_INDIR(hif._shutdown(h)) +#define HIF_register_callback(h, pConfig) A_INDIR(hif._register_callback(h, pConfig)) +#define HIF_start(h) A_INDIR(hif._start(h)) +#define HIF_config_pipe(h, pipe, desc_list) A_INDIR(hif._config_pipe(h, pipe, desc_list)) +#define HIF_send_buffer(h, pipe, buf) A_INDIR(hif._send_buffer(h, pipe, buf)) +#define HIF_return_recv_buf(h, pipe, buf) A_INDIR(hif._return_recv_buf(h, pipe, buf)) +#define HIF_isr_handler(h) A_INDIR(hif._isr_handler(h)) +#define HIF_is_pipe_supported(h, pipe) A_INDIR(hif._is_pipe_supported(h, pipe)) +#define HIF_get_max_msg_len(h, pipe) A_INDIR(hif._get_max_msg_len(h, pipe)) +#define HIF_get_reserved_headroom(h) A_INDIR(hif._get_reserved_headroom(h)) +#define HIF_get_default_pipe(h,u,d) A_INDIR(hif._get_default_pipe(h,u,d)) + +/* VBUF APIs */ +#ifdef MAGPIE_FW_BUILD +#define VBUF_MODULE_INSTALL() vbuf_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vbuf) +#define VBUF_init(nBuf) A_INDIR(vbuf._init(nBuf)) +#define VBUF_alloc_vbuf() A_INDIR(vbuf._alloc_vbuf()) +#define VBUF_free_vbuf(buf) A_INDIR(vbuf._free_vbuf(buf)) +#endif + +/* VDESC APIs */ +#ifdef MAGPIE_FW_BUILD +#define VDESC_MODULE_INSTALL() vdesc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vdesc) +#define VDESC_init(nDesc) A_INDIR(vdesc._init(nDesc)) +#define VDESC_alloc_vdesc() A_INDIR(vdesc._alloc_vdesc()) +#define VDESC_get_hw_desc(desc) A_INDIR(vdesc._get_hw_desc(desc)) +#define VDESC_swap_vdesc(dst, src) A_INDIR(vdesc._swap_vdesc(dst, src)) +#endif + +#define HTC_MODULE_INSTALL() htc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->htc) +#define HTC_init(SetupComplete, pConfig) A_INDIR(htc._HTC_Init(SetupComplete, pConfig)) +#define HTC_Shutdown(h) A_INDIR(htc._HTC_Shutdown(h)) +#define HTC_RegisterService(h, s) A_INDIR(htc._HTC_RegisterService(h, s)) +#define HTC_Ready(h) A_INDIR(htc._HTC_Ready(h)) +#define HTC_SendMsg(h, endpt, buf) A_INDIR(htc._HTC_SendMsg(h, endpt, buf)) +#define HTC_ReturnBuffers(h, endpt, buf) A_INDIR(htc._HTC_ReturnBuffers(h, endpt, buf)) +#define HTC_ReturnBuffersList(h, endpt, hd) A_INDIR(htc._HTC_ReturnBuffersList(h, endpt, hd)) +#define HTC_GetReservedHeadroom(h) A_INDIR(htc._HTC_GetReservedHeadroom(h)) + +#define HTC_NotifyTargetInserted(h) +#define HTC_NotifyTargetDetached(h) + +/* WMI SVC module */ +#define WMI_SERVICE_MODULE_INSTALL() WMI_service_module_install(&_A_MAGPIE_INDIRECTION_TABLE->wmi_svc_api) +#define WMI_Init(pCfg) A_INDIR(wmi_svc_api._WMI_Init(pCfg)) +#define WMI_RegisterDispatchTable(h,pT) A_INDIR(wmi_svc_api._WMI_RegisterDispatchTable(h, pT)) +#define WMI_AllocEvent(h,ec,len) A_INDIR(wmi_svc_api._WMI_AllocEvent(h, ec, len)) +#define WMI_SendEvent(h,ev,id,seq,len) A_INDIR(wmi_svc_api._WMI_SendEvent(h, ev, id, seq, len)) +#define WMI_GetPendingEventsCount() A_INDIR(wmi_svc_api._WMI_GetPendingEventsCount()) +#define WMI_GetControlEp() A_INDIR(wmi_svc_api._WMI_GetControlEp()) +#define WMI_SendCompleteHandler(ep, buf) A_INDIR(wmi_svc_api._WMI_SendCompleteHandler(ep, buf)) +#define WMI_Shutdown(h) A_INDIR(wmi_svc_api._WMI_Shutdown(h)) + +/* USB FIFO module */ +#define USBFIFO_MODULE_INSTALL() usbfifo_module_install(&_A_MAGPIE_INDIRECTION_TABLE->usbfifo_api) +#define USBFIFO_init(pConfig) A_INDIR(usbfifo_api._init(pConfig)) +#define USBFIFO_enable_event_isr() A_INDIR(usbfifo_api._enable_event_isr()) + +/* BUF pool module */ +#define BUF_POOL_MODULE_INSTALL() buf_pool_module_install(&_A_MAGPIE_INDIRECTION_TABLE->buf_pool) +#define BUF_Pool_init(h) A_INDIR(buf_pool._init(h)) +#define BUF_Pool_shutdown(h) A_INDIR(buf_pool._shutdown(h)) +#define BUF_Pool_create_pool(h, id, nItems, nSize) A_INDIR(buf_pool._create_pool(h, id, nItems, nSize)) +#define BUF_Pool_alloc_buf(h, id, reserve) A_INDIR(buf_pool._alloc_buf(h, id, reserve)) +#define BUF_Pool_alloc_buf_align(h, id, reserve,align) A_INDIR(buf_pool._alloc_buf_align(h, id, reserve,align)) +#define BUF_Pool_free_buf(h, id, buf) A_INDIR(buf_pool._free_buf(h, id, buf)) + +/* + * This defines the layout of the indirection table, which + * is used to access exported APIs of various modules. The + * layout is shared across ROM and RAM code. RAM code may + * call into ROM and ROM code may call into RAM. Because + * of the latter, existing offsets must not change for the + * lifetime of a revision of ROM; but new members may be + * added at the end. + */ +typedef struct _A_magpie_indirection_table { + _A_cmnos_indirection_table_t cmnos; + +//#if SYSTEM_MODULE_DBG + struct dbg_api dbg; // move to firmware not in cmnos +//#endif + struct hif_api hif; + struct htc_apis htc; + WMI_SVC_APIS wmi_svc_api; + struct usbfifo_api usbfifo_api; + struct buf_pool_api buf_pool; +#ifdef MAGPIE_FW_BUILD + struct vbuf_api vbuf; + struct vdesc_api vdesc; + struct allocram_api allocram; +#endif + struct dma_engine_api dma_engine; + struct dma_lib_api dma_lib; + +// structure to be added after this.... + struct sflash_api sflash; +} _A_magpie_indirection_table_t; + +extern _A_magpie_indirection_table_t _indir_tbl; +#define _A_MAGPIE_INDIRECTION_TABLE_SIZE sizeof(_A_magpie_indirection_table_t) +#if defined(__mips__) +#define _A_MAGPIE_INDIRECTION_TABLE ((_A_magpie_indirection_table_t *)0x700) +#else +#define _A_MAGPIE_INDIRECTION_TABLE (&_indir_tbl) +#endif + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/athos_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/athos_api.h new file mode 100755 index 0000000..ea658fe --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/athos_api.h @@ -0,0 +1,188 @@ +#ifndef __ATHOS_API_H__ +#define __ATHOS_API_H__ + +/* + * This file contains wrappers to OS operating system functions + * that are available in the Athos version of the operating system. + * + * Target software must always use these wrappers to access OS + * services -- it may not access any OS services directly. + * + * These wrappers are intended to provide OS-independence for applications. + * Using this header file, an application should be able to compile and + * fully link without any other OS header files, source files, or + * binary files. + */ + +#include +#include "dt_defs.h" +#include "cmnos_api.h" +//#include "HIF_api.h" +//#include "vbuf_api.h" +//#include "vdesc_api.h" +//#include "htc_api.h" +#include "Magpie_api.h" + +/* ROM Patch API */ + + +/* HTC API */ + + +/* WMI Adaptive API - required for WMI SVCs as they refer some of them*/ + + +/* WLAN WMI API - required for WMI SVCs and others...*/ + +#if 0 +#define A_INDIR(sym) _A_OS_INDIRECTION_TABLE->sym + +/* HIF support */ +#define HIF_MODULE_INSTALL() hif_module_install(&_A_OS_INDIRECTION_TABLE->hif) +#define HIF_init(pConfig) A_INDIR(hif._init(pConfig)) +#define HIF_start() A_INDIR(hif._start()) +#define HIF_config_pipe(pipe, desc_list) A_INDIR(hif._config_pipe(pipe, desc_list)) +#define HIF_send_buffer(pipe, buf) A_INDIR(hif._send_buffer(pipe, buf)) +#define HIF_return_recv_buf(pipe, buf) A_INDIR(hif._return_recv_buf(pipe, buf)) +#define HIF_isr_handler() A_INDIR(hif._isr_handler()) +#define HIF_is_pipe_supported(pipe) A_INDIR(hif._is_pipe_supported(pipe)) + +/* VBUF APIs */ +#define VBUF_MODULE_INSTALL() vbuf_module_install(&_A_OS_INDIRECTION_TABLE->vbuf) +#define VBUF_init(dataAddr, nBuf) A_INDIR(vbuf._init(dataAddr, nBuf)) +#define VBUF_alloc_vbuf() A_INDIR(vbuf._alloc_vbuf()) +#define VBUF_free_vbuf(buf) A_INDIR(vbuf._free_vbuf(buf)) + +/* VDESC APIs */ +#define VDESC_MODULE_INSTALL() vdesc_module_install(&_A_OS_INDIRECTION_TABLE->vdesc) +#define VDESC_init(dataAddr, nTxDesc, nRxDesc) A_INDIR(vdesc._init(dataAddr, nTxDesc, nRxDesc)) +#define VDESC_alloc_vdesc(type) A_INDIR(vdesc._alloc_vdesc(type)) +#define VDESC_get_hw_desc(type, desc) A_INDIR(vdesc._get_hw_desc(type, desc)) +//#define VDESC_free_vdesc(buf) A_INDIR(vdesc._free_vdesc(buf)) + +#define HTC_MODULE_INSTALL() htc_module_install(&_A_OS_INDIRECTION_TABLE->htc) +//#define HTC_init(dataAddr, SetupComplete, RecvBufferSize) A_INDIR(htc._HTC_Init(dataAddr, SetupComplete, RecvBufferSize)) +#define HTC_init(dataAddr, SetupComplete, pConfig) A_INDIR(htc._HTC_Init(dataAddr, SetupComplete, pConfig)) +#define HTC_RegisterService(s) A_INDIR(htc._HTC_RegisterService(s)) +#define HTC_Ready() A_INDIR(htc._HTC_Ready()) +#define HTC_SendMsg(endpt, buf) A_INDIR(htc._HTC_SendMsg(endpt, buf)) +#define HTC_ReturnBuffers(endpt, buf) A_INDIR(htc._HTC_ReturnBuffers(endpt, buf)) + +#if 0 +/* WMI SVC module */ +#define WMI_SERVICE_MODULE_INSTALL() WMI_service_module_install(&_A_OS_INDIRECTION_TABLE->wmi_svc_api) +#define WMI_Init(dataAddr, pCfg) A_INDIR(wmi_svc_api._WMI_Init(dataAddr, pCfg)) +#define WMI_RegisterDispatchTable(pT) A_INDIR(wmi_svc_api._WMI_RegisterDispatchTable(pT)) +#define WMI_AllocEvent(ec,len) A_INDIR(wmi_svc_api._WMI_AllocEvent(ec, len)) +#define WMI_SendEvent(ev,id,seq,len) A_INDIR(wmi_svc_api._WMI_SendEvent(ev, id, seq, len)) +#define WMI_GetPendingEventsCount() A_INDIR(wmi_svc_api._WMI_GetPendingEventsCount()) +#define WMI_GetControlEp() A_INDIR(wmi_svc_api._WMI_GetControlEp()) +#define WMI_SendCompleteHandler(ep, buf) A_INDIR(wmi_svc_api._WMI_SendCompleteHandler(ep, buf)) +#endif + +/* + * This defines the layout of the indirection table, which + * is used to access exported APIs of various modules. The + * layout is shared across ROM and RAM code. RAM code may + * call into ROM and ROM code may call into RAM. Because + * of the latter, existing offsets must not change for the + * lifetime of a revision of ROM; but new members may be + * added at the end. + */ +typedef struct _A_athos_indirection_table { + _A_cmnos_indirection_table_t cmnos; + + /* TBD: to be added */ + struct hif_api hif; + struct vbuf_api vbuf; + struct vdesc_api vdesc; + struct htc_apis htc; + //WMI_SVC_APIS wmi_svc_api; +} _A_athos_indirection_table_t; + +#if 1 +extern _A_athos_indirection_table_t _indir_tbl; +#define _A_OS_INDIRECTION_TABLE_SIZE sizeof(_A_athos_indirection_table_t) +#define _A_OS_INDIRECTION_TABLE (&_indir_tbl) +#endif +#endif + +extern unsigned int _data_start_in_rom; +extern unsigned int _data_start; +extern unsigned int _data_end; +extern unsigned int _bss_start; +extern unsigned int _bss_end; +extern unsigned int _stack_sentry; +extern unsigned int __stack; +extern unsigned int _fw_image_end; + +#if defined(__XTENSA__) +#define START_DATA _data_start +#define END_DATA _data_end +#define START_BSS _bss_start +#define END_BSS _bss_end + +#define STACK_START _stack_sentry +#define STACK_END __stack +#endif + + +struct _A_os_linkage_check { + int version; + int table; +}; + + +/* + * A_INIT() handles any initialization needed by the OS abstraction, + * and it clears the application's BSS, if necessary. (Application BSS + * is not cleared if the application is linked into a single image that + * includes AthOS.) + * + * A_INIT() must be called first thing in the application (from app_start) + * in order to guarantee that BSS has been cleared properly. + */ +static INLINE int +A_INIT(void) +{ + struct _A_os_linkage_check link_check; + unsigned int *clrptr; + + if (&START_BSS != _A_MAGPIE_INDIRECTION_TABLE->cmnos.start_bss) { + /* Clear BSS */ + for (clrptr = &START_BSS; clrptr < &END_BSS; clrptr++) { + *clrptr = 0; + } + } + + { + /* Copy writable data from flash to RAM. */ + unsigned int *srcptr, *destptr; + + /* + * The _data_start symbol points to the start of data IN FLASH. + * It is defined by flash.ld at application link time. If flash.ld + * is not used, it is defined (on the link line) as 0. + */ + static int *data_start_addr = &_data_start; + + if (data_start_addr != 0) { + for (srcptr = &_data_start, destptr = &START_DATA; + destptr < &END_DATA; + srcptr++, destptr++) + { + *destptr = *srcptr; + } + } + } + +#define OS_LINKAGE_VERSION 4 + link_check.version = OS_LINKAGE_VERSION; + link_check.table = _A_MAGPIE_INDIRECTION_TABLE_SIZE; + + return A_CMN(hal_linkage_check(sizeof(link_check), &link_check)); +} + + +#endif /* __ATHOS_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/magpie/reg_defs.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/magpie/reg_defs.h new file mode 100755 index 0000000..bdf6893 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/magpie/reg_defs.h @@ -0,0 +1,251 @@ +/*************************************************************************/ +/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : reg_defs.h */ +/* */ +/* Abstract */ +/* This file contains the register addr and marco definition. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ +#ifndef _REG_DEFS_H_ +#define _REG_DEFS_H_ + +#include "dt_defs.h" + +#define BIT_SET(bit) (1<>2)) + +#endif /* _MEM_ADDRS_H_ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/magpie_regdump.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/magpie_regdump.h new file mode 100755 index 0000000..6a599f8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/magpie_regdump.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2006 Atheros Communications Inc. + * All rights reserved. + */ + +#ifndef __MAGPIE_REGDUMP_H__ +#define __MAGPIE_REGDUMP_H__ + +#if !defined(__ASSEMBLER__) +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ +struct XTensa_exception_frame_s { + uint32_t xt_pc; + uint32_t xt_ps; + uint32_t xt_sar; + uint32_t xt_vpri; + uint32_t xt_a2; + uint32_t xt_a3; + uint32_t xt_a4; + uint32_t xt_a5; + uint32_t xt_exccause; + uint32_t xt_lcount; + uint32_t xt_lbeg; + uint32_t xt_lend; + + /* Extra info to simplify post-mortem stack walkback */ +#define MAGPIE_REGDUMP_FRAMES 5 + struct { + uint32_t a0; /* pc */ + uint32_t a1; /* sp */ + uint32_t a2; + uint32_t a3; + } wb[MAGPIE_REGDUMP_FRAMES]; +}; + +typedef struct XTensa_exception_frame_s CPU_exception_frame_t; +#define RD_SIZE sizeof(CPU_exception_frame_t) + +#endif +#endif /* __MAGPIE_REGDUMP_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/opt_ah.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/opt_ah.h new file mode 100755 index 0000000..eeec53d --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/opt_ah.h @@ -0,0 +1,8 @@ +#define AH_SUPPORT_AR5416 1 +#define AH_SUPPORT_2133 1 +#define AH_SUPPORT_5413 1 +//#define AH_DEBUG 1 +//#define AR5416_EMULATION 1 +#define ATH_FORCE_PPM 1 +#define ATH_FORCE_BIAS 1 +#define AH_SUPPORT_DFS 1 diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/regdump.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/regdump.h new file mode 100755 index 0000000..6b8df63 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/regdump.h @@ -0,0 +1,33 @@ +#ifndef __REGDUMP_H__ +#define __REGDUMP_H__ + +#include "magpie_regdump.h" + + +#if !defined(__ASSEMBLER__) + +/* + * XTensa CPU state + * This must match the state saved by the target exception handler. + */ + +#define RD_SIZE sizeof(CPU_exception_frame_t) + +/* + * Target CPU state at the time of failure is reflected + * in a register dump, which the Host can fetch through + * the diagnostic window. + */ +struct register_dump_s { + uint32_t target_id; /* Target ID */ + uint32_t assline; /* Line number (if assertion failure) */ + uint32_t pc; /* Program Counter at time of exception */ + uint32_t badvaddr; /* Virtual address causing exception */ + CPU_exception_frame_t exc_frame; /* CPU-specific exception info */ + + /* Could copy top of stack here, too.... */ +}; + + +#endif /* __ASSEMBLER__ */ +#endif /* __REGDUMP_H__ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/sys_cfg.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/sys_cfg.h new file mode 100755 index 0000000..c2a2092 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/inc/sys_cfg.h @@ -0,0 +1,67 @@ +/*************************************************************************/ +/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : sys_cfg.h */ +/* */ +/* Abstract */ +/* This file contains definition of platform and sysmte config . */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _SYS_CFG_H_ +#define _SYS_CFG_H_ + +/************************** FPGA version **************************/ +#define MAGPIE_FPGA_RAM_256K 1 + +/************************** ROM DEFINE ***************************/ + +#if defined(_ROM_) +#include "rom_cfg.h" + +#if MAGPIE_FPGA_RAM_256K == 1 +#undef MAX_BUF_NUM +#define MAX_BUF_NUM 100 +#endif + +#elif defined(_RAM_) + +#include "rom_cfg.h" +#include "magpie_mem.h" + +/************************* Resource DEFS ***********************/ +#define MAX_DESC_NUM 100 + +#ifdef RX_SCATTER +#define MAX_BUF_NUM 60 +#else +#define MAX_BUF_NUM 40 +#endif + +#if MAGPIE_FPGA_RAM_256K == 1 +#undef MAX_BUF_NUM +#define MAX_BUF_NUM 100 +#endif + +#undef SYSTEM_MODULE_DBG +#define SYSTEM_MODULE_DBG 1 + +/************************* WLAN DEFS ***************************/ +#define MAGPIE_ENABLE_WLAN 1 +#define MAGPIE_ENABLE_PCIE 1 +#define MAGPIE_ENABLE_WLAN_IN_TARGET 0 +#define MAGPIE_ENABLE_WLAN_SELF_TX 0 +#define MAGPIE_ENABLE_WLAN_RATE_CTRL 1 +#define WLAN_MAX_RXBUF 15 +#define WLAN_MAX_TXBUF 10 + +/****************************** WATCH DOG *******************************/ +#define WDT_DEFAULT_TIMEOUT_VALUE 3*ONE_MSEC*1000 // Initial value is 3 seconds, firmware changes it to 65 milliseconds + +#endif + + +#endif /* _SYS_CFG_H_ */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/Makefile new file mode 100755 index 0000000..f2f8552 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/Makefile @@ -0,0 +1,60 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export SSNAME = vbuf + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libvbuf.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/Makefile.ss new file mode 100755 index 0000000..fafc020 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/Makefile.ss @@ -0,0 +1,45 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/vbuf.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/inc/vbuf_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/inc/vbuf_api.h new file mode 100755 index 0000000..6119eb5 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/inc/vbuf_api.h @@ -0,0 +1,46 @@ +/* + * @File: VBUF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _VBUF_API_H +#define _VBUF_API_H + +#include + +#define MAX_BUF_CTX_LEN 20 + +typedef struct _VBUF +{ + VDESC *desc_list; + struct _VBUF *next_buf; + A_UINT16 buf_length; + A_UINT8 reserved[2]; + A_UINT8 ctx[MAX_BUF_CTX_LEN]; + //A_UINT8 end_point; + //A_UINT8 reserved[1]; +} VBUF; + +#define VBUF_GET_DATA_ADDR(vbuf) (vbuf->desc_list->buf_addr + vbuf->desc_list->data_offset) + +/* hardware API table structure (API descriptions below) */ +struct vbuf_api { + void (*_init)(int nBuf); + VBUF* (*_alloc_vbuf)(void); + VBUF* (*_alloc_vbuf_with_size)(int size, int reserve); + void (*_free_vbuf)(VBUF *buf); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void vbuf_module_install(struct vbuf_api *apis); + +#endif /* #ifndef _HIF_API_H */ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/src/vbuf.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/src/vbuf.c new file mode 100755 index 0000000..581bdaa --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/src/vbuf.c @@ -0,0 +1,94 @@ +/* + * @File: vbuf.c + * + * @Abstract: + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + + +#include +#include +#include + +#include "vbuf.h" + +#define VBUF_SIZE sizeof(VBUF) + +struct VBUF_CONTEXT g_vbufCtx; + +void _vbuf_init(int nBuf); +VBUF* _vbuf_alloc_vbuf(void); +void _vbuf_free_vbuf(VBUF *buf); + +void _vbuf_init(int nBuf) +{ + int i; + VBUF *vbuf; + + //vbuf = (VBUF*)dataAddr; + vbuf = (VBUF*)A_ALLOCRAM(VBUF_SIZE); + vbuf->next_buf = NULL; + vbuf->desc_list = NULL; + + g_vbufCtx.free_buf_head = vbuf; + + for(i=1; idesc_list = NULL; + vbuf->next_buf = g_vbufCtx.free_buf_head; + g_vbufCtx.free_buf_head = vbuf; + } + + g_vbufCtx.nVbufNum = nBuf; + //return (dataAddr + nBuf*VBUF_SIZE); + return; +} + +VBUF* _vbuf_alloc_vbuf(void) +{ + VBUF *allocBuf = NULL; + + if ( g_vbufCtx.free_buf_head != NULL ) + { + allocBuf = g_vbufCtx.free_buf_head; + g_vbufCtx.nVbufNum--; + + g_vbufCtx.free_buf_head = allocBuf->next_buf; + allocBuf->next_buf = NULL; + } + + return allocBuf; +} + +void _vbuf_free_vbuf(VBUF *buf) +{ + // assert buf != NULL + + buf->next_buf = g_vbufCtx.free_buf_head; + g_vbufCtx.free_buf_head = buf; + + g_vbufCtx.nVbufNum++; +} + +/* the exported entry point into this module. All apis are accessed through + * function pointers */ +void vbuf_module_install(struct vbuf_api *apis) +{ + /* hook in APIs */ + apis->_init = _vbuf_init; + apis->_alloc_vbuf = _vbuf_alloc_vbuf; + apis->_free_vbuf = _vbuf_free_vbuf; + + /* save ptr to the ptr to the context for external code to inspect/modify internal module state */ + //apis->pReserved = &g_pMboxHWContext; +} + + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/src/vbuf.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/src/vbuf.h new file mode 100755 index 0000000..d76ed03 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vbuf/src/vbuf.h @@ -0,0 +1,25 @@ +/* + * @File: + * + * @Abstract: + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef VBUF_H_ +#define VBUF_H_ + +struct VBUF_CONTEXT { + VBUF *free_buf_head; + int nVbufNum; + + // Left a door for extension the structure + void *pReserved; +}; + +#endif /*VBUF_H_*/ diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/Makefile b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/Makefile new file mode 100755 index 0000000..cae0ee1 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/Makefile @@ -0,0 +1,60 @@ +include $(MAGPIE_ROOT)/build/make_opt/Makefile.h + + +# +# Sub-system source main path +# +# !!Customize!! + +export SSNAME = vdesc + + +# +# Sub-system source main path +# + +export SSMPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME) + + +# +# Sub-system object search path for GNU tool chain +# +# !!Customize!! + +export SSOBJPATH = $(PRJ_ROOT)/$(TARGET)/$(SSNAME)/obj + + +# +# Sub-system/module list at this layer +# +# !!Customize!! + +SUBDIRS = . + + +# +# Archive for this package +# +# !!Customize!! + +export L_TARGET = $(LIB_PATH)/libvdesc.a + + +# +# Targets +# + +all: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss all || exit $?; done +# ar -rcs $(L_TARGET) `find . -name "*.o"` + + +dep: + for i in $(SUBDIRS) ; do $(MAKE) -C $$i -f Makefile.ss dep || exit $?; done + +clean: + $(MAKE) clean -f Makefile.ss + +init: + $(MAKE) -f Makefile.ss init + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/Makefile.ss b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/Makefile.ss new file mode 100755 index 0000000..c908045 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/Makefile.ss @@ -0,0 +1,44 @@ +# +# Sub-system source search path for Adjust_Dep at this dir level +# +# !!Customize!! + +export SSPATH = $(SSMPATH)/src + + +# +# Extra include paths required by this module at this directory level +# +# !!Customize!! + +EXTRA_HPATH = -I$(SSPATH) -I$(SSMPATH)/inc +#EXTRA_HPATH = + +EXTRA_CFLAGS = +EXTRA_CCFLAGS = +EXTRA_ASFLAGS = +CFLAGS += + + +# +# Search path for GNU tool chain +# + +VPATH = $(LIB_PATH):$(SSOBJPATH) + + +# +# Object list at this directory level +# +# !!Customize!! + +O_OBJS = $(SSOBJPATH)/vdesc.o + + +include $(MAGPIE_ROOT)/build/make_opt/Rules.make + +# +# The followings are automatically generated by the tool adj_dep +# + +### Dep diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/inc/vdesc_api.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/inc/vdesc_api.h new file mode 100755 index 0000000..631f134 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/inc/vdesc_api.h @@ -0,0 +1,46 @@ +/* + * @File: VBUF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _VDESC_API_H +#define _VDESC_API_H + +//#define VDESC_CONTROL_BUF_HDR (1 << 6) /* the buffer was manipulated and a header added */ + +#define MAX_HW_DESC_SIZE 20 + +typedef struct _VDESC +{ + struct _VDESC *next_desc; + A_UINT8 *buf_addr; + A_UINT16 buf_size; + A_UINT16 data_offset; + A_UINT16 data_size; + A_UINT16 control; + A_UINT8 hw_desc_buf[MAX_HW_DESC_SIZE]; +} VDESC; + +//#define VDESC_HW_TO_VDESC(hwdesc) ((VDESC *)(((A_UINT32 *)hwdesc - 4))) +#define VDESC_HW_TO_VDESC(hwdesc) ((VDESC *)(((A_UINT32 *)hwdesc - 4))) + +struct vdesc_api { + void (*_init)(int nDesc); + VDESC* (*_alloc_vdesc)(); + A_UINT8* (*_get_hw_desc)(VDESC *desc); + void (*_swap_vdesc)(VDESC *dest, VDESC *src); + //void (*_free_vdesc)(void); + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void vdesc_module_install(struct vdesc_api *apis); + +#endif diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/src/vdesc.c b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/src/vdesc.c new file mode 100755 index 0000000..5cfd7ce --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/src/vdesc.c @@ -0,0 +1,218 @@ +/* + * @File: vdesc.c + * + * @Abstract: + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + + +#include +#include +#include + +#include "vdesc.h" + +#define VDESC_SIZE sizeof(VDESC) +//#define VDESC_TX_SIZE sizeof(VDESC_TX) +//#define VDESC_RX_SIZE sizeof(VDESC_RX) + +static VDESC* alloc_rx_desc(void); +static VDESC* alloc_tx_desc(void); +void _vdesc_init(int nDesc); +A_UINT8* _vdesc_get_hw_desc(VDESC *desc); +VDESC* _vdesc_alloc_desc(); +void _vdesc_swap_vdesc(VDESC *dest, VDESC *src); + +struct VDESC_CONTEXT g_vdescCtx; + +void _vdesc_init(int nDesc) +{ + int i; + VDESC *vdesc; + //int nextAddr = dataAddr; + //int nDesc = nTxDesc + nRxDesc; + + // Initialize VDESC_TX for nTxDesc number + //vdesc = (VDESC*)dataAddr; + vdesc = (VDESC *)A_ALLOCRAM(sizeof(VDESC)); + vdesc->next_desc = NULL; + vdesc->control = 0; + +#if 1 + g_vdescCtx.free_vdesc_head = vdesc; + + for(i=1; icontrol = 0; + + vdesc->next_desc = g_vdescCtx.free_vdesc_head; + g_vdescCtx.free_vdesc_head = vdesc; + } + + //nextAddr = nextAddr + VDESC_SIZE; + //return nextAddr; + return; +#else + g_vdescCtx.free_vdesc_tx_head = vdesc; + for(i=1; icontrol = 0; + + vdesc->next_desc = g_vdescCtx.free_vdesc_tx_head; + g_vdescCtx.free_vdesc_tx_head = vdesc; + } + + nextAddr = nextAddr + VDESC_TX_SIZE; + + // Initialize VDESC_RX for nTxDesc number + vdesc = (VDESC*)nextAddr; + vdesc->next_desc = NULL; + vdesc->control = 0; + + g_vdescCtx.free_vdesc_rx_head = vdesc; + for(i=1; icontrol = 0; + + vdesc->next_desc = g_vdescCtx.free_vdesc_rx_head; + g_vdescCtx.free_vdesc_rx_head = vdesc; + } + + return (nextAddr + nRxDesc*VDESC_RX_SIZE); +#endif +} + +#if 0 +static VDESC* alloc_tx_desc(void) +{ + VDESC *allocDesc = NULL; + + if ( g_vdescCtx.free_vdesc_tx_head != NULL ) + { + allocDesc = g_vdescCtx.free_vdesc_tx_head; + + //g_vbufCtx.nVbufNum--; + + g_vdescCtx.free_vdesc_tx_head = allocDesc->next_desc; + allocDesc->next_desc = NULL; + } + + return allocDesc; +} + +static VDESC* alloc_rx_desc(void) +{ + VDESC *allocDesc = NULL; + + if ( g_vdescCtx.free_vdesc_rx_head != NULL ) + { + allocDesc = g_vdescCtx.free_vdesc_rx_head; + //g_vbufCtx.nVbufNum--; + + g_vdescCtx.free_vdesc_rx_head = allocDesc->next_desc; + allocDesc->next_desc = NULL; + } + + return allocDesc; +} +#endif + +VDESC* _vdesc_alloc_desc() +{ +#if 1 + VDESC *allocDesc = NULL; + + if ( g_vdescCtx.free_vdesc_head != NULL ) + { + allocDesc = g_vdescCtx.free_vdesc_head; + //g_vbufCtx.nVbufNum--; + + g_vdescCtx.free_vdesc_head = allocDesc->next_desc; + allocDesc->next_desc = NULL; + } + + return allocDesc; +#else + if ( type == VDESC_TYPE_RX ) + { + return alloc_rx_desc(); + } + else + { + return alloc_tx_desc(); + } +#endif +} + +A_UINT8* _vdesc_get_hw_desc(VDESC *desc) +{ +#if 1 + return desc->hw_desc_buf; +#else + if ( type == VDESC_TYPE_RX ) + { + return ((VDESC_RX*)desc)->hw_desc_buf; + } + else + { + return ((VDESC_TX*)desc)->hw_desc_buf; + } +#endif +} + +void _vdesc_swap_vdesc(VDESC *dest, VDESC *src) +{ + A_UINT32 tmp; + A_UINT8 *tmpAddr; + + tmp = dest->buf_size; + dest->buf_size = src->buf_size; + src->buf_size = tmp; + + tmp = dest->data_offset; + dest->data_offset = src->data_offset; + src->data_offset = tmp; + + tmp = dest->data_size; + dest->data_size = src->data_size; + src->data_size = tmp; + + tmp = dest->control; + dest->control = src->control; + src->control = tmp; + + tmpAddr = dest->buf_addr; + dest->buf_addr = src->buf_addr; + src->buf_addr = tmpAddr; +} + +/* the exported entry point into this module. All apis are accessed through + * function pointers */ +void vdesc_module_install(struct vdesc_api *apis) +{ + /* hook in APIs */ + apis->_init = _vdesc_init; + apis->_alloc_vdesc = _vdesc_alloc_desc; + apis->_get_hw_desc = _vdesc_get_hw_desc; + apis->_swap_vdesc = _vdesc_swap_vdesc; + + //apis->_free_vbuf = _vbuf_free_vbuf; + + /* save ptr to the ptr to the context for external code to inspect/modify internal module state */ + //apis->pReserved = &g_pMboxHWContext; +} + + diff --git a/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/src/vdesc.h b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/src/vdesc.h new file mode 100755 index 0000000..f9d2d52 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/magpie_1_1/sboot/vdesc/src/vdesc.h @@ -0,0 +1,24 @@ +/* + * @File: + * + * @Abstract: + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef VDESC_H_ +#define VDESC_H_ + +struct VDESC_CONTEXT { + VDESC *free_vdesc_head; + + // Left a door for extension the structure + void *pReserved; +}; + +#endif /*VDESC_H_*/ diff --git a/target_firmware/magpie_fw_dev/build/make_opt/Makefile.h b/target_firmware/magpie_fw_dev/build/make_opt/Makefile.h new file mode 100755 index 0000000..e59e436 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/make_opt/Makefile.h @@ -0,0 +1,48 @@ +# +# Include the make variables (CC, etc...) +# + +export XTENSA_TOOL_INSTALLED=1 + +ifeq ($(XTENSA_TOOLS_ROOT),) +XTENSA_TOOL_INSTALLED=0 +export XTENSA_INSTALL_PATH=$(PWD)/../../../../../../toolchain +export XTENSA_CORE=Magpie_P0 +export LM_LICENSE_FILE=27020@us1-lic1:1718@xia:27020@zydasfs +export XTENSA_TOOLS_ROOT=$(XTENSA_INSTALL_PATH)/inst +export XTENSA_ROOT=$(XTENSA_INSTALL_PATH)/builds/RB-2007.2-linux/$(XTENSA_CORE) +export XTENSA_SYSTEM=$(XTENSA_ROOT)/config +endif +export XTENSA_TOOL_INSTALLED=1 +export XCC=$(XTENSA_TOOLS_ROOT)/bin/xtensa-elf-gcc +export XLD=$(XTENSA_TOOLS_ROOT)/bin/xtensa-elf-ld +export XAR=$(XTENSA_TOOLS_ROOT)/bin/xtensa-elf-ar +export XOBJCOPY=$(XTENSA_TOOLS_ROOT)/bin/xtensa-elf-objcopy +export XOBJDUMP=$(XTENSA_TOOLS_ROOT)/bin/xtensa-elf-objdump + +export CC = $(CROSS_COMPILE)/$(TARGET_PREFIX)xcc +export AS = $(CROSS_COMPILE)/$(TARGET_PREFIX)xcc +export AR = $(CROSS_COMPILE)/$(TARGET_PREFIX)ar +export LD = $(CROSS_COMPILE)/$(TARGET_PREFIX)xcc +export NM = $(CROSS_COMPILE)/$(TARGET_PREFIX)nm +export OBJCOPY = $(CROSS_COMPILE)/$(TARGET_PREFIX)objcopy +export OBJDUMP = $(CROSS_COMPILE)/$(TARGET_PREFIX)objdump +export BIN2HEX = $(MAGPIE_ROOT)/build/utility/bin/bin2hex +export IMGHDR = $(MAGPIE_ROOT)/build/utility/bin/imghdr +export MK_SYMBOL = sh $(MAGPIE_ROOT)/build/utility/sh/make_ld.sh +export RM rm + +# +# export all these symbols for compilation +# +export CFLAGS = $(ARCH) $(DEFS) $(DFLAGS) $(CCOPTS) $(HPATH) +export CCFLAGS = $(HPATH) $(DEFS) $(DFLAGS) $(CCOPTS) +export ASFLAGS = $(ARCH) $(DEFS) $(DFLAGS) $(ASOPTS) $(HPATH) +export ARFLAGS = -rcs + +# +# Set the default value of MAGPIE_IF to usb if not specified +# +ifeq ($(MAGPIE_IF),) +MAGPIE_IF=usb +endif diff --git a/target_firmware/magpie_fw_dev/build/make_opt/Rules.make b/target_firmware/magpie_fw_dev/build/make_opt/Rules.make new file mode 100755 index 0000000..87a3bf2 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/make_opt/Rules.make @@ -0,0 +1,91 @@ +# +# This file contains rules which are shared between multiple Makefiles +# +# + +# +# Special variables which should not be exported +# + +unexport EXTRA_CFLAGS +unexport EXTRA_CCFLAGS +unexport EXTRA_ASFLAGS +unexport EXTRA_HPATH + + +# +# Common rules +# + +E=echo + +$(SSOBJPATH)/%.o: $(SSPATH)/%.c Makefile.ss + @mkdir -p ./obj + @$(CC) $(EXTRA_HPATH) $(CFLAGS) $(EXTRA_CFLAGS) -c -o $@ $< + @$(E) " CC " $(shell basename $<) + +$(SSOBJPATH)/%.o: $(SSPATH)/%.cpp Makefile.ss + @$(CPP) $(EXTRA_HPATH) $(CCFLAGS) $(EXTRA_CCFLAGS) -c -o $@ $< + @$(E) " CPP " $(shell basename $<) + +$(SSOBJPATH)/%.o: $(SSPATH)/%.s Makefile.ss + @$(AS) $(EXTRA_HPATH) $(ASFLAGS) $(EXTRA_ASFLAGS) -c -o $@ $< + @$(E) " AS " $(shell basename $<) + +$(SSOBJPATH)/%.o: $(SSPATH)/%.S Makefile.ss + @$(AS) $(EXTRA_HPATH) $(ASFLAGS) $(EXTRA_ASFLAGS) -c -o $@ $< + @$(E) " AS " $(shell basename $<) + +$(L_TARGET): $(O_OBJS) + @$(AR) $(ARFLAGS) $@ $? + @$(E) " AR " $(shell basename $@) + + +# +# Target for this sub Makefile +# + +all: $(L_TARGET) $(ASM_OBJS) + +dep: + sed '/\#\#\# Dep/q' < Makefile.ss > tmp_make + $(CC) $(EXTRA_HPATH) $(CFLAGS) $(EXTRA_CFLAGS) -MM $(SSPATH)/*.c $(ASM_OBJS:$(SSOBJPATH)/%.o=$(SSPATH)/%.S) > tmp1_file + $(MAGPIE_ROOT)/build/utility/bin/adj_dep $(SSOBJPATH)/ + cat tmp2_file >> tmp_make + mv tmp_make Makefile.ss + -rm tmp1_file + -rm tmp2_file + +clean: + @find $(SSOBJPATH) -name "*.o" -exec rm {} \; + @rm -rf obj + @if [ -f "$(L_TARGET)" ]; then rm $(L_TARGET); fi + +init: # copy/share subsystem headers file + #-mkdir $(MAGPIE_ROOT)/src/ss_hdr/$(LAYERNAME)/$(SSNAME) + #-mkdir $(MAGPIE_ROOT)/src/ss_hdr/$(LAYERNAME)/$(SSNAME)/hdr + #-cp -p $(SSMPATH)/hdr/*.h $(MAGPIE_ROOT)/src/ss_hdr/$(LAYERNAME)/$(SSNAME)/hdr + -chmod o+w $(SSPATH)/*.c + -chmod o+w $(SSPATH)/*.S + -chmod o+w $(SSPATH)/*.s + -rm $(SSPATH)/*.c + -rm $(SSPATH)/*.S + -rm $(SSPATH)/*.s + -chmod o+w $(SSMPATH)/*.c + -chmod o+w $(SSMPATH)/*.S + -chmod o+w $(SSMPATH)/*.s + -rm $(SSMPATH)/*.c + -rm $(SSMPATH)/*.S + -rm $(SSMPATH)/*.s + + +# +# test only +# +# Linux use below: +$(SSOBJPATH)/%: + $(CC) $(CFLAGS) $(EXTRA_HPATH) $(EXTRA_CFLAGS) -o $@ $(SSOBJPATH)/*.o $(LDFLAGS) +# Cygwin use below +#$(SSOBJPATH)/%: +# $(CC) $(CFLAGS) $(EXTRA_HPATH) $(EXTRA_CFLAGS) -o $@ $(SSOBJPATH)/*.o +exe: $(O_EXE) diff --git a/target_firmware/magpie_fw_dev/build/make_opt/RulesCPP.make b/target_firmware/magpie_fw_dev/build/make_opt/RulesCPP.make new file mode 100755 index 0000000..cded53f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/make_opt/RulesCPP.make @@ -0,0 +1,107 @@ +# +# This file contains rules which are shared between multiple Makefiles +# +# $Log: RulesCPP.make,v $ +# Revision 1.2 2004/06/30 08:01:08 wyatthsu +# use CPP instead of CC +# +# Revision 1.1 2003/06/26 02:14:53 dinoking +# add for dependcy of CPP files +# +# Revision 1.11 2003/06/03 14:20:29 philiphuang +# Remove warning messge for -rm *.o ..... +# +# Revision 1.10 2003/04/02 01:59:11 yhlin +# Make this file checking dependency of Makefile.ss +# +# Revision 1.9 2003/03/27 08:28:07 yhlin +# Put .S back to Rules.make. .s and .S are meanful for GCC. +# +# Revision 1.8 2003/03/26 14:39:46 yhlin +# Take off redendent rules +# +# Revision 1.7 2003/03/25 08:08:40 tedwang +# 1. Add target rule for capital .S, +# $(SSOBJPATH)/%.o: $(SSPATH)/%.S +# 2. Add target variable $(ASM_OBJS) for assembly object and dependency generation. +# +# Revision 1.6 2003/03/24 16:29:53 yhlin +# Add ability to do assembler +# +# Revision 1.5 2003/03/20 11:39:53 yhlin +# no message +# +# Revision 1.4 2003/03/17 16:08:29 yhlin +# Make sure common rule for L_TARGET is working and take off redundant rules. +# +# + +# +# Special variables which should not be exported +# + +unexport EXTRA_CFLAGS +unexport EXTRA_CCFLAGS +unexport EXTRA_ASFLAGS +unexport EXTRA_HPATH + + +# +# Common rules +# + +$(SSOBJPATH)/%.o: $(SSPATH)/%.c Makefile.ss + $(CC) $(EXTRA_HPATH) $(CFLAGS) $(EXTRA_CFLAGS) -c -o $@ $< + $(MAGPIE_ROOT)/build/utility/bin/adj_time $(L_TARGET) $@ + +$(SSOBJPATH)/%.o: $(SSPATH)/%.cpp Makefile.ss + $(CPP) $(EXTRA_HPATH) $(CCFLAGS) $(EXTRA_CCFLAGS) -c -o $@ $< + $(MAGPIE_ROOT)/build/utility/bin/adj_time $(L_TARGET) $@ + +$(SSOBJPATH)/%.o: $(SSPATH)/%.s Makefile.ss + $(AS) $(EXTRA_HPATH) $(ASFLAGS) $(EXTRA_ASFLAGS) -c -o $@ $< + $(MAGPIE_ROOT)/build/utility/bin/adj_time $(L_TARGET) $@ + +$(SSOBJPATH)/%.o: $(SSPATH)/%.S Makefile.ss + $(AS) $(EXTRA_HPATH) $(ASFLAGS) $(EXTRA_ASFLAGS) -c -o $@ $< + $(MAGPIE_ROOT)/build/utility/bin/adj_time $(L_TARGET) $@ + +$(L_TARGET): $(O_OBJS) + $(AR) $(ARFLAGS) $@ $? + + +# +# Target for this sub Makefile +# + +all: $(L_TARGET) $(ASM_OBJS) + +dep: + sed '/\#\#\# Dep/q' < Makefile.ss > tmp_make + $(CPP) $(EXTRA_HPATH) $(CFLAGS) $(EXTRA_CFLAGS) -MM $(SSPATH)/*.cpp $(ASM_OBJS:$(SSOBJPATH)/%.o=$(SSPATH)/%.S) > tmp1_file + $(MAGPIE_ROOT)/build/utility/bin/adj_dep $(SSOBJPATH)/ + cat tmp2_file >> tmp_make + mv tmp_make Makefile.ss + -rm tmp1_file + -rm tmp2_file + +clean: + @find $(SSOBJPATH) -name "*.o" -exec rm {} \; + @if [ -f "$(L_TARGET)" ]; then rm $(L_TARGET); fi + +init: # copy/share subsystem headers file + -mkdir $(MAGPIE_ROOT)/src/ss_hdr/$(LAYERNAME)/$(SSNAME) + -mkdir $(MAGPIE_ROOT)/src/ss_hdr/$(LAYERNAME)/$(SSNAME)/hdr + -cp -p $(SSMPATH)/hdr/*.h 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exit(1); + } + + while (fgets(line_in_buf, BUF_LEN, file_in) != NULL) + { + if (line_in_buf[0] != ' ') + { + strcpy(line_out_buf, argv[1]); + strcat(line_out_buf, line_in_buf); + } + else + { + strcpy(line_out_buf, line_in_buf); + } + + fputs(line_out_buf, file_out); + } + + fclose(file_in); + fclose(file_out); +} diff --git a/target_firmware/magpie_fw_dev/build/utility/adjust_time/Makefile b/target_firmware/magpie_fw_dev/build/utility/adjust_time/Makefile new file mode 100755 index 0000000..779f010 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/adjust_time/Makefile @@ -0,0 +1,10 @@ +TARGET = ../bin/adj_time # for Linux environment +#TARGET = ../bin/adj_time.exe # for CygWin environment + +all: $(TARGET) + +$(TARGET): + gcc -o $(TARGET) adj_time.c + +clean: + -rm $(TARGET) diff --git a/target_firmware/magpie_fw_dev/build/utility/adjust_time/adj_time.c b/target_firmware/magpie_fw_dev/build/utility/adjust_time/adj_time.c new file mode 100755 index 0000000..367231f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/adjust_time/adj_time.c @@ -0,0 +1,39 @@ +#include +#include +#include +#include + +#define FILE_NAME_LEN 256 + + +int main(int argc, char **argv) +{ + char ar_file_name[FILE_NAME_LEN], obj_file_name[FILE_NAME_LEN]; + + struct stat ar_file_stat, obj_file_stat; + + struct utimbuf obj_file_utb; + + if (argc != 3) + { + printf("\nUsage: adj_time archive_file obj_file\n"); + } + else + { + strcpy(ar_file_name, argv[1]); + strcpy(obj_file_name, argv[2]); + + stat(ar_file_name, &ar_file_stat); + stat(obj_file_name, &obj_file_stat); + + if (ar_file_stat.st_mtime == obj_file_stat.st_mtime) + { + obj_file_utb.actime = obj_file_stat.st_atime; + obj_file_utb.modtime = obj_file_stat.st_mtime + 1; + + utime(obj_file_name, &obj_file_utb); + } + } + + exit(0); +} diff --git a/target_firmware/magpie_fw_dev/build/utility/athfw2lnx/Makefile b/target_firmware/magpie_fw_dev/build/utility/athfw2lnx/Makefile new file mode 100644 index 0000000..f13c296 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/athfw2lnx/Makefile @@ -0,0 +1,11 @@ +all: athfw2lnx + +ifeq ($(ATH_FW),) +$(error "ERROR: usage: make ATH_FW=fw.c") +endif + +athfw2lnx: athfw2lnx.c $(ATH_FW) + gcc -o $@ athfw2lnx.c $(ATH_FW) + +clean: + rm -f athfw2lnx diff --git a/target_firmware/magpie_fw_dev/build/utility/athfw2lnx/athfw2lnx.c b/target_firmware/magpie_fw_dev/build/utility/athfw2lnx/athfw2lnx.c new file mode 100644 index 0000000..f1adff8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/athfw2lnx/athfw2lnx.c @@ -0,0 +1,14 @@ +#include +#include +#include + +/* These names may vary but this is typical */ +extern const uint32_t zcFwImage[]; +extern const uint32_t zcFwImageSize; + +int main() +{ + uint32_t i; + for (i = 0; i < zcFwImageSize/4; i++) + write(1, &zcFwImage[i], 4); +} diff --git a/target_firmware/magpie_fw_dev/build/utility/bin/adj_dep b/target_firmware/magpie_fw_dev/build/utility/bin/adj_dep new file mode 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+############################################################### +use strict; + +my ($format, $binfile, $outfile, $arr_form, $ColNum, $show_hex, $filesize); +$format = $ARGV[0] || usage(); +$binfile = $ARGV[1] || usage(); +$outfile = $ARGV[2] || $binfile.".$format"; +$arr_form = $ARGV[3]; +$ColNum = $ARGV[4] || usage(); +$show_hex = $ARGV[5]; + +my ($orig, @converted); + + $orig = readdata ($binfile); + + $orig = hexdump($orig); + if ($show_hex) {print "Original Binary text:\n\t $orig","\n\n";} + + if ($format eq 'a' || $format eq 'asm') { + @converted = convert_to_asm ($orig); + + } elsif ($format eq 'c') { + @converted = convert_to_c ($orig); + + } else { + print "Unknown format to convert!\n"; + exit (-1); + } + if ($show_hex) {print "Converted hex text:\n",join ('', @converted), "\n";} + + writedata ($outfile, @converted); + +sub convert_to_asm { + my @data = split(' ', join (' ', @_)); #nop here only one list passed to join + + my $i = 0; + if ($arr_form){ + foreach (@data) { + if ($i++ < 8) { + $_=$_."h, 0"; + } else { + $_=$_."h\nbyte 0"; + $i = 0; + } + } + + unshift (@data, "byte 0"); + $data[-1] =~s/[,|\nbyte] 0$//g; + }else{ + foreach (@data){ + if ($i++ < $ColNum-1) { + #$_.=","; + }else { + $_.="\n"; + $i = 0; + } + } + } + return @data; +} + +sub convert_to_c { + my @data = split(' ', join (' ', @_)); #nop here only one list passed to join + + my $i = 0; + if ($arr_form){ + foreach (@data) { + if ($i++ < $ColNum-1) { + $_.=", 0x"; + } else { + $_.=",\n\t0x"; + $i = 0; + } + } + unshift (@data, "unsigned char data[$filesize] = {\n\t0x"); #add some pattern at the front of @data + $data[-1] =~s/0x$//g; + $data[-1] =~s/[ |\n\t]//g; + $data[-1] =~s/\,//g; + push (@data, "\n};"); + }else{ + foreach (@data){ + if ($i++ < $ColNum-1) { + }else { + $_.="\n"; + $i = 0; + } + } + } + return @data; +} + +sub readdata { + my ($line); + my ($file) = @_; + #printf "dbg:file = $file\n"; + open (BF, "$file") || die "Cannot open $file: $!"; #$! contains current value of errno + binmode (BF); + $filesize = (stat($file))[7]; + my ($DATA) = ""; #; + my (@Data_check) = ; + foreach $line (@Data_check){ + #printf "dbg:line = $line\n"; + $DATA.=$line; + } + #printf "dbg:DATA string = $DATA\n"; + close (BF); + return ($DATA); +} + +sub writedata { + my ($file, @FomatData) = @_; + open (AF, ">$file") || die "Cannot open $file: $!"; + my $i = 0; + my $b0 = 0; + my $b1 = 0; + my $b2 = 0; + my $b3 = 0; + foreach (@FomatData) { + if($ColNum eq '1') { + if($i == 0) { + $b0 = $_; + $i++; + } else { + if($i == 1) { + $b1 = $_; + $i++; + } else { + if($i == 2) { + $b2 = $_; + $i++; + } else { + print AF "$_"; + print AF "$b2"; + print AF "$b1"; + print AF "$b0"; + $i = 0; + }}} + }else{ + print AF "$_"; + } + } + close (AF); +} + +sub hexdump +{ + join ' ', map { sprintf "%02X", $_ } unpack "C*", $_[0]; +} + +sub usage { + print STDERR < 'assembly', + c ==> 'C' + binfile binary file you want to convert. + outfile output file to store the result of output. + arr_form displayed in array-form + ColNum num of columns of the shown array + +EOF + exit(-1); +} + diff --git a/target_firmware/magpie_fw_dev/build/utility/bin2hex/Makefile b/target_firmware/magpie_fw_dev/build/utility/bin2hex/Makefile new file mode 100755 index 0000000..4dacafd --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/bin2hex/Makefile @@ -0,0 +1,12 @@ +TARGET = ../bin/bin2hex # for Linux environment + +E=echo + +all: $(TARGET) + +$(TARGET): + gcc -o $(TARGET) bin2hex.c + @$(E) " CC " $@ + +clean: + -rm $(TARGET) diff --git a/target_firmware/magpie_fw_dev/build/utility/bin2hex/bin2hex b/target_firmware/magpie_fw_dev/build/utility/bin2hex/bin2hex new file mode 100755 index 0000000000000000000000000000000000000000..9f1267a08b85da9076e78d3acf1321c4c22afbed GIT binary patch literal 6956 zcmcIp4QyN06~0Ma2qiRWT1sKr@Jh0!V>LvyTq#2VGQ97*KgmmI zV3W4no}ByLbM86k-gnP^_gx>h8aEXb6bMraMUfyXd)QOF8hmt-lB^b9aiyph72=J?beYEdeG`M%yG=&{u$7yIKem`-?Iqmu=sL3{-&* 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zY&s*%YMGyZ3L>scu50<-3c$5%3S}%efpD^ydh+`c0xz&B9$l#ge-~?<_LyH=w4RZZ zlWqes$Ee4=3q!9Tb><_gQiu810AlV@k9k^+3iHzx>ayGkVvbRd`SmO+%TYIe*-qLA zVotKoyzED%26eYzK+z7uXO8T{yv{+7$z<%26L*4)9`}Js=y89boZ~Zkhfrs%+-JBC zZNZ?pcbH=A^3fT+1JFAFy;DXBoO-0gAfv}Si!wBRo5po1)4T`V=yBhB4jWvBQ35x9 zGg^=HG6=mv=v~E*x){ADfZ0sF5xmPsFi0b#s;Peub?Wii@%6@gjp@zHrT2_W?@j2v zIgj3tU3&Z=x-gGl&K0MDe&sz0^oCLA^JQUtjN=y|6W=N9>!%_lw>2d!* z4ZYP=(1kjrA&{|`gs7u4T8q8YIz_tD~_8wT~3;A8b@NY3d$IVP$~(fx^lI z^Il&dAt$KCxx*nP?$FgV{%cL z9}3H3ip&Fr)ny>pyTYYpa$PH|vW@FkVLlbykxXNr3e-`FjBPxC_tq-wpZeF8_}K%X0}h{eKJG%x{4x6+ZxW z$MZb!5&e8PKIWS#9N((|W_+UXQvM%v@FXzvmwgHfuN8~1klp$#=HNAR@TNIkkmC z^-}(XmY>w}p8-$0!brmcE2`A~K+S+^p+~qbj?bvNMZr#&_8)DnuI16oSm=@u5))@^sp`dTg zm)F#bPBL61+rhZq9*wv9qqaQl+5S`)u8VOBw1cURjzh+QwSD7^eFHY_UVoQm8$@TO zK4VoLC8bsU)h2`POoVt2wdDtzx`~D-9!GUkC>9j<=EfZx);HQaHf`EtHQ7z;H#Axt z +#include + +#define MAX_READ_SIZE 80 + +unsigned long checksum = 0; + +void write_file(FILE *out, unsigned char *buf, unsigned long size, unsigned char *endian, unsigned char nl) +{ + int i=0; + unsigned char tmp_buf[4]; + + for(i=0; i\n"); + fprintf(out, "const uint32_t zcFwImage[] = {\n"); + while(1) + { + size = fread(buffer, sizeof(unsigned char), sizeof(buffer), in); + file_size += size; + if( size == 0 ) + { + if (multiple) + { + fprintf(out, "0x%08X\n", checksum); + file_size += 4; + } + + fprintf(out, "};\n"); + fprintf(out, "\nconst unsigned long zcFwImageSize=%ld;\n", file_size); + + goto ERR_DONE; + } + else if (size +#include + +#define MAX_READ_SIZE 80 + +unsigned long checksum = 0; + +void write_file(FILE *out, unsigned char *buf, unsigned long size, unsigned char *endian, unsigned char nl) +{ + int i=0; + unsigned char tmp_buf[4]; + + for(i=0; i=size) + { + if(i%4==3) + { + tmp_buf[3] = 0x0; // padding + printf("3: i:%d size:%d\n\r", i, size); + } + else if (i%4==2) + { + tmp_buf[2] = 0x0; // padding + tmp_buf[3] = 0x0; // padding + printf("2: i:%d size:%d\n\r", i, size); + } + else if (i%4==1) + { + tmp_buf[1] = 0x0; // padding + tmp_buf[2] = 0x0; // padding + tmp_buf[3] = 0x0; // padding + printf("1: i:%d size:%d\n\r", i, size); + } + } +#endif + fprintf(out, "0x%08X, ", *((unsigned long *)(&tmp_buf[0]))); + } + else + { + + if(i%16 == 0){ + fprintf(out, "\n"); + } + + tmp_buf[0] = buf[i+3]; + tmp_buf[1] = buf[i+2]; + tmp_buf[2] = buf[i+1]; + tmp_buf[3] = buf[i+0]; +#if 0 + if( i+4>=size) + { + if(i%4==3) + { + tmp_buf[0] = 0x0; // padding + } + else if (i%4==2) + { + tmp_buf[0] = 0x0; // padding + tmp_buf[1] = 0x0; // padding + } + else if (i%4==1) + { + tmp_buf[0] = 0x0; // padding + tmp_buf[1] = 0x0; // padding + tmp_buf[2] = 0x0; // padding + } + } + else + { + + } +#endif + fprintf(out, "0x%08X, ", *((unsigned long *)(&tmp_buf[0]))); + } + checksum = checksum ^ *((unsigned long *)(&tmp_buf[0])); + } +} + +void write_rom(FILE *out, FILE *in) +{ + int size; + long file_size; + unsigned char buffer[MAX_READ_SIZE]; + int multiple = 0; + + file_size = size = 0; + + while(1) + { + size = fread(buffer, sizeof(unsigned char), sizeof(buffer), in); + file_size += size; + + //write_file(out, buffer, size, NULL, 0); + if( size == 0 ) + { + if (multiple) + fprintf(out, "%08X\n", checksum); + + goto ERR_DONE; + } + else if (size +#include + + +#define MAX_READ_SIZE 80 + +static void crc16ccitt_init(unsigned short *uCcitt16) +{ + *uCcitt16 = 0xFFFF; +} + +static void crc16ccitt_update(unsigned short *uCcitt16, unsigned char *pBuffer, unsigned long uBufSize) +{ + unsigned long i = 0; + unsigned long j = 0; + + for(i = 0; i < uBufSize; i++) + { + for(j=0; j<3; j++) + { + *uCcitt16 = (*uCcitt16 >> 8) | (*uCcitt16 << 8); + *uCcitt16 ^= pBuffer[3-j]; + *uCcitt16 ^= (*uCcitt16 & 0xFF) >> 4; + *uCcitt16 ^= (*uCcitt16 << 8) << 4; + *uCcitt16 ^= ((*uCcitt16 & 0xFF) << 4) << 1; + } + } +} + +static void crc16ccitt_final(unsigned short *uCcitt16) +{ + *uCcitt16 = ~(*uCcitt16); +} + +void write_file(unsigned short crc, unsigned short file_size, FILE *out, FILE *in) +{ + unsigned char buffer[MAX_READ_SIZE]; + unsigned short size; + + //set file pointer to start of the file + if( feof(in) ) + fseek(in,0,SEEK_SET); + + while(1) + { + size = fread(buffer, sizeof(unsigned char), sizeof(buffer), in); + + if (size output crc 0x%04x with file size 0x%04x\n\r", crc, file_size); + + return crc; +} + + +int main(int argc, char* argv[]) +{ + FILE *in, *out; + int retVal; + int i=0; + unsigned short crc = 0; + unsigned short size = 0; + char input_file_name[80]; + char output_file_name[80]; + + in = out = 0x0; + + if( argc < 3 ) + { + printf("\"imghdr [input_file] [output_file] - calculate the image and prefix to the binary \"!\n\r"); + goto ERR_DONE; + } + strcpy(input_file_name, argv[1]); + strcpy(output_file_name, argv[2]); + + printf("imghdr %s %s!\n\r", input_file_name, output_file_name); + + if((in = fopen(input_file_name,"rb")) == NULL) + goto ERR_DONE; + + if((out = fopen(output_file_name,"wt")) == NULL) + goto ERR_DONE; + + crc = cal_crc(in); + + fseek( in, 0, SEEK_END ); + size = ftell(in); // get file length + fseek( in, 0, SEEK_SET ); + + printf(" ==> (2) output crc 0x%04x with file size 0x%04x\n\r", crc, size); + write_file(crc, size, out, in); + + +ERR_DONE: + + if(in) fclose(in); + if(out) fclose(out); + + return 0; + +} diff --git a/target_firmware/magpie_fw_dev/build/utility/patch_gen/Makefile b/target_firmware/magpie_fw_dev/build/utility/patch_gen/Makefile new file mode 100755 index 0000000..ed2fda8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/patch_gen/Makefile @@ -0,0 +1,13 @@ +TARGET = ../bin/patch_gen # for Linux environment +#TARGET = ../bin/_gen.exe # for CygWin environment + +INC = $(HOME)/project/src/inc + +all: $(TARGET) + +$(TARGET): + gcc -o $(TARGET) -I$(INC) main.c patch.c + + +clean: + -rm $(TARGET) diff --git a/target_firmware/magpie_fw_dev/build/utility/patch_gen/dt_defs.h b/target_firmware/magpie_fw_dev/build/utility/patch_gen/dt_defs.h new file mode 100755 index 0000000..1cffc7f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/patch_gen/dt_defs.h @@ -0,0 +1,47 @@ +/*************************************************************************/ +/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : dt_defs.h */ +/* */ +/* Abstract */ +/* This file contains the common data structure definition. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _DT_DEFS_H +#define _DT_DEFS_H + +#if 0 +#define LOCAL static +#else +#define LOCAL +#endif + +/* data type definition */ +typedef unsigned long uint32_t; +typedef unsigned short uint16_t; +typedef unsigned char uint8_t; + +typedef signed long int32_t; +typedef signed short int16_t; +typedef signed char int8_t; + +typedef uint16_t BOOLEAN; + +#define ptrData uint8_t * + +/* marco definition */ +#define SIZE_HASH_BUFFER 128 + +#define TRUE (0==0) +#define FALSE (0!=0) + + +#ifndef NULL +#define NULL 0x0 +#endif + +#endif diff --git a/target_firmware/magpie_fw_dev/build/utility/patch_gen/main.c b/target_firmware/magpie_fw_dev/build/utility/patch_gen/main.c new file mode 100755 index 0000000..4e2ee9b --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/patch_gen/main.c @@ -0,0 +1,102 @@ +#include +#include +#include +#include "dt_defs.h" +#include "patch.h" + +#define SIZE_HASH_BUFFER 4096 + +#define ROM_SIZE 32 + +uint8_t pBuf[SIZE_HASH_BUFFER]; + +//unsigned short m_crc16ccitt; + +void print_help() +{ + printf("\n\rThis utility is used to prefix a header to the patch code!\n\r"); + printf("For loading into the bootcode and the integrity crc header!\n\r"); + printf(" - patch_hdr [patch binary] [load address]\n\r"); + printf("\n\r e.g. patch_hdr patch.bin 0x8e0000\n\r"); +} + + +#define _ROMP_SIZE_ 64 + +int main(int argc, char* argv[] ) +{ + FILE *out; + FILE *in; + + struct rom_patch_st patch_item; + uint8_t *pBufPtr = NULL; + uint32_t ran_patch_size = 0; + uint8_t *ld_addr; + uint8_t *fun_addr; + uint8_t name_of_patch[32]; + + // init the patch + _patch_init(&patch_item); + + if(argc==2) + { + _patch_oepn(pBuf, argv[1]); + _patch_dump(pBuf); + + goto ERROR; + } + else if (argc<3) + goto ERROR; + else + printf("%s %s %s\n\r", argv[0], argv[1], argv[2]); + + + + /***************************************************************/ + // allocate the buffer space for func address + if( !(patch_item.fun = (uint8_t *)malloc(SIZE_HASH_BUFFER)) ) + goto ERROR; + + // check the function address of the patch code + ld_addr = argv[2]; + if( db_ascii_to_hex((ld_addr+2), &(patch_item.ld_addr))!=0 ) + goto ERROR; + + // check the function address of the patch code + fun_addr = argv[3]; + if( db_ascii_to_hex((fun_addr+2), &(patch_item.fun_addr))!=0 ) + goto ERROR; + + /***************************************************************/ + + if( gen_patch_item(&patch_item, argv[1])!=TRUE ) + goto ERROR; + + printf(" - prefix to the patch binary -\n\r"); + _patch_dump(&patch_item); + + sprintf(name_of_patch, "h_%s", argv[1]); + + printf("%s is to be outputed\n\r", name_of_patch); + + _patch_append(pBuf, &patch_item); + + out = fopen(name_of_patch, "wb"); + + // ( struct size -4 ) + patch_code size + 4-%4( make it alignment ) + printf(" write %d bytes to h_%s as an output file", (sizeof(struct rom_patch_st)-4)+patch_item.len+(4-(patch_item.len%4)), argv[1]); + fwrite((uint8_t *)pBuf, sizeof(uint8_t), (sizeof(struct rom_patch_st)-4)+patch_item.len+(4-(patch_item.len%4)), out); + + fclose(out); + + goto DONE; + +ERROR: + print_help(); + +DONE: + if( patch_item.fun ) + free(patch_item.fun); + + return 0; +} diff --git a/target_firmware/magpie_fw_dev/build/utility/patch_gen/patch.c b/target_firmware/magpie_fw_dev/build/utility/patch_gen/patch.c new file mode 100755 index 0000000..6f8548d --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/patch_gen/patch.c @@ -0,0 +1,164 @@ +#include +#include "dt_defs.h" +#include "patch.h" + +//extern unsigned short m_crc16ccitt; +uint16_t uRead = 0; +uint8_t patchBuf[SIZE_HASH_BUFFER]; + + +int db_ascii_to_hex(char* num_str, unsigned long* hex_num) +{ + int i = 0; + + *hex_num = 0; + while (num_str[i]) + { + if ((num_str[i] >= '0') && (num_str[i] <= '9')) + { + *hex_num <<= 4; + *hex_num += (num_str[i] - '0'); + } + else if ((num_str[i] >= 'A') && (num_str[i] <= 'F')) + { + *hex_num <<= 4; + *hex_num += (num_str[i] - 'A' + 10); + } + else if ((num_str[i] >= 'a') && (num_str[i] <= 'f')) + { + *hex_num <<= 4; + *hex_num += (num_str[i] - 'a' + 10); + } + else + { + return -1; + } + i++; + } + return 0; +} + + +#if 0 +void dump_hex(uint8_t *buf, uint16_t size) +{ + uint16_t i=0; + + + for(i=0; i0) && (i%8==0) ) + printf("- "); + + printf("%02x ", buf[i]); + } +} +#endif + + +BOOLEAN gen_patch_item(struct rom_patch_st *patch, uint8_t *file_name) +{ + BOOLEAN retVal = FALSE; + FILE *in; + uint8_t *ptr; + uint16_t size = 0; + + if((in = fopen(file_name,"rb")) != NULL) + retVal = TRUE; + else + goto ERR_DONE; + + ptr = patchBuf; + while (1) + { + ptr += uRead; + uRead = fread(ptr, 1, SIZE_HASH_BUFFER, in); + + // debug to dump the data we read + //dump_hex(ptr, uRead); + + patch->len += uRead; + + if(uRead != SIZE_HASH_BUFFER) + break; + } + + memcpy(patch->fun, patchBuf, patch->len); + patch->crc16 = patch->len; // bugs? workaround? + + printf("\n\n"); + + fclose(in); +ERR_DONE: + + return retVal; +} + +BOOLEAN _patch_init(struct rom_patch_st *patch) +{ + // init the pact_pack + //memset((uint8_t *)patch_patck, 0x0, sizeof(struct rom_patch_pack_st)); + patch->crc16 = 0; + patch->len = 0; + patch->ld_addr = 0; + patch->fun_addr = 0; + patch->fun = NULL; + + return TRUE; +} + +void _patch_dump(struct rom_patch_st *patch) +{ + printf(" -----------------------------\n\r"); + printf(" patch code crc: 0x%04x\n\r", patch->crc16); + printf(" patch code size: %d\n\r", patch->len); + printf(" patch ld_addr: 0x%08x\n\r", patch->ld_addr); + printf(" patch fun_addr: 0x%08x\n\r", patch->fun_addr); + printf(" -----------------------------\n\r"); +} + + +BOOLEAN _patch_oepn(uint8_t *buf, uint8_t *mFile) +{ + FILE *in; + BOOLEAN retVal = FALSE; + uint16_t offset = 0; + + if((in = fopen(mFile,"rb")) != NULL) + { + printf("%s is opened successful!\n\r", mFile); + retVal = TRUE; + } + else + goto ERROR; + + while (1) + { + uRead = fread(buf+offset, 1, SIZE_HASH_BUFFER, in); + + // debug to dump the data we read + //dump_hex(buf+offset, uRead); + + offset += uRead; + if(uRead != SIZE_HASH_BUFFER) break; + + } +ERROR: + if(in) + close(in); + + return retVal; +} + +uint32_t _patch_append(uint8_t *buf, struct rom_patch_st *patch) +{ + + memcpy(buf, (uint8_t *)patch, (sizeof(struct rom_patch_st)-4)); + memcpy(buf+(sizeof(struct rom_patch_st)-4), patch->fun, patch->len); + + return 0; +} + + diff --git a/target_firmware/magpie_fw_dev/build/utility/patch_gen/patch.h b/target_firmware/magpie_fw_dev/build/utility/patch_gen/patch.h new file mode 100755 index 0000000..b7e380f --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/patch_gen/patch.h @@ -0,0 +1,16 @@ +#include "dt_defs.h" + +#define MAX_NUM_OF_PATCH 16 + +struct rom_patch_st { +#if 0 + uint16_t len; + uint16_t crc16; +#else + uint16_t crc16; + uint16_t len; +#endif + uint32_t ld_addr; + uint32_t fun_addr; // entry address of the patch code + uint8_t *fun; +}; diff --git a/target_firmware/magpie_fw_dev/build/utility/sh/make_fw.sh b/target_firmware/magpie_fw_dev/build/utility/sh/make_fw.sh new file mode 100755 index 0000000..e3b1829 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/sh/make_fw.sh @@ -0,0 +1,58 @@ +#!/bin/sh +# Copyright (c) 2008 Atheros Communications Inc. +# All rights reserved. +# $ATH_LICENSE_TARGET_MK$ + +# This script constructs an AR6002 ROM firmware binary image +# for FPGA(if FPGA_FLAG is "1") or for actual silicon if FPGA_FLAG +# is not "1". +# +# It takes two things as input: +# sw.rom.out, which is an ELF image of ROM software +# that was built for actual hardware or for FPGA +# data.rom.hw.bin OR data.rom.fpga.bin, which contains +# DataSets and other data that is to be included +# at the end of the firmware image +# +# It produces fw.rom.bin, a firmware image appropriate for +# use with AR6002 ROM. +# +# The image is constructed by converting the sw.rom.out ELF +# image to binary, padding at the end of that binary, +# and appending the data binary from data.rom.*.bin. So the +# final fw.rom.bin image is a binary image that's exactly +# the same size as the ROM hardware and which contains ROM +# software (including literals, read-only data, data that +# will be copied to RAM in order to initialize read/write data), +# DataSet Metadata, and DataSets. + + +sw_image=${sw_image:-$PRJ_ROOT/build/image/magpie/rom.out} +sw_bin=${sw_bin:-$PRJ_ROOT/build/image/magpie/rom.bin} + + +ds_in_rom="0x`xt-nm $sw_image | grep " _data_start_in_rom" | cut -b -8`" + +# Place data binary at the end of ROM. +#data_start=$((9168*1024-`stat --format='%s' $data_bin`)) + +xt-objcopy \ + --change-section-lma .lit4+0x400000 \ + --change-section-vma .lit4+0x400000 \ + --change-section-lma .rodata+0x400000 \ + --change-section-vma .rodata+0x400000 \ + --change-section-lma .dram0.literal+0x400000 \ + --change-section-vma .dram0.literal+0x400000 \ + --remove-section .dport0.data \ + --change-section-lma .data=$((ds_in_rom)) \ + --change-section-vma .data=$((ds_in_rom)) \ + -O binary $sw_image $sw_bin + +#cat $sw_bin $data_bin > $fw_bin + +#if [ `stat --format='%s' $fw_bin` -ne $((96*1024)) ] +#then +# echo "$0 ERROR: firmware $fw_bin is NOT the expected size." +#fi + +exit 0 diff --git a/target_firmware/magpie_fw_dev/build/utility/sh/make_ld.sh b/target_firmware/magpie_fw_dev/build/utility/sh/make_ld.sh new file mode 100755 index 0000000..69ba805 --- /dev/null +++ b/target_firmware/magpie_fw_dev/build/utility/sh/make_ld.sh @@ -0,0 +1,66 @@ +#!/bin/sh + +# This script is intended for use with separately linked ROM and RAM. +# It creates EITHER a linker script that satisfies references made by RAM +# applications to ROM symbols OR a linker script that forces symbols to +# be included in a ROM image. +# +# The option "--addrs" causes the RAM linkage script to be generated +# and the option "--externs" causes the ROM linkage script to be generated. +# +# Example usage: +# make_ld.sh --addrs athos.rom.out athos.rom.symbols > rom.addrs.ld +# make_ld.sh --externs athos.rom.symbols > rom.externs.ld + +eval XTNM=xt-nm + +Usage() { + echo Usage: + echo $progname '{--addrs ROM_ELF_Image | --externs} symbol_file' +} + +Provide() { + addr0=`echo $1 | sed 's/ $//'` + addr=0x`nm $image_file | grep -w $addr0 | cut -d ' ' -f 1` + if [ "$addr" != "0x" ] + then + echo PROVIDE \( $addr0 = $addr \)\; + fi +} + +Extern() { + echo EXTERN \( $1 \)\; +} + +progname=$0 +script_choice=$1 + +if [ "$script_choice"=="--addrs" ] +then + action=Provide + image_file=$2 + + if [ ! -r "$image_file" ] + then + echo "Cannot read ELF image: $image_file" + Usage + fi + symbol_file=$3 +elif [ "$script_choice"=="--externs" ] +then + action=Extern + symbol_file=$2 + + if [ ! -r "$symbol_file" ] + then + echo "Cannot read symbol list from: $symbol_file" + Usage + fi +else + Usage +fi + +for i in `cat $symbol_file` +do + $action $i +done diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_nbuf.c b/target_firmware/magpie_fw_dev/target/adf/adf_nbuf.c new file mode 100755 index 0000000..69b00c4 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_nbuf.c @@ -0,0 +1,692 @@ +/** + * (c) Copyright Atheros Communications Inc.,2002-2008 + * All rights reserved + * + * This file contains buffer Abstraction routines for FreeBSD + * the abstracted buffer called adf_nbuf is opaque to the + * user,hence these routines should be called to manipulate + * anything inside it. + * + */ +#include +#include +#include "cmnos_api.h" +#include +#include + +// ############################################################################# +VDESC * __adf_nbuf_last(VBUF *buf); + + +// ############################################################################# + +/** + * + * @brief allocate a new nbuf, + * + * @param hdl (adf_net handle) + * @param size (size of the new buf) + * @param reserve (amount of space to reserve in the head) + * + * @return newly allocated nbuf + */ +__adf_nbuf_t +__adf_nbuf_alloc(adf_os_size_t size, a_uint32_t reserve, + a_uint32_t align) +{ + VBUF *buf = NULL; + VDESC *desc; + + buf = VBUF_alloc_vbuf(); + if ( buf != NULL ) { + desc = VDESC_alloc_vdesc(); + desc->buf_addr = (A_UINT8 *)A_ALLOCRAM(size); + desc->buf_size = size; + desc->next_desc = NULL; + desc->data_offset = reserve; + desc->data_size = 0; + desc->control = 0; + + buf->desc_list = desc; + buf->buf_length = 0; + } + + return buf; +} + +/** + * @brief Free the nbuf + * function to be called in + * @param hdl + * @param adf_nbuf + * + */ +void __adf_nbuf_free(__adf_nbuf_t buf) +{ + adf_os_assert(0); +} + +/** + * @brief reallocate the head space, call it only after the you + * have called headroom + * + * @param adf_nbuf + * @param headroom + * + * @return new nbuf + */ +__adf_nbuf_t +__adf_nbuf_realloc_headroom(__adf_nbuf_t buf, a_uint32_t headroom) +{ + adf_os_assert(0); + return NULL; +} + +/** + * @brief expand the tailroom, mostly by adding the new tail + * buffer, also take care of the priv + * + * @param buf + * @param tailroom + * + * @return struct mbuf * (buffer with the new tailroom) + */ +__adf_nbuf_t +__adf_nbuf_realloc_tailroom(__adf_nbuf_t buf, a_uint32_t tailroom) +{ + adf_os_assert(0); + return NULL; +} + +/** + * @brief expand the headroom or tailroom or both + * + * @param buf + * @param headroom ( 0 if no headroom expansion req) + * @param tailroom ( 0 if no tailroom expansion req) + * + * @return struct mbuf* (NULL if something goofed up) + */ +__adf_nbuf_t +__adf_nbuf_expand(__adf_nbuf_t buf, a_uint32_t headroom, a_uint32_t tailroom) +{ + adf_os_assert(0); + return NULL; +} + +/** + * @brief put data in the head + * + * @param buf + * @param len (how much data to put) + * + * @return new data pointer ,NULL if the len is more than the + * space available in the head frag. + */ +a_uint8_t * +__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *ptr = NULL; + VDESC *desc = buf->desc_list; + + desc->data_offset -= len; + desc->data_size += len; + buf->buf_length += len; + ptr = desc->buf_addr + desc->data_offset; + return(ptr); +} + +/** + * + * @brief add data in the end of tail + * + * @param buf + * @param len (how much data to put) + * + * @return previous tail (data+len),NULL if the len is more than + * space available + */ +a_uint8_t * +__adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *tail = NULL; + VDESC *last_desc = __adf_nbuf_last(buf); + + tail = last_desc->buf_addr + last_desc->data_offset + last_desc->data_size; + last_desc->data_size += len; + buf->buf_length += len; + + return tail; +} + +/** + * @brief strip data from head + * + * @param adf_nbuf + * @param len (how much data to rip) + * + * @return new data pointer + */ +a_uint8_t * +__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t len) +{ + a_uint8_t *ptr = NULL; + VDESC *desc = buf->desc_list; + + desc->data_offset += len; + desc->data_size -= len; + buf->buf_length -= len; + ptr = desc->buf_addr + desc->data_offset; + + return ptr; +} +/** + * @brief strip data from tail, priv safe + * + * @param buf + * @param len (how much to strip down) + * + */ +void +__adf_nbuf_trim_tail(__adf_nbuf_t buf, adf_os_size_t len) +{ + VDESC *last_desc = __adf_nbuf_last(buf); + + adf_os_assert(buf != NULL); + last_desc->data_size -= len; + buf->buf_length -= len; + + //adf_os_assert(0); //0820 +} +/** + * @brief Copy assumes that we create a writeable copy of the + * nbuf which is equivalent in FreeBSD as duping the + * mbuf. + * + * @param src + * + * @return struct mbuf * (newly allocated buffer) + */ +__adf_nbuf_t +__adf_nbuf_copy(__adf_nbuf_t src) +{ + __adf_nbuf_t buf = NULL; + + adf_os_assert(src != NULL); + + return buf; +} +/** + * @brief make the writable copy of the nbuf + * + * @param adf_nbuf + * + * @return new nbuf + */ +__adf_nbuf_t +__adf_nbuf_unshare(__adf_nbuf_t src) +{ + __adf_nbuf_t buf = NULL; + + adf_os_assert(src != NULL); + + return buf; +} + +/** + * @brief return the frag data & len, where frag no. is + * specified by the index + * + * @param[in] buf + * @param[out] sg (scatter/gather list of all the frags) + * + */ +void +__adf_nbuf_frag_info(__adf_nbuf_t buf, adf_os_sglist_t *sg) +{ + VDESC *desc = buf->desc_list; + int count = 0; + + while( desc != NULL ) { + sg->sg_segs[count].vaddr = desc->buf_addr + desc->data_offset; + sg->sg_segs[count].len = desc->data_size; + + count++; + desc = desc->next_desc; + } + + sg->nsegs = count; +} +/** + * @brief retrieve the priv space pointer from nbuf + * + * @param buf (nbuf to attach the priv space) + * + * @return uint8_t* ( pointer to the data ) + */ +a_uint8_t * +__adf_nbuf_get_priv(__adf_nbuf_t buf) +{ + adf_os_assert(buf != NULL); + + return buf->ctx; +} + +/** + * + * @brief append the nbuf to the queue + * + * @param adf_qhead + * @param adf_nbuf + * + */ +void +__adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead, + __adf_nbuf_t buf) +{ + qhead->qlen++; + + buf->next_buf = NULL; + + if (qhead->head == NULL) { + qhead->head = buf; + } + else { + qhead->tail->next_buf = buf; + } + qhead->tail = buf; +} + +/** + * @brief dequeue an nbuf + * + * @param adf_qhead + * + * @return the nbuf + */ +__adf_nbuf_t +__adf_nbuf_queue_remove(__adf_nbuf_qhead_t *qhead) +{ + __adf_nbuf_t b0 = NULL; + + if (qhead->head) { + qhead->qlen--; + b0 = qhead->head; + if ( qhead->head == qhead->tail ) { + qhead->head = NULL; + qhead->tail = NULL; + } else { + qhead->head = qhead->head->next_buf; + } + + b0->next_buf = NULL; + } + return b0; +} + +/** + * ****************DMA Routines Start Here***************** + */ + + +/** + * @brief creates a streaming mapping (takes a pre allocated + * global tag for 4K mbuf sizes) + * + * @param hdl + * @param max_sz + * @param dmap + * + * @return a_status_t + */ +a_status_t +__adf_nbuf_dmamap_create(__adf_os_device_t osdev, __adf_os_dma_map_t *dmap) +{ + a_status_t retval = A_STATUS_OK; + + (*dmap) = A_ALLOCRAM(sizeof(struct __adf_dma_map)); + if(*dmap == NULL) + return A_STATUS_ENOMEM; + + (*dmap)->buf = NULL; + return retval; +} + + +a_status_t +__adf_nbuf_map(__adf_os_device_t osdev, __adf_os_dma_map_t bmap, + __adf_nbuf_t buf, adf_os_dma_dir_t dir) +{ + bmap->buf = buf; + + return A_STATUS_OK; +} + +void +__adf_nbuf_unmap(__adf_os_device_t osdev, __adf_os_dma_map_t bmap, + adf_os_dma_dir_t dir) +{ + bmap->buf = NULL; + + return; +} + +void +__adf_nbuf_dmamap_destroy(__adf_os_device_t osdev, + __adf_os_dma_map_t dmap) +{ + //dmap->buf = NULL; + + // Should not be called in FW! + //return A_STATUS_OK; +} + + + +/** + * @brief return the dma map info + * + * @param[in] bmap + * @param[out] sg (map_info ptr) + */ +void +__adf_nbuf_dmamap_info(__adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg) +{ + VDESC *desc = bmap->buf->desc_list; + int count = 0; + + while( desc != NULL ) { + sg->dma_segs[count].paddr = (adf_os_dma_addr_t)(desc->buf_addr + desc->data_offset); + sg->dma_segs[count].len = desc->data_size; + + count++; + desc = desc->next_desc; + } + + sg->nsegs = count; +} + +/** + * **************************Misc routines*************** + */ + + +/** + * @brief sets the cksum type & value for nbuf + * XXX: not fully implemented + * + * @param buf + * @param cksum + */ +void +__adf_nbuf_set_rx_cksum(__adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum) +{ + +} + +a_status_t +__adf_nbuf_get_vlan_info(adf_net_handle_t hdl, __adf_nbuf_t buf, + adf_net_vlanhdr_t *vlan) +{ + return A_STATUS_OK; +} + +__adf_nbuf_t +__adf_nbuf_create_frm_frag(__adf_nbuf_queue_t *qhead) +{ + VBUF *buf_tmp, *buf_head = NULL; + VDESC *vdesc_prev = NULL, *vdesc_tmp = NULL; + a_uint32_t cnt = 0, len = __adf_nbuf_queue_len(qhead); + a_uint16_t total_len = 0; + + buf_head = VBUF_alloc_vbuf(); + buf_tmp = __adf_nbuf_queue_first(qhead); + + __adf_os_assert(buf_head); + __adf_os_assert(buf_tmp); + + buf_head->desc_list = buf_tmp->desc_list; + + while ((buf_tmp = __adf_nbuf_queue_remove(qhead)) != NULL) { + cnt++; + + //adf_os_print("merge buf: %x\n", buf_tmp->desc_list->buf_addr + buf_tmp->desc_list->data_offset); + + total_len += buf_tmp->buf_length; + + if (vdesc_prev) { + /* link "the last VDESC of previous VBUF" to "the 1st VDESC of this VBUF" */ + vdesc_prev->next_desc = buf_tmp->desc_list; + } + + /* traverse VDESC list in this VBUF to find out the last VDESC */ + vdesc_tmp = buf_tmp->desc_list; + while (vdesc_tmp->next_desc) { + vdesc_tmp = vdesc_tmp->next_desc; + } + vdesc_prev = vdesc_tmp; + + /* return VBUF to the pool */ + buf_tmp->desc_list = NULL; + buf_tmp->buf_length = 0; + VBUF_free_vbuf(buf_tmp); + } + + if (cnt != len) { + //adf_os_print("cnt: %x, len: %x, __adf_nbuf_queue_len: %x\n", cnt, len, + // __adf_nbuf_queue_len(qhead)); + adf_os_assert(0); + } + //__adf_os_assert(cnt == len); + + buf_head->buf_length = total_len; + + return buf_head; +} + +void +__adf_nbuf_split_to_frag(__adf_nbuf_t buf, __adf_nbuf_qhead_t *qhead) +{ + VBUF *buf_tmp; + VDESC *desc_tmp = NULL; + + __adf_nbuf_queue_init(qhead); + desc_tmp = buf->desc_list; + + while (desc_tmp /*&& desc_tmp->buf_addr*/) { + buf_tmp = VBUF_alloc_vbuf(); + + __adf_os_assert(buf_tmp); + + //desc_tmp->data_size = 0; + buf_tmp->desc_list = desc_tmp; + //buf_tmp->buf_length = desc_tmp->buf_size; + buf_tmp->buf_length = desc_tmp->data_size; + buf_tmp->next_buf = NULL; + + //adf_os_print("split - buf: %x\n", buf_tmp->desc_list->buf_addr + buf_tmp->desc_list->data_offset); + + __adf_nbuf_queue_add(qhead, buf_tmp); + + desc_tmp = desc_tmp->next_desc; + + buf_tmp->desc_list->next_desc = NULL; + } + + buf->desc_list = NULL; + buf->buf_length = 0; + VBUF_free_vbuf(buf); + +} + +/** + * @brief return the last mbuf + * + * @param m0 + * + * @return struct mbuf* + */ +VDESC * +__adf_nbuf_last(VBUF *buf) +{ + VDESC *desc = buf->desc_list; + + //for(; desc->next_desc != NULL; desc = desc->next_desc) + // ; + while(desc->next_desc != NULL) + { + desc = desc->next_desc; + } + + return desc; +} + +/** + * @brief num bytes in the head + * + * @param adf_nbuf + * + * @return num of bytes available + */ +a_uint32_t +__adf_nbuf_headroom(__adf_nbuf_t buf) +{ + return buf->desc_list->data_offset; +} + + +/** + * @brief num of bytes available in the tail excluding the priv + * portion + * + * @param adf_nbuf + * + * @return num of bytes + */ + +a_uint32_t +__adf_nbuf_tailroom(__adf_nbuf_t buf) +{ + VDESC *last_desc = __adf_nbuf_last(buf); + + return last_desc->buf_size - last_desc->data_offset - last_desc->data_size; +} + +/** + * @brief get the entire packet length + * + * @param adf_nbuf + * + * @return total length of packet (sum of all frag lengths) + */ +a_uint32_t +__adf_nbuf_len(__adf_nbuf_t buf) +{ + return buf->buf_length; +} + +/** + * @brief Clone the nbuf (will not create writeable copies) + * + * @param adf_nbuf + * + * @return Read-only copy of the nbuf (including clusters) + */ +__adf_nbuf_t +__adf_nbuf_clone(__adf_nbuf_t src) +{ + __adf_nbuf_t buf = NULL; + + return buf; +} + +void +__adf_nbuf_cat(__adf_nbuf_t dst, __adf_nbuf_t src) +{ + +} + + + +/* + * @brief check if the mbuf is cloned or not + * + * @param buf + * + * @return a_bool_t + */ +a_bool_t +__adf_nbuf_is_cloned(__adf_nbuf_t buf) +{ + return A_FALSE; +} +/** + * @brief This will return the header's addr & m_len + */ +void +__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr, + a_uint32_t *len) +{ + VDESC *desc = buf->desc_list; + + *addr = desc->buf_addr + desc->data_offset; + *len = desc->data_size; +} +/** + * @brief init the queue + * @param qhead + */ +void +__adf_nbuf_queue_init(__adf_nbuf_qhead_t *qhead) +{ + qhead->qlen = 0; + qhead->head = NULL; + qhead->tail = NULL; +} +/** + * @brief return the length of queue + * @param adf_qhead + * + * @return length + * + */ +a_uint32_t +__adf_nbuf_queue_len(__adf_nbuf_qhead_t *qhead) +{ + return qhead->qlen; +} +/** + * @brief returns the first guy in the Q + * @param qhead + * + * @return (NULL if the Q is empty) + */ +__adf_nbuf_t +__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead) +{ + return qhead->head; +} +/** + * @brief return the next packet from packet chain + * + * @param buf (packet) + * + * @return (NULL if no packets are there) + */ +__adf_nbuf_t +__adf_nbuf_queue_next(__adf_nbuf_t buf) +{ + return buf->next_buf; +} +/** + * @brief check if the queue is empty or not + * + * @param qhead + * + * @return a_bool_t + */ +a_bool_t +__adf_nbuf_is_queue_empty(__adf_nbuf_qhead_t *qhead) +{ + return ((qhead->qlen == 0)); +} diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_nbuf_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_nbuf_pvt.h new file mode 100755 index 0000000..a93e2be --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_nbuf_pvt.h @@ -0,0 +1,232 @@ +/* + * (c) Copyright Atheros Communications + * FreeBSD specific prototypes + */ +#ifndef _ADF_NBUF_PVT_H +#define _ADF_NBUF_PVT_H + +#include +//#include +#include +//#include + +#define __ADF_NBUF_NULL NULL +#define __ADF_NBUF_CTX_BUF + +typedef VBUF * __adf_nbuf_t; + +/** + * queue head + */ +typedef struct __adf_nbuf_qhead { + VBUF *head; + VBUF *tail; + a_uint32_t qlen; +}__adf_nbuf_qhead_t; + +typedef __adf_nbuf_qhead_t __adf_nbuf_queue_t; + +__adf_nbuf_t +__adf_nbuf_alloc(adf_os_size_t size, + a_uint32_t reserve, a_uint32_t align); + +void +__adf_nbuf_free(__adf_nbuf_t buf); + +a_uint8_t * +__adf_nbuf_push_head(__adf_nbuf_t buf, adf_os_size_t size); + +a_uint8_t * +__adf_nbuf_pull_head(__adf_nbuf_t buf, adf_os_size_t size); + +a_uint8_t * +__adf_nbuf_put_tail(__adf_nbuf_t buf, adf_os_size_t size); + +void +__adf_nbuf_trim_tail(__adf_nbuf_t buf, adf_os_size_t size); + +__adf_nbuf_t +__adf_nbuf_realloc_headroom(__adf_nbuf_t buf, + a_uint32_t headroom); + +__adf_nbuf_t +__adf_nbuf_realloc_tailroom(__adf_nbuf_t buf, + a_uint32_t tailroom); + +__adf_nbuf_t +__adf_nbuf_expand(__adf_nbuf_t buf, + a_uint32_t headroom, a_uint32_t tailroom); + +__adf_nbuf_t +__adf_nbuf_copy(__adf_nbuf_t src); + +__adf_nbuf_t +__adf_nbuf_unshare(__adf_nbuf_t src); + +void +__adf_nbuf_frag_info(__adf_nbuf_t buf, adf_os_sglist_t *sg); + +a_uint8_t * +__adf_nbuf_get_priv(__adf_nbuf_t buf); +void +__adf_nbuf_queue_add(__adf_nbuf_qhead_t *qhead, + __adf_nbuf_t buf); + +__adf_nbuf_t +__adf_nbuf_queue_remove(__adf_nbuf_qhead_t *qhead); + +a_uint32_t +__adf_nbuf_tx_cksum_info(__adf_nbuf_t buf, + a_uint8_t **hdr_off, + a_uint8_t **where); + +void +__adf_nbuf_set_rx_cksum(__adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum); +void +__adf_nbuf_get_tso_info(__adf_nbuf_t buf, adf_nbuf_tso_t *tso); + +a_status_t +__adf_nbuf_get_vlan_info(adf_net_handle_t hdl, + __adf_nbuf_t buf, + adf_net_vlanhdr_t *vlan); + +void +__adf_nbuf_dmamap_info(__adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg); + +/** + * @brief return the last mbuf + * + * @param m0 + * + * @return struct mbuf* + */ +VDESC * +__adf_nbuf_last(VBUF *buf); + +/** + * @brief num bytes in the head + * + * @param adf_nbuf + * + * @return num of bytes available + */ +a_uint32_t +__adf_nbuf_headroom(__adf_nbuf_t buf); + +/** + * @brief num of bytes available in the tail excluding the priv + * portion + * + * @param adf_nbuf + * + * @return num of bytes + */ + +a_uint32_t +__adf_nbuf_tailroom(__adf_nbuf_t buf); + +/** + * @brief get the entire packet length + * + * @param adf_nbuf + * + * @return total length of packet (sum of all frag lengths) + */ +a_uint32_t +__adf_nbuf_len(__adf_nbuf_t buf); + +/** + * @brief Clone the nbuf (will not create writeable copies) + * + * @param adf_nbuf + * + * @return Read-only copy of the nbuf (including clusters) + */ +__adf_nbuf_t +__adf_nbuf_clone(__adf_nbuf_t src); + +void +__adf_nbuf_cat(__adf_nbuf_t dst, __adf_nbuf_t src); + + +/* + * @brief check if the mbuf is cloned or not + * + * @param buf + * + * @return a_bool_t + */ +a_bool_t +__adf_nbuf_is_cloned(__adf_nbuf_t buf); + +/** + * @brief This will return the header's addr & m_len + */ +void +__adf_nbuf_peek_header(__adf_nbuf_t buf, a_uint8_t **addr, + a_uint32_t *len); + +/** + * @brief init the queue + * @param qhead + */ +void +__adf_nbuf_queue_init(__adf_nbuf_qhead_t *qhead); + +/** + * @brief return the length of queue + * @param adf_qhead + * + * @return length + * + */ +a_uint32_t +__adf_nbuf_queue_len(__adf_nbuf_qhead_t *qhead); + +/** + * @brief returns the first guy in the Q + * @param qhead + * + * @return (NULL if the Q is empty) + */ +__adf_nbuf_t +__adf_nbuf_queue_first(__adf_nbuf_queue_t *qhead); + +/** + * @brief return the next packet from packet chain + * + * @param buf (packet) + * + * @return (NULL if no packets are there) + */ +__adf_nbuf_t +__adf_nbuf_queue_next(__adf_nbuf_t buf); + +/** + * @brief check if the queue is empty or not + * + * @param qhead + * + * @return a_bool_t + */ +a_bool_t +__adf_nbuf_is_queue_empty(__adf_nbuf_qhead_t *qhead); + +__adf_nbuf_t +__adf_nbuf_create_frm_frag(__adf_nbuf_queue_t *head); +void +__adf_nbuf_split_to_frag(__adf_nbuf_t buf, __adf_nbuf_queue_t *qhead); + +a_status_t __adf_nbuf_dmamap_create(__adf_os_device_t osdev, + __adf_os_dma_map_t *dmap); + +void __adf_nbuf_dmamap_destroy(__adf_os_device_t osdev, + __adf_os_dma_map_t dmap); + +a_status_t __adf_nbuf_map(__adf_os_device_t osdev, __adf_os_dma_map_t dmap, + __adf_nbuf_t buf, adf_os_dma_dir_t dir); +void __adf_nbuf_unmap(__adf_os_device_t osdev, __adf_os_dma_map_t dmap, + adf_os_dma_dir_t dir); + +#endif + diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_net.c b/target_firmware/magpie_fw_dev/target/adf/adf_net.c new file mode 100755 index 0000000..f4e2e11 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_net.c @@ -0,0 +1,39 @@ +/** + * Copyright (c) 2002-2008 Atheros Communications, Inc. + * All rights reserved + * + * @module_name ADF_NET + * @module_desc Magpie Network Shim + */ + +#include +//#include +//#include "adf_net_wcmd_pvt.h" +#include + +/** + * Prototypes + */ + +/** + * @brief register the driver into the shim + * @param[in] drv + * + * @return a_status_t + */ +a_status_t +__adf_net_register_drv(adf_drv_info_t *drv) +{ + wlan_pci_register_drv(drv); + return A_STATUS_OK; +} + +/** + * @brief unregister the driver from the shim + * @param[in] name + */ +void +__adf_net_unregister_drv(a_uint8_t *name) +{ + // do nothing... +} diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_net_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_net_pvt.h new file mode 100755 index 0000000..8fd66ca --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_net_pvt.h @@ -0,0 +1,111 @@ +#ifndef __ADF_NET_PVT_H +#define __ADF_NET_PVT_H + + + +#define ADF_NET_MAX_NAME 64 +#define ADF_DEF_TX_TIMEOUT 5 /*Seconds I suppose*/ + +#define __ADF_NET_NULL NULL +#define __ADF_PCI_BAR0 0x10 + + +a_status_t +__adf_net_register_drv(adf_drv_info_t *drv); + +void +__adf_net_unregister_drv(a_uint8_t *name); + +typedef struct __adf_net_mod { +int dummy; +}__adf_net_mod_t; + + + +typedef struct __adf_softc { +int dummy; +}__adf_softc_t; + +static inline a_bool_t +__adf_net_carrier_ok(adf_net_handle_t hdl) +{ + return 1; +} + +static inline void +__adf_net_carrier_off(adf_net_handle_t hdl) +{ + +} + +static inline void +__adf_net_carrier_on(adf_net_handle_t hdl) +{ + +} + +static inline void +__adf_net_start_queue(adf_net_handle_t hdl) +{ + +} + +static inline void +__adf_net_stop_queue(adf_net_handle_t hdl) +{ + +} + +static inline void +__adf_net_wake_queue(adf_net_handle_t hdl) +{ +} + +static inline a_bool_t +__adf_net_queue_stopped(adf_net_handle_t hdl) +{ + return 1; +} + +static inline a_bool_t +__adf_net_is_running(adf_net_handle_t hdl) +{ + return 1; +} +static inline a_bool_t +__adf_net_is_up(adf_net_handle_t hdl) +{ + return 1; +} + +static inline adf_net_handle_t __adf_net_dev_create(adf_drv_handle_t hdl, adf_dev_sw_t *op, + adf_net_dev_info_t *info) +{ + return NULL; +} + +static inline adf_net_handle_t __adf_net_vdev_create(adf_net_handle_t dev_hdl, + adf_drv_handle_t hdl, adf_vdev_sw_t *op, + adf_net_dev_info_t *info) +{ + return NULL; +} + +static inline const a_uint8_t * __adf_net_ifname(adf_net_handle_t hdl) +{ + return NULL; +} + +static inline adf_os_handle_t +__adf_net_dev_to_os(__adf_os_device_t osdev) +{ + return NULL; +} + +static inline adf_os_handle_t +__adf_net_hdl_to_os(adf_net_handle_t hdl) +{ + return NULL; +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_atomic_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_atomic_pvt.h new file mode 100755 index 0000000..61fdb5a --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_atomic_pvt.h @@ -0,0 +1,50 @@ +#ifndef __ADF_OS_ATOMIC_PVT_H +#define __ADF_OS_ATOMIC_PVT_H + +//#include +//#include + +#include + +typedef a_uint32_t __adf_os_atomic_t; + +/** + * @brief This initiallizes the varriable to zero + * + * @param __adf_os_atomic_t (int pointer) + * + */ +static inline void +__adf_os_atomic_init(__adf_os_atomic_t *v) +{ + //atomic_store_rel_int(v,0); +} +static inline a_uint32_t +__adf_os_atomic_read(__adf_os_atomic_t *v) +{ + //return (atomic_load_acq_int(v)); + return *v; +} + +static inline void +__adf_os_atomic_inc(__adf_os_atomic_t *v) +{ + //atomic_add_int(v,1); + (*v)++; +} + +static inline void +__adf_os_atomic_dec(__adf_os_atomic_t *v) +{ + //atomic_subtract_int(v,1); + (*v)--; +} +/* +static inline void +__adf_os_atomic_write(__adf_os_atomic_t *v,a_uint32_t p) +{ + atomic_store_rel_int(v,(int)p); +} + */ + +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_defer_pvt.c b/target_firmware/magpie_fw_dev/target/adf/adf_os_defer_pvt.c new file mode 100755 index 0000000..c4c638b --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_defer_pvt.c @@ -0,0 +1,11 @@ +#include "adf_os_defer_pvt.h" + +void +__adf_os_defer_func(void *arg, int pending) +{ + __adf_os_defer_ctx_t *ctx = (__adf_os_defer_ctx_t *)arg; + + ctx->caller_fn(ctx->caller_arg); +} + + diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_defer_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_defer_pvt.h new file mode 100755 index 0000000..a0d3592 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_defer_pvt.h @@ -0,0 +1,89 @@ +#ifndef __ADF_OS_DEFER_PVT_H +#define __ADF_OS_DEFER_PVT_H + +#include +#include +#include "Magpie_api.h" + +/* + * Because the real function taked an extra int :( + */ +typedef struct { + adf_os_defer_fn_t caller_fn; + void *caller_arg; +}__adf_os_defer_ctx_t; + +/* + * wrapper around the real task func + */ +typedef struct { + //struct task tsk; + __adf_os_defer_ctx_t ctx; +}__adf_os_defer_t; + +//typedef __adf_os_defer_t __adf_os_bh_t; +typedef A_tasklet_t __adf_os_bh_t; +typedef __adf_os_defer_t __adf_os_work_t; + +/* + * wrapper function + */ +extern void __adf_os_defer_func(void *arg, int pending); + +/** + * @brief initiallize the defer function (work or bh) + * + * @param defer + * @param func + * @param arg + */ +static inline void __adf_os_init_defer(__adf_os_defer_t *defer, + adf_os_defer_fn_t func, + void *arg) +{ + defer->ctx.caller_fn = func; + defer->ctx.caller_arg = arg; + + //TASK_INIT(&defer->tsk, 0, __adf_os_defer_func, &defer->ctx); +} + +static inline void __adf_os_init_work(adf_os_handle_t hdl, + __adf_os_work_t *work, + adf_os_defer_fn_t func, + void *arg) +{ + __adf_os_init_defer(work, func, arg); +} + +static inline void __adf_os_init_bh(adf_os_handle_t hdl, + __adf_os_bh_t *bh, + adf_os_defer_fn_t func, + void *arg) +{ + //__adf_os_init_defer(bh, func, arg); + A_TASKLET_INIT_TASK(func, arg, bh); +} +static inline void __adf_os_sched_work(adf_os_handle_t hdl, + __adf_os_work_t * work) +{ + //taskqueue_enqueue(taskqueue_thread, &work->tsk); +} +static inline void __adf_os_disable_work(adf_os_handle_t hdl, + __adf_os_work_t * work) +{ + //taskqueue_drain(taskqueue_thread, &work->tsk); +} + +static inline void __adf_os_sched_bh(adf_os_handle_t hdl, + __adf_os_bh_t * bh) +{ + A_TASKLET_SCHEDULE(bh); +} + +static inline void __adf_os_disable_bh(adf_os_handle_t hdl, + __adf_os_bh_t * bh) +{ + A_TASKLET_DISABLE(bh); +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_dma.c b/target_firmware/magpie_fw_dev/target/adf/adf_os_dma.c new file mode 100755 index 0000000..7bae273 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_dma.c @@ -0,0 +1,47 @@ +#include +#include "Magpie_api.h" +#include "cmnos_api.h" + +#if 0 +void __adf_os_dma_load(void *arg, bus_dma_segment_t *dseg, int nseg, int error) +{ + if (error) + return; + + adf_os_assert(nseg == 1); + + ((bus_dma_segment_t *)arg)[0].ds_addr = dseg[0].ds_addr; + ((bus_dma_segment_t *)arg)[0].ds_len = dseg[0].ds_len; +} +#endif + +/** + * @brief Allocates a DMA region, uses the tag elem to store the + * tag value which constant for all the mappings done + * through this API. + * + * @param osdev + * @param size + * @param coherent + * @param dmap + * + * @return void* (Virtual address) + */ +inline void* +__adf_os_dmamem_alloc(__adf_os_device_t osdev, adf_os_size_t size, + a_bool_t coherent, __adf_os_dma_map_t *dmap) +{ + (*dmap) = A_ALLOCRAM(sizeof(struct __adf_dma_map)); + + if((*dmap) == NULL){ + goto fail_malloc; + } + + (*dmap)->ds_addr = A_ALLOCRAM(size); + (*dmap)->ds_len = size; + + return (*dmap)->ds_addr; + +fail_malloc: + return NULL; +} diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_dma_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_dma_pvt.h new file mode 100755 index 0000000..508bea8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_dma_pvt.h @@ -0,0 +1,42 @@ +#ifndef __ADF_NBUF_DMA_PVT_H +#define __ADF_NBUF_DMA_PVT_H + +#include +#include + +inline void* +__adf_os_dmamem_alloc(__adf_os_device_t osdev, adf_os_size_t size, + a_bool_t coherent, __adf_os_dma_map_t *dmap); + +/* + * Free a previously mapped DMA buffer + * Direction doesnt matter, since this API is called at closing time. + */ +static inline void +__adf_os_dmamem_free(adf_os_device_t osdev, __adf_os_size_t size, a_bool_t coherent, + void *vaddr, __adf_os_dma_map_t dmap) +{ + +} + + +//#define __adf_os_dmamem_map2addr(_dmap) ((_dmap)->seg[0].ds_addr) +#define __adf_os_dmamem_map2addr(_dmap) ((adf_os_dma_addr_t)(_dmap)->ds_addr) + +static inline void +__adf_os_dmamem_cache_sync(__adf_os_device_t osdev, __adf_os_dma_map_t dmap, adf_os_cache_sync_t sync) +{ + +} + + +static inline adf_os_size_t +__adf_os_cache_line_size(void) +{ + /** + * Todo + */ + return 0; +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_io_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_io_pvt.h new file mode 100755 index 0000000..98cfcbb --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_io_pvt.h @@ -0,0 +1,69 @@ +#ifndef _ADF_OS_IO_PVT_H +#define _ADF_OS_IO_PVT_H + +#include + +#define __bswap16(x) \ + ((((x) & 0xff00) >> 8) | \ + (((x) & 0x00ff) << 8)) + +#define __bswap32(x) \ + ((((x) & 0xff000000) >> 24) | \ + (((x) & 0x00ff0000) >> 8) | \ + (((x) & 0x0000ff00) << 8) | \ + (((x) & 0x000000ff) << 24)) + +#if 0 +static __inline __uint64_t +__bswap64(__uint64_t _x) +{ + + return ((_x >> 56) | ((_x >> 40) & 0xff00) | ((_x >> 24) & 0xff0000) | + ((_x >> 8) & 0xff000000) | ((_x << 8) & ((__uint64_t)0xff << 32)) | + ((_x << 24) & ((__uint64_t)0xff << 40)) | + ((_x << 40) & ((__uint64_t)0xff << 48)) | ((_x << 56))); +} +#endif + +#define __adf_os_reg_read8(_dev, _addr) oops no implementation... + +#define __adf_os_reg_read16(_dev, _addr) oops no implementation... + +#define __adf_os_reg_read32(_dev, _addr) *((a_uint32_t *)(WLAN_BASE_ADDRESS + _addr)) + +#define __adf_os_reg_read64(_dev, _addr) oops no implementation... + +#define __adf_os_reg_write8(_dev, _addr, _val) oops no implementation... + +#define __adf_os_reg_write16(_dev, _addr, _val) oops no implementation... + +// RAY: The delay is required. But needs to know why?? +//#define __adf_os_reg_write32(_dev, _addr, _val) *((a_uint32_t *)(0x10ff0000 + _addr)) = _val; A_DELAY_USECS(100); +//RAY 0806: Move the delay (100us) to the host side because of throughput issue +#define __adf_os_reg_write32(_dev, _addr, _val) *((a_uint32_t *)(WLAN_BASE_ADDRESS + _addr)) = _val; + +#define __adf_os_reg_write64(_dev, _addr, _val) oops no implementation... + +#define __adf_os_ntohs(x) x +#define __adf_os_ntohl(x) x + +#define __adf_os_htons(x) x +#define __adf_os_htonl(x) x + +#define __adf_os_cpu_to_le16(x) __bswap16(x) +#define __adf_os_cpu_to_le32(x) __bswap32(x) +#define __adf_os_cpu_to_le64(x) x + +#define __adf_os_cpu_to_be16(x) x +#define __adf_os_cpu_to_be32(x) x +#define __adf_os_cpu_to_be64(x) x + +#define __adf_os_le16_to_cpu(x) __bswap16(x) +#define __adf_os_le32_to_cpu(x) __bswap32(x) +#define __adf_os_le64_to_cpu(x) x + +#define __adf_os_be16_to_cpu(x) x +#define __adf_os_be32_to_cpu(x) x +#define __adf_os_be64_to_cpu(x) x + +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_irq_pvt.c b/target_firmware/magpie_fw_dev/target/adf/adf_os_irq_pvt.c new file mode 100755 index 0000000..69f0b42 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_irq_pvt.c @@ -0,0 +1,35 @@ + +#include +#include + +int __adf_os_setup_intr(__adf_os_device_t osdev, adf_os_drv_intr fn); +void __adf_os_free_intr(__adf_os_device_t osdev); + +extern adf_os_drv_intr g_wlan_intr; + +/** + * @brief setup the Interrupt handler for the driver + * @param[in] dev + * @param[in] sc + * + * @return int + */ + +int +__adf_os_setup_intr(__adf_os_device_t osdev, adf_os_drv_intr fn) +{ + g_wlan_intr = fn; + + return 0; +} + +/** + * @brief deregister from the kernel the interrupt handler + * @param[in] dev + * @param[in] sc + */ +void +__adf_os_free_intr(__adf_os_device_t osdev) +{ + g_wlan_intr = NULL; +} diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_irq_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_irq_pvt.h new file mode 100755 index 0000000..2730b37 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_irq_pvt.h @@ -0,0 +1,7 @@ +#ifndef __ADF_OS_IRQ_PVT_H +#define __ADF_OS_IRQ_PVT_H + +int __adf_os_setup_intr(__adf_os_device_t osdev, adf_os_drv_intr fn); +void __adf_os_free_intr(__adf_os_device_t osdev); + +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_lock_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_lock_pvt.h new file mode 100755 index 0000000..bf9654c --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_lock_pvt.h @@ -0,0 +1,51 @@ +#ifndef _ADF_OS_LOCK_PVT_H +#define _ADF_OS_LOCK_PVT_H + +typedef int __adf_os_spinlock_t; +typedef int __adf_os_mutex_t; + +static inline void __adf_os_init_mutex(__adf_os_mutex_t *mtx) +{ + +} + +static inline int __adf_os_mutex_acquire(__adf_os_mutex_t *mtx) +{ + return 0; +} +static inline void __adf_os_mutex_release(__adf_os_mutex_t *mtx) +{ + +} +static inline void __adf_os_spinlock_init(__adf_os_spinlock_t *lock) +{ + +} +/* + * Synchronous versions - only for OS' that have interrupt disable + */ +static inline void __adf_os_spin_lock_irq(__adf_os_spinlock_t *lock, a_uint32_t *flags) +{ + //mtx_lock_spin(lock); + (*flags)=0; +} + +static inline void __adf_os_spin_unlock_irq(__adf_os_spinlock_t *lock, a_uint32_t *flags) +{ + //mtx_unlock_spin(lock); +} + +static inline void __adf_os_spin_lock_bh(__adf_os_spinlock_t *lock) +{ + //mtx_lock_spin(lock); +} +static inline void __adf_os_spin_unlock_bh(__adf_os_spinlock_t *lock) +{ + //mtx_unlock_spin(lock); +} +static inline a_bool_t __adf_os_spinlock_irq_exec(adf_os_handle_t hdl, __adf_os_spinlock_t *lock, + adf_os_irqlocked_func_t func, void *arg) +{ + return 0; +} +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_mem_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_mem_pvt.h new file mode 100755 index 0000000..cf8dadd --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_mem_pvt.h @@ -0,0 +1,48 @@ +#ifndef ADF_OS_MEM_PVT_H +#define ADF_OS_MEM_PVT_H + +#include "cmnos_api.h" +#include "Magpie_api.h" + +static inline void * __adf_os_mem_alloc(adf_os_size_t size) +{ +// return (malloc(size,M_DEVBUF,M_DONTWAIT | M_ZERO)); + return A_ALLOCRAM(size); +} + +static inline void __adf_os_mem_free(void *buf) +{ + //Should not be called in FW! + //free(buf,M_DEVBUF); +} + +/* move a memory buffer */ +static inline void __adf_os_mem_copy(void *dst, void *src, adf_os_size_t size) +{ + A_MEMCPY(dst,src,size); +} + +/* set a memory buffer */ +static inline void +__adf_os_mem_set(void *buf, a_uint8_t b, adf_os_size_t size) +{ + A_MEMSET(buf, b, size); +} +static inline void +__adf_os_mem_move(void *dst, void *src, adf_os_size_t size) +{ + A_MEMMOVE(dst, src, size); +} +/* zero a memory buffer */ +static inline void +__adf_os_mem_zero(void *buf, adf_os_size_t size) +{ + A_MEMZERO(buf,size); +} +/* compare two memory buffers */ +static inline int +__adf_os_mem_cmp(void *buf1, void *buf2, adf_os_size_t size) +{ + return (A_MEMCMP (buf1, buf2, size) == 0) ? 0 : 1; +} +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_module_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_module_pvt.h new file mode 100755 index 0000000..d42be1a --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_module_pvt.h @@ -0,0 +1,44 @@ +#ifndef __ADF_OS_MODULE_PVT_H +#define __ADF_OS_MODULE_PVT_H + +//#include +//#include + + +//int __adf_os_virt_mod(struct module *mod, int event, void *arg); + + + + +/** + * MACRO's for initiallization + */ + +/** + * init module macro + */ +#define __adf_os_virt_module_init(_fn) + +/** + * @brief generic driver /module init function + * + * @param mod (module data) + * @param event (LOAD or UNLOAD) + * @param arg (any extra argument needed if + * + * @return int + */ +/** + * exit module macro + */ +#define __adf_os_virt_module_exit(_fn) + +/** + * initiallize a generic module + */ +#define __adf_os_virt_module_name(_name) + + +#define __adf_os_module_dep(_name, _dep) + +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_pci_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_pci_pvt.h new file mode 100755 index 0000000..20f6e85 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_pci_pvt.h @@ -0,0 +1,86 @@ +#ifndef __ADF_OS_PCI_PVT_H +#define __ADF_OS_PCI_PVT_H + +#include + +//extern A_PCI_INIT_FUNC g_pci_init_func; + +/** + * init module macro + */ +#define __adf_os_pci_module_init(_fn) A_PCI_INIT_FUNC g_pci_init_func = _fn; + +/** + * exit module macro + */ +#define __adf_os_pci_module_exit(_fn) + +/** + * initiallize the PCI driver structure + * Instance name will be _pci_info + */ +#define __adf_os_pci_set_drv_info(_name, _pci_ids, _attach, _detach, _suspend, _resume) \ +{ \ + (_attach), \ + (_detach), \ + (_suspend), \ + (_resume), \ + ADF_OS_BUS_TYPE_PCI, \ + { (_pci_ids)}, \ + #_name \ +}; + +/** + * XXX: pci functions undone + * @param osdev + * @param offset + * @param val + * + * @return int + */ +static inline int +__adf_os_pci_config_read8(adf_os_device_t osdev, int offset, a_uint8_t *val) +{ + (*val) = wlan_pci_config_read(offset, 1); + return 0; + /** + * XXX:how do we know the read succeded + */ +} + +static inline int +__adf_os_pci_config_write8(adf_os_device_t osdev, int offset, a_uint8_t val) +{ + wlan_pci_config_write(offset, val, 1); + return 0; +} + +static inline int +__adf_os_pci_config_read16(adf_os_device_t osdev, int offset, a_uint16_t *val) +{ + (*val) = wlan_pci_config_read(offset, 2); + return 0; +} + +static inline int +__adf_os_pci_config_write16(adf_os_device_t osdev, int offset, a_uint16_t val) +{ + wlan_pci_config_write(offset, val, 2); + return 0; +} + +static inline int +__adf_os_pci_config_read32(adf_os_device_t osdev, int offset, a_uint32_t *val) +{ + (*val) = wlan_pci_config_read(offset, 4); + return 0; +} + +static inline int +__adf_os_pci_config_write32(adf_os_device_t osdev, int offset, a_uint32_t val) +{ + wlan_pci_config_write(offset, val, 4); + return 0; +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_time_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_time_pvt.h new file mode 100755 index 0000000..6c9e355 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_time_pvt.h @@ -0,0 +1,47 @@ +#ifndef _ADF_OS_TIME_PVT_H +#define _ADF_OS_TIME_PVT_H + +#include +#include "Magpie_api.h" + +/** + * @brief this code is modified version of tvtohz(9) which + * returns signed int which we don't require, hence we + * got rid of the type casting thing + * + * @return unsigned long + */ +static inline unsigned long +__adf_os_ticks(void) +{ + return MSEC_TO_TICK(A_MILLISECONDS()); +} +static inline a_uint32_t +__adf_os_ticks_to_msecs(unsigned long ticks) +{ + return TICK_TO_MSEC(ticks); +} +static inline unsigned long +__adf_os_msecs_to_ticks(a_uint32_t msecs) +{ + return MSEC_TO_TICK(msecs); +} +static inline unsigned long +__adf_os_getuptime(void) +{ + return MSEC_TO_TICK(A_MILLISECONDS());; +} + +static inline void +__adf_os_udelay(int usecs) +{ + A_DELAY_USECS(usecs); +} + +static inline void +__adf_os_mdelay(int msecs) +{ + A_DELAY_USECS(msecs*1000); +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_timer.c b/target_firmware/magpie_fw_dev/target/adf/adf_os_timer.c new file mode 100755 index 0000000..519d9a3 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_timer.c @@ -0,0 +1,11 @@ + +#include +#include + +void +__adf_os_timer_func(A_HANDLE timer_handle, void *arg) +{ + __adf_os_timer_t *timer = (__adf_os_timer_t *)timer_handle; + + timer->timer_func(arg); +} diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_timer_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_timer_pvt.h new file mode 100755 index 0000000..43cb0ca --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_timer_pvt.h @@ -0,0 +1,73 @@ +#ifndef _ADF_OS_TIMER_PVT_H +#define _ADF_OS_TIMER_PVT_H + +#include +#include "Magpie_api.h" + + +typedef struct +{ + A_timer_t *magpie_timer; + adf_os_timer_func_t timer_func; +}__adf_os_timer_t; + +//typedef A_timer_t __adf_os_timer_t; + +void +__adf_os_timer_func(A_HANDLE timer_handle, void *arg); + +/* + * Initialize a timer + */ +static inline void +__adf_os_timer_init(adf_os_handle_t hdl, __adf_os_timer_t *timer, + adf_os_timer_func_t func, void *arg) +{ + timer->timer_func = func; + A_INIT_TIMER(timer->magpie_timer, __adf_os_timer_func, arg); +} + +/* + * start a timer + */ +static inline void +__adf_os_timer_start(__adf_os_timer_t *timer, int msec) +{ + A_TIMEOUT_MS(timer->magpie_timer, msec); +} +/* + * Cancel a timer + * + * Return: TRUE if timer was cancelled and deactived, + * FALSE if timer was cancelled but already got fired. + */ +static inline a_bool_t +__adf_os_timer_cancel(__adf_os_timer_t *timer) +{ + A_UNTIMEOUT(timer->magpie_timer); + return A_TRUE; +} + +/* + * XXX Synchronously canel a timer + * + * Return: TRUE if timer was cancelled and deactived, + * FALSE if timer was cancelled but already got fired. + * + * Synchronization Rules: + * 1. caller must make sure timer function will not use + * adf_os_set_timer to add iteself again. + * 2. caller must not hold any lock that timer function + * is likely to hold as well. + * 3. It can't be called from interrupt context. + */ +static inline a_bool_t +__adf_os_timer_sync_cancel(__adf_os_timer_t *timer) +{ + // @TODO: IS OK?? + A_UNTIMEOUT(timer->magpie_timer); + return A_TRUE; +} + + +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_types_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_types_pvt.h new file mode 100755 index 0000000..38921f3 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_types_pvt.h @@ -0,0 +1,146 @@ +#ifndef __ADF_OS_TYPES_PVT_H +#define __ADF_OS_TYPES_PVT_H + +#include +#include +//#include "cmnos_api.h" +//#include "Magpie_api.h" +#include + +#define __ADF_OS_MAX_SCATTER 1 +#define __adf_os_packed __attribute__((__packed__)) +#define __ADF_OS_NAME_SIZE 10 + +/* + * Private definitions of general data types + */ +/** + * Endian-ness + */ +#undef ADF_LITTLE_ENDIAN_MACHINE +#undef ADF_BIG_ENDIAN_MACHINE + +//#if (_BYTE_ORDER == _LITTLE_ENDIAN) +#ifdef LITTLE_ENDIAN +#define ADF_LITTLE_ENDIAN_MACHINE +//#elif (_BYTE_ORDER == _BIG_ENDIAN) +#elif BIG_ENDIAN +#define ADF_BIG_ENDIAN_MACHINE +#endif + +/** + * CACHE-SYNC (DMA) + */ +#define __ADF_SYNC_PREREAD 0 +#define __ADF_SYNC_POSTREAD 1 +#define __ADF_SYNC_PREWRITE 2 +#define __ADF_SYNC_POSTWRITE 3 + +#define __ADF_OS_DMA_TO_DEVICE 0 +#define __ADF_OS_DMA_FROM_DEVICE 1 + + +struct __adf_softc; + + +enum __adf_net_wireless_evcode{ + __ADF_IEEE80211_ASSOC = 100, + __ADF_IEEE80211_REASSOC = 101, + __ADF_IEEE80211_DISASSOC = 102, + __ADF_IEEE80211_JOIN = 103, + __ADF_IEEE80211_LEAVE = 104, + __ADF_IEEE80211_SCAN = 105, + __ADF_IEEE80211_REPLAY = 106, + __ADF_IEEE80211_MICHAEL = 107, + __ADF_IEEE80211_REJOIN = 108, + __ADF_CUSTOM_PUSH_BUTTON = 109, +}; + +/* generic data types */ +struct __adf_device { +int dummy; +}; + +typedef struct __adf_device *__adf_os_device_t; + + +struct __adf_dma_map { + VBUF *buf; + + A_UINT32 *ds_addr; + A_UINT16 ds_len; +}; + +typedef struct __adf_dma_map *__adf_os_dma_map_t; + +typedef A_UINT32 __adf_os_dma_addr_t; +typedef A_UINT32 __adf_os_dma_size_t; + +typedef unsigned int __adf_os_size_t; +typedef int __adf_os_off_t; + +#define __adf_os_iomem_t + +#if 0 +typedef int __a_uint8_t; +typedef int __a_int8_t; +typedef int __a_uint16_t; +typedef int __a_int16_t; +typedef int __a_uint32_t; +typedef int __a_int32_t; +typedef int __a_uint64_t; +typedef int __a_int64_t; +#else +typedef A_UINT8 __a_uint8_t; +typedef A_INT8 __a_int8_t; +typedef A_UINT16 __a_uint16_t; +typedef A_INT16 __a_int16_t; +typedef A_UINT32 __a_uint32_t; +typedef A_INT32 __a_int32_t; +typedef A_UINT64 __a_uint64_t; +typedef A_INT64 __a_int64_t; + +typedef A_UINT32 u_int32_t; +typedef A_UINT16 u_int16_t; +typedef A_UINT8 u_int8_t; +typedef unsigned int u_int; +typedef unsigned long u_long; +//typedef __adf_os_size_t size_t; + +typedef A_UINT64 u_int64_t; + +#endif + +//extern void my_printf(struct ath_hal *ah, const char* fmt, ...); + +//#define __adf_os_print my_printf +#define __adf_os_print A_PRINTF + +#if 1 +#if defined(__XCC__) +#include "stdarg.h" +#define __va_list __gnuc_va_list +#endif +#endif + +/* For compiling WLAN drivers */ +#define IFNAMSIZ 10 +#define ENXIO -1 +#define ENOMEM -1 +#define EIO -1 +#define caddr_t int +#define ENODEV -1 +#define EOPNOTSUPP -1 +#define KASSERT(exp, msg) + +#if 0 +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif + +#ifndef roundup +#define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */ +#endif +#endif + +#endif diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_util_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_util_pvt.h new file mode 100755 index 0000000..f147f19 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_util_pvt.h @@ -0,0 +1,66 @@ +#ifndef __ADF_OS_UTIL_PVT_H +#define __ADF_OS_UTIL_PVT_H + +#include + +#define __adf_os_unlikely(_expr) +#define __adf_os_likely(_expr) + +/** + * @brief memory barriers. + */ +#define __adf_os_wmb() oops no implementation... +#define __adf_os_rmb() oops no implementation... +#define __adf_os_mb() oops no implementation... + +#define __adf_os_min(_a, _b) ((_a < _b) ? _a : _b) +#define __adf_os_max(_a, _b) ((_a > _b) ? _a : _b) + +#ifdef _DEBUG_BUILD_ +#define __adf_os_assert(expr) do {\ + if(!(expr)) { \ + adf_os_print("Assertion failed! %s:%s %s:%d\n", #expr, __FUNCTION__, __FILE__, __LINE__); \ + while(1){} \ + \ + }\ +}while(0); +#else +#if defined(PROJECT_MAGPIE) +#define __adf_os_assert(expr) do { \ + if(!(expr)) { \ + adf_os_print("Assertion failed! %s\n", __FUNCTION__); \ + (*((volatile uint32_t *)(0x12345678))); \ + } \ +}while(0); +#else +#define __adf_os_assert(expr) do { \ + if(!(expr)) { \ + while(1){} \ + } \ +}while(0); +#endif +#endif + +#ifndef inline +#define inline +#endif + +static void inline +__adf_os_get_rand(adf_os_handle_t hdl,__a_uint8_t *ptr, __a_uint32_t len) +{ +#if 0 + u_int8_t *dp = ptr; + u_int32_t v; + size_t nb; + while (len > 0) { + v = arc4random(); + nb = len > sizeof(u_int32_t) ? sizeof(u_int32_t) : len; + bcopy(&v, dp, len > sizeof(u_int32_t) ? sizeof(u_int32_t) : len); + dp += sizeof(u_int32_t); + len -= nb; + } +#endif +} + + +#endif /*_ADF_OS_UTIL_PVT_H*/ diff --git a/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_api.h b/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_api.h new file mode 100755 index 0000000..c69e1b7 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_api.h @@ -0,0 +1,50 @@ +/* + * @File: buf_pool_api.h + * + * @Abstract: BUF Pool api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _BUF_POOL_API_H +#define _BUF_POOL_API_H + +#include + +/* endpoint defines */ +typedef enum +{ + POOL_ID_HTC_CONTROL = 0, + POOL_ID_WMI_SVC_CMD_REPLY = 1, + POOL_ID_WMI_SVC_EVENT = 2, + POOL_ID_WLAN_RX_BUF = 3, + POOL_ID_MAX = 10 +} BUF_POOL_ID; + +typedef void* pool_handle_t; + +/* hardware API table structure (API descriptions below) */ +struct buf_pool_api { + pool_handle_t (*_init)(adf_os_handle_t handle); + + void (*_shutdown)(pool_handle_t handle); + + void (*_create_pool)(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize); + + adf_nbuf_t (*_alloc_buf)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve); + + adf_nbuf_t (*_alloc_buf_align)(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align); + + void (*_free_buf)(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void buf_pool_module_install(struct buf_pool_api *apis); + +#endif /* #ifndef _BUF_POOL_API_H */ diff --git a/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_dynamic.c b/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_dynamic.c new file mode 100755 index 0000000..33caf24 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_dynamic.c @@ -0,0 +1,97 @@ +/* + * @File: + * + * @Abstract: Buf pool implementation: Dynamic version + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ +#include +#include +#include +#include +//#include +#include + +LOCAL htc_handle_t _buf_pool_dynamic_init(adf_os_handle_t handle); +LOCAL void _buf_pool_dynamic_create_pool(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize); +LOCAL adf_nbuf_t _buf_pool_dynamic_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve); +LOCAL adf_nbuf_t _buf_pool_dynamic_alloc_buf_align(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align); +LOCAL void _buf_pool_dynamic_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf); +LOCAL void _buf_pool_dynamic_shutdown(pool_handle_t handle); + +typedef struct _POOL_CONFIG { + int nSize; +} POOL_CONFIG; + +typedef struct _BUF_POOL_DYNAMIC_CONTEXT { + adf_os_handle_t OSHandle; + POOL_CONFIG poolConf[POOL_ID_MAX]; +} BUF_POOL_DYNAMIC_CONTEXT; + +void buf_pool_module_install(struct buf_pool_api *pAPIs) +{ + pAPIs->_init = _buf_pool_dynamic_init; + pAPIs->_create_pool = _buf_pool_dynamic_create_pool; + pAPIs->_alloc_buf = _buf_pool_dynamic_alloc_buf; + pAPIs->_alloc_buf_align = _buf_pool_dynamic_alloc_buf_align; + pAPIs->_free_buf = _buf_pool_dynamic_free_buf; + pAPIs->_shutdown = _buf_pool_dynamic_shutdown; +} + +LOCAL pool_handle_t _buf_pool_dynamic_init(adf_os_handle_t handle) +{ + BUF_POOL_DYNAMIC_CONTEXT *ctx; + + ctx = (BUF_POOL_DYNAMIC_CONTEXT *)adf_os_mem_alloc(sizeof(BUF_POOL_DYNAMIC_CONTEXT)); + ctx->OSHandle = handle; + + return ctx; +} + +LOCAL void _buf_pool_dynamic_shutdown(pool_handle_t handle) +{ + BUF_POOL_DYNAMIC_CONTEXT *ctx = (BUF_POOL_DYNAMIC_CONTEXT *)handle; + + adf_os_mem_free(ctx); +} + +LOCAL void _buf_pool_dynamic_create_pool(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize) +{ + BUF_POOL_DYNAMIC_CONTEXT *ctx = (BUF_POOL_DYNAMIC_CONTEXT *)handle; + + ctx->poolConf[poolId].nSize = nSize; +} + +LOCAL adf_nbuf_t _buf_pool_dynamic_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve) +{ + BUF_POOL_DYNAMIC_CONTEXT *ctx = (BUF_POOL_DYNAMIC_CONTEXT *)handle; + POOL_CONFIG *poolConf = &ctx->poolConf[poolId]; + + return adf_nbuf_alloc(poolConf->nSize, + reserve, 0); + +} + +LOCAL adf_nbuf_t _buf_pool_dynamic_alloc_buf_align(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align) +{ + BUF_POOL_DYNAMIC_CONTEXT *ctx = (BUF_POOL_DYNAMIC_CONTEXT *)handle; + POOL_CONFIG *poolConf = &ctx->poolConf[poolId]; + + return adf_nbuf_alloc(poolConf->nSize, + reserve, align); + +} + +LOCAL void _buf_pool_dynamic_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf) +{ + //BUF_POOL_DYNAMIC_CONTEXT *ctx = (BUF_POOL_DYNAMIC_CONTEXT *)handle; + + adf_nbuf_free(buf); +} + +adf_os_export_symbol(buf_pool_module_install); diff --git a/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_static.c b/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_static.c new file mode 100755 index 0000000..8365a60 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_static.c @@ -0,0 +1,128 @@ +/* + * @File: + * + * @Abstract: Buf pool implementation: static version + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "buf_pool_static.h" + +LOCAL htc_handle_t _buf_pool_static_init(adf_net_handle_t handle); +LOCAL void _buf_pool_static_create_pool(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize); +LOCAL adf_nbuf_t _buf_pool_static_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve); +LOCAL adf_nbuf_t _buf_pool_static_alloc_buf_align(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align); +LOCAL void _buf_pool_static_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf); +LOCAL void _buf_pool_static_shutdown(pool_handle_t handle); + +BUF_POOL_STATIC_CONTEXT g_poolCtx; + +void buf_pool_module_install(struct buf_pool_api *pAPIs) +{ + pAPIs->_init = _buf_pool_static_init; + pAPIs->_create_pool = _buf_pool_static_create_pool; + pAPIs->_alloc_buf = _buf_pool_static_alloc_buf; + pAPIs->_alloc_buf_align = _buf_pool_static_alloc_buf_align; + pAPIs->_free_buf = _buf_pool_static_free_buf; + pAPIs->_shutdown = _buf_pool_static_shutdown; +} + +LOCAL pool_handle_t _buf_pool_static_init(adf_os_handle_t handle) +{ +#if 1 + int i; + + for(i=0; i < POOL_ID_MAX; i++) { + g_poolCtx.bufQ[i] = NULL; + } + + return &g_poolCtx; +#else + BUF_POOL_STATIC_CONTEXT *ctx; + + //ctx = (BUF_POOL_static_CONTEXT *)A_ALLOCRAM(sizeof(BUF_POOL_static_CONTEXT)); + ctx = (BUF_POOL_STATIC_CONTEXT *)adf_os_mem_alloc(sizeof(BUF_POOL_STATIC_CONTEXT)); + ctx->NetHandle = handle; + + return ctx; +#endif +} + +LOCAL void _buf_pool_static_shutdown(pool_handle_t handle) +{ + // SHALL NOT BE USED in FW +} + +LOCAL void _buf_pool_static_create_pool(pool_handle_t handle, BUF_POOL_ID poolId, int nItems, int nSize) +{ + int i; + VBUF *buf; + VDESC *desc; + + //BUF_POOL_STATIC_CONTEXT *ctx = (BUF_POOL_STATIC_CONTEXT *)handle; + + for ( i = 0; i < nItems; i++) { + buf = VBUF_alloc_vbuf(); + desc = VDESC_alloc_vdesc(); + + desc->buf_addr = (A_UINT8 *)adf_os_mem_alloc(nSize); + desc->buf_size = nSize; + desc->data_offset = 0; + desc->data_size = 0; + + buf->buf_length = 0; + buf->desc_list = desc; + + if ( g_poolCtx.bufQ[poolId] == NULL ) { + g_poolCtx.bufQ[poolId] = buf; + } else { + buf->next_buf = g_poolCtx.bufQ[poolId]; + g_poolCtx.bufQ[poolId] = buf; + } + } +} + +LOCAL adf_nbuf_t _buf_pool_static_alloc_buf(pool_handle_t handle, BUF_POOL_ID poolId, int reserve) +{ + VBUF *buf; + + buf = g_poolCtx.bufQ[poolId]; + if ( buf != NULL ) { + g_poolCtx.bufQ[poolId] = buf->next_buf; + + buf->next_buf = NULL; + buf->desc_list->data_offset = reserve; + buf->desc_list->data_size = 0; + buf->buf_length = 0; + } + + return buf; +} + +LOCAL adf_nbuf_t _buf_pool_static_alloc_buf_align(pool_handle_t handle, BUF_POOL_ID poolId, int reserve, int align) +{ + return _buf_pool_static_alloc_buf(handle, poolId, reserve); +} + +LOCAL void _buf_pool_static_free_buf(pool_handle_t handle, BUF_POOL_ID poolId, adf_nbuf_t buf) +{ + if ( g_poolCtx.bufQ[poolId] == NULL ) { + g_poolCtx.bufQ[poolId] = buf; + } else { + buf->next_buf = g_poolCtx.bufQ[poolId]; + g_poolCtx.bufQ[poolId] = buf; + } +} diff --git a/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_static.h b/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_static.h new file mode 100755 index 0000000..32feb19 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/buf_pool/buf_pool_static.h @@ -0,0 +1,24 @@ +/* + * @File: + * + * @Abstract: + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef BUF_POOL_STATIC_H_ +#define BUF_POOL_STATIC_H_ + +typedef struct _BUF_POOL_STATIC_CONTEXT { + VBUF *bufQ[POOL_ID_MAX]; + + // Left a door for extension the structure + void *pReserved; +} BUF_POOL_STATIC_CONTEXT; + +#endif /*BUF_POOL_STATIC_H_*/ diff --git a/target_firmware/magpie_fw_dev/target/cmnos/clock_api.h b/target_firmware/magpie_fw_dev/target/cmnos/clock_api.h new file mode 100755 index 0000000..e4c9b27 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/cmnos/clock_api.h @@ -0,0 +1,21 @@ +#ifndef __CLOCK_API_H__ +#define __CLOCK_API_H__ + +#define TICK_MSEC_RATIO 1 +#define TICK_TO_MSEC(tick) ((tick)/TICK_MSEC_RATIO) +#define MSEC_TO_TICK(msec) ((msec)* TICK_MSEC_RATIO) + +struct clock_api { + void (* _clock_init)(A_UINT32 ref_clk); + void (* _clockregs_init)(void); + A_UINT32 (* _uart_frequency)(void); + void (* _delay_us)(int); + void (* _wlan_band_set)(int); + A_UINT32 (* _refclk_speed_get)(void); + A_UINT32 (* _milliseconds)(void); + void (* _sysclk_change)(void); + + void (* _clock_tick)(void); +}; + +#endif /* __CLOCK_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/cmnos/cmnos_api.h b/target_firmware/magpie_fw_dev/target/cmnos/cmnos_api.h new file mode 100755 index 0000000..40fa033 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/cmnos/cmnos_api.h @@ -0,0 +1,638 @@ +#ifndef __CMNOS_API_H__ +#define __CMNOS_API_H__ + +/* + * This file contains wrappers to OS operating system functions + * that are available in all versions of the operating system. + * + * Target software must always use these wrappers to access OS + * services -- it may not access any OS services directly. + */ + +#include "sys_cfg.h" + +#include "xtensa/config/core.h" +#include "xtensa/hal.h" +#include "xtensa/xtruntime.h" + +/* cmnos interface */ +#include "printf_api.h" +#include "uart_api.h" +#include "dbg_api.h" +#include "mem_api.h" +#include "misc_api.h" +#include "string_api.h" +#include "timer_api.h" +#include "romp_api.h" +#include "allocram_api.h" +#include "tasklet_api.h" +#include "clock_api.h" +#include "intr_api.h" +#include "wdt_api.h" +#include "eeprom_api.h" +#include "usb_api.h" +#include +#include + +#if defined(PROJECT_K2) +#if SYSTEM_MODULE_SFLASH +#include "sflash_api.h" +#endif +#endif + +#define AR6K_ROM_START 0x004e0000 +#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) +#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) + +#define IML_SIGNAL_UNUSED0_ADDR TARG_ROM_ADDRS(0) /* Cannot be used -- aligned */ +#define IML_SIGNAL_ASSERT_ADDR TARG_ROM_ADDRS(1) /* Signal an assertion failure */ +#define IML_SIGNAL_PRINTF_ADDR TARG_ROM_ADDRS(2) /* Signal a printf request */ +#define IML_SIGNAL_UNUSED4_ADDR TARG_ROM_ADDRS(4) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSED8_ADDR TARG_ROM_ADDRS(8) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSEDC_ADDR TARG_ROM_ADDRS(0xc) /* Cannot be used -- aligned */ +#define IML_SIGNAL_MASK 0xfffe000f +#define IML_LINENUM_SHIFT 4 + +#define NOW() xthal_get_ccount() + +#if defined(__XTENSA__) +#define _A_BARRIER asm volatile("memw") +#else +#define _A_BARRIER +#endif + +#define A_ASSERT( __bool ) \ + do { \ + if (0 == (__bool)) { \ + (void)*((volatile int *)(IML_SIGNAL_ASSERT_ADDR+(__LINE__<<4)));\ + _A_BARRIER; \ + } \ + } while (0) + + +#define A_IML_IS_ASSERT(vaddr) \ + (((vaddr) & IML_SIGNAL_MASK) == (IML_SIGNAL_ASSERT_ADDR & IML_SIGNAL_MASK)) + + +#define PRINT_FAILURE_STATE() \ +do { \ + uint32_t epc1, epc2, epc3, epc4; \ + \ + asm volatile("rsr %0,%1" : "=r" (epc1) : "n" (EPC_1)); \ + asm volatile("rsr %0,%1" : "=r" (epc2) : "n" (EPC_2)); \ + asm volatile("rsr %0,%1" : "=r" (epc3) : "n" (EPC_3)); \ + asm volatile("rsr %0,%1" : "=r" (epc4) : "n" (EPC_4)); \ + \ + A_PRINTF("\tepc1=0x%x, epc2=0x%x, epc3=0x%x, epc4=0x%x\n", \ + epc1, epc2, epc3, epc4); \ + A_PRINTF("0x%08x, 0x%08x, 0x%08x, \n\r", \ + DEBUG_SYSTEM_STATE, WATCH_DOG_RESET_COUNTER, \ + WATCH_DOG_MAGIC_PATTERN); \ +} while(0) +//////////////////////////////////////////////////////////////////////////////////// + + +//#define A_CMN(sym) _A_OS_INDIRECTION_TABLE->cmnos.sym +#define A_CMN(sym) _A_MAGPIE_INDIRECTION_TABLE->cmnos.sym + +#if SYSTEM_MODULE_MEM +/* Mem interfaces */ +#define A_MEMSET(addr, value, size) \ + A_CMN(mem._memset((char *)(addr), (int)(value), (int)(size))) + +#define A_MEMZERO(addr, size) \ + A_CMN(mem._memset((char *)(addr), (int)0, (int)(size))) + +#define A_MEMCPY(dst, src, size) \ + A_CMN(mem._memcpy((char *)(dst), (char *)(src), (int)(size))) + +#define A_MEMMOVE(dst, src, size) \ + A_CMN(mem._memmove((char *)(dst), (char *)(src), (int)(size))) + +#define A_MEMCMP(p1, p2, nbytes) \ + A_CMN(mem._memcmp)((void *)(p1), (void *)(p2), (int)(nbytes)) +#else +/* Mem interfaces */ +#define A_MEMSET(addr, value, size) + +#define A_MEMZERO(addr, size) + +#define A_MEMCPY(dst, src, size) + +#define A_MEMMOVE(dst, src, size) + +#define A_MEMCMP(p1, p2, nbytes) +#endif + + +#if 1 + /* String interfaces */ + #define A_STRCPY(dst, src) A_CMN(string._strcpy((dst), (src))) + #define A_STRNCPY(dst, src, n) A_CMN(string._strncpy((dst), (src), (n))) + #define A_STRLEN(str) A_CMN(string._strlen(str)) + #define A_STRCMP(str1, str2) A_CMN(string._strcmp((str1), (str2))) + #define A_STRNCMP(str1, str2, n) A_CMN(string._strncmp((str1), (str2), (n))) +#endif + +#if SYSTEM_MODULE_PRINT +/* Printf support */ +#define A_PRINTF_INIT() A_CMN(printf._printf_init()) +#define A_PRINTF A_CMN(printf._printf) +#else +#define A_PRINTF_INIT() +#define A_PRINTF +#endif /* SYSTEM_MODULE_PRINT */ + +#if SYSTEM_MODULE_UART +/* Serial port support */ +#define A_UART_INIT() A_CMN(uart._uart_init()) + +#define A_UART_HWINIT(freq, baud) \ + A_CMN(uart._uart_hwinit((freq), (baud))) + +#define A_UART_ENABLED() (HOST_INTEREST->hi_uart_enable) + +#define A_PUTS(str) A_CMN(uart._uart_str_out(str)) + +#define A_PUTC(ch) A_CMN(uart._uart_char_put(ch)) +#define A_GETC(pCh) A_CMN(uart._uart_char_get(pCh)) + +#define A_UART_TASK() A_CMN(uart._uart_task()) +#define A_UART_CONFIG(x) A_CMN(uart._uart_config(x)) + +#else + +#define A_UART_INIT() + +#define A_UART_HWINIT(freq, baud) + +#define A_UART_ENABLED() + +#define A_PUTS(str) + +#define A_PUTC(ch) +#define A_GETC(pCh) + +#define A_UART_TASK() +#define A_UART_CONFIG(x) + +#endif + +#if SYSTEM_MODULE_MISC +/* Reset Support */ +#define A_RESET() A_CMN(misc._system_reset()) +#define A_RESET_MAC() A_CMN(misc._mac_reset()) + +/* Assertion failure */ +#define A_ASSFAIL(regdump) A_CMN(misc._assfail((regdump))) + +/* Report a failure to the Host */ +#define A_REPORT_FAILURE(data, len) \ + A_CMN(misc._report_failure_to_host((data), (len))) + +/* UNALIGNED references are used for ASSERTs */ +#define A_MISALIGNED_LOAD_HANDLER(dump) A_CMN(misc._misaligned_load_handler(dump)) + +/* reture the host interface type */ +#define A_IS_HOST_PRESENT() A_CMN(misc._is_host_present()) +#define A_KBHIT(delay) A_CMN(misc._kbhit(delay)) +#define A_GET_ROM_VER() A_CMN(misc._rom_version_get()) +#else +/* Reset Support */ +#define A_RESET() +#define A_RESET_MAC() + +/* Assertion failure */ +#define A_ASSFAIL(regdump) + +#define A_MISALIGNED_LOAD_HANDLER(dump) + +/* Report a failure to the Host */ +#define A_REPORT_FAILURE(data, len) + +#define A_IS_HOST_PRESENT() +#define A_KBHIT(delay) +#define A_GET_ROM_VER() +#endif + +//#if SYSTEM_MODULE_DBG +/* debug Support */ +//#define A_DBG_INIT() A_CMN(dbg._dbg_init()) +//#define A_DBG_TASK() A_CMN(dbg._dbg_task()) +//#else +//#define A_DBG_INIT() +//#define A_DBG_TASK() +//#endif + +#if SYSTEM_MODULE_USB +/* debug Support */ +#define A_USB_INIT() A_CMN(usb._usb_init()) +#define A_USB_ROM_TASK() A_CMN(usb._usb_rom_task()) +#define A_USB_FW_TASK() A_CMN(usb._usb_fw_task()) +#define A_USB_INIT_PHY() A_CMN(usb._usb_init_phy()) + +#define A_USB_EP0_SETUP() A_CMN(usb._usb_ep0_setup()) +#define A_USB_EP0_TX_DATA() A_CMN(usb._usb_ep0_tx_data()) +#define A_USB_EP0_RX_DATA() A_CMN(usb._usb_ep0_rx_data()) + +#define A_USB_GET_CONFIG() A_CMN(usb._usb_get_configuration()) +#define A_USB_SET_CONFIG() A_CMN(usb._usb_set_configuration()) + +#define A_USB_GET_INTERFACE() A_CMN(usb._usb_get_interface()) +#define A_USB_SET_INTERFACE() A_CMN(usb._usb_set_interface()) + +#define A_USB_STANDARD_CMD() A_CMN(usb._usb_standard_cmd()) +#define A_USB_VENDOR_CMD() A_CMN(usb._usb_vendor_cmd()) + +#define A_USB_POWER_OFF() A_CMN(usb._usb_power_off()) +#define A_USB_RESET_FIFO() A_CMN(usb._usb_reset_fifo()) +#define A_USB_GEN_WDT() A_CMN(usb._usb_gen_wdt()) +#define A_USB_JUMP_BOOT() A_CMN(usb._usb_jump_boot()) + +#define A_USB_GET_DESCRIPTOR() A_CMN(usb._usb_get_descriptor()) +#define A_USB_SET_ADDRESS() A_CMN(usb._usb_set_address()) +#define A_USB_SET_FEATURE() A_CMN(usb._usb_set_feature()) +#define A_USB_CLEAR_FEATURE() A_CMN(usb._usb_clr_feature()) + +#define A_USB_GET_STATUS() A_CMN(usb._usb_get_status()) +#define A_USB_SETUP_DESC() A_CMN(usb._usb_setup_desc()) +#define A_USB_STATUS_IN() A_CMN(usb._usb_status_in()) +#define A_USB_REG_OUT() A_CMN(usb._usb_reg_out()) + +#define A_USB_EP0_TX() A_CMN(usb._usb_ep0_tx()) +#define A_USB_EP0_RX() A_CMN(usb._usb_ep0_rx()) +#define A_USB_CLK_INIT() A_CMN(usb._usb_clk_init()) + +#else +#define A_USB_INIT() +#define A_USB_TASK() +#define A_USB_INIT_PHY() + +#define A_USB_EP0_SETUP() +#define A_USB_EP0_TX() +#define A_USB_EP0_RX() + +#define A_USB_GET_CONFIG() +#define A_USB_SET_CONFIG() + +#define A_USB_GET_INTERFACE() +#define A_USB_SET_INTERFACE() + +#define A_USB_STANDARD_CMD() +#define A_USB_VENDOR_CMD() + +#define A_USB_POWER_OFF() +#define A_USB_RESET_FIFO() +#define A_USB_GEN_WDT() +#define A_USB_JUMP_BOOT() + +#define A_USB_GET_DESCRIPTOR() +#define A_USB_SET_ADDRESS() +#define A_USB_SET_FEATURE() +#define A_USB_CLEAR_FEATURE() + +#define A_USB_GET_STATUS() +#define A_USB_SETUP_DESC() + + +#define A_USB_STATUS_IN() +#define A_USB_REG_OUT() + +#define A_USB_EP0_TX() +#define A_USB_EP0_RX() + +#define A_USB_CLK_INIT() +#endif + +#if SYSTEM_MODULE_INTR +/* Low-level interrupt support intended for use by OS modules */ +#define A_INTR_GET_INTRENABLE() A_CMN(intr._get_intrenable()) +#define A_INTR_SET_INTRENABLE(val) A_CMN(intr._set_intrenable(val)) +#define A_INTR_GET_INTRPENDING() A_CMN(intr._get_intrpending()) +#define A_INTR_UNBLOCK_ALL_INTRLVL() A_CMN(intr._unblock_all_intrlvl()) + +/* Interrupt support */ +#define A_INTR_INIT() A_CMN(intr._intr_init()) + +#define A_INTR_DISABLE(pOld) \ + do { \ + *(pOld) = A_CMN(intr._intr_disable()); \ + } while (0) + +#define A_INTR_RESTORE(old) A_CMN(intr._intr_restore((old))) + +#define A_INVOKE_ISR(inum) A_CMN(intr._intr_invoke_isr(inum)) + +#define A_INTR_MASK(inum) A_CMN(intr._intr_mask_inum(inum)) +#define A_INTR_UNMASK(inum) A_CMN(intr._intr_unmask_inum(inum)) + +#define A_ATTACH_ISR(inum, isr, arg) A_CMN(intr._intr_attach_isr(inum, isr, arg)) +#else +#define A_INTR_INIT() +#define A_INTR_DISABLE(pOld) +#define A_INTR_RESTORE(old) + +#define A_INTR_GET_INTRENABLE() +#define A_INTR_SET_INTRENABLE(val) +#define A_INTR_GET_INTRPENDING() +#define A_INTR_UNBLOCK_ALL_INTRLVL() +#define A_INVOKE_ISR(inum) +#define A_INTR_MASK(inum) +#define A_INTR_UNMASK(inum) +#define A_ATTACH_ISR(inum, isr, arg) + +#endif + +/* Tasklet Support */ +#define A_TASKLET_INIT() A_CMN(tasklet._tasklet_init()) +#define A_TASKLET_INIT_TASK(f, arg, t) A_CMN(tasklet._tasklet_init_task(f, arg, t)) +#define A_TASKLET_DISABLE(t) A_CMN(tasklet._tasklet_disable(t)) +#define A_TASKLET_SCHEDULE(t) A_CMN(tasklet._tasklet_schedule(t)) +#define A_TASKLET_RUN() A_CMN(tasklet._tasklet_run()) + + +/* RAM Allocation Support */ +#if defined(__mips__) +#define alloc_arena_start _end +#endif +#if defined(__XTENSA__) +#define alloc_arena_start _end +#endif + +#if SYSTEM_MODULE_CLOCK + +#define A_CLOCK_INIT(refclk_guess) A_CMN(clock._clock_init(refclk_guess)) +#define A_CLOCK_TICK() A_CMN(clock._clock_tick()) +#define A_CLOCK_GET_TICK() A_CMN(clock._clock_get_tick()) + +/* + * Get the number of millisecond ticks since the system was started. + * Note that this only approximates 1Ms. It's actually 32 ticks of + * a 32KHz clock. + * + * Returns a A_UINT32 value. + */ +#define A_MILLISECONDS() A_CMN(clock._milliseconds()) + +/* + * Get the frequency of the reference clock, expressed as + * an A_refclk_speed_t. + */ +#define A_REFCLK_SPEED_GET() A_CMN(clock._refclk_speed_get()) + +/* Spin delay */ +#define A_DELAY_USECS(us) A_CMN(clock._delay_us(us)) + +#define A_UART_FREQUENCY() A_CMN(clock._uart_frequency()) + +#define A_CLOCKREGS_INIT() A_CMN(clock._clockregs_init()) + +/* which_band is either A_BAND_24GHZ or A_BAND_5GHZ */ +#define A_WLAN_BAND_SET(which_band) \ + A_CMN(clock._wlan_band_set(which_band)) + +/* Called whenever the system clock changes speed */ +#define A_SYSCLK_CHANGE() A_CMN(clock._sysclk_change()) + +#else + +#define A_CLOCK_INIT(refclk_guess) +#define A_CLOCK_TICK() +#define A_CLOCK_GET_TICK() +#define A_MILLISECONDS() +#define A_REFCLK_SPEED_GET() +#define A_DELAY_USECS(us) +#define A_UART_FREQUENCY() +#define A_CLOCKREGS_INIT() +#define A_WLAN_BAND_SET(which_band) +#define A_SYSCLK_CHANGE() + +#endif + +// Timer +#define A_INIT_TIMER(pTimer, pFunction, pArg) \ + A_CMN(timer._timer_setfn((pTimer), (pFunction), (pArg))) + +/* Set a (possibly periodic) timer for "period" Milliseconds. */ +#define A_TIMEOUT_MS(pTimer, period) \ + A_CMN(timer._timer_arm((pTimer), (period))) + +#define A_UNTIMEOUT(pTimer) \ + A_CMN(timer._timer_disarm(pTimer)) + +#define A_TIMER_RUN() \ + A_CMN(timer._timer_run()) + +#define A_PCI_BOOT_INIT() \ + A_CMN(pci.pci_boot_init()) + +#define A_GMAC_BOOT_INIT() \ + A_CMN(gmac.gmac_boot_init()) + +#if SYSTEM_MODULE_ALLOCRAM +/* Default size of ALLOCRAM area */ +#define ARENA_SZ_DEFAULT 12000 + +#define A_ALLOCRAM_INIT(arena_start, arena_size) \ +do { \ + extern unsigned int alloc_arena_start; \ + void *astart; \ + int asize; \ + astart = (arena_start) ? (void *)(arena_start) : &alloc_arena_start; \ + asize = (arena_size) ? (arena_size) : (ARENA_SZ_DEFAULT); \ + A_CMN(allocram.cmnos_allocram_init((astart), (asize))); \ +} while (0) + +#define A_ALLOCRAM(nbytes) A_CMN(allocram.cmnos_allocram(0, (nbytes))) + +#define A_ALLOCRAM_DEBUG() A_CMN(allocram.cmnos_allocram_debug()) + +#else +#define A_ALLOCRAM_INIT(arena_start, arena_size) +#define A_ALLOCRAM(nbytes) +#define A_ALLOCRAM_DEBUG() +#endif + +#if SYSTEM_MODULE_ROM_PATCH + +#define A_ROMP_INIT() A_CMN(romp._romp_init()) +#define A_ROMP_DOWNLOAD(x) A_CMN(romp._romp_download(x)) +#define A_ROMP_DECODE(addr) A_CMN(romp._romp_decode(addr)) +#define A_ROMP_INSTALL() A_CMN(romp._romp_install()) +#else +#define A_ROMP_INIT() +#define A_ROMP_DOWNLOAD(x) +#define A_ROMP_DECODE(addr) +#define A_ROMP_INSTALL() +#endif + +#if SYSTEM_MODULE_WDT + +#define A_WDT_INIT() A_CMN(wdt_timer._wdt_init()) +#define A_WDT_ENABLE() A_CMN(wdt_timer._wdt_enable()) +#define A_WDT_DISABLE() A_CMN(wdt_timer._wdt_disable()) +#define A_WDT_SET(t) A_CMN(wdt_timer._wdt_set(t)) +#define A_WDT_TASK() A_CMN(wdt_timer._wdt_task()) +#define A_WDT_LASTBOOT() A_CMN(wdt_timer._wdt_last_boot()) +#define A_WDT_RESET() A_CMN(wdt_timer._wdt_reset()) + +#else +#define A_WDT_INIT() +#define A_WDT_ENABLE() +#define A_WDT_DISABLE() +#define A_WDT_SET(t) +#define A_WDT_TASK() +#define A_WDT_LASTBOOT() +#define A_WDT_RESET() +#endif + + +#if SYSTEM_MODULE_EEPROM +#define A_EEP_INIT() A_CMN(eep._eep_init()) +#define A_EEP_READ(off, len, buf) A_CMN(eep._eep_read(off, len, buf)) +#define A_EEP_WRITE(off, len, buf) A_CMN(eep._eep_write(off, len, buf)) +#define A_EEP_IS_EXIST() A_CMN(eep._eep_is_exist()) +#else +#define A_EEP_INIT() +#define A_EEP_READ(off, len, buf) +#define A_EEP_WRITE(off, len, buf) +#define A_EEP_IS_EXIST() +#endif + + + +struct _A_os_linkage_check; /* OS-dependent */ + +typedef struct _A_cmnos_indirection_table { + int (* hal_linkage_check)(int sz, struct _A_os_linkage_check *); + unsigned int *start_bss; + void (* app_start)(void); + +#if SYSTEM_MODULE_MEM + struct mem_api mem; +#endif + +#if SYSTEM_MODULE_MISC + struct misc_api misc; +#endif + +#if SYSTEM_MODULE_PRINT + struct printf_api printf; +#endif + +#if SYSTEM_MODULE_UART + struct uart_api uart; +#endif + +//#if SYSTEM_MODULE_DBG +// struct dbg_api dbg; +//#endif + +#if SYSTEM_MODULE_PCI + struct pci_api pci; +#endif + +#if SYSTEM_MODULE_GMAC + struct gmac_api gmac; +#endif + +#if SYSTEM_MODULE_USB + struct usb_api usb; +#endif + +#if SYSTEM_MODULE_CLOCK + struct clock_api clock; +#endif + +#if SYSTEM_MODULE_TIMER + struct timer_api timer; +#endif + +#if SYSTEM_MODULE_INTR + struct intr_api intr; +#endif + +#if SYSTEM_MODULE_ALLOCRAM + struct allocram_api allocram; +#endif + +#if SYSTEM_MODULE_ROM_PATCH + struct romp_api romp; +#endif + +#if SYSTEM_MODULE_WDT + struct wdt_api wdt_timer; +#endif + +#if SYSTEM_MODULE_EEPROM + struct eep_api eep; +#endif + + struct string_api string; + struct tasklet_api tasklet; + +} _A_cmnos_indirection_table_t; + +/* Module installation for cmnos modules */ + +#if SYSTEM_MODULE_MEM +extern void cmnos_mem_module_install(struct mem_api *); +#endif + +#if SYSTEM_MODULE_MISC +extern void cmnos_misc_module_install(struct misc_api *); +#endif + +#if SYSTEM_MODULE_PRINT +extern void cmnos_printf_module_install(struct printf_api *); +#endif + +#if SYSTEM_MODULE_UART +extern void cmnos_uart_module_install(struct uart_api *); +#endif + +//#if SYSTEM_MODULE_DBG +//extern void cmnos_dbg_module_install(struct dbg_api *); +//#endif + +#if SYSTEM_MODULE_USB +extern void cmnos_usb_module_install(struct usb_api *); +#endif + +#if SYSTEM_MODULE_INTR +extern void cmnos_intr_module_install(struct intr_api *); +#endif + +#if SYSTEM_MODULE_CLOCK +extern void cmnos_clock_module_install(struct clock_api *); +#endif + +#if SYSTEM_MODULE_TIMER +extern void cmnos_timer_module_install(struct timer_api *); +#endif + +#if SYSTEM_MODULE_ALLOCRAM +extern void cmnos_allocram_module_install(struct allocram_api *); +#endif + +#if SYSTEM_MODULE_ROM_PATCH +extern void cmnos_romp_module_install(struct romp_api *); +#endif + +#if SYSTEM_MODULE_WDT +extern void cmnos_wdt_module_install(struct wdt_api *); +#endif + +#if SYSTEM_MODULE_EEPROM +extern void cmnos_eep_module_install(struct eep_api *); +#endif + +#if SYSTEM_MODULE_PCI +extern void cmnos_pci_module_install(struct pci_api *); +#endif + +extern void cmnos_tasklet_module_install(struct tasklet_api *); + +extern void cmnos_string_module_install(struct string_api *tbl); + +#endif /* __CMNOS_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/cmnos/cmnos_clock.c b/target_firmware/magpie_fw_dev/target/cmnos/cmnos_clock.c new file mode 100755 index 0000000..f466d8d --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/cmnos/cmnos_clock.c @@ -0,0 +1,290 @@ +#include "sys_cfg.h" + +#if SYSTEM_MODULE_CLOCK +#include "athos_api.h" + +LOCAL A_UINT32 cticks = 0; + +#define A_BAND_DEFAULT 0 // not ust now, avoiding compile error/warning, Ryan + +LOCAL int curr_band = A_BAND_DEFAULT; +LOCAL void cmnos_pll_init(void); + +/* We accept frequencies within this deviation from an expected frequency. */ +#define A_REFCLK_DEVIATION 800000 + +#define A_REFCLK_UNKNOWN SYS_CFG_REFCLK_UNKNOWN +#define A_REFCLK_10_MHZ SYS_CFG_REFCLK_10_MHZ +#define A_REFCLK_20_MHZ SYS_CFG_REFCLK_20_MHZ +#define A_REFCLK_40_MHZ SYS_CFG_REFCLK_40_MHZ + +LOCAL const struct cmnos_clock_s { + A_refclk_speed_t refclk_speed; + A_UINT32 ticks_per_sec; + // below are useless so far, ryan + A_UINT32 pll_ctrl_5ghz; + A_UINT32 pll_ctrl_24ghz; + A_UINT32 pll_settling_time; /* 50us */ +} cmnos_clocking_table[] = { + {A_REFCLK_10_MHZ, + //10485760, + 10000000, + 0x0, + 0x0, + 0x0}, + + {A_REFCLK_20_MHZ, + //20971520, + 20000000, + 0x0, + 0x0, + 0x0}, + + {A_REFCLK_40_MHZ, + //41943040, + 40000000, + 0x0, + 0x0, + 0x0}, + + {A_REFCLK_UNKNOWN, + 0, + 0x0, + 0x0, + 0x0}, +}; + + +#define CMNOS_CLOCKING_TABLE_NUM_ENTRIES \ + (sizeof(cmnos_clocking_table)/sizeof(cmnos_clocking_table[0])) + +LOCAL struct cmnos_clock_s *clock_info; + + +LOCAL void cmnos_tick(void); + +/* + * In case we have PLL initialization problems, software can arrange + * (e.g. through BMI) to skip PLL initialization, and other software + * can handle it. + */ +int cmnos_skip_pll_init = 0; +A_UINT32 pll_ctrl_setting_24ghz = 0; +A_UINT32 pll_ctrl_setting_5ghz = 0; + +/* + * Use default hardware values for clock-related registers. + * The defaults can be overridden through BMI, EJTAG, or patches. + * + * CPU clock frequencies depend on what mode we're in (2.4GHz or 5GHz): + * NB: AR6001 has a "reduced power" mode, but we don't use it. + * + * AR6001/AR6002 FPGA CPU clock is always at 40MHz + * + * AR6001 Rev 2.x supports 4 CPU speed selections: + * selector: 0 1 2 3 + * 2.4GHz: 44, 88, 141, refclk + * 5 GHz: 40, 80, 128, refclk + * + * AR6002 supports 7 CPU/SoC speed selections via CORE_CLK: + * CORE_CLK.DIV setting: 6,7 5 4 3 2 1 0 + * divisor: 16 14 12 10 8 6 4 + * 2.4GHz (pll at 352MHz): 22 25.1, 29.3, 35.2, 44, 58.7, 88 + * 5 GHz (pll at 320MHz): 20 22.9, 26.7, 32, 40, 53.3, 80 + */ + +#if defined(DISABLE_SYNC_DURING_PLL_UPDATE_WAR) +A_UINT32 cpu_clock_setting; +#endif + +//A_COMPILE_TIME_ASSERT(verify_host_interest_small_enough, +// (sizeof(struct host_interest_s) <= HOST_INTEREST_MAX_SIZE)) + +//A_COMPILE_TIME_ASSERT(verify_flash_is_present_addr, +// ((A_UINT32)&HOST_INTEREST->hi_flash_is_present) == FLASH_IS_PRESENT_TARGADDR) + + +LOCAL void +cmnos_delay_us(int us) +{ +// A_UINT32 start_time = A_RTC_REG_READ(LF_TIMER_COUNT0_ADDRESS); +// unsigned int num_LF_ticks = (us+29) / 30 + 1; /* ~30.5us per LF tick */ + //A_UINT32 ref_clk = (clock_info->ticks_per_sec)/1000/1000; + A_UINT32 ref_clk = (clock_info->ticks_per_sec) >> 20; + A_UINT32 start_time = NOW(); + unsigned int num_ticks = us*ref_clk; // system_freq == number of ticks per 1us + + while ( (NOW() - start_time) < num_ticks) { + /* busy spin */; + } +} + +/* + * Return the number of milliseconds since startup. + * For this purpose, a "millisecond" is approximated by + * 1/32 of a 32KHz clock. + */ +LOCAL A_UINT32 +cmnos_milliseconds(void) +{ + //unsigned int lowfreq_timer; + + //lowfreq_timer = A_RTC_REG_READ(LF_TIMER_COUNT0_ADDRESS); + //lowfreq_timer = NOW(); + + /* LF0 timer counts at 32KHz, so adjust to approximate Ms with >> 5. */ + //lowfreq_timer = lowfreq_timer; + + /* + * NB: We do not account for wrap, which occurs every 36 + * hours when the 32768Hz low frequency timer wraps the + * 32 bit counter. + */ + cmnos_tick(); + + return cticks; +} + + +/* Expect 40MHz on AR6001 and 26MHz on AR6002 */ +//LOCAL A_refclk_speed_t cmnos_refclk_speed; + +LOCAL A_UINT32 +cmnos_refclk_speed_get(void) +{ + return clock_info->ticks_per_sec; +} + +/* The UART is clocked at the reference clock frequency. */ +LOCAL A_UINT32 +cmnos_uart_frequency(void) +{ +#if 0 +#if defined(FPGA) + return clock_info->ticks_per_sec; +#else + return clock_info->ticks_per_sec; +#endif +#else + /* TBD */ + /* do we need keep a struct to hold the data ?*/ +#endif +} + + +/* + * Adjust any state that needs adjusting when the clock + * speed changes. + */ +LOCAL void +cmnos_sysclk_change(void) +{ + /* OS may override this function */ +} + + +LOCAL void +cmnos_clockregs_init(void) +{ + /* TBD */ + /* we might don't need this init() */ +} + +/* + * Make whatever system-level changes are needed in order to operate + * in the specified wireless band. + * + * For AR6K, we just need to set the PLL appropriately. + */ +LOCAL void +cmnos_wlan_band_set(int which_band) +{ + /* TBD */ + /* we don't have wlan need to config */ +} + +LOCAL void +cmnos_pll_init(void) +{ + /* TBD */ + /* we don't have pll now, */ +} + +LOCAL void +cmnos_clock_init(A_UINT32 ref_clk) +{ +#if 1 + unsigned int i; + + /* Look up the nearest supported frequency. */ + for (i = 0; + i < CMNOS_CLOCKING_TABLE_NUM_ENTRIES-1; + i++) + { + A_UINT32 ticks_per_sec; + + ticks_per_sec = cmnos_clocking_table[i].ticks_per_sec; + if ((ref_clk > ticks_per_sec - A_REFCLK_DEVIATION) && + (ref_clk < ticks_per_sec + A_REFCLK_DEVIATION)) + { + break; + } + } + + clock_info = (struct cmnos_clock_s *)&cmnos_clocking_table[i]; +// HOST_INTEREST->hi_clock_info = (A_UINT32)clock_info; + +#endif +} + +//////////////////////////////////////////////////////////////////////// +// software emulate ticks on millisecond based +LOCAL void +cmnos_tick(void) +{ +#if 0 + + set_ccompare0(xthal_get_ccompare(XTENSA_TIMER_0)+ONE_MSEC); + + cticks++; + +#else + static A_UINT32 last_tick = 0; + A_UINT32 current_tick = NOW(); + A_UINT32 delta_tick; + + // tick is 32 bit register, will overflow soon + if( current_tick < last_tick ) + { + delta_tick = (A_UINT32 )((0xffffffff-last_tick)+current_tick+1)/(1000); + } + else + { + delta_tick = (A_UINT32 ) (current_tick - last_tick)/(1000); + } + + if( delta_tick > 0 ) + last_tick = current_tick; + + cticks += delta_tick; +#endif +} + +//////////////////////////////////////////////////////////////////////// + +void +cmnos_clock_module_install(struct clock_api *tbl) +{ + tbl->_clock_init = cmnos_clock_init; + tbl->_clockregs_init = cmnos_clockregs_init; + tbl->_delay_us = cmnos_delay_us; + tbl->_wlan_band_set = cmnos_wlan_band_set; + tbl->_refclk_speed_get = cmnos_refclk_speed_get; + tbl->_milliseconds = cmnos_milliseconds; + tbl->_uart_frequency = cmnos_uart_frequency; + tbl->_sysclk_change = cmnos_sysclk_change; + + tbl->_clock_tick = cmnos_tick; +} +#endif /* SYSTEM_MODULE_CLOCK */ + diff --git a/target_firmware/magpie_fw_dev/target/cmnos/cmnos_printf.c b/target_firmware/magpie_fw_dev/target/cmnos/cmnos_printf.c new file mode 100755 index 0000000..1f0a55e --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/cmnos/cmnos_printf.c @@ -0,0 +1,322 @@ +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### + +#include "dt_defs.h" +#include "sys_cfg.h" + +#if SYSTEM_MODULE_PRINT + +#include "athos_api.h" + +#define is_digit(c) ((c >= '0') && (c <= '9')) + +#if defined(__GNUC__) && defined(__mips__) +#define va_list __builtin_va_list +#define va_arg __builtin_va_arg +#define va_start __builtin_va_start +#define va_end __builtin_va_end +#define va_copy __builtin_va_copy +#endif + +#if defined(__XCC__) +#include "stdarg.h" +#define va_list __gnuc_va_list +#endif + +void +cmnos_write_char(char c) +{ + if (c == '\n') { + A_PUTC('\r'); + A_PUTC('\n'); + } else if (c == '\r') { + } else { + A_PUTC(c); + } +} + +void (*_putc)(char c) = cmnos_write_char; + +static int _cvt(unsigned long val, char *buf, long radix, char *digits) +{ + char temp[80]; + char *cp = temp; + int length = 0; + + if (val == 0) { + /* Special case */ + *cp++ = '0'; + } else { + while (val) { + *cp++ = digits[val % radix]; + val /= radix; + } + } + while (cp != temp) { + *buf++ = *--cp; + length++; + } + *buf = '\0'; + return (length); +} + + +static int cmnos_vprintf(void (*putc)(char c), const char *fmt, va_list ap) +{ + char buf[sizeof(long)*8]; + char c, sign, *cp=buf; + int left_prec, right_prec, zero_fill, pad, pad_on_right, + i, islong, islonglong; + long val = 0; + int res = 0, length = 0; + + while ((c = *fmt++) != '\0') { + if (c == '%') { + c = *fmt++; + left_prec = right_prec = pad_on_right = islong = islonglong = 0; + if (c == '-') { + c = *fmt++; + pad_on_right++; + } + if (c == '0') { + zero_fill = TRUE; + c = *fmt++; + } else { + zero_fill = FALSE; + } + while (is_digit(c)) { + left_prec = (left_prec * 10) + (c - '0'); + c = *fmt++; + } + if (c == '.') { + c = *fmt++; + zero_fill++; + while (is_digit(c)) { + right_prec = (right_prec * 10) + (c - '0'); + c = *fmt++; + } + } else { + right_prec = left_prec; + } + sign = '\0'; + if (c == 'l') { + // 'long' qualifier + c = *fmt++; + islong = 1; + if (c == 'l') { + // long long qualifier + c = *fmt++; + islonglong = 1; + } + } + // Fetch value [numeric descriptors only] + switch (c) { + case 'p': + islong = 1; + case 'd': + case 'D': + case 'x': + case 'X': + case 'u': + case 'U': + case 'b': + case 'B': + if (islonglong) { + val = va_arg(ap, long); + } else if (islong) { + val = (long)va_arg(ap, long); + } else{ + val = (long)va_arg(ap, int); + } + if ((c == 'd') || (c == 'D')) { + if (val < 0) { + sign = '-'; + val = -val; + } + } else { + // Mask to unsigned, sized quantity + if (islong) { + val &= (1ULL << (sizeof(long) * 8)) - 1; + } else{ + val &= (1ULL << (sizeof(int) * 8)) - 1; + } + } + break; + default: + break; + } + // Process output + switch (c) { + case 'p': // Pointer + (*putc)('0'); + (*putc)('x'); + zero_fill = TRUE; + left_prec = sizeof(unsigned long)*2; + case 'd': + case 'D': + case 'u': + case 'U': + case 'x': + case 'X': + switch (c) { + case 'd': + case 'D': + case 'u': + case 'U': + length = _cvt(val, buf, 10, "0123456789"); + break; + case 'p': + case 'x': + length = _cvt(val, buf, 16, "0123456789abcdef"); + break; + case 'X': + length = _cvt(val, buf, 16, "0123456789ABCDEF"); + break; + } + cp = buf; + break; + case 's': + case 'S': + cp = va_arg(ap, char *); + if (cp == NULL) { + cp = ""; + } + length = 0; + while (cp[length] != '\0') length++; + break; + case 'c': + case 'C': + c = va_arg(ap, int /*char*/); + (*putc)(c); + res++; + continue; + case 'b': + case 'B': + length = left_prec; + if (left_prec == 0) { + if (islonglong) + length = sizeof(long)*8; + else if (islong) + length = sizeof(long)*8; + else + length = sizeof(int)*8; + } + for (i = 0; i < length-1; i++) { + buf[i] = ((val & ((long)1< 0) { + (*putc)(c); + res++; + } + } + if (sign != '\0') { + (*putc)(sign); + res++; + } + while (length-- > 0) { + c = *cp++; + (*putc)(c); + res++; + } + if (pad_on_right) { + while (pad-- > 0) { + (*putc)(' '); + res++; + } + } + } else { + (*putc)(c); + res++; + } + } + return (res); +} + +int cmnos_printf(const char *fmt, ...) +{ + va_list ap; + int ret; + + va_start(ap, fmt); + + //if (A_SERIAL_ENABLED()) { + if (1) { + ret = cmnos_vprintf(_putc, fmt, ap); + } else { + ret = 0; + } + + va_end(ap); + + return (ret); +} + +void +cmnos_printf_init(void) +{ +} + +void cmnos_printf_module_install(struct printf_api *tbl) +{ + tbl->_printf_init = cmnos_printf_init; + tbl->_printf = cmnos_printf; +} + +#endif /* SYSTEM_MODULE_PRINT */ + diff --git a/target_firmware/magpie_fw_dev/target/cmnos/cmnos_sflash.c b/target_firmware/magpie_fw_dev/target/cmnos/cmnos_sflash.c new file mode 100755 index 0000000..8fc81fe --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/cmnos/cmnos_sflash.c @@ -0,0 +1,598 @@ +#include "sys_cfg.h" +#include "athos_api.h" + +#if SYSTEM_MODULE_SFLASH + +#include "reg_defs.h" +#include "sflash_api.h" + +/******************************************* + * Definitions of module internal constant * + *******************************************/ + +/* Definitions of base address and Flash sise -> Project dependent */ +#define ZM_SPI_REGISTER_BASE SPI_REG_BASE_ADDRESS /* 0x0005B000 */ +#define ZM_SPI_FLASH_BASE SPI_FLASH_BASE /* 0x0F000000 */ +#define ZM_SPI_FLASH_MAX_ADDR SPI_FLASH_MAX_ADDR /* 0x0FFFFFFF */ +#define ZM_SPI_FLASH_MAX_SIZE SPI_FLASH_MAX_SIZE /* 0x01000000 */ + +/* + * Base address of Clock and Reset Control Registers is 0x00050000 + * Offset of Clock Control Register is 0x40 + * SPI_SEL (bit 8) : Switch the function of I/O pin 19~22 between GPIO and SPI. + * 0 -> act as GPIO5~8; + * 1 -> act as SPI pins. + */ +#define ZM_SPI_CLK_CTRL_ADDR 0x00050040 +#define ZM_SPI_SPI_SEL_BIT 0x100 + +/* Definitions of Serial Flash constants -> According to standard or vendor dependent */ +#define ZM_SFLASH_PAGE_SIZE 256 + +/* Definitions of OP Code -> According to standard or vendor dependent */ +#define ZM_SFLASH_OP_READ 0x03 /* Read Data Bytes */ +#define ZM_SFLASH_OP_FAST_READ 0x0B /* Read Data Bytes at Higher Speed */ +/* + * For MXIC, sector erase : Command 0x20, size 4K bytes + * block erase : Command 0xD8, size 64K bytes + * chip earse : command 0x60 or 0xC7 + * For Spansion, sector erase : Command 0x20 or 0xD8, size 64K bytes (For 64 KB sector devices, either command is valid and performs the same function.) + * block erase : Command 0xD8, size 256K bytes + * chip earse : command 0x60 or 0xC7, Uniform 64 KB Sector Product (For 64 KB sector devices, either command is valid and performs the same function.) + * 0xC7, Uniform 256 KB Sector Product + */ +#define ZM_SFLASH_OP_SE 0x20 /* Sector Erase */ +#define ZM_SFLASH_OP_BE 0xD8 /* Block Erase */ +#define ZM_SFLASH_OP_CE 0xC7 /* Chip Erase */ +#define ZM_SFLASH_OP_PP 0x02 /* Page Program */ +#define ZM_SFLASH_OP_RDSR 0x05 /* Read from Status Register */ +#define ZM_SFLASH_OP_WRSR 0x01 /* Write to Status Register */ +#define ZM_SFLASH_OP_WREN 0x06 /* Write Enable */ +#define ZM_SFLASH_OP_WRDI 0x04 /* Write Disable */ +#define ZM_SFLASH_OP_RDID 0x9F /* Read Identification */ +#define ZM_SFLASH_OP_DP 0xB9 /* Deep Power Down */ +#define ZM_SFLASH_OP_RES 0xAB /* Release from Deep Power Down, Release from Deep Power Down and Read Electronic Signature */ + +/* Definitions of Status Register -> According to standard or vendor dependent */ +/* Write in progress bit + * 1 = Device Busy. A Write Status Register, program, or erase operation is in progress + * 0 = Ready. Device is in standby mode and can accept commands. + */ +#define ZM_SFLASH_STATUS_REG_WIP (1<<0) +/* Write enable latch bit + * 1 = Device accepts Write Status Register, program, or erase commands + * 0 = Ignores Write Status Register, program, or erase commands + */ +#define ZM_SFLASH_STATUS_REG_WEL (1<<1) +/* Status register write disable bit + * 1 = Protects when WP#/ACC is low + * 0 = No protection, even when WP#/ACC is low + */ +#define ZM_SFLASH_STATUS_REG_SRWD (1<<7) + +/* Definitions of SPI Flash Controller -> SPI Flash Controller dependent */ +/* SPI Flash Controller used in K2 project is part of Falcon's "Driver Support Logic" (DSL) block */ +/* + * Offset Register + * ====== ========================================================== + * 0x0000 SPI control/status register (SPI_CS) + * 0x0004 SPI address/opcode register (SPI_AO) + * 0x0008 SPI data register (SPI_D) + */ + +/* + * SPI control/status register (SPI_CS) + * Access: R/W + * Cold reset: (See field descriptions) + * Warm reset: (Same as cold reset) + * Notes: + * + * 3:0 - Transmit byte count. Determines the number of bytes + * transmitted from Falcon to the SPI device. Values of 1-8 are + * valid; other values are illegal. See the 'Notes' section below + * for details on how to use this field. Resets to an undefined + * value. + * 7:4 - Receive byte count. Determines the number of bytes received + * from the SPI device into Falcon. Values of 0-8 are valid; + * other values are illegal. See the 'Notes' section below for + * details on how to use this field. Resets to an undefined + * value. + * 8 - SPI transaction start. Only writes to this field are + * meaningful; reads always return 0. Resets to 0x0. For writes: + * * A write of '1' starts the SPI transaction defined by the + * transmit byte count, receive byte count, SPI_AO, and SPI_D + * registers. + * * A write of '0' has no effect + * 9 - SPI chip select 1 enable. Resets to 0x0. See bug 12540. + * 0 - SP0 is enabled and SP1 is forced inactive. + * 1 - SP1 is enabled and SP0 is forced inactive. + * 15:10 - Reserved + * 16 - Transaction busy indication. Read-only; writes to this bit are + * ignored. Resets to 0x0. + * 0 - No SPI transaction is ongoing. Software may start a new + * SPI transaction by writing to the 'SPI transaction start' + * bit within this register. + * 1 - An SPI transaction presently is underway. Software must + * not try to start a new SPI transaction, nor may software + * alter the value of any field of the SPI_CS, SPI_AO, or + * SPI_D registers. + * 18:17 - Automatically-determined SPI address size. Read-only; writes + * to this bit are ignored. Resets to an undefined value, but + * then is updated after the autosizing process completes. + * 0 - SPI address size was determined to be 16 bits + * 1 - SPI address size was determined to be 24 bits + * 2 - Reserved + * 3 - Automatic SPI address size determination failed. Typical + * causes of this result: + * * The SPI device is missing + * * The SPI device is unprogrammed + * * The SPI device is programmed with an incorrect + * SPI_MAGIC value + * 20:19 - SPI autosize override. Resets to 0x0. + * 0 - Use automatically-determined SPI address size (see bits + * [18:17] of this register) + * 1 - Force SPI address size to 16 bits + * 2 - Force SPI address size to 24 bits + * 3 - Reserved + * 31:21 - Reserved + */ + +#define SPI_CS_ADDRESS MAGPIE_REG_SPI_CS_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000000) +/* 3:0 - Transmit byte count, values of 1-8 are valid */ +#define SPI_CS_TXBCNT_MSB 3 +#define SPI_CS_TXBCNT_LSB 0 +#define SPI_CS_TXBCNT_MASK 0x0000000f +#define SPI_CS_TXBCNT_GET(x) (((x) & SPI_CS_TXBCNT_MASK) >> SPI_CS_TXBCNT_LSB) +#define SPI_CS_TXBCNT_SET(x) (((0x0 | (x)) << SPI_CS_TXBCNT_LSB) & SPI_CS_TXBCNT_MASK) + +/* 7:4 - Receive byte count, values of 1-8 are valid */ +#define SPI_CS_RXBCNT_MSB 7 +#define SPI_CS_RXBCNT_LSB 4 +#define SPI_CS_RXBCNT_MASK 0x000000f0 +#define SPI_CS_RXBCNT_GET(x) (((x) & SPI_CS_RXBCNT_MASK) >> SPI_CS_RXBCNT_LSB) +#define SPI_CS_RXBCNT_SET(x) (((0x0 | (x)) << SPI_CS_RXBCNT_LSB) & SPI_CS_RXBCNT_MASK) + +/* 8 - SPI transaction start */ +#define SPI_CS_XCNSTART_MSB 8 +#define SPI_CS_XCNSTART_LSB 8 +#define SPI_CS_XCNSTART_MASK 0x00000100 +#define SPI_CS_XCNSTART_GET(x) 0x0 +#define SPI_CS_XCNSTART_SET(x) (((0x0 | (x)) << SPI_CS_XCNSTART_LSB) & SPI_CS_XCNSTART_MASK) +#define SPI_CS_XCNSTART_RESET 0x0 + +/* 9 - SPI chip select */ +#define SPI_CS_CS_MSB 9 +#define SPI_CS_CS_LSB 9 +#define SPI_CS_CS_MASK 0x00000200 +#define SPI_CS_CS_GET(x) (((x) & SPI_CS_CS_MASK) >> SPI_CS_CS_LSB) +#define SPI_CS_CS_SET(x) (((0x0 | (x)) << SPI_CS_CS_LSB) & SPI_CS_CS_MASK) +#define SPI_CS_CS_RESET 0x0 + +/* 16 - Transaction busy indication */ +#define SPI_CS_BUSY_MSB 16 +#define SPI_CS_BUSY_LSB 16 +#define SPI_CS_BUSY_MASK 0x00010000 +#define SPI_CS_BUSY_GET(x) (((x) & SPI_CS_BUSY_MASK) >> SPI_CS_BUSY_LSB) +#define SPI_CS_BUSY_SET(x) (((0x0 | (x)) << SPI_CS_BUSY_LSB) & SPI_CS_BUSY_MASK) +#define SPI_CS_BUSY_RESET 0x0 + +/* 18:17 - Automatically-determined SPI address size */ +#define SPI_CS_AUTOSIZ_MSB 18 +#define SPI_CS_AUTOSIZ_LSB 17 +#define SPI_CS_AUTOSIZ_MASK 0x00060000 +#define SPI_CS_AUTOSIZ_GET(x) (((x) & SPI_CS_AUTOSIZ_MASK) >> SPI_CS_AUTOSIZ_LSB) +#define SPI_CS_AUTOSIZ_SET(x) (((0x0 | (x)) << SPI_CS_AUTOSIZ_LSB) & SPI_CS_AUTOSIZ_MASK) + +/* 20:19 - SPI autosize override */ +#define SPI_CS_AUTOSIZ_OVR_MSB 20 +#define SPI_CS_AUTOSIZ_OVR_LSB 19 +#define SPI_CS_AUTOSIZ_OVR_MASK 0x00180000 +#define SPI_CS_AUTOSIZ_OVR_GET(x) (((x) & SPI_CS_AUTOSIZ_OVR_MASK) >> SPI_CS_AUTOSIZ_OVR_LSB) +#define SPI_CS_AUTOSIZ_OVR_SET(x) (((0x0 | (x)) << SPI_CS_AUTOSIZ_OVR_LSB) & SPI_CS_AUTOSIZ_OVR_MASK) +#define SPI_CS_AUTOSIZ_OVR_RESET 0x0 + +#define SPI_CS_RESET (0x0 | \ + SPI_CS_AUTOSIZ_OVR_SET(SPI_CS_AUTOSIZ_OVR_RESET) | \ + SPI_CS_BUSY_SET(SPI_CS_BUSY_RESET) | \ + SPI_CS_CS_SET(SPI_CS_CS_RESET) | \ + SPI_CS_XCNSTART_SET(SPI_CS_XCNSTART_RESET)) + +/* + * SPI address/opcode register (SPI_AO) + * Access: R/W + * Cold reset: (See field descriptions) + * Warm reset: (Same as cold reset) + * Notes: + * + * 7:0 - SPI opcode. Usually this field specifies the 8-bit opcode + * (aka "instruction") to transmit to the SPI device as the first + * part of an SPI transaction. See the 'Notes' section below for + * more details. Resets to an undefined value. + * 31:8 - Address. Usually this field specifies the 24-bit address to + * transmit to the SPI device. See the 'Notes' section below for + * more details. Resets to an undefined value. + */ + +#define SPI_AO_ADDRESS MAGPIE_REG_SPI_AO_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000004) +/* 7:0 - SPI opcode */ +#define SPI_AO_OPC_MSB 7 +#define SPI_AO_OPC_LSB 0 +#define SPI_AO_OPC_MASK 0x000000ff +#define SPI_AO_OPC_GET(x) (((x) & SPI_AO_OPC_MASK) >> SPI_AO_OPC_LSB) +#define SPI_AO_OPC_SET(x) (((0x0 | (x)) << SPI_AO_OPC_LSB) & SPI_AO_OPC_MASK) +/* 31:8 - Address */ +#define SPI_AO_ADDR_MSB 31 +#define SPI_AO_ADDR_LSB 8 +#define SPI_AO_ADDR_MASK 0xffffff00 +#define SPI_AO_ADDR_GET(x) (((x) & SPI_AO_ADDR_MASK) >> SPI_AO_ADDR_LSB) +#define SPI_AO_ADDR_SET(x) (((0x0 | (x)) << SPI_AO_ADDR_LSB)& SPI_AO_ADDR_MASK) + +/* + * SPI data register (SPI_D) + * Access: R/W + * Cold reset: (See field descriptions) + * Warm reset: (Same as cold reset) + * Notes: + * + * 31:0 - SPI data. Usually this register specifies a series of up to + * four data bytes to transmit to or receive from the SPI device. + * See the 'Notes' section below for more details. Resets to an + * undefined value. + */ + +#define SPI_D_ADDRESS MAGPIE_REG_SPI_D_ADDR //(ZM_SPI_REGISTER_BASE + 0x00000008) +/* 31:0 - SPI data */ +#define SPI_D_DATA_MSB 31 +#define SPI_D_DATA_LSB 0 +#define SPI_D_DATA_MASK 0xffffffff +#define SPI_D_DATA_GET(x) (((x) & SPI_D_DATA_MASK) >> SPI_D_DATA_LSB) +#define SPI_D_DATA_SET(x) (((0x0 | (x)) << SPI_D_DATA_LSB) & SPI_D_DATA_MASK) + +/* + * SPI clock division register (SPI_CLKDIV) + * Access: R/W + * Cold reset: (See field descriptions) + * Warm reset: (Same as cold reset) + * Notes: + * + * 17:16 - 0b00(fastest), 0b01, 0b10, 0b11(slowest) + */ +#define SPI_CLKDIV_ADDRESS MAGPIE_REG_SPI_CLKDIV_ADDR //SPI_BASE_ADDRESS + 0x0000001c +#define SPI_CLKDIV_MSB 17 +#define SPI_CLKDIV_LSB 16 +#define SPI_CLKDIV_MASK 0x00030000 +#define SPI_CLKDIV_GET(x) (((x) & SPI_CLKDIV_MASK) >> SPI_CLKDIV_LSB) +#define SPI_CLKDIV_SET(x) (((0x0 | (x)) << SPI_CLKDIV_LSB) & SPI_CLKDIV_MASK) // read-then-write +#define SPI_CLKDIV_RESET 0x3 + +/* + * Notes + * ----- + * * Background + * An SPI transaction consists of three phases: an opcode transmit + * phase (always a single byte), followed by an optional address + * transmit phase of 0-3 bytes, followed by an optional data transmit + * or receive phase of 0-4 bytes. + * + * Combined, then, an SPI transaction consists of a 1- to 8-byte + * transmit phase from Falcon to the SPI device, followed by a 0- to + * 8-byte receive phase from the SPI device into Falcon. + * + * The 'transmit byte count' field in the SPI_CS register controls the + * size (number of bytes) of the transmit phase. The source of each + * of the bytes transmitted is fixed: + * + * Byte Source + * ---- ----------------------------------------------------------- + * 0 SPI_AO[7:0] (the 'SPI opcode' field) + * 1 SPI_AO[31:24] (the high byte of the 'SPI address' field) + * 2 SPI_AO[23:16] (the middle byte of the 'SPI address' field) + * 3 SPI_AO[15:8] (the low byte of the 'SPI address' field) + * 4 SPI_D[7:0] (the low byte of the 'SPI data' register) + * 5 SPI_D[15:8] (the next byte of the 'SPI data' register) + * 6 SPI_D[23:16] (the next byte of the 'SPI data' register) + * 7 SPI_D[31:24] (the high byte of the 'SPI data' register) + * + * + * The 'receive byte count' field in the SPI_CS register controls the + * size (number of bytes) of the receive phase. The destination of + * each of the bytes received is fixed: + * + * Byte Destination + * ---- ----------------------------------------------------------- + * 0 SPI_D[7:0] (the low byte of the 'SPI data' register) + * 1 SPI_D[15:8] (the next byte of the 'SPI data' register) + * 2 SPI_D[23:16] (the next byte of the 'SPI data' register) + * 3 SPI_D[31:24] (the high byte of the 'SPI data' register) + * 4 SPI_AO[7:0] (the 'SPI opcode' field) + * 5 SPI_AO[15:8] (the low byte of the 'SPI address' field) + * 6 SPI_AO[23:16] (the middle byte of the 'SPI address' field) + * 7 SPI_AO[31:24] (the high byte of the 'SPI address' field) + * + * + * * To perform an SPI transaction: + * Write the appropriate values into the SPI_AO and SPI_D registers + * * Write the appropriate values into the 'transmit byte count' and + * 'received byte count' fields of the SPI_CS register. + * * Write a '1' to the 'SPI transaction start' bit of the SPI_CS + * register (this step can be combined with the one above if desired + * so that only a single SPI_CS write is needed). + * * Poll the 'transaction busy indication' bit in the SPI_CS register + * until it is clear, indicating that the SPI transaction has + * completed. + * * If the transaction included a receive phase, then retrieve the + * received data by reading the appropriate bytes from the SPI_D and + * SPI_AO registers. + * + * + * * Examples: + * * A "write disable" (WRDI) transaction: + * * Opcode (SPI_AO[7:0]): 0x04 (for STMicro; varies by + * manufacturer and device type) + * * Address (SPI_AO[31:8]): don't care (not used) + * * Data (SPI_D[31:0]): don't care (not used) + * * Transmission byte count: 1 + * * Receive byte count: 0 + * + * * A "read status register" (RDSR) transaction: + * * Opcode (SPI_AO[7:0]): 0x05 (for STMicro; varies by + * manufacturer and device type) + * * Address (SPI_AO[31:8]): don't care (not used) + * * Data (SPI_D[31:0]): don't care (not used) + * * Transmission byte count: 1 + * * Receive byte count: 1 + * * Read SPI_D[7:0] to retrieve status register value + * + * * A "page program" (PP) transaction to write a value of 0xdeadbeef + * to address 0x123456: + * * Opcode (SPI_AO[7:0]): 0x02 (for STMicro; varies by + * manufacturer and device type) + * * Address (SPI_AO[31:8]): 0x123456 + * * Data (SPI_D[31:0]): 0xdeadbeef + * * Transmission byte count: 8 + * * Receive byte count: 0 + */ + +/* Wait till Transaction busy indication bit in SPI control/status register of Falcon's SPI Flash Controller is clear */ +LOCAL void +_cmnos_sflash_WaitTillTransactionOver(void) +{ + A_UINT32 poldata; + A_UINT32 flg; + + do + { + poldata = HAL_WORD_REG_READ(SPI_CS_ADDRESS); + + flg = SPI_CS_BUSY_GET(poldata); + } while (flg != 0x0); +} + +/* Wait till Write In Progress bit in Status Register of Serial Flash is clear */ +LOCAL void +_cmnos_sflash_WaitTillNotWriteInProcess(void) +{ + A_UINT32 poldata; + A_UINT32 flg; + + do + { + _cmnos_sflash_WaitTillTransactionOver(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1) ); + + _cmnos_sflash_WaitTillTransactionOver(); + + poldata = HAL_WORD_REG_READ(SPI_D_ADDRESS); + flg = poldata & ZM_SFLASH_STATUS_REG_WIP; + + } while (flg != 0x0); +} + +/************************************************************************/ +/* Function to Send WREN(Write Enable) Operation */ +/************************************************************************/ +LOCAL void +_cmnos_sflash_WriteEnable() +{ + _cmnos_sflash_WaitTillNotWriteInProcess(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_WREN) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) ); + + _cmnos_sflash_WaitTillTransactionOver(); +} + +/************************************************************************/ +/* Function to Initialize SPI Flash Controller */ +/************************************************************************/ +LOCAL void +cmnos_sflash_init(void) +{ + /* Switch the function of I/O pin 19~22 to act as SPI pins */ + HAL_WORD_REG_WRITE( MAGPIE_REG_CLOCK_CTRL_ADDR, HAL_WORD_REG_READ(MAGPIE_REG_CLOCK_CTRL_ADDR)|BIT8 ); + + /* "Autosize-determination of the address size of serial flash" is obsolete according to Brian Yang's mail : + * The designers reached an conclusion that the spi master (the apb_spi interface control) will be + * modified as ¡§presuming the attached flash model to be 24-bit addressing¡¨, i.e., no more + * auto-size detection! + * Hence you are free to force the 24-bit addressing in the *.c test code. + */ + + /* Force SPI address size to 24 bits */ + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_AUTOSIZ_OVR_SET(2) ); +} + +/************************************************************************/ +/* Function to Send Sector/Block/Chip Erase Operation */ +/************************************************************************/ +LOCAL void +cmnos_sflash_erase(A_UINT32 erase_type, A_UINT32 addr) +{ + A_UINT32 erase_opcode; + A_UINT32 tx_len; + + if (erase_type == ZM_SFLASH_SECTOR_ERASE) + { + erase_opcode = ZM_SFLASH_OP_SE; + tx_len = 4; + } + else if (erase_type == ZM_SFLASH_BLOCK_ERASE) + { + erase_opcode = ZM_SFLASH_OP_BE; + tx_len = 4; + } + else + { + erase_opcode = ZM_SFLASH_OP_CE; + tx_len = 1; + } + + _cmnos_sflash_WriteEnable(); + _cmnos_sflash_WaitTillNotWriteInProcess(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(erase_opcode) | SPI_AO_ADDR_SET(addr) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(tx_len) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) ); + +#if 0 + /* Do not wait(let it be completed in background) */ + _cmnos_sflash_WaitTillTransactionOver(); +#else + /* Wait till completion */ + _cmnos_sflash_WaitTillNotWriteInProcess(); /* Chip Erase takes 80 - 200 seconds to complete */ +#endif +} + +/************************************************************************/ +/* Function to Perform Page Program Operation */ +/* Notes: */ +/* Serial Flash has the following characteristics : */ +/* 1) In datasheet, 1-256 data bytes can be sent at a time, but */ +/* Falcon supports only 4 bytes at a time. */ +/* 2) If the eight least significant address bits(A7-A0) are not */ +/* all 0, all transmitted data which goes beyond the end of the */ +/* current page are programmed from the start address in the */ +/* same page. */ +/* This API hides the complexity of the above. */ +/************************************************************************/ +LOCAL void +cmnos_sflash_program(A_UINT32 addr, A_UINT32 len, A_UINT8 *buf) +{ + A_UINT32 s_addr, e_addr; + A_UINT32 reminder, write_byte; + A_UINT32 data_offset; + A_UINT32 next_page_base; + A_UINT32 t_word_data; + + e_addr = addr + len; + for (s_addr = addr; s_addr < e_addr; ) + { + next_page_base = (s_addr - s_addr%ZM_SFLASH_PAGE_SIZE) + ZM_SFLASH_PAGE_SIZE; + + reminder = e_addr - s_addr; + + write_byte = next_page_base - s_addr; + + if (write_byte >= 4) + write_byte = 4; + + if (write_byte > reminder) + write_byte = reminder; + + data_offset = s_addr - addr; + + A_MEMCPY(&t_word_data, buf + data_offset, write_byte); + + _cmnos_sflash_WriteEnable(); + _cmnos_sflash_WaitTillNotWriteInProcess(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_PP) | SPI_AO_ADDR_SET(s_addr) ); + HAL_WORD_REG_WRITE( SPI_D_ADDRESS, SPI_D_DATA_SET(t_word_data) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(4 + write_byte) | SPI_CS_RXBCNT_SET(0) | SPI_CS_XCNSTART_SET(1) ); + + _cmnos_sflash_WaitTillTransactionOver(); + + s_addr += write_byte; + } +} + +/************************************************************************/ +/* Function to Send Read/Fast Read Data Operation */ +/************************************************************************/ +LOCAL void +cmnos_sflash_read(A_UINT32 fast, A_UINT32 addr, A_UINT32 len, A_UINT8 *buf) +{ + A_UINT32 read_opcode; + A_UINT32 i; + A_UINT32 read_cnt, remainder; + A_UINT32 write_byte, read_byte; + + if (fast) + { + read_opcode = ZM_SFLASH_OP_FAST_READ; + write_byte = 5; + } + else + { + read_opcode = ZM_SFLASH_OP_READ; + write_byte = 4; + } + + read_cnt = len/4; + remainder = len%4; + if (remainder) + read_cnt++; + + read_byte = 4; + for (i = 0; i < read_cnt; i ++) + { + if (i == read_cnt-1 && remainder) + read_byte = remainder; + + _cmnos_sflash_WaitTillNotWriteInProcess(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(read_opcode) | SPI_AO_ADDR_SET(addr + i*4) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(write_byte) | SPI_CS_RXBCNT_SET(read_byte) | SPI_CS_XCNSTART_SET(1) ); + + _cmnos_sflash_WaitTillTransactionOver(); + + A_MEMCPY(buf + i*4, (A_UINT8 *)(SPI_D_ADDRESS), read_byte); + } +} + +/************************************************************************/ +/* Function to Read Flash Status Register */ +/************************************************************************/ +LOCAL A_UINT32 +cmnos_sflash_rdsr(void) +{ + A_UINT32 word_data; + + _cmnos_sflash_WaitTillTransactionOver(); + + HAL_WORD_REG_WRITE( SPI_AO_ADDRESS, SPI_AO_OPC_SET(ZM_SFLASH_OP_RDSR) ); + HAL_WORD_REG_WRITE( SPI_CS_ADDRESS, SPI_CS_TXBCNT_SET(1) | SPI_CS_RXBCNT_SET(1) | SPI_CS_XCNSTART_SET(1) ); + + _cmnos_sflash_WaitTillTransactionOver(); + + word_data = HAL_WORD_REG_READ(SPI_D_ADDRESS) & 0x000000FF; + + return word_data; +} + +void +cmnos_sflash_module_install(struct sflash_api *tbl) +{ + /* Indispensable functions */ + tbl->_sflash_init = cmnos_sflash_init; + tbl->_sflash_erase = cmnos_sflash_erase; + tbl->_sflash_program = cmnos_sflash_program; + tbl->_sflash_read = cmnos_sflash_read; + + /* Dispensable functions */ + tbl->_sflash_rdsr = cmnos_sflash_rdsr; +} + +#endif /* SYSTEM_MODULE_SFLASH */ + diff --git a/target_firmware/magpie_fw_dev/target/cmnos/dbg_api.c b/target_firmware/magpie_fw_dev/target/cmnos/dbg_api.c new file mode 100755 index 0000000..0662a82 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/cmnos/dbg_api.c @@ -0,0 +1,1159 @@ +#include "sys_cfg.h" +#include "athos_api.h" + +#if defined(PROJECT_K2) +#if SYSTEM_MODULE_SFLASH +#include "sflash_api.h" +#endif +#endif /* #if defined(PROJECT_K2) */ + +#if defined(SYSTEM_MODULE_DBG) + +/* Function prototypes */ +int db_help_cmd(char *, char*, char*, char*); +int db_ldr_cmd(char*, char*, char*, char*); +int db_str_cmd(char*, char*, char*, char*); +int db_dump_memory(char* cmd, char* param1, char* param2, char* param3); +int db_info_cmd(char*, char*, char*, char*); +int db_cmd_dbg(char*, char*, char*, char*); +int db_usb_cmd(char*, char*, char*, char*); +int db_intr_cmd(char*, char*, char*, char*); +int db_patch_cmd(char*, char*, char*, char*); + +int db_cmd_memtest(char* cmd, char* param1, char* param2, char* param3); +int db_cmd_dmips(char* cmd, char* param1, char* param2, char* param3); +int db_cmd_starthtc(char* cmd, char* param1, char* param2, char* param3); + +int db_eeprom_cmd(char* cmd, char* param1, char* param2, char* param3); +int db_wdt_cmd(char* cmd, char* param1, char* param2, char* param3); + +#if defined(PROJECT_K2) +#if SYSTEM_MODULE_SFLASH +int db_cmd_sferase(char* cmd, char* param1, char* param2, char* param3); +int db_cmd_sfpg(char* cmd, char* param1, char* param2, char* param3); +int db_cmd_sfru(char* cmd, char* param1, char* param2, char* param3); +int db_cmd_sfrm(char* cmd, char* param1, char* param2, char* param3); +int db_cmd_sfrdsr(char* cmd, char* param1, char* param2, char* param3); +#endif +#endif /* #if defined(PROJECT_K2) */ +int db_cmd_memcmp(char* cmd, char* param1, char* param2, char* param3); +int db_cmd_memdump(char* cmd, char* param1, char* param2, char* param3); + +int db_clock_cmd(char* cmd, char* param1, char* param2, char* param3); + +uint16_t db_get_cmd_line(uint8_t ch, char *cmd_line, uint16_t* i); +int db_formalize_command(char*, char*); +int db_ascii_to_hex(char*, unsigned long*); +int db_hex_to_ascii(unsigned long, char*); +void zfDebugTask(void); + +int db_info_intr(char* cmd, char* param1, char* param2, char* param3); + +extern u32_t this_is_global_variables; + +/* Console debug command table */ +const struct DB_COMMAND_STRUCT command_table[] = +{ + {"HELP", ", List all debug commands", db_help_cmd}, + {"?", ", Equal to HELP comamnd", db_help_cmd}, + + /* Basic load/store/dump command */ + {"LDR", ", Load word", db_ldr_cmd}, + {"LDRH", ", Load half word", db_ldr_cmd}, + {"LDRB", ", Load byte", db_ldr_cmd}, + {"STR", " , Store word", db_str_cmd}, + {"STRH", " , Store half word", db_str_cmd}, + {"STRB", " , Store byte", db_str_cmd}, + {"DUMP", ", Dump memory", db_dump_memory}, + {"INFO", ", Print debug information", db_info_cmd}, + {"USB", ", usb releated command", db_usb_cmd}, + {"INTR", ", intr releated command", db_intr_cmd}, + {"PATCH", ", patch function releated command", db_patch_cmd}, + {"DBG", ", mute all print msg", db_cmd_dbg}, + {"CLOCK", ", change the clock...", db_clock_cmd}, + {"MEMTEST", " test memory", db_cmd_memtest}, + {"HTCR", "Issue HTC ready to host", db_cmd_starthtc}, + {"EEP", ", eeprom r/w debug command", db_eeprom_cmd}, + {"WDT", ", wdt debug command", db_wdt_cmd}, +#if defined(PROJECT_K2) +#if SYSTEM_MODULE_SFLASH + {"SFE", ", S/B/C, SPI Flash chip erase", db_cmd_sferase}, + {"SFPG", " , SPI Flash program", db_cmd_sfpg}, + {"SFRU", "f/r , SPI Flash fast read/read to UART", db_cmd_sfru}, + {"SFRM", "f/r , SPI Flash fast read/read to Memory 0x520000", db_cmd_sfrm}, + {"SFRDSR", ", SPI Flash status register read", db_cmd_sfrdsr}, +#endif +#endif /* #if defined(PROJECT_K2) */ + {"MEMCMP", " , memory comparison", db_cmd_memcmp}, + {"MEMDMP", " , memory dump", db_cmd_memdump}, + {"", "", 0} + /* {Command, Help description, function} */ +}; + +char cmd_buffer[COMMAND_BUFFER_SIZE][DB_MAX_COMMAND_LENGTH]; /* Backup previous command */ +int cmd_buf_ptr; +int cmd_buf_full; +char raw_cmd[DB_MAX_COMMAND_LENGTH]; +char cmd_str[DB_MAX_COMMAND_LENGTH*4]; +int cmd_not_found; +uint16_t gvLen; +int pressed_time; + +////////////////////////////////////////////////// +#define MAX_REG_NUM 16 + +typedef struct reg_elem { + unsigned char valid; + unsigned char mode; // byte, half-word word + unsigned long reg_addr; +} t_reg_elem; + +t_reg_elem reg_buffer[MAX_REG_NUM]; + +////////////////////////////////////////////////// + +void zfDebugInit(void) +{ + uint8_t ch; + + /* Purge Rx FIFO */ + while ((zm_get_char(&ch)) != 0) + { + } + + cmd_buf_ptr = 0; + cmd_buf_full = FALSE; + gvLen = 0; + pressed_time = 0; +} + +void zfDebugTask(void) +{ + int i; + uint8_t ch; + + if ((zm_get_char(&ch)) == 0) + { + return; + } + + if (db_get_cmd_line(ch, raw_cmd, &gvLen) == 0) + { + return; + } + + if (db_formalize_command(raw_cmd, cmd_str)) + { + gvLen = 0; + i = 0; + + cmd_not_found = TRUE; + while(command_table[i].cmd_func) + { + if (!strcmp(command_table[i].cmd_str, cmd_str)) + { + cmd_not_found = FALSE; + command_table[i].cmd_func(cmd_str, + cmd_str+DB_MAX_COMMAND_LENGTH, + cmd_str+DB_MAX_COMMAND_LENGTH*2, + cmd_str+DB_MAX_COMMAND_LENGTH*3); + break; + } + i++; + } + if (cmd_not_found) + { + zm_uart_send("Error, HELP for command list.\n\r", 31); + } + + } + + zm_uart_send(">", 1); + return; +} + +uint16_t db_get_cmd_line(uint8_t ch, char *cmd_line, uint16_t* i) +{ + int cmd_buf_loc; + + switch (ch) + { + case '\\' : /* Last command */ + pressed_time++; + if (pressed_time >= COMMAND_BUFFER_SIZE) + { + pressed_time--; + } + cmd_buf_loc = cmd_buf_ptr - pressed_time; + if (cmd_buf_loc < 0) + { + if (cmd_buf_full == TRUE) + { + cmd_buf_loc += COMMAND_BUFFER_SIZE; + } + else + { + cmd_buf_loc = 0; + } + } + + if(strlen(cmd_buffer[cmd_buf_loc]) != 0) + { + strcpy(cmd_line, cmd_buffer[cmd_buf_loc]); + *i = strlen(cmd_buffer[cmd_buf_loc]); + zm_uart_send("\r>", 2); + zm_uart_send(cmd_line, *i); + } + break; + case 13 : /* Return */ + pressed_time = 0; + cmd_line[*i] = 0; + zm_uart_send("\n\r", 2); + if (*i != 0) + { + //Filter duplicated string in command history + if (strcmp(cmd_buffer[(cmd_buf_ptr==0)?(COMMAND_BUFFER_SIZE-1):(cmd_buf_ptr-1)], cmd_line) != 0) + { + strcpy(cmd_buffer[cmd_buf_ptr++], cmd_line); + } + } + if (cmd_buf_ptr >= COMMAND_BUFFER_SIZE) + { + cmd_buf_ptr = 0; + cmd_buf_full = TRUE; + } + return 1; + case '\b' : /* Backspace */ + pressed_time = 0; + if (*i > 0) + { + *i = *i-1; + zm_uart_send("\b \b", 3); + } + break; + case 0 : //None + break; + default : + if ((ch >= ' ') && (ch <= '~')) + { + pressed_time = 0; + if (*i < DB_MAX_COMMAND_LENGTH-2) + { + if ((ch >= 0x11) && (ch <= 0x7e)) + { + //if ((buf <= 'z') && (buf >= 'a')) + //{ + // buf -= 'a' - 'A'; + //} + cmd_line[*i] = ch; + *i = *i + 1; + zm_uart_send(&ch, 1); + } + } + } + else + { + ch = 7; /* Beep */ + zm_uart_send(&ch, 1); + } + break; + } /* end of switch */ + + return 0; + +} + +int db_formalize_command(char* raw_str, char* cmd_str) +{ + int i = 0; + int j; + int k; + + + for (k=0; k<4; k++) + { + /* Remove preceeding spaces */ + while (raw_str[i++] == ' '){} + i--; + + /* Copy command string */ + j = 0; + while(raw_str[i] && (raw_str[i] != ' ')) + { + if (k == 0) + { + if ((raw_str[i] <= 'z') && (raw_str[i] >= 'a')) + { + raw_str[i] -= 'a' - 'A'; + } + cmd_str[k*DB_MAX_COMMAND_LENGTH + j++] = raw_str[i++]; + } + else + { + cmd_str[k*DB_MAX_COMMAND_LENGTH + j++] = raw_str[i++]; + } + } + cmd_str[k*DB_MAX_COMMAND_LENGTH + j] = 0; + } + return (int)strlen(cmd_str); +} + +int db_ascii_to_hex(char* num_str, unsigned long* hex_num) +{ + int i = 0; + + *hex_num = 0; + while (num_str[i]) + { + if ((num_str[i] >= '0') && (num_str[i] <= '9')) + { + *hex_num <<= 4; + *hex_num += (num_str[i] - '0'); + } + else if ((num_str[i] >= 'A') && (num_str[i] <= 'F')) + { + *hex_num <<= 4; + *hex_num += (num_str[i] - 'A' + 10); + } + else if ((num_str[i] >= 'a') && (num_str[i] <= 'f')) + { + *hex_num <<= 4; + *hex_num += (num_str[i] - 'a' + 10); + } + else + { + return -1; + } + i++; + } + return 0; +} + +int db_ascii_to_int(char* num_str, unsigned long* int_num) +{ + int i = 0; + + *int_num = 0; + while (num_str[i]) + { + if ((num_str[i] >= '0') && (num_str[i] <= '9')) + { + *int_num *= 10; + *int_num += (num_str[i] - '0'); + } + else + { + return -1; + } + i++; + } + return 0; +} + +int db_hex_to_ascii(unsigned long hex_num, char* num_str) +{ + int i; + unsigned long four_bits; + + for (i=7; i>=0; i--) + { + four_bits = (hex_num >> i*4) & 0xf; + if (four_bits < 10) + { + num_str[7-i] = four_bits + '0'; + } + else + { + num_str[7-i] = four_bits - 10 + 'A'; + } + } + num_str[8] = 0; + return 0; +} + +int db_help_cmd(char* cmd, char* param1, char* param2, char* param3) +{ + int i; + + i = 0; + + zm_uart_send(ATH_DEBUGGER_VERSION_STR, strlen(ATH_DEBUGGER_VERSION_STR)); + zm_uart_send(ATH_COMMAND_LIST_STR, strlen(ATH_COMMAND_LIST_STR)); + + while (command_table[i].cmd_func) + { + zm_uart_send(command_table[i].cmd_str, strlen(command_table[i].cmd_str)); + zm_uart_send("\t", 1); + zm_uart_send(command_table[i].help_str, strlen(command_table[i].help_str)); + zm_uart_send("\n\r", 2); + i++; + } + return i; +} + +int db_ldr_cmd(char* cmd, char* param1, char* param2, char* param3) +{ + unsigned long val; + unsigned long addr; + char val_str[20]; + char addr_str[20]; + + if (db_ascii_to_hex(param1, &addr) != -1) + { + if( addr == 0 ) + { + zm_uart_send("Error! bad address 0x%08x.\n\r", (unsigned long)addr); + return -1; + } + if (strcmp(cmd, "LDR") == 0) + { + addr &= 0xfffffffc; + //val = *(unsigned long *)addr; + + val = HAL_WORD_REG_READ(addr); + } + else if (strcmp(cmd, "LDRH") == 0) + { + addr &= 0xfffffffe; + val = HAL_HALF_WORD_REG_READ(addr); + } + else if (strcmp(cmd, "LDRB") == 0) + { + } + + db_hex_to_ascii(val, val_str); + db_hex_to_ascii(addr, addr_str); + + zm_uart_send(addr_str, strlen(addr_str)); + zm_uart_send(" : ", 3); + zm_uart_send(val_str, strlen(val_str)); + zm_uart_send("\n\r", 2); + + return 0; + } + else + { + zm_uart_send("Error! Incorrect format.\n\r", 26); + + return -1; + } +} + +int db_str_cmd(char* cmd, char* param1, char* param2, char* param3) +{ + unsigned long val; + unsigned long addr; + char val_str[20]; + char addr_str[20]; + + if ((strlen(param2) > 0) && + (db_ascii_to_hex(param1, &addr) != -1) && + (db_ascii_to_hex(param2, &val) != -1)) + { + if (strcmp(cmd, "STR") == 0) + { + addr &= 0xfffffffc; + //HAL_WORD_REG_WRITE(addr, val); + HAL_WORD_REG_WRITE(addr, val); + //*(volatile unsigned long *)(addr & 0xfffffffc) = (unsigned long)val; + } + + else if (strcmp(cmd, "STRH") == 0) + { + addr &= 0xfffffffe; + //*(volatile unsigned short *)(addr & 0xfffffffe) = (unsigned short)val; + HAL_HALF_WORD_REG_WRITE(addr, val); + } + else if (strcmp(cmd, "STRB") == 0) + { + if( addr & 0x00f00000 ) + HAL_BYTE_REG_WRITE(addr, val); + else + HAL_BYTE_REG_WRITE(addr^3, val); + //*(volatile unsigned char *)addr = (unsigned char)val; + } + + db_hex_to_ascii(val, val_str); + db_hex_to_ascii(addr, addr_str); + + zm_uart_send(addr_str, strlen(addr_str)); + zm_uart_send(" : ", 3); + zm_uart_send(val_str, strlen(val_str)); + zm_uart_send("\n\r", 2); + + return 0; + } + else + { + zm_uart_send("Error! Incorrect format.\n\r", 26); + + return -1; + } +} + +// macro extension the address to dump the memory +#define FOUR_BYTE_HEX_DUMP(addr) (" %02x %02x %02x %02x", \ + *(uint8_t*)((addr)+3), *(uint8_t*)((addr)+2), \ + *(uint8_t*)((addr)+1), *(uint8_t*)((addr))) + + +int db_dump_memory(char* cmd, char* param1, char* param2, char* param3) +{ + unsigned long addr; + unsigned long length; + unsigned long ptrAddr; + int i; + + if (db_ascii_to_hex(param1, &addr) != -1 && + (db_ascii_to_int(param2, &length) != -1)) + { + // if no length, default is 128 bytes to dump + if( length == 0 ) + length = 128; + addr &= 0xfffffffc; + + A_PRINTF("length: %d\n\r", length); + + //zm_uart_send(" 7 6 5 4 3 2 1 0\n\r", 28); + A_PRINTF(" 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00\n\r"); + A_PRINTF("------------------------------------------------------------\n\r"); + for (i=0; i=0 && data <=10 ) + delay = data; + else + delay = 3; + + A_PRINTF("==>set cb to %d seconds \n\r", delay); + } + + } + else + { + A_PRINTF("\tintr read - read the interrenable status\n\r"); + A_PRINTF("\tintr timer on/off/tick - timer attach on/off/ticks\n\r"); + + } + +#endif //#if SYSTEM_MODULE_INTR + return 0; +} + +uint32_t usb_swap_flag = 0; //default +uint32_t usb_swap_flag_changed = 0; +int db_usb_cmd(char* cmd, char* param1, char* param2, char* param3) +{ + A_PRINTF("THIS IS USB COMMAND\n\r"); + + if( strcmp(param1, "que") == 0 ) + { + HIFusb_DescTraceDump(); + } + else + { + A_PRINTF("\tusb que - dump descriptor queue\n\r"); + A_PRINTF("\tusb fw on/off - enable/disable write fw download to ram\n\r"); + + } + return 0; +} + +static void clk_change(uint32_t clk, uint32_t ratio, uint32_t baud) +{ + uint32_t clk_sel = 0; + + switch(clk){ + case 22: + clk_sel = 0; + break; + case 88: + clk_sel = 1; + break; + case 44: + clk_sel = 2; + break; + case 117: + clk_sel = 4; + break; + case 40: + clk_sel = 6; + break; + default: + clk_sel = 6; + break; + } + + HAL_WORD_REG_WRITE(0x50040, (0x300|clk_sel|(ratio>>1)<<12)); + A_UART_HWINIT((clk*1000*1000)/ratio, baud); + +} + +int db_clock_cmd(char* cmd, char* param1, char* param2, char* param3) +{ + uint32_t ratio = 1; + uint32_t baud = 19200; + uint32_t clk = 0; + + if( db_ascii_to_int(param1, &clk) != -1 ) + { + A_PRINTF("changing clock to %d\n", clk); + clk_change(clk, ratio, baud); + } +} + +int db_info_cmd(char* cmd, char* param1, char* param2, char* param3) +{ +#if 1 + + if(strcmp(param1, "ram") == 0 ) + { + A_ALLOCRAM_DEBUG(); + } +#if SYSTEM_MODULE_SYS_MONITOR + else if(strcmp(param1, "cpu") == 0) + zfPrintCpuUtilization(); +#endif + else // defalut dump + HIFusb_DescTraceDump(); + + return 1; + +#else + + { + uint32_t ccount1; + uint32_t ccount2; + + uint32_t data; + register uint32_t data1; + if( db_ascii_to_hex(param1, &data1)==0 ) + { + __asm__ __volatile__ ( + "rsr %0, ccount" + : "=a" (ccount1) : : "memory" + ); + data = *(volatile uint32_t *)(data1); + __asm__ __volatile__ ( + "rsr %0, ccount" + : "=a" (ccount2) : : "memory" + ); + A_PRINTF("\n\rread 0x%08x (0x%08x) use %d clocks\n\r", data1, data, ccount2-ccount1); + } + + __asm__ __volatile__ ( + "rsr %0, ccount" + : "=a" (ccount1) : : "memory" + ); + data = *(volatile uint32_t *)(data1); + __asm__ __volatile__ ( + "rsr %0, ccount" + : "=a" (ccount2) : : "memory" + ); + A_PRINTF("\n\rread 0x%08x (0x%08x) use %d clocks\n\r", data1, data, ccount2-ccount1); + + + __asm__ __volatile__ ( + "rsr %0, ccount" + : "=a" (ccount1) : : "memory" + ); + data = *(volatile uint32_t *)(data2); + __asm__ __volatile__ ( + "rsr %0, ccount" + : "=a" (ccount2) : : "memory" + ); + A_PRINTF("read 0x%08x (0x%08x) use %d clocks\n\r", data2, data, ccount2-ccount1); + + + __asm__ __volatile__ ( + "rsr %0, ccount" + : "=a" (ccount1) : : "memory" + ); + data = *(volatile uint32_t *)(data3); + __asm__ __volatile__ ( + "rsr %0, ccount" + : "=a" (ccount2) : : "memory" + ); + A_PRINTF("read 0x%08x (0x%08x) use %d clocks\n\r", data3, data, ccount2-ccount1); + + } +#endif + return 1; +} + +int db_cmd_dbg(char* cmd, char* param1, char* param2, char* param3) +{ +} + +int db_cmd_dmips(char* cmd, char* param1, char* param2, char* param3) +{ + +} + +int db_cmd_starthtc(char* cmd, char* param1, char* param2, char* param3) +{ + extern htc_handle_t htc_handle; + HTC_Ready(htc_handle); +} + +int db_cmd_memtest(char* cmd, char* param1, char* param2, char* param3) +{ +} + + +void eep_test() +{ +} + +#define WRITE_USB_DESC(pDesc, Offset) \ + { \ + uint16_t *pSrc = 0; \ + uint16_t mSize = 0; \ + pSrc = (uint16_t *)(pDesc); \ + mSize = (*pSrc&0xff)/2; \ + A_PRINTF("0x%04x, 0x%04x, 0x%08x\n", Offset, mSize, pSrc); \ + A_EEP_WRITE(Offset, mSize, pSrc); \ + A_DELAY_USECS(500); \ + } + +#define READ_USB_DESC(pDesc, Offset, Size) \ + { \ + uint16_t *pDst; \ + uint16_t mSize; \ + pDst = (uint16_t *)pDesc; \ + A_EEP_READ(Offset, 1, &mSize); \ + mSize = mSize &0xff; \ + mSize = mSize/2; \ + if( mSize > Size) \ + mSize = Size; \ + A_PRINTF("0x%04x, 0x%04x, 0x%08x\n", Offset, mSize, pDst); \ + A_EEP_READ(Offset, mSize, pDst); \ + A_DELAY_USECS(500); \ + } + + +//////////////////////////////////////////////////////////////////////////////////////////////// + +extern uint16_t UsbDeviceDescriptor[]; +extern uint16_t String00Descriptor[]; +extern uint16_t String10Descriptor[]; +extern uint16_t String20Descriptor[]; +extern uint16_t String30Descriptor[]; + +int db_eeprom_cmd(char* cmd, char* param1, char* param2, char* param3) +{ + +} + +int db_wdt_cmd(char* cmd, char* param1, char* param2, char* param3) +{ + if ( strcmp(param1, "rst") == 0 ) + { + A_PRINTF(" reseting.....................\n\n\r"); + A_WDT_RESET(); + } + else if( strcmp(param1, "on") == 0 ) + { + A_WDT_ENABLE(); + } + else if (strcmp(param1, "off") == 0 ) + { + A_WDT_DISABLE(); + } + else if ( strcmp(param1, "boot") == 0 ) + { + if (ENUM_WDT_BOOT == A_WDT_LASTBOOT() ) + A_PRINTF("LAST BOOT IS %s", "wdt"); + else + A_PRINTF("LAST BOOT IS %s", "normal boot"); + } + else if (strcmp(param1, "loop") == 0 ) + { + T_WDT_CMD wdt_cmd; + uint32_t time_offset; + A_PRINTF(" doing the wdt reseting................\n\n\r"); + + if( db_ascii_to_hex(param2, &time_offset)!=0 ) + { + if( time_offset < 0 || time_offset >0xffffffff ) + time_offset = 0xffffff; + } + A_PRINTF(" doing the wdt reseting (wdt tick: 0x%08x................\n\n\r", time_offset); + wdt_cmd.cmd = WDT_TIMEOUT; + wdt_cmd.timeout = time_offset; + + A_WDT_SET(wdt_cmd); + while(1) ; + } + else if (strcmp(param1, "noloop") == 0 ) + { + T_WDT_CMD wdt_cmd; + uint32_t time_offset; + A_PRINTF(" doing the wdt reseting................\n\n\r"); + + if( db_ascii_to_hex(param3, &time_offset)!=0 ) + { + if( time_offset < 0 || time_offset >0xffffffff ) + time_offset = 0xffffff; + } + A_PRINTF(" doing the wdt reseting (wdt tick: 0x%08x................\n\n\r", time_offset); + + wdt_cmd.cmd = WDT_TIMEOUT; + wdt_cmd.timeout = time_offset; + + A_WDT_SET(wdt_cmd); + } + else if( strcmp(param1, "event") == 0 ) + { + uint32_t event= 0x00123400; +#define USB_BYTE_REG_WRITE(addr, val) HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val)) +#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3)) + +#define USB_WORD_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val)) +#define USB_WORD_REG_READ(addr) HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr)) + + // disable ep3 intr + USB_BYTE_REG_WRITE(0x17, USB_BYTE_REG_READ(0x17)|0xc0); + + //ZM_CBUS_FIFO_SIZE_REG = 0xf; + USB_WORD_REG_WRITE(0x100, 0x0f); + + //ZM_EP3_DATA_REG = event; + USB_WORD_REG_WRITE(0xF8, event); + + // tx done + USB_BYTE_REG_WRITE(0xAE, USB_BYTE_REG_READ(0xAE)|0x08); + + // enable ep3 intr + USB_BYTE_REG_WRITE(0x17, USB_BYTE_REG_READ(0x17)&0xbf); + } +} + +#if defined(PROJECT_K2) +#if SYSTEM_MODULE_SFLASH +/* Serial Flash -> Chip Erase, Sector Erase, Block Erase */ +int db_cmd_sferase(char* cmd, char* param1, char* param2, char* param3) +{ + unsigned long addr; + + if (strcmp(param1, "s") == 0) + { + if (db_ascii_to_hex(param2, &addr) != -1 && addr < SPI_FLASH_MAX_SIZE) + { + /* Sector size is 4K (0x1000) */ + A_PRINTF("Sector addr : 0x%08X\n\r", addr - addr%0x1000); + A_SFLASH_ERASE(ZM_SFLASH_SECTOR_ERASE, addr); + + return 0; + } + else + { + A_PRINTF("Error! Incorrect format.\n\r"); + return -1; + } + } + else if (strcmp(param2, "b") == 0) + { + if (db_ascii_to_hex(param2, &addr) != -1 && addr < SPI_FLASH_MAX_SIZE) + { + /* Sector size is 64K (0x10000) */ + A_PRINTF("Block addr : 0x%08X\n\r", addr - addr%0x10000); + A_SFLASH_ERASE(ZM_SFLASH_BLOCK_ERASE, addr); + + return 0; + } + else + { + A_PRINTF("Error! Incorrect format.\n\r"); + return -1; + } + } + else if (strcmp(param1, "c") == 0) + { + A_SFLASH_ERASE(ZM_SFLASH_CHIP_ERASE, addr); + + A_PRINTF("\n\r"); + return 0; + } + else + { + A_PRINTF("Error! Unknown command.\n\r"); + return -1; + } +} + +/* Serial Flash -> Program */ +int db_cmd_sfpg(char* cmd, char* param1, char* param2, char* param3) +{ + unsigned long addr, len, buf; + + if (db_ascii_to_hex(param1, &addr) != -1 && + db_ascii_to_hex(param2, &len) != -1 && + db_ascii_to_hex(param3, &buf) != -1 && + ((addr+len) <= SPI_FLASH_MAX_SIZE) && + addr%4 == 0 && len%4 == 0 && buf%4 == 0 && + ((buf >=0x500000 && buf < 0x528000) || (buf >=0x4e0000 && buf < 0x4e6000)) ) + { + A_SFLASH_PROG(addr, len, (A_UINT8 *)buf); + + A_PRINTF("\n\r"); + return 0; + } + else + { + A_PRINTF("Error! Incorrect format.\n\r"); + return -1; + } +} + +/* Serial Flash -> Read, Fast Read to UART */ +int db_cmd_sfru(char* cmd, char* param1, char* param2, char* param3) +{ + A_UINT32 i; + unsigned long addr1, addr2, t_addr; + A_UINT32 fast, val; + + if (strcmp(param1, "r") == 0) + fast = 0; + else if (strcmp(param1, "f") == 0) + fast = 1; + else + { + A_PRINTF("Error! Unknown command.\n\r"); + return -1; + } + + if (db_ascii_to_hex(param2, &addr1) != -1 && + db_ascii_to_hex(param3, &addr2) != -1 && + addr1 < addr2 && addr1 < SPI_FLASH_MAX_SIZE && + addr2 < SPI_FLASH_MAX_SIZE && addr1%4 == 0) + { + A_PRINTF("addr data data data data data data data data\n\r"); + A_PRINTF("====== ======== ======== ======== ======== ======== ======== ======== ========"); + + for (i = 0, t_addr = addr1; t_addr < addr2; i++, t_addr += 4) + { + if ((i%8) == 0) + A_PRINTF("\n\r%06X ", t_addr); + + A_SFLASH_READ(fast, t_addr, 4, (A_UINT8 *)&val); + A_PRINTF("%08X ", val); + } + + A_PRINTF("\n\r"); + return 0; + } + else + { + A_PRINTF("Error! Incorrect format.\n\r"); + return -1; + } +} + +/* Serial Flash -> Read, Fast Read to Memory */ +int db_cmd_sfrm(char* cmd, char* param1, char* param2, char* param3) +{ + A_UINT32 i; + unsigned long addr1, addr2, t_addr; + A_UINT32 fast; + A_UINT8 *buf = (A_UINT8 *)0x520000; + + if (strcmp(param1, "r") == 0) + fast = 0; + else if (strcmp(param1, "f") == 0) + fast = 1; + else + { + A_PRINTF("Error! Unknown command.\n\r"); + return -1; + } + + if (db_ascii_to_hex(param2, &addr1) != -1 && + db_ascii_to_hex(param3, &addr2) != -1 && + addr1 < addr2 && addr1 < SPI_FLASH_MAX_SIZE && + addr2 < SPI_FLASH_MAX_SIZE && addr1%4 == 0) + { + for (i = 0, t_addr = addr1; t_addr < addr2; i++, t_addr += 4) + { + A_SFLASH_READ(fast, t_addr, 4, buf + i*4); + } + + A_PRINTF("\n\r"); + return 0; + } + else + { + A_PRINTF("Error! Incorrect format.\n\r"); + return -1; + } +} + +/* Serial Flash -> Read Status Register */ +int db_cmd_sfrdsr(char* cmd, char* param1, char* param2, char* param3) +{ + A_PRINTF("0x%02X\n\r", A_SFLASH_RDSR()); + return 0; +} +#endif +#endif /* #if defined(PROJECT_K2) */ + +/* Memory Comparison */ +int db_cmd_memcmp(char* cmd, char* param1, char* param2, char* param3) +{ + unsigned long addr1, addr2, len; + A_UINT8 *buf1, *buf2; + + if (db_ascii_to_hex(param1, &addr1) != -1 && + db_ascii_to_hex(param2, &addr2) != -1 && + db_ascii_to_hex(param3, &len) != -1 && + addr1 != addr2 && addr1%4 == 0 && addr2%4 == 0 && len%4 == 0) + { + buf1 = (A_UINT8 *)addr1; + buf2 = (A_UINT8 *)addr2; ; + + A_PRINTF("memcmp(buf1, buf2, len) = %d\n\r", A_MEMCMP(buf1, buf2, len)); + return 0; + } + else + { + A_PRINTF("Error! Incorrect format.\n\r"); + return -1; + } +} + +/* Memory Dump */ +int db_cmd_memdump(char* cmd, char* param1, char* param2, char* param3) +{ + A_UINT32 i; + unsigned long addr1, addr2, t_addr; + A_UINT32 *val; + + if (db_ascii_to_hex(param1, &addr1) != -1 && db_ascii_to_hex(param2, &addr2) != -1 && addr1 < addr2 && addr1%4 == 0) + { + A_PRINTF("addr data data data data data data data data\n\r"); + A_PRINTF("====== ======== ======== ======== ======== ======== ======== ======== ========"); + + for (i = 0, t_addr = addr1; t_addr < addr2; i++, t_addr += 4) + { + if ((i%8) == 0) + A_PRINTF("\n\r%06X ", t_addr); + + val = (A_UINT32 *)t_addr; + A_PRINTF("%08X ", *val); + } + + A_PRINTF("\n\r"); + return 0; + } + else + { + A_PRINTF("Error! Incorrect format.\n\r"); + return -1; + } +} +void cmnos_dbg_module_install(struct dbg_api *apis) +{ + apis->_dbg_init = zfDebugInit; + apis->_dbg_task = zfDebugTask; +} + +#endif /* SYSTEM_MODULE_DBG */ + diff --git a/target_firmware/magpie_fw_dev/target/cmnos/dbg_api.h b/target_firmware/magpie_fw_dev/target/cmnos/dbg_api.h new file mode 100755 index 0000000..8d877b2 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/cmnos/dbg_api.h @@ -0,0 +1,43 @@ +/************************************************************************/ +/* */ +/* FILE DESCRIPTION */ +/* */ +/* This file contains console debug command table structure and */ +/* relative defination. */ +/* */ +/* ROUTINES */ +/* */ +/* None */ +/* */ +/* NOTES */ +/* */ +/* None */ +/* */ +/************************************************************************/ +#ifndef _DB_DEFS_H +#define _DB_DEFS_H + +#define ATH_DEBUGGER_VERSION_STR "Magpie Debugger: "ATH_VERSION_STR +#define ATH_COMMAND_LIST_STR "\n\r===Command Listing===\n\r" + +#define DB_MAX_COMMAND_LENGTH 40 /* Maximum command line length */ +#define COMMAND_BUFFER_SIZE 6 /* Maximum command buffer size */ + +struct DB_COMMAND_STRUCT +{ + char* cmd_str; /* Command string */ + char* help_str; /* Help description */ + int (*cmd_func)(char *, char*, char*, char*); /* Command function */ +}; + +#define zm_uart_send(x, y) A_PUTS(x) +#define zm_get_char(x) A_GETC(x) + +/******** hardware API table structure (API descriptions below) *************/ +struct dbg_api { + void (*_dbg_init)(void); + void (*_dbg_task)(void); +}; + + +#endif diff --git a/target_firmware/magpie_fw_dev/target/cmnos/k2_cmnos_clock_patch.c b/target_firmware/magpie_fw_dev/target/cmnos/k2_cmnos_clock_patch.c new file mode 100755 index 0000000..0e08535 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/cmnos/k2_cmnos_clock_patch.c @@ -0,0 +1,60 @@ +#include "athos_api.h" +#include "sys_cfg.h" + +a_uint32_t ref_clk = 0; +extern a_uint32_t cticks; + +// clock change +// +void cmnos_clock_init_patch(a_uint32_t refclk) +{ + ref_clk = refclk; +} + +// retrieve current clock setting +// +a_uint32_t cmnos_refclk_speed_get_patch(void) +{ + return ref_clk; +} + + +// software emulate delay function +// +void cmnos_delay_us_patch(int us) +{ + a_uint32_t start_time = NOW(); + unsigned int num_ticks = us*ref_clk; // system_freq == number of ticks per 1us + + while ( (NOW() - start_time) < num_ticks) { + /* busy spin */ + ; + } +} + + +// software emulate microsecond ticks +// +void cmnos_tick_patch(void) +{ + static a_uint32_t last_tick = 0; + a_uint32_t current_tick = NOW(); + a_uint32_t delta_tick; + + delta_tick = (A_UINT32 ) (current_tick - last_tick)/(ref_clk<<10); + + if( delta_tick > 0 ) + last_tick = current_tick; + + cticks += delta_tick; +} + +// get current sysmem up time in milliseconds based +// +a_uint32_t cmnos_milliseconds_patch(void) +{ + cmnos_tick_patch(); + + return (cticks); +} + diff --git a/target_firmware/magpie_fw_dev/target/cmnos/k2_fw_cmnos_printf.c b/target_firmware/magpie_fw_dev/target/cmnos/k2_fw_cmnos_printf.c new file mode 100755 index 0000000..32dc65e --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/cmnos/k2_fw_cmnos_printf.c @@ -0,0 +1,316 @@ +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### + + +#include "sys_cfg.h" + +#include "dt_defs.h" + +#if SYSTEM_MODULE_PRINT + +#if MOVE_PRINT_TO_RAM + +#include "athos_api.h" + +#define is_digit(c) ((c >= '0') && (c <= '9')) + +#if defined(__GNUC__) && defined(__mips__) +#define va_list __builtin_va_list +#define va_arg __builtin_va_arg +#define va_start __builtin_va_start +#define va_end __builtin_va_end +#define va_copy __builtin_va_copy +#endif + +#include + +LOCAL void +cmnos_write_char(char c) +{ + if (c == '\n') { + A_PUTC('\r'); + A_PUTC('\n'); + } else if (c == '\r') { + } else { + A_PUTC(c); + } +} + +LOCAL void +(*_putc)(char c) = cmnos_write_char; + +LOCAL int +_cvt(unsigned long val, char *buf, long radix, char *digits) +{ + char temp[80]; + char *cp = temp; + int length = 0; + + if (val == 0) { + /* Special case */ + *cp++ = '0'; + } else { + while (val) { + *cp++ = digits[val % radix]; + val /= radix; + } + } + while (cp != temp) { + *buf++ = *--cp; + length++; + } + *buf = '\0'; + return (length); +} + + +LOCAL +int cmnos_vprintf(void (*putc)(char c), const char *fmt, va_list ap) +{ + char buf[sizeof(long)*8]; + char c, sign, *cp=buf; + int left_prec, right_prec, zero_fill, pad, pad_on_right, + i, islong, islonglong; + long val = 0; + int res = 0, length = 0; + + while ((c = *fmt++) != '\0') { + if (c == '%') { + c = *fmt++; + left_prec = right_prec = pad_on_right = islong = islonglong = 0; + if (c == '-') { + c = *fmt++; + pad_on_right++; + } + if (c == '0') { + zero_fill = TRUE; + c = *fmt++; + } else { + zero_fill = FALSE; + } + while (is_digit(c)) { + left_prec = (left_prec * 10) + (c - '0'); + c = *fmt++; + } + if (c == '.') { + c = *fmt++; + zero_fill++; + while (is_digit(c)) { + right_prec = (right_prec * 10) + (c - '0'); + c = *fmt++; + } + } else { + right_prec = left_prec; + } + sign = '\0'; + if (c == 'l') { + // 'long' qualifier + c = *fmt++; + islong = 1; + if (c == 'l') { + // long long qualifier + c = *fmt++; + islonglong = 1; + } + } + // Fetch value [numeric descriptors only] + switch (c) { + case 'p': + islong = 1; + case 'd': + case 'D': + case 'x': + case 'X': + case 'u': + case 'U': + case 'b': + case 'B': + if (islonglong) { + val = va_arg(ap, long); + } else if (islong) { + val = (long)va_arg(ap, long); + } else{ + val = (long)va_arg(ap, int); + } + if ((c == 'd') || (c == 'D')) { + if (val < 0) { + sign = '-'; + val = -val; + } + } else { + // Mask to unsigned, sized quantity + if (islong) { + val &= (1ULL << (sizeof(long) * 8)) - 1; + } else{ + val &= (1ULL << (sizeof(int) * 8)) - 1; + } + } + break; + default: + break; + } + // Process output + switch (c) { + case 'p': // Pointer + (*putc)('0'); + (*putc)('x'); + zero_fill = TRUE; + left_prec = sizeof(unsigned long)*2; + case 'd': + case 'D': + case 'u': + case 'U': + case 'x': + case 'X': + switch (c) { + case 'd': + case 'D': + case 'u': + case 'U': + length = _cvt(val, buf, 10, "0123456789"); + break; + case 'p': + case 'x': + length = _cvt(val, buf, 16, "0123456789abcdef"); + break; + case 'X': + length = _cvt(val, buf, 16, "0123456789ABCDEF"); + break; + } + cp = buf; + break; + case 's': + case 'S': + cp = va_arg(ap, char *); + if (cp == NULL) { + cp = ""; + } + length = 0; + while (cp[length] != '\0') length++; + break; + case 'c': + case 'C': + c = va_arg(ap, int /*char*/); + (*putc)(c); + res++; + continue; + case 'b': + case 'B': + length = left_prec; + if (left_prec == 0) { + if (islonglong) + length = sizeof(long)*8; + else if (islong) + length = sizeof(long)*8; + else + length = sizeof(int)*8; + } + for (i = 0; i < length-1; i++) { + buf[i] = ((val & ((long)1< 0) { + (*putc)(c); + res++; + } + } + if (sign != '\0') { + (*putc)(sign); + res++; + } + while (length-- > 0) { + c = *cp++; + (*putc)(c); + res++; + } + if (pad_on_right) { + while (pad-- > 0) { + (*putc)(' '); + res++; + } + } + } else { + (*putc)(c); + res++; + } + } + return (res); +} + +int +fw_cmnos_printf(const char *fmt, ...) +{ + va_list ap; + int ret; + + va_start(ap, fmt); + + //if (A_SERIAL_ENABLED()) { + if (1) { + ret = cmnos_vprintf(_putc, fmt, ap); + } else { + ret = 0; + } + + va_end(ap); + return (ret); +} + +#endif /* MOVE_PRINT_TO_RAM */ + +#endif /* SYSTEM_MODULE_PRINT */ diff --git a/target_firmware/magpie_fw_dev/target/cmnos/printf_api.h b/target_firmware/magpie_fw_dev/target/cmnos/printf_api.h new file mode 100755 index 0000000..afcb837 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/cmnos/printf_api.h @@ -0,0 +1,15 @@ +#ifndef __PRINTF_API_H__ +#define __PRINTF_API_H__ + +struct printf_api { + void (* _printf_init)(void); + int (* _printf)(const char * fmt, ...); +}; + +/* NB: The printf module requires the serial module. */ +void cmnos_printf_module_install(struct printf_api *tbl); +int cmnos_printf(const char *fmt, ...); + + + +#endif /* __PRINTF_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/cmnos/sflash_api.h b/target_firmware/magpie_fw_dev/target/cmnos/sflash_api.h new file mode 100755 index 0000000..e6d21a8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/cmnos/sflash_api.h @@ -0,0 +1,24 @@ +#ifndef __SFLASH_API_H__ +#define __SFLASH_API_H__ + +/* Constant definition */ +#define ZM_SFLASH_SECTOR_ERASE 1 +#define ZM_SFLASH_BLOCK_ERASE 2 +#define ZM_SFLASH_CHIP_ERASE 0 + +/*!- interface of eeprom access + * + */ +struct sflash_api { + /* Indispensable functions */ + void (* _sflash_init)(void); + void (* _sflash_erase)(A_UINT32 erase_type, A_UINT32 addr); /* 1. erase_type : chip/block/sector, 2. addr : no use for chip erase */ + void (* _sflash_program)(A_UINT32 addr, A_UINT32 len, A_UINT8 *buf); /* 1. addr : spi flash address(start from 0x0), 2. len : bite number to write , 3. *buf : source memory address */ + void (* _sflash_read)(A_UINT32 fast, A_UINT32 addr, A_UINT32 len, A_UINT8 *buf); /* 1. fast : 1 for fast read, 0 for read, 2. addr : spi flash address(start from 0x0), 3. len : bite number to read , 3. *buf : destination memory address */ + + /* Dispensable functions */ + A_UINT32 (* _sflash_rdsr)(void); /* return the value of status register */ +}; + +#endif /* __SFLASH_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/target/hif/k2_HIF_usb_patch.c b/target_firmware/magpie_fw_dev/target/hif/k2_HIF_usb_patch.c new file mode 100755 index 0000000..2cbf40e --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/hif/k2_HIF_usb_patch.c @@ -0,0 +1,37 @@ +#include "sys_cfg.h" +#include "dt_defs.h" +#include "reg_defs.h" + +#include +#include +#include +#include +#include +#include + +#include "hif_usb.h" + +/* + * -- support more than 64 bytes command on ep4 -- + */ +int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe) +{ + switch(pipe) { + case HIF_USB_PIPE_INTERRUPT: + case HIF_USB_PIPE_COMMAND: + return 512; + + default: + return 1600; + } +} + +/* + * -- move the usb_task to here -- + */ +void _HIFusb_isr_handler_patch(hif_handle_t h) +{ + A_USB_FW_TASK(); + + _HIFusb_isr_handler(); +} diff --git a/target_firmware/magpie_fw_dev/target/hif/k2_fw_usb_api.c b/target_firmware/magpie_fw_dev/target/hif/k2_fw_usb_api.c new file mode 100755 index 0000000..c9f15e4 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/hif/k2_fw_usb_api.c @@ -0,0 +1,744 @@ +#include "usb_defs.h" +#include "usb_type.h" +#include "usb_pre.h" +#include "usb_extr.h" +#include "usb_std.h" +#include "reg_defs.h" +#include "athos_api.h" +#include "usbfifo_api.h" + + +#include "sys_cfg.h" + +typedef void (* USBFIFO_recv_command)(VBUF *cmd); +void _fw_usb_suspend_reboot(); + +extern Action eUsbCxFinishAction; +extern CommandType eUsbCxCommand; +extern BOOLEAN UsbChirpFinish; +extern USB_FIFO_CONFIG usbFifoConf; + +USBFIFO_recv_command m_origUsbfifoRecvCmd = NULL; + +#if SYSTEM_MODULE_USB +#define vUsb_ep0end(void) \ +{ \ + eUsbCxCommand = CMD_VOID; \ + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); \ +} + +#define vUsb_ep0fail(void) USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04) + +#define vUsb_rst() \ +{ \ + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT1)); \ + UsbChirpFinish = FALSE; \ +} + +#define vUsb_suspend() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT2)) + +#define vUsb_resm() USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_OFFSET, \ + (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~BIT3)) + +void _fw_usbfifo_recv_command(VBUF *buf) +{ + A_UINT8 *cmd_data; + A_UINT32 tmp; + + cmd_data = (A_UINT8 *)(buf->desc_list->buf_addr + buf->desc_list->data_offset); + tmp = *((A_UINT32 *)cmd_data); + if ( tmp == 0xFFFFFFFF ) { + _fw_usb_suspend_reboot(); + } else { + m_origUsbfifoRecvCmd(buf); + } +} + +void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig) +{ + m_origUsbfifoRecvCmd = pConfig->recv_command; + + usbFifoConf.get_command_buf = pConfig->get_command_buf; + usbFifoConf.recv_command = _fw_usbfifo_recv_command; + usbFifoConf.get_event_buf = pConfig->get_event_buf; + usbFifoConf.send_event_done = pConfig->send_event_done; +} + +#define CHECK_SOF_LOOP_CNT 50 + +void _fw_usb_suspend_reboot() +{ + volatile uint32_t gpio_in = 0; + volatile uint32_t pupd = 0; + volatile uint32_t t = 0; + volatile uint32_t sof_no=0,sof_no_new=0; + /* Set GO_TO_SUSPEND bit to USB main control register */ + vUsb_suspend(); + A_PRINTF("!USB suspend\n\r"); + + // keep the record of suspend +#if defined(PROJECT_MAGPIE) + *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = SUS_MAGIC_PATTERN; +#elif defined(PROJECT_K2) + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN); +#endif /* #if defined(PROJECT_MAGPIE) */ + + /* Reset USB FIFO */ + A_USB_RESET_FIFO(); + + /* Turn off power */ + A_USB_POWER_OFF(); + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1000; + + // reset ep3/ep4 fifo in case there is data which might affect resuming +// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10)); +// HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10)); + + { + // config gpio to input before goto suspend + + //disable JTAG/ICE + //jtag = HAL_WORD_REG_READ(0x10004054); + //HAL_WORD_REG_WRITE(0x10004054, (jtag|BIT17)); + + //disable SPI + //spi = HAL_WORD_REG_READ(0x50040); + //HAL_WORD_REG_WRITE(0x50040, (spi&~(BIT8))); + + //set all GPIO to input + gpio_in = HAL_WORD_REG_READ(0x1000404c); + HAL_WORD_REG_WRITE(0x100404c, 0x0); + + //set PU/PD for all GPIO except two UART pins + pupd = HAL_WORD_REG_READ(0x10004088); + HAL_WORD_REG_WRITE(0x10004088, 0xA982AA6A); + } + + sof_no= HAL_WORD_REG_READ(0x10004); + for (t = 0; t < CHECK_SOF_LOOP_CNT; t++) + { + A_DELAY_USECS(1000); //delay 1ms + sof_no_new = HAL_WORD_REG_READ(0x10004); + + if(sof_no_new == sof_no) + break; + + sof_no = sof_no_new; + } + + /* + * Reset "printf" module patch point(RAM to ROM) when K2 warm start or suspend, + * which fixed the error issue cause by redownload another different firmware. + */ + _indir_tbl.cmnos.printf._printf = save_cmnos_printf; + + /////////////////////////////////////////////////////////////// + // setting the go suspend here, power down right away... + if (t != CHECK_SOF_LOOP_CNT) // not time out + HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8)); + /////////////////////////////////////////////////////////////// + + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1100; + +#if 0 // pll unstable, h/w bug? + HAL_WORD_REG_WRITE(0x50040, (0x300|6|(1>>1)<<12)); + A_UART_HWINIT((40*1000*1000)/1, 19200); +#endif + { + // restore gpio setting + //HAL_WORD_REG_WRITE(0x10004054, jtag); + //HAL_WORD_REG_WRITE(0x50040, spi); + HAL_WORD_REG_WRITE(0x1000404c, gpio_in); + HAL_WORD_REG_WRITE(0x10004088, pupd); + } + DEBUG_SYSTEM_STATE = (DEBUG_SYSTEM_STATE&(~0xffff)) | 0x1200; + + { + // since we still need to touch mac_base address after resuming back, so that + // reset mac can't be done in ResetFifo function, move to here... + // whole mac control reset.... (bit1) + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT1) ); + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0)); + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 ); + } + + //A_PRINTF("reg(0x10020)=(%x)\n", HAL_WORD_REG_READ(0x10020)); + // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!! + mUSB_STATUS_IN_INT_DISABLE(); + + MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; + MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; + + if (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16 == 0x5342)) { + /* UART_SEL and SPI_SEL */ + HAL_WORD_REG_WRITE(0x50040, (0x300|0|(1>>1)<<12)); + } + + /* Jump to boot code */ + A_USB_JUMP_BOOT(); + +} + +/* + * -- patch usb_fw_task -- + * . usb zero length interrupt should not clear by s/w, h/w will handle that + * . complete suspend handle, configure gpio, turn off related function, + * slow down the pll for stable issue + */ +void _fw_usb_fw_task(void) +{ + register uint8_t usb_interrupt_level1; + register uint8_t usb_interrupt_level2; + + usb_interrupt_level1 = USB_BYTE_REG_READ(ZM_INTR_GROUP_OFFSET); +#if 0 // these endpoints are handled by DMA + if (usb_interrupt_level1 & BIT5) //Group Byte 5 + { + vUsb_Data_In(); + } +#endif + if (usb_interrupt_level1 & BIT4) + { + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_4_OFFSET); + if( usb_interrupt_level2 & BIT6) + A_USB_REG_OUT();//vUsb_Reg_Out(); + } + + if (usb_interrupt_level1 & BIT6) + { + //zfGenWatchDogEvent(); + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_6_OFFSET); + if( usb_interrupt_level2 & BIT6) + A_USB_STATUS_IN();//vUsb_Status_In(); + } + + if (usb_interrupt_level1 & BIT0) //Group Byte 0 + { + //usb_interrupt_level2 = ZM_INTR_SOURCE_0_REG; + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET); + + // refer to FUSB200, p 48, offset:21H, bit7 description, should clear the command abort interrupt first!? + if (usb_interrupt_level2 & BIT7) + { + //ZM_INTR_SOURCE_0_REG &= 0x7f; // Handle command abort + USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_0_OFFSET, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_0_OFFSET)& ~BIT7)); + A_PRINTF("![SOURCE_0] bit7 on\n\r"); + } + + if (usb_interrupt_level2 & BIT1) + { + //A_PRINTF("![USB] ep0 IN in \n\r"); + A_USB_EP0_TX(); // USB EP0 tx interrupt + } + if (usb_interrupt_level2 & BIT2) + { + //A_PRINTF("![USB] ep0 OUT in\n\r"); + A_USB_EP0_RX(); // USB EP0 rx interrupt + } + if (usb_interrupt_level2 & BIT0) + { + //A_PRINTF("![USB] ep0 SETUP in\n\r"); + A_USB_EP0_SETUP(); + //vWriteUSBFakeData(); + } +// else if (usb_interrupt_level2 & BIT3) + if (usb_interrupt_level2 & BIT3) + { + vUsb_ep0end(); +// A_PRINTF("![SOURCE_0] ep0 CMD_END\n\r"); + } + if (usb_interrupt_level2 & BIT4) + { + vUsb_ep0fail(); +// A_PRINTF("![SOURCE_0] ep0 CMD_FAIL\n\r"); + } + if (eUsbCxFinishAction == ACT_STALL) + { + // set CX_STL to stall Endpoint0 & will also clear FIFO0 + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x04); +// A_PRINTF("![USB] ZM_CX_CONFIG_STATUS_REG = 0x04\n\r"); + } + else if (eUsbCxFinishAction == ACT_DONE) + { + // set CX_DONE to indicate the transmistion of control frame + USB_BYTE_REG_WRITE(ZM_CX_CONFIG_STATUS_OFFSET, 0x01); + } + eUsbCxFinishAction = ACT_IDLE; + } + + if (usb_interrupt_level1 & BIT7) //Group Byte 7 + { + //usb_interrupt_level2 = ZM_INTR_SOURCE_7_REG; + usb_interrupt_level2 = USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET); + +#if 0 + if (usb_interrupt_level2 & BIT7) + { + vUsb_Data_Out0Byte(); +// A_PRINTF("![SOURCE_7] bit7 on, clear it\n\r"); + } + if (usb_interrupt_level2 & BIT6) + { + vUsb_Data_In0Byte(); +// A_PRINTF("![SOURCE_7] bit6 on, clear it\n\r"); + } +#endif + + if (usb_interrupt_level2 & BIT1) + { + vUsb_rst(); + //USB_BYTE_REG_WRITE(ZM_INTR_SOURCE_7_REG, (USB_BYTE_REG_READ(ZM_INTR_SOURCE_7_OFFSET)&~0x2)); + A_PRINTF("!USB reset\n\r"); +// A_PRINTF("![0x1012c]: %\n\r", USB_WORD_REG_READ(0x12c)); + } + if (usb_interrupt_level2 & BIT2) + { + // TBD: the suspend resume code should put here, Ryan, 07/18 + // + // issue, jump back to rom code and what peripherals should we reset here? + // + _fw_usb_suspend_reboot(); + } + if (usb_interrupt_level2 & BIT3) + { + vUsb_resm(); + A_PRINTF("!USB resume\n\r"); + } + } + +} + + +void _fw_usb_reset_fifo(void) +{ + volatile uint32_t *reg_data; + + HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10)); + HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10)); + + // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!! + mUSB_STATUS_IN_INT_DISABLE(); + + // update magic pattern to indicate this is a suspend + // k2: MAGPIE_REG_RST_WDT_TIMER_CTRL_ADDR + // magpie: MAGPIE_REG_RST_STATUS_ADDR + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, SUS_MAGIC_PATTERN); + + /* + * Before USB suspend, USB DMA must be reset(refer to Otus) + * Otus runs the following statements only + * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, BIT0|BIT2 ); + * HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 ); + * K2 must run the following statements additionally + * reg_data = (A_UINT32 *)(USB_CTRL_BASE_ADDRESS + 0x118); + * *reg_data = 0x00000000; + * *reg_data = 0x00000001; + * because of Hardware bug in K2 + */ + reg_data = (uint32_t *)(USB_CTRL_BASE_ADDRESS + 0x118); + *reg_data = 0x00000000; + + // reset both usb(bit2)/wlan(bit1) dma + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (BIT2) ); + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, (HAL_WORD_REG_READ(MAGPIE_REG_RST_PWDN_CTRL_ADDR)|BIT0)); + HAL_WORD_REG_WRITE( MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0 ); + + *reg_data = 0x00000001; + + /* MAC warem reset */ + //reg_data = (uint32_t *)(K2_REG_MAC_BASE_ADDR + 0x7000); + //*reg_data = 0x00000001; + + //A_DELAY_USECS(1); + + //*reg_data = 0x00000000; + + //while (*reg_data) ; + + A_PRINTF("\n change clock to 22 and go to suspend now!"); + + /* UART_SEL */ + HAL_WORD_REG_WRITE(0x50040, (0x200|0|(1>>1)<<12)); + A_UART_HWINIT((22*1000*1000), 19200); +} + +/* + * -- support more than 64 bytes command on ep4 -- + */ +void vUsb_Reg_Out_patch(void) +{ + uint16_t usbfifolen; + uint16_t ii; + uint32_t ep4_data; + static volatile uint32_t *regaddr; // = (volatile uint32_t *) ZM_CMD_BUFFER; + static uint16_t cmdLen; + static VBUF *buf; + BOOLEAN cmd_is_last = FALSE; + static BOOLEAN cmd_is_new = TRUE; + + // get the size of this transcation + usbfifolen = USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_LOW_OFFSET); + + // check is command is new + if( cmd_is_new ){ + + buf = usbFifoConf.get_command_buf(); + cmdLen = 0; + + if( !buf ) + goto ERR; + + // copy free, assignment buffer of the address + regaddr = (uint32_t *)buf->desc_list->buf_addr; + + cmd_is_new = FALSE; + } + + // just in case, suppose should not happen + if( !buf ) + goto ERR; + + // if size is smaller, this is the last command! + // + // zero-length supposed should be set through 0x27/bit7->0x19/bit4, not here + // + if( usbfifolen> 2) + 1; + else + usbfifolen = usbfifolen >> 2; + +// A_PRINTF("copy data out from fifo to - %p\n\r", regaddr); + // retrieve the data from fifo + for(ii = 0; ii < usbfifolen; ii++) + { + ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out + *regaddr = ep4_data; + regaddr++; + } + + // if this is the last command, callback to HTC + if ( cmd_is_last ) + { + buf->desc_list->next_desc = NULL; + buf->desc_list->data_offset = 0; + buf->desc_list->data_size = cmdLen; + buf->desc_list->control = 0; + buf->next_buf = NULL; + buf->buf_length = cmdLen; + + usbFifoConf.recv_command(buf); + + cmd_is_new = TRUE; + } + + goto DONE; +ERR: +// we might get no command buffer here? +// but if we return here, the ep4 fifo will be lock out, +// so that we still read them out but just drop it ? + for(ii = 0; ii < usbfifolen; ii++) + { + ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out + } + +DONE: + //mUSB_STATUS_IN_INT_ENABLE(); + ; +} + + + +/* + * -- usb1.1 ep6 fix -- + */ +extern uint16_t u8UsbConfigValue; +extern uint16_t u8UsbInterfaceValue; +extern uint16_t u8UsbInterfaceAlternateSetting; +extern SetupPacket ControlCmd; +extern void vUsbClrEPx(void); + +void vUSBFIFO_EP6Cfg_FS_patch(void) +{ +#if (FS_C1_I0_A0_EP_NUMBER >= 6) + int i; + + //EP0X06 + mUsbEPMap(EP6, FS_C1_I0_A0_EP6_MAP); + mUsbFIFOMap(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_MAP); + mUsbFIFOConfig(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_CONFIG); + + for(i = FS_C1_I0_A0_EP6_FIFO_START + 1 ; + i < FS_C1_I0_A0_EP6_FIFO_START + FS_C1_I0_A0_EP6_FIFO_NO ; i ++) + { + mUsbFIFOConfig(i, (FS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff)); + mUsbEPMxPtSzLow(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff)); + mUsbEPinHighBandSet(EP6 , FS_C1_I0_A0_EP6_DIRECTION, FS_C1_I0_A0_EP6_MAX_PACKET); +#endif +} + +void vUsbFIFO_EPxCfg_FS_patch(void) +{ + switch (u8UsbConfigValue) + { + #if (FS_CONFIGURATION_NUMBER >= 1) + // Configuration 0X01 + case 0X01: + switch (u8UsbInterfaceValue) + { + #if (FS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + case 0: + switch (u8UsbInterfaceAlternateSetting) + { + + #if (FS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0 + case 0: + + // snapped.... + + // patch up this ep6_fs config + vUSBFIFO_EP6Cfg_FS_patch(); + + break; + + #endif + default: + break; + } + break; + #endif + default: + break; + } + break; + #endif + default: + break; + } + //mCHECK_STACK(); +} + + +BOOLEAN bSet_configuration_patch(void) +{ + //A_PRINTF("bSet_configuration...\n\r"); + + bSet_configuration(); + + if (mLOW_BYTE(mDEV_REQ_VALUE()) == 0) + { + // snapped.... + ; + } + else + { + if (mUsbHighSpeedST()) // First judge HS or FS?? + { + // snapped.... + ; + } + else + { + // snapped.... + vUsbFIFO_EPxCfg_FS_patch(); + } + + // snapped.... + } + + eUsbCxFinishAction = ACT_DONE; + return TRUE; +} + + +/* + * -- support more than 64 bytes command on ep3 -- + */ +void vUsb_Status_In_patch(void) +{ + uint16_t count; + uint16_t remainder; + u16_t RegBufLen; + BOOLEAN cmdEnd = FALSE; + + static u16_t mBufLen; + static VBUF *evntbuf = NULL; + static volatile u32_t *regaddr; + static BOOLEAN cmd_is_new = TRUE; + + if( cmd_is_new ) + { + evntbuf = usbFifoConf.get_event_buf(); + if ( evntbuf != NULL ) + { + regaddr = VBUF_GET_DATA_ADDR(evntbuf); + mBufLen = evntbuf->buf_length; + } + else + { + mUSB_STATUS_IN_INT_DISABLE(); + goto ERR_DONE; + } + + } + +// if( mBufLen>bUSB_EP_MAX_PKT_SIZE_64 ) +// A_PRINTF("EP3 send %d bytes to host \n", mBufLen); + +// while(1) + { + if( mBufLen > bUSB_EP_MAX_PKT_SIZE_64 ) { + RegBufLen = bUSB_EP_MAX_PKT_SIZE_64; + mBufLen -= bUSB_EP_MAX_PKT_SIZE_64; + } + // TODO: 64 byes... controller supposed will take care of zero-length? + else { + RegBufLen = mBufLen; + cmdEnd = TRUE; + } + + /* INT use EP3 */ + for(count = 0; count < (RegBufLen / 4); count++) + { + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr); + regaddr++; + } + + remainder = RegBufLen % 4; + + if (remainder) + { + switch(remainder) + { + case 3: + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7); + break; + case 2: + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3); + break; + case 1: + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1); + break; + } + + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr); + + // Restore CBus FIFO size to word size + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF); + } + + mUSB_EP3_XFER_DONE(); + +// if( mBufLen<=bUSB_EP_MAX_PKT_SIZE_64 ) +// break; + } + + if ( evntbuf != NULL && cmdEnd ) + { + usbFifoConf.send_event_done(evntbuf); + cmd_is_new = TRUE; + } + +ERR_DONE: + ; +} + +extern uint16_t *u8ConfigDescriptorEX; +extern uint16_t *pu8DescriptorEX; +extern uint16_t u16TxRxCounter; +extern BOOLEAN bGet_descriptor(void); + +uint16_t ConfigDescriptorPatch[30]; + +#define EP3_TRANSFER_TYPE_OFFSET 17 +#define EP3_INT_INTERVAL 19 +#define EP4_TRANSFER_TYPE_OFFSET 21 +#define EP4_INT_INTERVAL 22 + +BOOLEAN bGet_descriptor_patch(void) +{ + if (mDEV_REQ_VALUE_HIGH() == 2) { + uint8_t *p = (uint8_t *)u8ConfigDescriptorEX; + + /* Copy ConfigDescriptor */ + memcpy(ConfigDescriptorPatch, p, sizeof(ConfigDescriptorPatch)); + + p = (uint8_t *)ConfigDescriptorPatch; + + /* Patch the transfer type of EP3 and EP4 */ + ConfigDescriptorPatch[EP3_TRANSFER_TYPE_OFFSET] = 0x0283; + ConfigDescriptorPatch[EP3_INT_INTERVAL] = 0x0700; + ConfigDescriptorPatch[EP4_TRANSFER_TYPE_OFFSET] = 0x4002; + ConfigDescriptorPatch[EP4_INT_INTERVAL] = 0x00; + + switch (mDEV_REQ_VALUE_LOW()) + { + case 0x00: // configuration no: 0 + pu8DescriptorEX = ConfigDescriptorPatch; + u16TxRxCounter = ConfigDescriptorPatch[1]; + //u16TxRxCounter = 46; + break; + default: + return FALSE; + } + + if (u16TxRxCounter > mDEV_REQ_LENGTH()) + u16TxRxCounter = mDEV_REQ_LENGTH(); + + A_USB_EP0_TX_DATA(); + return TRUE; + } + else { + return bGet_descriptor(); + } +} + +extern BOOLEAN bStandardCommand(void); + +BOOLEAN bStandardCommand_patch(void) +{ + if (mDEV_REQ_REQ() == USB_SET_CONFIGURATION) { + A_USB_SET_CONFIG(); + +#if ENABLE_SWAP_DATA_MODE + // SWAP FUNCTION should be enabled while DMA engine is not working, + // the best place to enable it is before we trigger the DMA + MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; + + #if SYSTEM_MODULE_HP_EP5 + MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; + #endif + + #if SYSTEM_MODULE_HP_EP6 + MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; + #endif + +#endif //ENABLE_SWAP_DATA_MODE + return TRUE; + } + else { + return bStandardCommand(); + } +} + +#endif + + diff --git a/target_firmware/magpie_fw_dev/target/htc/htc.c b/target_firmware/magpie_fw_dev/target/htc/htc.c new file mode 100755 index 0000000..99c1561 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/htc/htc.c @@ -0,0 +1,821 @@ +/* + * @File: + * + * @Abstract: host target communications + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include "htc_internal.h" + +#define A_UNCACHED_ADDR(addr) addr + +/* prototypes */ +LOCAL void HTCControlSvcProcessMsg(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t pBuffers, void *arg); +LOCAL void HTCControlSvcProcessSendComplete(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg); +LOCAL void HTCMsgRecvHandler(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); +LOCAL void HTCSendDoneHandler(adf_nbuf_t buf, void *context); +LOCAL void HTCFreeMsgBuffer(HTC_CONTEXT *pHTC, adf_nbuf_t pBuffer); +LOCAL adf_nbuf_t HTCAllocMsgBuffer(HTC_CONTEXT *pHTC); +LOCAL void HTCCheckAndSendCreditReport(HTC_CONTEXT *pHTC, A_UINT32 EpMask, HTC_ENDPOINT *pEndpoint, HTC_ENDPOINT_ID Id); +LOCAL void AdjustCreditThreshold(HTC_ENDPOINT *pEndpoint); +LOCAL void HTC_AssembleBuffers(HTC_CONTEXT *pHTC, int Count, int Size); +LOCAL htc_handle_t _HTC_Init(/*A_UINT32 dataAddr,*/ + HTC_SETUP_COMPLETE_CB SetupComplete, + HTC_CONFIG *pConfig); +LOCAL void _HTC_RegisterService(htc_handle_t handle, HTC_SERVICE *pService); +LOCAL void _HTC_Ready(htc_handle_t handle); +LOCAL void ReturnBuffers(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, A_BOOL sendCreditFlag); +LOCAL void _HTC_ReturnBuffers(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers); +LOCAL void _HTC_ReturnBuffersList(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t bufHead); +LOCAL void _HTC_SendMsg(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers); +void _HTC_PauseRecv(HTC_ENDPOINT_ID EndpointID); +void _HTC_ResumeRecv(HTC_ENDPOINT_ID EndpointID); +LOCAL void HTCProcessConnectMsg(HTC_CONTEXT *pHTC, HTC_CONNECT_SERVICE_MSG *pMsg); +LOCAL void HTCProcessConfigPipeMsg(HTC_CONTEXT *pHTC, HTC_CONFIG_PIPE_MSG *pMsg); +LOCAL void RedistributeCredit(adf_nbuf_t buf, int toPipeId); +LOCAL void _HTC_Shutdown(htc_handle_t htcHandle); + +/* macro to check if the service wants to prevent credit dribbling by using + a dynamic threshold */ +#define CHECK_AND_ADJUST_CREDIT_THRESHOLD(pEndpoint) \ + if ((pEndpoint)->ConnectionFlags & HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE) { \ + AdjustCreditThreshold((pEndpoint)); \ + } + +LOCAL void HTC_AssembleBuffers(HTC_CONTEXT *pHTC, int Count, int Size) +{ + BUF_Pool_create_pool(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, Count, Size); +} + +LOCAL htc_handle_t _HTC_Init(HTC_SETUP_COMPLETE_CB SetupComplete, + HTC_CONFIG *pConfig) +{ + HIF_CALLBACK hifCBConfig; + HTC_CONTEXT *pHTC; + + pHTC = (HTC_CONTEXT *)adf_os_mem_alloc(sizeof(HTC_CONTEXT)); + + adf_os_mem_zero(pHTC, sizeof(HTC_CONTEXT)); + + pHTC->OSHandle = pConfig->OSHandle; + pHTC->PoolHandle = pConfig->PoolHandle; + pHTC->hifHandle = pConfig->HIFHandle; + + hifCBConfig.send_buf_done = A_INDIR(htc._HTC_SendDoneHandler); + hifCBConfig.recv_buf = A_INDIR(htc._HTC_MsgRecvHandler); + hifCBConfig.context = pHTC; + + /* initialize hardware layer */ + HIF_register_callback(pConfig->HIFHandle, &hifCBConfig); + + /* see if the host wants us to override the number of ctrl buffers */ + pHTC->NumBuffersForCreditRpts = 0; + + if (0 == pHTC->NumBuffersForCreditRpts) { + /* nothing to override, simply set default */ + pHTC->NumBuffersForCreditRpts = HTC_DEFAULT_NUM_CTRL_BUFFERS; + } + + pHTC->MaxEpPendingCreditRpts = 0; + + if (0 == pHTC->MaxEpPendingCreditRpts) { + pHTC->MaxEpPendingCreditRpts = HTC_DEFAULT_MAX_EP_PENDING_CREDIT_REPORTS; + } + /* calculate the total allocation size based on the number of credit report buffers */ + pHTC->CtrlBufferAllocSize = MIN_CREDIT_BUFFER_ALLOC_SIZE * pHTC->NumBuffersForCreditRpts; + /* we need at least enough buffer space for 1 ctrl message */ + pHTC->CtrlBufferAllocSize = A_MAX(pHTC->CtrlBufferAllocSize,MAX_HTC_SETUP_MSG_SIZE); + + /* save the size of each buffer/credit we will receive */ + pHTC->RecvBufferSize = pConfig->CreditSize; //RecvBufferSize; + pHTC->TotalCredits = pConfig->CreditNumber; + pHTC->TotalCreditsAssigned = 0; + + /* setup the pseudo service that handles HTC control messages */ + pHTC->HTCControlService.ProcessRecvMsg = A_INDIR(htc._HTC_ControlSvcProcessMsg); + pHTC->HTCControlService.ProcessSendBufferComplete = A_INDIR(htc._HTC_ControlSvcProcessSendComplete); + pHTC->HTCControlService.TrailerSpcCheckLimit = HTC_CTRL_BUFFER_CHECK_SIZE; + pHTC->HTCControlService.MaxSvcMsgSize = MAX_HTC_SETUP_MSG_SIZE; + pHTC->HTCControlService.ServiceCtx = pHTC; + + /* automatically register this pseudo service to endpoint 1 */ + pHTC->Endpoints[ENDPOINT0].pService = &pHTC->HTCControlService; + HIF_get_default_pipe(pHTC->hifHandle, &pHTC->Endpoints[ENDPOINT0].UpLinkPipeID, + &pHTC->Endpoints[ENDPOINT0].DownLinkPipeID); + + /* Initialize control pipe so we could receive the HTC control packets */ + // @TODO: msg size! + HIF_config_pipe(pHTC->hifHandle, pHTC->Endpoints[ENDPOINT0].UpLinkPipeID, 1); + + /* set the first free endpoint */ + pHTC->CurrentEpIndex = ENDPOINT1; + pHTC->SetupCompleteCb = SetupComplete; + + /* setup buffers for just the setup phase, we only need 1 buffer to handle + * setup */ + HTC_AssembleBuffers(pHTC, 4, MAX_HTC_SETUP_MSG_SIZE); + + /* start hardware layer so that we can queue buffers */ + HIF_start(pHTC->hifHandle); + + return pHTC; +} + +LOCAL void _HTC_Shutdown(htc_handle_t htcHandle) +{ + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + + adf_os_mem_free(pHTC); +} + +LOCAL void _HTC_RegisterService(htc_handle_t htcHandle, HTC_SERVICE *pService) +{ + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + + /* add it to the list */ + pService->pNext = pHTC->pServiceList; + pHTC->pServiceList = pService; +} + +LOCAL void _HTC_Ready(htc_handle_t htcHandle) +{ + adf_nbuf_t pBuffer; + HTC_READY_MSG *pReady; + a_uint8_t *addr; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + + pBuffer = HTCAllocMsgBuffer(pHTC); + + /* an optimization... the header length is chosen to + * be aligned on a 16 bit bounday, the fields in the message are designed to + * be aligned */ + addr = adf_nbuf_put_tail(pBuffer, sizeof(HTC_READY_MSG)); + pReady = (HTC_READY_MSG *)addr; + A_MEMZERO(pReady,sizeof(HTC_READY_MSG)); + pReady->MessageID = adf_os_htons(HTC_MSG_READY_ID); + pReady->CreditSize = adf_os_htons((A_UINT16)pHTC->RecvBufferSize); + pReady->CreditCount = adf_os_htons((A_UINT16)pHTC->TotalCredits); + pReady->MaxEndpoints = ENDPOINT_MAX; + + /* send out the message */ + HTC_SendMsg(pHTC, ENDPOINT0, pBuffer); + /* now we need to wait for service connection requests */ +} + +LOCAL void ReturnBuffers(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, + adf_nbuf_t pBuffers, A_BOOL sendCreditFlag) +{ + int nbufs = 1; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + + /* supply some head-room again */ + adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH); + + /* enqueue all buffers to the single mailbox */ + HIF_return_recv_buf(pHTC->hifHandle, pHTC->Endpoints[EndpointID].UpLinkPipeID, pBuffers); + + if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) { + A_UINT32 epCreditMask = (1 << EndpointID); + /* we are running normally */ + /* update pending credit counts with the number of buffers that were added */ + pHTC->Endpoints[EndpointID].CreditsToReturn += (A_INT16)nbufs; + pHTC->Endpoints[EndpointID].CreditsConsumed -= (A_INT16)nbufs; + /* update bit map that this endpoint has non-zero credits */ + pHTC->EpCreditPendingMap |= epCreditMask; + + if (sendCreditFlag) { + HTCCheckAndSendCreditReport(pHTC, epCreditMask,&pHTC->Endpoints[EndpointID],EndpointID); + } + + } else { + /* we have not started yet so all return operations are simply adding buffers + * to the interface at startup, so we can keep track of how many total + * credits we get */ + /* update global count that will be returned to the host */ + pHTC->TotalCredits += nbufs; + } +} + +LOCAL void _HTC_ReturnBuffersList(htc_handle_t htcHandle, + HTC_ENDPOINT_ID EndpointID, + adf_nbuf_queue_t bufHead) +{ + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + adf_nbuf_t netbuf, tmpNbuf; + + /* retrieve each nbuf in the queue */ + netbuf = adf_nbuf_queue_first(&bufHead); + + while (netbuf) { + + tmpNbuf = netbuf; + netbuf = adf_nbuf_queue_next(netbuf); + + ReturnBuffers(htcHandle, EndpointID, tmpNbuf, FALSE); + } + + HTCCheckAndSendCreditReport(pHTC, (1 << EndpointID),&pHTC->Endpoints[EndpointID],EndpointID); +} + +LOCAL void _HTC_ReturnBuffers(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, + adf_nbuf_t pBuffers) +{ + ReturnBuffers(htcHandle, EndpointID, pBuffers, TRUE); +} + +LOCAL void _HTC_SendMsg(htc_handle_t htcHandle, HTC_ENDPOINT_ID EndpointID, + adf_nbuf_t pBuffers) +{ + HTC_FRAME_HDR *pHTCHdr; + int totsz; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + HTC_BUF_CONTEXT *ctx; + + ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pBuffers); + + /* init total size (this does not include the space we will put in for the HTC header) */ + totsz = adf_nbuf_len(pBuffers); + + /* the first buffer stores the header */ + /* back up buffer by a header size when we pass it down, by agreed upon convention the caller + * points the buffer to it's payload and leaves head room for the HTC header + * Note: in HTCSendDoneHandler(), we undo this so that the caller get's it's buffer + * back untainted */ + pHTCHdr = (HTC_FRAME_HDR *)adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH); + + /* flag that this is the header buffer that was modified */ + ctx->htc_flags |= HTC_FLAGS_BUF_HDR; + /* mark where this buffer came from */ + ctx->end_point = EndpointID; + /* the header start is ALWAYS aligned since we DMA it directly */ + + /* set some fields, the rest of them will be filled below when we check for + * trailer space */ + pHTCHdr->Flags = 0; + pHTCHdr->EndpointID = EndpointID; + + /* check opportunistically if we can return any reports via a trailer */ + do { + int room,i,totalReportBytes; + A_UINT32 creditsPendingMap, compareMask; + HTC_CREDIT_REPORT *pCreditRpt; + HTC_RECORD_HDR *pRecHdr; + int pipeMaxLen; + A_UINT32 roomForPipeMaxLen; + + /* figure out how much room the last buffer can spare */ + pipeMaxLen = HIF_get_max_msg_len(pHTC->hifHandle, + pHTC->Endpoints[EndpointID].DownLinkPipeID); + roomForPipeMaxLen = pipeMaxLen - adf_nbuf_headroom(pBuffers) - adf_nbuf_len(pBuffers); + if ( roomForPipeMaxLen < 0 ) { + roomForPipeMaxLen = 0; + } + + room = adf_os_min( adf_nbuf_tailroom(pBuffers), roomForPipeMaxLen); + if (room < (int)(sizeof(HTC_CREDIT_REPORT) + sizeof(HTC_RECORD_HDR))) { + /* no room for any reports */ + break; + } + /* note, a record header only has 8 bit fields, so this is safe. + * we need an uncached pointer here too */ + totalReportBytes = 0; + + /* get a copy */ + creditsPendingMap = pHTC->EpCreditPendingMap; + + /* test pending map to see if we can send a report , if any + * credits are available, we might as well send them on the + * unused space in the buffer */ + if (creditsPendingMap) { + + pRecHdr = (HTC_RECORD_HDR *)adf_nbuf_put_tail(pBuffers, + sizeof(HTC_RECORD_HDR)); + + /* set the ID, the length will be updated with the number of credit reports we + * can fit (see below) */ + pRecHdr->RecordID = HTC_RECORD_CREDITS; + pRecHdr->Length = 0; + /* the credit report follows the record header */ + totalReportBytes += sizeof(HTC_RECORD_HDR); + room -= sizeof(HTC_RECORD_HDR); + + /* walkthrough pending credits map and build the records */ + for (i = 0; + (creditsPendingMap != 0) && (room >= (int)sizeof(HTC_CREDIT_REPORT)); + i++) { + compareMask = (1 << i); + if (compareMask & creditsPendingMap) { + + pCreditRpt = (HTC_CREDIT_REPORT *)adf_nbuf_put_tail(pBuffers, + sizeof(HTC_CREDIT_REPORT)); + + /* clear pending mask, we are going to return all these credits */ + creditsPendingMap &= ~(compareMask); + /* add this record */ + pCreditRpt->EndpointID = i; + pCreditRpt->Credits = (A_UINT8)pHTC->Endpoints[i].CreditsToReturn; + /* remove pending credits, we always send deltas */ + pHTC->Endpoints[i].CreditsToReturn = 0; + /* adjust new threshold for this endpoint if needed */ + CHECK_AND_ADJUST_CREDIT_THRESHOLD(&pHTC->Endpoints[i]); + /* update this record length */ + pRecHdr->Length += sizeof(HTC_CREDIT_REPORT); + room -= sizeof(HTC_CREDIT_REPORT); + totalReportBytes += sizeof(HTC_CREDIT_REPORT); + + if ( room < sizeof(HTC_CREDIT_REPORT) ) { + break; + } + } + } + + /* update new pending credits map */ + pHTC->EpCreditPendingMap = creditsPendingMap; + } + + if (totalReportBytes <= 0) { + break; + } + + /* must fit into a byte, this should never actually happen since + * the maximum possible number of endpoints is 32. + * The trailer can have at most 1 credit record with up to 32 reports in the record. + * The trailer can have at most 1 lookahead record with only 1 lookahead report in the record. + */ + + /* set header option bytes */ + pHTCHdr->ControlBytes[0] = totalReportBytes; + /* HTC frame contains a trailer */ + pHTCHdr->Flags |= HTC_FLAGS_RECV_TRAILER; + /* increment total size by the reports we added */ + totsz += totalReportBytes; + /* adjust the last buffer we used for adding on the trailer */ + } while (FALSE); + + if (totsz == 0) { + } + + /* set length for message (this includes any reports that were added above) */ + pHTCHdr->PayloadLen = adf_os_htons(totsz); + HIF_send_buffer(pHTC->hifHandle, pHTC->Endpoints[EndpointID].DownLinkPipeID, pBuffers); +} + +void _HTC_PauseRecv(HTC_ENDPOINT_ID EndpointID) +{ +} + +void _HTC_ResumeRecv(HTC_ENDPOINT_ID EndpointID) +{ +} + +int _HTC_GetReservedHeadroom(htc_handle_t htcHandle) +{ + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)htcHandle; + + return HTC_HDR_LENGTH + HIF_get_reserved_headroom(pHTC->hifHandle); +} + +void htc_module_install(struct htc_apis *pAPIs) +{ + pAPIs->_HTC_Init = _HTC_Init; + pAPIs->_HTC_ReturnBuffers = _HTC_ReturnBuffers; + pAPIs->_HTC_ReturnBuffersList = _HTC_ReturnBuffersList; + pAPIs->_HTC_Ready = _HTC_Ready; + pAPIs->_HTC_RegisterService = _HTC_RegisterService; + pAPIs->_HTC_SendMsg = _HTC_SendMsg; + pAPIs->_HTC_Shutdown = _HTC_Shutdown; + pAPIs->_HTC_GetReservedHeadroom = _HTC_GetReservedHeadroom; + pAPIs->_HTC_MsgRecvHandler = HTCMsgRecvHandler; + pAPIs->_HTC_SendDoneHandler = HTCSendDoneHandler; + pAPIs->_HTC_ControlSvcProcessMsg = HTCControlSvcProcessMsg; + pAPIs->_HTC_ControlSvcProcessSendComplete = HTCControlSvcProcessSendComplete; +} + +/* free message to the free list */ +LOCAL void HTCFreeMsgBuffer(HTC_CONTEXT *pHTC, adf_nbuf_t buf) +{ + BUF_Pool_free_buf(pHTC->PoolHandle, POOL_ID_HTC_CONTROL, buf); +} + +/* HTC control message allocator (also used for empty frames to send trailer options) */ +LOCAL adf_nbuf_t HTCAllocMsgBuffer(HTC_CONTEXT *pHTC) +{ + return BUF_Pool_alloc_buf(pHTC->PoolHandle, + POOL_ID_HTC_CONTROL, + HTC_GetReservedHeadroom(pHTC)); +} + +LOCAL void HTCCheckAndSendCreditReport(HTC_CONTEXT *pHTC, A_UINT32 EpMask, + HTC_ENDPOINT *pEndpoint, HTC_ENDPOINT_ID Eid) +{ + adf_nbuf_t pCredBuffer; + HTC_BUF_CONTEXT *ctx; + + do { + /* check if host needs credits */ + if (!(pHTC->EpHostNeedsCreditMap & EpMask)) { + /* host does not need any credits for this set */ + break; + } + /* check if any are pending */ + if (!(pHTC->EpCreditPendingMap & EpMask)) { + /* nothing to send up */ + break; + } + /* was an endpoint specified? */ + if (pEndpoint != NULL) { + /* see if a threshold is in effect for this endpoint */ + if (pEndpoint->CreditReturnThreshhold != 0) { + if (pEndpoint->CreditsToReturn < pEndpoint->CreditReturnThreshhold) { + /* this endpoint is using a threshold to prevent credits from dribbling + * back to the host */ + break; + } + } + + if (pEndpoint->PendingCreditReports >= pHTC->MaxEpPendingCreditRpts) { + /* this endpoint already has some reports outstanding */ + /* flag that as soon as a buffer is reaped, we issue a credit update to + * pick up this credit that is being held up because the endpoint has already + * exceeded the max outstanding credit report limit */ + pHTC->StateFlags |= HTC_SEND_CREDIT_UPDATE_SOON; + break; + } + } + + /* if we get here we have some credits to send up */ + + /* allocate a message buffer for the trailer */ + pCredBuffer = HTCAllocMsgBuffer(pHTC); + if (NULL == pCredBuffer) { + /* no buffers left to send an empty message with trailers, host will just + * have to wait until we get our endpoint 0 messages back.. */ + /* mark that we need to send an update as soon as we can get a buffer back */ + pHTC->StateFlags |= HTC_SEND_CREDIT_UPDATE_SOON; + break; + } + + ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pCredBuffer); + if (pEndpoint != NULL) { + /* keep track of pending reports */ + pEndpoint->PendingCreditReports++; + /* save the endpoint in order to decrement the count when the send completes */ + ctx->htc_flags = Eid | HTC_FLAGS_CREDIT_RPT; + } + + /* this is an empty message, the HTC_SendMsg will tack on a trailer in the remaining + * space, NOTE: no need to flush the cache, the header and trailers are assembled + * using uncached addresses */ + HTC_SendMsg(pHTC, ENDPOINT0, pCredBuffer); + + } while (FALSE); +} + +/* called in response to the arrival of a service connection message */ +LOCAL void HTCProcessConnectMsg(HTC_CONTEXT *pHTC, HTC_CONNECT_SERVICE_MSG *pMsg) +{ + HTC_SERVICE *pService = pHTC->pServiceList; + A_UINT8 connectStatus = HTC_SERVICE_NOT_FOUND; + adf_nbuf_t pBuffer; + HTC_CONNECT_SERVICE_RESPONSE_MSG *pRspMsg; + int metaDataOutLen = 0; + A_UINT16 serviceId = adf_os_ntohs(pMsg->ServiceID); + + pBuffer = HTCAllocMsgBuffer(pHTC); + /* note : this will be aligned */ + pRspMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *) + adf_nbuf_put_tail(pBuffer, sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG)); + + A_MEMZERO(pRspMsg,sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG)); + pRspMsg->MessageID = adf_os_htons(HTC_MSG_CONNECT_SERVICE_RESPONSE_ID); + /* reflect the service ID for this connect attempt */ + pRspMsg->ServiceID = adf_os_htons(serviceId); + + while (pService) { + + if (pHTC->CurrentEpIndex >= ENDPOINT_MAX) { + /* no more endpoints */ + connectStatus = HTC_SERVICE_NO_RESOURCES; + break; + } + + if (serviceId == pService->ServiceID) { + /* we found a match */ + A_UINT8 *pMetaDataIN = NULL; + A_UINT8 *pMetaDataOut; + + /* outgoing meta data resides in the space after the response message */ + pMetaDataOut = ((A_UINT8 *)pRspMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG); + + if (pMsg->ServiceMetaLength != 0) { + /* the meta data follows the connect service message */ + pMetaDataIN = ((A_UINT8 *)pMsg) + sizeof(HTC_CONNECT_SERVICE_MSG); + } + + /* call the connect callback with the endpoint to use and pointers to meta data */ + connectStatus = pService->ProcessConnect(pService, + pHTC->CurrentEpIndex, + pMetaDataIN, + pMsg->ServiceMetaLength, + pMetaDataOut, + &metaDataOutLen); + + /* check if the service accepted this connection request */ + if (HTC_SERVICE_SUCCESS == connectStatus) { + /* set the length of the response meta data going back to the host */ + pRspMsg->ServiceMetaLength = (A_UINT8)metaDataOutLen; + /* set the endpoint ID the host will now communicate over */ + pRspMsg->EndpointID = pHTC->CurrentEpIndex; + /* return the maximum message size for this service */ + pRspMsg->MaxMsgSize = adf_os_htons((A_UINT16)pService->MaxSvcMsgSize); + /* assign this endpoint to this service, this will be used in routing messages */ + pHTC->Endpoints[pHTC->CurrentEpIndex].pService = pService; + /* set connection flags */ + pHTC->Endpoints[pHTC->CurrentEpIndex].ConnectionFlags = pMsg->ConnectionFlags; + + pHTC->Endpoints[pHTC->CurrentEpIndex].DownLinkPipeID = pMsg->DownLinkPipeID; + pHTC->Endpoints[pHTC->CurrentEpIndex].UpLinkPipeID = pMsg->UpLinkPipeID; + + /* mark that we are now connected */ + pService->ServiceFlags |= HTC_SERVICE_FLAGS_CONNECTED; + /* bump up our index, this EP is now in use */ + pHTC->CurrentEpIndex++; + } + + break; + } + + pService = pService->pNext; + } + + pRspMsg->Status = connectStatus; + + /* send out the response message */ + HTC_SendMsg(pHTC, ENDPOINT0, pBuffer); +} + +LOCAL void HTCProcessConfigPipeMsg(HTC_CONTEXT *pHTC, HTC_CONFIG_PIPE_MSG *pMsg) +{ + adf_nbuf_t pBuffer; + HTC_CONFIG_PIPE_RESPONSE_MSG *pRspMsg; + + pBuffer = HTCAllocMsgBuffer(pHTC); + + /* note : this will be aligned */ + pRspMsg = (HTC_CONFIG_PIPE_RESPONSE_MSG *) + adf_nbuf_put_tail(pBuffer, sizeof(HTC_CONFIG_PIPE_RESPONSE_MSG)); + + A_MEMZERO(pRspMsg,sizeof(HTC_CONFIG_PIPE_RESPONSE_MSG)); + + pRspMsg->MessageID = adf_os_htons(HTC_MSG_CONFIG_PIPE_RESPONSE_ID); + /* reflect the service ID for this connect attempt */ + pRspMsg->PipeID = pMsg->PipeID; + + if ( HIF_is_pipe_supported(pHTC->hifHandle, pMsg->PipeID) ) { + pRspMsg->Status = 0; + } else { + pRspMsg->Status = 1; + goto config_done; + } + + if ( (pHTC->TotalCreditsAssigned + pMsg->CreditCount) <= pHTC->TotalCredits ) { + pHTC->TotalCreditsAssigned += pMsg->CreditCount; + } else { + pRspMsg->Status = 2; + goto config_done; + } + + HIF_config_pipe(pHTC->hifHandle, pMsg->PipeID, pMsg->CreditCount); + +config_done: + /* send out the response message */ + HTC_SendMsg(pHTC, ENDPOINT0, pBuffer); +} + +/* process an incomming control message from the host */ +LOCAL void HTCControlSvcProcessMsg(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, + adf_nbuf_t pBuffers, void *arg) +{ + A_BOOL setupComplete = FALSE; + a_uint8_t *anbdata; + a_uint32_t anblen; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)arg; + HTC_UNKNOWN_MSG *pMsg; + + adf_os_assert(hdr_buf == ADF_NBUF_NULL); + + /* we assume buffers are aligned such that we can access the message + * parameters directly*/ + adf_nbuf_peek_header(pBuffers, &anbdata, &anblen); + pMsg = (HTC_UNKNOWN_MSG *)anbdata; + + /* we cannot handle fragmented messages across buffers */ + + switch ( adf_os_ntohs(pMsg->MessageID) ) { + case HTC_MSG_CONNECT_SERVICE_ID: + HTCProcessConnectMsg(pHTC, (HTC_CONNECT_SERVICE_MSG *)pMsg); + break; + case HTC_MSG_CONFIG_PIPE_ID: + HTCProcessConfigPipeMsg(pHTC, (HTC_CONFIG_PIPE_MSG *)pMsg); + break; + case HTC_MSG_SETUP_COMPLETE_ID: + /* the host has indicated that it has completed all + setup tasks and we can now let the services take over to + run the rest of the application */ + setupComplete = TRUE; + /* can't get this more than once */ + break; + default: + ; + } + + if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) { + /* recycle buffer only if we are fully running */ + HTC_ReturnBuffers(pHTC, ENDPOINT0,pBuffers); + } else { + /* supply some head-room again */ + adf_nbuf_push_head(pBuffers, HTC_HDR_LENGTH); + + /* otherwise return the packet back to mbox */ + HIF_return_recv_buf(pHTC->hifHandle, pHTC->Endpoints[EndpointID].UpLinkPipeID, pBuffers); + } + + if (setupComplete) { + /* mark that setup has completed */ + pHTC->StateFlags |= HTC_STATE_SETUP_COMPLETE; + if (pHTC->SetupCompleteCb != NULL) { + pHTC->SetupCompleteCb(); + } + } +} + +/* callback when endpoint 0 send buffers are completed */ +LOCAL void HTCControlSvcProcessSendComplete(HTC_ENDPOINT_ID EndpointID, + adf_nbuf_t pBuffers, void *arg) +{ + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)arg; + HTC_BUF_CONTEXT *ctx; + HTC_ENDPOINT_ID creditRptEndpoint; + + ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(pBuffers); + + /* put them back into the pool */ + if ( ctx->htc_flags & HTC_FLAGS_CREDIT_RPT ) { + /* extract the endpoint number that requested this credit report */ + creditRptEndpoint = ctx->htc_flags & HTC_FLAGS_CRPT_EP_MASK; + pHTC->Endpoints[creditRptEndpoint].PendingCreditReports--; + } + + HTCFreeMsgBuffer(pHTC, pBuffers); + + if (pHTC->StateFlags & HTC_SEND_CREDIT_UPDATE_SOON) { + /* this flag is set when the host could not send a credit report + * because we ran out of HTC control buffers */ + pHTC->StateFlags &= ~HTC_SEND_CREDIT_UPDATE_SOON; + /* send out a report if anything is pending */ + HTCCheckAndSendCreditReport(pHTC, HTC_ANY_ENDPOINT_MASK,NULL,ENDPOINT_MAX); + } +} + +LOCAL void HTCSendDoneHandler(adf_nbuf_t buf, void *context) +{ + A_UINT8 current_eid; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)context; + HTC_BUF_CONTEXT *ctx; + + ctx = (HTC_BUF_CONTEXT *)adf_nbuf_get_priv(buf); + current_eid = ctx->end_point; + + /* Walk through the buffers and fixup the ones we used for HTC headers. + * The buffer list may contain more than one string of HTC buffers comprising of an + * HTC message so we need to check every buffer */ + adf_nbuf_pull_head(buf, HTC_HDR_LENGTH); + + pHTC->Endpoints[current_eid].pService-> + ProcessSendBufferComplete(current_eid, + buf, + pHTC->Endpoints[current_eid].pService->ServiceCtx); +} + +LOCAL void AdjustCreditThreshold(HTC_ENDPOINT *pEndpoint) +{ + A_INT16 creditsOutstanding = pEndpoint->CreditsToReturn + pEndpoint->CreditsConsumed; + /* set the new threshold based on the number of credits that have been consumed + * and which have not been returned by the app. + * Note: it is okay for this threshold to be zero which indicates no threshold + * is in use */ + switch (pEndpoint->ConnectionFlags & HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK) { + case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH : + creditsOutstanding >>= 2; + break; + case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF : + creditsOutstanding >>= 1; + break; + case HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS : + creditsOutstanding = (creditsOutstanding * 3) >> 2; + break; + /* default case is unity */ + } + + pEndpoint->CreditReturnThreshhold = creditsOutstanding; + +} + +LOCAL void RedistributeCredit(adf_nbuf_t buf, int toPipeId) +{ + +} + +/* callback from the mailbox hardware layer when a full message arrives */ +LOCAL void HTCMsgRecvHandler(adf_nbuf_t hdr_buf, adf_nbuf_t buffer, void *context) +{ + A_UINT16 totsz; + HTC_ENDPOINT *pEndpoint; + A_UINT32 eidMask; + int eid; + a_uint8_t *anbdata; + a_uint32_t anblen; + HTC_FRAME_HDR *pHTCHdr; + HTC_CONTEXT *pHTC = (HTC_CONTEXT *)context; + adf_nbuf_t tmp_nbuf; + + if (hdr_buf == ADF_NBUF_NULL) { + /* HTC hdr is not in the hdr_buf */ + tmp_nbuf = buffer; + } + else { + tmp_nbuf = hdr_buf; + } + + adf_nbuf_peek_header(tmp_nbuf, &anbdata, &anblen); + pHTCHdr = (HTC_FRAME_HDR *)anbdata; + + totsz = adf_os_ntohs(pHTCHdr->PayloadLen); + + eid = pHTCHdr->EndpointID; + + pEndpoint = &pHTC->Endpoints[eid]; + eidMask = 1 << eid; + + if (pHTCHdr->Flags & HTC_FLAGS_CREDIT_REDISTRIBUTION) { + /* The pipe id where the credit is redistributed to is carried in Control + * Byte 0 */ + RedistributeCredit(tmp_nbuf, pHTCHdr->ControlBytes[0]); + return; + } + + if (pHTC->StateFlags & HTC_STATE_SETUP_COMPLETE) { + /* after setup we keep track of credit consumption to allow us to + * adjust thresholds to reduce credit dribbling */ + pEndpoint->CreditsConsumed ++; + } + + /* from the design document, we put the endpoint into a "host-needs-credit" state + * when we receive a frame with the NEED_CREDIT_UPDATE flag set . + * if the host received credits through an opportunistic path, then it can + * issue a another frame with this bit cleared, this signals the target to clear + * the "host-needs-credit" state */ + if (pHTCHdr->Flags & HTC_FLAGS_NEED_CREDIT_UPDATE) { + /* the host is running low (or is out) of credits on this + * endpoint, update mask */ + pHTC->EpHostNeedsCreditMap |= eidMask; + /* check and set new threshold since host has reached a low credit situation */ + CHECK_AND_ADJUST_CREDIT_THRESHOLD(pEndpoint); + } else { + /* clear the flag */ + pHTC->EpHostNeedsCreditMap &= ~(eidMask); + pEndpoint->CreditReturnThreshhold = 0; + } + + /* Adjust the first buffer to point to the start of the actual + payload, the first buffer contains the header */ + adf_nbuf_pull_head(tmp_nbuf, HTC_HDR_LENGTH); + + /* NOTE : This callback could re-queue the recv buffers within this calling context. + * The callback could also send a response message within the context of this callback + * as the result of parsing this message. In either case, if there are + * pending credits and the host needs them, a credit report will be sent either through + * the response message trailer or a NULL message through HTC_ReturnBuffers(). + */ + + pEndpoint->pService->ProcessRecvMsg(eid, hdr_buf, buffer, pEndpoint->pService->ServiceCtx); + + /* Calls to HTC_ReturnBuffers drives the endpoint credit reporting state machine. + * We do not want to delay credits for too long in the event that the application is + * holding onto buffers for excessive periods of time. This gives us "some" better + * opportunities to send up credits. */ + HTCCheckAndSendCreditReport(pHTC, eidMask, pEndpoint, eid); +} diff --git a/target_firmware/magpie_fw_dev/target/htc/htc_api.h b/target_firmware/magpie_fw_dev/target/htc/htc_api.h new file mode 100755 index 0000000..a89df34 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/htc/htc_api.h @@ -0,0 +1,117 @@ +/* + * @File: htc_api.h + * + * @Abstract: host-target communications API + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef __HTC_API_H__ +#define __HTC_API_H__ + +#include +#include +#include +#include + +#define HTC_HDR_SZ HTC_HDR_LENGTH +#define HTC_BUFSZ_MAX_SEND 2048 + +typedef void (* HTC_SERVICE_ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx); +typedef void (* HTC_SERVICE_ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx); + +/* HTC service structure : + * the caller is required to allocate storage for the service structure and register the + * structure using HTC_RegisterService() The service must set the following fields: + * ProcessRecvMsg + * ProcessSendBufferComplete + * ProcessConnect + * ServiceID + * MaxSvcMsgSize (for message validation) + * */ +typedef struct _HTC_SERVICE { + struct _HTC_SERVICE *pNext; + /* Callback for processing receive messages. HTC calls this callback whenever a + * message arrives on the endpoint assigned to this service. + * HTC_BUFFER is a chain of buffers containing a full application message. + * HTC_BUFFER->buffer points to the start of the msg buffer (past the HTC header) */ + void (* ProcessRecvMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, adf_nbuf_t, void *ServiceCtx); + /* callback to process completed send buffers */ + void (* ProcessSendBufferComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t, void *ServiceCtx); + /* optional callback when a connection request occurs. + * The EndpointID is the assigned endpoint, the callback returns a connect + * response status code to allow or disallow the connection. + * pDataIn points to the optional meta data supplied in the connection request + * pDataOut points to a buffer to send back meta data + * If no callback is supplied, HTC assumes the connect is allowed */ + A_UINT8 (* ProcessConnect)(struct _HTC_SERVICE *pService, + HTC_ENDPOINT_ID EndpointID, + A_UINT8 *pDataIn, + int LengthIn, + A_UINT8 *pDataOut, + int *pLengthOut); + + A_UINT16 ServiceID; /* service ID to match connection requests */ + A_UINT16 ServiceFlags; /* service flags */ + A_UINT16 MaxSvcMsgSize; /* maximum length of service-specific messages exchanged on the endpoint */ + A_UINT16 TrailerSpcCheckLimit; /* amount of space in each send buffer that HTC can check for trailer + data. This should be set to the smallest HTC buffer that can be sent + through the service. The service can disable trailer data insertion + by setting this value to 0. */ + void *ServiceCtx; +} HTC_SERVICE; + +#define HTC_SERVICE_FLAGS_CONNECTED (1 << 0) /* service has at least 1 connection */ + +#define IS_SERVICE_CONNECTED(s) ((s)->ServiceFlags & HTC_SERVICE_FLAGS_CONNECTED) + +/* configuration settings for the WMI service */ +typedef struct _HTC_CONFIG { + int CreditSize; /* */ + int CreditNumber; + adf_os_handle_t OSHandle; + hif_handle_t HIFHandle; + pool_handle_t PoolHandle; +} HTC_CONFIG; + +typedef struct _HTC_BUF_CONTEXT { + A_UINT8 end_point; + A_UINT8 htc_flags; /* htc flags (used by HTC layer only) */ +} HTC_BUF_CONTEXT; + +typedef void* htc_handle_t; + +/* + * setup complete function, supplied by HTC caller at HTC_init time. + * HTC calls this function after the host has indicated that the service connection + * phase is complete. + * + */ +typedef void (* HTC_SETUP_COMPLETE_CB)(void); + +struct htc_apis { + htc_handle_t (* _HTC_Init)(HTC_SETUP_COMPLETE_CB, HTC_CONFIG *pConfig); + void (* _HTC_Shutdown)(htc_handle_t); + void (* _HTC_RegisterService)(htc_handle_t, HTC_SERVICE *); + void (* _HTC_Ready)(htc_handle_t); + void (* _HTC_ReturnBuffers)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t); + void (* _HTC_ReturnBuffersList)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_queue_t); + void (* _HTC_SendMsg)(htc_handle_t handle, HTC_ENDPOINT_ID EndpointID, adf_nbuf_t); + int (* _HTC_GetReservedHeadroom)(htc_handle_t handle); + + /* These APIs below are for patch purpose only */ + void (*_HTC_MsgRecvHandler)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); + void (*_HTC_SendDoneHandler)(adf_nbuf_t buf, void *context); + void (*_HTC_ControlSvcProcessMsg)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *arg); + void (*_HTC_ControlSvcProcessSendComplete)(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t pBuffers, void *arg); + + void *pReserved; /* for expansion if need be */ +}; + +extern void htc_module_install(struct htc_apis *pAPIs); + +#endif /* _HTC_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/htc/htc_internal.h b/target_firmware/magpie_fw_dev/target/htc/htc_internal.h new file mode 100755 index 0000000..b1dcaa9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/htc/htc_internal.h @@ -0,0 +1,94 @@ +/* + * @File: + * + * @Abstract: internal data and structure definitions for HTC + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef HTC_INTERNAL_H_ +#define HTC_INTERNAL_H_ + +/* minimum buffer size to hold up to 8 endpoint reports, lookahead and the HTC header */ +#define MIN_BUF_SIZE_FOR_RPTS (A_ROUND_UP((sizeof(HTC_LOOKAHEAD_REPORT) + \ + (sizeof(HTC_CREDIT_REPORT)) * 8 + \ + (sizeof(HTC_RECORD_HDR)) * 2 ) + \ + HTC_HDR_LENGTH, \ + sizeof(A_UINT32))) +/* minimum allocation for a credit message */ +#define MIN_CREDIT_BUFFER_ALLOC_SIZE (MIN_BUF_SIZE_FOR_RPTS) + +/* max ctrl buffers size for a setup message */ +#define MAX_HTC_SETUP_MSG_SIZE 64 /* The max size of USB command/event pipe is 64 bytes */ + +/* check size for trailer space */ +#define HTC_CTRL_BUFFER_CHECK_SIZE (MIN_BUF_SIZE_FOR_RPTS - HTC_HDR_LENGTH) + +#define HTC_DEFAULT_NUM_CTRL_BUFFERS 6 + +#define HTC_DEFAULT_MAX_EP_PENDING_CREDIT_REPORTS 3 /* an EP should not have more than this many outstanding reports */ + +#define HTC_FLAGS_CRPT_EP_MASK 0x1F /* if the message is a credit report this is the endpoint + that issued it */ + +#define HTC_FLAGS_CREDIT_RPT (1 << 5) /* the buffer was a credit report */ +#define HTC_FLAGS_BUF_HDR (1 << 6) /* the buffer was manipulated and a header added */ +#define HTC_FLAGS_RECV_END_MSG (1 << 7) /* this buffer is the last buffer for the recev + message (used for recv pause logic) */ + +#define HTC_MAILBOX 0 /* we use mailbox 0 for all communications */ +#define HTC_ANY_ENDPOINT_MASK 0xFFFFFFFF +#define HTC_LOOKAHEAD_POST_VALID 0x55 +#define HTC_LOOKAHEAD_PRE_VALID 0xAA +#define MAX_HTC_CREDITS 255 + +typedef struct _HTC_ENDPOINT { + A_INT16 CreditsToReturn; /* credits that are ready to be returned to the host */ + HTC_SERVICE *pService; /* service that is bound to this endpoint */ +#ifdef HTC_PAUSE_RESUME_REF_COUNTING + int PauseRefCount; /* reference count */ +#endif + A_INT16 CreditReturnThreshhold; /* threshold before credits are returned via NULL pkts, + this reduces dribbling effect */ + A_INT16 CreditsConsumed; /* number of credits consumed (outstanding) on the endpoint */ + A_UINT16 ConnectionFlags; /* HTC connection flags */ + int PendingCreditReports; /* no. of pending credit reports issued by this endpoint */ + A_UINT8 DownLinkPipeID; /* The pipe ID to be use for the direction: target -> host */ + A_UINT8 UpLinkPipeID; /* The pipe ID to be use for the direction: host -> target */ +} HTC_ENDPOINT; + +typedef struct _HTC_CONTEXT { + adf_os_handle_t OSHandle; + HTC_ENDPOINT Endpoints[ENDPOINT_MAX]; /* endpoint state structs */ + A_UINT32 EpHostNeedsCreditMap; /* credit update bit map for all EPs */ + A_UINT32 EpCreditPendingMap; /* credits pending bit map for all EPs */ + A_UINT32 EpRecvPausedMap; /* recv pause state bit map for all EPs */ + HTC_ENDPOINT_ID CurrentEpIndex; /* current unused endpoint index */ + HTC_SERVICE HTCControlService; /* the pseudo service that handles EP0 traffic */ + HTC_SERVICE *pServiceList; /* the service list */ + int RecvBufferSize; /* the length of each recv buffer that HTC is given */ + A_UINT32 StateFlags; /* state flags */ + HTC_SETUP_COMPLETE_CB SetupCompleteCb; /* caller supplied setup completion routine */ + int TotalCredits; /* total credits in system */ + int TotalCreditsAssigned; + int NumBuffersForCreditRpts; /* number of control buffers for credit reports */ + int CtrlBufferAllocSize; /* length of allocation */ + A_UINT8 *pCtrlBuffer; /* control buffer to be carved up for messages */ + int MaxEpPendingCreditRpts; /* maximum number of pending credit reports that any 1 EP can have */ + hif_handle_t hifHandle; + pool_handle_t PoolHandle; + + // Left a door for extension the structure + void *pReserved; +} HTC_CONTEXT; + +#define HTC_STATE_SETUP_COMPLETE (1 << 0) /* HTC host-target setup is complete */ +#define HTC_SEND_CREDIT_UPDATE_SOON (1 << 1) /* Credit update message needs to be sent */ +#define HTC_STATE_BUFF_REALLOC (1 << 2) /* buffers have been reallocated for credit messages */ + +#endif /*HTC_INTERNAL_H_*/ diff --git a/target_firmware/magpie_fw_dev/target/htc/htc_tgt.c b/target_firmware/magpie_fw_dev/target/htc/htc_tgt.c new file mode 100755 index 0000000..370aca8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/htc/htc_tgt.c @@ -0,0 +1,42 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +_A_magpie_indirection_table_t _indir_tbl; + +int init_htc_tgt(void); + +int init_htc_tgt(void) +{ + /* target-side HIF/HTC/WMI module installation */ + BUF_POOL_MODULE_INSTALL(); + HIF_MODULE_INSTALL(); + HTC_MODULE_INSTALL(); + WMI_SERVICE_MODULE_INSTALL(); + + adf_os_print("HTC Target Version 1.xx Loaded...\n"); + return 0; +} + +void exit_htc_tgt(void); + +void exit_htc_tgt(void) +{ + adf_os_print("HTC Target UnLoaded...\n"); +} + +adf_os_export_symbol(_indir_tbl); + +adf_os_virt_module_init(init_htc_tgt); +adf_os_virt_module_exit(exit_htc_tgt); +adf_os_module_dep(htc_tgt, adf_net); +adf_os_module_dep(htc_tgt, inproc_hif); +adf_os_virt_module_name(htc_tgt); diff --git a/target_firmware/magpie_fw_dev/target/inc/OTUS/OTUS_htc.h b/target_firmware/magpie_fw_dev/target/inc/OTUS/OTUS_htc.h new file mode 100755 index 0000000..ba7a62c --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/OTUS/OTUS_htc.h @@ -0,0 +1,88 @@ +#ifndef __AR6K_HTC_H__ +#define __AR6K_HTC_H__ + +/* Host/Target Communications for an AR6K Target */ + +/* Number of mailboxes */ +#define AR6000_MBOX_COUNT 4 + +/* ------ MBOX ID ------ */ +typedef enum +{ + ENDPOINT_UNUSED = -1, + ENDPOINT1 = 0, + ENDPOINT2, + ENDPOINT3, + ENDPOINT4, +} HTC_ENDPOINT_ID; + + +/* An AR6000 DMA Descriptor. See HTC_descriptor(). */ +struct AR6000_DMA_desc_s { + A_UINT32 dma_control; + char *dma_data; + struct AR6000_DMA_desc_s *dma_next; +}; + + +/* + * Make a Mailbox DMA descriptor available to HTC. + * + * Once made available, there is no way to reclaim this memory. + * The caller must guarantee that a descriptor exists for each + * buffer that is used to send or receive. It is expected that + * the caller will supply a bunch of descriptors once during + * initialization, and then forget about them. The number of + * buffers given to HTC for send+recv must never exceed the + * number of descriptors given to HTC. + * + * HTC accesses descriptors via uncached accesses. The caller + * must guarantee not to place any other data in the same cache + * line as a DMA descriptor! In practice, this means that the + * caller should allocate a block of memory for descriptors, + * and the block should include padding at the start and end + * to guarantee there will be no other data in the same cache + * line. + * + * It would be far preferable to bury descriptors in the bufinfo + * structure; but there are practical issues that prevent this. + * It turns out that the most efficient way to add descriptors + * to an active DMA engine requires HTC to "own and actively + * manage" the descriptors. HTC needs to make the association + * between descriptors and buffers at the last possible moment. + * + * extern void _HTC_descriptor(struct AR6000_DMA_desc_s *descriptor); + */ + +/* + * The following interfaces make it easy to allocate suitable + * descriptors for HTC. During initialization, simply use the + * HTC_DESCRIPTORS_INIT macro and specify the number of descriptors + * desired. This number must be a constant, since it is used to + * declare a static array! + * + * The descriptor array is padded with a cache line at the start + * and another at the end. This avoids false sharing between adjacent + * cached data and uncached descriptors. + */ +#define HTC_DESCRIPTOR_SPACE_SIZE(ndescs) \ + (((ndescs) * sizeof(struct AR6000_DMA_desc_s)) + 2*A_CACHE_LINE_SIZE) + +#define HTC_DESCRIPTORS_INIT(ndescs) \ +{ \ + static A_UINT8 HTC_descriptor_space[HTC_DESCRIPTOR_SPACE_SIZE(ndescs)]; \ + struct AR6000_DMA_desc_s *desc; \ + int i; \ + \ + A_DATA_CACHE_FLUSH(HTC_descriptor_space, sizeof(HTC_descriptor_space)); \ + \ + desc = (struct AR6000_DMA_desc_s *) \ + A_ROUND_UP((A_UINT32)HTC_descriptor_space, A_CACHE_LINE_SIZE); \ + \ + for (i=0; i<(ndescs); i++) { \ + HTC_descriptor(desc); \ + desc++; \ + } \ +} + +#endif /* __AR6K_HTC_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/OTUS/OTUS_misc.h b/target_firmware/magpie_fw_dev/target/inc/OTUS/OTUS_misc.h new file mode 100755 index 0000000..666f5e2 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/OTUS/OTUS_misc.h @@ -0,0 +1,70 @@ +#ifndef __AR6K_MISC_H__ +#define __AR6K_MISC_H__ + +/* + * AR6001: CIS Tuple 0x82, "Board Hardware Configuration Information", + * is set at chip reset according to board configuration. Bits in this + * register indicate what type of Host connection is in use. We don't + * have proper header files to describe tuples, so the offset and layout + * for the one tuple that firmwware needs is defined here. + * + * AR6002: The RESET_TUPLE_STATUS register in the GPIO block holds + * Board Hardware Configuration Information. + * + * If the interface is SDIO, then the "INFO_MASK" must be "SDIO_NORMAL". + * For debug purposes, a Target with the KeepAlive jumper may be booted + * before the Host. In this case, INFO_MASK is 0. + * + * For NON-SDIO Host interfaces, the INFO_MASK may hold board information. + * + * By convention, hostless boards set INTERFACE to SDIO, and INFO to + * something OTHER than SDIO_NORMAL or 0. + * + * Layout of Board HW Cfg Info is below. These values are captured at + * reset and made available to software. + * + * These 3 bits are available on AR6002 via RESET_TUPLE_STATUS_ADDRESS; + * they are NOT available on AR6001. + * bit 10: rftest ??? + * bit 9: cmode[1] Bits 9..8 indicate modes as follows: + * bit 8: cmode[0] 0-->normal + * 1-->rftest + * 2-->functional test (ATE) + * 3-->ATPG/MBIST + * + * These 8 bits are available on AR6002 through RESET_TUPLE_STATUS_ADDRESS + * and on both AR6001 and AR6002 through CIS Tuple 0x82. + * bit 7: gpio9 (aka hmode0) Bits 7..6 are the "Interface Config bits" + * bit 6: tdo (aka hmode1) + * bit 5: clk_req + * bit 4: sdio_cmd + * bit 3: sdio_dat[3] + * bit 2: sdio_dat[2] + * bit 1: sdio_dat[1] + * bit 0: sdio_dat[0] + */ + +#if defined(RESET_TUPLE_STATUS_ADDRESS) +#define AR6K_BOARD_HWCFG_CMODE_MASK 0x300 +#define AR6K_BOARD_HWCFG_CMODE_ATE 0x200 +#else +/* + * CIS Tuple 0x82 happens to be located at offset 0x13c into CIS registers. + * This may change across tapeouts, if CIS tuple information changes. + */ +#define AR6K_BOARD_HWCFG_TUPLE_OFFSET 0x13c +#endif + +#define AR6K_BOARD_HWCFG_INTERFACE_MASK 0xc0 +#define AR6K_BOARD_HWCFG_KEEP_ALIVE_MASK 0x20 +#define AR6K_BOARD_HWCFG_INFO_MASK 0x1f + +/* Values for INTERFACE_MASK indicate type of interface */ +#define AR6K_BOARD_HWCFG_SPI 0x00 +#define AR6K_BOARD_HWCFG_SDIO 0x40 +#define AR6K_BOARD_HWCFG_LBCF 0x80 +#define AR6K_BOARD_HWCFG_MSIO 0xc0 + +#define AR6K_BOARD_HWCFG_SDIO_NORMAL 0x1f + +#endif /* __AR6K_MISC_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/OTUS/OTUS_soc.h b/target_firmware/magpie_fw_dev/target/inc/OTUS/OTUS_soc.h new file mode 100755 index 0000000..fda1c5d --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/OTUS/OTUS_soc.h @@ -0,0 +1,225 @@ +#ifndef __AR6K_SOC_H__ +#define __AR6K_SOC_H__ + +//#include "hw/apb_map.h" +//#include "hw/rtc_reg.h" +//#include "hw/mbox_reg.h" + +/* + * Basic types, appropriate for both + * the 32-bit MIPS core on AR6000 and + * the 32-bit XTensa core on AR6002 + */ +typedef signed char A_CHAR; +typedef signed char A_INT8; +typedef unsigned char A_UINT8; +typedef unsigned char A_UCHAR; +typedef short A_INT16; +typedef unsigned short A_UINT16; +typedef int A_INT32; +typedef unsigned int A_UINT32; +typedef long long A_INT64; +typedef unsigned long long A_UINT64; +typedef int A_BOOL; +typedef unsigned int ULONG; +typedef ULONG A_ULONG; +typedef A_ULONG A_ADDR; + +#if 0 +//#include "targaddrs.h" + +/* + * Some platform-specific macros and constants that may needed + * outside of the BSP. + */ + +/* + * AR6001/MIPS uses a cache line size of 16 Bytes. + * AR6002/Xtensa has no caches; but existing code assumes + * that this constant is non-zero. To avoid code complexity + * and possibly subtle bugs we define a bogus cache + * line size for Xtensa that matches MIPs'. + */ +#define A_CACHE_LINE_SIZE 16 + +#if defined(AR6001) +#define A_MIPS_KSEG_UNCACHED 0xa0000000 +#define A_MIPS_KSEG_CACHED 0x80000000 +#define A_MIPS_KSEG_MASK 0xe0000000 + +/* + * Convert a cached virtual address or a CPU physical address into + * an uncached virtual address. + */ +#define A_UNCACHED_ADDR(addr) \ + ((void *)(((A_UINT32)(addr)) | A_MIPS_KSEG_UNCACHED)) + +/* + * Convert an uncached or CPU physical address into + * a cached virtual address. + */ +#define A_CACHED_ADDR(addr) \ + ((void *)((((A_UINT32)(addr)) & ~A_MIPS_KSEG_MASK) | A_MIPS_KSEG_CACHED)) + +/* Read/Write a 32-bit AR6000 SOC register, specified by its physical address */ +#define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr))) + +#define A_SOC_ADDR_WRITE(addr, val) \ + do { \ + (*((volatile A_UINT32 *)A_UNCACHED_ADDR(addr))) = (A_UINT32)(val); \ + } while (0) + +#define A_RTC_REG_READ(addr) A_SOC_ADDR_READ(addr) +#define A_MC_REG_READ(addr) A_SOC_ADDR_READ(addr) +#define A_UART_REG_READ(addr) A_SOC_ADDR_READ(addr) +#define A_SI_REG_READ(addr) A_SOC_ADDR_READ(addr) +#define A_GPIO_REG_READ(addr) A_SOC_ADDR_READ(addr) +#define A_MBOX_REG_READ(addr) A_SOC_ADDR_READ(addr) +#define A_WMAC_REG_READ(addr) A_SOC_ADDR_READ(addr) +#define A_ANALOG_REG_READ(addr) A_SOC_ADDR_READ(addr) + +#define A_RTC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) +#define A_MC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) +#define A_UART_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) +#define A_SI_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) +#define A_GPIO_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) +#define A_MBOX_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) +#define A_WMAC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) +#define A_ANALOG_REG_WRITE(addr, val) A_SOC_ADDR_WRITE((addr), (val)) +#endif + +#if defined(AR6002) +#define A_UNCACHED_ADDR(addr) (addr) +#define A_CACHED_ADDR(addr) (addr) + +#define A_SOC_ADDR_READ(addr) (*((volatile A_UINT32 *)(addr))) + +#define A_SOC_ADDR_WRITE(addr, val) \ + do { \ + (*((volatile A_UINT32 *)(addr))) = (A_UINT32)(val); \ + } while (0) + +#define A_RTC_REG_READ(addr) A_SOC_ADDR_READ(RTC_BASE_ADDRESS|(A_UINT32)(addr)) +#define A_MC_REG_READ(addr) A_SOC_ADDR_READ(VMC_BASE_ADDRESS|(A_UINT32)(addr)) +#define A_UART_REG_READ(addr) A_SOC_ADDR_READ(UART_BASE_ADDRESS|(A_UINT32)(addr)) +#define A_SI_REG_READ(addr) A_SOC_ADDR_READ(SI_BASE_ADDRESS|(A_UINT32)(addr)) +#define A_GPIO_REG_READ(addr) A_SOC_ADDR_READ(GPIO_BASE_ADDRESS|(A_UINT32)(addr)) +#define A_MBOX_REG_READ(addr) A_SOC_ADDR_READ(MBOX_BASE_ADDRESS|(A_UINT32)(addr)) +#define A_WMAC_REG_READ(addr) A_SOC_ADDR_READ(MAC_BASE_ADDRESS|(A_UINT32)(addr)) +#define A_ANALOG_REG_READ(addr) A_SOC_ADDR_READ(ANALOG_INTF_BASE_ADDRESS|(A_UINT32)(addr)) + +#define A_RTC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(RTC_BASE_ADDRESS|(A_UINT32)(addr), (val)) +#define A_MC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(VMC_BASE_ADDRESS|(A_UINT32)(addr), (val)) +#define A_UART_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(UART_BASE_ADDRESS|(A_UINT32)(addr), (val)) +#define A_SI_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(SI_BASE_ADDRESS|(A_UINT32)(addr), (val)) +#define A_GPIO_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(GPIO_BASE_ADDRESS|(A_UINT32)(addr), (val)) +#define A_MBOX_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(MBOX_BASE_ADDRESS|(A_UINT32)(addr), (val)) +#define A_WMAC_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(MAC_BASE_ADDRESS|(A_UINT32)(addr), (val)) +#define A_ANALOG_REG_WRITE(addr, val) A_SOC_ADDR_WRITE(ANALOG_INTF_BASE_ADDRESS|(A_UINT32)(addr), (val)) + +#endif /* AR6002 */ + +/* + * Sleep/stay awake control. + * It is the caller's responsibility to guarantee atomicity. + */ + +typedef A_UINT32 A_old_sleep_t; + +#define A_SYSTEM_SLEEP_DISABLE(pOldSystemSleep) \ +do { \ + *(pOldSystemSleep) = A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); \ + A_RTC_REG_WRITE(SYSTEM_SLEEP_ADDRESS, \ + *(pOldSystemSleep) | SYSTEM_SLEEP_DISABLE_MASK); \ + (void)A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); /* flush */ \ +} while (0) + +#define A_SYSTEM_SLEEP_RESTORE(OldSystemSleep) \ +do { \ + A_RTC_REG_WRITE(SYSTEM_SLEEP_ADDRESS, (OldSystemSleep)); \ + (void)A_RTC_REG_READ(SYSTEM_SLEEP_ADDRESS); /* flush */ \ +} while (0) + + +/* + * AR6K-specific High Frequency Timestamp support. + * This is intended for use as a performance tool, and + * is not to be used in normal operation. + */ +typedef struct { + A_UINT32 highfreq; /* ~40MHz resolution */ + A_UINT32 lowfreq; /* ~32KHz resolution */ +} A_timestamp_t; + +/* + * Enable HighFrequency timer. + * Normally, we keep this OFF in order to save power. + */ +#define HF_TIMER_CONTROL_START_MASK HF_TIMER_CONTROL_ON_MASK +#define A_TIMESTAMP_ENABLE() \ +do { \ + A_RTC_REG_WRITE(HF_TIMER_ADDRESS, (40000000/32768)<<12); \ + A_RTC_REG_WRITE(HF_TIMER_CONTROL_ADDRESS, \ + HF_TIMER_CONTROL_START_MASK | \ + HF_TIMER_CONTROL_AUTO_RESTART_MASK | \ + HF_TIMER_CONTROL_RESET_MASK); \ +} while (0) + +/* + * Turn it OFF when you're done: + */ +#define A_TIMESTAMP_DISABLE() A_RTC_REG_WRITE(HF_TIMER_CONTROL_ADDRESS, 0) + +/* + * Get a timestamp. It's the caller's responsibility to + * guarantee atomicity of the two reads, if needed. + */ +#define A_TIMESTAMP(pTimestamp) \ + do { \ + (pTimestamp)->highfreq = A_RTC_REG_READ(HF_TIMER_COUNT_ADDRESS); \ + (pTimestamp)->lowfreq = A_RTC_REG_READ(HF_LF_COUNT_ADDRESS); \ + } while (0) + +/* + * Supported reference clock speeds. + * + * Note: MAC HAL code has multiple tables indexed by these values, + * so do not rearrange them. Add any new refclk values at the end. + */ +typedef enum { + AR6K_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */ + AR6K_REFCLK_19_2_MHZ = 0, + AR6K_REFCLK_26_MHZ = 1, + AR6K_REFCLK_40_MHZ = 2, + AR6K_REFCLK_52_MHZ = 3, + AR6K_REFCLK_38_4_MHZ = 4, + AR6K_REFCLK_24_MHZ = 5, +} A_refclk_speed_t; + +#define A_REFCLK_UNKNOWN AR6K_REFCLK_UNKNOWN +#define A_REFCLK_19_2_MHZ AR6K_REFCLK_19_2_MHZ +#define A_REFCLK_26_MHZ AR6K_REFCLK_26_MHZ +#define A_REFCLK_40_MHZ AR6K_REFCLK_40_MHZ +#define A_REFCLK_52_MHZ AR6K_REFCLK_52_MHZ +#define A_REFCLK_38_4_MHZ AR6K_REFCLK_38_4_MHZ +#define A_REFCLK_24_MHZ AR6K_REFCLK_24_MHZ + +/* System defaults to 2.4GHz settings */ +#define A_BAND_DEFAULT A_BAND_24GHZ + +#if defined(AR6001) +#define FLASH_ADDR(n) AR6000_FLASH_ADDR(n) +#endif + +#if defined(AR6002) +#define HOST_INTEREST ((struct host_interest_s *)AR6002_HOST_INTEREST_ADDRESS) +#else +#define HOST_INTEREST ((struct host_interest_s *)AR6001_HOST_INTEREST_ADDRESS) +#endif + +#define AR6K_OPTION_TEST(option) \ + (A_MBOX_REG_READ(LOCAL_SCRATCH_ADDRESS) & (option)) + +#endif + +#endif /* __AR6K_SOC_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_nbuf.h b/target_firmware/magpie_fw_dev/target/inc/adf_nbuf.h new file mode 100755 index 0000000..5ef7d7f --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_nbuf.h @@ -0,0 +1,645 @@ +/* (c) Copyright 2002 - 2008 Atheros Communications Inc. */ + +/** + * @defgroup adf_nbuf_public network buffer API + */ + +/** + * @ingroup adf_nbuf_public + * @file adf_nbuf.h + * This file defines the network buffer abstraction. + */ + +#ifndef _ADF_NBUF_H +#define _ADF_NBUF_H + +#include +#include +#include +#include +#include + +/** + * @brief Platform indepedent packet abstraction + */ +typedef __adf_nbuf_t adf_nbuf_t; + +/** + * @brief invalid handle + */ +#define ADF_NBUF_NULL __ADF_NBUF_NULL +/** + * @brief Platform independent packet queue abstraction + */ +typedef __adf_nbuf_queue_t adf_nbuf_queue_t; + +/** + * BUS/DMA mapping routines + */ + +/** + * @brief Create a DMA map. This can later be used to map + * networking buffers. They : + * - need space in adf_drv's software descriptor + * - are typically created during adf_drv_create + * - need to be created before any API(adf_nbuf_map) that uses them + * + * @param[in] osdev os device + * @param[out] dmap map handle + * + * @return status of the operation + */ +static inline a_status_t +adf_nbuf_dmamap_create(adf_os_device_t osdev, + adf_os_dma_map_t *dmap) +{ + return (__adf_nbuf_dmamap_create(osdev, dmap)); +} + + +/** + * @brief Delete a dmap map + * + * @param[in] osdev os device + * @param[in] dmap + */ +static inline void +adf_nbuf_dmamap_destroy(adf_os_device_t osdev, adf_os_dma_map_t dmap) +{ + __adf_nbuf_dmamap_destroy(osdev, dmap); +} + + +/** + * @brief Map a buffer to local bus address space + * + * @param[in] osdev os device + * @param[in] bmap map handle + * @param[in] buf buf to be mapped + * @param[in] dir DMA direction + * + * @return status of the operation + */ +static inline a_status_t +adf_nbuf_map(adf_os_device_t osdev, + adf_os_dma_map_t bmap, + adf_nbuf_t buf, + adf_os_dma_dir_t dir) +{ + return __adf_nbuf_map(osdev, bmap, buf, dir); +} + + +/** + * @brief Unmap a previously mapped buf + * + * @param[in] osdev os device + * @param[in] bmap map handle + * @param[in] dir DMA direction + */ +static inline void +adf_nbuf_unmap(adf_os_device_t osdev, + adf_os_dma_map_t bmap, + adf_os_dma_dir_t dir) +{ + __adf_nbuf_unmap(osdev, bmap, dir); +} + +/** + * @brief returns information about the mapped buf + * + * @param[in] bmap map handle + * @param[out] sg map info + */ +static inline void +adf_nbuf_dmamap_info(adf_os_dma_map_t bmap, adf_os_dmamap_info_t *sg) +{ + __adf_nbuf_dmamap_info(bmap, sg); +} + + + +/* + * nbuf allocation rouines + */ + + +/** + * @brief Allocate adf_nbuf + * + * The nbuf created is guarenteed to have only 1 physical segment + * + * @param[in] hdl platform device object + * @param[in] size data buffer size for this adf_nbuf including max header + * size + * @param[in] reserve headroom to start with. + * @param[in] align alignment for the start buffer. + * + * @return The new adf_nbuf instance or NULL if there's not enough memory. + */ +static inline adf_nbuf_t +adf_nbuf_alloc(adf_os_size_t size, + int reserve, + int align) +{ + return __adf_nbuf_alloc(size, reserve,align); +} + + +/** + * @brief Free adf_nbuf + * + * @param[in] buf buffer to free + */ +static inline void +adf_nbuf_free(adf_nbuf_t buf) +{ + __adf_nbuf_free(buf); +} + + +/** + * @brief Reallocate such that there's required headroom in + * buf. Note that this can allocate a new buffer, or + * change geometry of the orignial buffer. The new buffer + * is returned in the (new_buf). + * + * @param[in] buf (older buffer) + * @param[in] headroom + * + * @return newly allocated buffer + */ +static inline adf_nbuf_t +adf_nbuf_realloc_headroom(adf_nbuf_t buf, a_uint32_t headroom) +{ + return (__adf_nbuf_realloc_headroom(buf, headroom)); +} + + +/** + * @brief expand the tailroom to the new tailroom, but the buffer + * remains the same + * + * @param[in] buf buffer + * @param[in] tailroom new tailroom + * + * @return expanded buffer or NULL on failure + */ +static inline adf_nbuf_t +adf_nbuf_realloc_tailroom(adf_nbuf_t buf, a_uint32_t tailroom) +{ + return (__adf_nbuf_realloc_tailroom(buf, tailroom)); +} + + +/** + * @brief this will expand both tail & head room for a given + * buffer, you may or may not get a new buffer.Use it + * only when its required to expand both. Otherwise use + * realloc (head/tail) will solve the purpose. Reason for + * having an extra API is that some OS do this in more + * optimized way, rather than calling realloc (head/tail) + * back to back. + * + * @param[in] buf buffer + * @param[in] headroom new headroom + * @param[in] tailroom new tailroom + * + * @return expanded buffer + */ +static inline adf_nbuf_t +adf_nbuf_expand(adf_nbuf_t buf, a_uint32_t headroom, a_uint32_t tailroom) +{ + return (__adf_nbuf_expand(buf,headroom,tailroom)); +} + + +/** + * @brief Copy src buffer into dst. This API is useful, for + * example, because most native buffer provide a way to + * copy a chain into a single buffer. Therefore as a side + * effect, it also "linearizes" a buffer (which is + * perhaps why you'll use it mostly). It creates a + * writeable copy. + * + * @param[in] buf source nbuf to copy from + * + * @return the new nbuf + */ +static inline adf_nbuf_t +adf_nbuf_copy(adf_nbuf_t buf) +{ + return(__adf_nbuf_copy(buf)); +} + + +/** + * @brief link two nbufs, the new buf is piggybacked into the + * older one. + * + * @param[in] dst buffer to piggyback into + * @param[in] src buffer to put + * + * @return status of the call + */ +static inline void +adf_nbuf_cat(adf_nbuf_t dst,adf_nbuf_t src) +{ + __adf_nbuf_cat(dst, src); +} + + +/** + * @brief clone the nbuf (copy is readonly) + * + * @param[in] buf nbuf to clone from + * + * @return cloned buffer + */ +static inline adf_nbuf_t +adf_nbuf_clone(adf_nbuf_t buf) +{ + return(__adf_nbuf_clone(buf)); +} + + +/** + * @brief Create a version of the specified nbuf whose + * contents can be safely modified without affecting + * other users.If the nbuf is a clone then this function + * creates a new copy of the data. If the buffer is not + * a clone the original buffer is returned. + * + * @param[in] buf source nbuf to create a writable copy from + * + * @return new buffer which is writeable + */ +static inline adf_nbuf_t +adf_nbuf_unshare(adf_nbuf_t buf) +{ + return(__adf_nbuf_unshare(buf)); +} + + + +/* + * nbuf manipulation routines + */ + + + +/** + * @brief return the amount of headroom int the current nbuf + * + * @param[in] buf buffer + * + * @return amount of head room + */ +static inline a_uint32_t +adf_nbuf_headroom(adf_nbuf_t buf) +{ + return (__adf_nbuf_headroom(buf)); +} + + +/** + * @brief return the amount of tail space available + * + * @param[in] buf buffer + * + * @return amount of tail room + */ +static inline a_uint32_t +adf_nbuf_tailroom(adf_nbuf_t buf) +{ + return (__adf_nbuf_tailroom(buf)); +} + + +/** + * @brief Push data in the front + * + * @param[in] buf buf instance + * @param[in] size size to be pushed + * + * @return New data pointer of this buf after data has been pushed, + * or NULL if there is not enough room in this buf. + */ +static inline a_uint8_t * +adf_nbuf_push_head(adf_nbuf_t buf, adf_os_size_t size) +{ + return __adf_nbuf_push_head(buf, size); +} + + +/** + * @brief Puts data in the end + * + * @param[in] buf buf instance + * @param[in] size size to be pushed + * + * @return data pointer of this buf where new data has to be + * put, or NULL if there is not enough room in this buf. + */ +static inline a_uint8_t * +adf_nbuf_put_tail(adf_nbuf_t buf, adf_os_size_t size) +{ + return __adf_nbuf_put_tail(buf, size); +} + + +/** + * @brief pull data out from the front + * + * @param[in] buf buf instance + * @param[in] size size to be popped + * + * @return New data pointer of this buf after data has been popped, + * or NULL if there is not sufficient data to pull. + */ +static inline a_uint8_t * +adf_nbuf_pull_head(adf_nbuf_t buf, adf_os_size_t size) +{ + return __adf_nbuf_pull_head(buf, size); +} + + +/** + * + * @brief trim data out from the end + * + * @param[in] buf buf instance + * @param[in] size size to be popped + * + * @return none + */ +static inline void +adf_nbuf_trim_tail(adf_nbuf_t buf, adf_os_size_t size) +{ + __adf_nbuf_trim_tail(buf, size); +} + + +/** + * @brief Get the length of the buf + * + * @param[in] buf the buf instance + * + * @return The total length of this buf. + */ +static inline adf_os_size_t +adf_nbuf_len(adf_nbuf_t buf) +{ + return (__adf_nbuf_len(buf)); +} + +/** + * @brief test whether the nbuf is cloned or not + * + * @param[in] buf buffer + * + * @return TRUE if it is cloned, else FALSE + */ +static inline a_bool_t +adf_nbuf_is_cloned(adf_nbuf_t buf) +{ + return (__adf_nbuf_is_cloned(buf)); +} + + + +/* + * nbuf frag routines + */ + +/** + * @brief return the frag pointer & length of the frag + * + * @param[in] buf buffer + * @param[out] sg this will return all the frags of the nbuf + * + */ +static inline void +adf_nbuf_frag_info(adf_nbuf_t buf, adf_os_sglist_t *sg) +{ + __adf_nbuf_frag_info(buf, sg); +} +/** + * @brief return the data pointer & length of the header + * + * @param[in] buf nbuf + * @param[out] addr data pointer + * @param[out] len length of the data + * + */ +static inline void +adf_nbuf_peek_header(adf_nbuf_t buf, a_uint8_t **addr, a_uint32_t *len) +{ + __adf_nbuf_peek_header(buf, addr, len); +} +/* + * nbuf private context routines + */ + +/** + * @brief get the priv pointer from the nbuf'f private space + * + * @param[in] buf + * + * @return data pointer to typecast into your priv structure + */ +static inline a_uint8_t * +adf_nbuf_get_priv(adf_nbuf_t buf) +{ + return (__adf_nbuf_get_priv(buf)); +} + + +/* + * nbuf queue routines + */ + + +/** + * @brief Initialize buf queue + * + * @param[in] head buf queue head + */ +static inline void +adf_nbuf_queue_init(adf_nbuf_queue_t *head) +{ + __adf_nbuf_queue_init(head); +} + + +/** + * @brief Append a nbuf to the tail of the buf queue + * + * @param[in] head buf queue head + * @param[in] buf buf + */ +static inline void +adf_nbuf_queue_add(adf_nbuf_queue_t *head, adf_nbuf_t buf) +{ + __adf_nbuf_queue_add(head, buf); +} + + +/** + * @brief Retrieve a buf from the head of the buf queue + * + * @param[in] head buf queue head + * + * @return The head buf in the buf queue. + */ +static inline adf_nbuf_t +adf_nbuf_queue_remove(adf_nbuf_queue_t *head) +{ + return __adf_nbuf_queue_remove(head); +} + + +/** + * @brief get the length of the queue + * + * @param[in] head buf queue head + * + * @return length of the queue + */ +static inline a_uint32_t +adf_nbuf_queue_len(adf_nbuf_queue_t *head) +{ + return __adf_nbuf_queue_len(head); +} + + +/** + * @brief get the first guy/packet in the queue + * + * @param[in] head buf queue head + * + * @return first buffer in queue + */ +static inline adf_nbuf_t +adf_nbuf_queue_first(adf_nbuf_queue_t *head) +{ + return (__adf_nbuf_queue_first(head)); +} + + +/** + * @brief get the next guy/packet of the given buffer (or + * packet) + * + * @param[in] buf buffer + * + * @return next buffer/packet + */ +static inline adf_nbuf_t +adf_nbuf_queue_next(adf_nbuf_t buf) +{ + return (__adf_nbuf_queue_next(buf)); +} + + +/** + * @brief Check if the buf queue is empty + * + * @param[in] nbq buf queue handle + * + * @return TRUE if queue is empty + * @return FALSE if queue is not emty + */ +static inline a_bool_t +adf_nbuf_is_queue_empty(adf_nbuf_queue_t * nbq) +{ + return __adf_nbuf_is_queue_empty(nbq); +} + + + +/* + * nbuf extension routines XXX + */ + + + +/** + * @brief Gets the tx checksumming to be performed on this buf + * + * @param[in] buf buffer + * @param[out] hdr_off the (tcp) header start + * @param[out] where the checksum offset + */ +static inline adf_net_cksum_type_t +adf_nbuf_tx_cksum_info(adf_nbuf_t buf, a_uint8_t **hdr_off, a_uint8_t **where) +{ + return(__adf_nbuf_tx_cksum_info(buf, hdr_off, where)); +} + + +/** + * @brief Drivers that support hw checksumming use this to + * indicate checksum info to the stack. + * + * @param[in] buf buffer + * @param[in] cksum checksum + */ +static inline void +adf_nbuf_set_rx_cksum(adf_nbuf_t buf, adf_nbuf_rx_cksum_t *cksum) +{ + __adf_nbuf_set_rx_cksum(buf, cksum); +} + + +/** + * @brief Drivers that are capable of TCP Large segment offload + * use this to get the offload info out of an buf. + * + * @param[in] buf buffer + * @param[out] tso offload info + */ +static inline void +adf_nbuf_get_tso_info(adf_nbuf_t buf, adf_nbuf_tso_t *tso) +{ + __adf_nbuf_get_tso_info(buf, tso); +} + + +/*static inline void +adf_nbuf_set_vlan_info(adf_nbuf_t buf, adf_net_vlan_tag_t vlan_tag) +{ + __adf_nbuf_set_vlan_info(buf, vlan_tag); +}*/ + +/** + * @brief This function extracts the vid & priority from an + * nbuf + * + * + * @param[in] hdl net handle + * @param[in] buf buffer + * @param[in] vlan vlan header + * + * @return status of the operation + */ +static inline a_status_t +adf_nbuf_get_vlan_info(adf_net_handle_t hdl, adf_nbuf_t buf, + adf_net_vlanhdr_t *vlan) +{ + return __adf_nbuf_get_vlan_info(hdl, buf, vlan); +} + +static inline adf_nbuf_t +adf_nbuf_create_frm_frag(adf_nbuf_queue_t *head) +{ + return __adf_nbuf_create_frm_frag(head); +} + +static inline void +adf_nbuf_split_to_frag(adf_nbuf_t buf, adf_nbuf_queue_t *qhead) +{ + return __adf_nbuf_split_to_frag(buf, qhead); +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_net.h b/target_firmware/magpie_fw_dev/target/inc/adf_net.h new file mode 100755 index 0000000..bfa2230 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_net.h @@ -0,0 +1,445 @@ +/** + * @defgroup adf_net_public network abstraction API + */ + +/** + * @ingroup adf_net_public + * @file adf_net.h + * These APIs abstract the OS networking stack from a driver. + */ + +/** + * @mainpage + * @section Introduction + * The Atheros Driver Framework provides a mechanism to run the Atheros + * WLAN driver on a variety of Operating Systems and Platforms. It achieves + * this by abstracting all OS-specific and platform-specific functionality + * the driver requires. This ensures the core logic in the driver is OS- + * and platform-independent. + * @section Modules + * The driver framework consists of three main components: + * @subsection sec1 Network Stack + * This component abstracts the OS network stack. See @ref adf_net_public for details. + * @subsection sec2 Network Buffer + * This component abstracts the OS network buffer. See @ref adf_nbuf_public for details. + * @subsection sec3 OS services + * This component abstracts any OS services. See @ref adf_os_public for details. + */ + +#ifndef _ADF_NET_H +#define _ADF_NET_H + +#include +#include +#include "adf_net_types.h" +#include "adf_net_wcmd.h" +#include +#include + +/* + * check for a NULL handle + * */ +#define ADF_NET_NULL __ADF_NET_NULL + +/** + * @brief this register the driver to the shim, but won't get + * any handle until create device is called. + * + * @param[in] drv driver info structure + * + * @return status of operation + */ +static inline a_status_t +adf_net_register_drv(adf_drv_info_t *drv) +{ + return(__adf_net_register_drv(drv)); +} + + +/** + * @brief deregister the driver from the shim + * + * @param[in] name driver name passed in adf_drv_info_t + * + * @see adf_net_register_drv() + */ +static inline void +adf_net_unregister_drv(a_uint8_t *drv_name) +{ + __adf_net_unregister_drv(drv_name); +} + + +/** + * @brief register a real device with the kernel + * + * @param[in] hdl driver handle for this device + * @param[in] op per-device switch structure + * @param[in] info basic device information + * + * @return opaque device handle + */ +static inline adf_net_handle_t +adf_net_dev_create(adf_drv_handle_t hdl, + adf_dev_sw_t *op, + adf_net_dev_info_t *info) +{ + return (__adf_net_dev_create(hdl, op, info)); +} + + +/** + * @brief unregister a real device with the kernel + * + * @param[in] hdl opaque device handle returned by adf_net_dev_create() + * @see adf_net_dev_create() + */ +static inline void +adf_net_dev_delete(adf_net_handle_t hdl) +{ + __adf_net_dev_delete(hdl); +} + + +/** + * @brief register a virtual device with the kernel. + * A virtual device is always backed by a real device. + * + * @param[in] dev_hdl opaque device handle for the real device + * @param[in] hdl driver handle for this virtual device + * @param[in] op per-virtual-device switch structure + * @param[in] info basic virtual device information + * + * @return opaque device handle + * + * @see adf_net_dev_create() + */ +static inline adf_net_handle_t +adf_net_vdev_create(adf_net_handle_t dev_hdl, + adf_drv_handle_t hdl, + adf_vdev_sw_t *op, + adf_net_dev_info_t *info) +{ + return (__adf_net_vdev_create(dev_hdl, hdl, op, info)); +} + + +/** + * @brief unregister the virtual device with the kernel. + * + * @param[in] hdl opaque device handle returned by adf_net_vdev_create() + * + * @see adf_net_vdev_create() + */ +static inline void +adf_net_vdev_delete(adf_net_handle_t hdl) +{ + __adf_net_vdev_delete(hdl); +} + + +/** + * @brief open the real device + * + * @param[in] hdl opaque device handle + * + * @return status of the operation + * + * @see adf_net_dev_create() + */ +static inline a_status_t +adf_net_dev_open(adf_net_handle_t hdl) +{ + return (__adf_net_dev_open(hdl)); +} + + +/** + * @brief close the real device + * + * @param[in] hdl opaque device handle + * + * @see adf_net_dev_open() + */ +static inline void +adf_net_dev_close(adf_net_handle_t hdl) +{ + __adf_net_dev_close(hdl); +} + + +/** + * @brief transmit a network buffer using a device + * + * @param[in] hdl opaque device handle + * @param[in] pkt network buffer to transmit + * + * @return status of the operation + */ +static inline a_status_t +adf_net_dev_tx(adf_net_handle_t hdl, adf_nbuf_t pkt) +{ + return (__adf_net_dev_tx(hdl,pkt)); +} + + +/** + * @brief Checks if the interface is running or not + * + * @param[in] hdl opaque device handle + * + * @return true if running, false if not + */ +static inline a_bool_t +adf_net_is_running(adf_net_handle_t hdl) +{ + return (__adf_net_is_running(hdl)); +} + +/** + * @brief Checks if the interface is up or not + * + * @param[in] hdl opaque device handle + * + * @return true if up, false if not + */ +static inline a_bool_t +adf_net_is_up(adf_net_handle_t hdl) +{ + return (__adf_net_is_up(hdl)); +} + + +/** + * @brief check whether the carrier is available or not + * + * @param[in] hdl opaque device handle + * + * @return a_bool_t true if available, false if not + */ +static inline a_bool_t +adf_net_carrier_ok(adf_net_handle_t hdl) +{ + return(__adf_net_carrier_ok(hdl)); +} + + +/** + * @brief inform the networking stack that the link is down + * + * @param[in] hdl opaque device handle + */ +static inline void +adf_net_carrier_off(adf_net_handle_t hdl) +{ + __adf_net_carrier_off(hdl); +} + + +/** + * @brief inform the networking stack that the link is up + * + * @param[in] hdl opaque device handle + * + * @see adf_net_carrier_off() + */ +static inline void +adf_net_carrier_on(adf_net_handle_t hdl) +{ + __adf_net_carrier_on(hdl); +} + + +/* + * Queue mgmt. + * driver will use these to keep the native networking stack abreast of its + * resource (descriptor) situation. + */ + +/** + * @brief inform the networking stack that the device is ready to receive + * transmit packets. Typically called during init. + * + * @param[in] hdl opaque device handle + */ +static inline void +adf_net_start_queue(adf_net_handle_t hdl) +{ + __adf_net_start_queue(hdl); +} + +/** + * @brief inform the networking stack to stop sending transmit packets. + * Typically called if the driver runs out of resources for the device. + * + * @param[in] hdl opaque device handle + */ +static inline void +adf_net_stop_queue(adf_net_handle_t hdl) +{ + __adf_net_stop_queue(hdl); +} + + +/** + * @brief inform the native stack to resume sending packets + * to transmit.Typically called when the driver has resources + * available again for the device. + * + * @note adf_net_wake_queue() is the counterpart of adf_net_stop_queue() + * + * @param[in] hdl opaque device handle + */ +static inline void +adf_net_wake_queue(adf_net_handle_t hdl) +{ + __adf_net_wake_queue(hdl); +} + + +/** + * @brief Check the state of the queue + * + * @param[in] hdl opaque device handle + * + * @return true if stopped, false if not + */ +static inline a_bool_t +adf_net_queue_stopped(adf_net_handle_t hdl) +{ + return(__adf_net_queue_stopped(hdl)); +} + + +/** + * @brief This indicates a packet to the networking stack + * (minus the FCS). The driver should just strip + * the FCS and give the packet as a whole. This is + * necessary because different native stacks have + * different expectation of how they want to recv the + * packet. This fucntion will strip off whatever is + * required for the OS interface. The routine will also + * figure out whether its being called in irq context and + * call the appropriate OS API. + * + * @param[in] hdl opaque device handle + * @param[in] pkt network buffer to indicate + * @param[in] len length of buffer + */ +static inline void +adf_net_indicate_packet(adf_net_handle_t hdl, adf_nbuf_t pkt, a_uint32_t len) +{ + __adf_net_indicate_packet(hdl, pkt, len); +} + +/** + * @brief use this when indicating a vlan tagged packet on RX + * + * @param[in] hdl opaque device handle + * @param[in] pkt network buffer to indicate + * @param[in] len length of buffer + * @param[in] vid vlan id + * + * @return status of operation + */ +static inline a_status_t +adf_net_indicate_vlanpkt(adf_net_handle_t hdl, adf_nbuf_t pkt, + a_uint32_t len, adf_net_vid_t *vid) +{ + return (__adf_net_indicate_vlanpkt(hdl, pkt, len, vid)); +} + +/** + * @brief get interface name + * + * @param[in] hdl opaque device handle + * + * @return name of interface + */ +static inline const a_uint8_t * +adf_net_ifname(adf_net_handle_t hdl) +{ + return (__adf_net_ifname(hdl)); +} + +/** + * @brief send management packets to apps (listener). + * This is used for wireless applications. + * + * @param[in] hdl opaque device handle + * @param[in] pkt network buffer to send + * @param[in] len length of buffer + */ +static inline void +adf_net_fw_mgmt_to_app(adf_net_handle_t hdl, adf_nbuf_t pkt, a_uint32_t len) +{ + __adf_net_fw_mgmt_to_app(hdl, pkt, len); +} +/** + * @brief send wireless events to listening applications + * + * @param[in] hdl opaque device handle + * @param[in] what event to send + * @param[in] data information about event + * @param[in] data_len length of accompanying information + */ +static inline void +adf_net_send_wireless_event(adf_net_handle_t hdl, + adf_net_wireless_event_t what, + void *data, adf_os_size_t data_len) +{ + __adf_net_send_wireless_event(hdl, what, data, data_len); +} + +/** + * @brief schedule the poll controller. + * + * @param[in] hdl opaque device handle + */ +static inline void +adf_net_poll_schedule(adf_net_handle_t hdl) +{ + __adf_net_poll_schedule(hdl); +} + + +/** + * @brief per cpu deffered callback (e.g. for RSS) + * + * @param[in] hdl opaque device handle + * @param[in] cpu_msk + * @param[in] arg + */ +static inline void +adf_net_poll_schedule_cpu(adf_net_handle_t hdl, a_uint32_t cpu_msk, void *arg) +{ + __adf_net_poll_schedule_cpu(hdl, cpu_msk, arg); +} + +/** + * @brief Get OS Handle from OS device object. + * + * @param[in] osdev OS device object + * + * @return OS handle + */ +static inline adf_os_handle_t +adf_net_dev_to_os(adf_os_device_t osdev) +{ + return __adf_net_dev_to_os(osdev); +} + +/** + * @brief Get OS Handle from OS net handle. + * + * @param[in] osdev OS net handle + * + * @return OS handle + */ +static inline adf_os_handle_t +adf_net_hdl_to_os(adf_net_handle_t hdl) +{ + return __adf_net_hdl_to_os(hdl); +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_net_sw.h b/target_firmware/magpie_fw_dev/target/inc/adf_net_sw.h new file mode 100755 index 0000000..00e7eab --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_net_sw.h @@ -0,0 +1,108 @@ +/** + * @ingroup adf_net_public + * @file adf_net_sw.h + * This file defines the device and virtual device switch tables. + */ + +#ifndef __ADF_NET_SW_H +#define __ADF_NET_SW_H + + +/** + * @brief per device switch structure + */ +typedef struct _adf_dev_sw{ + /** + * @brief Handler for device open - mandatory interface + */ + a_status_t (*drv_open) (adf_drv_handle_t hdl); + /** + * @brief Handler for device close - mandatory interface + */ + void (*drv_close) (adf_drv_handle_t hdl); + /** + * @brief Handler for transmit - mandatory interface + */ + a_status_t (*drv_tx) (adf_drv_handle_t hdl, adf_nbuf_t pkt); + /** + * @brief Handler for configuration command - mandatory interface + */ + a_status_t (*drv_cmd) (adf_drv_handle_t hdl, adf_net_cmd_t cmd, + adf_net_cmd_data_t *data); + /** + * @brief Handler for ioctl - mandatory interface + */ + a_status_t (*drv_ioctl) (adf_drv_handle_t hdl, int num, + void *data); + /** + * @brief Handler for transmission timeout - mandatory interface + */ + a_status_t (*drv_tx_timeout)(adf_drv_handle_t hdl); + /** + * @brief Handler for wireless configuration - optional interface + */ + a_status_t (*drv_wcmd) (adf_drv_handle_t hdl, adf_net_wcmd_type_t cmd, + adf_net_wcmd_data_t *data); + /** + * @brief Handler for polling if polling/deferred processing required - + * optional interface + */ + adf_net_poll_resp_t (*drv_poll) (adf_drv_handle_t hdl, int quota, + int *work_done); + /** + * @brief Handler for per cpu deffered callback (e.g. for RSS) - optional + * interface + */ + adf_net_poll_resp_t (*drv_poll_cpu) (adf_drv_handle_t hdl, int quota, + int *work_done, void *arg); + /** + * @brief Handler for disabling receive interrupts for polling. + * adf_drv should do proper locking - these are not called in atomic context + */ + void (*drv_poll_int_disable)(adf_drv_handle_t hdl); + /** + * @brief Handler for enabling receive interrupts for polling. + * adf_drv should do proper locking - these are not called in atomic context + */ + void (*drv_poll_int_enable) (adf_drv_handle_t hdl); + +}adf_dev_sw_t; + +/** + * @brief Virtual device switch structure + */ +typedef struct _adf_vdev_sw{ + /** + * @brief Handler for device open + */ + a_status_t (*drv_open) (adf_drv_handle_t hdl); + /** + * @brief Handler for device close + */ + void (*drv_close) (adf_drv_handle_t hdl); + /** + * @brief Handler for transmit + */ + a_status_t (*drv_tx) (adf_drv_handle_t hdl, adf_nbuf_t pkt); + /** + * @brief Handler for configuration command + */ + a_status_t (*drv_cmd) (adf_drv_handle_t hdl, adf_net_cmd_t cmd, + adf_net_cmd_data_t *data); + /** + * @brief Handler for wireless configuration + */ + a_status_t (*drv_wcmd) (adf_drv_handle_t hdl, adf_net_wcmd_type_t cmd, + adf_net_wcmd_data_t *data); + /** + * @brief Handler for transmission timeout + */ + a_status_t (*drv_tx_timeout) (adf_drv_handle_t hdl); + /** + * @brief Handler for ioctl + */ + a_status_t (*drv_ioctl) (adf_drv_handle_t hdl, int num, void *data); +}adf_vdev_sw_t; + +#endif + diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_net_types.h b/target_firmware/magpie_fw_dev/target/inc/adf_net_types.h new file mode 100755 index 0000000..459d084 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_net_types.h @@ -0,0 +1,341 @@ +/** + * @ingroup adf_net_public + * @file adf_net_types.h + * This file defines types used in the networking stack abstraction. + */ + +#ifndef _ADF_NET_TYPES_H +#define _ADF_NET_TYPES_H + + + +/** + * @brief These control/get info from the device + */ +#define ADF_NET_CMD(_x) \ + ADF_NET_CMD_GET_##_x, \ + ADF_NET_CMD_SET_##_x + +/** + * @brief Get/Set commands from anet to adf_drv + */ +typedef enum { + ADF_NET_CMD(LINK_INFO), + ADF_NET_CMD(POLL_INFO), + ADF_NET_CMD(CKSUM_INFO), + ADF_NET_CMD(RING_INFO), + ADF_NET_CMD(MAC_ADDR), + ADF_NET_CMD(MTU), + ADF_NET_CMD_GET_DMA_INFO, + ADF_NET_CMD_GET_OFFLOAD_CAP, + ADF_NET_CMD_GET_STATS, + ADF_NET_CMD_ADD_VID, + ADF_NET_CMD_DEL_VID, + ADF_NET_CMD_SET_MCAST, + ADF_NET_CMD_GET_MCAST_CAP +}adf_net_cmd_t; + + + +/** + * @brief Indicates what features are supported by the interface. + */ +#define ADF_NET_LINK_SUPP_10baseT_Half (1 << 0) +#define ADF_NET_LINK_SUPP_10baseT_Full (1 << 1) +#define ADF_NET_LINK_SUPP_100baseT_Half (1 << 2) +#define ADF_NET_LINK_SUPP_100baseT_Full (1 << 3) +#define ADF_NET_LINK_SUPP_1000baseT_Half (1 << 4) +#define ADF_NET_LINK_SUPP_1000baseT_Full (1 << 5) +#define ADF_NET_LINK_SUPP_Autoneg (1 << 6) +#define ADF_NET_LINK_SUPP_Pause (1 << 7) +#define ADF_NET_LINK_SUPP_Asym_Pause (1 << 8) + +#define ADF_NET_LINK_SUPP_100 (ADF_NET_LINK_SUPP_10baseT_Half | \ + ADF_NET_LINK_SUPP_10baseT_Full | \ + ADF_NET_LINK_SUPP_100baseT_Half | \ + ADF_NET_LINK_SUPP_100baseT_Full) + +#define ADF_NET_LINK_SUPP_1000 (ADF_NET_LINK_SUPP_100 | \ + ADF_NET_LINK_SUPP_1000baseT_Full) + +/** + * @brief Indicates what features are advertised by the interface. + */ +#define ADF_NET_LINK_ADV_10baseT_Half (1 << 0) +#define ADF_NET_LINK_ADV_10baseT_Full (1 << 1) +#define ADF_NET_LINK_ADV_100baseT_Half (1 << 2) +#define ADF_NET_LINK_ADV_100baseT_Full (1 << 3) +#define ADF_NET_LINK_ADV_1000baseT_Half (1 << 4) +#define ADF_NET_LINK_ADV_1000baseT_Full (1 << 5) +#define ADF_NET_LINK_ADV_Autoneg (1 << 6) +#define ADF_NET_LINK_ADV_Pause (1 << 7) +#define ADF_NET_LINK_ADV_Asym_Pause (1 << 8) + +#define ADF_NET_LINK_ADV_100 (ADF_NET_LINK_ADV_10baseT_Half | \ + ADF_NET_LINK_ADV_10baseT_Full | \ + ADF_NET_LINK_ADV_100baseT_Half | \ + ADF_NET_LINK_ADV_100baseT_Full) + +#define ADF_NET_LINK_ADV_1000 (ADF_NET_LINK_ADV_100 | \ + ADF_NET_LINK_ADV_1000baseT_Full) + +/** + * @brief The forced/current speed/duplex/autoneg + */ +#define ADF_NET_LINK_SPEED_10 10 +#define ADF_NET_LINK_SPEED_100 100 +#define ADF_NET_LINK_SPEED_1000 1000 + +#define ADF_NET_LINK_DUPLEX_HALF 0x00 +#define ADF_NET_LINK_DUPLEX_FULL 0x01 + +#define ADF_NET_LINK_AUTONEG_DISABLE 0x00 +#define ADF_NET_LINK_AUTONEG_ENABLE 0x01 + +#define ADF_NET_MAC_ADDR_MAX_LEN 6 +#define ADF_NET_IF_NAME_SIZE 64 +#define ADF_NET_ETH_LEN ADF_NET_MAC_ADDR_MAX_LEN +#define ADF_NET_MAX_MCAST_ADDR 128 + +/** + * @brief link info capability/parameters for the device + * Note the flags below + */ +typedef struct { + a_uint32_t supported; /*RO Features this if supports*/ + a_uint32_t advertized; /*Features this interface advertizes*/ + a_int16_t speed; /*Force speed 10M, 100M, gigE*/ + a_int8_t duplex; /*duplex full or half*/ + a_uint8_t autoneg; /*Enabled/disable autoneg*/ +}adf_net_cmd_link_info_t; + +typedef struct adf_net_ethaddr{ + a_uint8_t addr[ADF_NET_ETH_LEN]; +} adf_net_ethaddr_t; +typedef struct { + a_uint8_t ether_dhost[ADF_NET_ETH_LEN]; /* destination eth addr */ + a_uint8_t ether_shost[ADF_NET_ETH_LEN]; /* source ether addr */ + a_uint16_t ether_type; /* packet type ID field */ +}adf_net_ethhdr_t; + +typedef struct { +#if defined (ADF_LITTLE_ENDIAN_MACHINE) + a_uint8_t ip_hl:4, + ip_version:4; +#elif defined (ADF_BIG_ENDIAN_MACHINE) + a_uint8_t ip_version:4, + ip_hl:4; +#else +#error "Please fix" +#endif + a_uint8_t ip_tos; + + a_uint16_t ip_len; + a_uint16_t ip_id; + a_uint16_t ip_frag_off; + a_uint8_t ip_ttl; + a_uint8_t ip_proto; + a_uint16_t ip_check; + a_uint32_t ip_saddr; + a_uint32_t ip_daddr; + /*The options start here. */ + }adf_net_iphdr_t; + +/** + * @brief Vlan header + */ +typedef struct adf_net_vlanhdr{ + a_uint16_t tpid; +#if defined (ADF_LITTLE_ENDIAN_MACHINE) + a_uint16_t vid:12; /* Vlan id*/ + a_uint8_t cfi:1; /* reserved for CFI, don't use*/ + a_uint8_t prio:3; /* Priority*/ +#elif defined (ADF_BIG_ENDIAN_MACHINE) + a_uint8_t prio:3; /* Priority*/ + a_uint8_t cfi:1; /* reserved for CFI, don't use*/ + a_uint16_t vid:12; /* Vlan id*/ +#else +#error "Please fix" +#endif +}adf_net_vlanhdr_t; + +typedef struct adf_net_vid{ +#if defined (ADF_LITTLE_ENDIAN_MACHINE) + a_uint16_t val:12; + a_uint8_t res:4; +#elif defined (ADF_BIG_ENDIAN_MACHINE) + a_uint8_t res:4; + a_uint16_t val:12; +#else +#error "Please fix" +#endif +}adf_net_vid_t; + + +/** + * @brief Command for setting ring paramters. + */ +typedef struct { + a_uint32_t rx_bufsize; /*Ro field. For shim's that maintain a pool*/ + a_uint32_t rx_ndesc; + a_uint32_t tx_ndesc; +}adf_net_cmd_ring_info_t; + +/** + * @brief Whether the interface is polled or not. If so, the polling bias (number of + * packets it wants to process per invocation + */ +typedef struct { + a_bool_t polled; + a_uint32_t poll_wt; +}adf_net_cmd_poll_info_t; + +/** + * @brief Basic device info + */ +typedef struct { + a_uint8_t if_name[ADF_NET_IF_NAME_SIZE]; + a_uint8_t dev_addr[ADF_NET_MAC_ADDR_MAX_LEN]; +}adf_net_dev_info_t; + +typedef struct adf_dma_info { + adf_os_dma_mask_t dma_mask; + a_uint32_t sg_nsegs; /**< scatter segments */ +}adf_net_cmd_dma_info_t; + +/** + * @brief Defines the TX and RX checksumming capabilities/state of the device + * The actual checksum handling happens on an adf_nbuf + * If offload capability command not supported, all offloads are assumed to be + * none. + */ +typedef enum { + ADF_NET_CKSUM_NONE, /*Cannot do any checksum*/ + ADF_NET_CKSUM_TCP_UDP_IPv4, /*tcp/udp on ipv4 with pseudo hdr*/ + ADF_NET_CKSUM_TCP_UDP_IPv6, /*tcp/udp on ipv6*/ +}adf_net_cksum_type_t; + +typedef struct { + adf_net_cksum_type_t tx_cksum; + adf_net_cksum_type_t rx_cksum; +}adf_net_cksum_info_t; + +typedef adf_net_cksum_info_t adf_net_cmd_cksum_info_t; /*XXX needed?*/ + +/** + * @brief Command for set/unset vid + */ +typedef a_uint16_t adf_net_cmd_vid_t ; /*get/set vlan id*/ + +typedef enum { + ADF_NET_TSO_NONE, + ADF_NET_TSO_IPV4, /**< for tsp ipv4 only*/ + ADF_NET_TSO_ALL, /**< ip4 & ipv6*/ +}adf_net_tso_type_t; + +/** + * @brief Command for getting offloading capabilities of a device + */ +typedef struct { + adf_net_cksum_info_t cksum_cap; + adf_net_tso_type_t tso; + a_uint8_t vlan_supported; +}adf_net_cmd_offload_cap_t; + +/** + * @brief Command for getting general stats from a device + */ +typedef struct { + a_uint32_t tx_packets; /**< total packets transmitted*/ + a_uint32_t rx_packets; /**< total packets recieved*/ + a_uint32_t tx_bytes; /**< total bytes transmitted*/ + a_uint32_t rx_bytes; /**< total bytes recieved*/ + a_uint32_t tx_dropped; /**< total tx dropped because of lack of buffers*/ + a_uint32_t rx_dropped; /**< total rx dropped because of lack of buffers*/ + a_uint32_t rx_errors; /**< bad packet recieved*/ + a_uint32_t tx_errors; /**< transmisison problems*/ +}adf_net_cmd_stats_t; + +typedef enum adf_net_cmd_mcast_cap{ + ADF_NET_MCAST_SUP=0, + ADF_NET_MCAST_NOTSUP +}adf_net_cmd_mcast_cap_t; + +typedef struct adf_net_cmd_mcaddr{ + a_uint32_t nelem; /**< No. of mcast addresses*/ + adf_net_ethaddr_t mcast[ADF_NET_MAX_MCAST_ADDR]; +}adf_net_cmd_mcaddr_t; + +typedef union { + adf_net_cmd_link_info_t link_info; + adf_net_cmd_poll_info_t poll_info; + adf_net_cmd_cksum_info_t cksum_info; + adf_net_cmd_ring_info_t ring_info; + adf_net_cmd_dma_info_t dma_info; + adf_net_cmd_vid_t vid; + adf_net_cmd_offload_cap_t offload_cap; + adf_net_cmd_stats_t stats; + adf_net_cmd_mcaddr_t mcast_info; + adf_net_cmd_mcast_cap_t mcast_cap; +}adf_net_cmd_data_t; + +/** + * @brief For polled devices, adf_drv responds with one of the following status in + * its poll function. + */ +typedef enum { + ADF_NET_POLL_DONE, + ADF_NET_POLL_NOT_DONE, + ADF_NET_POLL_OOM, +}adf_net_poll_resp_t; + +/** + * @brief For recieve checksum API + */ +typedef enum { + ADF_NBUF_RX_CKSUM_NONE, /*device failed to ckecksum*/ + ADF_NBUF_RX_CKSUM_HW, /*checksum successful and value returned*/ + ADF_NBUF_RX_CKSUM_UNNECESSARY, /*cksum successful, no value*/ +}adf_nbuf_rx_cksum_type_t; + +typedef struct { + adf_nbuf_rx_cksum_type_t result; + a_uint32_t val; +}adf_nbuf_rx_cksum_t; + +/** + * @brief For TCP large Segment Offload + */ +typedef struct { + adf_net_tso_type_t type; + a_uint16_t mss; + a_uint8_t hdr_off; +}adf_nbuf_tso_t; + +/** + * @brief Wireless events + * ADF_IEEE80211_ASSOC = station associate (bss mode) + * ADF_IEEE80211_REASSOC = station re-associate (bss mode) + * ADF_IEEE80211_DISASSOC = station disassociate (bss mode) + * ADF_IEEE80211_JOIN = station join (ap mode) + * ADF_IEEE80211_LEAVE = station leave (ap mode) + * ADF_IEEE80211_SCAN = scan complete, results available + * ADF_IEEE80211_REPLAY = sequence counter replay detected + * ADF_IEEE80211_MICHAEL = Michael MIC failure detected + * ADF_IEEE80211_REJOIN = station re-associate (ap mode) + * ADF_CUSTOM_PUSH_BUTTON = + */ +typedef enum adf_net_wireless_events{ + ADF_IEEE80211_ASSOC = __ADF_IEEE80211_ASSOC, + ADF_IEEE80211_REASSOC = __ADF_IEEE80211_REASSOC, + ADF_IEEE80211_DISASSOC = __ADF_IEEE80211_DISASSOC, + ADF_IEEE80211_JOIN = __ADF_IEEE80211_JOIN, + ADF_IEEE80211_LEAVE = __ADF_IEEE80211_LEAVE, + ADF_IEEE80211_SCAN = __ADF_IEEE80211_SCAN, + ADF_IEEE80211_REPLAY = __ADF_IEEE80211_REPLAY, + ADF_IEEE80211_MICHAEL = __ADF_IEEE80211_MICHAEL, + ADF_IEEE80211_REJOIN = __ADF_IEEE80211_REJOIN, + ADF_CUSTOM_PUSH_BUTTON = __ADF_CUSTOM_PUSH_BUTTON +}adf_net_wireless_event_t; + +#endif /*_ADF_NET_TYPES_H*/ diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_net_wcmd.h b/target_firmware/magpie_fw_dev/target/inc/adf_net_wcmd.h new file mode 100755 index 0000000..a2070c3 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_net_wcmd.h @@ -0,0 +1,1489 @@ +/** + * Copyright (c) Atheros Communications Inc. 2002-2008 + * + */ + +#ifndef __ADF_NET_WCMD_H +#define __ADF_NET_WCMD_H + +#include +#include +#include + + + +/** + * Defines + */ +#define ADF_NET_WCMD_NAME_SIZE __ADF_OS_NAME_SIZE +#define ADF_NET_WCMD_NICK_NAME 32 /**< Max Device nick name size*/ +#define ADF_NET_WCMD_MODE_NAME_LEN 6 +#define ADF_NET_WCMD_IE_MAXLEN 256 /** Max Len for IE */ + +#define ADF_NET_WCMD_MAX_BITRATES 32 +#define ADF_NET_WCMD_MAX_ENC_SZ 8 +#define ADF_NET_WCMD_MAX_FREQ 32 +#define ADF_NET_WCMD_MAX_TXPOWER 8 +#define ADF_NET_WCMD_EVENT_CAP 6 + +/** + * @brief key set/get info + */ +#define ADF_NET_WCMD_KEYBUF_SIZE 16 +#define ADF_NET_WCMD_MICBUF_SIZE 16/**< space for tx+rx keys */ +#define ADF_NET_WCMD_KEY_DEFAULT 0x80/**< default xmit key */ +#define ADF_NET_WCMD_ADDR_LEN 6 +#define ADF_NET_WCMD_KEYDATA_SZ \ + (ADF_NET_WCMD_KEYBUF_SIZE + ADF_NET_WCMD_MICBUF_SIZE) +/** + * @brief key flags + * XXX: enum's + */ +#define ADF_NET_WCMD_VAPKEY_XMIT 0x01/**< xmit */ +#define ADF_NET_WCMD_VAPKEY_RECV 0x02/**< recv */ +#define ADF_NET_WCMD_VAPKEY_GROUP 0x04/**< WPA group*/ +#define ADF_NET_WCMD_VAPKEY_SWCRYPT 0x10/**< Encrypt/decrypt*/ +#define ADF_NET_WCMD_VAPKEY_SWMIC 0x20/**< Enmic/Demic */ +#define ADF_NET_WCMD_VAPKEY_DEFAULT 0x80/**< Default key */ + +#define ADF_NET_WCMD_MAX_SSID 32 +#define ADF_NET_WCMD_CHAN_BYTES 32 + +#define ADF_NET_WCMD_RTS_DEFAULT 512 +#define ADF_NET_WCMD_RTS_MIN 1 +#define ADF_NET_WCMD_RTS_MAX 2346 + +#define ADF_NET_WCMD_FRAG_MIN 256 +#define ADF_NET_WCMD_FRAG_MAX 2346 +/** + * @brief Maximum number of address that you may get in the + * list of access ponts + */ +#define ADF_NET_WCMD_MAX_AP 64 + +#define ADF_NET_WCMD_RATE_MAXSIZE 30 +#define ADF_NET_WCMD_NUM_TR_ENTS 128 +/** + * @brief Ethtool specific + */ +#define ADF_NET_WCMD_BUSINFO_LEN 32 +#define ADF_NET_WCMD_DRIVSIZ 32 +#define ADF_NET_WCMD_VERSIZ 32 +#define ADF_NET_WCMD_FIRMSIZ 32 +/** + * *******************************Enums****************** + */ +typedef enum adf_net_wcmd_vapmode{ + ADF_NET_WCMD_VAPMODE_AUTO, /**< Driver default*/ + ADF_NET_WCMD_VAPMODE_ADHOC, /**< Single cell*/ + ADF_NET_WCMD_VAPMODE_INFRA, /**< Multi Cell or Roaming*/ + ADF_NET_WCMD_VAPMODE_MASTER, /**< Access Point*/ + ADF_NET_WCMD_VAPMODE_REPEAT, /**< Wireless Repeater*/ + ADF_NET_WCMD_VAPMODE_SECOND, /**< Secondary master or repeater*/ + ADF_NET_WCMD_VAPMODE_MONITOR /**< Passive Monitor*/ +}adf_net_wcmd_vapmode_t; +/** + * @brief key type + */ +typedef enum adf_net_wcmd_ciphermode{ + ADF_NET_WCMD_CIPHERMODE_WEP, + ADF_NET_WCMD_CIPHERMODE_TKIP, + ADF_NET_WCMD_CIPHERMODE_AES_OCB, + ADF_NET_WCMD_CIPHERMODE_AES_CCM , + ADF_NET_WCMD_CIPHERMODE_RESERVE, + ADF_NET_WCMD_CIPHERMODE_CKIP, + ADF_NET_WCMD_CIPHERMODE_NONE +}adf_net_wcmd_ciphermode_t; +/** + * @brief Get/Set wireless commands + */ +typedef enum adf_net_wcmd_type{ + /* net80211 */ + ADF_NET_WCMD_GET_RTS_THRES, + ADF_NET_WCMD_SET_RTS_THRES, + ADF_NET_WCMD_GET_FRAGMENT, + ADF_NET_WCMD_SET_FRAGMENT, + ADF_NET_WCMD_GET_VAPMODE, + ADF_NET_WCMD_SET_VAPMODE, + ADF_NET_WCMD_GET_BSSID, + ADF_NET_WCMD_SET_BSSID, + ADF_NET_WCMD_GET_NICKNAME, + ADF_NET_WCMD_SET_NICKNAME, + ADF_NET_WCMD_GET_FREQUENCY, + ADF_NET_WCMD_SET_FREQUENCY, + ADF_NET_WCMD_GET_ESSID, + ADF_NET_WCMD_SET_ESSID, + ADF_NET_WCMD_GET_TX_POWER, + ADF_NET_WCMD_SET_TX_POWER, + ADF_NET_WCMD_GET_PARAM, + ADF_NET_WCMD_SET_PARAM, + ADF_NET_WCMD_GET_OPT_IE, + ADF_NET_WCMD_SET_OPT_IE, + ADF_NET_WCMD_GET_APP_IE_BUF, + ADF_NET_WCMD_SET_APP_IE_BUF, + ADF_NET_WCMD_SET_ENC, + ADF_NET_WCMD_GET_KEY, + ADF_NET_WCMD_SET_KEY, + ADF_NET_WCMD_GET_SCAN, + ADF_NET_WCMD_SET_SCAN, + ADF_NET_WCMD_GET_MODE, + ADF_NET_WCMD_SET_MODE, + ADF_NET_WCMD_GET_CHAN_LIST, + ADF_NET_WCMD_SET_CHAN_LIST, + ADF_NET_WCMD_GET_WMM_PARAM, + ADF_NET_WCMD_SET_WMM_PARAM, + ADF_NET_WCMD_GET_VAPNAME, + ADF_NET_WCMD_GET_IC_CAPS, + ADF_NET_WCMD_GET_RETRIES, + ADF_NET_WCMD_GET_WAP_LIST, + ADF_NET_WCMD_GET_ADDBA_STATUS, + ADF_NET_WCMD_GET_CHAN_INFO, + ADF_NET_WCMD_GET_WPA_IE, + ADF_NET_WCMD_GET_WSC_IE, + ADF_NET_WCMD_SET_TXPOWER_LIMIT, + ADF_NET_WCMD_SET_TURBO, + ADF_NET_WCMD_SET_FILTER, + ADF_NET_WCMD_SET_ADDBA_RESPONSE, + ADF_NET_WCMD_SET_MLME, + ADF_NET_WCMD_SET_SEND_ADDBA, + ADF_NET_WCMD_SET_SEND_DELBA, + ADF_NET_WCMD_SET_DELKEY, + ADF_NET_WCMD_SET_DELMAC, + ADF_NET_WCMD_SET_ADD_MAC, + ADF_NET_WCMD_GET_RANGE, + ADF_NET_WCMD_GET_POWER, + ADF_NET_WCMD_SET_POWER, + ADF_NET_WCMD_GET_DEVSTATS, + ADF_NET_WCMD_SET_MTU, + ADF_NET_WCMD_SET_SYSCTL, + ADF_NET_WCMD_GET_STA_STATS,/* stats_sta */ + ADF_NET_WCMD_GET_VAP_STATS, /* stats_vap */ + ADF_NET_WCMD_GET_STATION_LIST, /* station */ + /* Device specific */ + ADF_NET_WCMD_SET_DEV_VAP_CREATE, + ADF_NET_WCMD_SET_DEV_TX_TIMEOUT, /* XXX:No data definition */ + ADF_NET_WCMD_SET_DEV_MODE_INIT, /* XXX:No data definition */ + ADF_NET_WCMD_GET_DEV_STATUS, + ADF_NET_WCMD_GET_DEV_STATUS_CLR, /* XXX:No data definition */ + ADF_NET_WCMD_GET_DEV_DIALOG, + ADF_NET_WCMD_GET_DEV_PHYERR, + ADF_NET_WCMD_GET_DEV_CWM, + ADF_NET_WCMD_GET_DEV_ETHTOOL, + ADF_NET_WCMD_SET_DEV_MAC, + ADF_NET_WCMD_SET_DEV_CAP,/*ATH_CAP*/ + /* Device write specific */ + ADF_NET_WCMD_SET_DEV_EIFS_MASK, + ADF_NET_WCMD_SET_DEV_EIFS_DUR, + ADF_NET_WCMD_SET_DEV_SLOTTIME, + ADF_NET_WCMD_SET_DEV_ACKTIMEOUT, + ADF_NET_WCMD_SET_DEV_CTSTIMEOUT, + ADF_NET_WCMD_SET_DEV_SOFTLED, + ADF_NET_WCMD_SET_DEV_LEDPIN, + ADF_NET_WCMD_SET_DEV_DEBUG, + ADF_NET_WCMD_SET_DEV_TXANTENNA, + ADF_NET_WCMD_SET_DEV_RXANTENNA, + ADF_NET_WCMD_SET_DEV_DIVERSITY, + ADF_NET_WCMD_SET_DEV_TXINTRPERIOD, + ADF_NET_WCMD_SET_DEV_FFTXQMIN, + ADF_NET_WCMD_SET_DEV_TKIPMIC, + ADF_NET_WCMD_SET_DEV_GLOBALTXTIMEOUT, + ADF_NET_WCMD_SET_DEV_SW_WSC_BUTTON, + /* Device read specific */ + ADF_NET_WCMD_GET_DEV_EIFS_MASK, + ADF_NET_WCMD_GET_DEV_EIFS_DUR, + ADF_NET_WCMD_GET_DEV_SLOTTIME, + ADF_NET_WCMD_GET_DEV_ACKTIMEOUT, + ADF_NET_WCMD_GET_DEV_CTSTIMEOUT, + ADF_NET_WCMD_GET_DEV_SOFTLED, + ADF_NET_WCMD_GET_DEV_LEDPIN, + ADF_NET_WCMD_GET_DEV_COUNTRYCODE, + ADF_NET_WCMD_GET_DEV_REGDOMAIN, + ADF_NET_WCMD_GET_DEV_DEBUG, + ADF_NET_WCMD_GET_DEV_TXANTENNA, + ADF_NET_WCMD_GET_DEV_RXANTENNA, + ADF_NET_WCMD_GET_DEV_DIVERSITY, + ADF_NET_WCMD_GET_DEV_TXINTRPERIOD, + ADF_NET_WCMD_GET_DEV_FFTXQMIN, + ADF_NET_WCMD_GET_DEV_TKIPMIC, + ADF_NET_WCMD_GET_DEV_GLOBALTXTIMEOUT, + ADF_NET_WCMD_GET_DEV_SW_WSC_BUTTON +}adf_net_wcmd_type_t; +/** + * @brief Opmodes for the VAP + */ +typedef enum adf_net_wcmd_opmode{ + ADF_NET_WCMD_OPMODE_IBSS,/**< IBSS (adhoc) station */ + ADF_NET_WCMD_OPMODE_STA,/**< Infrastructure station */ + ADF_NET_WCMD_OPMODE_WDS,/**< WDS link */ + ADF_NET_WCMD_OPMODE_AHDEMO,/**< Old lucent compatible adhoc demo */ + ADF_NET_WCMD_OPMODE_RESERVE0,/** +/** + * @brief Atomic type of variable. + * Use this when you want a simple resource counter etc. which is atomic + * across multiple CPU's. These maybe slower than usual counters on some + * platforms/OS'es, so use them with caution. + */ +typedef __adf_os_atomic_t adf_os_atomic_t; + +/** + * @brief Initialize an atomic type variable + * @param[in] v a pointer to an opaque atomic variable + */ +static inline void +adf_os_atomic_init(adf_os_atomic_t *v) +{ + __adf_os_atomic_init(v); +} + +/** + * @brief Read the value of an atomic variable. + * @param[in] v a pointer to an opaque atomic variable + * + * @return the current value of the variable + */ +static inline a_uint32_t +adf_os_atomic_read(adf_os_atomic_t *v) +{ + return (__adf_os_atomic_read(v)); +} + +/** + * @brief Increment the value of an atomic variable. + * @param[in] v a pointer to an opaque atomic variable + */ +static inline void +adf_os_atomic_inc(adf_os_atomic_t *v) +{ + return (__adf_os_atomic_inc(v)); +} + +/** + * @brief Decrement the value of an atomic variable. + * @param v a pointer to an opaque atomic variable + */ +static inline void +adf_os_atomic_dec(adf_os_atomic_t *v) +{ + return (__adf_os_atomic_dec(v)); +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_bitops.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_bitops.h new file mode 100755 index 0000000..d132eed --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_bitops.h @@ -0,0 +1,199 @@ +/** + * @ingroup adf_os_public + * @file adf_os_bitops.h + * This file abstracts bit-level operations on a stream of bytes. + */ + +#ifndef _ADF_OS_BITOPS_H +#define _ADF_OS_BITOPS_H + +#include + +/** + * @brief Set a bit atomically + * @param[in] nr Bit to change + * @param[in] addr Address to start counting from + * + * @note its atomic and cannot be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_set_bit_a(a_uint32_t nr, volatile a_uint32_t *addr) +{ + __adf_os_set_bit_a(nr, addr); +} + +/** + * @brief Set a bit + * @param[in] nr Bit to change + * @param[in] addr Address to start counting from + * + * @note its not atomic and can be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_set_bit(a_uint32_t nr, volatile a_uint32_t *addr) +{ + __adf_os_set_bit(nr, addr); +} + +/** + * @brief Clear a bit atomically + * @param[in] nr Bit to change + * @param[in] addr Address to start counting from + * + * @note its atomic and cannot be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_clear_bit_a(a_uint32_t nr, volatile a_uint32_t *addr) +{ + __adf_os_clear_bit_a(nr, addr); +} + +/** + * @brief Clear a bit + * @param[in] nr Bit to change + * @param[in] addr Address to start counting from + * + * @note its not atomic and can be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_clear_bit(a_uint32_t nr, volatile a_uint32_t *addr) +{ + __adf_os_clear_bit(nr, addr); +} + +/** + * @brief Toggle a bit atomically + * @param[in] nr Bit to change + * @param[in] addr Address to start counting from + * + * @note its atomic and cannot be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_change_bit_a(a_uint32_t nr, volatile a_uint32_t *addr) +{ + __adf_os_change_bit_a(nr, addr); +} + +/** + * @brief Toggle a bit + * @param[in] nr Bit to change + * @param[in] addr Address to start counting from + * + * @note its not atomic and can be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_change_bit(a_uint32_t nr, volatile a_uint32_t *addr) +{ + __adf_os_change_bit(nr, addr); +} + +/** + * @brief Test and Set a bit atomically + * @param[in] nr Bit to set + * @param[in] addr Address to start counting from + * + * @note its atomic and cannot be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_test_and_set_bit_a(a_uint32_t nr, + volatile a_uint32_t *addr) +{ + __adf_os_test_and_set_bit_a(nr, addr); +} + +/** + * @brief Test and Set a bit + * @param[in] nr Bit to set + * @param[in] addr Address to start counting from + * + * @note its not atomic and can be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_test_and_set_bit(a_uint32_t nr, + volatile a_uint32_t *addr) +{ + __adf_os_test_and_set_bit(nr, addr); +} + +/** + * @brief Test and clear a bit atomically + * @param[in] nr Bit to set + * @param[in] addr Address to start counting from + * + * @note its atomic and cannot be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_test_and_clear_bit_a(a_uint32_t nr, + volatile a_uint32_t *addr) +{ + __adf_os_test_and_clear_bit_a(nr, addr); +} + +/** + * @brief Test and clear a bit + * @param[in] nr Bit to set + * @param[in] addr Address to start counting from + * + * @note its not atomic and can be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_test_and_clear_bit(a_uint32_t nr, + volatile a_uint32_t *addr) +{ + __adf_os_test_and_clear_bit(nr, addr); +} + +/** + * @brief Test and change a bit atomically + * @param[in] nr Bit to set + * @param[in] addr Address to start counting from + * + * @note its atomic and cannot be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_test_and_change_bit_a(a_uint32_t nr, + volatile a_uint32_t *addr) +{ + __adf_os_test_and_change_bit_a(nr, addr); +} + +/** + * @brief Test and clear a bit + * @param[in] nr Bit to set + * @param[in] addr Address to start counting from + * + * @note its not atomic and can be re-ordered. + * Note that nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void adf_os_test_and_change_bit(a_uint32_t nr, + volatile a_uint32_t *addr) +{ + __adf_os_test_and_change_bit(nr, addr); +} + +/** + * @brief test_bit - Determine whether a bit is set + * @param[in] nr bit number to test + * @param[in] addr Address to start counting from + * + * @return 1 if set, 0 if not + */ +static inline int adf_os_test_bit(a_uint32_t nr, volatile a_uint32_t *addr) +{ + __adf_os_test_bit(nr, addr); +} + + +#endif /**_AOD_BITOPS_H*/ diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_crypto.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_crypto.h new file mode 100755 index 0000000..273e63c --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_crypto.h @@ -0,0 +1,76 @@ +/** + * @ingroup adf_os_public + * @file adf_os_crypto.h + * This file defines crypto APIs + */ + +#ifndef __ADF_OS_CRYPTO_H +#define __ADF_OS_CRYPTO_H + +#include + +/** + * @brief Representation of a cipher context. + */ +typedef __adf_os_cipher_t adf_os_cipher_t; + +/** + * @brief Types of crypto algorithms + */ +typedef enum adf_os_crypto_alg{ + ADF_OS_CRYPTO_AES = __ADF_OS_CRYPTO_AES, + ADF_OS_CRYPTO_OTHER = __ADF_OS_CRYPTO_OTHER, +}adf_os_crypto_alg_t; + + +/** + * @brief allocate the cipher context + * @param[in] type crypto algorithm + * + * @return the new cipher context + */ +static inline adf_os_cipher_t +adf_os_crypto_alloc_cipher(adf_os_crypto_alg_t type) +{ + return __adf_os_crypto_alloc_cipher(type); +} + +/** + * @brief free the cipher context + * + * @param[in] cipher cipher context + */ +static inline void +adf_os_crypto_free_cipher(adf_os_cipher_t cipher) +{ + __adf_os_crypto_free_cipher(cipher); +} + +/** + * @brief set the key for cipher context with length keylen + * + * @param[in] cipher cipher context + * @param[in] key key material + * @param[in] keylen length of key material + * + * @return a_uint32_t + */ +static inline a_uint32_t +adf_os_crypto_cipher_setkey(adf_os_cipher_t cipher, const a_uint8_t *key, a_uint8_t keylen) +{ + return __adf_os_crypto_cipher_setkey(cipher, key, keylen); +} + +/** + * @brief encrypt the data with AES + * + * @param[in] cipher cipher context + * @param[in] src unencrypted data + * @param[out] dst encrypted data + */ +static inline void +adf_os_crypto_rijndael_encrypt(adf_os_cipher_t cipher, const void *src, void *dst) +{ + __adf_os_crypto_rijndael_encrypt(cipher, src, dst); +} +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_defer.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_defer.h new file mode 100755 index 0000000..20d40d5 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_defer.h @@ -0,0 +1,126 @@ +/** + * @ingroup adf_os_public + * @file adf_os_defer.h + * This file abstracts deferred execution contexts. + */ + +#ifndef __ADF_OS_DEFER_H +#define __ADF_OS_DEFER_H + +#include +#include + +/** + * TODO This implements work queues (worker threads, kernel threads etc.). + * Note that there is no cancel on a scheduled work. You cannot free a work + * item if its queued. You cannot know if a work item is queued or not unless + * its running, whence you know its not queued. + * + * so if, say, a module is asked to unload itself, how exactly will it make + * sure that the work's not queued, for OS'es that dont provide such a + * mechanism?? + */ + +/** + * @brief Representation of a work queue. + */ +typedef __adf_os_work_t adf_os_work_t; + +/** + * @brief Representation of a bottom half. + */ +typedef __adf_os_bh_t adf_os_bh_t; + + + +/** + * @brief This initiallizes the Bottom half deferred handler + * + * @param[in] hdl OS handle + * @param[in] bh bottom instance + * @param[in] func deferred function to run at bottom half interrupt + * context. + * @param[in] arg argument for the deferred function + */ +static inline void +adf_os_init_bh(adf_os_handle_t hdl, adf_os_bh_t *bh, + adf_os_defer_fn_t func,void *arg) +{ + __adf_os_init_bh(hdl, bh, func, arg); +} + + +/** + * @brief schedule a bottom half (DPC) + * + * @param[in] hdl OS handle + * @param[in] bh bottom instance + */ +static inline void +adf_os_sched_bh(adf_os_handle_t hdl, adf_os_bh_t *bh) +{ + __adf_os_sched_bh(hdl, bh); +} + +/** + * @brief disable the bh (synchronous) + * + * @param[in] hdl OS handle + * @param[in] bh bottom instance + */ +static inline void +adf_os_disable_bh(adf_os_handle_t hdl, adf_os_bh_t *bh) +{ + __adf_os_disable_bh(hdl,bh); +} + +/*********************Non-Interrupt Context deferred Execution***************/ + +/** + * @brief allocate a work/task queue, This runs in non-interrupt + * context, so can be preempted by H/W & S/W intr + * + * @param[in] hdl OS handle + * @param[in] work work instance + * @param[in] func deferred function to run at bottom half non-interrupt + * context. + * @param[in] arg argument for the deferred function + */ +static inline void +adf_os_init_work(adf_os_handle_t hdl, adf_os_work_t *work, + adf_os_defer_fn_t func, void *arg) +{ + __adf_os_init_work(hdl, work, func, arg); +} + +/** + * @brief Schedule a deferred task on non-interrupt context + * + * @param[in] hdl OS handle + * @param[in] work work instance + */ +static inline void +adf_os_sched_work(adf_os_handle_t hdl, adf_os_work_t *work) +{ + __adf_os_sched_work(hdl, work); +} + +/** + *@brief disable the deferred task (synchronous) + * + *@param[in] hdl OS handle + *@param[in] work work instance + */ +static inline void +adf_os_disable_work(adf_os_handle_t hdl, adf_os_work_t *work) +{ + __adf_os_disable_work(hdl, work); +} + + +/** + * XXX API to specify processor while scheduling a bh => only on vista + */ + + +#endif /*_ADF_OS_DEFER_H*/ diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_dma.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_dma.h new file mode 100755 index 0000000..512ce69 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_dma.h @@ -0,0 +1,94 @@ +/** + * @ingroup adf_os_public + * @file adf_os_dma.h + * This file abstracts DMA operations. + */ + +#ifndef _ADF_OS_DMA_H +#define _ADF_OS_DMA_H + +#include +#include + +/* + * @brief a dma address representation of a platform + */ + +/** + * @brief Allocate a DMA buffer and map it to local bus address space + * + * @param[in] osdev platform device instance + * @param[in] size DMA buffer size + * @param[in] coherent 0 => cached. + * @param[out] dmap opaque coherent memory handle + * + * @return returns the virtual address of the memory + */ +static inline void * +adf_os_dmamem_alloc(adf_os_device_t osdev, + adf_os_size_t size, + a_bool_t coherent, + adf_os_dma_map_t *dmap) +{ + return __adf_os_dmamem_alloc(osdev, size, coherent, dmap); +} + +/** + * @brief Free a previously mapped DMA buffer + * + * @param[in] osdev platform device instance + * @param[in] size DMA buffer size + * @param[in] coherent 0 => cached. + * @param[in] vaddr virtual address of DMA buffer + * @param[in] dmap memory handle + */ +static inline void +adf_os_dmamem_free(adf_os_device_t osdev, + adf_os_size_t size, + a_bool_t coherent, + void *vaddr, + adf_os_dma_map_t dmap) +{ + __adf_os_dmamem_free(osdev, size, coherent, vaddr, dmap); +} + +/** + * @brief given a dmamem map, returns the (bus) address + * + * @param[in] dmap memory handle + * + * @return the (bus) address + */ +static inline adf_os_dma_addr_t +adf_os_dmamem_map2addr(adf_os_dma_map_t dmap) +{ + return(__adf_os_dmamem_map2addr(dmap)); +} + +/** + * @brief Flush and invalidate cache for a given dmamem map + * + * @param[in] osdev platform device instance + * @param[in] dmap mem handle + * @param[in] op op code for sync type, (see @ref adf_os_types.h) + */ +static inline void +adf_os_dmamem_cache_sync(adf_os_device_t osdev, + adf_os_dma_map_t dmap, + adf_os_cache_sync_t op) +{ + __adf_os_dmamem_cache_sync(osdev, dmap, op); +} + +/** + * @brief Get the cpu cache line size + * + * @return The CPU cache line size in bytes. + */ +static inline adf_os_size_t +adf_os_cache_line_size(void) +{ + return __adf_os_cache_line_size(); +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h new file mode 100755 index 0000000..424f8e3 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h @@ -0,0 +1,169 @@ +/** + * @ingroup adf_os_public + * @file adf_os_io.h + * This file abstracts I/O operations. + */ + +#ifndef _ADF_OS_IO_H +#define _ADF_OS_IO_H + +#include + + +/** + * @brief Read an 8-bit register value + * + * @param[in] osdev platform device object + * @param[in] addr register addr + * + * @return An 8-bit register value. + */ +#define adf_os_reg_read8(osdev, addr) __adf_os_reg_read8(osdev, addr) + +/** + * @brief Read a 16-bit register value + * + * @param[in] osdev platform device object + * @param[in] addr register addr + * + * @return A 16-bit register value. + */ +#define adf_os_reg_read16(osdev, addr) __adf_os_reg_read16(osdev, addr) + +/** + * @brief Read a 32-bit register value + * + * @param[in] osdev platform device object + * @param[in] addr register addr + * + * @return A 32-bit register value. + */ +#define adf_os_reg_read32(osdev, addr) __adf_os_reg_read32(osdev, addr) + +/** + * @brief Read a 64-bit register value + * + * @param[in] osdev platform device object + * @param[in] addr register addr + * + * @return A 64-bit register value. + */ +#define adf_os_reg_read64(osdev, addr) __adf_os_reg_read64(osdev, addr) + +/** + * @brief Write an 8-bit value into register + * + * @param[in] osdev platform device object + * @param[in] addr register addr + * @param[in] b the 8-bit value to be written + */ +#define adf_os_reg_write8(osdev, addr, b) __adf_os_reg_write8(osdev, addr, b) + +/** + * @brief Write a 16-bit value into register + * + * @param[in] osdev platform device object + * @param[in] addr register addr + * @param[in] w the 16-bit value to be written + */ +#define adf_os_reg_write16(osdev, addr, w) __adf_os_reg_write16(osdev, addr, w) + +/** + * @brief Write a 32-bit value into register + * + * @param[in] osdev platform device object + * @param[in] addr register addr + * @param[in] l the 32-bit value to be written + */ +#define adf_os_reg_write32(osdev, addr, l) __adf_os_reg_write32(osdev, addr, l) + +/** + * @brief Write a 64-bit value into register + * + * @param[in] osdev platform device object + * @param[in] addr register addr + * @param[in] q the 64-bit value to be written + */ +#define adf_os_reg_write64(osdev, addr, q) __adf_os_reg_write64(osdev, addr, q) + +/** + * @brief Convert a 16-bit value from network byte order to host byte order + */ +#define adf_os_ntohs(x) __adf_os_ntohs(x) + +/** + * @brief Convert a 32-bit value from network byte order to host byte order + */ +#define adf_os_ntohl(x) __adf_os_ntohl(x) + +/** + * @brief Convert a 16-bit value from host byte order to network byte order + */ +#define adf_os_htons(x) __adf_os_htons(x) + +/** + * @brief Convert a 32-bit value from host byte order to network byte order + */ +#define adf_os_htonl(x) __adf_os_htonl(x) + +/** + * @brief Convert a 16-bit value from CPU byte order to big-endian byte order + */ +#define adf_os_cpu_to_be16(x) __adf_os_cpu_to_be16(x) + +/** + * @brief Convert a 32-bit value from CPU byte order to big-endian byte order + */ +#define adf_os_cpu_to_be32(x) __adf_os_cpu_to_be32(x) + +/** + * @brief Convert a 64-bit value from CPU byte order to big-endian byte order + */ +#define adf_os_cpu_to_be64(x) __adf_os_cpu_to_be64(x) + +/** + * @brief Convert a 16-bit value from CPU byte order to little-endian byte order + */ +#define adf_os_cpu_to_le16(x) __adf_os_cpu_to_le16(x) + +/** + * @brief Convert a 32-bit value from CPU byte order to little-endian byte order + */ +#define adf_os_cpu_to_le32(x) __adf_os_cpu_to_le32(x) + +/** + * @brief Convert a 64-bit value from CPU byte order to little-endian byte order + */ +#define adf_os_cpu_to_le64(x) __adf_os_cpu_to_le64(x) + +/** + * @brief Convert a 16-bit value from big-endian byte order to CPU byte order + */ +#define adf_os_be16_to_cpu(x) __adf_os_be16_to_cpu(x) + +/** + * @brief Convert a 32-bit value from big-endian byte order to CPU byte order + */ +#define adf_os_be32_to_cpu(x) __adf_os_be32_to_cpu(x) + +/** + * @brief Convert a 64-bit value from big-endian byte order to CPU byte order + */ +#define adf_os_be64_to_cpu(x) __adf_os_be64_to_cpu(x) + +/** + * @brief Convert a 16-bit value from little-endian byte order to CPU byte order + */ +#define adf_os_le16_to_cpu(x) __adf_os_le16_to_cpu(x) + +/** + * @brief Convert a 32-bit value from little-endian byte order to CPU byte order + */ +#define adf_os_le32_to_cpu(x) __adf_os_le32_to_cpu(x) + +/** + * @brief Convert a 64-bit value from little-endian byte order to CPU byte order + */ +#define adf_os_le64_to_cpu(x) __adf_os_le64_to_cpu(x) + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_irq.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_irq.h new file mode 100755 index 0000000..5bd4baa --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_irq.h @@ -0,0 +1,19 @@ +#ifndef __ADF_OS_IRQ_H +#define __ADF_OS_IRQ_H + +#include +#include + +static inline int +adf_os_setup_intr(adf_os_device_t osdev, adf_os_drv_intr fn) +{ + return __adf_os_setup_intr(osdev, fn); +} + +static inline void +adf_os_free_intr(adf_os_device_t osdev) +{ + __adf_os_free_intr(osdev); +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_lock.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_lock.h new file mode 100755 index 0000000..bf53640 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_lock.h @@ -0,0 +1,134 @@ +/** + * @ingroup adf_os_public + * @file adf_os_lock.h + * This file abstracts locking operations. + */ + +#ifndef _ADF_OS_LOCK_H +#define _ADF_OS_LOCK_H + +#include +#include + +/** + * @brief Platform spinlock object + */ +typedef __adf_os_spinlock_t adf_os_spinlock_t; + +/** + * @brief Platform mutex object + */ +typedef __adf_os_mutex_t adf_os_mutex_t; + +/** + * @brief Initialize a mutex + * + * @param[in] m mutex to initialize + */ +static inline void adf_os_init_mutex(adf_os_mutex_t *m) +{ + __adf_os_init_mutex(m); +} + +/** + * @brief Take the mutex + * + * @param[in] m mutex to take + */ +static inline int adf_os_mutex_acquire(adf_os_mutex_t *m) +{ + return (__adf_os_mutex_acquire(m)); +} + +/** + * @brief Give the mutex + * + * @param[in] m mutex to give + */ +static inline void adf_os_mutex_release(adf_os_mutex_t *m) +{ + __adf_os_mutex_release(m); +} + +/** + * @brief Initialize a spinlock + * + * @param[in] lock spinlock object pointer + */ +static inline void +adf_os_spinlock_init(adf_os_spinlock_t *lock) +{ + __adf_os_spinlock_init(lock); +} + + +/** + * @brief Acquire a spinlock by disabling the interrupts + * + * @param[in] lock spinlock object pointer + * @param[out] flags flags used to hold interrupt state + */ +static inline void +adf_os_spin_lock_irq(adf_os_spinlock_t *lock, a_uint32_t *flags) +{ + __adf_os_spin_lock_irq(lock,flags); +} + + +/** + * @brief Release a spinlock & restore the irq + * + * @param[in] lock spinlock object pointer + * @param[in] flags flags filled in by @ref adf_os_spin_lock_irq + */ +static inline void +adf_os_spin_unlock_irq(adf_os_spinlock_t *lock, a_uint32_t *flags) +{ + __adf_os_spin_unlock_irq(lock,flags); +} + + +/** + * @brief locks the spinlock mutex in soft irq context + * + * @param[in] lock spinlock object pointer + */ +static inline void +adf_os_spin_lock_bh(adf_os_spinlock_t *lock) +{ + __adf_os_spin_lock_bh(lock); +} + + +/** + * @brief unlocks the spinlock mutex in soft irq context + * + * @param[in] lock spinlock object pointer + */ +static inline void +adf_os_spin_unlock_bh(adf_os_spinlock_t *lock) +{ + __adf_os_spin_unlock_bh(lock); +} + + +/** + * @brief Execute the input function with spinlock held and interrupt disabled. + * + * @param[in] hdl OS handle + * @param[in] lock spinlock to be held for the critical region + * @param[in] func critical region function that to be executed + * @param[in] context context of the critical region function + * + * @return Boolean status returned by the critical region function + */ +static inline a_bool_t +adf_os_spinlock_irq_exec(adf_os_handle_t hdl, + adf_os_spinlock_t *lock, + adf_os_irqlocked_func_t func, + void *arg) +{ + return __adf_os_spinlock_irq_exec(hdl, lock, func, arg); +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_mem.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_mem.h new file mode 100755 index 0000000..3b42e95 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_mem.h @@ -0,0 +1,107 @@ +/** + * @ingroup adf_os_public + * @file adf_os_mem.h + * This file abstracts memory operations. + */ + +#ifndef _ADF_OS_MEM_H +#define _ADF_OS_MEM_H + +#include +#include + +/** + * @brief Allocate a memory buffer. Note this call can block. + * + * @param[in] size buffer size + * + * @return Buffer pointer or NULL if there's not enough memory. + */ +static inline void * +adf_os_mem_alloc(adf_os_size_t size) +{ + return __adf_os_mem_alloc(size); +} + +/** + * @brief Free malloc'ed buffer + * + * @param[in] buf buffer pointer allocated by @ref adf_os_mem_alloc + */ +static inline void +adf_os_mem_free(void *buf) +{ + __adf_os_mem_free(buf); +} + +/** + * @brief Move a memory buffer. Overlapping regions are not allowed. + * + * @param[in] dst destination address + * @param[in] src source address + * @param[in] size buffer size + */ +static inline void +adf_os_mem_copy(void *dst, void *src, adf_os_size_t size) +{ + __adf_os_mem_copy(dst, src, size); +} + +/** + * @brief Does a non-destructive copy of memory buffer + * + * @param[in] dst destination address + * @param[in] src source address + * @param[in] size buffer size + */ +static inline void +adf_os_mem_move(void *dst, void *src, adf_os_size_t size) +{ + __adf_os_mem_move(dst,src,size); +} + + +/** + * @brief Fill a memory buffer + * + * @param[in] buf buffer to be filled + * @param[in] b byte to fill + * @param[in] size buffer size + */ +static inline void +adf_os_mem_set(void *buf, a_uint8_t b, adf_os_size_t size) +{ + __adf_os_mem_set(buf, b, size); +} + + +/** + * @brief Zero a memory buffer + * + * @param[in] buf buffer to be zeroed + * @param[in] size buffer size + */ +static inline void +adf_os_mem_zero(void *buf, adf_os_size_t size) +{ + __adf_os_mem_zero(buf, size); +} + + +/** + * @brief Compare two memory buffers + * + * @param[in] buf1 first buffer + * @param[in] buf2 second buffer + * @param[in] size buffer size + * + * @retval 0 equal + * @retval 1 not equal + */ +static inline int +adf_os_mem_cmp(void *buf1, void *buf2, adf_os_size_t size) +{ + return __adf_os_mem_cmp(buf1, buf2, size); +} + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_module.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_module.h new file mode 100755 index 0000000..f17f631 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_module.h @@ -0,0 +1,101 @@ +/** + * @ingroup adf_os_public + * @file adf_os_module.h + * This file abstracts "kernel module" semantics. + */ + +#ifndef _ADF_OS_MODULE_H +#define _ADF_OS_MODULE_H + +#include + +typedef a_status_t (*module_init_func_t)(void); + +/** + * @brief Specify the module's entry point. + */ +#define adf_os_virt_module_init(_mod_init_func) __adf_os_virt_module_init(_mod_init_func) + +/** + * @brief Specify the module's exit point. + */ +#define adf_os_virt_module_exit(_mod_exit_func) __adf_os_virt_module_exit(_mod_exit_func) + +/** + * @brief Specify the module's name. + */ +#define adf_os_virt_module_name(_name) __adf_os_virt_module_name(_name) + +/** + * @brief Specify the module's dependency on another module. + */ +#define adf_os_module_dep(_name,_dep) __adf_os_module_dep(_name,_dep) + +/** + * @brief Export a symbol from a module. + */ +#define adf_os_export_symbol(_sym) __adf_os_export_symbol(_sym) + +/** + * @brief Module parameter of type integer. + */ +#define ADF_OS_PARAM_TYPE_INT32 __ADF_OS_PARAM_TYPE_INT32 + +/** + * @brief Module parameter of type string. + */ +#define ADF_OS_PARAM_TYPE_STRING __ADF_OS_PARAM_TYPE_STRING + +/** + * @brief Declare a module parameter. + * + * @param[in] name name of the parameter + * @param[in] type type of the parameter + * + * @note These provide the config data defined by the userland + * for this device. It can be queried at any time, given the name string + * Only two types are supported + * ADF_OS_PARAM_TYPE_STRING + * ADF_OS_PARAM_TYPE_INT32 + * For example, say, the parameters name "my_int" and "my_name" are of + * variables of type int and string respectively. Then you would declare them + * as follows: + * @code + * adf_os_declare_param(my_int, ADF_OS_PARAM_TYPE_INT32); + * adf_os_declare_param(my_name, ADF_OS_PARAM_TYPE_STRING); + * @endcode + * To read the userland provided config value, you would do something like + * + * @code + * adf_os_read_param(my_name, &softc->sc_my_name); + * @endcode + * + * or + * @code + * st = adf_os_read_param(my_int, &softc->sc_my_int); + * @endcode + * st could be : + * + * A_STATUS_OK + * A_STATUS_ENOMEM + * A_STATUS_ENOENT + * + */ +#define adf_os_declare_param(_name, _type) __adf_os_declare_param(_name, _type) + +/** + * @brief Read a parameter's value + * + * @param[in] osdev os handle + * @param[in] name name of parameter + * @param[in] type type of parameter + * @param[out] val value read + * + * @note pval is a point to the variable. Therefore, + * for strings it is a_uint8_t ** + * for integers it is a_int_t * + */ +#define adf_os_read_param(_osdev, _name, _type, _pval) \ + __adf_os_read_param(_osdev, _name, _type, _pval) + +#endif /*_ADF_OS_MODULE_H*/ diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_pci.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_pci.h new file mode 100755 index 0000000..235b42d --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_pci.h @@ -0,0 +1,118 @@ +/** + * @ingroup adf_os_public + * @file adf_os_pci.h + * This file abstracts the PCI subsystem. + */ +#ifndef __ADF_OS_PCI_H +#define __ADF_OS_PCI_H + +#include + +/** + * @brief Define the entry point for the PCI module. + */ +#define adf_os_pci_module_init(_fn) __adf_os_pci_module_init(_fn) + +/** + * @brief Define the exit point for the PCI module. + */ +#define adf_os_pci_module_exit(_fn) __adf_os_pci_module_exit(_fn) + +/** + * @brief Setup the following driver information: name, PCI IDs of devices + * supported and some device handlers. + */ +#define adf_os_pci_set_drv_info(_name, _pci_ids, _attach, _detach, _suspend, _resume) \ + __adf_os_pci_set_drv_info(_name, _pci_ids, _attach, _detach, _suspend, _resume) + +/** + * @brief Read a byte of PCI config space. + * + * @param[in] osdev platform device instance + * @param[in] offset offset to read + * @param[out] val value read + * + * @return status of operation + */ +static inline int +adf_os_pci_config_read8(adf_os_device_t osdev, int offset, a_uint8_t *val) +{ + return __adf_os_pci_config_read8(osdev, offset, val); +} + +/** + * @brief Write a byte to PCI config space. + * + * @param[in] osdev platform device instance + * @param[in] offset offset to write + * @param[in] val value to write + * + * @return status of operation + */ +static inline int +adf_os_pci_config_write8(adf_os_device_t osdev, int offset, a_uint8_t val) +{ + return __adf_os_pci_config_write8(osdev, offset, val); +} + +/** + * @brief Read 2 bytes of PCI config space. + * + * @param[in] osdev platform device instance + * @param[in] offset offset to read + * @param[out] val value read + * + * @return status of operation + */ +static inline int +adf_os_pci_config_read16(adf_os_device_t osdev, int offset, a_uint16_t *val) +{ + return __adf_os_pci_config_read16(osdev, offset, val); +} + +/** + * @brief Write 2 bytes to PCI config space. + * + * @param[in] osdev platform device instance + * @param[in] offset offset to write + * @param[in] val value to write + * + * @return status of operation + */ +static inline int +adf_os_pci_config_write16(adf_os_device_t osdev, int offset, a_uint16_t val) +{ + return __adf_os_pci_config_write16(osdev, offset, val); +} + +/** + * @brief Read 4 bytes of PCI config space. + * + * @param[in] osdev platform device instance + * @param[in] offset offset to read + * @param[out] val value read + * + * @return status of operation + */ +static inline int +adf_os_pci_config_read32(adf_os_device_t osdev, int offset, a_uint32_t *val) +{ + return __adf_os_pci_config_read32(osdev, offset, val); +} + +/** + * @brief Write 4 bytes to PCI config space. + * + * @param[in] osdev platform device instance + * @param[in] offset offset to write + * @param[in] val value to write + * + * @return status of operation + */ +static inline int +adf_os_pci_config_write32(adf_os_device_t osdev, int offset, a_uint32_t val) +{ + return __adf_os_pci_config_write32(osdev, offset, val); +} +#endif + diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_pseudo.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_pseudo.h new file mode 100755 index 0000000..695775b --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_pseudo.h @@ -0,0 +1,31 @@ +/** + * @ingroup adf_os_public + * @file adf_os_pseudo.h + * This file abstracts "pseudo module" semantics. + */ +#ifndef __ADF_OS_PSEUDO_H +#define __ADF_OS_PSEUDO_H + +#include + +/** + * @brief Specify the module's entry point. + */ +#define adf_os_pseudo_module_init(_fn) __adf_os_pseudo_module_init(_fn) + +/** + * @brief Specify the module's exit point. + */ +#define adf_os_pseudo_module_exit(_fn) __adf_os_pseudo_module_exit(_fn) + +/** + * @brief Setup the following driver information: name, pseudo IDs of devices + * supported and some device handlers. + */ +#define adf_os_pseudo_set_drv_info(_name, _ifname, _pseudo_ids, _attach, _detach, \ + _suspend, _resume) \ + __adf_os_pseudo_set_drv_info(_name, _ifname, _pseudo_ids, \ + _attach, _detach, \ + _suspend, _resume) +#endif + diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_stdtypes.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_stdtypes.h new file mode 100755 index 0000000..b43a69c --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_stdtypes.h @@ -0,0 +1,33 @@ +/** + * @defgroup adf_os_public OS abstraction API + */ + +/** + * @ingroup adf_os_public + * @file adf_os_stdtypes.h + * This file defines standard types. + */ + +#ifndef _ADF_OS_STDTYPES_H +#define _ADF_OS_STDTYPES_H + +#include + +/** + * @brief basic data types. + */ +typedef enum { + A_FALSE, + A_TRUE +}a_bool_t; + +typedef __a_uint8_t a_uint8_t; +typedef __a_int8_t a_int8_t; +typedef __a_uint16_t a_uint16_t; +typedef __a_int16_t a_int16_t; +typedef __a_uint32_t a_uint32_t; +typedef __a_int32_t a_int32_t; +typedef __a_uint64_t a_uint64_t; +typedef __a_int64_t a_int64_t; + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_time.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_time.h new file mode 100755 index 0000000..494e4a6 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_time.h @@ -0,0 +1,95 @@ +/** + * @ingroup adf_os_public + * @file adf_os_time.h + * This file abstracts time related functionality. + */ +#ifndef _ADF_OS_TIME_H +#define _ADF_OS_TIME_H + +#include + +/** + * @brief count the number of ticks elapsed from the time when + * the system booted + * + * @return ticks + */ +static inline unsigned long +adf_os_ticks(void) +{ + return __adf_os_ticks(); +} + +/** + * @brief convert ticks to milliseconds + * + * @param[in] ticks number of ticks + * @return time in milliseconds + */ +static inline a_uint32_t +adf_os_ticks_to_msecs(unsigned long ticks) +{ + return (__adf_os_ticks_to_msecs(ticks)); +} + +/** + * @brief convert milliseconds to ticks + * + * @param[in] time in milliseconds + * @return number of ticks + */ +static inline unsigned long +adf_os_msecs_to_ticks(a_uint32_t msecs) +{ + return (__adf_os_msecs_to_ticks(msecs)); +} + +/** + * @brief Return a monotonically increasing time. This increments once per HZ ticks + */ +static inline unsigned long +adf_os_getuptime(void) +{ + return (__adf_os_getuptime()); +} + +/** + * @brief Delay in microseconds + * + * @param[in] microseconds to delay + */ +static inline void +adf_os_udelay(int usecs) +{ + __adf_os_udelay(usecs); +} + +/** + * @brief Delay in milliseconds. + * + * @param[in] milliseconds to delay + */ +static inline void +adf_os_mdelay(int msecs) +{ + __adf_os_mdelay(msecs); +} + +/** + * @brief Check if _a is later than _b. + */ +#define adf_os_time_after(_a, _b) __adf_os_time_after(_a, _b) + +/** + * @brief Check if _a is prior to _b. + */ +#define adf_os_time_before(_a, _b) __adf_os_time_before(_a, _b) + +/** + * @brief Check if _a atleast as recent as _b, if not later. + */ +#define adf_os_time_after_eq(_a, _b) __adf_os_time_after_eq(_a, _b) + +#endif + + diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_timer.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_timer.h new file mode 100755 index 0000000..83a731a --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_timer.h @@ -0,0 +1,64 @@ +/** + * @ingroup adf_os_public + * @file adf_os_timer.h + * This file abstracts OS timers. + */ + +#ifndef _ADF_OS_TIMER_H +#define _ADF_OS_TIMER_H + +#include +#include + + +/** + * @brief Platform timer object + */ +typedef __adf_os_timer_t adf_os_timer_t; + + +/** + * @brief Initialize a timer + * + * @param[in] hdl OS handle + * @param[in] timer timer object pointer + * @param[in] func timer function + * @param[in] context context of timer function + */ +static inline void +adf_os_timer_init(adf_os_handle_t hdl, + adf_os_timer_t *timer, + adf_os_timer_func_t func, + void *arg) +{ + __adf_os_timer_init(hdl, timer, func, arg); +} + +/** + * @brief Start a one-shot timer + * + * @param[in] timer timer object pointer + * @param[in] msec expiration period in milliseconds + */ +static inline void +adf_os_timer_start(adf_os_timer_t *timer, int msec) +{ + __adf_os_timer_start(timer, msec); +} + +/** + * @brief Cancel a timer + * + * @param[in] timer timer object pointer + * + * @retval TRUE timer was cancelled and deactived + * @retval FALSE timer was cancelled but already got fired. + */ +static inline a_bool_t +adf_os_timer_cancel(adf_os_timer_t *timer) +{ + return __adf_os_timer_cancel(timer); +} + +#endif + diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_types.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_types.h new file mode 100755 index 0000000..5e180a9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_types.h @@ -0,0 +1,300 @@ +/** + * @ingroup adf_os_public + * @file adf_os_types.h + * This file defines types used in the OS abstraction API. + */ + +#ifndef _ADF_OS_TYPES_H +#define _ADF_OS_TYPES_H + + +#include +#include + +#define ADF_OS_MAX_SCATTER __ADF_OS_MAX_SCATTER +/** + * @brief Max number of scatter-gather segments. + */ +#define ADF_OS_MAX_SGLIST 4 + +/** + * @brief denotes structure is packed. + */ +#define adf_os_packed __adf_os_packed + +/** + * @brief handles opaque to each other + */ +typedef void * adf_net_handle_t; +typedef void * adf_drv_handle_t; +typedef void * adf_os_handle_t; + +/* + * XXX FIXME For compilation only. + * + */ +typedef void * adf_os_pm_t; + +/** + * @brief Platform/bus generic handle. Used for bus specific functions. + */ +typedef __adf_os_device_t adf_os_device_t; + +/** + * @brief size of an object + */ +typedef __adf_os_size_t adf_os_size_t; + +/** + * @brief offset for API's that need them. + */ +typedef __adf_os_off_t adf_os_off_t; + +/** + * @brief DMA mapping object. + */ +typedef __adf_os_dma_map_t adf_os_dma_map_t; + +/** + * @brief DMA address. + */ +typedef __adf_os_dma_addr_t adf_os_dma_addr_t; + +/** + * @brief DMA size. + */ +typedef __adf_os_dma_size_t adf_os_dma_size_t; + +/** + * @brief Information inside a DMA map. + */ +typedef struct adf_os_dmamap_info{ + a_uint32_t nsegs; /**< total number mapped segments*/ + struct __dma_segs{ + adf_os_dma_addr_t paddr; /**< physical(dma'able) address of the segment*/ + adf_os_dma_size_t len; /**< length of the segment*/ + } dma_segs[ADF_OS_MAX_SCATTER]; + +}adf_os_dmamap_info_t; + +/** + * @brief Representation of a scatter-gather list. + */ +typedef struct adf_os_sglist{ + a_uint32_t nsegs; /**< total number of segments*/ + struct __sg_segs{ + a_uint8_t *vaddr; /**< Virtual address of the segment*/ + a_uint32_t len; /**< Length of the segment*/ + } sg_segs[ADF_OS_MAX_SGLIST]; + +}adf_os_sglist_t; + +/** + * @brief All operations specified below are performed from + * the host memory point of view, where a read + * implies data coming from the device to the host + * memory, and a write implies data going from the + * host memory to the device. Alternately, the + * operations can be thought of in terms of driver + * operations, where reading a network packet or + * storage sector corresponds to a read operation in + * bus_dma. + * + * ADF_SYNC_PREREAD Perform any synchronization + * required prior to an update + * of host memory by the DMA + * read operation. + * ADF_SYNC_PREWRITE Perform any synchronization + * required after an update of + * host memory by the CPU and + * prior to DMA write + * operations. + * ADF_SYNC_POSTREAD Perform any synchronization + * required after DMA read + * operations and prior to CPU + * access to host + * memory. + * ADF_SYNC_POSTWRITE Perform any synchronization + * required after DMA write + * operations. + */ + +typedef enum adf_os_cache_sync{ + ADF_SYNC_PREREAD=__ADF_SYNC_PREREAD, + ADF_SYNC_PREWRITE=__ADF_SYNC_PREWRITE, + ADF_SYNC_POSTREAD=__ADF_SYNC_POSTREAD, + ADF_SYNC_POSTWRITE=__ADF_SYNC_POSTWRITE +}adf_os_cache_sync_t; + +/** + * @brief Generic status to be used by adf_drv. + */ +typedef enum { + A_STATUS_OK, + A_STATUS_FAILED, + A_STATUS_ENOENT, + A_STATUS_ENOMEM, + A_STATUS_EINVAL, + A_STATUS_EINPROGRESS, + A_STATUS_ENOTSUPP, + A_STATUS_EBUSY, + A_STATUS_E2BIG, + A_STATUS_EADDRNOTAVAIL, + A_STATUS_ENXIO, + A_STATUS_EFAULT, + A_STATUS_EIO, +} a_status_t; + +/** + * @brief An ecore needs to provide a table of all pci device/vendor id's it + * supports + * + * This table should be terminated by a NULL entry , i.e. {0} + */ +typedef struct { + a_uint32_t vendor; + a_uint32_t device; + a_uint32_t subvendor; + a_uint32_t subdevice; +}adf_os_pci_dev_id_t; + +#define ADF_OS_PCI_ANY_ID (~0) + +/** + * @brief Typically core's can use this macro to create a table of various device + * ID's + */ +#define ADF_OS_PCI_DEVICE(_vendor, _device) \ + (_vendor), (_device), ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID + + +#define adf_os_iomem_t __adf_os_iomem_t; +/** + * @brief These define the hw resources the OS has allocated for the device + * Note that start defines a mapped area. + */ +typedef enum { + ADF_OS_RESOURCE_TYPE_MEM, + ADF_OS_RESOURCE_TYPE_IO, +}adf_os_resource_type_t; + +/** + * @brief Representation of a h/w resource. + */ +typedef struct { + a_uint64_t start; + a_uint64_t end; + adf_os_resource_type_t type; +}adf_os_resource_t; + +#define ADF_OS_DEV_ID_TABLE_MAX 256 + +/** + * @brief Representation of bus registration data. + */ +typedef union { + adf_os_pci_dev_id_t *pci; + void *raw; +}adf_os_bus_reg_data_t; + +/** + * @brief Representation of data required for attach. + */ +typedef union { + adf_os_pci_dev_id_t pci; + void *raw; +}adf_os_attach_data_t; + +#define ADF_OS_REGIONS_MAX 5 + +/** + * @brief Types of buses. + */ +typedef enum { + ADF_OS_BUS_TYPE_PCI = 1, + ADF_OS_BUS_TYPE_GENERIC, +}adf_os_bus_type_t; + +/** + * @brief IRQ handler response codes. + */ +typedef enum { + ADF_OS_IRQ_NONE, + ADF_OS_IRQ_HANDLED, +}adf_os_irq_resp_t; + +/** + * @brief DMA mask types. + */ +typedef enum { + ADF_OS_DMA_MASK_32BIT, + ADF_OS_DMA_MASK_64BIT, +}adf_os_dma_mask_t; + + +/** + * @brief DMA directions + * ADF_OS_DMA_TO_DEVICE (data going from device to memory) + * ADF_OS_DMA_FROM_DEVICE (data going from memory to device) + */ +typedef enum { + ADF_OS_DMA_TO_DEVICE = __ADF_OS_DMA_TO_DEVICE, + ADF_OS_DMA_FROM_DEVICE = __ADF_OS_DMA_FROM_DEVICE, +} adf_os_dma_dir_t; + +/* + * Protoypes shared between public and private headers + */ + + +/** + * @brief work queue(kernel thread)/DPC function callback + */ +typedef void (*adf_os_defer_fn_t)(void *); + +/** + * @brief Prototype of the critical region function that is to be + * executed with spinlock held and interrupt disalbed + */ +typedef a_bool_t (*adf_os_irqlocked_func_t)(void *); + + +/** + * @brief Prototype of timer function + */ +typedef void (*adf_os_timer_func_t)(void *); + +/** + * @brief Prototype of IRQ function. + */ +typedef adf_os_irq_resp_t (*adf_os_drv_intr)(adf_drv_handle_t hdl); + +/** + * @brief The OS print routine. + */ +#define adf_os_print __adf_os_print + +/** + * @brief driver info structure needed while we do the register + * for the driver to the shim. + */ +typedef struct _adf_drv_info{ + /** + * @brief driver specific functions + */ + adf_drv_handle_t (*drv_attach) (adf_os_resource_t *res, int count, + adf_os_attach_data_t *data, + adf_os_device_t osdev); + void (*drv_detach) (adf_drv_handle_t hdl); + void (*drv_suspend) (adf_drv_handle_t hdl, adf_os_pm_t pm); + void (*drv_resume) (adf_drv_handle_t hdl); + /** + * @brief driver specific data + */ + adf_os_bus_type_t bus_type; + adf_os_bus_reg_data_t bus_data; + unsigned char *mod_name; + unsigned char *ifname; +}adf_drv_info_t; + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_util.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_util.h new file mode 100755 index 0000000..98e3b25 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_util.h @@ -0,0 +1,62 @@ +/** + * @ingroup adf_os_public + * @file adf_os_util.h + * This file defines utility functions. + */ + +#ifndef _ADF_OS_UTIL_H +#define _ADF_OS_UTIL_H + +#include + +/** + * @brief Compiler-dependent macro denoting code likely to execute. + */ +#define adf_os_unlikely(_expr) __adf_os_unlikely(_expr) + +/** + * @brief Compiler-dependent macro denoting code unlikely to execute. + */ +#define adf_os_likely(_expr) __adf_os_likely(_expr) + +/** + * @brief read memory barrier. + */ +#define adf_os_wmb() __adf_os_wmb() + +/** + * @brief write memory barrier. + */ +#define adf_os_rmb() __adf_os_rmb() + +/** + * @brief read + write memory barrier. + */ +#define adf_os_mb() __adf_os_mb() + +/** + * @brief return the lesser of a, b + */ +#define adf_os_min(_a, _b) __adf_os_min(_a, _b) + +/** + * @brief return the larger of a, b + */ +#define adf_os_max(_a, _b) __adf_os_max(_a, _b) + +/** + * @brief assert "expr" evaluates to true. + */ +#define adf_os_assert(expr) __adf_os_assert(expr) + +/** + * @brief supply pseudo-random numbers + */ +static inline void adf_os_get_rand(adf_os_handle_t hdl, + a_uint8_t *ptr, + a_uint32_t len) +{ + __adf_os_get_rand(hdl, ptr, len); +} + +#endif /*_ADF_OS_UTIL_H*/ diff --git a/target_firmware/magpie_fw_dev/target/inc/asf_bitmap.h b/target_firmware/magpie_fw_dev/target/inc/asf_bitmap.h new file mode 100755 index 0000000..38fa652 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/asf_bitmap.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications, Inc. + * All rights reserved. + */ +#ifndef _ASF_BITMAP_H_ +#define _ASF_BITMAP_H_ + +#include "adf_os_types.h" +#include "adf_os_mem.h" + +#define ASF_BYTESZ 8 + +typedef a_uint8_t * asf_bitmap_t; + +/* Bit map related macros. */ +// setbit(a,i) ((a)[(i)/NBBY] |= 1<<((i)%NBBY)) +// clrbit(a,i) ((a)[(i)/NBBY] &= ~(1<<((i)%NBBY))) +// isset(a,i) ((a)[(i)/NBBY] & (1<<((i)%NBBY))) +// isclr(a,i) (((a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0) + +#define asf_howmany(x, y) (((x)+((y)-1))/(y)) +#define asf_roundup(x, y) ((((x)+((y)-1))/(y))*(y)) + + +static inline a_uint8_t * +asf_bitmap_alloc(int sz_bits) +{ + a_uint8_t * bm; + int sz_bytes = sz_bits / ASF_BYTESZ; + + bm = adf_os_mem_alloc(sz_bytes); + if (bm == NULL) + return NULL; + + adf_os_mem_zero(bm, sz_bytes); + return bm; +} + +static inline void +asf_bitmap_free(a_uint8_t *bm) +{ + adf_os_mem_free(bm); +} + +static inline void +asf_bitmap_setbit(a_uint8_t *bm, int pos) +{ + bm[pos / ASF_BYTESZ] |= 1 << (pos % ASF_BYTESZ); +} + + +static inline void +asf_bitmap_clrbit(a_uint8_t *bm, int pos) +{ + bm[pos / ASF_BYTESZ] &= ~(1 << (pos % ASF_BYTESZ)); +} + +static inline a_bool_t +asf_bitmap_isset(a_uint8_t *bm, int pos) +{ + return bm[pos / ASF_BYTESZ] & (1 << (pos % ASF_BYTESZ)); +} + +static inline a_bool_t +asf_bitmap_isclr(a_uint8_t *bm, int pos) +{ + return ((bm[pos / ASF_BYTESZ] & (1 << (pos % ASF_BYTESZ))) == 0); +} + +#endif /* _ASF_BITMAP_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/asf_queue.h b/target_firmware/magpie_fw_dev/target/inc/asf_queue.h new file mode 100755 index 0000000..1c2caab --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/asf_queue.h @@ -0,0 +1,571 @@ +/* + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)queue.h 8.5 (Berkeley) 8/20/94 + * $FreeBSD: src/sys/sys/queue.h,v 1.58 2004/04/07 04:19:49 imp Exp $ + * $Id: //depot/sw/branches/fusion_usb/target_firmware/magpie_fw_dev/asf/include/asf_queue.h#1 $ + */ + +#ifndef _ASF_QUEUE_H_ +#define _ASF_QUEUE_H_ + +/** + * General purpose routines + */ +#define asf_offsetof(type, member) ((adf_os_size_t) &((type *)0)->member) + +#define asf_containerof(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__lptr = (ptr); \ + (type *)( (char *)__mptr - asf_offsetof(type,member) );}) + +/* + * This file defines four types of data structures: singly-linked lists, + * singly-linked tail queues, lists and tail queues. + * + * A singly-linked list is headed by a single forward pointer. The elements + * are singly linked for minimum space and pointer manipulation overhead at + * the expense of O(n) removal for arbitrary elements. New elements can be + * added to the list after an existing element or at the head of the list. + * Elements being removed from the head of the list should use the explicit + * macro for this purpose for optimum efficiency. A singly-linked list may + * only be traversed in the forward direction. Singly-linked lists are ideal + * for applications with large datasets and few or no removals or for + * implementing a LIFO queue. + * + * A singly-linked tail queue is headed by a pair of pointers, one to the + * head of the list and the other to the tail of the list. The elements are + * singly linked for minimum space and pointer manipulation overhead at the + * expense of O(n) removal for arbitrary elements. New elements can be added + * to the list after an existing element, at the head of the list, or at the + * end of the list. Elements being removed from the head of the tail queue + * should use the explicit macro for this purpose for optimum efficiency. + * A singly-linked tail queue may only be traversed in the forward direction. + * Singly-linked tail queues are ideal for applications with large datasets + * and few or no removals or for implementing a FIFO queue. + * + * A list is headed by a single forward pointer (or an array of forward + * pointers for a hash table header). The elements are doubly linked + * so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before + * or after an existing element or at the head of the list. A list + * may only be traversed in the forward direction. + * + * A tail queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or + * after an existing element, at the head of the list, or at the end of + * the list. A tail queue may be traversed in either direction. + * + * For details on the use of these macros, see the queue(3) manual page. + * + * + * asf_slist asf_list asf_stailq asf_tailq + * _head + + + + + * _head_initializer + + + + + * _entry + + + + + * _init + + + + + * _empty + + + + + * _first + + + + + * _next + + + + + * _prev - - - + + * _last - - + + + * _foreach + + + + + * _foreach_safe + + + + + * _foreach_reverse - - - + + * _foreach_reverse_safe - - - + + * _insert_head + + + + + * _insert_before - + - + + * _insert_after + + + + + * _insert_tail - - + + + * _concat - - + + + * _remove_head + - + - + * _remove + + + + + * + */ +#define QUEUE_MACRO_DEBUG 0 +#if QUEUE_MACRO_DEBUG +/* Store the last 2 places the queue element or head was altered */ +struct asf_qm_trace { + char * lastfile; + int lastline; + char * prevfile; + int prevline; +}; + +#define TRACEBUF struct asf_qm_trace trace +#define trashit(x) do {(x) = (void *)-1;} while (0) + +#define qmd_trace_head(head) do { \ + (head)->trace.prevline = (head)->trace.lastline; \ + (head)->trace.prevfile = (head)->trace.lastfile; \ + (head)->trace.lastline = __LINE__; \ + (head)->trace.lastfile = __FILE__; \ +} while (0) + +#define qmd_trace_elem(elem) do { \ + (elem)->trace.prevline = (elem)->trace.lastline; \ + (elem)->trace.prevfile = (elem)->trace.lastfile; \ + (elem)->trace.lastline = __LINE__; \ + (elem)->trace.lastfile = __FILE__; \ +} while (0) + +#else +#define qmd_trace_elem(elem) +#define qmd_trace_head(head) +#define TRACEBUF +#define trashit(x) +#endif /* QUEUE_MACRO_DEBUG */ + +/* + * Singly-linked List declarations. + */ +#define asf_slist_head(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ +} + +#define asf_slist_head_initializer(head) \ + { NULL } + +#define asf_slist_entry(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List functions. + */ +#define asf_slist_empty(head) ((head)->slh_first == NULL) + +#define asf_slist_first(head) ((head)->slh_first) + +#define asf_slist_foreach(var, head, field) \ + for ((var) = asf_slist_first((head)); \ + (var); \ + (var) = asf_slist_next((var), field)) + +#define asf_slist_foreach_safe(var, head, field, tvar) \ + for ((var) = asf_slist_first((head)); \ + (var) && ((tvar) = asf_slist_next((var), field), 1); \ + (var) = (tvar)) + +#define asf_slist_foreach_prevptr(var, varp, head, field) \ + for ((varp) = &asf_slist_first((head)); \ + ((var) = *(varp)) != NULL; \ + (varp) = &asf_slist_next((var), field)) + +#define asf_slist_init(head) do { \ + asf_slist_first((head)) = NULL; \ +} while (0) + +#define asf_slist_insert_after(slistelm, elm, field) do { \ + asf_slist_next((elm), field) = asf_slist_next((slistelm), field); \ + asf_slist_next((slistelm), field) = (elm); \ +} while (0) + +#define asf_slist_insert_head(head, elm, field) do { \ + asf_slist_next((elm), field) = asf_slist_first((head)); \ + asf_slist_first((head)) = (elm); \ +} while (0) + +#define asf_slist_next(elm, field) ((elm)->field.sle_next) + +#define asf_slist_remove(head, elm, type, field) do { \ + if (asf_slist_first((head)) == (elm)) { \ + asf_slist_remove_head((head), field); \ + } \ + else { \ + struct type *curelm = asf_slist_first((head)); \ + while (asf_slist_next(curelm, field) != (elm)) \ + curelm = asf_slist_next(curelm, field); \ + asf_slist_next(curelm, field) = \ + asf_slist_next(asf_slist_next(curelm, field), field); \ + } \ +} while (0) + +#define asf_slist_remove_head(head, field) do { \ + asf_slist_first((head)) = asf_slist_next(asf_slist_first((head)), field); \ +} while (0) + +/* + * Singly-linked Tail queue declarations. + */ +#define asf_stailq_head(name, type) \ +struct name { \ + struct type *stqh_first;/* first element */ \ + struct type **stqh_last;/* addr of last next element */ \ +} + +#define asf_stailq_head_initializer(head) \ + { NULL, &(head).stqh_first } + +#define asf_stailq_entry(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Singly-linked Tail queue functions. + */ +#define asf_stailq_concat(head1, head2) do { \ + if (!asf_stailq_empty((head2))) { \ + *(head1)->stqh_last = (head2)->stqh_first; \ + (head1)->stqh_last = (head2)->stqh_last; \ + asf_stailq_init((head2)); \ + } \ +} while (0) + +#define asf_stailq_empty(head) ((head)->stqh_first == NULL) + +#define asf_stailq_first(head) ((head)->stqh_first) + +#define asf_stailq_foreach(var, head, field) \ + for((var) = asf_stailq_first((head)); \ + (var); \ + (var) = asf_stailq_next((var), field)) + + +#define asf_stailq_foreach_safe(var, head, field, tvar) \ + for ((var) = asf_stailq_first((head)); \ + (var) && ((tvar) = asf_stailq_next((var), field), 1); \ + (var) = (tvar)) + +#define asf_stailq_init(head) do { \ + asf_stailq_first((head)) = NULL; \ + (head)->stqh_last = &asf_stailq_first((head)); \ +} while (0) + +#define asf_stailq_insert_after(head, tqelm, elm, field) do { \ + if ((asf_stailq_next((elm), field) = asf_stailq_next((tqelm), field)) == NULL)\ + (head)->stqh_last = &asf_stailq_next((elm), field); \ + asf_stailq_next((tqelm), field) = (elm); \ +} while (0) + +#define asf_stailq_insert_head(head, elm, field) do { \ + if ((asf_stailq_next((elm), field) = asf_stailq_first((head))) == NULL) \ + (head)->stqh_last = &asf_stailq_next((elm), field); \ + asf_stailq_first((head)) = (elm); \ +} while (0) + +#define asf_stailq_insert_tail(head, elm, field) do { \ + asf_stailq_next((elm), field) = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &asf_stailq_next((elm), field); \ +} while (0) + +#define asf_stailq_last(head, type, field) \ + (asf_stailq_empty((head)) ? \ + NULL : \ + ((struct type *) \ + ((char *)((head)->stqh_last) - __offsetof(struct type, field)))) + +#define asf_stailq_next(elm, field) ((elm)->field.stqe_next) + +#define asf_stailq_remove(head, elm, type, field) do { \ + if (asf_stailq_first((head)) == (elm)) { \ + asf_stailq_remove_head((head), field); \ + } \ + else { \ + struct type *curelm = asf_stailq_first((head)); \ + while (asf_stailq_next(curelm, field) != (elm)) \ + curelm = asf_stailq_next(curelm, field); \ + if ((asf_stailq_next(curelm, field) = \ + asf_stailq_next(asf_stailq_next(curelm, field), field)) == NULL)\ + (head)->stqh_last = &asf_stailq_next((curelm), field);\ + } \ +} while (0) + + +#define asf_stailq_remove_after(head, elm, field) do { \ + if (asf_stailq_next(elm, field)) { \ + if ((asf_stailq_next(elm, field) = \ + asf_stailq_next(asf_stailq_next(elm, field), field)) == NULL)\ + (head)->stqh_last = &asf_stailq_next((elm), field); \ + } \ +} while (0) + + +#define asf_stailq_remove_head(head, field) do { \ + if ((asf_stailq_first((head)) = \ + asf_stailq_next(asf_stailq_first((head)), field)) == NULL) \ + (head)->stqh_last = &asf_stailq_first((head)); \ +} while (0) + +#define asf_stailq_remove_head_until(head, elm, field) do { \ + if ((asf_stailq_first((head)) = asf_stailq_next((elm), field)) == NULL) \ + (head)->stqh_last = &asf_stailq_first((head)); \ +} while (0) + +/* + * List declarations. + */ +#define asf_list_head(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define asf_list_head_initializer(head) \ + { NULL } + +#define asf_list_entry(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * List functions. + */ + +#define asf_list_empty(head) ((head)->lh_first == NULL) + +#define asf_list_first(head) ((head)->lh_first) + +#define asf_list_foreach(var, head, field) \ + for ((var) = asf_list_first((head)); \ + (var); \ + (var) = asf_list_next((var), field)) + +#define asf_list_foreach_safe(var, head, field, tvar) \ + for ((var) = asf_list_first((head)); \ + (var) && ((tvar) = asf_list_next((var), field), 1); \ + (var) = (tvar)) + +#define asf_list_init(head) do { \ + asf_list_first((head)) = NULL; \ +} while (0) + +#define asf_list_insert_after(listelm, elm, field) do { \ + if ((asf_list_next((elm), field) = asf_list_next((listelm), field)) != NULL)\ + asf_list_next((listelm), field)->field.le_prev = \ + &asf_list_next((elm), field); \ + asf_list_next((listelm), field) = (elm); \ + (elm)->field.le_prev = &asf_list_next((listelm), field); \ +} while (0) + +#define asf_list_insert_before(listelm, elm, field) do { \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + asf_list_next((elm), field) = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &asf_list_next((elm), field); \ +} while (0) + +#define asf_list_insert_head(head, elm, field) do { \ + if ((asf_list_next((elm), field) = asf_list_first((head))) != NULL) \ + asf_list_first((head))->field.le_prev = &asf_list_next((elm), field);\ + asf_list_first((head)) = (elm); \ + (elm)->field.le_prev = &asf_list_first((head)); \ +} while (0) + +#define asf_list_next(elm, field) ((elm)->field.le_next) + +#define asf_list_remove(elm, field) do { \ + if (asf_list_next((elm), field) != NULL) \ + asf_list_next((elm), field)->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = asf_list_next((elm), field); \ +} while (0) + +/* + * Tail queue declarations. + */ +#define asf_tailq_head(name, type) \ +struct name { \ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ + TRACEBUF; \ +} + +#define asf_tailq_head_initializer(head) \ + { NULL, &(head).tqh_first } + +#define asf_tailq_entry(type) \ +struct { \ + struct type *tqe_next; /* next element */ \ + struct type **tqe_prev; /* address of previous next element */ \ + TRACEBUF; \ +} + +/* + * Tail queue functions. + */ +#define asf_tailq_concat(head1, head2, field) do { \ + if (!asf_tailq_empty(head2)) { \ + *(head1)->tqh_last = (head2)->tqh_first; \ + (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ + (head1)->tqh_last = (head2)->tqh_last; \ + asf_tailq_init((head2)); \ + qmd_trace_head(head); \ + qmd_trace_head(head2); \ + } \ +} while (0) + +#define asf_tailq_empty(head) ((head)->tqh_first == NULL) + +#define asf_tailq_first(head) ((head)->tqh_first) + +#define asf_tailq_foreach(var, head, field) \ + for ((var) = asf_tailq_first((head)); \ + (var); \ + (var) = asf_tailq_next((var), field)) + +#define asf_tailq_foreach_safe(var, head, field, tvar) \ + for ((var) = asf_tailq_first((head)); \ + (var) && ((tvar) = asf_tailq_next((var), field), 1); \ + (var) = (tvar)) + +#define asf_tailq_foreach_reverse(var, head, headname, field) \ + for ((var) = asf_tailq_last((head), headname); \ + (var); \ + (var) = asf_tailq_prev((var), headname, field)) + +#define asf_tailq_foreach_reverse_safe(var, head, headname, field, tvar) \ + for ((var) = asf_tailq_last((head), headname); \ + (var) && ((tvar) = asf_tailq_prev((var), headname, field), 1); \ + (var) = (tvar)) + +#define asf_tailq_init(head) do { \ + asf_tailq_first((head)) = NULL; \ + (head)->tqh_last = &asf_tailq_first((head)); \ + qmd_trace_head(head); \ +} while (0) + +#define asf_tailq_insert_after(head, listelm, elm, field) do { \ + if ((asf_tailq_next((elm), field) = asf_tailq_next((listelm), field)) != NULL)\ + asf_tailq_next((elm), field)->field.tqe_prev = \ + &asf_tailq_next((elm), field); \ + else { \ + (head)->tqh_last = &asf_tailq_next((elm), field); \ + qmd_trace_head(head); \ + } \ + asf_tailq_next((listelm), field) = (elm); \ + (elm)->field.tqe_prev = &asf_tailq_next((listelm), field); \ + qmd_trace_elem(&(elm)->field); \ + qmd_trace_elem(&listelm->field); \ +} while (0) + +#define asf_tailq_insert_before(listelm, elm, field) do { \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + asf_tailq_next((elm), field) = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &asf_tailq_next((elm), field); \ + qmd_trace_elem(&(elm)->field); \ + qmd_trace_elem(&listelm->field); \ +} while (0) + +#define asf_tailq_insert_head(head, elm, field) do { \ + if ((asf_tailq_next((elm), field) = asf_tailq_first((head))) != NULL) \ + asf_tailq_first((head))->field.tqe_prev = \ + &asf_tailq_next((elm), field); \ + else \ + (head)->tqh_last = &asf_tailq_next((elm), field); \ + asf_tailq_first((head)) = (elm); \ + (elm)->field.tqe_prev = &asf_tailq_first((head)); \ + qmd_trace_head(head); \ + qmd_trace_elem(&(elm)->field); \ +} while (0) + +#define asf_tailq_insert_tail(head, elm, field) do { \ + asf_tailq_next((elm), field) = NULL; \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &asf_tailq_next((elm), field); \ + qmd_trace_head(head); \ + qmd_trace_elem(&(elm)->field); \ +} while (0) + +#define asf_tailq_last(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) + +#define asf_tailq_next(elm, field) ((elm)->field.tqe_next) + +#define asf_tailq_prev(elm, headname, field) \ + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) + +#define asf_tailq_remove(head, elm, field) do { \ + if ((asf_tailq_next((elm), field)) != NULL) \ + asf_tailq_next((elm), field)->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else { \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + qmd_trace_head(head); \ + } \ + *(elm)->field.tqe_prev = asf_tailq_next((elm), field); \ + trashit((elm)->field.tqe_next); \ + trashit((elm)->field.tqe_prev); \ + qmd_trace_elem(&(elm)->field); \ +} while (0) + + +#ifdef _KERNEL + +/* + * XXX asf_insque() and remque() are an old way of handling certain queues. + * They bogusly assumes that all queue heads look alike. + */ + +struct asf_qhead { + struct asf_qhead *qh_link; + struct asf_qhead *qh_rlink; +}; + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) + +static __inline void +asf_insque(void *a, void *b) +{ + struct asf_qhead *element = (struct asf_qhead *)a, + *head = (struct asf_qhead *)b; + + element->qh_link = head->qh_link; + element->qh_rlink = head; + head->qh_link = element; + element->qh_link->qh_rlink = element; +} + +static __inline void +asf_remque(void *a) +{ + struct asf_qhead *element = (struct asf_qhead *)a; + + element->qh_link->qh_rlink = element->qh_rlink; + element->qh_rlink->qh_link = element->qh_link; + element->qh_rlink = 0; +} + +#else /* !(__GNUC__ || __INTEL_COMPILER) */ + +void asf_insque(void *a, void *b); +void asf_remque(void *a); + +#endif /* __GNUC__ || __INTEL_COMPILER */ + +#endif /* _KERNEL */ + +#endif /* !_ASF_QUEUE_H_ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/asf_sm.h b/target_firmware/magpie_fw_dev/target/inc/asf_sm.h new file mode 100755 index 0000000..be8632e --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/asf_sm.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2007-2008 Atheros Communications, Inc. + * All rights reserved. + */ +#ifndef _ASF_SM_H_ +#define _ASF_SM_H_ + +typedef void (*asf_sm_fn_t)(void *object, int event); + +typedef struct asf_sm_s { + void * object; + asf_sm_fn_t fn; + void * event_arg; +} asf_sm_t; + +static inline void +asf_sm_init(asf_sm_t *sm, void *object) +{ + sm->object = object; +} + +static inline void +asf_sm_set_state(asf_sm_t *sm, asf_sm_fn_t fn) +{ + sm->fn = fn; +} + +static inline void +asf_sm_send_event(asf_sm_t *sm, int event) +{ + sm->fn(sm->object, event); +} + +static inline void +asf_sm_set_event_arg(asf_sm_t *sm, void *arg) +{ + sm->event_arg = arg; +} + +static inline void * +asf_sm_get_event_arg(asf_sm_t *sm) +{ + return sm->event_arg; +} + +#endif /* _ASF_SM_H_ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/dt_defs.h b/target_firmware/magpie_fw_dev/target/inc/dt_defs.h new file mode 100755 index 0000000..a2426b2 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/dt_defs.h @@ -0,0 +1,92 @@ +/*************************************************************************/ +/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : dt_defs.h */ +/* */ +/* Abstract */ +/* This file contains the common data structure definition. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _DT_DEFS_H_ +#define _DT_DEFS_H_ + +#ifndef LOCAL +#define LOCAL static +#endif + +/* data type definition */ +typedef unsigned long uint32_t; +typedef unsigned short uint16_t; +typedef unsigned char uint8_t; + +typedef signed long int32_t; +typedef signed short int16_t; +typedef signed char int8_t; + +typedef uint16_t BOOLEAN; + +// Ray for porting +/* Basic data type */ +#define u32_t unsigned long +#define s32_t signed long +#define u16_t unsigned short +#define s16_t signed short +#define u8_t unsigned char +#define s8_t signed char + +#define ptrData uint8_t * + +/* marco definition */ +//#define SIZE_HASH_BUFFER 128 + +#ifndef TRUE +#define TRUE (0==0) +#endif + +#ifndef FALSE +#define FALSE (0!=0) +#endif + +#ifndef NULL +#define NULL 0x0 +#endif + +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif + diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/Magpie_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/Magpie_api.h new file mode 100755 index 0000000..d579ba1 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/Magpie_api.h @@ -0,0 +1,194 @@ +/* + * @File: Magpie_api.h + * + * @Abstract: Magpie FW api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _MAGPIE_API_H +#define _MAGPIE_API_H + +#include +#include "cmnos_api.h" +#include "vbuf_api.h" +#include "vdesc_api.h" +#include "usbfifo_api.h" +#include "hif_api.h" +#include "htc_api.h" +#include "wmi_svc_api.h" +#include "buf_pool_api.h" +#include "dma_engine_api.h" +#include "dma_lib.h" +#if defined(PROJECT_K2) +#include "sflash_api.h" +#endif + +#define A_INDIR(sym) _A_MAGPIE_INDIRECTION_TABLE->sym + +#if SYSTEM_MODULE_DBG +/* debug Support */ +#define DBG_MODULE_INSTALL() cmnos_dbg_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dbg) +#define A_DBG_INIT() A_INDIR(dbg._dbg_init()) +#define A_DBG_TASK() A_INDIR(dbg._dbg_task()) +#else +#define DBG_MODULE_INSTALL() +#define A_DBG_INIT() +#define A_DBG_TASK() +#endif + +/* Serial Flash support */ +#if SYSTEM_MODULE_SFLASH +#define SFLASH_MODULE_INSTALL() cmnos_sflash_module_install(&_A_MAGPIE_INDIRECTION_TABLE->sflash) +#define A_SFLASH_INIT() A_INDIR(sflash._sflash_init()) +#define A_SFLASH_ERASE(erase_type, addr) A_INDIR(sflash._sflash_erase(erase_type, addr)) +#define A_SFLASH_PROG(addr, len, buf) A_INDIR(sflash._sflash_program(addr, len, buf)) +#define A_SFLASH_READ(fast, addr, len, buf) A_INDIR(sflash._sflash_read(fast, addr, len, buf)) +#define A_SFLASH_RDSR() A_INDIR(sflash._sflash_rdsr()) +#else +#define SFLASH_MODULE_INSTALL() +#define A_SFLASH_INIT() +#define A_SFLASH_ERASE(erase_type, addr) +#define A_SFLASH_PROG(addr, len, buf) +#define A_SFLASH_READ(fast, addr, len, buf) +#define A_SFLASH_RDSR() +#endif + +/* DMA Engine Interface */ +#define DMA_ENGINE_MODULE_INSTALL() dma_engine_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_engine); +#define DMA_Engine_init() A_INDIR(dma_engine._init()) +#define DMA_Engine_config_rx_queue(q, nDesc, size) A_INDIR(dma_engine._config_rx_queue(q, nDesc, size)) +#define DMA_Engine_xmit_buf(q, buf) A_INDIR(dma_engine._xmit_buf(q, buf)) +#define DMA_Engine_flush_xmit(q) A_INDIR(dma_engine._flush_xmit(q)) +#define DMA_Engine_reap_recv_buf(q) A_INDIR(dma_engine._reap_recv_buf(q)) +#define DMA_Engine_return_recv_buf(q,buf) A_INDIR(dma_engine._return_recv_buf(q, buf)) +#define DMA_Engine_reap_xmited_buf(q) A_INDIR(dma_engine._reap_xmited_buf(q)) +#define DMA_Engine_swap_data(desc) A_INDIR(dma_engine._swap_data(desc)) +#define DMA_Engine_init_rx_queue(q) A_INDIR(dma_engine._init_rx_queue(q)) +#define DMA_Engine_init_tx_queue(q) A_INDIR(dma_engine._init_tx_queue(q)) +#define DMA_Engine_has_compl_packets(q) A_INDIR(dma_engine._has_compl_packets(q)) +#define DMA_Engine_desc_dump(q) A_INDIR(dma_engine._desc_dump(q)) +#define DMA_Engine_get_packet(q) A_INDIR(dma_engine._get_packet(q)) +#define DMA_Engine_reclaim_packet(q,desc) A_INDIR(dma_engine._reclaim_packet(q,desc)) +#define DMA_Engine_put_packet(q,desc) A_INDIR(dma_engine._put_packet(q,desc)) + +/*DMA Library support for GMAC & PCI(E)*/ +#define DMA_LIB_MODULE_INSTALL() dma_lib_module_install(&_A_MAGPIE_INDIRECTION_TABLE->dma_lib) +#define dma_lib_tx_init(eng_no, if_type) A_INDIR(dma_lib.tx_init(eng_no, if_type)) +#define dma_lib_rx_init(eng_no, if_type) A_INDIR(dma_lib.rx_init(eng_no, if_type)) +#define dma_lib_rx_config(eng_no, desc, gran) A_INDIR(dma_lib.rx_config(eng_no, desc, gran)) +#define dma_lib_tx_start(eng_no) A_INDIR(dma_lib.tx_start(eng_no)) +#define dma_lib_rx_start(eng_no) A_INDIR(dma_lib.rx_start(eng_no)) +#define dma_lib_intr_status(if_type) A_INDIR(dma_lib.intr_status(if_type)) +#define dma_lib_hard_xmit(eng_no, buf) A_INDIR(dma_lib.hard_xmit(eng_no, buf)) +#define dma_lib_flush_xmit(eng_no) A_INDIR(dma_lib.flush_xmit(eng_no)) +#define dma_lib_xmit_done(eng_no) A_INDIR(dma_lib.xmit_done(eng_no)) +#define dma_lib_reap_xmitted(eng_no) A_INDIR(dma_lib.reap_xmitted(eng_no)) +#define dma_lib_reap_recv(eng_no) A_INDIR(dma_lib.reap_recv(eng_no)) +#define dma_lib_return_recv(eng_no, buf) A_INDIR(dma_lib.return_recv(eng_no, buf)) +#define dma_lib_recv_pkt(eng_no) A_INDIR(dma_lib.recv_pkt(eng_no)) + +/* HIF support */ +#define HIF_MODULE_INSTALL() hif_module_install(&_A_MAGPIE_INDIRECTION_TABLE->hif) +#define HIF_init(pConfig) A_INDIR(hif._init(pConfig)) +#define HIF_shutdown(h) A_INDIR(hif._shutdown(h)) +#define HIF_register_callback(h, pConfig) A_INDIR(hif._register_callback(h, pConfig)) +#define HIF_start(h) A_INDIR(hif._start(h)) +#define HIF_config_pipe(h, pipe, desc_list) A_INDIR(hif._config_pipe(h, pipe, desc_list)) +#define HIF_send_buffer(h, pipe, buf) A_INDIR(hif._send_buffer(h, pipe, buf)) +#define HIF_return_recv_buf(h, pipe, buf) A_INDIR(hif._return_recv_buf(h, pipe, buf)) +#define HIF_isr_handler(h) A_INDIR(hif._isr_handler(h)) +#define HIF_is_pipe_supported(h, pipe) A_INDIR(hif._is_pipe_supported(h, pipe)) +#define HIF_get_max_msg_len(h, pipe) A_INDIR(hif._get_max_msg_len(h, pipe)) +#define HIF_get_reserved_headroom(h) A_INDIR(hif._get_reserved_headroom(h)) +#define HIF_get_default_pipe(h,u,d) A_INDIR(hif._get_default_pipe(h,u,d)) + +/* VBUF APIs */ +#define VBUF_MODULE_INSTALL() vbuf_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vbuf) +#define VBUF_init(nBuf) A_INDIR(vbuf._init(nBuf)) +#define VBUF_alloc_vbuf() A_INDIR(vbuf._alloc_vbuf()) +#define VBUF_free_vbuf(buf) A_INDIR(vbuf._free_vbuf(buf)) + +/* VDESC APIs */ +#define VDESC_MODULE_INSTALL() vdesc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->vdesc) +#define VDESC_init(nDesc) A_INDIR(vdesc._init(nDesc)) +#define VDESC_alloc_vdesc() A_INDIR(vdesc._alloc_vdesc()) +#define VDESC_get_hw_desc(desc) A_INDIR(vdesc._get_hw_desc(desc)) +#define VDESC_swap_vdesc(dst, src) A_INDIR(vdesc._swap_vdesc(dst, src)) + +#define HTC_MODULE_INSTALL() htc_module_install(&_A_MAGPIE_INDIRECTION_TABLE->htc) +#define HTC_init(SetupComplete, pConfig) A_INDIR(htc._HTC_Init(SetupComplete, pConfig)) +#define HTC_Shutdown(h) A_INDIR(htc._HTC_Shutdown(h)) +#define HTC_RegisterService(h, s) A_INDIR(htc._HTC_RegisterService(h, s)) +#define HTC_Ready(h) A_INDIR(htc._HTC_Ready(h)) +#define HTC_SendMsg(h, endpt, buf) A_INDIR(htc._HTC_SendMsg(h, endpt, buf)) +#define HTC_ReturnBuffers(h, endpt, buf) A_INDIR(htc._HTC_ReturnBuffers(h, endpt, buf)) +#define HTC_ReturnBuffersList(h, endpt, hd) A_INDIR(htc._HTC_ReturnBuffersList(h, endpt, hd)) +#define HTC_GetReservedHeadroom(h) A_INDIR(htc._HTC_GetReservedHeadroom(h)) + +#define HTC_NotifyTargetInserted(h) +#define HTC_NotifyTargetDetached(h) + +/* WMI SVC module */ +#define WMI_SERVICE_MODULE_INSTALL() WMI_service_module_install(&_A_MAGPIE_INDIRECTION_TABLE->wmi_svc_api) +#define WMI_Init(pCfg) A_INDIR(wmi_svc_api._WMI_Init(pCfg)) +#define WMI_RegisterDispatchTable(h,pT) A_INDIR(wmi_svc_api._WMI_RegisterDispatchTable(h, pT)) +#define WMI_AllocEvent(h,ec,len) A_INDIR(wmi_svc_api._WMI_AllocEvent(h, ec, len)) +#define WMI_SendEvent(h,ev,id,seq,len) A_INDIR(wmi_svc_api._WMI_SendEvent(h, ev, id, seq, len)) +#define WMI_GetPendingEventsCount() A_INDIR(wmi_svc_api._WMI_GetPendingEventsCount()) +#define WMI_GetControlEp() A_INDIR(wmi_svc_api._WMI_GetControlEp()) +#define WMI_SendCompleteHandler(ep, buf) A_INDIR(wmi_svc_api._WMI_SendCompleteHandler(ep, buf)) +#define WMI_Shutdown(h) A_INDIR(wmi_svc_api._WMI_Shutdown(h)) + +/* USB FIFO module */ +#define USBFIFO_MODULE_INSTALL() usbfifo_module_install(&_A_MAGPIE_INDIRECTION_TABLE->usbfifo_api) +#define USBFIFO_init(pConfig) A_INDIR(usbfifo_api._init(pConfig)) +#define USBFIFO_enable_event_isr() A_INDIR(usbfifo_api._enable_event_isr()) + +/* BUF pool module */ +#define BUF_POOL_MODULE_INSTALL() buf_pool_module_install(&_A_MAGPIE_INDIRECTION_TABLE->buf_pool) +#define BUF_Pool_init(h) A_INDIR(buf_pool._init(h)) +#define BUF_Pool_shutdown(h) A_INDIR(buf_pool._shutdown(h)) +#define BUF_Pool_create_pool(h, id, nItems, nSize) A_INDIR(buf_pool._create_pool(h, id, nItems, nSize)) +#define BUF_Pool_alloc_buf(h, id, reserve) A_INDIR(buf_pool._alloc_buf(h, id, reserve)) +#define BUF_Pool_alloc_buf_align(h, id, reserve,align) A_INDIR(buf_pool._alloc_buf_align(h, id, reserve,align)) +#define BUF_Pool_free_buf(h, id, buf) A_INDIR(buf_pool._free_buf(h, id, buf)) + +/* + * This defines the layout of the indirection table, which + * is used to access exported APIs of various modules. The + * layout is shared across ROM and RAM code. RAM code may + * call into ROM and ROM code may call into RAM. Because + * of the latter, existing offsets must not change for the + * lifetime of a revision of ROM; but new members may be + * added at the end. + */ +typedef struct _A_magpie_indirection_table { + _A_cmnos_indirection_table_t cmnos; + struct dbg_api dbg; + struct sflash_api sflash; + struct hif_api hif; + struct htc_apis htc; + WMI_SVC_APIS wmi_svc_api; + struct usbfifo_api usbfifo_api; + struct buf_pool_api buf_pool; + struct vbuf_api vbuf; + struct vdesc_api vdesc; + struct allocram_api allocram; + struct dma_engine_api dma_engine; + struct dma_lib_api dma_lib; +} _A_magpie_indirection_table_t; + +extern _A_magpie_indirection_table_t _indir_tbl; +#define _A_MAGPIE_INDIRECTION_TABLE_SIZE sizeof(_A_magpie_indirection_table_t) +#if defined(__mips__) +#define _A_MAGPIE_INDIRECTION_TABLE ((_A_magpie_indirection_table_t *)0x700) +#else +#define _A_MAGPIE_INDIRECTION_TABLE (&_indir_tbl) +#endif + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/allocram_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/allocram_api.h new file mode 100755 index 0000000..ca0872c --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/allocram_api.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2007 Atheros Communications, Inc. All rights reserved. + */ + +#ifndef __ALLOCRAM_API_H__ +#define __ALLOCRAM_API_H__ + +/* API for Target-side startup-time RAM allocations */ + +struct allocram_api { + /* + * Initialize allocram, providing it with a block of RAM + * (an "arena") from which to allocate. + * + * If arena_start is 0, a default start -- the end of + * the application's text & data -- is used. + * + * If arena_sz is 0, a default size -- which uses most + * of physical RAM beyond arena_start -- is used. + * + * Return value is reserved for future use -- it's an arena handle. + */ + void *(* cmnos_allocram_init)(void *arena_start, A_UINT32 arena_sz); + + /* + * Allocate nbytes of memory, returning a pointer to the start + * of the allocated block. Allocation size is rounded up to the + * nearest A_CACHE_LINE_SIZE and the returned address similarly + * aligned. + * + * There is no need to check the return value from this function. + * A failure to satisfy a RAM allocation request is treated as a + * fatal error. + * + * Allocations are expected to occur only during startup; this + * API does not, for instance, guarantee atomicity with respect + * to allocations that might (foolishly) be attempted from + * interrupt handlers. + * + * The "which_arena" parameter is currently unused, and should + * be set to 0 -- only a single arena is currently supported. + */ + void *(* cmnos_allocram)(void *which_arena, A_UINT32 nbytes); + + void (* cmnos_allocram_debug)(void); +}; + +extern void allocram_module_install(struct allocram_api *api); + + +#endif /* __ALLOCRAM_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/athos_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/athos_api.h new file mode 100755 index 0000000..3147d5e --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/athos_api.h @@ -0,0 +1,99 @@ +#ifndef __ATHOS_API_H__ +#define __ATHOS_API_H__ + +/* + * This file contains wrappers to OS operating system functions + * that are available in the Athos version of the operating system. + * + * Target software must always use these wrappers to access OS + * services -- it may not access any OS services directly. + * + * These wrappers are intended to provide OS-independence for applications. + * Using this header file, an application should be able to compile and + * fully link without any other OS header files, source files, or + * binary files. + */ + +#include +#include "dt_defs.h" +#include "cmnos_api.h" +#include "Magpie_api.h" + +/* ROM Patch API */ + +/* save the ROM printf function point */ +extern uint32_t save_cmnos_printf; + +extern unsigned int _data_start_in_rom; +extern unsigned int _data_start; +extern unsigned int _data_end; +extern unsigned int _bss_start; +extern unsigned int _bss_end; +extern unsigned int _stack_sentry; +extern unsigned int __stack; +extern unsigned int _fw_image_end; + +#if defined(__XTENSA__) +#define START_DATA _data_start +#define END_DATA _data_end +#define START_BSS _bss_start +#define END_BSS _bss_end + +#define STACK_START _stack_sentry +#define STACK_END __stack +#endif + +struct _A_os_linkage_check { + int version; + int table; +}; + +/* + * A_INIT() handles any initialization needed by the OS abstraction, + * and it clears the application's BSS, if necessary. (Application BSS + * is not cleared if the application is linked into a single image that + * includes AthOS.) + * + * A_INIT() must be called first thing in the application (from app_start) + * in order to guarantee that BSS has been cleared properly. + */ +static INLINE int +A_INIT(void) +{ + struct _A_os_linkage_check link_check; + unsigned int *clrptr; + + if (&START_BSS != _A_MAGPIE_INDIRECTION_TABLE->cmnos.start_bss) { + /* Clear BSS */ + for (clrptr = &START_BSS; clrptr < &END_BSS; clrptr++) { + *clrptr = 0; + } + } + + /* Copy writable data from flash to RAM. */ + unsigned int *srcptr, *destptr; + + /* + * The _data_start symbol points to the start of data IN FLASH. + * It is defined by flash.ld at application link time. If flash.ld + * is not used, it is defined (on the link line) as 0. + */ + static int *data_start_addr = &_data_start; + + if (data_start_addr != 0) { + for (srcptr = &_data_start, destptr = &START_DATA; + destptr < &END_DATA; + srcptr++, destptr++) { + *destptr = *srcptr; + } + } + +#define OS_LINKAGE_VERSION 4 + link_check.version = OS_LINKAGE_VERSION; + link_check.table = _A_MAGPIE_INDIRECTION_TABLE_SIZE; + + return A_CMN(hal_linkage_check(sizeof(link_check), &link_check)); +} + +#endif /* __ATHOS_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/clock_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/clock_api.h new file mode 100755 index 0000000..74b7753 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/clock_api.h @@ -0,0 +1,29 @@ +#ifndef __CLOCK_API_H__ +#define __CLOCK_API_H__ + +#define TICK_MSEC_RATIO 1 +#define TICK_TO_MSEC(tick) ((tick)/TICK_MSEC_RATIO) +#define MSEC_TO_TICK(msec) ((msec)* TICK_MSEC_RATIO) + +typedef struct date_s { + uint16_t miliseconds; + uint16_t seconds; + uint16_t minutes; + uint16_t hours; +} A_DATE_T; + +struct clock_api { + void (* _clock_init)(A_UINT32 ref_clk); + void (* _clockregs_init)(void); + A_UINT32 (* _uart_frequency)(void); + void (* _delay_us)(int); + void (* _wlan_band_set)(int); + A_UINT32 (* _refclk_speed_get)(void); + A_UINT32 (* _milliseconds)(void); + void (* _sysclk_change)(uint32_t sys_clk); + A_UINT32 (* _sysclk_get)(void); + + void (* _clock_tick)(void); +}; + +#endif /* __CLOCK_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/cmnos_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/cmnos_api.h new file mode 100755 index 0000000..8689a55 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/cmnos_api.h @@ -0,0 +1,630 @@ +#ifndef __CMNOS_API_H__ +#define __CMNOS_API_H__ + +/* + * This file contains wrappers to OS operating system functions + * that are available in all versions of the operating system. + * + * Target software must always use these wrappers to access OS + * services -- it may not access any OS services directly. + */ + +#include "xtensa/config/core.h" +#include "xtensa/hal.h" +#include "xtensa/xtruntime.h" +#include "sys_cfg.h" + +/* cmnos interface */ +#include "printf_api.h" +#include "uart_api.h" +#include "dbg_api.h" +#include "mem_api.h" +#include "misc_api.h" +#include "string_api.h" +#include "timer_api.h" +#include "romp_api.h" +#include "allocram_api.h" +#include "tasklet_api.h" +#include "clock_api.h" +#include "intr_api.h" +#include "wdt_api.h" +#include "eeprom_api.h" +#include "usb_api.h" + +#if defined(PROJECT_K2) +#if SYSTEM_MODULE_SFLASH +#include "sflash_api.h" +#endif +#endif + +#define AR6K_ROM_START 0x004e0000 +#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset)) +#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset) + +#define IML_SIGNAL_UNUSED0_ADDR TARG_ROM_ADDRS(0) /* Cannot be used -- aligned */ +#define IML_SIGNAL_ASSERT_ADDR TARG_ROM_ADDRS(1) /* Signal an assertion failure */ +#define IML_SIGNAL_PRINTF_ADDR TARG_ROM_ADDRS(2) /* Signal a printf request */ +#define IML_SIGNAL_UNUSED4_ADDR TARG_ROM_ADDRS(4) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSED8_ADDR TARG_ROM_ADDRS(8) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSEDC_ADDR TARG_ROM_ADDRS(0xc) /* Cannot be used -- aligned */ +#define IML_SIGNAL_MASK 0xfffe000f +#define IML_LINENUM_SHIFT 4 + +#define NOW() xthal_get_ccount() + +#if defined(__XTENSA__) +#define _A_BARRIER asm volatile("memw") +#else +#define _A_BARRIER +#endif + +#define A_ASSERT( __bool ) \ + do { \ + if (0 == (__bool)) { \ + (void)*((volatile int *)(IML_SIGNAL_ASSERT_ADDR+(__LINE__<<4)));\ + _A_BARRIER; \ + } \ + } while (0) + + +#define A_IML_IS_ASSERT(vaddr) \ + (((vaddr) & IML_SIGNAL_MASK) == (IML_SIGNAL_ASSERT_ADDR & IML_SIGNAL_MASK)) + + +#define PRINT_FAILURE_STATE() \ +do { \ + uint32_t epc1, epc2, epc3, epc4; \ + \ + asm volatile("rsr %0,%1" : "=r" (epc1) : "n" (EPC_1)); \ + asm volatile("rsr %0,%1" : "=r" (epc2) : "n" (EPC_2)); \ + asm volatile("rsr %0,%1" : "=r" (epc3) : "n" (EPC_3)); \ + asm volatile("rsr %0,%1" : "=r" (epc4) : "n" (EPC_4)); \ + \ + A_PRINTF("\tepc1=0x%x, epc2=0x%x, epc3=0x%x, epc4=0x%x\n", \ + epc1, epc2, epc3, epc4); \ + A_PRINTF("0x%08x, 0x%08x, 0x%08x, \n\r", \ + DEBUG_SYSTEM_STATE, WATCH_DOG_RESET_COUNTER, \ + WATCH_DOG_MAGIC_PATTERN); \ +} while(0) +//////////////////////////////////////////////////////////////////////////////////// + + +//#define A_CMN(sym) _A_OS_INDIRECTION_TABLE->cmnos.sym +#define A_CMN(sym) _A_MAGPIE_INDIRECTION_TABLE->cmnos.sym + +#if SYSTEM_MODULE_MEM +/* Mem interfaces */ +#define A_MEMSET(addr, value, size) \ + A_CMN(mem._memset((char *)(addr), (int)(value), (int)(size))) + +#define A_MEMZERO(addr, size) \ + A_CMN(mem._memset((char *)(addr), (int)0, (int)(size))) + +#define A_MEMCPY(dst, src, size) \ + A_CMN(mem._memcpy((char *)(dst), (char *)(src), (int)(size))) + +#define A_MEMMOVE(dst, src, size) \ + A_CMN(mem._memmove((char *)(dst), (char *)(src), (int)(size))) + +#define A_MEMCMP(p1, p2, nbytes) \ + A_CMN(mem._memcmp)((void *)(p1), (void *)(p2), (int)(nbytes)) +#else +/* Mem interfaces */ +#define A_MEMSET(addr, value, size) + +#define A_MEMZERO(addr, size) + +#define A_MEMCPY(dst, src, size) + +#define A_MEMMOVE(dst, src, size) + +#define A_MEMCMP(p1, p2, nbytes) +#endif + + +#if 1 + /* String interfaces */ + #define A_STRCPY(dst, src) A_CMN(string._strcpy((dst), (src))) + #define A_STRNCPY(dst, src, n) A_CMN(string._strncpy((dst), (src), (n))) + #define A_STRLEN(str) A_CMN(string._strlen(str)) + #define A_STRCMP(str1, str2) A_CMN(string._strcmp((str1), (str2))) + #define A_STRNCMP(str1, str2, n) A_CMN(string._strncmp((str1), (str2), (n))) +#endif + +#if SYSTEM_MODULE_PRINT +/* Printf support */ +#define A_PRINTF_INIT() A_CMN(printf._printf_init()) +#define A_PRINTF A_CMN(printf._printf) +#else +#define A_PRINTF_INIT() +#define A_PRINTF +#endif /* SYSTEM_MODULE_PRINT */ + +#if SYSTEM_MODULE_UART +/* Serial port support */ +#define A_UART_INIT() A_CMN(uart._uart_init()) + +#define A_UART_HWINIT(freq, baud) \ + A_CMN(uart._uart_hwinit((freq), (baud))) + +#define A_UART_ENABLED() (HOST_INTEREST->hi_uart_enable) + +#define A_PUTS(str) A_CMN(uart._uart_str_out(str)) + +#define A_PUTC(ch) A_CMN(uart._uart_char_put(ch)) +#define A_GETC(pCh) A_CMN(uart._uart_char_get(pCh)) + +#define A_UART_TASK() A_CMN(uart._uart_task()) +#define A_UART_CONFIG(x) A_CMN(uart._uart_config(x)) + +#else + +#define A_UART_INIT() + +#define A_UART_HWINIT(freq, baud) + +#define A_UART_ENABLED() + +#define A_PUTS(str) + +#define A_PUTC(ch) +#define A_GETC(pCh) + +#define A_UART_TASK() +#define A_UART_CONFIG(x) + +#endif + +#if SYSTEM_MODULE_MISC +/* Reset Support */ +#define A_RESET() A_CMN(misc._system_reset()) +#define A_RESET_MAC() A_CMN(misc._mac_reset()) + +/* Assertion failure */ +#define A_ASSFAIL(regdump) A_CMN(misc._assfail((regdump))) + +/* Report a failure to the Host */ +#define A_REPORT_FAILURE(data, len) \ + A_CMN(misc._report_failure_to_host((data), (len))) + +/* UNALIGNED references are used for ASSERTs */ +#define A_MISALIGNED_LOAD_HANDLER(dump) A_CMN(misc._misaligned_load_handler(dump)) + +/* reture the host interface type */ +#define A_IS_HOST_PRESENT() A_CMN(misc._is_host_present()) +#define A_KBHIT(delay) A_CMN(misc._kbhit(delay)) +#define A_GET_ROM_VER() A_CMN(misc._rom_version_get()) +#else +/* Reset Support */ +#define A_RESET() +#define A_RESET_MAC() + +/* Assertion failure */ +#define A_ASSFAIL(regdump) + +#define A_MISALIGNED_LOAD_HANDLER(dump) + +/* Report a failure to the Host */ +#define A_REPORT_FAILURE(data, len) + +#define A_IS_HOST_PRESENT() +#define A_KBHIT(delay) +#define A_GET_ROM_VER() +#endif + +#if SYSTEM_MODULE_USB +/* debug Support */ +#define A_USB_INIT() A_CMN(usb._usb_init()) +#define A_USB_ROM_TASK() A_CMN(usb._usb_rom_task()) +#define A_USB_FW_TASK() A_CMN(usb._usb_fw_task()) +#define A_USB_INIT_PHY() A_CMN(usb._usb_init_phy()) + +#define A_USB_EP0_SETUP() A_CMN(usb._usb_ep0_setup()) +#define A_USB_EP0_TX_DATA() A_CMN(usb._usb_ep0_tx_data()) +#define A_USB_EP0_RX_DATA() A_CMN(usb._usb_ep0_rx_data()) + +#define A_USB_GET_CONFIG() A_CMN(usb._usb_get_configuration()) +#define A_USB_SET_CONFIG() A_CMN(usb._usb_set_configuration()) + +#define A_USB_GET_INTERFACE() A_CMN(usb._usb_get_interface()) +#define A_USB_SET_INTERFACE() A_CMN(usb._usb_set_interface()) + +#define A_USB_STANDARD_CMD() A_CMN(usb._usb_standard_cmd()) +#define A_USB_VENDOR_CMD() A_CMN(usb._usb_vendor_cmd()) + +#define A_USB_POWER_OFF() A_CMN(usb._usb_power_off()) +#define A_USB_RESET_FIFO() A_CMN(usb._usb_reset_fifo()) +#define A_USB_GEN_WDT() A_CMN(usb._usb_gen_wdt()) +#define A_USB_JUMP_BOOT() A_CMN(usb._usb_jump_boot()) + +#define A_USB_GET_DESCRIPTOR() A_CMN(usb._usb_get_descriptor()) +#define A_USB_SET_ADDRESS() A_CMN(usb._usb_set_address()) +#define A_USB_SET_FEATURE() A_CMN(usb._usb_set_feature()) +#define A_USB_CLEAR_FEATURE() A_CMN(usb._usb_clr_feature()) + +#define A_USB_GET_STATUS() A_CMN(usb._usb_get_status()) +#define A_USB_SETUP_DESC() A_CMN(usb._usb_setup_desc()) +#define A_USB_STATUS_IN() A_CMN(usb._usb_status_in()) +#define A_USB_REG_OUT() A_CMN(usb._usb_reg_out()) + +#define A_USB_EP0_TX() A_CMN(usb._usb_ep0_tx()) +#define A_USB_EP0_RX() A_CMN(usb._usb_ep0_rx()) +#define A_USB_CLK_INIT() A_CMN(usb._usb_clk_init()) + +#else +#define A_USB_INIT() +#define A_USB_TASK() +#define A_USB_INIT_PHY() + +#define A_USB_EP0_SETUP() +#define A_USB_EP0_TX() +#define A_USB_EP0_RX() + +#define A_USB_GET_CONFIG() +#define A_USB_SET_CONFIG() + +#define A_USB_GET_INTERFACE() +#define A_USB_SET_INTERFACE() + +#define A_USB_STANDARD_CMD() +#define A_USB_VENDOR_CMD() + +#define A_USB_POWER_OFF() +#define A_USB_RESET_FIFO() +#define A_USB_GEN_WDT() +#define A_USB_JUMP_BOOT() + +#define A_USB_GET_DESCRIPTOR() +#define A_USB_SET_ADDRESS() +#define A_USB_SET_FEATURE() +#define A_USB_CLEAR_FEATURE() + +#define A_USB_GET_STATUS() +#define A_USB_SETUP_DESC() + + +#define A_USB_STATUS_IN() +#define A_USB_REG_OUT() + +#define A_USB_EP0_TX() +#define A_USB_EP0_RX() + +#define A_USB_CLK_INIT() +#endif + +#if SYSTEM_MODULE_INTR +/* Low-level interrupt support intended for use by OS modules */ +#define A_INTR_GET_INTRENABLE() A_CMN(intr._get_intrenable()) +#define A_INTR_SET_INTRENABLE(val) A_CMN(intr._set_intrenable(val)) +#define A_INTR_GET_INTRPENDING() A_CMN(intr._get_intrpending()) +#define A_INTR_UNBLOCK_ALL_INTRLVL() A_CMN(intr._unblock_all_intrlvl()) + +/* Interrupt support */ +#define A_INTR_INIT() A_CMN(intr._intr_init()) + +#define A_INTR_DISABLE(pOld) \ + do { \ + *(pOld) = A_CMN(intr._intr_disable()); \ + } while (0) + +#define A_INTR_RESTORE(old) A_CMN(intr._intr_restore((old))) + +#define A_INVOKE_ISR(inum) A_CMN(intr._intr_invoke_isr(inum)) + +#define A_INTR_MASK(inum) A_CMN(intr._intr_mask_inum(inum)) +#define A_INTR_UNMASK(inum) A_CMN(intr._intr_unmask_inum(inum)) + +#define A_ATTACH_ISR(inum, isr, arg) A_CMN(intr._intr_attach_isr(inum, isr, arg)) +#else +#define A_INTR_INIT() +#define A_INTR_DISABLE(pOld) +#define A_INTR_RESTORE(old) + +#define A_INTR_GET_INTRENABLE() +#define A_INTR_SET_INTRENABLE(val) +#define A_INTR_GET_INTRPENDING() +#define A_INTR_UNBLOCK_ALL_INTRLVL() +#define A_INVOKE_ISR(inum) +#define A_INTR_MASK(inum) +#define A_INTR_UNMASK(inum) +#define A_ATTACH_ISR(inum, isr, arg) + +#endif + +/* Tasklet Support */ +#define A_TASKLET_INIT() A_CMN(tasklet._tasklet_init()) +#define A_TASKLET_INIT_TASK(f, arg, t) A_CMN(tasklet._tasklet_init_task(f, arg, t)) +#define A_TASKLET_DISABLE(t) A_CMN(tasklet._tasklet_disable(t)) +#define A_TASKLET_SCHEDULE(t) A_CMN(tasklet._tasklet_schedule(t)) +#define A_TASKLET_RUN() A_CMN(tasklet._tasklet_run()) + + +/* RAM Allocation Support */ +#if defined(__mips__) +#define alloc_arena_start _end +#endif +#if defined(__XTENSA__) +#define alloc_arena_start _end +#endif + +#if SYSTEM_MODULE_CLOCK + +#define A_CLOCK_INIT(refclk_guess) A_CMN(clock._clock_init(refclk_guess)) +#define A_CLOCK_TICK() A_CMN(clock._clock_tick()) +#define A_CLOCK_GET_TICK() A_CMN(clock._clock_get_tick()) + +/* + * Get the number of millisecond ticks since the system was started. + * Note that this only approximates 1Ms. It's actually 32 ticks of + * a 32KHz clock. + * + * Returns a A_UINT32 value. + */ +#define A_MILLISECONDS() A_CMN(clock._milliseconds()) + +/* + * Get the frequency of the reference clock, expressed as + * an A_refclk_speed_t. + */ +#define A_REFCLK_SPEED_GET() A_CMN(clock._refclk_speed_get()) + +/* Spin delay */ +#define A_DELAY_USECS(us) A_CMN(clock._delay_us(us)) + +#define A_UART_FREQUENCY() A_CMN(clock._uart_frequency()) + +#define A_CLOCKREGS_INIT() A_CMN(clock._clockregs_init()) + +/* which_band is either A_BAND_24GHZ or A_BAND_5GHZ */ +#define A_WLAN_BAND_SET(which_band) \ + A_CMN(clock._wlan_band_set(which_band)) + +/* Called whenever the system clock changes speed */ +#define A_SYSCLK_CHANGE(mhz) A_CMN(clock._sysclk_change(mhz)) + +#define A_SYSCLK_GET() A_CMN(clock._sysclk_get()) + +#else + +#define A_CLOCK_INIT(refclk_guess) +#define A_CLOCK_TICK() +#define A_CLOCK_GET_TICK() +#define A_MILLISECONDS() +#define A_REFCLK_SPEED_GET() +#define A_DELAY_USECS(us) +#define A_UART_FREQUENCY() +#define A_CLOCKREGS_INIT() +#define A_WLAN_BAND_SET(which_band) +#define A_SYSCLK_CHANGE(mhz) +#define A_SYSCLK_GET() + +#endif + +// Timer +#define A_INIT_TIMER(pTimer, pFunction, pArg) \ + A_CMN(timer._timer_setfn((pTimer), (pFunction), (pArg))) + +/* Set a (possibly periodic) timer for "period" Milliseconds. */ +#define A_TIMEOUT_MS(pTimer, period) \ + A_CMN(timer._timer_arm((pTimer), (period))) + +#define A_UNTIMEOUT(pTimer) \ + A_CMN(timer._timer_disarm(pTimer)) + +#define A_TIMER_RUN() \ + A_CMN(timer._timer_run()) + +#define A_PCI_BOOT_INIT() \ + A_CMN(pci.pci_boot_init()) + +#define A_GMAC_BOOT_INIT() \ + A_CMN(gmac.gmac_boot_init()) + +#if SYSTEM_MODULE_ALLOCRAM +/* Default size of ALLOCRAM area */ +#define ARENA_SZ_DEFAULT 12000 + +#define A_ALLOCRAM_INIT(arena_start, arena_size) \ + do { \ + extern unsigned int alloc_arena_start; \ + void *astart; \ + int asize; \ + astart = (arena_start) ? (void *)(arena_start) : &alloc_arena_start; \ + asize = (arena_size) ? (arena_size) : (ARENA_SZ_DEFAULT); \ + A_CMN(allocram.cmnos_allocram_init((astart), (asize))); \ + } while (0) + +#define A_ALLOCRAM(nbytes) A_CMN(allocram.cmnos_allocram(0, (nbytes))) + +#define A_ALLOCRAM_DEBUG() A_CMN(allocram.cmnos_allocram_debug()) + +#else +#define A_ALLOCRAM_INIT(arena_start, arena_size) +#define A_ALLOCRAM(nbytes) +#define A_ALLOCRAM_DEBUG() +#endif + +#if SYSTEM_MODULE_ROM_PATCH + +#define A_ROMP_INIT() A_CMN(romp._romp_init()) +#define A_ROMP_DOWNLOAD(x) A_CMN(romp._romp_download(x)) +#define A_ROMP_DECODE(addr) A_CMN(romp._romp_decode(addr)) +#define A_ROMP_INSTALL() A_CMN(romp._romp_install()) +#else +#define A_ROMP_INIT() +#define A_ROMP_DOWNLOAD(x) +#define A_ROMP_DECODE(addr) +#define A_ROMP_INSTALL() +#endif + +#if SYSTEM_MODULE_WDT + +#define A_WDT_INIT() A_CMN(wdt_timer._wdt_init()) +#define A_WDT_ENABLE() A_CMN(wdt_timer._wdt_enable()) +#define A_WDT_DISABLE() A_CMN(wdt_timer._wdt_disable()) +#define A_WDT_SET(t) A_CMN(wdt_timer._wdt_set(t)) +#define A_WDT_TASK() A_CMN(wdt_timer._wdt_task()) +#define A_WDT_LASTBOOT() A_CMN(wdt_timer._wdt_last_boot()) +#define A_WDT_RESET() A_CMN(wdt_timer._wdt_reset()) + +#else +#define A_WDT_INIT() +#define A_WDT_ENABLE() +#define A_WDT_DISABLE() +#define A_WDT_SET(t) +#define A_WDT_TASK() +#define A_WDT_LASTBOOT() +#define A_WDT_RESET() +#endif + + +#if SYSTEM_MODULE_EEPROM +#define A_EEP_INIT() A_CMN(eep._eep_init()) +#define A_EEP_READ(off, len, buf) A_CMN(eep._eep_read(off, len, buf)) +#define A_EEP_WRITE(off, len, buf) A_CMN(eep._eep_write(off, len, buf)) +#define A_EEP_IS_EXIST() A_CMN(eep._eep_is_exist()) +#else +#define A_EEP_INIT() +#define A_EEP_READ(off, len, buf) +#define A_EEP_WRITE(off, len, buf) +#define A_EEP_IS_EXIST() +#endif + + + +struct _A_os_linkage_check; /* OS-dependent */ + +typedef struct _A_cmnos_indirection_table { + int (* hal_linkage_check)(int sz, struct _A_os_linkage_check *); + unsigned int *start_bss; + void (* app_start)(void); + +#if SYSTEM_MODULE_MEM + struct mem_api mem; +#endif + +#if SYSTEM_MODULE_MISC + struct misc_api misc; +#endif + +#if SYSTEM_MODULE_PRINT + struct printf_api printf; +#endif + +#if SYSTEM_MODULE_UART + struct uart_api uart; +#endif + +#if SYSTEM_MODULE_DBG +#if !MOVE_DBG_TO_RAM // move to firmware not in cmnos + struct dbg_api dbg; +#endif +#endif +#if SYSTEM_MODULE_PCI + struct pci_api pci; +#endif + +#if SYSTEM_MODULE_GMAC + struct gmac_api gmac; +#endif + +#if SYSTEM_MODULE_USB + struct usb_api usb; +#endif + +#if SYSTEM_MODULE_CLOCK + struct clock_api clock; +#endif + +#if SYSTEM_MODULE_TIMER + struct timer_api timer; +#endif + +#if SYSTEM_MODULE_INTR + struct intr_api intr; +#endif + +#if SYSTEM_MODULE_ALLOCRAM + struct allocram_api allocram; +#endif + +#if SYSTEM_MODULE_ROM_PATCH + struct romp_api romp; +#endif + +#if SYSTEM_MODULE_WDT + struct wdt_api wdt_timer; +#endif + +#if SYSTEM_MODULE_EEPROM + struct eep_api eep; +#endif + + struct string_api string; + struct tasklet_api tasklet; + +} _A_cmnos_indirection_table_t; + +/* Module installation for cmnos modules */ + +#if SYSTEM_MODULE_MEM +extern void cmnos_mem_module_install(struct mem_api *); +#endif + +#if SYSTEM_MODULE_MISC +extern void cmnos_misc_module_install(struct misc_api *); +#endif + +#if SYSTEM_MODULE_PRINT +extern void cmnos_printf_module_install(struct printf_api *); +#endif + +#if SYSTEM_MODULE_UART +extern void cmnos_uart_module_install(struct uart_api *); +#endif + +#if SYSTEM_MODULE_DBG +extern void cmnos_dbg_module_install(struct dbg_api *); +#endif + +#if SYSTEM_MODULE_USB +extern void cmnos_usb_module_install(struct usb_api *); +#endif + +#if SYSTEM_MODULE_INTR +extern void cmnos_intr_module_install(struct intr_api *); +#endif + +#if SYSTEM_MODULE_CLOCK +extern void cmnos_clock_module_install(struct clock_api *); +#endif + +#if SYSTEM_MODULE_TIMER +extern void cmnos_timer_module_install(struct timer_api *); +#endif + +#if SYSTEM_MODULE_ALLOCRAM +extern void cmnos_allocram_module_install(struct allocram_api *); +#endif + +#if SYSTEM_MODULE_ROM_PATCH +extern void cmnos_romp_module_install(struct romp_api *); +#endif + +#if SYSTEM_MODULE_WDT +extern void cmnos_wdt_module_install(struct wdt_api *); +#endif + +#if SYSTEM_MODULE_EEPROM +extern void cmnos_eep_module_install(struct eep_api *); +#endif + +#if SYSTEM_MODULE_PCI +extern void cmnos_pci_module_install(struct pci_api *); +#endif + +extern void cmnos_tasklet_module_install(struct tasklet_api *); + +extern void cmnos_string_module_install(struct string_api *tbl); + +#endif /* __CMNOS_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/dma_engine_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/dma_engine_api.h new file mode 100755 index 0000000..937b5c3 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/dma_engine_api.h @@ -0,0 +1,92 @@ +/* + * @File: dma_engine_api.h + * + * @Abstract: DMA Engine api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _DMA_ENGINE_API_H +#define _DMA_ENGINE_API_H + +#include +#include + +struct zsDmaDesc +{ +#if 1 // BIG_ENDIAN + volatile u16_t ctrl; // Descriptor control + volatile u16_t status; // Descriptor status + volatile u16_t totalLen; // Total length + volatile u16_t dataSize; // Data size +#else + volatile u16_t status; // Descriptor status + volatile u16_t ctrl; // Descriptor control + volatile u16_t dataSize; // Data size + volatile u16_t totalLen; // Total length +#endif + struct zsDmaDesc* lastAddr; // Last address of this chain + volatile u32_t dataAddr; // Data buffer address + struct zsDmaDesc* nextAddr; // Next TD address +}; + +struct zsDmaQueue +{ + struct zsDmaDesc* head; + struct zsDmaDesc* terminator; +}; + +// Subclass of zsDmaQueue for TX +struct zsTxDmaQueue +{ + struct zsDmaDesc* head; + struct zsDmaDesc* terminator; + + /* Below are fields specific to TX */ + VBUF *xmited_buf_head; + VBUF *xmited_buf_tail; +}; + +/* hardware API table structure (API descriptions below) */ +struct dma_engine_api +{ + void (*_init)(); + + void (*_init_rx_queue)(struct zsDmaQueue *q); + + void (*_init_tx_queue)(struct zsTxDmaQueue *q); + + void (*_config_rx_queue)(struct zsDmaQueue *q, int num_desc, int buf_size); + + void (*_xmit_buf)(struct zsTxDmaQueue *q, VBUF *buf); + + void (*_flush_xmit)(struct zsDmaQueue *q); + + VBUF* (*_reap_recv_buf)(struct zsDmaQueue *q); + + void (*_return_recv_buf)(struct zsDmaQueue *q, VBUF *buf); + + VBUF* (*_reap_xmited_buf)(struct zsTxDmaQueue *q); + + void (*_swap_data)(struct zsDmaDesc* desc); + + int (*_has_compl_packets)(struct zsDmaQueue *q); + + void (*_desc_dump)(struct zsDmaQueue *q); + + /* The functions below are for patchable */ + struct zsDmaDesc* (*_get_packet)(struct zsDmaQueue* q); + void (*_reclaim_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc); + void (*_put_packet)(struct zsDmaQueue* q, struct zsDmaDesc* desc); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void dma_engine_module_install(struct dma_engine_api *apis); + +#endif /* #ifndef _DMA_ENGINE_API_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/dma_lib.h b/target_firmware/magpie_fw_dev/target/inc/k2/dma_lib.h new file mode 100755 index 0000000..7b44c56 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/dma_lib.h @@ -0,0 +1,57 @@ +#ifndef __DMA_LIB_H +#define __DMA_LIB_H + + +/***********************External***************************/ + +/** + * @brief DMA engine numbers, HIF need to map them to there + * respective order + */ +typedef enum dma_engine{ + DMA_ENGINE_RX0, + DMA_ENGINE_RX1, + DMA_ENGINE_RX2, + DMA_ENGINE_RX3, + DMA_ENGINE_TX0, + DMA_ENGINE_TX1, + DMA_ENGINE_MAX +}dma_engine_t; + +/** + * @brief Interface type, each HIF should call with its own interface type + */ +typedef enum dma_iftype{ + DMA_IF_GMAC = 0x0,/* GMAC */ + DMA_IF_PCI = 0x1,/*PCI */ + DMA_IF_PCIE = 0x2 /*PCI Express */ +}dma_iftype_t; + + +struct dma_lib_api{ + A_UINT16 (*tx_init)(dma_engine_t eng_no, dma_iftype_t if_type); + void (*tx_start)(dma_engine_t eng_no); + A_UINT16 (*rx_init)(dma_engine_t eng_no, dma_iftype_t if_type); + void (*rx_config)(dma_engine_t eng_no, a_uint16_t num_desc, + a_uint16_t gran); + void (*rx_start)(dma_engine_t eng_no); + A_UINT32 (*intr_status)(dma_iftype_t if_type); + A_UINT16 (*hard_xmit)(dma_engine_t eng_no, VBUF *buf); + void (*flush_xmit)(dma_engine_t eng_no); + A_UINT16 (*xmit_done)(dma_engine_t eng_no); + VBUF * (*reap_xmitted)(dma_engine_t eng_no); + VBUF * (*reap_recv)(dma_engine_t eng_no); + void (*return_recv)(dma_engine_t eng_no, VBUF *buf); + A_UINT16 (*recv_pkt)(dma_engine_t eng_no); +}; + + +/** + * @brief Install the DMA lib api's this for ROM patching + * support + * + * @param apis + */ +void dma_lib_module_install(struct dma_lib_api *apis); + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/eeprom_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/eeprom_api.h new file mode 100755 index 0000000..bcaa0cf --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/eeprom_api.h @@ -0,0 +1,27 @@ +#ifndef __EEPROM_API_H__ +#define __EEPROM_API_H__ + +typedef enum { + RET_SUCCESS = 0, + RET_NOT_INIT, + RET_NOT_EXIST, + RET_EEP_CORRUPT, + RET_EEP_OVERFLOW, + + // add return code from here + RET_UNKNOWN +} T_EEP_RET; + + +/*!- interface of eeprom access + * + */ +struct eep_api { + void (* _eep_init)(void); + T_EEP_RET (* _eep_read)(uint16_t, uint16_t, uint16_t *); + T_EEP_RET (* _eep_write)(uint16_t, uint16_t, uint16_t *); + T_EEP_RET (*_eep_is_exist)(void); +}; + +#endif /* __EEPROM_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/hif_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/hif_api.h new file mode 100755 index 0000000..734dcea --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/hif_api.h @@ -0,0 +1,70 @@ +/* + * @File: HIF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _HIF_API_H +#define _HIF_API_H + +#include + +/* mailbox hw module configuration structure */ +typedef struct _HIF_CONFIG { + int dummy; +} HIF_CONFIG; + +typedef struct _HIF_CALLBACK { + /* callback when a buffer has be sent to the host*/ + void (*send_buf_done)(adf_nbuf_t buf, void *context); + /* callback when a receive message is received */ + void (*recv_buf)(adf_nbuf_t hdr_buf, adf_nbuf_t buf, void *context); + /* context used for all callbacks */ + void *context; +} HIF_CALLBACK; + +typedef void* hif_handle_t; + +/* hardware API table structure (API descriptions below) */ +struct hif_api { + hif_handle_t (*_init)(HIF_CONFIG *pConfig); + + void (* _shutdown)(hif_handle_t); + + void (*_register_callback)(hif_handle_t, HIF_CALLBACK *); + + int (*_get_total_credit_count)(hif_handle_t); + + void (*_start)(hif_handle_t); + + void (*_config_pipe)(hif_handle_t handle, int pipe, int creditCount); + + int (*_send_buffer)(hif_handle_t handle, int pipe, adf_nbuf_t buf); + + void (*_return_recv_buf)(hif_handle_t handle, int pipe, adf_nbuf_t buf); + //void (*_set_recv_bufsz)(int pipe, int bufsz); + //void (*_pause_recv)(int pipe); + //void (*_resume_recv)(int pipe); + int (*_is_pipe_supported)(hif_handle_t handle, int pipe); + + int (*_get_max_msg_len)(hif_handle_t handle, int pipe); + + int (*_get_reserved_headroom)(hif_handle_t handle); + + void (*_isr_handler)(hif_handle_t handle); + + void (*_get_default_pipe)(hif_handle_t handle, A_UINT8 *pipe_uplink, A_UINT8 *pipe_downlink); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void hif_module_install(struct hif_api *apis); + +#endif /* #ifndef _HIF_API_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/hif_gmac.h b/target_firmware/magpie_fw_dev/target/inc/k2/hif_gmac.h new file mode 100755 index 0000000..71229bf --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/hif_gmac.h @@ -0,0 +1,35 @@ + +#ifndef __HIF_GMAC_H +#define __HIF_GMAC_H + +#include +#include + + +#define ETH_ALEN 6 +#define GMAC_MAX_PKT_LEN 1600 +#define GMAC_MAX_DESC 5 + +#define GMAC_DISCV_PKT_SZ 60 +#define GMAC_DISCV_WAIT 2000 + +#define ATH_P_MAGBOOT 0x12 /*Magpie GMAC 18 for boot downloader*/ +#define ATH_P_MAGNORM 0x13 /*Magpie GMAC 19 for HTC & others*/ + +#define ETH_P_ATH 0x88bd + +typedef enum hif_gmac_pipe{ + HIF_GMAC_PIPE_RX = 1, /*Normal Priority RX*/ + HIF_GMAC_PIPE_TX = 2, /*Normal Priority TX*/ +}hif_gmac_pipe_t; + +struct gmac_api{ + void (*gmac_boot_init)(void); +}; + +void cmnos_gmac_module_install(struct gmac_api *boot_apis); +void hif_gmac_module_install(struct hif_api *apis); + + +#endif + diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/hif_pci.h b/target_firmware/magpie_fw_dev/target/inc/k2/hif_pci.h new file mode 100755 index 0000000..0db441a --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/hif_pci.h @@ -0,0 +1,33 @@ + +#ifndef __HIF_PCI_H +#define __HIF_PCI_H + +#include + + +#define PCI_MAX_PKT_LEN 1600 +#define PCI_MAX_DESC 2 + +typedef enum hif_pci_pipe_rx{ + HIF_PCI_PIPE_RX0, /*Normal Priority RX*/ + HIF_PCI_PIPE_RX1, + HIF_PCI_PIPE_RX2, + HIF_PCI_PIPE_RX3, + HIF_PCI_PIPE_RX_MAX +}hif_pci_pipe_rx_t; + +typedef enum hif_pci_pipe_tx{ + HIF_PCI_PIPE_TX0, /*Normal Priority TX*/ + HIF_PCI_PIPE_TX1, + HIF_PCI_PIPE_TX_MAX +}hif_pci_pipe_tx_t; + +struct pci_api{ + void (*pci_boot_init)(void); +}; + +void cmnos_pci_module_install(struct pci_api *apis); +void hif_pci_module_install(struct hif_api *apis); +#endif + + diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/hif_usb.h b/target_firmware/magpie_fw_dev/target/inc/k2/hif_usb.h new file mode 100755 index 0000000..f5d1a24 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/hif_usb.h @@ -0,0 +1,54 @@ +/* + * @File: mbox_hw.h + * + * @Abstract: mailbox hardware definitions + * + * @Notes: + * * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef __HIF_USB_H__ +#define __HIF_USB_H__ + +#include +#include +//#include +#include + +#define HIF_USB_PIPE_TX 1 +#define HIF_USB_PIPE_RX 2 +#define HIF_USB_PIPE_INTERRUPT 3 +#define HIF_USB_PIPE_COMMAND 4 +#define HIF_USB_PIPE_HP_TX 5 +#define HIF_USB_PIPE_MP_TX 6 + +struct VBUF_QUEUE +{ + VBUF *head; + VBUF *tail; +}; + + /* the mailbox hardware layer context */ +typedef struct _HIF_USB_CONTEXT { + HIF_CALLBACK hifCb; + struct zsDmaQueue dnQ; + struct zsTxDmaQueue upQ; +#if SYSTEM_MODULE_HP_EP5 + struct zsDmaQueue hpdnQ; // high priority +#endif +#if SYSTEM_MODULE_HP_EP6 + struct zsDmaQueue mpdnQ; // medium priority +#endif + //struct VBUF_QUEUE upVbufQ; + VBUF *cmdQueue; + struct VBUF_QUEUE eventBufQ; + + // Left a door for extension the structure + void *pReserved; +} HIF_USB_CONTEXT; + + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/intr_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/intr_api.h new file mode 100755 index 0000000..b0eb658 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/intr_api.h @@ -0,0 +1,144 @@ +#ifndef __INTR_API_H__ +#define __INTR_API_H__ + +/* + * Interrupt handler, for application-managed interrupts. + * When an interrupt occurs, it is automatically disabled. + * See A_WMAC_INTR_ATTACH() and A_MBOX_INTR_ATTACH(). + * + * If a handler returns A_HANDLER_DONE, the interrupt is + * re-enabled. The OS calls the handler next time service + * is required. This is the normal case for a handler. + * + * If a handler returns A_HANDLER_YIELD, the interrupt + * remains masked. The handler is called again when + * it is "convenient". This gives the OS an opportunity + * to run other code/handlers. A handler should return + * A_HANDLER_YIELD if it might dominate the CPU for too + * long. + * + * If a handler returns A_HANDLER_NOENABLE, the interrupt + * remains disabled. It is up to the application to re-enable + * the interrupt (via A_*_INTR_UNMASK) when it's appropriate. + * + * Note that many combinations of interrupt functions and + * interrupt vectors are NOT supported: Callers should use + * only the macros defined in cmnos_api.h to access the + * interrupt API. + */ +#include "cmnos_api.h" + +typedef uint32_t A_old_intr_t; + +////////////////////////////////////////////////////////////////// +// this is copied from mercury/cmnos_xtensa.h +/* + * These are CMNOS interrupt manifest constants. + * They have specially-chosen values that align with hardware and or + * operating system values (see cmnos_interrupt_info). + */ +#if defined(__XTENSA__) +/* + * Enumeration of low and medium priority interrupt numbers + * which match the CPU hardware configuration: + */ + +/* XTensa Level 1 interrupt */ +#define A_INUM_SOFTWARE 0 /* currently unused */ + +/* XTensa Level2 interrupts */ +#define A_INUM_XTTIMER 1 /* Tensilica timer */ +#define A_INUM_TBD_2 2 /* TBD */ +#define A_INUM_CPU_WDT 3 /* RST_CPU watchodg interrupt */ +#define A_INUM_TBD_4 4 /* TBD */ +#define A_INUM_TBD_5 5 /* TBD */ +#define A_INUM_TBD_6 6 /* TBD */ +#define A_INUM_CPU_GEN_TIMER 7 /* CPU general timer */ +#define A_INUM_TBD_8 8 /* TBD */ +#define A_INUM_TBD_9 9 /* TBD */ +#define A_INUM_USB_CTRL 10 /* USB core control */ +#define A_INUM_USB_DMA 11 /* USB DMA */ +#define A_INUM_TBD_12 12 /* TBD */ +#define A_INUM_TBD_13 13 /* TBD */ +#define A_INUM_TBD_14 14 /* TBD */ + +/* Level 3 interrupts */ +#define A_INUM_ERROR 15 /* Errors (e.g. access illegal address) */ +#define A_INUM_TBD_16 16 /* TBD */ +#define A_INUM_MAC 17 /* MAC */ + +/* Level 5 interrupts */ +#define A_INUM_CPU_NMI 18 /* CPU NMI */ + +/* Number of interrupts that map directly into CPU/hal interrupt bits. */ +#define NUM_DIRECT_INTR 19 + +#endif +////////////////////////////////////////////////////////////////// + +#define CMNOS_IMASK_XTTIMER (1< + +/************************* Resource DEFS ***********************/ +#define MAX_DESC_NUM 100 + +#ifdef RX_SCATTER +#define MAX_BUF_NUM 100 +#else +#define MAX_BUF_NUM 60 +#endif + +#undef SYSTEM_MODULE_DBG +#undef MOVE_PRINT_TO_RAM +#ifdef _DEBUG_BUILD_ +#define SYSTEM_MODULE_DBG 1 +#define MOVE_PRINT_TO_RAM 1 +#else +#define SYSTEM_MODULE_DBG 0 +#define MOVE_PRINT_TO_RAM 1 +#endif +#undef SYSTEM_MODULE_SFLASH +#define SYSTEM_MODULE_SFLASH 0 + +/************************* WLAN DEFS ***************************/ +#define MAGPIE_ENABLE_WLAN 1 +#define MAGPIE_ENABLE_PCIE 0 +#define MAGPIE_ENABLE_WLAN_IN_TARGET 0 +#define MAGPIE_ENABLE_WLAN_SELF_TX 0 +#define MAGPIE_ENABLE_WLAN_RATE_CTRL 1 + +/****************************** WATCH DOG *******************************/ +#define WDT_DEFAULT_TIMEOUT_VALUE 3*ONE_MSEC*1000 // Initial value is 3 seconds, firmware changes it to 65 milliseconds + +#endif + + +#endif /* _SYS_CFG_H_ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/tasklet_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/tasklet_api.h new file mode 100755 index 0000000..526cb64 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/tasklet_api.h @@ -0,0 +1,26 @@ +#ifndef __TASKLET_API_H__ +#define __TASKLET_API_H__ + +typedef void (*A_TASKLET_FUNC)(void *arg); + +#define A_TASKLET_STATE_DISABLE 0 +#define A_TASKLET_STATE_SCHEDULED 1 +#define A_TASKLET_STATE_RUNNING 2 + +struct _tasklet { + A_TASKLET_FUNC func; + void *arg; + int state; + struct _tasklet *next; +}; + +typedef struct _tasklet A_tasklet_t; + +struct tasklet_api { + void (* _tasklet_init)(void); + void (* _tasklet_init_task)(A_TASKLET_FUNC, void * arg, A_tasklet_t *); + void (* _tasklet_disable)(A_tasklet_t *); + void (* _tasklet_schedule)(A_tasklet_t *); + void (* _tasklet_run)(void); +}; +#endif /* __TASKLET_API_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/timer_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/timer_api.h new file mode 100755 index 0000000..925579b --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/timer_api.h @@ -0,0 +1,23 @@ +#ifndef __TIMER_API_H__ +#define __TIMER_API_H__ +/* + * In order to remain completely independent of OS header files, + * "_SPACE" structures are declared with sufficient room to hold + * corresponding OS structures. + */ +typedef unsigned int _A_TIMER_SPACE[5]; +typedef _A_TIMER_SPACE A_timer_t; +#define A_TIMER A_timer_t /* historical */ + +typedef unsigned int A_HANDLE; /* historical */ +typedef void A_TIMER_FUNC(A_HANDLE timer_handle, void *arg); + +struct timer_api { + void (* _timer_init)(void); + void (* _timer_arm)(A_timer_t *, unsigned int); + void (* _timer_disarm)(A_timer_t *); + void (* _timer_setfn)(A_timer_t *, A_TIMER_FUNC, void *); + void (* _timer_run)(void); +}; +#endif /* __TIMER_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/uart_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/uart_api.h new file mode 100755 index 0000000..3d0870f --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/uart_api.h @@ -0,0 +1,304 @@ +/*************************************************************************/ +/* Copyright (c) 2006 Atheros Communications, Inc., All Rights Reserved */ +/* */ +/* Module Name : uart.h */ +/* */ +/* Abstract */ +/* This file contains definition of uart registers, marco and api. */ +/* */ +/* NOTES */ +/* None */ +/* */ +/*************************************************************************/ + +#ifndef _UART_API_H_ +#define _UART_API_H_ + +#include "k2/reg_defs.h" + +/************************* Register Process marco ************************/ +#define UART_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(UART_BASE_ADDRESS|(uint32_t)(addr), (val)) +#define UART_REG_READ(addr) HAL_WORD_REG_READ(UART_BASE_ADDRESS|(uint32_t)(addr)) + +/************************** Register deinition ***************************/ +#define RBR_ADDRESS 0x00051000 +#define RBR_OFFSET 0x00000000 +#define RBR_RBR_MSB 7 +#define RBR_RBR_LSB 0 +#define RBR_RBR_MASK 0x000000ff +#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB) +#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK) + +#define THR_ADDRESS 0x00051000 +#define THR_OFFSET 0x00000000 +#define THR_THR_MSB 7 +#define THR_THR_LSB 0 +#define THR_THR_MASK 0x000000ff +#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB) +#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK) + +#define DLL_ADDRESS 0x00051000 +#define DLL_OFFSET 0x00000000 +#define DLL_DLL_MSB 7 +#define DLL_DLL_LSB 0 +#define DLL_DLL_MASK 0x000000ff +#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB) +#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK) + +#define DLH_ADDRESS 0x00051004 +#define DLH_OFFSET 0x00000004 +#define DLH_DLH_MSB 7 +#define DLH_DLH_LSB 0 +#define DLH_DLH_MASK 0x000000ff +#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB) +#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK) + +#define IER_ADDRESS 0x00051004 +#define IER_OFFSET 0x00000004 +#define IER_EDDSI_MSB 3 +#define IER_EDDSI_LSB 3 +#define IER_EDDSI_MASK 0x00000008 +#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB) +#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK) +#define IER_ELSI_MSB 2 +#define IER_ELSI_LSB 2 +#define IER_ELSI_MASK 0x00000004 +#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB) +#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK) +#define IER_ETBEI_MSB 1 +#define IER_ETBEI_LSB 1 +#define IER_ETBEI_MASK 0x00000002 +#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB) +#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK) +#define IER_ERBFI_MSB 0 +#define IER_ERBFI_LSB 0 +#define IER_ERBFI_MASK 0x00000001 +#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB) +#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK) + +#define IIR_ADDRESS 0x00051008 +#define IIR_OFFSET 0x00000008 +#define IIR_FIFO_STATUS_MSB 7 +#define IIR_FIFO_STATUS_LSB 6 +#define IIR_FIFO_STATUS_MASK 0x000000c0 +#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB) +#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK) +#define IIR_IID_MSB 3 +#define IIR_IID_LSB 0 +#define IIR_IID_MASK 0x0000000f +#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB) +#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK) + +#define FCR_ADDRESS 0x00051008 +#define FCR_OFFSET 0x00000008 +#define FCR_RCVR_TRIG_MSB 7 +#define FCR_RCVR_TRIG_LSB 6 +#define FCR_RCVR_TRIG_MASK 0x000000c0 +#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB) +#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK) +#define FCR_DMA_MODE_MSB 3 +#define FCR_DMA_MODE_LSB 3 +#define FCR_DMA_MODE_MASK 0x00000008 +#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB) +#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK) +#define FCR_XMIT_FIFO_RST_MSB 2 +#define FCR_XMIT_FIFO_RST_LSB 2 +#define FCR_XMIT_FIFO_RST_MASK 0x00000004 +#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB) +#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK) +#define FCR_RCVR_FIFO_RST_MSB 1 +#define FCR_RCVR_FIFO_RST_LSB 1 +#define FCR_RCVR_FIFO_RST_MASK 0x00000002 +#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB) +#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK) +#define FCR_FIFO_EN_MSB 0 +#define FCR_FIFO_EN_LSB 0 +#define FCR_FIFO_EN_MASK 0x00000001 +#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB) +#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK) + +#define LCR_ADDRESS 0x0005100c +#define LCR_OFFSET 0x0000000c +#define LCR_DLAB_MSB 7 +#define LCR_DLAB_LSB 7 +#define LCR_DLAB_MASK 0x00000080 +#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB) +#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK) +#define LCR_BREAK_MSB 6 +#define LCR_BREAK_LSB 6 +#define LCR_BREAK_MASK 0x00000040 +#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB) +#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK) +#define LCR_EPS_MSB 4 +#define LCR_EPS_LSB 4 +#define LCR_EPS_MASK 0x00000010 +#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB) +#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK) +#define LCR_PEN_MSB 3 +#define LCR_PEN_LSB 3 +#define LCR_PEN_MASK 0x00000008 +#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB) +#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK) +#define LCR_STOP_MSB 2 +#define LCR_STOP_LSB 2 +#define LCR_STOP_MASK 0x00000004 +#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB) +#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK) +#define LCR_CLS_MSB 1 +#define LCR_CLS_LSB 0 +#define LCR_CLS_MASK 0x00000003 +#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB) +#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK) + +#define MCR_ADDRESS 0x00051010 +#define MCR_OFFSET 0x00000010 +#define MCR_LOOPBACK_MSB 5 +#define MCR_LOOPBACK_LSB 5 +#define MCR_LOOPBACK_MASK 0x00000020 +#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB) +#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK) +#define MCR_OUT2_MSB 3 +#define MCR_OUT2_LSB 3 +#define MCR_OUT2_MASK 0x00000008 +#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB) +#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK) +#define MCR_OUT1_MSB 2 +#define MCR_OUT1_LSB 2 +#define MCR_OUT1_MASK 0x00000004 +#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB) +#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK) +#define MCR_RTS_MSB 1 +#define MCR_RTS_LSB 1 +#define MCR_RTS_MASK 0x00000002 +#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB) +#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK) +#define MCR_DTR_MSB 0 +#define MCR_DTR_LSB 0 +#define MCR_DTR_MASK 0x00000001 +#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB) +#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK) + +#define LSR_ADDRESS 0x00051014 +#define LSR_OFFSET 0x00000014 +#define LSR_FERR_MSB 7 +#define LSR_FERR_LSB 7 +#define LSR_FERR_MASK 0x00000080 +#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB) +#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK) +#define LSR_TEMT_MSB 6 +#define LSR_TEMT_LSB 6 +#define LSR_TEMT_MASK 0x00000040 +#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB) +#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK) +#define LSR_THRE_MSB 5 +#define LSR_THRE_LSB 5 +#define LSR_THRE_MASK 0x00000020 +#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB) +#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK) +#define LSR_BI_MSB 4 +#define LSR_BI_LSB 4 +#define LSR_BI_MASK 0x00000010 +#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB) +#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK) +#define LSR_FE_MSB 3 +#define LSR_FE_LSB 3 +#define LSR_FE_MASK 0x00000008 +#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB) +#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK) +#define LSR_PE_MSB 2 +#define LSR_PE_LSB 2 +#define LSR_PE_MASK 0x00000004 +#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB) +#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK) +#define LSR_OE_MSB 1 +#define LSR_OE_LSB 1 +#define LSR_OE_MASK 0x00000002 +#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB) +#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK) +#define LSR_DR_MSB 0 +#define LSR_DR_LSB 0 +#define LSR_DR_MASK 0x00000001 +#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB) +#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK) + +#define MSR_ADDRESS 0x00051018 +#define MSR_OFFSET 0x00000018 +#define MSR_DCD_MSB 7 +#define MSR_DCD_LSB 7 +#define MSR_DCD_MASK 0x00000080 +#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB) +#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK) +#define MSR_RI_MSB 6 +#define MSR_RI_LSB 6 +#define MSR_RI_MASK 0x00000040 +#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB) +#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK) +#define MSR_DSR_MSB 5 +#define MSR_DSR_LSB 5 +#define MSR_DSR_MASK 0x00000020 +#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB) +#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK) +#define MSR_CTS_MSB 4 +#define MSR_CTS_LSB 4 +#define MSR_CTS_MASK 0x00000010 +#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB) +#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK) +#define MSR_DDCD_MSB 3 +#define MSR_DDCD_LSB 3 +#define MSR_DDCD_MASK 0x00000008 +#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB) +#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK) +#define MSR_TERI_MSB 2 +#define MSR_TERI_LSB 2 +#define MSR_TERI_MASK 0x00000004 +#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB) +#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK) +#define MSR_DDSR_MSB 1 +#define MSR_DDSR_LSB 1 +#define MSR_DDSR_MASK 0x00000002 +#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB) +#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK) +#define MSR_DCTS_MSB 0 +#define MSR_DCTS_LSB 0 +#define MSR_DCTS_MASK 0x00000001 +#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB) +#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK) + + +/************************** config definition ***************************/ +#define UART_FIFO_SIZE 512 //Must be 2^N + +#define USE_POST_BUFFER 0 // ENABLE a tx buffer for post processing, +/*********************** data struction definition ************************/ +// data struction definition +struct uart_fifo { +#if USE_POST_BUFFER + uint8_t buf[UART_FIFO_SIZE]; +#endif + uint16_t start_index; + uint16_t end_index; + uint32_t overrun_err; +}; + + +struct uart_blk { + uint16_t debug_mode; + uint16_t baud; + struct uart_api *_uart; + struct uart_fifo _tx; +}; + +/******** hardware API table structure (API descriptions below) *************/ +struct uart_api { + uint32_t (*_uart_init)(void); + void (*_uart_char_put)(uint8_t ch); + uint16_t (*_uart_char_get)(uint8_t* ch); + void (*_uart_str_out)(uint8_t* str); + void (*_uart_task)(void); + uint32_t (*_uart_status)(void); + void (*_uart_config)(uint16_t flag); + void (*_uart_hwinit)(uint32_t freq, uint32_t baud); +}; + +#endif // end of _UART_API_H_ + diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/usb_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/usb_api.h new file mode 100755 index 0000000..a9c3168 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/usb_api.h @@ -0,0 +1,52 @@ +#ifndef USB_API_H +#define USB_API_H + +#include "dt_defs.h" + +/******** hardware API table structure (API descriptions below) *************/ +struct usb_api { + void (*_usb_init)(void); + void (*_usb_rom_task)(void); + void (*_usb_fw_task)(void); + void (*_usb_init_phy)(void); + + // ep0 operation + void (*_usb_ep0_setup)(void); + + void (*_usb_ep0_tx)(void); + void (*_usb_ep0_rx)(void); + + // get/set interface + BOOLEAN (*_usb_get_interface)(void); + BOOLEAN (*_usb_set_interface)(void); + + // get/set configuration + BOOLEAN (*_usb_get_configuration)(void); + BOOLEAN (*_usb_set_configuration)(void); + + // standard/vendor command + BOOLEAN (*_usb_standard_cmd)(void); + void (*_usb_vendor_cmd)(void); + + void (*_usb_power_off)(void); + void (*_usb_reset_fifo)(void); + void (*_usb_gen_wdt)(void); + void (*_usb_jump_boot)(void); + + BOOLEAN (*_usb_clr_feature)(void); + BOOLEAN (*_usb_set_feature)(void); + BOOLEAN (*_usb_set_address)(void); + BOOLEAN (*_usb_get_descriptor)(void); + + BOOLEAN (*_usb_get_status)(void); + void (*_usb_setup_desc)(void); + void (*_usb_reg_out)(void); + void (*_usb_status_in)(void); + + void (*_usb_ep0_tx_data)(void); + void (*_usb_ep0_rx_data)(void); + + void (*_usb_clk_init)(void); +}; + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/usb_defs.h b/target_firmware/magpie_fw_dev/target/inc/k2/usb_defs.h new file mode 100755 index 0000000..bef0190 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/usb_defs.h @@ -0,0 +1,904 @@ +#ifndef USB_DEFS_H +#define USB_DEFS_H + +#include "usb_table.h" +#include "dt_defs.h" +#include "reg_defs.h" + +#define CHECK_SWITCH_BY_BOOTCODE 1 //to be verified for ZD1215, OK for ZD1211 +#define VERIFY_CHECKSUM_BY_BOOTCODE 1 + +/***********************************************************************/ +/* for SEEPROM Boot */ +/***********************************************************************/ +#define WLAN_BOOT_SIGNATURE (0x19710303) + +#define WLAN_SIGNATURE_ADDR (0x102000) + +#define cMAX_ADDR 0x10000 + +#define cEEPROM_SIZE 0x800 // 2k word (4k byte) + +#define cRESERVE_LOAD_SPACE 0 + +// start addr. of boot code +#define cBOOT_CODE_ADDR (cMAX_ADDR - cEEPROM_SIZE) // 0xF800 + +/************************** Register Addr Process *********************/ +#define mpADDR(addr) ((volatile uint16_t*) (addr)) +#define mADDR(addr) (*mpADDR(addr)) +#define muADDR(addr) ((uint16_t) (&(addr))) + +#define USB_BYTE_REG_WRITE(addr, val) HAL_BYTE_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3), (val)) +#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr^3)) +//#define USB_BYTE_REG_READ(addr) HAL_BYTE_REG_READ(USB_CTRL_BASE_ADDRESS|(uint8_t)(addr)) + +#define USB_HALF_WORD_REG_WRITE(addr, val) HAL_HALF_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr), (val)) +#define USB_HALF_WORD_REG_READ(addr) HAL_HALF_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint16_t)(addr)) + +#define USB_WORD_REG_WRITE(addr, val) HAL_WORD_REG_WRITE(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr), (val)) +#define USB_WORD_REG_READ(addr) HAL_WORD_REG_READ(USB_CTRL_BASE_ADDRESS|(uint32_t)(addr)) + + +/************************** Register Deinition ***************************/ +//#define USB_BASE_ADDR_SOC 0x8000 + +//#define SOC_Reg mpADDR(USB_BASE_ADDR_SOC) + +#define cSOC_USB_OFST (0x100) + +#define ZM_CBUS_FIFO_SIZE_OFFSET (cSOC_USB_OFST) //OFFSET 0 + +#define cSOC_CBUS_CTL_OFFSET 0xF0 + +#define ZM_FUSB_BASE USB_CTRL_BASE_ADDRESS + +#define ZM_MAIN_CTRL_OFFSET 0x00 +#define ZM_DEVICE_ADDRESS_OFFSET 0x01 +#define ZM_TEST_OFFSET 0x02 +#define ZM_PHY_TEST_SELECT_OFFSET 0x08 +#define ZM_VDR_SPECIFIC_MODE_OFFSET 0x0A +#define ZM_CX_CONFIG_STATUS_OFFSET 0x0B +#define ZM_EP0_DATA1_OFFSET 0x0C +#define ZM_EP0_DATA2_OFFSET 0x0D +#define ZM_EP0_DATA_OFFSET 0x0C + +#define ZM_INTR_MASK_BYTE_0_OFFSET 0x11 +#define ZM_INTR_MASK_BYTE_1_OFFSET 0x12 +#define ZM_INTR_MASK_BYTE_2_OFFSET 0x13 +#define ZM_INTR_MASK_BYTE_3_OFFSET 0x14 +#define ZM_INTR_MASK_BYTE_4_OFFSET 0x15 +#define ZM_INTR_MASK_BYTE_5_OFFSET 0x16 +#define ZM_INTR_MASK_BYTE_6_OFFSET 0x17 +#define ZM_INTR_MASK_BYTE_7_OFFSET 0x18 + +#define ZM_INTR_GROUP_OFFSET 0x20 +#define ZM_INTR_SOURCE_0_OFFSET 0x21 +#define ZM_INTR_SOURCE_1_OFFSET 0x22 +#define ZM_INTR_SOURCE_2_OFFSET 0x23 +#define ZM_INTR_SOURCE_3_OFFSET 0x24 +#define ZM_INTR_SOURCE_4_OFFSET 0x25 +#define ZM_INTR_SOURCE_5_OFFSET 0x26 +#define ZM_INTR_SOURCE_6_OFFSET 0x27 +#define ZM_INTR_SOURCE_7_OFFSET 0x28 + +#define ZM_EP_IN_MAX_SIZE_HIGH_OFFSET 0x3F +#define ZM_EP_IN_MAX_SIZE_LOW_OFFSET 0x3E + +#define ZM_EP_OUT_MAX_SIZE_HIGH_OFFSET 0x5F +#define ZM_EP_OUT_MAX_SIZE_LOW_OFFSET 0x5E + +#define ZM_EP3_BYTE_COUNT_HIGH_OFFSET 0xAE +#define ZM_EP3_BYTE_COUNT_LOW_OFFSET 0xBE +#define ZM_EP4_BYTE_COUNT_HIGH_OFFSET 0xAF +#define ZM_EP4_BYTE_COUNT_LOW_OFFSET 0xBF + +#define ZM_EP3_DATA_OFFSET 0xF8 +#define ZM_EP4_DATA_OFFSET 0xFC + +#define ZM_SOC_USB_MODE_CTRL_OFFSET 0x108 +#define ZM_SOC_USB_MAX_AGGREGATE_OFFSET 0x110 +#define ZM_SOC_USB_TIME_CTRL_OFFSET 0x114 + +#define ZM_ADDR_CONV 0x0 + +#define ZM_CBUS_FIFO_SIZE_REG (ZM_CBUS_FIFO_SIZE_OFFSET^ZM_ADDR_CONV) + +#define ZM_CBUS_CTRL_REG (cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET^ZM_ADDR_CONV) + +#define ZM_MAIN_CTRL_REG (ZM_MAIN_CTRL_OFFSET^ZM_ADDR_CONV) + +#define ZM_DEVICE_ADDRESS_REG (ZM_DEVICE_ADDRESS_OFFSET^ZM_ADDR_CONV) + +#define ZM_TEST_REG (ZM_TEST_OFFSET^ZM_ADDR_CONV) + +#define ZM_PHY_TEST_SELECT_REG (ZM_PHY_TEST_SELECT_OFFSET^ZM_ADDR_CONV))) + +#define ZM_CX_CONFIG_STATUS_REG (ZM_CX_CONFIG_STATUS_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP0_DATA1_REG (ZM_EP0_DATA1_OFFSET^ZM_ADDR_CONV))) + +#define ZM_EP0_DATA2_REG (ZM_EP0_DATA2_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP0_DATA_REG (ZM_EP0_DATA_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_0_REG (ZM_INTR_MASK_BYTE_0_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_1_REG (ZM_INTR_MASK_BYTE_1_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_2_REG (ZM_INTR_MASK_BYTE_2_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_3_REG (ZM_INTR_MASK_BYTE_3_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_4_REG (ZM_INTR_MASK_BYTE_4_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_5_REG (ZM_INTR_MASK_BYTE_5_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_6_REG (ZM_INTR_MASK_BYTE_6_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_MASK_BYTE_7_REG (ZM_INTR_MASK_BYTE_7_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_0_REG (ZM_INTR_SOURCE_0_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_1_REG (ZM_INTR_SOURCE_1_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_2_REG (ZM_INTR_SOURCE_2_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_3_REG (ZM_INTR_SOURCE_3_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_4_REG (ZM_INTR_SOURCE_4_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_5_REG (ZM_INTR_SOURCE_5_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_6_REG (ZM_INTR_SOURCE_6_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_SOURCE_7_REG (ZM_INTR_SOURCE_7_OFFSET^ZM_ADDR_CONV) + +#define ZM_INTR_GROUP_REG (ZM_INTR_GROUP_OFFSET^ZM_ADDR_CONV))) + +#define ZM_EP3_BYTE_COUNT_HIGH_REG (ZM_EP3_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP3_BYTE_COUNT_LOW_REG (ZM_EP3_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP4_BYTE_COUNT_HIGH_REG (ZM_EP4_BYTE_COUNT_HIGH_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP4_BYTE_COUNT_LOW_REG (ZM_EP4_BYTE_COUNT_LOW_OFFSET^ZM_ADDR_CONV) + +#define ZM_EP3_DATA_REG (ZM_EP3_DATA_OFFSET) + +#define ZM_EP4_DATA_REG (ZM_EP4_DATA_OFFSET) + +#define ZM_SOC_USB_MODE_CTRL_REG (ZM_SOC_USB_MODE_CTRL_OFFSET) + +#define ZM_SOC_USB_MAX_AGGREGATE_REG (ZM_SOC_USB_MAX_AGGREGATE_OFFSET) + +#define ZM_SOC_USB_TIME_CTRL_REG (ZM_SOC_USB_TIME_CTRL_OFFSET) + +#define bmHIGH_SPEED BIT6 +#define bmCWR_BUF_END BIT1 + +#define mUsbEP0DataRd1() (USB_BYTE_REG_READ(ZM_EP0_DATA1_OFFSET)) +//#define mUsbEP0DataRd2() ZM_EP0_DATA2_REG +//#define mUsbEP0DataRd3() ZM_EP0_DATA3_REG +//#define mUsbEP0DataRd4() ZM_EP0_DATA4_REG +#define mUsbEP0DataWr1(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA1_OFFSET, data)) +#define mUsbEP0DataWr2(data) (USB_BYTE_REG_WRITE(ZM_EP0_DATA2_OFFSET, data)) + +#define mGetByte0(data) ( data & 0xff ) +#define mGetByte1(data) ( (data >> 8) & 0xff ) +#define mGetByte2(data) ( (data >> 16) & 0xff ) +#define mGetByte3(data) ( (data >> 24) & 0xff ) + +//#define mUsbHighSpeedST() (ZM_MAIN_CTRL_REG & BIT6) +//#define mUsbCfgST() (ZM_DEVICE_ADDRESS_REG & BIT7) +//#define mUsbApWrEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END) +//#define mUsbApRdEnd() (ZM_CBUS_CTRL_REG = bmCWR_BUF_END) + +#define mUsbHighSpeedST() (USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET) & BIT6) +#define mUsbCfgST() (USB_BYTE_REG_READ(ZM_DEVICE_ADDRESS_OFFSET) & BIT7) +#define mUsbApWrEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END) +#define mUsbApRdEnd() (USB_BYTE_REG_WRITE((cSOC_USB_OFST+cSOC_CBUS_CTL_OFFSET), bmCWR_BUF_END) + +#define mUsbRmWkupST() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT0) +#define mUsbRmWkupClr() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&~BIT0) +#define mUsbRmWkupSet() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT0) + +#define mUsbGlobIntEnable() USB_BYTE_REG_WRITE(ZM_MAIN_CTRL_OFFSET, \ + USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)|BIT2) + +#define mUSB_REG_OUT_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)&0x3f) +#define mUSB_REG_OUT_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_4_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_4_OFFSET)|0xc0) +#define mUSB_STATUS_IN_INT_ENABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)&0xbf) +#define mUSB_STATUS_IN_INT_DISABLE() USB_BYTE_REG_WRITE(ZM_INTR_MASK_BYTE_6_OFFSET, \ + USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0xc0) +// USB_BYTE_REG_READ(ZM_INTR_MASK_BYTE_6_OFFSET)|0x40) + +#define mUSB_EP3_XFER_DONE() USB_BYTE_REG_WRITE(ZM_EP3_BYTE_COUNT_HIGH_OFFSET, \ + USB_BYTE_REG_READ(ZM_EP3_BYTE_COUNT_HIGH_OFFSET)|0x08) + + + +#define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512 +#define HS_C1_I0_A0_EP1_bInterval 00 + +#define HS_C1_I0_A0_EP_NUMBER 0x06 +#define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER) +#define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH) +#define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH) + +#define HS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + HS_C1_INTERFACE_LENGTH) +#define FS_C1_CONFIG_TOTAL_LENGTH (CONFIG_LENGTH + INTERFACE_LENGTH + FS_C1_INTERFACE_LENGTH) + +#define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64 +//#define FS_C1_I0_A0_EP1_bInterval HS_C1_I0_A0_EP1_bInterval + +#define HS_CONFIGURATION_NUMBER 1 +#define FS_CONFIGURATION_NUMBER 1 + +#define fDOUBLE_BUF 1 +#define fDOUBLE_BUF_IN 1 + +#define fFLASH_DISK 0 +#define fENABLE_ISO 0 + +#if (HS_CONFIGURATION_NUMBER >= 1) + // Configuration 0X01 + #define HS_C1_INTERFACE_NUMBER 0x01 + #define HS_C1 0x01 + #define HS_C1_iConfiguration 0x00 + #define HS_C1_bmAttribute 0x80 + #if !(fFLASH_DISK && !fFLASH_BOOT) + #define HS_C1_iMaxPower 0xFA + #else + #define HS_C1_iMaxPower 0x32 + #endif + + #if (HS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #define HS_C1_I0_ALT_NUMBER 0X01 + #if (HS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0X00 + #define HS_C1_I0_A0_bInterfaceNumber 0X00 + #define HS_C1_I0_A0_bAlternateSetting 0X00 + //JWEI 2003/07/14 + //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT) + #define HS_C1_I0_A0_EP_NUMBER 0x06 + //#else + //#define HS_C1_I0_A0_EP_NUMBER 0X03 + //#endif + #if !(fFLASH_DISK && !fFLASH_BOOT) + #define HS_C1_I0_A0_bInterfaceClass 0XFF + #define HS_C1_I0_A0_bInterfaceSubClass 0X00 + #define HS_C1_I0_A0_bInterfaceProtocol 0X00 + #else + #define HS_C1_I0_A0_bInterfaceClass 0X08 + #define HS_C1_I0_A0_bInterfaceSubClass 0X06 + #define HS_C1_I0_A0_bInterfaceProtocol 0X50 + #endif + #define HS_C1_I0_A0_iInterface 0X00 + + #if (HS_C1_I0_A0_EP_NUMBER >= 1) + //EP0X01 + #define HS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE + //JWEI 2003/05/19 + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP1_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK + //JWEI 2003/05/07 + #define HS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP1_bInterval 00 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 2) + //EP0X02 + #define HS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE + //JWEI 2003/08/20 + #if fDOUBLE_BUF_IN + #define HS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP2_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN + #define HS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK + #define HS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP2_bInterval 00 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 3) + //EP0X03 + #define HS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE + #define HS_C1_I0_A0_EP3_BLKNO SINGLE_BLK + #define HS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN + #define HS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT + #define HS_C1_I0_A0_EP3_MAX_PACKET 0x0040 + #define HS_C1_I0_A0_EP3_bInterval 01 + #endif + // Note: HS Bulk type require max pkt size = 512 + // ==> must use Interrupt type for max pkt size = 64 + #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + //EP0X04 + #define HS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE + #define HS_C1_I0_A0_EP4_BLKNO SINGLE_BLK + #define HS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP4_TYPE TF_TYPE_INTERRUPT + #define HS_C1_I0_A0_EP4_MAX_PACKET 0x0040 + #define HS_C1_I0_A0_EP4_bInterval 01 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 5) + //EP0X04 + #define HS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP5_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK + #define HS_C1_I0_A0_EP5_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP5_bInterval 00 + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 6) + //EP0X04 + #define HS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK + #else + #define HS_C1_I0_A0_EP6_BLKNO SINGLE_BLK + #endif + #define HS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT + #define HS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK + #define HS_C1_I0_A0_EP6_MAX_PACKET MX_PA_SZ_512 + #define HS_C1_I0_A0_EP6_bInterval 00 + #endif + #endif + #endif +#endif + +#if (HS_CONFIGURATION_NUMBER >= 1) + // Configuration 1 + #if (HS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #if (HS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define HS_C1_I0_A0_EP_LENGTH (EP_LENGTH * HS_C1_I0_A0_EP_NUMBER) + #if (HS_C1_I0_A0_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I0_A0_EP1_FIFO_START FIFO0 + #define HS_C1_I0_A0_EP1_FIFO_NO (HS_C1_I0_A0_EP1_BLKNO * HS_C1_I0_A0_EP1_BLKSIZE) + #define HS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP1_BLKNO - 1) << 2) | HS_C1_I0_A0_EP1_TYPE) + #define HS_C1_I0_A0_EP1_FIFO_MAP (((1 - HS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I0_A0_EP1_MAP (HS_C1_I0_A0_EP1_FIFO_START | (HS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP1_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 2) + // EP2 + #if fDOUBLE_BUF + #define HS_C1_I0_A0_EP2_FIFO_START (HS_C1_I0_A0_EP1_FIFO_START + HS_C1_I0_A0_EP1_FIFO_NO) + #else + #define HS_C1_I0_A0_EP2_FIFO_START FIFO2 + #endif + #define HS_C1_I0_A0_EP2_FIFO_NO (HS_C1_I0_A0_EP2_BLKNO * HS_C1_I0_A0_EP2_BLKSIZE) + #define HS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP2_BLKNO - 1) << 2) | HS_C1_I0_A0_EP2_TYPE) + #define HS_C1_I0_A0_EP2_FIFO_MAP (((1 - HS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I0_A0_EP2_MAP (HS_C1_I0_A0_EP2_FIFO_START | (HS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP2_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 3) + // EP3 + //JWEI 2003/07/15 + // #define HS_C1_I0_A0_EP3_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO) + #define HS_C1_I0_A0_EP3_FIFO_START FIFO14 + #define HS_C1_I0_A0_EP3_FIFO_NO (HS_C1_I0_A0_EP3_BLKNO * HS_C1_I0_A0_EP3_BLKSIZE) + #define HS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP3_BLKNO - 1) << 2) | HS_C1_I0_A0_EP3_TYPE) + #define HS_C1_I0_A0_EP3_FIFO_MAP (((1 - HS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I0_A0_EP3_MAP (HS_C1_I0_A0_EP3_FIFO_START | (HS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP3_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + // EP4 + #define HS_C1_I0_A0_EP4_FIFO_START (HS_C1_I0_A0_EP3_FIFO_START + HS_C1_I0_A0_EP3_FIFO_NO) + #define HS_C1_I0_A0_EP4_FIFO_NO (HS_C1_I0_A0_EP4_BLKNO * HS_C1_I0_A0_EP4_BLKSIZE) + #define HS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP4_BLKNO - 1) << 2) | HS_C1_I0_A0_EP4_TYPE) + #define HS_C1_I0_A0_EP4_FIFO_MAP (((1 - HS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4) + #define HS_C1_I0_A0_EP4_MAP (HS_C1_I0_A0_EP4_FIFO_START | (HS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP4_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 5) + // EP5 + #define HS_C1_I0_A0_EP5_FIFO_START (HS_C1_I0_A0_EP2_FIFO_START + HS_C1_I0_A0_EP2_FIFO_NO) + #define HS_C1_I0_A0_EP5_FIFO_NO (HS_C1_I0_A0_EP5_BLKNO * HS_C1_I0_A0_EP5_BLKSIZE) + #define HS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP5_BLKNO - 1) << 2) | HS_C1_I0_A0_EP5_TYPE) + #define HS_C1_I0_A0_EP5_FIFO_MAP (((1 - HS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5) + #define HS_C1_I0_A0_EP5_MAP (HS_C1_I0_A0_EP5_FIFO_START | (HS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP5_DIRECTION))) + #endif + #if (HS_C1_I0_A0_EP_NUMBER >= 6) + // EP5 + #define HS_C1_I0_A0_EP6_FIFO_START (HS_C1_I0_A0_EP5_FIFO_START + HS_C1_I0_A0_EP5_FIFO_NO) + #define HS_C1_I0_A0_EP6_FIFO_NO (HS_C1_I0_A0_EP6_BLKNO * HS_C1_I0_A0_EP6_BLKSIZE) + #define HS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((HS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((HS_C1_I0_A0_EP6_BLKNO - 1) << 2) | HS_C1_I0_A0_EP6_TYPE) + #define HS_C1_I0_A0_EP6_FIFO_MAP (((1 - HS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6) + #define HS_C1_I0_A0_EP6_MAP (HS_C1_I0_A0_EP6_FIFO_START | (HS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A0_EP6_DIRECTION))) + #endif + #endif + + #if (HS_C1_I0_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define HS_C1_I0_A1_EP_LENGTH (EP_LENGTH * HS_C1_I0_A1_EP_NUMBER) + #if (HS_C1_I0_A1_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I0_A1_EP1_FIFO_START FIFO0 + #define HS_C1_I0_A1_EP1_FIFO_NO (HS_C1_I0_A1_EP1_BLKNO * HS_C1_I0_A1_EP1_BLKSIZE) + #define HS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP1_BLKNO - 1) << 2) | HS_C1_I0_A1_EP1_TYPE) + #define HS_C1_I0_A1_EP1_FIFO_MAP (((1 - HS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I0_A1_EP1_MAP (HS_C1_I0_A1_EP1_FIFO_START | (HS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP1_DIRECTION))) + #endif + #if (HS_C1_I0_A1_EP_NUMBER >= 2) + // EP2 + #define HS_C1_I0_A1_EP2_FIFO_START (HS_C1_I0_A1_EP1_FIFO_START + HS_C1_I0_A1_EP1_FIFO_NO) + #define HS_C1_I0_A1_EP2_FIFO_NO (HS_C1_I0_A1_EP2_BLKNO * HS_C1_I0_A1_EP2_BLKSIZE) + #define HS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP2_BLKNO - 1) << 2) | HS_C1_I0_A1_EP2_TYPE) + #define HS_C1_I0_A1_EP2_FIFO_MAP (((1 - HS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I0_A1_EP2_MAP (HS_C1_I0_A1_EP2_FIFO_START | (HS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP2_DIRECTION))) + #endif + #if (HS_C1_I0_A1_EP_NUMBER >= 3) + // EP3 + #define HS_C1_I0_A1_EP3_FIFO_START (HS_C1_I0_A1_EP2_FIFO_START + HS_C1_I0_A1_EP2_FIFO_NO) + #define HS_C1_I0_A1_EP3_FIFO_NO (HS_C1_I0_A1_EP3_BLKNO * HS_C1_I0_A1_EP3_BLKSIZE) + #define HS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I0_A1_EP3_BLKNO - 1) << 2) | HS_C1_I0_A1_EP3_TYPE) + #define HS_C1_I0_A1_EP3_FIFO_MAP (((1 - HS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I0_A1_EP3_MAP (HS_C1_I0_A1_EP3_FIFO_START | (HS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I0_A1_EP3_DIRECTION))) + #endif + #endif + + #if (HS_C1_I0_ALT_NUMBER == 1) + #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH) + #elif (HS_C1_I0_ALT_NUMBER == 2) + #define HS_C1_I0_ALT_LENGTH (HS_C1_I0_A0_EP_LENGTH + HS_C1_I0_A1_EP_LENGTH) + #endif + #endif + + #if (HS_C1_INTERFACE_NUMBER >= 2) + // Interface 1 + #if (HS_C1_I1_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define HS_C1_I1_A0_EP_LENGTH (EP_LENGTH * HS_C1_I1_A0_EP_NUMBER) + #if (HS_C1_I1_A0_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I1_A0_EP1_FIFO_START FIFO0 + #define HS_C1_I1_A0_EP1_FIFO_NO (HS_C1_I1_A0_EP1_BLKNO * HS_C1_I1_A0_EP1_BLKSIZE) + #define HS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP1_BLKNO - 1) << 2) | HS_C1_I1_A0_EP1_TYPE) + #define HS_C1_I1_A0_EP1_FIFO_MAP (((1 - HS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I1_A0_EP1_MAP (HS_C1_I1_A0_EP1_FIFO_START | (HS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP1_DIRECTION))) + #endif + #if (HS_C1_I1_A0_EP_NUMBER >= 2) + // EP2 + #define HS_C1_I1_A0_EP2_FIFO_START (HS_C1_I1_A0_EP1_FIFO_START + HS_C1_I1_A0_EP1_FIFO_NO) + #define HS_C1_I1_A0_EP2_FIFO_NO (HS_C1_I1_A0_EP2_BLKNO * HS_C1_I1_A0_EP2_BLKSIZE) + #define HS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP2_BLKNO - 1) << 2) | HS_C1_I1_A0_EP2_TYPE) + #define HS_C1_I1_A0_EP2_FIFO_MAP (((1 - HS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I1_A0_EP2_MAP (HS_C1_I1_A0_EP2_FIFO_START | (HS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP2_DIRECTION))) + #endif + #if (HS_C1_I1_A0_EP_NUMBER >= 3) + // EP3 + #define HS_C1_I1_A0_EP3_FIFO_START (HS_C1_I1_A0_EP2_FIFO_START + HS_C1_I1_A0_EP2_FIFO_NO) + #define HS_C1_I1_A0_EP3_FIFO_NO (HS_C1_I1_A0_EP3_BLKNO * HS_C1_I1_A0_EP3_BLKSIZE) + #define HS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A0_EP3_BLKNO - 1) << 2) | HS_C1_I1_A0_EP3_TYPE) + #define HS_C1_I1_A0_EP3_FIFO_MAP (((1 - HS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I1_A0_EP3_MAP (HS_C1_I1_A0_EP3_FIFO_START | (HS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A0_EP3_DIRECTION))) + #endif + #endif + + #if (HS_C1_I1_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define HS_C1_I1_A1_EP_LENGTH (EP_LENGTH * HS_C1_I1_A1_EP_NUMBER) + #if (HS_C1_I1_A1_EP_NUMBER >= 1) + // EP1 + #define HS_C1_I1_A1_EP1_FIFO_START FIFO0 + #define HS_C1_I1_A1_EP1_FIFO_NO (HS_C1_I1_A1_EP1_BLKNO * HS_C1_I1_A1_EP1_BLKSIZE) + #define HS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP1_BLKNO - 1) << 2) | HS_C1_I1_A1_EP1_TYPE) + #define HS_C1_I1_A1_EP1_FIFO_MAP (((1 - HS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1) + #define HS_C1_I1_A1_EP1_MAP (HS_C1_I1_A1_EP1_FIFO_START | (HS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP1_DIRECTION))) + #endif + #if (HS_C1_I1_A1_EP_NUMBER >= 2) + // EP2 + #define HS_C1_I1_A1_EP2_FIFO_START (HS_C1_I1_A1_EP1_FIFO_START + HS_C1_I1_A1_EP1_FIFO_NO) + #define HS_C1_I1_A1_EP2_FIFO_NO (HS_C1_I1_A1_EP2_BLKNO * HS_C1_I1_A1_EP2_BLKSIZE) + #define HS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP2_BLKNO - 1) << 2) | HS_C1_I1_A1_EP2_TYPE) + #define HS_C1_I1_A1_EP2_FIFO_MAP (((1 - HS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2) + #define HS_C1_I1_A1_EP2_MAP (HS_C1_I1_A1_EP2_FIFO_START | (HS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP2_DIRECTION))) + #endif + #if (HS_C1_I1_A1_EP_NUMBER >= 3) + // EP3 + #define HS_C1_I1_A1_EP3_FIFO_START (HS_C1_I1_A1_EP2_FIFO_START + HS_C1_I1_A1_EP2_FIFO_NO) + #define HS_C1_I1_A1_EP3_FIFO_NO (HS_C1_I1_A1_EP3_BLKNO * HS_C1_I1_A1_EP3_BLKSIZE) + #define HS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((HS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((HS_C1_I1_A1_EP3_BLKNO - 1) << 2) | HS_C1_I1_A1_EP3_TYPE) + #define HS_C1_I1_A1_EP3_FIFO_MAP (((1 - HS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3) + #define HS_C1_I1_A1_EP3_MAP (HS_C1_I1_A1_EP3_FIFO_START | (HS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*HS_C1_I1_A1_EP3_DIRECTION))) + #endif + #endif + + #if (HS_C1_I1_ALT_NUMBER == 1) + #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH) + #elif (HS_C1_I1_ALT_NUMBER == 2) + #define HS_C1_I1_ALT_LENGTH (HS_C1_I1_A0_EP_LENGTH + HS_C1_I1_A1_EP_LENGTH) + #endif + #endif + + #if (HS_C1_INTERFACE_NUMBER == 1) + #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH) + #elif (HS_C1_INTERFACE_NUMBER == 2) + #define HS_C1_INTERFACE_LENGTH (HS_C1_I0_ALT_LENGTH + HS_C1_I1_ALT_LENGTH) + #endif +#endif + +#if (FS_CONFIGURATION_NUMBER >= 1) + // Configuration 0X01 + #define FS_C1_INTERFACE_NUMBER 0X01 + #define FS_C1 0X01 + #define FS_C1_iConfiguration 0X00 + #define FS_C1_bmAttribute 0X80 + #define FS_C1_iMaxPower 0XFA + + #if (FS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #define FS_C1_I0_ALT_NUMBER 0X01 + #if (FS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0X00 + #define FS_C1_I0_A0_bInterfaceNumber 0X00 + #define FS_C1_I0_A0_bAlternateSetting 0X00 + //JWEI 2003/07/14 + //#if fINDEPEND_REG_RW && !(fFLASH_DISK && !fFLASH_BOOT) + #define FS_C1_I0_A0_EP_NUMBER 0x05 + //#else + //#define FS_C1_I0_A0_EP_NUMBER 0X03 + //#endif + #if !(fFLASH_DISK && !fFLASH_BOOT) + #define FS_C1_I0_A0_bInterfaceClass 0XFF + #define FS_C1_I0_A0_bInterfaceSubClass 0X00 + #define FS_C1_I0_A0_bInterfaceProtocol 0X00 + #else + #define FS_C1_I0_A0_bInterfaceClass 0X08 + #define FS_C1_I0_A0_bInterfaceSubClass 0X06 + #define FS_C1_I0_A0_bInterfaceProtocol 0X50 + #endif + #define FS_C1_I0_A0_iInterface 0X00 + + #if (FS_C1_I0_A0_EP_NUMBER >= 1) + //EP0X01 + #define FS_C1_I0_A0_EP1_BLKSIZE BLK512BYTE + //JWEI 2003/05/19 + #if fDOUBLE_BUF + #define FS_C1_I0_A0_EP1_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP1_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP1_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP1_TYPE TF_TYPE_BULK + //JWEI 2003/05/07 + #define FS_C1_I0_A0_EP1_MAX_PACKET MX_PA_SZ_64 + #define FS_C1_I0_A0_EP1_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 2) + //EP0X02 + #define FS_C1_I0_A0_EP2_BLKSIZE BLK512BYTE + //JWEI 2003/08/20 + #if fDOUBLE_BUF_IN + #define FS_C1_I0_A0_EP2_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP2_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP2_DIRECTION DIRECTION_IN + #define FS_C1_I0_A0_EP2_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP2_MAX_PACKET MX_PA_SZ_64 + #define FS_C1_I0_A0_EP2_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 3) + //EP0X03 + #define FS_C1_I0_A0_EP3_BLKSIZE BLK64BYTE + #define FS_C1_I0_A0_EP3_BLKNO SINGLE_BLK + #define FS_C1_I0_A0_EP3_DIRECTION DIRECTION_IN + #define FS_C1_I0_A0_EP3_TYPE TF_TYPE_INTERRUPT + #define FS_C1_I0_A0_EP3_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP3_bInterval 01 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + //EP0X04 + #define FS_C1_I0_A0_EP4_BLKSIZE BLK64BYTE + #define FS_C1_I0_A0_EP4_BLKNO SINGLE_BLK + #define FS_C1_I0_A0_EP4_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP4_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP4_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP4_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 5) + //EP0X04 + #define FS_C1_I0_A0_EP5_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF_IN + #define FS_C1_I0_A0_EP5_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP5_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP5_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP5_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP5_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP5_bInterval 00 + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 6) + //EP0X04 + #define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE + #if fDOUBLE_BUF_IN + #define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK + #else + #define FS_C1_I0_A0_EP6_BLKNO SINGLE_BLK + #endif + #define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT + #define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK + #define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040 + #define FS_C1_I0_A0_EP6_bInterval 00 + #endif + #endif + #endif +#endif + +#if (FS_CONFIGURATION_NUMBER >= 1) + // Configuration 1 + #if (FS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + #if (FS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define FS_C1_I0_A0_EP_LENGTH (EP_LENGTH * FS_C1_I0_A0_EP_NUMBER) + #if (FS_C1_I0_A0_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I0_A0_EP1_FIFO_START FIFO0 + #define FS_C1_I0_A0_EP1_FIFO_NO (FS_C1_I0_A0_EP1_BLKNO * FS_C1_I0_A0_EP1_BLKSIZE) + #define FS_C1_I0_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP1_BLKNO - 1) << 2) | FS_C1_I0_A0_EP1_TYPE) + #define FS_C1_I0_A0_EP1_FIFO_MAP (((1 - FS_C1_I0_A0_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I0_A0_EP1_MAP (FS_C1_I0_A0_EP1_FIFO_START | (FS_C1_I0_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP1_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I0_A0_EP2_FIFO_START (FS_C1_I0_A0_EP1_FIFO_START + FS_C1_I0_A0_EP1_FIFO_NO) + #define FS_C1_I0_A0_EP2_FIFO_NO (FS_C1_I0_A0_EP2_BLKNO * FS_C1_I0_A0_EP2_BLKSIZE) + #define FS_C1_I0_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP2_BLKNO - 1) << 2) | FS_C1_I0_A0_EP2_TYPE) + #define FS_C1_I0_A0_EP2_FIFO_MAP (((1 - FS_C1_I0_A0_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I0_A0_EP2_MAP (FS_C1_I0_A0_EP2_FIFO_START | (FS_C1_I0_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP2_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 3) + // EP3 + //JWEI 2003/07/15 + // #define FS_C1_I0_A0_EP3_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO) + #define FS_C1_I0_A0_EP3_FIFO_START FIFO14 + #define FS_C1_I0_A0_EP3_FIFO_NO (FS_C1_I0_A0_EP3_BLKNO * FS_C1_I0_A0_EP3_BLKSIZE) + #define FS_C1_I0_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP3_BLKNO - 1) << 2) | FS_C1_I0_A0_EP3_TYPE) + #define FS_C1_I0_A0_EP3_FIFO_MAP (((1 - FS_C1_I0_A0_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I0_A0_EP3_MAP (FS_C1_I0_A0_EP3_FIFO_START | (FS_C1_I0_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP3_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 4) || fFLASH_DISK + // EP4 + #define FS_C1_I0_A0_EP4_FIFO_START (FS_C1_I0_A0_EP3_FIFO_START + FS_C1_I0_A0_EP3_FIFO_NO) + #define FS_C1_I0_A0_EP4_FIFO_NO (FS_C1_I0_A0_EP4_BLKNO * FS_C1_I0_A0_EP4_BLKSIZE) + #define FS_C1_I0_A0_EP4_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP4_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP4_BLKNO - 1) << 2) | FS_C1_I0_A0_EP4_TYPE) + #define FS_C1_I0_A0_EP4_FIFO_MAP (((1 - FS_C1_I0_A0_EP4_DIRECTION) << 4) | EP4) + #define FS_C1_I0_A0_EP4_MAP (FS_C1_I0_A0_EP4_FIFO_START | (FS_C1_I0_A0_EP4_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP4_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 5) + // EP5 + #define FS_C1_I0_A0_EP5_FIFO_START (FS_C1_I0_A0_EP2_FIFO_START + FS_C1_I0_A0_EP2_FIFO_NO) + #define FS_C1_I0_A0_EP5_FIFO_NO (FS_C1_I0_A0_EP5_BLKNO * FS_C1_I0_A0_EP5_BLKSIZE) + #define FS_C1_I0_A0_EP5_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP5_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP5_BLKNO - 1) << 2) | FS_C1_I0_A0_EP5_TYPE) + #define FS_C1_I0_A0_EP5_FIFO_MAP (((1 - FS_C1_I0_A0_EP5_DIRECTION) << 4) | EP5) + #define FS_C1_I0_A0_EP5_MAP (FS_C1_I0_A0_EP5_FIFO_START | (FS_C1_I0_A0_EP5_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP5_DIRECTION))) + #endif + #if (FS_C1_I0_A0_EP_NUMBER >= 6) + // EP5 + #define FS_C1_I0_A0_EP6_FIFO_START (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO) + #define FS_C1_I0_A0_EP6_FIFO_NO (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE) + #define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE) + #define FS_C1_I0_A0_EP6_FIFO_MAP (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6) + #define FS_C1_I0_A0_EP6_MAP (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION))) + #endif + #endif + + #if (FS_C1_I0_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define FS_C1_I0_A1_EP_LENGTH (EP_LENGTH * FS_C1_I0_A1_EP_NUMBER) + #if (FS_C1_I0_A1_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I0_A1_EP1_FIFO_START FIFO0 + #define FS_C1_I0_A1_EP1_FIFO_NO (FS_C1_I0_A1_EP1_BLKNO * FS_C1_I0_A1_EP1_BLKSIZE) + #define FS_C1_I0_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP1_BLKNO - 1) << 2) | FS_C1_I0_A1_EP1_TYPE) + #define FS_C1_I0_A1_EP1_FIFO_MAP (((1 - FS_C1_I0_A1_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I0_A1_EP1_MAP (FS_C1_I0_A1_EP1_FIFO_START | (FS_C1_I0_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP1_DIRECTION))) + #endif + #if (FS_C1_I0_A1_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I0_A1_EP2_FIFO_START (FS_C1_I0_A1_EP1_FIFO_START + FS_C1_I0_A1_EP1_FIFO_NO) + #define FS_C1_I0_A1_EP2_FIFO_NO (FS_C1_I0_A1_EP2_BLKNO * FS_C1_I0_A1_EP2_BLKSIZE) + #define FS_C1_I0_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP2_BLKNO - 1) << 2) | FS_C1_I0_A1_EP2_TYPE) + #define FS_C1_I0_A1_EP2_FIFO_MAP (((1 - FS_C1_I0_A1_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I0_A1_EP2_MAP (FS_C1_I0_A1_EP2_FIFO_START | (FS_C1_I0_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP2_DIRECTION))) + #endif + #if (FS_C1_I0_A1_EP_NUMBER >= 3) + // EP3 + #define FS_C1_I0_A1_EP3_FIFO_START (FS_C1_I0_A1_EP2_FIFO_START + FS_C1_I0_A1_EP2_FIFO_NO) + #define FS_C1_I0_A1_EP3_FIFO_NO (FS_C1_I0_A1_EP3_BLKNO * FS_C1_I0_A1_EP3_BLKSIZE) + #define FS_C1_I0_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I0_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I0_A1_EP3_BLKNO - 1) << 2) | FS_C1_I0_A1_EP3_TYPE) + #define FS_C1_I0_A1_EP3_FIFO_MAP (((1 - FS_C1_I0_A1_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I0_A1_EP3_MAP (FS_C1_I0_A1_EP3_FIFO_START | (FS_C1_I0_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A1_EP3_DIRECTION))) + #endif + #endif + + #if (FS_C1_I0_ALT_NUMBER == 1) + #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH) + #elif (FS_C1_I0_ALT_NUMBER == 2) + #define FS_C1_I0_ALT_LENGTH (FS_C1_I0_A0_EP_LENGTH + FS_C1_I0_A1_EP_LENGTH) + #endif + #endif + + #if (FS_C1_INTERFACE_NUMBER >= 2) + // Interface 1 + #if (FS_C1_I1_ALT_NUMBER >= 1) + // AlternateSetting 0 + #define FS_C1_I1_A0_EP_LENGTH (EP_LENGTH * FS_C1_I1_A0_EP_NUMBER) + #if (FS_C1_I1_A0_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I1_A0_EP1_FIFO_START FIFO0 + #define FS_C1_I1_A0_EP1_FIFO_NO (FS_C1_I1_A0_EP1_BLKNO * FS_C1_I1_A0_EP1_BLKSIZE) + #define FS_C1_I1_A0_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP1_BLKNO - 1) << 2) | FS_C1_I1_A0_EP1_TYPE) + #define FS_C1_I1_A0_EP1_FIFO_MAP (((1 - FS_C1_I1_A0_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I1_A0_EP1_MAP (FS_C1_I1_A0_EP1_FIFO_START | (FS_C1_I1_A0_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP1_DIRECTION))) + #endif + #if (FS_C1_I1_A0_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I1_A0_EP2_FIFO_START (FS_C1_I1_A0_EP1_FIFO_START + FS_C1_I1_A0_EP1_FIFO_NO) + #define FS_C1_I1_A0_EP2_FIFO_NO (FS_C1_I1_A0_EP2_BLKNO * FS_C1_I1_A0_EP2_BLKSIZE) + #define FS_C1_I1_A0_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP2_BLKNO - 1) << 2) | FS_C1_I1_A0_EP2_TYPE) + #define FS_C1_I1_A0_EP2_FIFO_MAP (((1 - FS_C1_I1_A0_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I1_A0_EP2_MAP (FS_C1_I1_A0_EP2_FIFO_START | (FS_C1_I1_A0_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP2_DIRECTION))) + #endif + #if (FS_C1_I1_A0_EP_NUMBER >= 3) + // EP3 + #define FS_C1_I1_A0_EP3_FIFO_START (FS_C1_I1_A0_EP2_FIFO_START + FS_C1_I1_A0_EP2_FIFO_NO) + #define FS_C1_I1_A0_EP3_FIFO_NO (FS_C1_I1_A0_EP3_BLKNO * FS_C1_I1_A0_EP3_BLKSIZE) + #define FS_C1_I1_A0_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A0_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A0_EP3_BLKNO - 1) << 2) | FS_C1_I1_A0_EP3_TYPE) + #define FS_C1_I1_A0_EP3_FIFO_MAP (((1 - FS_C1_I1_A0_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I1_A0_EP3_MAP (FS_C1_I1_A0_EP3_FIFO_START | (FS_C1_I1_A0_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A0_EP3_DIRECTION))) + #endif + #endif + + #if (FS_C1_I1_ALT_NUMBER >= 2) + // AlternateSetting 1 + #define FS_C1_I1_A1_EP_LENGTH (EP_LENGTH * FS_C1_I1_A1_EP_NUMBER) + #if (FS_C1_I1_A1_EP_NUMBER >= 1) + // EP1 + #define FS_C1_I1_A1_EP1_FIFO_START FIFO0 + #define FS_C1_I1_A1_EP1_FIFO_NO (FS_C1_I1_A1_EP1_BLKNO * FS_C1_I1_A1_EP1_BLKSIZE) + #define FS_C1_I1_A1_EP1_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP1_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP1_BLKNO - 1) << 2) | FS_C1_I1_A1_EP1_TYPE) + #define FS_C1_I1_A1_EP1_FIFO_MAP (((1 - FS_C1_I1_A1_EP1_DIRECTION) << 4) | EP1) + #define FS_C1_I1_A1_EP1_MAP (FS_C1_I1_A1_EP1_FIFO_START | (FS_C1_I1_A1_EP1_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP1_DIRECTION))) + #endif + #if (FS_C1_I1_A1_EP_NUMBER >= 2) + // EP2 + #define FS_C1_I1_A1_EP2_FIFO_START (FS_C1_I1_A1_EP1_FIFO_START + FS_C1_I1_A1_EP1_FIFO_NO) + #define FS_C1_I1_A1_EP2_FIFO_NO (FS_C1_I1_A1_EP2_BLKNO * FS_C1_I1_A1_EP2_BLKSIZE) + #define FS_C1_I1_A1_EP2_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP2_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP2_BLKNO - 1) << 2) | FS_C1_I1_A1_EP2_TYPE) + #define FS_C1_I1_A1_EP2_FIFO_MAP (((1 - FS_C1_I1_A1_EP2_DIRECTION) << 4) | EP2) + #define FS_C1_I1_A1_EP2_MAP (FS_C1_I1_A1_EP2_FIFO_START | (FS_C1_I1_A1_EP2_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP2_DIRECTION))) + #endif + #if (FS_C1_I1_A1_EP_NUMBER >= 3) + // EP3 + #define FS_C1_I1_A1_EP3_FIFO_START (FS_C1_I1_A1_EP2_FIFO_START + FS_C1_I1_A1_EP2_FIFO_NO) + #define FS_C1_I1_A1_EP3_FIFO_NO (FS_C1_I1_A1_EP3_BLKNO * FS_C1_I1_A1_EP3_BLKSIZE) + #define FS_C1_I1_A1_EP3_FIFO_CONFIG (0x80 | ((FS_C1_I1_A1_EP3_BLKSIZE - 1) << 4) | ((FS_C1_I1_A1_EP3_BLKNO - 1) << 2) | FS_C1_I1_A1_EP3_TYPE) + #define FS_C1_I1_A1_EP3_FIFO_MAP (((1 - FS_C1_I1_A1_EP3_DIRECTION) << 4) | EP3) + #define FS_C1_I1_A1_EP3_MAP (FS_C1_I1_A1_EP3_FIFO_START | (FS_C1_I1_A1_EP3_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I1_A1_EP3_DIRECTION))) + #endif + #endif + + #if (FS_C1_I1_ALT_NUMBER == 1) + #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH) + #elif (FS_C1_I1_ALT_NUMBER == 2) + #define FS_C1_I1_ALT_LENGTH (FS_C1_I1_A0_EP_LENGTH + FS_C1_I1_A1_EP_LENGTH) + #endif + #endif + + #if (FS_C1_INTERFACE_NUMBER == 1) + #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH) + #elif (FS_C1_INTERFACE_NUMBER == 2) + #define FS_C1_INTERFACE_LENGTH (FS_C1_I0_ALT_LENGTH + HS_FS_C1_I1_ALT_LENGTH) + #endif +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT0)) // upstream DMA enable + +#define USB_DISABLE_UP_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))) // upstream DMA disable + +#define USB_UP_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))) // upQ stream mode + +#define USB_UP_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT3)) // upQ packet mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT1)) // lp downstream DMA enable + +#define USB_DISABLE_LP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))) // lp downstream DMA disable + +#define USB_LP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT6))) // lpQ packet mode + +#define USB_LP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6)) // lpQ stream mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8)) // hp downstream DMA enable + +#define USB_DISABLE_HP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT8))) // hp downstream DMA disable + +#define USB_HP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT7))) // hpQ packet mode + +#define USB_HP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT7)) // hpQ stream mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9)) // mp downstream DMA enable + +#define USB_DISABLE_MP_DN_DMA() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT9))) // mp downstream DMA disable + +#define USB_MP_DN_PACKET_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT10))) // hpQ packet mode + +#define USB_MP_DN_STREAM_MODE() USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT10)) // hpQ stream mode + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define USB_ENABLE_UP_PACKET_MODE() USB_DISABLE_UP_DMA(); \ + USB_UP_PACKET_MODE(); \ + USB_ENABLE_UP_DMA(); + +#define USB_ENABLE_LP_DN_PACKET_MODE() USB_DISABLE_LP_DN_DMA(); \ + USB_LP_DN_PACKET_MODE(); \ + USB_ENABLE_LP_DN_DMA() + +#define USB_ENABLE_MP_DN_PACKET_MODE() USB_DISABLE_MP_DN_DMA(); \ + USB_MP_DN_PACKET_MODE(); \ + USB_ENABLE_MP_DN_DMA(); + +#define USB_ENABLE_HP_DN_PACKET_MODE() USB_DISABLE_HP_DN_DMA(); \ + USB_HP_DN_PACKET_MODE(); \ + USB_ENABLE_HP_DN_DMA(); + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define USB_ENABLE_UP_STREAM_MODE() USB_DISABLE_UP_DMA(); \ + USB_UP_STREAM_MODE(); \ + USB_ENABLE_UP_DMA(); + +#define USB_ENABLE_LP_DN_STREAM_MODE() USB_DISABLE_LP_DN_DMA(); \ + USB_LP_DN_STREAM_MODE(); \ + USB_ENABLE_LP_DN_DMA() + +#define USB_ENABLE_MP_DN_STREAM_MODE() USB_DISABLE_MP_DN_DMA(); \ + USB_MP_DN_STREAM_MODE(); \ + USB_ENABLE_MP_DN_DMA(); + +#define USB_ENABLE_HP_DN_STREAM_MODE() USB_DISABLE_HP_DN_DMA(); \ + USB_HP_DN_STREAM_MODE(); \ + USB_ENABLE_HP_DN_DMA(); + +#define USB_STREAM_HOST_BUF_SIZE(size) USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(size))); +#define USB_STREAM_TIMEOUT(time_cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, time_cnt); // set stream mode timeout critirea +#define USB_STREAM_AGG_PKT_CNT(cnt) USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, cnt); // set stream mode packet buffer critirea + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/usb_extr.h b/target_firmware/magpie_fw_dev/target/inc/k2/usb_extr.h new file mode 100755 index 0000000..1886800 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/usb_extr.h @@ -0,0 +1,34 @@ +#ifndef USB_EXTR_H +#define USB_EXTR_H + +#if 0 +#include "dt_defs.h" +#include "usb_type.h" + +/* Variable for USB EP0 pipe (USB.c) */ +uint16_t *pu8DescriptorEX; +uint16_t u16TxRxCounter; +uint16_t *u8ConfigDescriptorEX; +//extern BOOLEAN bUsbEP0HaltSt; +Action eUsbCxFinishAction; +CommandType eUsbCxCommand; +BOOLEAN UsbChirpFinish; +uint16_t u8UsbConfigValue; +uint16_t u8UsbInterfaceValue; +uint16_t u8UsbInterfaceAlternateSetting; +uint16_t u16FirmwareComplete; + +uint16_t *UsbDeviceDescriptor; +uint16_t *String00Descriptor; +uint16_t *String10Descriptor; +uint16_t *String20Descriptor; +uint16_t *String30Descriptor; +uint16_t *u8DeviceQualifierDescriptorEX; +uint16_t *u8OtherSpeedConfigDescriptorEX; +uint16_t *u8UsbDeviceDescriptor; +uint16_t *u8String00Descriptor; +uint16_t *u8String10Descriptor; +uint16_t *u8String20Descriptor; +uint16_t *u8String30Descriptor; +#endif +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/usb_pre.h b/target_firmware/magpie_fw_dev/target/inc/k2/usb_pre.h new file mode 100755 index 0000000..b63e3a9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/usb_pre.h @@ -0,0 +1,99 @@ +#ifndef __USB_USER_PRE_H +#define __USB_USER_PRE_H + +#define FUSB200_MAX_EP 10 // 1..10 +#define FUSB200_MAX_FIFO 10 // 0.. 9 +#define EP0MAXPACKETSIZE 0x40 +// #define EP0FIFOSIZE 64 // EP0_FIFO +//JWEI 2003/04/29 +//#define EP0MAXPACKETSIZE 0x08 + +// Max. Packet Size define +#define MX_PA_SZ_8 8 +#define MX_PA_SZ_16 16 +#define MX_PA_SZ_32 32 +#define MX_PA_SZ_64 64 +#define MX_PA_SZ_128 128 +#define MX_PA_SZ_256 256 +#define MX_PA_SZ_512 512 +#define MX_PA_SZ_1024 1024 + +#define MASK_F0 0xF0 + +// Block Size define +#define BLK512BYTE 1 +#define BLK1024BYTE 2 + +#define BLK64BYTE 1 +#define BLK128BYTE 2 + +// Block toggle number define +#define SINGLE_BLK 1 +#define DOUBLE_BLK 2 +#define TRIBLE_BLK 3 + +// Endpoint transfer type +#define TF_TYPE_ISOCHRONOUS 1 +#define TF_TYPE_BULK 2 +#define TF_TYPE_INTERRUPT 3 + +// Endpoint or FIFO direction define +#define DIRECTION_IN 0 +#define DIRECTION_OUT 1 + +// FIFO number define +#define FIFO0 0x0 +#define FIFO1 0x1 +#define FIFO2 0x2 +#define FIFO3 0x3 +#define FIFO4 0x4 +#define FIFO5 0x5 +#define FIFO6 0x6 +#define FIFO7 0x7 +#define FIFO8 0x8 +#define FIFO9 0x9 +#define FIFO10 10 +#define FIFO11 11 +#define FIFO12 12 +#define FIFO13 13 +#define FIFO14 14 +#define FIFO15 15 + +// Descriptor Table uses the following parameters : fixed +#define DEVICE_LENGTH 0x12 +#define CONFIG_LENGTH 0x09 +#define INTERFACE_LENGTH 0x09 +#define EP_LENGTH 0x07 +#define DEVICE_QUALIFIER_LENGTH 0x0A + +//JWEI 2003/04/29 +// Endpoint number define +#define EP0 0 +#define EP1 1 +#define EP2 2 +#define EP3 3 +#define EP4 4 +#define EP5 5 +#define EP6 6 +#define EP7 7 +#define EP8 8 +#define EP9 9 +#define EP10 10 +#define EP11 11 +#define EP12 12 +#define EP13 13 +#define EP14 14 +#define EP15 15 + +#define STRING_00_LENGTH 0x04 +#define STRING_10_LENGTH 0x0c +#define STRING_20_LENGTH 0x18 +#define STRING_30_LENGTH 0x18 +#define STRING_40_LENGTH 0x04 +#define STRING_50_LENGTH 0x04 +#define STRING_60_LENGTH 0x04 +#define STRING_70_LENGTH 0x04 +#define STRING_80_LENGTH 0x04 +#define STRING_90_LENGTH 0x00 + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/usb_std.h b/target_firmware/magpie_fw_dev/target/inc/k2/usb_std.h new file mode 100755 index 0000000..7272eaf --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/usb_std.h @@ -0,0 +1,106 @@ +#ifndef USB_STD_H +#define USB_STD_H + +#define mDEV_REQ_REQ_DIR() (ControlCmd.Direction) +#define mDEV_REQ_REQ_TYPE() (ControlCmd.Type) +#define mDEV_REQ_REQ_RECI() (ControlCmd.Object) +#define mDEV_REQ_REQ() (ControlCmd.Request) +#define mDEV_REQ_VALUE() (ControlCmd.Value) +#define mDEV_REQ_VALUE_LOW() (mLOW_BYTE(mDEV_REQ_VALUE())) +#define mDEV_REQ_VALUE_HIGH() (mHIGH_BYTE(mDEV_REQ_VALUE())) +#define mDEV_REQ_INDEX() (ControlCmd.Index) +#define mDEV_REQ_LENGTH() (ControlCmd.Length) + +/******************** USB Protocol Definition *************************/ +/* Standard Request Code (Table 9-4) */ +#define USB_GET_STATUS 0 +#define USB_CLEAR_FEATURE 1 +#define USB_SET_FEATURE 3 +#define USB_SET_ADDRESS 5 +#define USB_GET_DESCRIPTOR 6 +#define USB_SET_DESCRIPTOR 7 +#define USB_GET_CONFIGURATION 8 +#define USB_SET_CONFIGURATION 9 +#define USB_GET_INTERFACE 10 +#define USB_SET_INTERFACE 11 +#define USB_SYNCH_FRAME 12 + +/* Descriptor Type (Table 9-5) */ +#define USB_DESC_TYPE_DEVICE 1 +#define USB_DESC_TYPE_CONFIG 2 +#define USB_DESC_TYPE_STRING 3 +#define USB_DESC_TYPE_INTERFACE 4 +#define USB_DESC_TYPE_ENDPOINT 5 + +/* Endpoint Attribute (Table 9-10) */ +#define USB_EP_ATTR_CTRL 0 +#define USB_EP_ATTR_ISOCH 1 +#define USB_EP_ATTR_BULK 2 +#define USB_EP_ATTR_INTRPT 3 + +/*********************** for USB 2.0 **********************************/ +// Table 9-5. Descriptor Types +#define DT_DEVICE 1 +#define DT_CONFIGURATION 2 +#define DT_STRING 3 +#define DT_INTERFACE 4 +#define DT_ENDPOINT 5 +#define DT_DEVICE_QUALIFIER 6 +#define DT_OTHER_SPEED_CONFIGURATION 7 +#define DT_INTERFACE_POWER 8 + +/**********************************************************************/ +// Values for bmAttributes Field in USB_CONFIGURATION_DESCRIPTOR +#define USB_BUS_POWERED 0x80 +#define USB_SELF_POWERED 0x40 +#define USB_REMOTE_WAKEUP 0x20 + +#define cUSB_REQTYPE_DIR_POS 7 +#define cUSB_REQTYPE_DIR_LEN 1 +#define cUSB_REQTYPE_TYPE_POS 5 +#define cUSB_REQTYPE_TYPE_LEN 2 +#define cUSB_REQTYPE_RX_POS 0 +#define cUSB_REQTYPE_RX_LEN 5 + +/* for USB State */ +#define cUSB_DEFAULT_STATE 0 +#define cUSB_ADDRESS_STATE 1 +#define cUSB_CONFIG_STATE 2 + +/* for Data transfer direction */ +#define bmUSB_HOST_DIR 7 /* Bit 7 */ +#define cUSB_DIR_HOST_OUT 0 +#define cUSB_DIR_HOST_IN 1 + +/* for Type */ +#define cUSB_REQTYPE_STD 0 +#define cUSB_REQTYPE_CLASS 1 +#define cUSB_REQTYPE_VENDOR 2 + +/* for Recipient */ +#define cUSB_REQTYPE_DEVICE 0 +#define cUSB_REQTYPE_INTERFACE 1 +#define cUSB_REQTYPE_ENDPOINT 2 +#define cUSB_REQTYPE_OTHER 3 + +/* for Descriptor Type */ +#define cUSB_DESTYPE_DEVICE 1 +#define cUSB_DESTYPE_CONFIG 2 +#define cUSB_DESTYPE_STRING 3 +#define cUSB_DESTYPE_INTERFACE 4 +#define cUSB_DESTYPE_ENDPOINT 5 +#define cUSB_DESTYPE_END cUSB_DESTYPE_ENDPOINT // for range check + +/* for Feature selector */ +#define cUSB_FEATSEL_RMWAKEUP 0 +#define cUSB_FEATSEL_EPHAL 1 +#define cUSB_FEATSEL_END cUSB_FEATSEL_EPHAL // for range check + +#define bmREQ_RECI 0 +#define bmwREQ_RECI 5 // mMASKS(bmwREQ_RECI, bmREQ_RECI) +#define bmREQ_TYPE 5 +#define bmwREQ_TYPE 2 // mMASKS(bmwREQ_TYPE, bmREQ_TYPE) +#define bmREQ_DIR 7 +#define bmwREQ_DIR 1 + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/usb_table.h b/target_firmware/magpie_fw_dev/target/inc/k2/usb_table.h new file mode 100755 index 0000000..0f0278f --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/usb_table.h @@ -0,0 +1,138 @@ +#ifndef _USB_TABLE_H_ +#define _USB_TABLE_H_ + +#include "sys_cfg.h" +// UsbDeviceDescriptor +#define USB_DEVICE_DESC_TYPE 0x01 +#define USB_DEVICE_DESC_LEN 0x12 +#define USB_SPEC_VERSION 0x0200 +#define USB_DEVICE_CLASS 0xFF +#define USB_DEVICE_SUB_CLASS 0xFF +#define USB_DEVICE_PROTOCOL 0xFF +#define USB_MAX_PKT_SIZE 0x40 +#define USB_VENDOR_ID 0x0CF3 +#define USB_PRODUCT_ID 0x9271 + +#if 1 /* USB Device Descriptor : byte 12, 13 Device BCD -> Device release number in binary-coded decimal. */ +#define USB_DEVICE_BCD BOOTROM_VER +#else +#define USB_DEVICE_BCD 0x0106 +#endif + +#define USB_MANUFACTURER_INDEX 0x10 +#define USB_PRODUCT_INDEX 0x20 +#define USB_SERIAL_INDEX 0x30 +#define USB_CONFIGURATION_NUM 0x01 +// end UsbDeviceDescriptor + +#define USB_CONFIG_DESC_TYPE 0x02 +#define USB_CONFIG_DESC_LEN 0x09 +//#define USB_TOTAL_DESC_LEN 0x002E // 4 ep +//#define USB_TOTAL_DESC_LEN 0x0035 // 5 ep +#define USB_TOTAL_DESC_LEN 0x003C // 6 ep +#define USB_INTERFACE_NUM 0x01 +#define USB_CONFIG_NUM 0x01 +#define USB_STRING_INDEX 0x00 +#define USB_ATTRIBUTE 0x80 +#define USB_MAX_POWER 0xFA + +#define USB_INTERFACE_DESC_TYPE 0x04 +#define USB_INTERFACE_DESC_LEN 0x09 +#define USB_INTERFACE_INDEX_NUM 0x00 +#define USB_INTERFACE_ALT_SETTING 0x00 +//#define USB_INTERFACE_EP_NUM 0x04 +//#define USB_INTERFACE_EP_NUM 0x05 +#define USB_INTERFACE_EP_NUM 0x06 +#define USB_INTERFACE_CLASS 0xFF +#define USB_INTERFACE_SUB_CLASS 0x00 +#define USB_INTERFACE_PROTOCOL 0x00 +#define USB_INTERFACE_STRING_INDEX 0x00 + +#define USB_EP_DESC_TYPE 0x05 +#define USB_EP_DESC_LEN 0x07 + +/* USB Endpoint attribute */ +#define bUSB_EP1_NUM 0x01 +#define bUSB_EP2_NUM 0x02 +#define bUSB_EP3_NUM 0x03 +#define bUSB_EP4_NUM 0x04 +#define bUSB_EP5_NUM 0x05 +#define bUSB_EP6_NUM 0x06 + +#define bUSB_EP_DIRECTION_IN 0x80 +#define bUSB_EP_DIRECTION_OUT 0x00 + +#define bUSB_EP_TYPE_CONTROL 0x00 +#define bUSB_EP_TYPE_ISOCHRONOUS 0x01 +#define bUSB_EP_TYPE_BULK 0x02 +#define bUSB_EP_TYPE_INTERRUPT 0x03 + +#define bUSB_EP_MAX_PKT_SIZE_64 0x0040 +#define bUSB_EP_MAX_PKT_SIZE_512 0x0200 + +/* High Speed Endpoint */ +#define USB_HS_EP1_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP1_NUM) +#define USB_HS_EP1_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP1_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP1_INTERVAL 0x00 + +#define USB_HS_EP2_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP2_NUM) +#define USB_HS_EP2_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP2_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP2_INTERVAL 0x00 + +#define USB_HS_EP3_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP3_NUM) +#define USB_HS_EP3_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT +#define USB_HS_EP3_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_HS_EP3_INTERVAL 0x01 + +#define USB_HS_EP4_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP4_NUM) +#define USB_HS_EP4_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT //bUSB_EP_TYPE_BULK +#define USB_HS_EP4_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_HS_EP4_INTERVAL 0x01 //0x00 + +#define USB_HS_EP5_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP5_NUM) +#define USB_HS_EP5_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP5_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP5_INTERVAL 0x00 + +#define USB_HS_EP6_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP6_NUM) +#define USB_HS_EP6_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_HS_EP6_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_512 +#define USB_HS_EP6_INTERVAL 0x00 + +/* Full Speed Endpoint */ +#define USB_FS_EP1_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP1_NUM) +#define USB_FS_EP1_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP1_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP1_INTERVAL 0x00 + +#define USB_FS_EP2_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP2_NUM) +#define USB_FS_EP2_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP2_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP2_INTERVAL 0x00 + +#define USB_FS_EP3_ADDRESS (bUSB_EP_DIRECTION_IN | bUSB_EP3_NUM) +#define USB_FS_EP3_ATTRIBUTE bUSB_EP_TYPE_INTERRUPT +#define USB_FS_EP3_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP3_INTERVAL 0x01 + +#define USB_FS_EP4_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP4_NUM) +#define USB_FS_EP4_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP4_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP4_INTERVAL 0x00 + +#define USB_FS_EP5_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP5_NUM) +#define USB_FS_EP5_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP5_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP5_INTERVAL 0x00 + +#define USB_FS_EP6_ADDRESS (bUSB_EP_DIRECTION_OUT | bUSB_EP6_NUM) +#define USB_FS_EP6_ATTRIBUTE bUSB_EP_TYPE_BULK +#define USB_FS_EP6_MAX_PACKET_SIZE bUSB_EP_MAX_PKT_SIZE_64 +#define USB_FS_EP6_INTERVAL 0x00 + +//#define USB_QUALIFIER_DESC_ADDR 0x8cff00 +//#define USB_OTHER_SPEED_DESC_ADDR 0x8cffA + +#endif // end of _USB_TABLE_H_ diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/usb_type.h b/target_firmware/magpie_fw_dev/target/inc/k2/usb_type.h new file mode 100755 index 0000000..7e31478 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/usb_type.h @@ -0,0 +1,60 @@ +#ifndef USB_TYPE_H +#define USB_TYPE_H + +#include "dt_defs.h" + +/*********************** for Faraday USB controller *******************/ +typedef enum +{ + CMD_VOID, // No command + CMD_GET_DESCRIPTOR, // Get_Descriptor command + CMD_SET_DESCRIPTOR // Set_Descriptor command +} CommandType; + +typedef enum +{ + ACT_IDLE, + ACT_DONE, + ACT_STALL +} Action; + +typedef struct Setup_Packet +{ + uint8_t Direction; /* Data transfer direction: IN, OUT */ + uint8_t Type; /* Request Type: Standard, Class, Vendor */ + uint8_t Object; /* Recipient: Device, Interface, Endpoint,other */ + uint16_t Request; /* Refer to Table 9-3 */ + uint16_t Value; + uint16_t Index; + uint16_t Length; +} SetupPacket; + +#define mBIT(b) (1 << (b)) +#define mMASK(w) (mBIT(w) - 1) + +#define mWORD_IDX(bsize) ((bsize) >> 1) +#define mWORD_SIZE(bsize) (((bsize) + 1) >> 1) + +#define mTABLE_WID mWORD_SIZE +#define mTABLE_IDX mWORD_IDX +#define mTABLE_LEN mLOW_BYTE + +#define mLOW_MASK(u16) ((uint8_t) ((u16) & mMASK(8))) +#define mHIGH_MASK(u16) ((uint8_t) ((u16) & ~mMASK(8))) +#define mLOW2HIGH(u16) (((uint8_t) (u16)) << 8) + +/* (1234) -> 0034 */ +//#define mLOW_BYTE(u16) ((U_8)(u16)) +#define mLOW_BYTE(u16) mLOW_MASK(u16) +/* (1234) -> 0012 */ +#define mHIGH_BYTE(u16) ((uint8_t) (((uint16_t) (u16)) >> 8)) + +#define mGET_REG1(var0, reg0) { var0 = reg0; } + +/* (1234, 5678) -> 7834 */ +#define m2BYTE(ch1L, ch2H) (mLOW_MASK(ch1L) | mLOW2HIGH(ch2H)) + +#define mREAD_WORD(var0, reg0, reg1) \ + { var0 = reg0; var0 += mLOW2HIGH(reg1); } + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/usbfifo_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/usbfifo_api.h new file mode 100755 index 0000000..08c4644 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/usbfifo_api.h @@ -0,0 +1,43 @@ +/* + * @File: HIF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _USB_FIFO_API_H +#define _USB_FIFO_API_H + +#include "vbuf_api.h" + +typedef struct _USB_FIFO_CONFIG { + /* callback to get the buf for receiving commands from USB FIFO */ + VBUF* (*get_command_buf)(void); + /* callback when receiving a command */ + void (*recv_command)(VBUF *cmd); + /* callback to get the buf for event to send to the host */ + VBUF* (*get_event_buf)(void); + /* callback to indicate the event has been sent to the host */ + void (*send_event_done)(VBUF *buf); + + /* context used for all callbacks */ + //void *context; +} USB_FIFO_CONFIG; + +/* hardware API table structure (API descriptions below) */ +struct usbfifo_api { + void (*_init)(USB_FIFO_CONFIG *pConfig); + void (*_enable_event_isr)(void); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void usbfifo_module_install(struct usbfifo_api *apis); + +#endif /* #ifndef _USB_FIFO_API_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/vbuf_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/vbuf_api.h new file mode 100755 index 0000000..7c35fc6 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/vbuf_api.h @@ -0,0 +1,44 @@ +/* + * @File: VBUF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _VBUF_API_H +#define _VBUF_API_H + +#include + +#define MAX_BUF_CTX_LEN 20 + +typedef struct _VBUF +{ + VDESC *desc_list; + struct _VBUF *next_buf; + A_UINT16 buf_length; + A_UINT8 reserved[2]; + A_UINT8 ctx[MAX_BUF_CTX_LEN]; +} VBUF; + +#define VBUF_GET_DATA_ADDR(vbuf) (vbuf->desc_list->buf_addr + vbuf->desc_list->data_offset) + +/* hardware API table structure (API descriptions below) */ +struct vbuf_api { + void (*_init)(int nBuf); + VBUF* (*_alloc_vbuf)(void); + VBUF* (*_alloc_vbuf_with_size)(int size, int reserve); + void (*_free_vbuf)(VBUF *buf); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void vbuf_module_install(struct vbuf_api *apis); + +#endif /* #ifndef _HIF_API_H */ diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/vdesc_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/vdesc_api.h new file mode 100755 index 0000000..09219f9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/vdesc_api.h @@ -0,0 +1,43 @@ +/* + * @File: VBUF_api.h + * + * @Abstract: Host Interface api + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _VDESC_API_H +#define _VDESC_API_H + +#define MAX_HW_DESC_SIZE 20 + +typedef struct _VDESC +{ + struct _VDESC *next_desc; + A_UINT8 *buf_addr; + A_UINT16 buf_size; + A_UINT16 data_offset; + A_UINT16 data_size; + A_UINT16 control; + A_UINT8 hw_desc_buf[MAX_HW_DESC_SIZE]; +} VDESC; + +#define VDESC_HW_TO_VDESC(hwdesc) ((VDESC *)(((A_UINT32 *)hwdesc - 4))) + +struct vdesc_api { + void (*_init)(int nDesc); + VDESC* (*_alloc_vdesc)(); + A_UINT8* (*_get_hw_desc)(VDESC *desc); + void (*_swap_vdesc)(VDESC *dest, VDESC *src); + + /* room to expand this table by another table */ + void *pReserved; +}; + +extern void vdesc_module_install(struct vdesc_api *apis); + +#endif diff --git a/target_firmware/magpie_fw_dev/target/inc/k2/wdt_api.h b/target_firmware/magpie_fw_dev/target/inc/k2/wdt_api.h new file mode 100755 index 0000000..8b5a820 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/k2/wdt_api.h @@ -0,0 +1,51 @@ +#ifndef __WDT_API_H__ +#define __WDT_API_H__ + +typedef enum { + WDT_ACTION_NO = 0, // bit1, bit0: 00 + WDT_ACTION_INTR, // bit1, bit0: 01 + WDT_ACTION_NMI, // bit1, bit0: 10 + WDT_ACTION_RESET, // bit1, bit0: 11 + + WDT_ACTION_UNKNOWN +} T_WDT_ACTION_TYPE; + +typedef enum { + WDT_TIMEOUT = 1, + WDT_ACTION, + + WDT_UNKNOWN +} T_WDT_CMD_TYPE; + +typedef struct { + uint32_t cmd; + union { + uint32_t timeout; + uint32_t action; + }; +}T_WDT_CMD; + +typedef enum { + ENUM_WDT_BOOT = 1, + ENUM_COLD_BOOT, + ENUM_SUSP_BOOT, + + // add above here + ENUM_UNKNOWN_BOOT +} T_BOOT_TYPE; + + +/*!- interface of watchdog timer + * + */ +struct wdt_api { + void (* _wdt_init)(void); + void (* _wdt_enable)(void); + void (* _wdt_disable)(void); + void (* _wdt_set)(T_WDT_CMD); + void (* _wdt_task)(void); + void (* _wdt_reset)(void); + T_BOOT_TYPE (*_wdt_last_boot)(void); +}; +#endif /* __WDT_API_H__ */ + diff --git a/target_firmware/magpie_fw_dev/target/inc/osapi.h b/target_firmware/magpie_fw_dev/target/inc/osapi.h new file mode 100755 index 0000000..06e84d6 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/inc/osapi.h @@ -0,0 +1,201 @@ +#ifndef __OSAPI_H__ +#define __OSAPI_H__ + +#define A_COMPILE_TIME_ASSERT(assertion_name, predicate) \ + typedef char assertion_name[(predicate) ? 1 : -1]; + +#if !defined(LOCAL) +#if 0 /* At least for now, simplify debugging. */ +#define LOCAL static +#else +#define LOCAL +#endif +#endif + +#if !defined(NULL) +#define NULL (void *)0 +#endif + +#if !defined(FALSE) +#define FALSE 0 +#endif + +#if !defined(TRUE) +#define TRUE 1 +#endif + +#ifdef __GNUC__ +#define __ATTRIB_PACK __attribute__ ((packed)) +#define __ATTRIB_PRINTF __attribute__ ((format (printf, 1, 2))) +#define __ATTRIB_NORETURN __attribute__ ((noreturn)) +#define __ATTRIB_ALIGN(x) __attribute__ ((aligned((x)))) +#define INLINE __inline__ +#else /* Not GCC */ +#define __ATTRIB_PACK +#define __ATTRIB_PRINTF +#define __ATTRIB_NORETURN +#define __ATTRIB_ALIGN(x) +#define INLINE __inline +#endif /* End __GNUC__ */ + +#define PREPACK +#define POSTPACK __ATTRIB_PACK + +/* Utility macros */ +#define A_SWAB32(_x) ( \ + ((A_UINT32)( \ + (((A_UINT32)(_x) & (A_UINT32)0x000000ffUL) << 24) | \ + (((A_UINT32)(_x) & (A_UINT32)0x0000ff00UL) << 8) | \ + (((A_UINT32)(_x) & (A_UINT32)0x00ff0000UL) >> 8) | \ + (((A_UINT32)(_x) & (A_UINT32)0xff000000UL) >> 24) )) \ +) + +#define A_SWAB16(_x) \ + ((A_UINT16)( \ + (((A_UINT16)(_x) & (A_UINT16)0x00ffU) << 8) | \ + (((A_UINT16)(_x) & (A_UINT16)0xff00U) >> 8) )) + +/* unaligned little endian access */ +#define A_LE_READ_2(p) \ + ((A_UINT16)( \ + (((A_UINT8 *)(p))[0]) | (((A_UINT8 *)(p))[1] << 8))) + +#define A_LE_READ_4(p) \ + ((A_UINT32)( \ + (((A_UINT8 *)(p))[0] ) | (((A_UINT8 *)(p))[1] << 8) | \ + (((A_UINT8 *)(p))[2] << 16) | (((A_UINT8 *)(p))[3] << 24))) + +#define A_LE64_TO_CPU(_x) ((A_UINT64)(_x)) +#define A_LE32_TO_CPU(_x) ((A_UINT32)(_x)) +#define A_CPU_TO_LE32(_x) ((A_UINT32)(_x)) +#define A_BE32_TO_CPU(_x) A_SWAB32(_x) +#define A_CPU_TO_BE32(_x) A_SWAB32(_x) +#define A_LE16_TO_CPU(_x) ((A_UINT16)(_x)) +#define A_CPU_TO_LE16(_x) ((A_UINT16)(_x)) +#define A_BE16_TO_CPU(_x) A_SWAB16(_x) +#define A_CPU_TO_BE16(_x) A_SWAB16(_x) + + +#define A_LE32TOH(_x) A_LE32_TO_CPU(_x) +#define A_HTOLE32(_x) A_CPU_TO_LE32(_x) +#define A_BE32TOH(_x) A_BE32_TO_CPU(_x) +#define A_HTOBE32(_x) A_CPU_TO_BE32(_x) +#define A_LE16TOH(_x) A_LE16_TO_CPU(_x) +#define A_HTOLE16(_x) A_CPU_TO_LE16(_x) +#define A_BE16TOH(_x) A_BE16_TO_CPU(_x) +#define A_HTOBE16(_x) A_CPU_TO_BE16(_x) + +#define A_MAX(x, y) (((x) > (y)) ? (x) : (y)) +#define A_MIN(x, y) (((x) < (y)) ? (x) : (y)) +#define A_ABS(x) (((x) >= 0) ? (x) : (-(x))) +#define A_ROUND_UP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +#define A_ROUND_UP_PAD(x, y) (A_ROUND_UP(x, y) - (x)) +#define A_ROUND_UP_PWR2(x, align) (((int) (x) + ((align)-1)) & ~((align)-1)) +#define A_ROUND_DOWN_PWR2(x, align) ((int)(x) & ~((align)-1)) + +#define A_TOLOWER(c) (((c) >= 'A' && (c) <= 'Z') ? ((c)-'A'+'a') : (c)) +#define A_TOUPPER(c) (((c) >= 'a' && (c) <= 'z') ? ((c)-'a'+'A') : (c)) + +#define A_ARRAY_NUM_ENTRIES(a) (sizeof(a)/sizeof(*(a))) +#define A_FIELD_OFFSET(type, field) ((int)(&((type *)0)->field)) + +#define A_MSECS_PER_SECOND 1000 /* Milliseconds */ +#define A_USECS_PER_SECOND 1000000 /* Microseconds */ +#define A_NSECS_PER_SECOND 1000000000 /* Nanoseconds */ + +/* + * Intentional Misaligned Load special "addresses". + * Loads from misaligned addresses have special semantics, + * handled by the OS, depending on the lower nibble. + * + * NOTE1: word-aligned nibbles will not cause any exception, + * so they must not be used. + * + * NOTE2: On AR6002, the Xtensa CPU may issue a load speculatively. + * If this load accesses an unmapped region of SOC (such as the + * lower 4KB), AR6002 hardware generates an Address Error interrupt + * even before the instruction has actually executed and therefore + * before it has a chance to generate the expected Misaligned Load + * error. To avoid this, we make these IML accesses be to an address + * range that is valid....ROM. + */ +#if 0 +#define IML_SIGNAL_UNUSED0_ADDR TARG_ROM_ADDRS(0) /* Cannot be used -- aligned */ +#define IML_SIGNAL_ASSERT_ADDR TARG_ROM_ADDRS(1) /* Signal an assertion failure */ +#define IML_SIGNAL_PRINTF_ADDR TARG_ROM_ADDRS(2) /* Signal a printf request */ +#define IML_SIGNAL_UNUSED4_ADDR TARG_ROM_ADDRS(4) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSED8_ADDR TARG_ROM_ADDRS(8) /* Cannot be used -- aligned */ +#define IML_SIGNAL_UNUSEDC_ADDR TARG_ROM_ADDRS(0xc) /* Cannot be used -- aligned */ +#define IML_SIGNAL_MASK 0xfffe000f +#define IML_LINENUM_SHIFT 4 +#endif + +#ifdef HTC_TRACE_MBOX_PAUSE +#define A_ASSERT( __bool ) +#else +/* + * Code space dedicated to asserts is minimal. We use an Intentional + * Misaligned Load to signal an assert failure. We embed the line + * number in the misaligned address as a debugging aid. This may + * make it a bit more difficult to recognize a bona fide misaligned + * load, but that's an acceptable tradeoff. + * + * Bits 3..0 encodes the IML_SIGNAL_* number. + * Bits 16..4 encode the LINE number of the ASSERTion. + * Upper nibbles are the start of ROM. + */ +#if defined(__XTENSA__) +#define _A_BARRIER asm volatile("memw") +#else +#define _A_BARRIER +#endif +#define A_ASSERT( __bool ) \ + do { \ + if (0 == (__bool)) { \ + (void)*((volatile int *)(IML_SIGNAL_ASSERT_ADDR+(__LINE__<<4)));\ + _A_BARRIER; \ + } \ + } while (0) +#endif + +#define A_IML_IS_ASSERT(vaddr) \ + (((vaddr) & IML_SIGNAL_MASK) == (IML_SIGNAL_ASSERT_ADDR & IML_SIGNAL_MASK)) + +/* + * The A_ASSERT macro encodes line number in the Intentionally Misaligned + * Address that it uses to signal a failure. This macro extracts that + * line number information. + * + * Note: ASSERTs up to line 8191 (13 bits) of a file are supported. + * Beyond that an assertion failure appears as a misaligned load. + */ +#define A_IML_ASSLINE(vaddr) (((vaddr) & ~IML_SIGNAL_MASK) >> IML_LINENUM_SHIFT) + +/* Prevent compiler code movement */ +#define A_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) + +/* + * Some general system settings may depend on which wireless band is + * to be used. For example, on AR6K the system PLL setting is + * band-dependent. + * + * These constants are used with A_WLAN_BAND_SET. + */ +#define A_BAND_24GHZ 0 +#define A_BAND_5GHZ 1 +#define A_NUM_BANDS 2 + +#define OTUS + +#if defined(AR6K) +//#include +#elif defined(OTUS) +#include +#else +#error "Unsupported platform" +#endif + + +//#include "os/athos_api.h" + +#endif /* __OSAPI_H__ */ diff --git a/target_firmware/magpie_fw_dev/target/init/app_start.c b/target_firmware/magpie_fw_dev/target/init/app_start.c new file mode 100644 index 0000000..5a4b754 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/init/app_start.c @@ -0,0 +1,276 @@ +#include "dt_defs.h" +#include "athos_api.h" + +#include "regdump.h" +#include "usb_defs.h" + +#include "init.h" +// @TODO: Should define the memory region later~ +#define ALLOCRAM_START ( ((unsigned int)&_fw_image_end) + 4) +#define ALLOCRAM_SIZE ( SYS_RAM_SZIE - ( ALLOCRAM_START - SYS_D_RAM_REGION_0_BASE) - SYS_D_RAM_STACK_SIZE) + +// support for more than 64 bytes on command pipe +extern void vUsb_Reg_Out_patch(void); +extern int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe); +extern void _HIFusb_isr_handler_patch(hif_handle_t h); +extern BOOLEAN bSet_configuration_patch(void); +extern void vUSBFIFO_EP6Cfg_FS_patch(void); +extern void vUsb_Status_In_patch(void); +extern void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig); +extern void zfTurnOffPower_patch(void); +extern void zfResetUSBFIFO_patch(void); +extern void _HIFusb_start_patch(hif_handle_t handle); +extern void hif_pci_patch_install(struct hif_api *apis); +extern BOOLEAN bGet_descriptor_patch(void); +extern BOOLEAN bStandardCommand_patch(void); + +// patch for clock +extern void cmnos_clock_init_patch(a_uint32_t refclk); +extern a_uint32_t cmnos_refclk_speed_get_patch(void); +extern void cmnos_delay_us_patch(int us); +extern void cmnos_tick_patch(void); +extern a_uint32_t cmnos_milliseconds_patch(void); + +extern BOOLEAN bJumptoFlash; +extern BOOLEAN bEepromExist; +void app_start() +{ + uint32_t rst_status; + A_HOSTIF hostif; +#if defined(PROJECT_MAGPIE) + T_EEP_RET retEEP; +#endif + + /* Zero BSS segment & dynamic memory section. */ + init_mem(); + +#if defined(PROJECT_MAGPIE) + fatal_exception_func(); +#endif + + if( IS_FLASHBOOT() ) { + athos_indirection_table_install(); + DBG_MODULE_INSTALL(); + A_CLOCK_INIT(SYSTEM_CLK); + A_UART_INIT(); + A_PRINTF_INIT(); + A_DBG_INIT(); + A_EEP_INIT(); + A_TASKLET_INIT(); + _indir_tbl.cmnos.timer._timer_init(); + +#if defined(PROJECT_K2) + /* + * WAR: these variable is not initialized when boot from flash + * either re-enumeration or config them to default value = 0 would fix the issue + */ + u8UsbInterfaceAlternateSetting = u8UsbConfigValue = u8UsbInterfaceValue = 0; +#endif + } +#ifdef ROM_VER_1_1 + else + A_EEP_INIT(); /*Required for 1_1*/ +#endif + +#if defined(PROJECT_MAGPIE) + retEEP = A_EEP_IS_EXIST(); + bJumptoFlash = FALSE; + if ( RET_SUCCESS == retEEP ) { + bEepromExist = TRUE; + } else { + bEepromExist = FALSE; + } +#endif + + hostif = A_IS_HOST_PRESENT(); + +#if defined(PROJECT_MAGPIE) + rst_status = *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR); +#elif defined(PROJECT_K2) + rst_status = HAL_WORD_REG_READ(MAGPIE_REG_RST_STATUS_ADDR); +#endif /* #if defined(PROJECT_MAGPIE) */ + + + A_PRINTF(" A_WDT_INIT()\n\r"); + +#if defined(PROJECT_K2) + save_cmnos_printf = (uint32_t) fw_cmnos_printf; +#endif + + if( hostif == HIF_USB ) { +#if defined(PROJECT_K2) +#if MOVE_PRINT_TO_RAM + save_cmnos_printf = (uint32_t) _indir_tbl.cmnos.printf._printf; + _indir_tbl.cmnos.printf._printf = fw_cmnos_printf; +#endif + _indir_tbl.cmnos.usb._usb_fw_task = _fw_usb_fw_task; + _indir_tbl.cmnos.usb._usb_reset_fifo = _fw_usb_reset_fifo; +#endif + } + + if( rst_status == WDT_MAGIC_PATTERN ) { + A_PRINTF(" ==>WDT reset<==\n"); +#if defined(PROJECT_MAGPIE) + reset_EP4_FIFO(); +#endif + *((volatile uint32_t*)WATCH_DOG_RESET_COUNTER_ADDR)+=1; + } else if (rst_status == SUS_MAGIC_PATTERN) { + A_PRINTF(" ==>warm start<==\n"); + } else + A_PRINTF(" ==>cold start<==\n"); + +#if defined(PROJECT_MAGPIE) + *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR)=WDT_MAGIC_PATTERN; +#elif defined(PROJECT_K2) + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_STATUS_ADDR, WDT_MAGIC_PATTERN); +#endif /* #if defined(PROJECT_MAGPIE) */ + + /* intr enable would left for firmware */ + /* athos_interrupt_init(); */ + + DBG_MODULE_INSTALL(); +#if defined(PROJECT_K2) + A_DBG_INIT(); +#endif + +#if defined(PROJECT_K2) +#if SYSTEM_MODULE_SFLASH + SFLASH_MODULE_INSTALL(); + A_SFLASH_INIT(); +#endif +#endif + + HIF_MODULE_INSTALL(); + HTC_MODULE_INSTALL(); + WMI_SERVICE_MODULE_INSTALL(); + BUF_POOL_MODULE_INSTALL(); + VBUF_MODULE_INSTALL(); + VDESC_MODULE_INSTALL(); + + //init each module, should be put together.. + A_PRINTF("ALLOCRAM start 0x%x size %d\n", ALLOCRAM_START, ALLOCRAM_SIZE); + A_ALLOCRAM_INIT(ALLOCRAM_START, ALLOCRAM_SIZE); + + if( hostif == HIF_USB ) { + _indir_tbl.hif._get_max_msg_len = _HIFusb_get_max_msg_len_patch; + _indir_tbl.cmnos.usb._usb_reg_out = vUsb_Reg_Out_patch; + _indir_tbl.hif._isr_handler = _HIFusb_isr_handler_patch; + _indir_tbl.cmnos.usb._usb_set_configuration = bSet_configuration_patch; + _indir_tbl.cmnos.usb._usb_status_in = vUsb_Status_In_patch; + _indir_tbl.cmnos.usb._usb_get_descriptor = bGet_descriptor_patch; + _indir_tbl.cmnos.usb._usb_standard_cmd = bStandardCommand_patch; + _indir_tbl.usbfifo_api._init = _fw_usbfifo_init; + +#if defined(PROJECT_MAGPIE) + _indir_tbl.cmnos.usb._usb_power_off = zfTurnOffPower_patch; + _indir_tbl.cmnos.usb._usb_reset_fifo = zfResetUSBFIFO_patch; + _indir_tbl.hif._start = _HIFusb_start_patch; + _indir_tbl.htc._HTC_MsgRecvHandler = HTCMsgRecvHandler_patch; + _indir_tbl.htc._HTC_ControlSvcProcessMsg = HTCControlSvcProcessMsg_patch; +#endif + + if (!(USB_BYTE_REG_READ(ZM_MAIN_CTRL_OFFSET)&BIT6)) { + vUSBFIFO_EP6Cfg_FS_patch(); + } + +#ifdef FUSION_USB_ENABLE_TX_STREAM + // For K2, enable tx stream mode + A_PRINTF("Enable Tx Stream mode\r\n"); + + // Patch for K2 USB STREAM mode + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT0))); // disable down stream DMA mode + + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, + ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT6))); + +#if SYSTEM_MODULE_HP_EP5 + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, + ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT8))); +#endif + +#if SYSTEM_MODULE_HP_EP6 + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, + ((USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|BIT9))); +#endif + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT0))); // enable down stream DMA mode +#endif + +#ifdef FUSION_USB_ENABLE_RX_STREAM + // Patch for K2 USB STREAM mode + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT1))); // disable upstream DMA mode + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(~BIT3))); // enable upstream stream mode + + // K2, Set maximum IN transfer to 8K + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)&(0xcf))); + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, \ + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(0x20))); + + USB_WORD_REG_WRITE(ZM_SOC_USB_MODE_CTRL_OFFSET, + (USB_WORD_REG_READ(ZM_SOC_USB_MODE_CTRL_OFFSET)|(BIT1))); // enable upstream DMA mode + + USB_WORD_REG_WRITE(ZM_SOC_USB_TIME_CTRL_OFFSET, 0xa0); // set stream mode timeout critirea +#if defined(PROJECT_K2) + /*0x10004020 is vaild in k2 but could be invaild in other chip*/ + if ((HAL_WORD_REG_READ(0x10004020) & 0x2000) != 0) { + /* disable stream mode for AR9270 */ + USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 0); + } else { + /* enable stream mode for AR9271 */ + USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9); + } +#else + USB_WORD_REG_WRITE(ZM_SOC_USB_MAX_AGGREGATE_OFFSET, 9); +#endif +#endif + } +#if defined(PROJECT_MAGPIE) && !defined(ROM_VER_1_1) + else if (hostif == HIF_PCI ) + hif_pci_patch_install(&_indir_tbl.hif); +#endif + + // patch the clock function + if(1) { + _indir_tbl.cmnos.clock._clock_init = cmnos_clock_init_patch; + _indir_tbl.cmnos.clock._refclk_speed_get = cmnos_refclk_speed_get_patch; + _indir_tbl.cmnos.clock._delay_us = cmnos_delay_us_patch; + _indir_tbl.cmnos.clock._clock_tick = cmnos_tick_patch; + _indir_tbl.cmnos.clock._milliseconds = cmnos_milliseconds_patch; + + //default clock, setup initial variable, SYSTEM_FREQ=40 + A_CLOCK_INIT(SYSTEM_FREQ); + } + + Magpie_init(); + +#if MAGPIE_ENABLE_WLAN == 1 + + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)&(~(BIT10|BIT8|BIT7|BIT6)))); +#if defined(PROJECT_MAGPIE) + HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT1)); +#endif + + wlan_pci_module_init(); + wlan_pci_probe(); +#endif + + + A_PRINTF("Tgt running\n\r"); + +#if defined(PROJECT_MAGPIE) + if(1) { + A_PRINTF("======= Apply MISC Assert patch\n\r"); + _assfail_ori = _indir_tbl.cmnos.misc._assfail; + _indir_tbl.cmnos.misc._assfail = exception_reset; + } + + change_magpie_clk(); +#endif + wlan_task(); //never return +} diff --git a/target_firmware/magpie_fw_dev/target/init/init.c b/target_firmware/magpie_fw_dev/target/init/init.c new file mode 100755 index 0000000..922cf6a --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/init/init.c @@ -0,0 +1,365 @@ +#if defined(_RAM_) + +#include "athos_api.h" + +#if defined(PROJECT_MAGPIE) +#include "regdump.h" +#include "usb_defs.h" +extern uint32_t *init_htc_handle; +uint8_t htc_complete_setup = 0; +void reset_EP4_FIFO(void); +#endif +#include "init.h" + +void Magpie_init(void); + + +#if defined(PROJECT_MAGPIE) +extern BOOLEAN bEepromExist; +extern BOOLEAN bJumptoFlash; +#endif + +static uint32_t loop_low, loop_high; + +// reference idle count at the beginning +uint32_t idle_cnt = 0; + +#if defined(PROJECT_K2) +// save the ROM printf function point +uint32_t save_cmnos_printf; +#endif + +#define ATH_DATE_STRING __DATE__" "__TIME__ + +static void idle_task(); + +#if defined(PROJECT_MAGPIE) +void fatal_exception_func() +{ + // patch for execption + (void)_xtos_set_exception_handler(EXCCAUSE_UNALIGNED, AR6002_fatal_exception_handler_patch); + (void)_xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_ERROR, AR6002_fatal_exception_handler_patch); + (void)_xtos_set_exception_handler(EXCCAUSE_ILLEGAL, AR6002_fatal_exception_handler_patch); + (void)_xtos_set_exception_handler(EXCCAUSE_INSTR_ERROR, AR6002_fatal_exception_handler_patch); + (void)_xtos_set_exception_handler(EXCCAUSE_PRIVILEGED, AR6002_fatal_exception_handler_patch); + (void)_xtos_set_exception_handler(EXCCAUSE_INSTR_DATA_ERROR, AR6002_fatal_exception_handler_patch); + (void)_xtos_set_exception_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, AR6002_fatal_exception_handler_patch); + (void)_xtos_set_exception_handler(EXCCAUSE_DIVIDE_BY_ZERO, AR6002_fatal_exception_handler_patch); +} +#endif + +#if defined(PROJECT_MAGPIE) +void +change_magpie_clk(void) +{ + volatile uint32_t i=0, rd_data; + + HAL_WORD_REG_WRITE(0x00056004, 0x11); + rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1; + + /* Wait for the update bit to get cleared */ + while (rd_data) + rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1; + + /* Put the PLL into reset */ + rd_data = HAL_WORD_REG_READ(0x00050010) | (1<<1); + HAL_WORD_REG_WRITE(0x00050010,rd_data); + + /* + * XXX: statically set the CPU clock to 200Mhz + */ + /* Setting of the PLL */ + HAL_WORD_REG_WRITE(0x00056000, 0x325);//400 MHz + + /* Pull CPU PLL out of Reset */ + rd_data = HAL_WORD_REG_READ(0x00050010) & ~(1<<1); + HAL_WORD_REG_WRITE(0x00050010,rd_data); + + A_DELAY_USECS(60); // wait for stable + + /* CPU & AHB settings */ + /* + * AHB clk = ( CPU clk / 2 ) + */ + HAL_WORD_REG_WRITE(0x00056004, ((0x00001 | (1 << 16)|(1 << 8)))); // set plldiv to 2 + rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1; + + while (rd_data) + rd_data = HAL_WORD_REG_READ(0x00056004) & 0x1; + + /* UART Setting */ + A_UART_HWINIT((100*1000*1000), 115200); + +} + +void exception_reset(struct register_dump_s *dump) +{ + A_PRINTF("exception_reset \n"); + + /* phase I dump info */ + A_PRINTF("exception reset-phase 1\n"); + if(_assfail_ori) + _assfail_ori(dump); + + /* phase II reset */ + A_PRINTF("exception reset-phase 2\n"); + *((volatile uint32_t*)WATCH_DOG_MAGIC_PATTERN_ADDR) = WDT_MAGIC_PATTERN; + + HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, + HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)|(BIT10|BIT8|BIT7|BIT6)); + + HAL_WORD_REG_WRITE(MAGPIE_REG_AHB_ARB_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_AHB_ARB_ADDR)|BIT1)); + + HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x0); + HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|BIT4); + A_DELAY_USECS(5); + HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)&~BIT4); + A_DELAY_USECS(5); + HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x1); + + // set clock to bypass mode - 40Mhz from XTAL + HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); + A_DELAY_USECS(100); // wait for stable + HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16)); + + A_UART_HWINIT((40*1000*1000), 115200); + + A_PRINTF("do TX/RX swap\n"); + + MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; + MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; + + A_PRINTF("Jump to BOOT\n"); + + // reboot..... + A_USB_JUMP_BOOT(); +} + +void reset_EP4_FIFO(void) +{ + int i; + + // reset EP4 FIFO + USB_BYTE_REG_WRITE(ZM_EP4_BYTE_COUNT_HIGH_OFFSET, (USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_HIGH_OFFSET) | BIT4)); + for(i = 0; i < 100; i++) {} + USB_BYTE_REG_WRITE(ZM_EP4_BYTE_COUNT_HIGH_OFFSET, (USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_HIGH_OFFSET) & ~BIT4)); +} + +LOCAL void zfGenExceptionEvent(uint32_t exccause, uint32_t pc, uint32_t badvaddr) +{ + uint32_t pattern = 0x33221199; + + A_PRINTF("Tgt Drv send an event 44332211 to Host Drv\n"); + mUSB_STATUS_IN_INT_DISABLE(); + + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f); + + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, pattern); + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, exccause); + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, pc); + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, badvaddr); + + mUSB_EP3_XFER_DONE(); +} + +LOCAL void zfGenWrongEpidEvent(uint32_t epid) +{ + uint32_t pattern = 0x33221299; + + A_PRINTF("Tgt Drv send an event 44332212 to Host Drv\n"); + mUSB_STATUS_IN_INT_DISABLE(); + + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x0f); + + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, pattern); + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, epid); + + mUSB_EP3_XFER_DONE(); +} + +void +AR6002_fatal_exception_handler_patch(CPU_exception_frame_t *exc_frame) +{ + struct register_dump_s dump; + void (*reset_func)(void) = (void*)(RESET_VECTOR_ADDRESS); + uint32_t exc_cause, exc_vaddr; + asm volatile("rsr %0,%1" : "=r" (exc_cause) : "n" (EXCCAUSE)); + asm volatile("rsr %0,%1" : "=r" (exc_vaddr) : "n" (EXCVADDR)); + + dump.exc_frame = *exc_frame; /* structure copy */ + dump.badvaddr = exc_vaddr; + dump.exc_frame.xt_exccause = exc_cause; + dump.pc = exc_frame->xt_pc; + dump.assline = 0; + + zfGenExceptionEvent(dump.exc_frame.xt_exccause, dump.pc, dump.badvaddr); + +#if SYSTEM_MODULE_PRINT + A_PRINTF("\nFatal exception (%d): \tpc=0x%x \n\r\tbadvaddr=0x%x \n\r\tdump area=0x%x\n", + dump.exc_frame.xt_exccause, dump.pc, dump.badvaddr, &dump); + PRINT_FAILURE_STATE(); +#else + A_PUTS("Fatal exception\n\r"); +#endif + A_ASSFAIL(&dump); + +#if defined(_ROM_) + A_WDT_ENABLE(); +#endif + + while(1) ; +} + +void +HTCControlSvcProcessMsg_patch(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, + adf_nbuf_t pBuffers, void *arg) +{ + a_uint8_t *anbdata; + a_uint32_t anblen; + HTC_UNKNOWN_MSG *pMsg; + + /* we assume buffers are aligned such that we can access the message + * parameters directly*/ + adf_nbuf_peek_header(pBuffers, &anbdata, &anblen); + pMsg = (HTC_UNKNOWN_MSG *)anbdata; + + if (pMsg->MessageID == HTC_MSG_SETUP_COMPLETE_ID) { + htc_complete_setup = 1; + } + + HTCControlSvcProcessMsg(EndpointID, hdr_buf, pBuffers, arg); +} + +/* Patch callback for check the endpoint ID is correct or not */ +void +HTCMsgRecvHandler_patch(adf_nbuf_t hdr_buf, adf_nbuf_t buffer, void *context) +{ + int eid; + a_uint8_t *anbdata; + a_uint32_t anblen; + adf_nbuf_t tmp_nbuf; + HTC_FRAME_HDR *pHTCHdr; + + if (hdr_buf == ADF_NBUF_NULL) { + /* HTC hdr is not in the hdr_buf */ + tmp_nbuf = buffer; + } else { + tmp_nbuf = hdr_buf; + } + + adf_nbuf_peek_header(tmp_nbuf, &anbdata, &anblen); + pHTCHdr = (HTC_FRAME_HDR *)anbdata; + + eid = pHTCHdr->EndpointID; + + if ((eid != 0) && (htc_complete_setup == 0)) { + A_PRINTF("\nHTC Hdr EndpointID = %d, anblen = %d\n", pHTCHdr->EndpointID, anblen); + A_PRINTF("HTC Hder : %2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x\n", + *anbdata, *(anbdata+1), *(anbdata+2), *(anbdata+3), + *(anbdata+4), *(anbdata+5), *(anbdata+6), *(anbdata+7), + *(anbdata+8), *(anbdata+9), *(anbdata+10), *(anbdata+11)); + A_PRINTF("init_htc_handle = 0x%8x\n", init_htc_handle); + + if (pHTCHdr->EndpointID == 1) { + A_PRINTF("Return WMI Command buffer\n"); + HTC_ReturnBuffers(init_htc_handle, 1, tmp_nbuf); + } else if ((pHTCHdr->EndpointID == 5) || (pHTCHdr->EndpointID == 6)) { + A_PRINTF("Return Data buffer\n"); + HTC_ReturnBuffers(init_htc_handle, 6, tmp_nbuf); + } else { + } + } else { + if ((pHTCHdr->EndpointID < 0) || (pHTCHdr->EndpointID >= ENDPOINT_MAX)) { + A_PRINTF("HTC Hdr EndpointID = %d, anblen = %d\n", pHTCHdr->EndpointID, anblen); + A_PRINTF("HTC Hder : %2x-%2x-%2x-%2x-%2x-%2x-%2x-%2x\n", + *anbdata, *(anbdata+1), *(anbdata+2), *(anbdata+3), + *(anbdata+4), *(anbdata+5), *(anbdata+6), *(anbdata+7)); + + if (anblen > 64) { + A_PRINTF("EP1-Tx-Data with Wrong Htc Header Endpoint ID, WAR free this buffer\n"); + HTC_ReturnBuffers(init_htc_handle, 6, tmp_nbuf); + A_PRINTF("EP1-Tx-Data > Free this buffer successfully\n"); + } else { + A_PRINTF("EP4-WMI-Cmd with Wrong Htc Header Endpoint ID, WAR free this buffer\n"); + zfGenWrongEpidEvent((a_uint32_t)pHTCHdr->EndpointID); + HTC_ReturnBuffers(init_htc_handle, 1, tmp_nbuf); + A_PRINTF("EP4-WMI-Cmd > Free this buffer successfully\n"); + } + } else + HTCMsgRecvHandler( hdr_buf, buffer, context); + } +} +#endif + +void init_mem() +{ + int i = 0; + uint32_t *temp = (uint32_t *)ALLOCRAM_START; + + /* clear bss segment */ + for(temp = (uint32_t *)&START_BSS; temp < (uint32_t *)&END_BSS; temp++) + *temp = 0; + + /* clear heap segment */ + for(i = 0; i < ((ALLOCRAM_SIZE - 4)/4); i++) + temp[i] = 0; +} + +static void idle_task() +{ + if (loop_low == 0xffffffff) { + loop_low = 0; + loop_high++; + } else { + loop_low++; + } + return; +} + +void wlan_task(void) +{ + loop_low=loop_high=0; + + while(1) { +#if defined(PROJECT_MAGPIE) + if (bJumptoFlash){ + bJumptoFlash = FALSE; + break; + } +#endif + + /* update wdt timer */ + A_WDT_TASK(); + + /* UPDATE cticks - to be moved to idle_tsk, put here will be easier to read */ + A_CLOCK_TICK(); + + HIF_isr_handler(NULL); + +#if MAGPIE_ENABLE_WLAN == 1 + wlan_pci_isr(); +#endif + + A_TASKLET_RUN(); + A_TIMER_RUN(); + + /* Low priority tasks */ + if ((loop_low & 0xf) == 0) { + } + + /* Very low priority tasks */ + if ((loop_low & 0xfff) == 0x7) { + if ((loop_low & 0x1000) == 0) { + A_DBG_TASK(); + } else { + } + } + + idle_task(); + } +} + +#endif /* #if defined(_RAM_) */ diff --git a/target_firmware/magpie_fw_dev/target/init/init.h b/target_firmware/magpie_fw_dev/target/init/init.h new file mode 100644 index 0000000..1900ced --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/init/init.h @@ -0,0 +1,37 @@ +// @TODO: Should define the memory region later~ +#define ALLOCRAM_START ( ((unsigned int)&_fw_image_end) + 4) +#define ALLOCRAM_SIZE ( SYS_RAM_SZIE - ( ALLOCRAM_START - SYS_D_RAM_REGION_0_BASE) - SYS_D_RAM_STACK_SIZE) + +#include "regdump.h" + +#define SBOOT_PATTERN 0x5342 +#define IS_FLASHBOOT() (((DEBUG_SYSTEM_STATE&~(0x0000ffff))>>16==SBOOT_PATTERN)) + +// patch for exception handle +void AR6002_fatal_exception_handler_patch(CPU_exception_frame_t *exc_frame); +void exception_reset(struct register_dump_s *dump); + +void (* _assfail_ori)(struct register_dump_s *); +void HTCMsgRecvHandler_patch(adf_nbuf_t hdr_buf, adf_nbuf_t buffer, void *context); +void HTCControlSvcProcessMsg_patch(HTC_ENDPOINT_ID EndpointID, adf_nbuf_t hdr_buf, + adf_nbuf_t pBuffers, void *arg); + +#if defined(PROJECT_K2) + +#if MOVE_PRINT_TO_RAM +extern int fw_cmnos_printf(const char *fmt, ...); + +extern uint16_t u8UsbConfigValue; +extern uint16_t u8UsbInterfaceValue; +extern uint16_t u8UsbInterfaceAlternateSetting; +#endif + +extern void _fw_usb_fw_task(void); +extern void _fw_usb_reset_fifo(void); + +#endif + + +void fatal_exception_func(); +void init_mem(); +void wlan_task(); diff --git a/target_firmware/magpie_fw_dev/target/init/magpie.c b/target_firmware/magpie_fw_dev/target/init/magpie.c new file mode 100755 index 0000000..4039eae --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/init/magpie.c @@ -0,0 +1,143 @@ +#include "sys_cfg.h" + +#if defined(_RAM_) + +#include "dt_defs.h" +#include "athos_api.h" + +#include "adf_os_mem.h" + +#define MAGPIE 1 + +#if MAGPIE==1 + +void htc_setup_comp(void) +{ +} + +/* target WMI command related globals */ +static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *buffer, int Length); + +static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] = +{ + {dispatch_magpie_sys_cmds, WMI_ECHO_CMDID, 0}, + {dispatch_magpie_sys_cmds, WMI_ACCESS_MEMORY_CMDID, 0} +}; + +static WMI_DECLARE_DISPATCH_TABLE(Magpie_Sys_Commands_Tbl, Magpie_Sys_DispatchEntries); + +htc_handle_t htc_handle; + +extern void HTC_Loopback_Init(htc_handle_t handle); +extern void _wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, + A_UINT16 SeqNo, A_UINT8 *buffer, int Length); + +static void handle_echo_command(void *pContext, A_UINT16 SeqNo, + A_UINT8 *buffer, int Length) +{ + _wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length); +} + +static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *buffer, int Length) +{ + switch(Command) + { + case WMI_ECHO_CMDID: + handle_echo_command(pContext, SeqNo, buffer, Length); + break; + + case WMI_ACCESS_MEMORY_CMDID: + break; + } +} + +void _wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo, + A_UINT8 *buffer, int Length) +{ + adf_nbuf_t netbuf = ADF_NBUF_NULL; + A_UINT8 *pData; + + netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY, sizeof(WMI_CMD_HDR) + Length); + + if (netbuf == ADF_NBUF_NULL) { + adf_os_print("%s: buffer allocation for event_id %x failed!\n", __FUNCTION__, cmd_id); + adf_os_assert(0); + return; + } + + if (Length != 0 && buffer != NULL) { + pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length); + adf_os_mem_copy(pData, buffer, Length); + } + + WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length); +} + + +void Magpie_init(void) +{ + A_PRINTF("[+++Magpie_init]\n\r"); + + A_PRINTF("[+++VBUF_init(%d)]\n\r", MAX_BUF_NUM); + VBUF_init(MAX_BUF_NUM); + + A_PRINTF("[+++VBUF_init(%d)]\n\r", MAX_DESC_NUM); + VDESC_init(MAX_DESC_NUM); + +#if MAGPIE_ENABLE_WLAN == 0 + aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa + hif_handle = HIF_init(0); + +#if ZM_FM_LOOPBACK == 1 + HIF_config_pipe(hif_handle, HIF_USB_PIPE_TX, 5); + HIF_config_pipe(hif_handle, HIF_USB_PIPE_COMMAND, 2); + +#if SYSTEM_MODULE_HP_EP5 + HIF_config_pipe(hif_handle, HIF_USB_PIPE_HP_TX, 3); +#endif +#if SYSTEM_MODULE_HP_EP6 + HIF_config_pipe(hif_handle, HIF_USB_PIPE_MP_TX, 3); +#endif + + A_PRINTF("[+++HIF_init(0)]\n\r"); + + HIF_start(hif_handle); + +#else /* ZM_FM_LOOPBACK == 0 */ + // initialize HTC + htcConf.CreditSize = 320; + htcConf.CreditNumber = 10; +#if 1 + htcConf.ControlDownLinkPipeID = HIF_USB_PIPE_INTERRUPT; // Target -> Host + htcConf.ControlUpLinkPipeID = HIF_USB_PIPE_COMMAND; // Host -> Target +#else + htcConf.ControlDownLinkPipeID = HIF_USB_PIPE_RX; + htcConf.ControlUpLinkPipeID = HIF_USB_PIPE_TX; +#endif + htcConf.HIFHandle = hif_handle; + htcConf.OSHandle = 0; // not used + htcConf.PoolHandle = pool_handle; + + htc_handle = HTC_init(htc_setup_comp, &htcConf); + // Initialize HTC services + HTC_Loopback_Init(htc_handle); + + adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG)); + wmiConfig.HtcHandle = htc_handle; + wmiConfig.PoolHandle = pool_handle; + wmiConfig.MaxCmdReplyEvts = 1; + wmiConfig.MaxEventEvts = 1; + + wmi_handle = WMI_Init(&wmiConfig); + Magpie_Sys_Commands_Tbl.pContext = wmi_handle; + WMI_RegisterDispatchTable(Magpie_Sys_Commands_Tbl.pContext, &Magpie_Sys_Commands_Tbl); + +#endif/* ZM_FM_LOOPBACK == 0 */ +#endif /* MAGPIE_ENABLE_WLAN */ +} + +#endif /* #if MAGPIE==1 */ + +#endif /* #if defined(_RAM_) */ diff --git a/target_firmware/magpie_fw_dev/target/rompatch/HIF_usb_patch.c b/target_firmware/magpie_fw_dev/target/rompatch/HIF_usb_patch.c new file mode 100755 index 0000000..d3a59f9 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/rompatch/HIF_usb_patch.c @@ -0,0 +1,70 @@ +#include "sys_cfg.h" +#include "dt_defs.h" +#include "reg_defs.h" + +#include +#include +#include +#include +#include +#include + +#include "hif_usb.h" + +/* + * -- support more than 64 bytes command on ep4 -- + */ +int _HIFusb_get_max_msg_len_patch(hif_handle_t handle, int pipe) +{ + switch(pipe) { + case HIF_USB_PIPE_INTERRUPT: + case HIF_USB_PIPE_COMMAND: + return 512; + + default: + return 1600; + } +} + +/* + * -- move the usb_task to here -- + */ +void _HIFusb_isr_handler_patch(hif_handle_t h) +{ + A_USB_FW_TASK(); + + _HIFusb_isr_handler(); +} + + +/* + * -- reset usb dma -- + * + * - make sure DMA_START bit0 is zero + * - update DMA_START bit4 to 1 + * - update DESC_START_ADDR + * - update DMA_START bit 0 + */ +void _HIFusb_start_patch(hif_handle_t handle) +{ + MAGPIE_REG_USB_TX0_DMA_START = 0x0; + MAGPIE_REG_USB_RX0_DMA_START = 0x0; + MAGPIE_REG_USB_RX1_DMA_START = 0x0; + MAGPIE_REG_USB_RX2_DMA_START = 0x0; + + while( 1 ) + { + if(!MAGPIE_REG_USB_TX0_DMA_START && + !MAGPIE_REG_USB_RX0_DMA_START && + !MAGPIE_REG_USB_RX1_DMA_START && + !MAGPIE_REG_USB_RX2_DMA_START ) + { + MAGPIE_REG_USB_TX0_DMA_START = MAGPIE_REG_USB_TX0_DMA_START|BIT4; + MAGPIE_REG_USB_RX0_DMA_START = MAGPIE_REG_USB_RX0_DMA_START|BIT4; + MAGPIE_REG_USB_RX1_DMA_START = MAGPIE_REG_USB_RX1_DMA_START|BIT4; + MAGPIE_REG_USB_RX2_DMA_START = MAGPIE_REG_USB_RX2_DMA_START|BIT4; + break; + } + } + _HIFusb_start(); +} diff --git a/target_firmware/magpie_fw_dev/target/rompatch/cmnos_clock_patch.c b/target_firmware/magpie_fw_dev/target/rompatch/cmnos_clock_patch.c new file mode 100755 index 0000000..4ecb9dc --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/rompatch/cmnos_clock_patch.c @@ -0,0 +1,55 @@ +#include "athos_api.h" +#include "sys_cfg.h" + +a_uint32_t ref_clk = 0; +extern a_uint32_t cticks; + +// clock change +// +void cmnos_clock_init_patch(a_uint32_t refclk) +{ + ref_clk = refclk; +} + +// retrieve current clock setting +a_uint32_t cmnos_refclk_speed_get_patch(void) +{ + return ref_clk; +} + + +// software emulate delay function +void cmnos_delay_us_patch(int us) +{ + a_uint32_t start_time = NOW(); + unsigned int num_ticks = us*ref_clk; // system_freq == number of ticks per 1us + + while ( (NOW() - start_time) < num_ticks) { + /* busy spin */ + ; + } +} + + +// software emulate microsecond ticks +void cmnos_tick_patch(void) +{ + static a_uint32_t last_tick = 0; + a_uint32_t current_tick = NOW(); + a_uint32_t delta_tick; + + delta_tick = (A_UINT32 ) (current_tick - last_tick)/(ref_clk<<10); + + if( delta_tick > 0 ) + last_tick = current_tick; + + cticks += delta_tick; +} + +// get current sysmem up time in milliseconds based +a_uint32_t cmnos_milliseconds_patch(void) +{ + cmnos_tick_patch(); + + return (cticks); +} diff --git a/target_firmware/magpie_fw_dev/target/rompatch/usb_api_patch.c b/target_firmware/magpie_fw_dev/target/rompatch/usb_api_patch.c new file mode 100755 index 0000000..c0747e4 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/rompatch/usb_api_patch.c @@ -0,0 +1,844 @@ +#include "usb_defs.h" +#include "usb_type.h" +#include "usb_pre.h" +#include "usb_extr.h" +#include "usb_std.h" +#include "reg_defs.h" +#include "athos_api.h" +#include "usbfifo_api.h" + +#include "sys_cfg.h" + +#define measure_time 0 +#define measure_time_pll 10000000 + +typedef void (* USBFIFO_recv_command)(VBUF *cmd); + +extern Action eUsbCxFinishAction; +extern CommandType eUsbCxCommand; +extern BOOLEAN UsbChirpFinish; +extern USB_FIFO_CONFIG usbFifoConf; +extern uint16_t *pu8DescriptorEX; +extern uint16_t u16TxRxCounter; + +USBFIFO_recv_command m_origUsbfifoRecvCmd = NULL; + +void zfTurnOffPower_patch(void); + +static void _fw_reset_dma_fifo(); +static void _fw_restore_dma_fifo(); +static void _fw_power_on(); +static void _fw_power_off(); + +BOOLEAN bEepromExist = TRUE; +BOOLEAN bJumptoFlash = FALSE; + +void _fw_usbfifo_recv_command(VBUF *buf) +{ + A_UINT8 *cmd_data; + A_UINT32 tmp; + + cmd_data = (A_UINT8 *)(buf->desc_list->buf_addr + buf->desc_list->data_offset); + tmp = *((A_UINT32 *)cmd_data); + if ( tmp == 0xFFFFFFFF ) { + // reset usb/wlan dma + _fw_reset_dma_fifo(); + + // restore gpio setting and usb/wlan dma state + _fw_restore_dma_fifo(); + + // set clock to bypass mode - 40Mhz from XTAL + HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); + + A_DELAY_USECS(100); // wait for stable + + HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16)); + + A_DELAY_USECS(100); // wait for stable + A_UART_HWINIT((40*1000*1000), 19200); + + A_CLOCK_INIT(40); + + if (!bEepromExist) { //jump to flash boot (eeprom data in flash) + bJumptoFlash = TRUE; + A_PRINTF("Jump to Flash BOOT\n"); + app_start(); + }else{ + A_PRINTF("receive the suspend command...\n"); + // reboot..... + A_USB_JUMP_BOOT(); + } + + } else { + m_origUsbfifoRecvCmd(buf); + } +} + +void _fw_usbfifo_init(USB_FIFO_CONFIG *pConfig) +{ + m_origUsbfifoRecvCmd = pConfig->recv_command; + + usbFifoConf.get_command_buf = pConfig->get_command_buf; + usbFifoConf.recv_command = _fw_usbfifo_recv_command; + usbFifoConf.get_event_buf = pConfig->get_event_buf; + usbFifoConf.send_event_done = pConfig->send_event_done; +} + +/* + * -- support more than 64 bytes command on ep4 -- + */ +void vUsb_Reg_Out_patch(void) +{ + uint16_t usbfifolen; + uint16_t ii; + uint32_t ep4_data; + static volatile uint32_t *regaddr; + static uint16_t cmdLen; + static VBUF *buf; + BOOLEAN cmd_is_last = FALSE; + static BOOLEAN cmd_is_new = TRUE; + + // get the size of this transcation + usbfifolen = USB_BYTE_REG_READ(ZM_EP4_BYTE_COUNT_LOW_OFFSET); + + // check is command is new + if( cmd_is_new ){ + + buf = usbFifoConf.get_command_buf(); + cmdLen = 0; + + if( !buf ) + goto ERR; + + // copy free, assignment buffer of the address + regaddr = (uint32_t *)buf->desc_list->buf_addr; + + cmd_is_new = FALSE; + } + + // just in case, suppose should not happen + if( !buf ) + goto ERR; + + // if size is smaller, this is the last command! + // zero-length supposed should be set through 0x27/bit7->0x19/bit4, not here + if( usbfifolen<64 ) { + cmd_is_last = TRUE; + } + + // accumulate the size + cmdLen += usbfifolen; + + // round it to alignment + if(usbfifolen % 4) + usbfifolen = (usbfifolen >> 2) + 1; + else + usbfifolen = usbfifolen >> 2; + + // retrieve the data from fifo + for(ii = 0; ii < usbfifolen; ii++) + { + ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out + *regaddr = ep4_data; + regaddr++; + } + + // if this is the last command, callback to HTC + if ( cmd_is_last ) + { + buf->desc_list->next_desc = NULL; + buf->desc_list->data_offset = 0; + buf->desc_list->data_size = cmdLen; + buf->desc_list->control = 0; + buf->next_buf = NULL; + buf->buf_length = cmdLen; + + usbFifoConf.recv_command(buf); + + cmd_is_new = TRUE; + } + + goto DONE; +ERR: + // we might get no command buffer here? + // but if we return here, the ep4 fifo will be lock out, + // so that we still read them out but just drop it ? + for(ii = 0; ii < usbfifolen; ii++) + { + ep4_data = USB_WORD_REG_READ(ZM_EP4_DATA_OFFSET); // read fifo data out + } + +DONE: + //mUSB_STATUS_IN_INT_ENABLE(); + ; +} + + +/* + * -- usb1.1 ep6 fix -- + */ +extern uint16_t u8UsbConfigValue; +extern uint16_t u8UsbInterfaceValue; +extern uint16_t u8UsbInterfaceAlternateSetting; +extern SetupPacket ControlCmd; +extern void vUsbClrEPx(void); + +#undef FS_C1_I0_A0_EP_NUMBER +#define FS_C1_I0_A0_EP_NUMBER 6 + +#define FS_C1_I0_A0_EP6_BLKSIZE BLK512BYTE +#define FS_C1_I0_A0_EP6_BLKNO DOUBLE_BLK +#define FS_C1_I0_A0_EP6_DIRECTION DIRECTION_OUT +#define FS_C1_I0_A0_EP6_TYPE TF_TYPE_BULK +#define FS_C1_I0_A0_EP6_MAX_PACKET 0x0040 +#define FS_C1_I0_A0_EP6_bInterval 00 + +// EP6 +#define FS_C1_I0_A0_EP6_FIFO_START (FS_C1_I0_A0_EP5_FIFO_START + FS_C1_I0_A0_EP5_FIFO_NO) +#define FS_C1_I0_A0_EP6_FIFO_NO (FS_C1_I0_A0_EP6_BLKNO * FS_C1_I0_A0_EP6_BLKSIZE) +#define FS_C1_I0_A0_EP6_FIFO_CONFIG (0x80 | ((FS_C1_I0_A0_EP6_BLKSIZE - 1) << 4) | ((FS_C1_I0_A0_EP6_BLKNO - 1) << 2) | FS_C1_I0_A0_EP6_TYPE) +#define FS_C1_I0_A0_EP6_FIFO_MAP (((1 - FS_C1_I0_A0_EP6_DIRECTION) << 4) | EP6) +#define FS_C1_I0_A0_EP6_MAP (FS_C1_I0_A0_EP6_FIFO_START | (FS_C1_I0_A0_EP6_FIFO_START << 4) | (MASK_F0 >> (4*FS_C1_I0_A0_EP6_DIRECTION))) + + +#define CMD_PCI_RC_RESET_ON() HAL_WORD_REG_WRITE(MAGPIE_REG_RST_RESET_ADDR, \ + (HAL_WORD_REG_READ(MAGPIE_REG_RST_RESET_ADDR)| \ + (PCI_RC_PHY_SHIFT_RESET_BIT|PCI_RC_PLL_RESET_BIT|PCI_RC_PHY_RESET_BIT|PCI_RC_RESET_BIT))) + +void vUSBFIFO_EP6Cfg_FS_patch(void) +{ +#if (FS_C1_I0_A0_EP_NUMBER >= 6) + int i; + + //EP0X06 + mUsbEPMap(EP6, FS_C1_I0_A0_EP6_MAP); + mUsbFIFOMap(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_MAP); + mUsbFIFOConfig(FS_C1_I0_A0_EP6_FIFO_START, FS_C1_I0_A0_EP6_FIFO_CONFIG); + + for(i = FS_C1_I0_A0_EP6_FIFO_START + 1 ; + i < FS_C1_I0_A0_EP6_FIFO_START + FS_C1_I0_A0_EP6_FIFO_NO ; i ++) + { + mUsbFIFOConfig(i, (FS_C1_I0_A0_EP6_FIFO_CONFIG & (~BIT7)) ); + } + + mUsbEPMxPtSzHigh(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff)); + mUsbEPMxPtSzLow(EP6, FS_C1_I0_A0_EP6_DIRECTION, (FS_C1_I0_A0_EP6_MAX_PACKET & 0x7ff)); + mUsbEPinHighBandSet(EP6 , FS_C1_I0_A0_EP6_DIRECTION, FS_C1_I0_A0_EP6_MAX_PACKET); +#endif +} + +void vUsbFIFO_EPxCfg_FS_patch(void) +{ + switch (u8UsbConfigValue) + { +#if (FS_CONFIGURATION_NUMBER >= 1) + // Configuration 0X01 + case 0X01: + switch (u8UsbInterfaceValue) + { +#if (FS_C1_INTERFACE_NUMBER >= 1) + // Interface 0 + case 0: + switch (u8UsbInterfaceAlternateSetting) + { + +#if (FS_C1_I0_ALT_NUMBER >= 1) + // AlternateSetting 0 + case 0: + + // snapped.... + + // patch up this ep6_fs config + vUSBFIFO_EP6Cfg_FS_patch(); + + break; + +#endif + default: + break; + } + break; +#endif + default: + break; + } + break; +#endif + default: + break; + } + //mCHECK_STACK(); +} + + +BOOLEAN bSet_configuration_patch(void) +{ + bSet_configuration(); + + if (mLOW_BYTE(mDEV_REQ_VALUE()) == 0) + { + // snapped.... + ; + } + else + { + if (mUsbHighSpeedST()) // First judge HS or FS?? + { + // snapped.... + ; + } + else + { + // snapped.... + vUsbFIFO_EPxCfg_FS_patch(); + } + + // snapped.... + } + + eUsbCxFinishAction = ACT_DONE; + return TRUE; +} + + +/* + * -- support more than 64 bytes command on ep3 -- + */ +void vUsb_Status_In_patch(void) +{ + uint16_t count; + uint16_t remainder; + u16_t RegBufLen; + BOOLEAN cmdEnd = FALSE; + + static u16_t mBufLen; + static VBUF *evntbuf = NULL; + static volatile u32_t *regaddr; + static BOOLEAN cmd_is_new = TRUE; + + if( cmd_is_new ) + { + evntbuf = usbFifoConf.get_event_buf(); + if ( evntbuf != NULL ) + { + regaddr = (u32_t *)VBUF_GET_DATA_ADDR(evntbuf); + mBufLen = evntbuf->buf_length; + } + else + { + mUSB_STATUS_IN_INT_DISABLE(); + goto ERR_DONE; + } + + cmd_is_new = FALSE; + } + + if( mBufLen > bUSB_EP_MAX_PKT_SIZE_64 ) { + RegBufLen = bUSB_EP_MAX_PKT_SIZE_64; + mBufLen -= bUSB_EP_MAX_PKT_SIZE_64; + } + // TODO: 64 byes... controller supposed will take care of zero-length? + else { + RegBufLen = mBufLen; + cmdEnd = TRUE; + } + + /* INT use EP3 */ + for(count = 0; count < (RegBufLen / 4); count++) + { + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr); + regaddr++; + } + + remainder = RegBufLen % 4; + + if (remainder) + { + switch(remainder) + { + case 3: + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x7); + break; + case 2: + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x3); + break; + case 1: + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0x1); + break; + } + + USB_WORD_REG_WRITE(ZM_EP3_DATA_OFFSET, *regaddr); + + // Restore CBus FIFO size to word size + USB_WORD_REG_WRITE(ZM_CBUS_FIFO_SIZE_OFFSET, 0xF); + } + + mUSB_EP3_XFER_DONE(); + + if ( evntbuf != NULL && cmdEnd ) + { + usbFifoConf.send_event_done(evntbuf); + cmd_is_new = TRUE; + } + +ERR_DONE: + ; +} + + +#define PCI_RC_RESET_BIT BIT6 +#define PCI_RC_PHY_RESET_BIT BIT7 +#define PCI_RC_PLL_RESET_BIT BIT8 +#define PCI_RC_PHY_SHIFT_RESET_BIT BIT10 + + +/* + * -- urn_off_merlin -- + * . values suggested from Lalit + * + */ +static void turn_off_merlin() +{ + volatile uint32_t default_data[9]; + volatile uint32_t read_data = 0; + uint32_t i=0; + + if(1) + { + A_PRINTF("turn_off_merlin_ep_start ......\n"); + A_DELAY_USECS(measure_time); + default_data[0] = 0x9248fd00; + default_data[1] = 0x24924924; + default_data[2] = 0xa8000019; + default_data[3] = 0x17160820; + default_data[4] = 0x25980560; + default_data[5] = 0xc1c00000; + default_data[6] = 0x1aaabe40; + default_data[7] = 0xbe105554; + default_data[8] = 0x00043007; + + for(i=0; i<9; i++) + { + A_DELAY_USECS(10); + + HAL_WORD_REG_WRITE( 0x10ff4040, default_data[i]); + } + A_DELAY_USECS(10); + HAL_WORD_REG_WRITE(0x10ff4044, BIT0); + A_PRINTF("turn_off_merlin_ep_end ......\n"); + } +} + +/* + * -- turn_off_phy -- + * + * . write shift register to both pcie ep and rc + * . + */ + +static void turn_off_phy() +{ + + volatile uint32_t default_data[9]; + volatile uint32_t read_data = 0; + uint32_t i=0; + + default_data[0] = 0x9248fd00; + default_data[1] = 0x24924924; + default_data[2] = 0xa8000019; + default_data[3] = 0x17160820; + default_data[4] = 0x25980560; + default_data[5] = 0xc1c00000; + default_data[6] = 0x1aaabe40; + default_data[7] = 0xbe105554; + default_data[8] = 0x00043007; + + for(i=0; i<9; i++) + { + // check for the done bit to be set + + while (1) + { + read_data=HAL_WORD_REG_READ(0x40028); + if( read_data & BIT31 ) + break; + } + + A_DELAY_USECS(1); + + HAL_WORD_REG_WRITE( 0x40024, default_data[i]); + } + HAL_WORD_REG_WRITE(0x40028, BIT0); +} + +static void turn_off_phy_rc() +{ + + volatile uint32_t default_data[9]; + volatile uint32_t read_data = 0; + uint32_t i=0; + + A_PRINTF("turn_off_phy_rc\n"); + + default_data[0] = 0x9248fd00; + default_data[1] = 0x24924924; + default_data[2] = 0xa8000019; + default_data[3] = 0x13160820;//PwdClk1MHz=0 + default_data[4] = 0x25980560; + default_data[5] = 0xc1c00000; + default_data[6] = 0x1aaabe40; + default_data[7] = 0xbe105554; + default_data[8] = 0x00043007; + + for(i=0; i<9; i++) + { + // check for the done bit to be set + + while (1) + { + read_data=HAL_WORD_REG_READ(0x40028); + if( read_data & BIT31 ) + break; + } + + A_DELAY_USECS(1); + + HAL_WORD_REG_WRITE( 0x40024, default_data[i]); + } + HAL_WORD_REG_WRITE(0x40028, BIT0); +} + +volatile uint32_t gpio_func = 0x0; +volatile uint32_t gpio = 0x0; + +/* + * -- patch zfTurnOffPower -- + * + * . set suspend counter to non-zero value + * . + */ +void zfTurnOffPower_patch(void) +{ + uint32_t i=0; + A_PRINTF("+++ goto suspend ......\n"); + + // setting the go suspend here, power down right away... + HAL_WORD_REG_WRITE(0x10000, HAL_WORD_REG_READ(0x10000)|(0x8)); + + A_DELAY_USECS(100); + + // TURN OFF ETH PLL + _fw_power_off(); + + //32clk wait for External ETH PLL stable + A_DELAY_USECS(100); + + HAL_WORD_REG_WRITE(0x52000, 0x70303);//read back 0x703f7 + HAL_WORD_REG_WRITE(0x52008, 0x0e91c);//read back 0x1e948 + + HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(BIT0))); //0x56030 + // wake up, and turn on cpu, eth, pcie and usb pll + _fw_power_on(); + // restore gpio and other settings + _fw_restore_dma_fifo(); + + // clear suspend.................. + HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)&(~BIT0))); + HAL_WORD_REG_WRITE(0x52028, HAL_WORD_REG_READ(0x52028)&(~(BIT8|BIT12|BIT16))); +} + +/* + * -- patch zfResetUSBFIFO_patch -- + * + * . clear ep3/ep4 fifo + * . set suspend magic pattern + * . reset pcie ep phy + * . reset pcie rc phy + * . turn off pcie pll + * . reset all pcie/gmac related registers + * . reset usb dma + */ +void zfResetUSBFIFO_patch(void) +{ + A_PRINTF("0x9808 0x%x ......\n", HAL_WORD_REG_READ(0x10ff9808)); + A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890)); + A_PRINTF("0x7890 0x%x ......\n", HAL_WORD_REG_READ(0x10ff7890)); + A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088)); + _fw_reset_dma_fifo(); +} + +static void _fw_reset_dma_fifo() +{ + int i; + + HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100ae)|0x10)); + HAL_BYTE_REG_WRITE(0x100ae, (HAL_BYTE_REG_READ(0x100af)|0x10)); + A_PRINTF("_fw_reset_dma_fifo\n"); + + // disable ep3 int enable, so that resume back won't send wdt magic pattern out!!! + mUSB_STATUS_IN_INT_DISABLE(); + + // update magic pattern to indicate this is a suspend + HAL_WORD_REG_WRITE(WATCH_DOG_MAGIC_PATTERN_ADDR, SUS_MAGIC_PATTERN); + + A_PRINTF("org 0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048)); + A_PRINTF("org 0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C)); + A_PRINTF("org 0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088)); + + HAL_WORD_REG_WRITE(0x10ff4088,0xaaa6a);//1010.1010.1010.0110.1010 for UB94 + HAL_WORD_REG_WRITE(0x10ff404C,0x0); + + A_DELAY_USECS(1000); + A_PRINTF("0x4048 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4048)); + A_PRINTF("0x404C 0x%x ......\n", HAL_WORD_REG_READ(0x10ff404C)); + A_PRINTF("0x4088 0x%x ......\n", HAL_WORD_REG_READ(0x10ff4088)); + + // turn off merlin + turn_off_merlin(); + // pcie ep + A_PRINTF("turn_off_magpie_ep_start ......\n"); + A_DELAY_USECS(measure_time); + HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)|BIT0|(1<<1))); + turn_off_phy(); + HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&~(BIT0|(1<<1)))); + A_PRINTF("turn_off_magpie_ep_end ......\n"); + + // pcie rc + A_PRINTF("turn_off_magpie_rc_start ......\n"); + A_DELAY_USECS(measure_time); + HAL_WORD_REG_WRITE( 0x40040, (HAL_WORD_REG_READ(0x40040)&(~BIT0))); + turn_off_phy_rc(); + A_PRINTF("turn_off_magpie_rc_end ......down\n"); + A_DELAY_USECS(measure_time); + + A_PRINTF("0x4001C %p ......\n", HAL_WORD_REG_READ(0x4001c)); + A_PRINTF("0x40040 %p ......\n", HAL_WORD_REG_READ(0x40040)); + + // turn off pcie_pll - power down (bit16) + A_PRINTF(" before pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C)); + HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)|(BIT18))); + A_PRINTF(" after pwd PCIE PLL CFG:0x5601C %p ......\n", HAL_WORD_REG_READ(0x5601C)); + + /* set everything to reset state?, requested by Oligo */ + HAL_WORD_REG_WRITE(0x50010, HAL_WORD_REG_READ(0x50010)|(BIT13|BIT12|BIT11|BIT9|BIT7|BIT6)); + + HAL_WORD_REG_WRITE(0x5C000, 0); + + A_DELAY_USECS(10); + + // reset usb DMA controller + HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x0); + + HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT4))); + A_DELAY_USECS(5); + HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~BIT4))); + + + HAL_WORD_REG_WRITE((USB_CTRL_BASE_ADDRESS+0x118), 0x1); +} + +static void _fw_power_off() +{ + /* + * 1. set CPU bypass + * 2. turn off CPU PLL + * 3. turn off ETH PLL + * 4. disable ETH PLL bypass and update + * 4.1 set suspend timeout + * 5. set SUSPEND_ENABLE + */ + + HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_BYPASS_ADDR, (BIT0|BIT4)); //0x56004 + + A_DELAY_USECS(100); // wait for stable + + HAL_WORD_REG_WRITE(MAGPIE_REG_CPU_PLL_ADDR, (BIT16));//0x56000 + + A_DELAY_USECS(100); // wait for stable + + A_UART_HWINIT((40*1000*1000), 19200); + A_CLOCK_INIT(40); + + HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)|(BIT16))); //0x5600c + + HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)|(BIT4|BIT0))); //0x56010 + + HAL_WORD_REG_WRITE(MAGPIE_REG_SUSPEND_ENABLE_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_SUSPEND_ENABLE_ADDR)|(0x10<<8))); //0x56030 +} + +static void _fw_power_on() +{ + /* + * 1. turn on CPU PLL + * 2. disable CPU bypass + * 3. turn on ETH PLL + * 4. disable ETH PLL bypass and update + * 5. turn on pcie pll + */ + + HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_ADDR)&(~BIT16))); + + // deassert eth_pll bypass mode and trigger update bit + HAL_WORD_REG_WRITE(MAGPIE_REG_ETH_PLL_BYPASS_ADDR, + (HAL_WORD_REG_READ(MAGPIE_REG_ETH_PLL_BYPASS_ADDR)&(~(BIT4|BIT0)))); +} + +static void _fw_restore_dma_fifo(void) +{ + HAL_WORD_REG_WRITE(0x5601C, (HAL_WORD_REG_READ(0x5601C)&(~(BIT18)))); + + // reset pcie_rc shift + HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)&(~(BIT10|BIT8|BIT7)))); + A_DELAY_USECS(1); + HAL_WORD_REG_WRITE(0x50010, (HAL_WORD_REG_READ(0x50010)|(BIT10|BIT8|BIT7))); + + // reset pci_rc phy + CMD_PCI_RC_RESET_ON(); + A_DELAY_USECS(20); + + // enable dma swap function + MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; + MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; +} + +extern uint16_t *u8ConfigDescriptorEX; +extern uint16_t *pu8DescriptorEX; +extern uint16_t u16TxRxCounter; + +extern uint16_t *u8UsbDeviceDescriptor; + +extern BOOLEAN bGet_descriptor(void); + +uint16_t ConfigDescriptorPatch[30]; + + uint16_t UsbDeviceDescriptorPatch[18]; + #define VENDOR_ID_OFFSET 8 + #define PRODUCT_ID_OFFSET 10 + +#define EP3_TRANSFER_TYPE_OFFSET 17 +#define EP3_INT_INTERVAL 19 +#define EP4_TRANSFER_TYPE_OFFSET 21 +#define EP4_INT_INTERVAL 22 + + + + #define A_SFLASH_READ_4B(u32Data, start_addr) u32Data = *(uint32_t *)(0xf000000+start_addr); + #define FLASH_SIZE 0x800000 //8M + #define FLASH_USB_VENDOR_ID_OFFSET 0x86 + #define FLASH_USB_PRODUCT_ID_OFFSET 0x87 + + // flash reserved size for saving eeprom data is 4K. + #define EE_DATA_RESERVED_LEN 0x1000 //4K + +#define mLOW_MASK(u16) ((uint8_t) ((u16) & mMASK(8))) +#define mHIGH_MASK(u16) ((uint8_t) ((u16) & ~mMASK(8))) + +/* (1234) -> 0034 */ +//#define mLOW_BYTE(u16) ((U_8)(u16)) +#define mLOW_BYTE(u16) mLOW_MASK(u16) +/* (1234) -> 0012 */ +#define mHIGH_BYTE(u16) ((uint8_t) (((uint16_t) (u16)) >> 8)) + +#define mLOW_WORD0(u32) ((uint16_t) ((u32) & 0xFFFF)) +#define mHIGH_WORD0(u32) ((uint16_t) ((u32) >> 16)) + +/* (1234) -> 3412 */ +#define mSWAP_BYTE(u16) ((mLOW_MASK(u16) << 8) | mHIGH_BYTE(u16)) + +BOOLEAN bGet_descriptor_patch(void) +{ + /* Patch for custom id from flash */ + if (bEepromExist == FALSE && mDEV_REQ_VALUE_HIGH() == 1) + { + uint8_t *p = (uint8_t *)u8UsbDeviceDescriptor; + uint32_t u32Tmp=0; + /* Copy Usb Device Descriptor */ + memcpy(UsbDeviceDescriptorPatch, p, sizeof(UsbDeviceDescriptorPatch)); + + A_SFLASH_READ_4B(u32Tmp, FLASH_SIZE - EE_DATA_RESERVED_LEN + FLASH_USB_VENDOR_ID_OFFSET*2); + UsbDeviceDescriptorPatch[VENDOR_ID_OFFSET] = mSWAP_BYTE(mLOW_WORD0(u32Tmp)); + UsbDeviceDescriptorPatch[PRODUCT_ID_OFFSET] = mSWAP_BYTE(mHIGH_WORD0(u32Tmp)); + + pu8DescriptorEX = UsbDeviceDescriptorPatch; + u16TxRxCounter = mTABLE_LEN(u8UsbDeviceDescriptor[0]); + + if (u16TxRxCounter > mDEV_REQ_LENGTH()) + u16TxRxCounter = mDEV_REQ_LENGTH(); + + A_USB_EP0_TX_DATA(); + + //u16TxRxCounter = 18; + return TRUE; + } + if (mDEV_REQ_VALUE_HIGH() == 2) { + uint8_t *p = (uint8_t *)u8ConfigDescriptorEX; + + /* Copy ConfigDescriptor */ + memcpy(ConfigDescriptorPatch, p, sizeof(ConfigDescriptorPatch)); + + p = (uint8_t *)ConfigDescriptorPatch; + + /* Patch the transfer type of EP3 and EP4 */ + ConfigDescriptorPatch[EP3_TRANSFER_TYPE_OFFSET] = 0x0283; + ConfigDescriptorPatch[EP3_INT_INTERVAL] = 0x0700; + ConfigDescriptorPatch[EP4_TRANSFER_TYPE_OFFSET] = 0x4002; + ConfigDescriptorPatch[EP4_INT_INTERVAL] = 0x00; + + switch (mDEV_REQ_VALUE_LOW()) + { + case 0x00: // configuration no: 0 + pu8DescriptorEX = ConfigDescriptorPatch; + u16TxRxCounter = ConfigDescriptorPatch[1]; + //u16TxRxCounter = 46; + break; + default: + return FALSE; + } + + if (u16TxRxCounter > mDEV_REQ_LENGTH()) + u16TxRxCounter = mDEV_REQ_LENGTH(); + + A_USB_EP0_TX_DATA(); + return TRUE; + } + else { + return bGet_descriptor(); + } +} + +extern BOOLEAN bStandardCommand(void); + +BOOLEAN bStandardCommand_patch(void) +{ + if (mDEV_REQ_REQ() == USB_SET_CONFIGURATION) { + A_USB_SET_CONFIG(); + +#if ENABLE_SWAP_DATA_MODE + // SWAP FUNCTION should be enabled while DMA engine is not working, + // the best place to enable it is before we trigger the DMA + MAGPIE_REG_USB_RX0_SWAP_DATA = 0x1; + MAGPIE_REG_USB_TX0_SWAP_DATA = 0x1; + +#if SYSTEM_MODULE_HP_EP5 + MAGPIE_REG_USB_RX1_SWAP_DATA = 0x1; +#endif + +#if SYSTEM_MODULE_HP_EP6 + MAGPIE_REG_USB_RX2_SWAP_DATA = 0x1; +#endif + +#endif //ENABLE_SWAP_DATA_MODE + return TRUE; + } + else { + return bStandardCommand(); + } +} diff --git a/target_firmware/magpie_fw_dev/target/wlan/wlan_pci.c b/target_firmware/magpie_fw_dev/target/wlan/wlan_pci.c new file mode 100755 index 0000000..a44b5c4 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/wlan/wlan_pci.c @@ -0,0 +1,131 @@ +#include +#include +#include +#include +#include +#include + +#if MAGPIE_ENABLE_WLAN == 0 +A_PCI_INIT_FUNC g_pci_init_func; +#endif + +#if MAGPIE_ENABLE_PCIE == 0 +#define EMULATE_PCI_CONFIG +#endif + +#define PCI_CONFIG_BASE_ADDR 0x14000000 + +extern A_PCI_INIT_FUNC g_pci_init_func; +adf_drv_info_t* g_wlan_drv = NULL; +adf_drv_handle_t g_wlan_drv_handle = NULL; +adf_os_drv_intr g_wlan_intr = NULL; + +void wlan_pci_module_init(void) +{ + if (g_pci_init_func != NULL) { + g_pci_init_func(); + } +} + +void wlan_pci_register_drv(adf_drv_info_t *drv) +{ + g_wlan_drv = drv; +} + +#define ATHEROS_VENDOR_ID 0x168c +#define AR5416_DEVID_PCIE 0x24 + +void wlan_pci_probe(void) +{ + __adf_softc_t *sc; + adf_os_resource_t drv_res = {0}; + adf_os_attach_data_t drv_data = {{0}}; + int vendor_id; + int device_id; + + A_PRINTF(": Attaching the driver\n"); + +#if MAGPIE_ENABLE_PCIE == 0 + vendor_id = ATHEROS_VENDOR_ID; + device_id = AR5416_DEVID_PCIE; +#else + vendor_id = wlan_pci_config_read(0, 2); + device_id = wlan_pci_config_read(2, 2); +#endif + A_PRINTF(": Vendor id 0x%x Dev id 0x%x\n", vendor_id, device_id); + + if (vendor_id != ATHEROS_VENDOR_ID) { + A_PRINTF(": Atheros card not found\n"); + return; + } + + /** + * Allocate the sc & zero down + */ + sc = A_ALLOCRAM(sizeof(__adf_softc_t)); + if (!sc) { + A_PRINTF("Cannot malloc softc\n"); + goto mem_fail; + } + +#define AR5416_DEVID_PCIE 0x24 + + drv_data.pci.device = AR5416_DEVID_PCIE; + drv_data.pci.vendor = 0x168c; + drv_data.pci.subvendor = 0; + drv_data.pci.subdevice = 0; + + drv_res.start = (a_uint32_t) 0; + drv_res.end = 0; + drv_res.type = ADF_OS_RESOURCE_TYPE_MEM; + + g_wlan_drv_handle = g_wlan_drv->drv_attach(&drv_res, 1, &drv_data, NULL); + + return; +mem_fail: + return; +} + +int wlan_pci_config_write(int offset, a_uint32_t val, int width) +{ +#if MAGPIE_ENABLE_PCIE == 1 + unsigned long addr = ( PCI_CONFIG_BASE_ADDR + offset ) & 0xfffffffc; + A_UINT8 *ptr = (A_UINT8 *)addr; + A_UINT8 *valptr = (A_UINT8 *)&val; + int idx = offset & 0x3; + int i; + + for (i = 0; i < width; i++) { + ptr[idx + i] = valptr[3-i]; + } +#endif + + return 0; +} + +int wlan_pci_config_read(int offset, int width) +{ +#if MAGPIE_ENABLE_PCIE == 0 + return 0; +#else + unsigned long addr = ( PCI_CONFIG_BASE_ADDR + offset ) & 0xfffffffc; + unsigned long value = *((unsigned long *)addr); + A_UINT8 *ptr = (A_UINT8 *)&value; + int idx = offset & 0x3; + int result = 0; + int i; + + for (i = 0; i < width; i++) { + result |= (ptr[ 3 - (idx + i)] << (8*i)); + } + + return result; +#endif +} + +void wlan_pci_isr() +{ + if (g_wlan_intr != NULL && g_wlan_drv_handle != NULL) { + g_wlan_intr(g_wlan_drv_handle); + } +} diff --git a/target_firmware/magpie_fw_dev/target/wlan/wlan_pci.h b/target_firmware/magpie_fw_dev/target/wlan/wlan_pci.h new file mode 100755 index 0000000..9a724d3 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/wlan/wlan_pci.h @@ -0,0 +1,27 @@ +/* + * @File: wlan_pci.h + * + * @Abstract: + * + * @Notes: + * + * Copyright (c) 2008 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef _WLAN_PCI_H +#define _WLAN_PCI_H + +typedef int (*A_PCI_INIT_FUNC)(void); + +//extern A_PCI_INIT_FUNC g_pci_init_func; + +void wlan_pci_module_init(void); +void wlan_pci_register_drv(adf_drv_info_t *drv); +void wlan_pci_probe(void); +int wlan_pci_config_write(int offset, a_uint32_t val, int width); +int wlan_pci_config_read(int offset, int width); +void wlan_pci_isr(); + +#endif /* #ifndef _WLAN_PCI_H */ diff --git a/target_firmware/magpie_fw_dev/target/wmi/wmi_internal.h b/target_firmware/magpie_fw_dev/target/wmi/wmi_internal.h new file mode 100755 index 0000000..2e4d210 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/wmi/wmi_internal.h @@ -0,0 +1,65 @@ +/* + * @File: + * + * @Abstract: internal data and structure definitions for WMI service + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ + +#ifndef WMI_INTERNAL_H_ +#define WMI_INTERNAL_H_ + +#define WMI_CMD_ALIGNMENT_SIZE 128 + +#ifdef WMI_DEBUG + +/* WMI debug log definitions */ + +#define WMI_DBG0_LOG(debugid) \ + DBGLOG_ARG0_RECORD(DBGLOG_HEADER_UPPER_HALF(debugid, \ + DBGLOG_MODULEID_WMI, 0)) + +#define WMI_DBG1_LOG(debugid, arg1) \ + DBGLOG_ARG1_RECORD(DBGLOG_HEADER_UPPER_HALF(debugid, \ + DBGLOG_MODULEID_WMI, 1), arg1) + +#define WMI_DBG2_LOG(debugid, arg1, arg2) \ + DBGLOG_ARG2_RECORD(DBGLOG_HEADER_UPPER_HALF(debugid, \ + DBGLOG_MODULEID_WMI, 2), arg1, arg2) + +#else +#define WMI_DBG0_LOG(debugid) +#define WMI_DBG1_LOG(debugid, arg1) +#define WMI_DBG2_LOG(debugid, arg1, arg2) +#endif /* WMI_DEBUG */ + +#define EVT_PKT_IN_USE (1 << 0) +#define EVT_PKT_IS_FREE(e) !((e)->Flags & EVT_PKT_IN_USE) +#define EVT_MARK_FREE(e) (e)->Flags &= ~EVT_PKT_IN_USE; +#define EVT_MARK_INUSE(e) (e)->Flags |= EVT_PKT_IN_USE +#define IS_EVT_CLASS_BUFFERED(ec) ((ec) != WMI_EVT_CLASS_DIRECT_BUFFER) + +typedef struct _WMI_POOL_STATE { + int MaxAllocation; /* maximum allocations allowed for this pool */ + int CurrentAllocation; /* current allocations outstanding */ +} WMI_POOL_STATE; + +typedef struct _WMI_SVC_CONTEXT { + htc_handle_t HtcHandle; + pool_handle_t PoolHandle; + int PendingEvents; /* no. of pending events */ + HTC_SERVICE WMIControlService; /* registered control service */ + HTC_ENDPOINT_ID ControlEp; /* endpoint assigned to us */ + WMI_DISPATCH_TABLE *pDispatchHead; /* dispatch list head ptr */ + WMI_DISPATCH_TABLE *pDispatchTail; /* dispatch list tail ptr */ + + // Left a door for extension the structure + void *pReserved; +} WMI_SVC_CONTEXT; + +#endif /*WMI_INTERNAL_H_*/ diff --git a/target_firmware/magpie_fw_dev/target/wmi/wmi_svc.c b/target_firmware/magpie_fw_dev/target/wmi/wmi_svc.c new file mode 100755 index 0000000..2173ae8 --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/wmi/wmi_svc.c @@ -0,0 +1,268 @@ +/* + * @File: + * + * @Abstract: Wireless Module Interface Service Implementation + * + * @Notes: + * + * + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + */ +#include +#include +#include +#include +#include +#include +#include + +#include "wmi_internal.h" + +static void WMIRecvMessageHandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, + adf_nbuf_t pHTCBuf, void *arg) +{ + void *pContext; + WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)arg; + WMI_DISPATCH_TABLE *pCurrentTable; + WMI_DISPATCH_ENTRY*pCurrentEntry; + WMI_CMD_HANDLER pCmdHandler; + A_UINT8* pCmdBuffer; + int i; + A_UINT16 cmd; + A_UINT16 seq; + int length; + a_uint8_t *anbdata; + a_uint32_t anblen; + WMI_CMD_HDR *cmdHdr; + + adf_os_assert(hdr_buf == ADF_NBUF_NULL); + + do { + length = adf_nbuf_len(pHTCBuf); + if (length < sizeof(WMI_CMD_HDR)) { + break; + } + + adf_nbuf_peek_header(pHTCBuf, &anbdata, &anblen); + + pCurrentTable = pWMI->pDispatchHead; + length = length - sizeof(WMI_CMD_HDR); + + cmdHdr = (WMI_CMD_HDR *)anbdata; + cmd = adf_os_ntohs(cmdHdr->commandId); + seq = adf_os_ntohs(cmdHdr->seqNo); + + pCmdBuffer = anbdata + sizeof(WMI_CMD_HDR); + pCmdHandler = NULL; + + while (pCurrentTable != NULL) { + + pContext = pCurrentTable->pContext; + pCurrentEntry = pCurrentTable->pTable; + + /* scan table entries */ + for (i = 0; i < pCurrentTable->NumberOfEntries; i++, pCurrentEntry++) { + if (pCurrentEntry->CmdID == cmd) { + /* found a match */ + pCmdHandler = pCurrentEntry->pCmdHandler; + + /* optionally check length */ + if ((pCurrentEntry->CheckLength != 0) && + (length < pCurrentEntry->CheckLength)) { + /* do not process command */ + pCmdHandler = NULL; + } + /* end search */ + break; + } + } + + if (pCmdHandler != NULL) { + /* found a handler */ + break; + } + + /* scan next table */ + pCurrentTable = pCurrentTable->pNext; + } + + if (NULL == pCmdHandler) { + break; + } + + /* if we get here, we have a command handler to dispatch */ + + /* call dispatch function */ + pCmdHandler(pContext, cmd, seq, pCmdBuffer, length); + + } while (FALSE); + + + /* Invalidate the buffer (including HTC header). Note : we only need to invalidate up to the portion + * that was used (cache invalidate will also round up to the nearest cache line). + * The rest of the buffer should still be coherent. + * */ + + HTC_ReturnBuffers(pWMI->HtcHandle, EndPt, pHTCBuf); +} + +/* send completion handler when any HTC buffers are returned */ +static void _WMI_SendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t pHTCBuf, void *arg) +{ + WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)arg; + WMI_BUF_CONTEXT *ctx; + BUF_POOL_ID poolId; + + ctx = (WMI_BUF_CONTEXT *)adf_nbuf_get_priv(pHTCBuf); + + if ( ctx->EventClass == WMI_EVT_CLASS_CMD_EVENT ) { + poolId = POOL_ID_WMI_SVC_EVENT; + } else { + poolId = POOL_ID_WMI_SVC_CMD_REPLY; + } + + BUF_Pool_free_buf(pWMI->PoolHandle, poolId, pHTCBuf); +} + +static A_UINT8 WMIServiceConnect(HTC_SERVICE *pService, + HTC_ENDPOINT_ID eid, + A_UINT8 *pDataIn, + int LengthIn, + A_UINT8 *pDataOut, + int *pLengthOut) +{ + WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)pService->ServiceCtx; + + /* save the eid to use */ + pWMI->ControlEp = eid; + return HTC_SERVICE_SUCCESS; +} + +/************** public APIS ********************************************/ + +static wmi_handle_t _WMI_Init(WMI_SVC_CONFIG *pWmiConfig) +{ + WMI_SVC_CONTEXT *pWMI = NULL; + int eventSize = WMI_SVC_MAX_BUFFERED_EVENT_SIZE + sizeof(WMI_CMD_HDR) + HTC_HDR_SZ; + + pWMI = (WMI_SVC_CONTEXT *)adf_os_mem_alloc(sizeof(WMI_SVC_CONTEXT)); + if (pWMI == NULL) { + return NULL; + } + + pWMI->pDispatchHead = NULL; + pWMI->PoolHandle = pWmiConfig->PoolHandle; + pWMI->HtcHandle = pWmiConfig->HtcHandle; + + BUF_Pool_create_pool(pWmiConfig->PoolHandle, POOL_ID_WMI_SVC_CMD_REPLY, + pWmiConfig->MaxCmdReplyEvts, eventSize); + + BUF_Pool_create_pool(pWmiConfig->PoolHandle, POOL_ID_WMI_SVC_EVENT, + pWmiConfig->MaxEventEvts, eventSize); + + /* NOTE: since RAM allocation is zero-initialized, there is nothing to do for the + * direct event pool */ + + /* register the WMI control service */ + pWMI->WMIControlService.ProcessRecvMsg = A_INDIR(wmi_svc_api._WMI_RecvMessageHandler); + pWMI->WMIControlService.ProcessSendBufferComplete = A_INDIR(wmi_svc_api._WMI_SendCompleteHandler); + pWMI->WMIControlService.ProcessConnect = A_INDIR(wmi_svc_api._WMI_ServiceConnect); + pWMI->WMIControlService.MaxSvcMsgSize = WMI_SVC_MSG_SIZE + sizeof(WMI_CMD_HDR); + /* all buffers that are sent through the control endpoint are at least WMI_SVC_MAX_BUFFERED_EVENT_SIZE + * in size. Any WMI event that supplies a data buffer must insure that the space in the buffer + * is at least this size. */ + pWMI->WMIControlService.TrailerSpcCheckLimit = WMI_SVC_MAX_BUFFERED_EVENT_SIZE; + pWMI->WMIControlService.ServiceID = WMI_CONTROL_SVC; + pWMI->WMIControlService.ServiceCtx = pWMI; + HTC_RegisterService(pWmiConfig->HtcHandle, &pWMI->WMIControlService); + + return pWMI; +} + +static int _WMI_GetPendingEventsCount(wmi_handle_t handle) +{ + WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; + return pWMI->PendingEvents; +} + +static int _WMI_GetControlEp(wmi_handle_t handle) +{ + WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; + return pWMI->ControlEp; +} + +static void _WMI_RegisterDispatchTable(wmi_handle_t handle, + WMI_DISPATCH_TABLE *pDispatchTable) +{ + WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; + + if (NULL == pWMI->pDispatchHead) { + pWMI->pDispatchHead = pDispatchTable; + pWMI->pDispatchTail = pDispatchTable; + } else { + /* link to the tail */ + pWMI->pDispatchTail->pNext = pDispatchTable; + pWMI->pDispatchTail = pDispatchTable; + } +} + +static adf_nbuf_t _WMI_AllocEvent(wmi_handle_t handle, WMI_EVT_CLASS EventClass, + int Length) +{ + BUF_POOL_ID poolId; + WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; + adf_nbuf_t buf; + WMI_BUF_CONTEXT *ctx; + + if ( EventClass == WMI_EVT_CLASS_CMD_EVENT ) { + poolId = POOL_ID_WMI_SVC_EVENT; + } else { + poolId = POOL_ID_WMI_SVC_CMD_REPLY; + } + + buf = BUF_Pool_alloc_buf(pWMI->PoolHandle, + poolId, + sizeof(WMI_CMD_HDR) + HTC_GetReservedHeadroom(pWMI->HtcHandle)); + + if ( buf != NULL ) { + ctx = (WMI_BUF_CONTEXT *)adf_nbuf_get_priv(buf); + ctx->EventClass = EventClass; + } + return buf; +} + +static void _WMI_SendEvent(wmi_handle_t handle, adf_nbuf_t pEvt, + A_UINT16 EventId, A_UINT16 SeqNo, int Length) +{ + WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; + A_UINT8 *pBuffer; + + pBuffer = adf_nbuf_push_head(pEvt, sizeof(WMI_CMD_HDR)); + A_SET_UINT16_FIELD(pBuffer, WMI_CMD_HDR, commandId, adf_os_htons(EventId)); + A_SET_UINT16_FIELD(pBuffer, WMI_CMD_HDR, seqNo, adf_os_htons(SeqNo)); + + HTC_SendMsg(pWMI->HtcHandle, pWMI->ControlEp, pEvt); +} + +static void _WMI_Shutdown(wmi_handle_t handle) +{ + WMI_SVC_CONTEXT *pWMI = (WMI_SVC_CONTEXT *)handle; + + adf_os_mem_free(pWMI); +} + +void WMI_service_module_install(WMI_SVC_APIS *pTbl) +{ + pTbl->_WMI_Init = _WMI_Init; + pTbl->_WMI_RegisterDispatchTable = _WMI_RegisterDispatchTable; + pTbl->_WMI_AllocEvent = _WMI_AllocEvent; + pTbl->_WMI_SendEvent = _WMI_SendEvent; + pTbl->_WMI_SendCompleteHandler = _WMI_SendCompleteHandler; + pTbl->_WMI_GetPendingEventsCount = _WMI_GetPendingEventsCount; + pTbl->_WMI_GetControlEp = _WMI_GetControlEp; + pTbl->_WMI_Shutdown = _WMI_Shutdown; + pTbl->_WMI_RecvMessageHandler = WMIRecvMessageHandler; + pTbl->_WMI_ServiceConnect = WMIServiceConnect; +} diff --git a/target_firmware/magpie_fw_dev/target/wmi/wmi_svc_api.h b/target_firmware/magpie_fw_dev/target/wmi/wmi_svc_api.h new file mode 100755 index 0000000..ad9c5eb --- /dev/null +++ b/target_firmware/magpie_fw_dev/target/wmi/wmi_svc_api.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + * + * This file contains the API for the Wireless Module Interface (WMI) Service + * + */ + +#ifndef WMI_SVC_API_H_ +#define WMI_SVC_API_H_ + +#include +#include +#include +#include +#include + +#define WMI_SVC_MAX_BUFFERED_EVENT_SIZE 100 +#define WMI_SVC_MSG_SIZE 1536 /* maximum size of any WMI control or event message */ + +/* event classes */ +typedef enum WMI_EVT_CLASS { + WMI_EVT_CLASS_NONE = -1, + WMI_EVT_CLASS_CMD_EVENT = 0, + WMI_EVT_CLASS_CMD_REPLY = 1, + WMI_EVT_CLASS_MAX +} WMI_EVT_CLASS; + +/* command handler callback when a message is dispatched */ +typedef void (* WMI_CMD_HANDLER)(void *pContext, /* application supplied context from dispatch table */ + A_UINT16 Command, /* command ID that was dispatched */ + A_UINT16 SeqNo, + A_UINT8 *pCmdBuffer, /* command data, 256 bytes max, 32-bit aligned */ + int Length); /* length of command (excludes WMI header) */ + +/* configuration settings for the WMI service */ +typedef struct _WMI_SVC_CONFIG { + htc_handle_t HtcHandle; + pool_handle_t PoolHandle; + int MaxCmdReplyEvts; /* total buffers for command replies */ + int MaxEventEvts; /* total buffers for low priority events */ +} WMI_SVC_CONFIG; + +/* command dispatch entry */ +typedef struct _WMI_DISPATCH_ENTRY { + WMI_CMD_HANDLER pCmdHandler; /* dispatch function */ + A_UINT16 CmdID; /* WMI command to dispatch from */ + A_UINT16 CheckLength; /* expected length of command, set to 0 to bypass check */ +} WMI_DISPATCH_ENTRY; + +/* dispatch table that is used to register a set of dispatch entries */ +typedef struct _WMI_DISPATCH_TABLE { + struct _WMI_DISPATCH_TABLE *pNext; /* next dispatch, WMI-reserved */ + void *pContext; /* optional context that is passed to command handlers + assigned to this dispatch table */ + int NumberOfEntries; /* number of elements pointed to by pTable */ + WMI_DISPATCH_ENTRY *pTable; /* start of table */ +} WMI_DISPATCH_TABLE; + +#define WMI_DISPATCH_ENTRY_COUNT(table) \ + (sizeof((table)) / sizeof(WMI_DISPATCH_ENTRY)) + + /* handy macro to declare a dispatch table */ +#define WMI_DECLARE_DISPATCH_TABLE(name,dispatchEntries) \ +WMI_DISPATCH_TABLE name = \ +{ NULL, NULL, WMI_DISPATCH_ENTRY_COUNT(dispatchEntries), dispatchEntries } + + /* macro to programatically set the dispatch table context */ +#define WMI_SET_DISPATCH_CONTEXT(pDispTable, pCtxt) (pDispTable)->pContext = (pCtxt) + +typedef struct _WMI_BUF_CONTEXT { + HTC_BUF_CONTEXT HtcBufCtx; + + WMI_EVT_CLASS EventClass; /* the event class this packet belongs to */ + A_UINT16 Flags; /* internal flags reserved for WMI */ +} WMI_BUF_CONTEXT; + +/* ROM-version, eventually. For now, in RAM */ + +typedef void* wmi_handle_t; + +/* the API table */ +typedef struct _wmi_svc_apis { + wmi_handle_t (* _WMI_Init)(WMI_SVC_CONFIG *pWmiConfig); + void (* _WMI_RegisterDispatchTable)(wmi_handle_t h, WMI_DISPATCH_TABLE *pDispatchTable); + adf_nbuf_t (* _WMI_AllocEvent)(wmi_handle_t h, WMI_EVT_CLASS EventClass, int Length); + void (* _WMI_SendEvent)(wmi_handle_t h, adf_nbuf_t pEvt, A_UINT16 EventId, A_UINT16 SeqNo, int Length); + int (* _WMI_GetPendingEventsCount)(wmi_handle_t handle); + void (* _WMI_SendCompleteHandler)(HTC_ENDPOINT_ID Endpt, adf_nbuf_t pHTCBuf, void *arg); + int (* _WMI_GetControlEp)(wmi_handle_t h); + void (* _WMI_Shutdown)(wmi_handle_t h); + + /* */ + void (*_WMI_RecvMessageHandler)(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, adf_nbuf_t pHTCBuf, void *arg); + A_UINT8 (*_WMI_ServiceConnect)(HTC_SERVICE *pService, HTC_ENDPOINT_ID eid, + A_UINT8 *pDataIn, + int LengthIn, + A_UINT8 *pDataOut, + int *pLengthOut); + + void *pReserved; /* for expansion if need be */ +} WMI_SVC_APIS; + +extern void WMI_service_module_install(WMI_SVC_APIS *pAPIs); + +#endif /*WMI_SVC_API_H_*/ diff --git a/target_firmware/wlan/_ieee80211.h b/target_firmware/wlan/_ieee80211.h new file mode 100755 index 0000000..1e64078 --- /dev/null +++ b/target_firmware/wlan/_ieee80211.h @@ -0,0 +1,96 @@ +/*- + * Copyright (c) 2001 Atsushi Onoe + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/net80211/_ieee80211.h,v 1.2 2004/12/31 22:42:38 sam Exp $ + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/madwifi/net80211/_ieee80211.h#1 $ + */ +#ifndef _NET80211__IEEE80211_H_ +#define _NET80211__IEEE80211_H_ + +enum ieee80211_phytype { + IEEE80211_T_DS, /* direct sequence spread spectrum */ + IEEE80211_T_FH, /* frequency hopping */ + IEEE80211_T_OFDM, /* frequency division multiplexing */ + IEEE80211_T_TURBO, /* high rate OFDM, aka turbo mode */ + IEEE80211_T_HT, /* HT - full GI */ + IEEE80211_T_MAX +}; +#define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclature */ + +/* XXX nOt really a mode; there are really multiple PHY's */ +enum ieee80211_phymode { + IEEE80211_MODE_11NA = 0, + IEEE80211_MODE_11NG = 1, +}; +#define IEEE80211_MODE_MAX (IEEE80211_MODE_11NG+1) + +enum ieee80211_opmode { + IEEE80211_M_STA = 1, /* infrastructure station */ + IEEE80211_M_IBSS = 0, /* IBSS (adhoc) station */ + IEEE80211_M_AHDEMO = 3, /* Old lucent compatible adhoc demo */ + IEEE80211_M_HOSTAP = 6, /* Software Access Point */ + IEEE80211_M_MONITOR = 8, /* Monitor mode */ + IEEE80211_M_WDS = 2 /* WDS link */ +}; + +/* + * 802.11g protection mode. + */ +enum ieee80211_protmode { + IEEE80211_PROT_NONE = 0, /* no protection */ + IEEE80211_PROT_CTSONLY = 1, /* CTS to self */ + IEEE80211_PROT_RTSCTS = 2, /* RTS-CTS */ +}; + +/* + * 802.11 rate set. + */ +#define IEEE80211_RATE_SIZE 8 /* 802.11 standard */ +#define IEEE80211_RATE_MAXSIZE 30 /* max rates we'll handle */ +#define IEEE80211_HT_RATE_SIZE 128 + + +/* + * 11n A-MPDU & A-MSDU limits + */ +#define IEEE80211_AMPDU_LIMIT_MIN (1 * 1024) +#define IEEE80211_AMPDU_LIMIT_MAX (64 * 1024 - 1) +#define IEEE80211_AMPDU_SUBFRAME_MIN 2 +#define IEEE80211_AMPDU_SUBFRAME_MAX 64 +#define IEEE80211_AMPDU_SUBFRAME_DEFAULT 32 +#define IEEE80211_AMSDU_LIMIT_MAX 4096 + +struct ieee80211_rateset { + a_uint8_t rs_nrates; + a_uint8_t rs_rates[IEEE80211_RATE_MAXSIZE]; +}; + +#endif /* _NET80211__IEEE80211_H_ */ diff --git a/target_firmware/wlan/ah.c b/target_firmware/wlan/ah.c new file mode 100755 index 0000000..837627c --- /dev/null +++ b/target_firmware/wlan/ah.c @@ -0,0 +1,195 @@ +#include "opt_ah.h" +#include "ah.h" +#include "ah_internal.h" +#include + +extern struct ath_hal *ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev, + HAL_BUS_HANDLE sh, a_uint32_t flags, HAL_STATUS *status); + +struct ath_hal* +ath_hal_attach_tgt(a_uint32_t devid,HAL_SOFTC sc, + adf_os_device_t dev, HAL_BUS_HANDLE sh, + a_uint32_t flags, HAL_STATUS *error) +{ + struct ath_hal *ah = AH_NULL; + + devid = AR5416_DEVID_PCIE; + ah = ar5416Attach(devid, sc, dev, sh, flags, error); + + return ah; +} + +HAL_STATUS +ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, + a_uint32_t capability, a_uint32_t *result) + +{ + const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; + switch (type) { + case HAL_CAP_TSF_ADJUST: + return HAL_ENOTSUPP; + case HAL_CAP_BSSIDMASK: + return pCap->halBssIdMaskSupport ? HAL_OK : HAL_ENOTSUPP; + case HAL_CAP_VEOL: + return pCap->halVEOLSupport ? HAL_OK : HAL_ENOTSUPP; +#ifdef MAGPIE_MERLIN + case HAL_CAP_RX_STBC: + return HAL_ENOTSUPP; + case HAL_CAP_TX_STBC: + return HAL_ENOTSUPP; +#endif + default: + return HAL_EINVAL; + } +} + +void +ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt) +{ + a_int32_t i; + + if (rt->rateCodeToIndex[0] != 0) + return; + + for (i = 0; i < 32; i++) + rt->rateCodeToIndex[i] = (a_uint8_t) -1; + for (i = 0; i < rt->rateCount; i++) { + a_uint8_t code = rt->info[i].rateCode; + a_uint8_t cix = rt->info[i].controlRate; + + rt->rateCodeToIndex[code] = i; + rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i; + rt->info[i].lpAckDuration = ath_hal_computetxtime(ah, rt, + WLAN_CTRL_FRAME_SIZE, cix, AH_FALSE); + rt->info[i].spAckDuration = ath_hal_computetxtime(ah, rt, + WLAN_CTRL_FRAME_SIZE, cix, AH_TRUE); + } +} + +#define CCK_SIFS_TIME 10 +#define CCK_PREAMBLE_BITS 144 +#define CCK_PLCP_BITS 48 + +#define OFDM_SIFS_TIME 16 +#define OFDM_PREAMBLE_TIME 20 +#define OFDM_PLCP_BITS 22 +#define OFDM_SYMBOL_TIME 4 + +#define OFDM_SIFS_TIME_HALF 32 +#define OFDM_PREAMBLE_TIME_HALF 40 +#define OFDM_PLCP_BITS_HALF 22 +#define OFDM_SYMBOL_TIME_HALF 8 + +#define OFDM_SIFS_TIME_QUARTER 64 +#define OFDM_PREAMBLE_TIME_QUARTER 80 +#define OFDM_PLCP_BITS_QUARTER 22 +#define OFDM_SYMBOL_TIME_QUARTER 16 + +a_uint16_t +ath_hal_computetxtime(struct ath_hal *ah, + const HAL_RATE_TABLE *rates, a_uint32_t frameLen, a_uint16_t rateix, + HAL_BOOL shortPreamble) +{ + a_uint32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime; + a_uint32_t kbps; + + kbps = rates->info[rateix].rateKbps; + + /* + * index can be invalid duting dynamic Turbo transitions. + */ + if(kbps == 0) return 0; + switch (rates->info[rateix].phy) { + + case IEEE80211_T_CCK: + phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; + if (shortPreamble && rates->info[rateix].shortPreamble) + phyTime >>= 1; + numBits = frameLen << 3; + txTime = phyTime + ((numBits * 1000)/kbps); + /* TODO: make sure the same value of txTime can use in all device */ + if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, AH_NULL) != HAL_OK) + txTime = txTime + CCK_SIFS_TIME; + break; + case IEEE80211_T_OFDM: + /* full rate channel */ + bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; + HALASSERT(bitsPerSymbol != 0); + + numBits = OFDM_PLCP_BITS + (frameLen << 3); + numSymbols = asf_howmany(numBits, bitsPerSymbol); + txTime = OFDM_PREAMBLE_TIME + (numSymbols * OFDM_SYMBOL_TIME); + /* TODO: make sure the same value of txTime can use in all device */ + if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, AH_NULL) != HAL_OK) + txTime = txTime + OFDM_SIFS_TIME; + break; + default: + txTime = 0; + break; + } + return txTime; +} + +#undef CCK_SIFS_TIME +#undef CCK_PREAMBLE_BITS +#undef CCK_PLCP_BITS + +#undef OFDM_SIFS_TIME +#undef OFDM_PREAMBLE_TIME +#undef OFDM_PLCP_BITS +#undef OFDM_SYMBOL_TIME + +#ifdef MAGPIE_MERLIN +a_uint32_t +ath_hal_get_curmode(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan) +{ + if (!chan) + return HAL_MODE_11NG; + + if (IS_CHAN_NA(chan)) + return HAL_MODE_11NA; + + if (IS_CHAN_A(chan)) + return HAL_MODE_11A; + + if (IS_CHAN_NG(chan)) + return HAL_MODE_11NG; + + if (IS_CHAN_G(chan)) + return HAL_MODE_11G; + + if (IS_CHAN_B(chan)) + return HAL_MODE_11B; + + HALASSERT(0); + return HAL_MODE_11NG; +} + +#endif + +HAL_BOOL +ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val) +{ +#define AH_TIMEOUT_11N 100000 +#define AH_TIMEOUT_11G 1000 + + a_int32_t i; + + if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, AH_NULL) == HAL_OK) { + for (i = 0; i < AH_TIMEOUT_11N; i++) { + if ((OS_REG_READ(ah, reg) & mask) == val) + return AH_TRUE; + OS_DELAY(10); + } + } else { + for (i = 0; i < AH_TIMEOUT_11G; i++) { + if ((OS_REG_READ(ah, reg) & mask) == val) + return AH_TRUE; + OS_DELAY(10); + } + } + return AH_FALSE; + +#undef AH_TIMEOUT_11N +#undef AH_TIMEOUT_11G +} diff --git a/target_firmware/wlan/ah.h b/target_firmware/wlan/ah.h new file mode 100755 index 0000000..c86d115 --- /dev/null +++ b/target_firmware/wlan/ah.h @@ -0,0 +1,457 @@ +#ifndef _ATH_AH_H_ +#define _ATH_AH_H_ + +#include +#include + +#ifndef __ahdecl +#define __ahdecl +#endif + +#define AR5416_DEVID_PCIE 0x0024 /* AR5416 PCI-E (XB) (Owl) */ + +typedef enum { + HAL_OK = 0, /* No error */ + HAL_ENXIO = 1, /* No hardware present */ + HAL_ENOMEM = 2, /* Memory allocation failed */ + HAL_EIO = 3, /* Hardware didn't respond as expected */ + HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ + HAL_EEVERSION = 5, /* EEPROM version invalid */ + HAL_EELOCKED = 6, /* EEPROM unreadable */ + HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ + HAL_EEREAD = 8, /* EEPROM read problem */ + HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ + HAL_EESIZE = 10, /* EEPROM size not supported */ + HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ + HAL_EINVAL = 12, /* Invalid parameter to function */ + HAL_ENOTSUPP = 13, /* Hardware revision not supported */ + HAL_ESELFTEST = 14, /* Hardware self-test failed */ + HAL_EINPROGRESS = 15, /* Operation incomplete */ + HAL_FULL_RESET = 16, /* Full reset done */ +} HAL_STATUS; + +typedef enum { + AH_FALSE = 0, + AH_TRUE = 1, +} HAL_BOOL; + +typedef enum { + HAL_CAP_VEOL = 0, + HAL_CAP_BSSIDMASK = 1, + HAL_CAP_TSF_ADJUST = 2, + HAL_CAP_RX_STBC = 3, + HAL_CAP_TX_STBC = 4, + HAL_CAP_HT = 5, + HAL_CAP_RTS_AGGR_LIMIT = 6, +} HAL_CAPABILITY_TYPE; + +typedef enum { + HAL_M_STA = 1, + HAL_M_IBSS = 0, + HAL_M_HOSTAP = 6, + HAL_M_MONITOR = 8, +} HAL_OPMODE; + +typedef enum { + HAL_TX_QUEUE_INACTIVE = 0, + HAL_TX_QUEUE_DATA = 1, + HAL_TX_QUEUE_BEACON = 2, + HAL_TX_QUEUE_CAB = 3, + HAL_TX_QUEUE_PSPOLL = 4, + HAL_TX_QUEUE_UAPSD = 5, +} HAL_TX_QUEUE; + +typedef enum { + HAL_WME_AC_BK = 0, + HAL_WME_AC_BE = 1, + HAL_WME_AC_VI = 2, + HAL_WME_AC_VO = 3, + HAL_WME_UPSD = 4, + HAL_XR_DATA = 5, +} HAL_TX_QUEUE_SUBTYPE; + +#define HAL_NUM_TX_QUEUES 10 + +typedef enum { + HAL_PKT_TYPE_NORMAL = 0, + HAL_PKT_TYPE_ATIM = 1, + HAL_PKT_TYPE_PSPOLL = 2, + HAL_PKT_TYPE_BEACON = 3, + HAL_PKT_TYPE_PROBE_RESP = 4, + HAL_PKT_TYPE_CHIRP = 5, + HAL_PKT_TYPE_GRP_POLL = 6, +} HAL_PKT_TYPE; + +typedef enum { + HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ + HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ +} HAL_HT_RXCLEAR; + +typedef enum { + HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ + HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ + HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ + HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ + HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ + HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ + HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */ + HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ + HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ +#ifdef MAGPIE_MERLIN + HAL_RX_FILTER_PHYRADAR = 0x00002000, /* Allow phy radar errors*/ + HAL_RX_FILTER_PSPOLL = 0x00004000, /* Allow PSPOLL frames */ + /* + ** PHY "Pseudo bits" should be in the upper 16 bits since the lower + ** 16 bits actually correspond to register 0x803c bits + */ +#else + HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors*/ +#endif +} HAL_RX_FILTER; + +#define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */ +#define CHANNEL_HALF 0x4000 /* Half rate channel */ + +typedef enum { + HAL_INT_RX = 0x00000001, /* Non-common mapping */ + HAL_INT_RXDESC = 0x00000002, + HAL_INT_RXNOFRM = 0x00000008, + HAL_INT_RXEOL = 0x00000010, + HAL_INT_RXORN = 0x00000020, + HAL_INT_TX = 0x00000040, /* Non-common mapping */ + HAL_INT_TXDESC = 0x00000080, + HAL_INT_TXURN = 0x00000800, + HAL_INT_MIB = 0x00001000, + HAL_INT_RXPHY = 0x00004000, + HAL_INT_RXKCM = 0x00008000, + HAL_INT_SWBA = 0x00010000, + HAL_INT_BMISS = 0x00040000, + HAL_INT_BNR = 0x00100000, /* Non-common mapping */ + HAL_INT_GPIO = 0x01000000, + HAL_INT_CST = 0x02000000, /* Non-common mapping */ + HAL_INT_GTT = 0x20000000, /* Non-common mapping */ + HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ + HAL_INT_GLOBAL = 0x80000000, /* Set/clear IER */ + HAL_INT_GENTIMER =0x08000000, /* Non-common mapping */ + + /* Interrupt bits that map directly to ISR/IMR bits */ + HAL_INT_COMMON = HAL_INT_RXNOFRM + | HAL_INT_RXDESC + | HAL_INT_RXEOL + | HAL_INT_RXORN + | HAL_INT_TXURN + | HAL_INT_TXDESC + | HAL_INT_MIB + | HAL_INT_RXPHY + | HAL_INT_RXKCM + | HAL_INT_SWBA + | HAL_INT_BMISS + | HAL_INT_GPIO, + HAL_INT_NOCARD = 0xffffffff /* To signal the card was removed */ +} HAL_INT; + +#ifdef MAGPIE_MERLIN + +#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ +#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ +#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ +#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ + +/* 11n */ +typedef enum { + HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ + HAL_HT_MACMODE_2040 = 1, /* 20/40 MHz operation */ +} HAL_HT_MACMODE; + +typedef enum { + HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ + HAL_HT_PHYMODE_2040 = 1, /* 20/40 MHz operation */ +} HAL_HT_PHYMODE; + +typedef enum { + HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ + HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ +} HAL_HT_EXTPROTSPACING; + +typedef struct { + HAL_HT_MACMODE ht_macmode; /* MAC - 20/40 mode */ + HAL_HT_PHYMODE ht_phymode; /* PHY - 20/40 mode */ + a_int8_t ht_extoff; /* ext channel offset */ + HAL_HT_EXTPROTSPACING ht_extprotspacing; /* ext channel protection spacing */ +} HAL_HT_CWM; + +typedef struct { + a_uint8_t ht_txchainmask; /* tx chain mask */ + a_uint8_t ht_rxchainmask; /* rx chain mask */ +} HAL_HT_MISC; + +typedef struct { + HAL_HT_CWM cwm; + HAL_HT_MISC misc; +} HAL_HT; + +/* channelFlags */ +#define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */ +#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ +#define CHANNEL_CCK 0x0020 /* CCK channel */ +#define CHANNEL_OFDM 0x0040 /* OFDM channel */ +#define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */ +#define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */ +#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */ +#define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */ +#define CHANNEL_XR 0x0800 /* XR channel */ +#define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */ +#define CHANNEL_HALF 0x4000 /* Half rate channel */ +#define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */ +#define CHANNEL_HT20 0x10000 /* HT20 channel */ +#define CHANNEL_HT40 0x20000 /* HT40 channel */ +#define CHANNEL_HT40U 0x40000 /* control channel can be upper channel */ +#define CHANNEL_HT40L 0x80000 /* control channel can be lower channel */ + +/* privFlags */ +#define CHANNEL_INTERFERENCE 0x01 +#define CHANNEL_DFS 0x02 /* DFS required on channel */ +#define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */ +#define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */ + +#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) +#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) +#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) +#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO) +#define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_108A CHANNEL_T +#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) + +#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) +#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) +#define CHANNEL_G_HT40 (CHANNEL_2GHZ|CHANNEL_HT20|CHANNEL_HT40) +#define CHANNEL_A_HT40 (CHANNEL_5GHZ|CHANNEL_HT20|CHANNEL_HT40) +#define CHANNEL_ALL \ + (CHANNEL_OFDM | \ + CHANNEL_CCK | \ + CHANNEL_2GHZ | \ + CHANNEL_5GHZ | \ + CHANNEL_TURBO | \ + CHANNEL_HT20 | \ + CHANNEL_HT40) +#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) + +typedef struct { + a_int32_t rateCount; + a_uint8_t rateCodeToIndex[32]; + struct { + a_uint8_t valid; + a_uint8_t phy; + a_int16_t txPower; + a_int16_t txPower2Chains; + a_int16_t txPower3Chains; + a_uint32_t rateKbps; + a_uint8_t rateCode; + a_uint8_t shortPreamble; + a_uint8_t dot11Rate; + a_uint8_t controlRate; + a_uint16_t lpAckDuration; + a_uint16_t spAckDuration; + } info[32]; +} HAL_RATE_TABLE; + +typedef struct { + a_uint32_t Tries; + a_uint32_t Rate; + a_uint32_t PktDuration; + a_uint32_t ChSel; + a_uint32_t RateFlags; + a_uint32_t RateIndex; + a_uint32_t TxPowerCap; /* in 1/2 dBm units */ +} HAL_11N_RATE_SERIES; + +#else + +typedef struct { + a_int32_t rateCount; + a_uint8_t rateCodeToIndex[32]; + struct { + a_uint8_t valid; + a_uint8_t phy; + a_uint32_t rateKbps; + a_uint8_t rateCode; + a_uint8_t shortPreamble; + a_uint8_t dot11Rate; + a_uint8_t controlRate; + a_uint16_t lpAckDuration; + a_uint16_t spAckDuration; + } info[32]; +} HAL_RATE_TABLE; + +#define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ +#define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ +#define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ +#define HAL_RATESERIES_STBC 0x0008 /* use STBC for series */ + +typedef struct { + a_uint32_t Tries; + a_uint32_t Rate; + a_uint32_t PktDuration; + a_uint32_t ChSel; + a_uint32_t RateFlags; +} HAL_11N_RATE_SERIES; + +#endif + +enum { + HAL_MODE_11A = 0x001, /* 11a channels */ + HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ + HAL_MODE_11B = 0x004, /* 11b channels */ + HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ + HAL_MODE_11G = 0x008, /* XXX historical */ + HAL_MODE_108G = 0x020, /* 11a+Turbo channels */ + HAL_MODE_108A = 0x040, /* 11g+Turbo channels */ + HAL_MODE_XR = 0x100, /* XR channels */ + HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */ + HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */ + HAL_MODE_11NG = 0x4000, /* 11ng channels */ + HAL_MODE_11NA = 0x8000, /* 11na channels */ + HAL_MODE_ALL = 0xffff +}; + +typedef enum { + HAL_KEY_TYPE_CLEAR, + HAL_KEY_TYPE_WEP, + HAL_KEY_TYPE_AES, + HAL_KEY_TYPE_TKIP, + HAL_KEY_TYPE_WAPI, +} HAL_KEY_TYPE; + +struct ath_desc; +struct ath_rx_status; + +struct ath_hal +{ + a_uint32_t ah_magic; + HAL_SOFTC ah_sc; + HAL_BUS_HANDLE ah_sh; + adf_os_device_t ah_dev; + + a_uint32_t ah_macVersion; + a_uint16_t ah_macRev; + a_uint16_t ah_phyRev; + const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, + a_uint32_t mode); + void __ahdecl(*ah_detach)(struct ath_hal*); + HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, + HAL_BOOL incTrigLevel); + + /* Misc Functions */ + HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, + HAL_CAPABILITY_TYPE, a_uint32_t capability, + a_uint32_t *result); + void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, a_uint32_t); + + HAL_BOOL __ahdecl(*ah_updateCTSForBursting)(struct ath_hal *, + struct ath_desc *, struct ath_desc *, + struct ath_desc *, struct ath_desc *, + a_uint32_t, a_uint32_t); + void __ahdecl(*ah_setRxFilter)(struct ath_hal*, a_uint32_t); + + + /* Target Transmit Functions */ + + a_uint32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, a_uint32_t); + HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, a_uint32_t, a_uint32_t txdp); + a_uint32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, a_uint32_t q); + HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, a_uint32_t); + HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, a_uint32_t); + + HAL_BOOL __ahdecl(*ah_abortTxDma)(struct ath_hal *); + + void __ahdecl(*ah_set11nTxDesc)(struct ath_hal *ah, + struct ath_desc *ds, + a_uint32_t pktLen, HAL_PKT_TYPE type, + a_uint32_t txPower, a_uint32_t keyIx, + HAL_KEY_TYPE keyType, + a_uint32_t flags); + void __ahdecl(*ah_set11nRateScenario)(struct ath_hal *ah, + struct ath_desc *ds, + a_uint32_t durUpdateEn, + a_uint32_t rtsctsRate, + a_uint32_t rtsctsDuration, + HAL_11N_RATE_SERIES series[], + a_uint32_t nseries, a_uint32_t flags); + void __ahdecl(*ah_set11nAggrFirst)(struct ath_hal *ah, + struct ath_desc *ds, a_uint32_t aggrLen, + a_uint32_t numDelims); + void __ahdecl(*ah_set11nAggrMiddle)(struct ath_hal *ah, + struct ath_desc *ds, a_uint32_t numDelims); + void __ahdecl(*ah_set11nAggrLast)(struct ath_hal *ah, + struct ath_desc *ds); + void __ahdecl(*ah_clr11nAggr)(struct ath_hal *ah, + struct ath_desc *ds); + void __ahdecl(*ah_set11nBurstDuration)(struct ath_hal *ah, + struct ath_desc *ds, + a_uint32_t burstDuration); + void __ahdecl(*ah_set11nVirtualMoreFrag)(struct ath_hal *ah, + struct ath_desc *ds, a_uint32_t vmf); + + HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, + a_uint32_t pktLen, a_uint32_t hdrLen, + HAL_PKT_TYPE type, a_uint32_t txPower, + a_uint32_t txRate0, a_uint32_t txTries0, + a_uint32_t keyIx, a_uint32_t antMode, a_uint32_t flags, + a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration, + a_uint32_t compicvLen, a_uint32_t compivLen, + a_uint32_t comp); + HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, + a_uint32_t segLen, HAL_BOOL firstSeg, + HAL_BOOL lastSeg, const struct ath_desc *); + HAL_BOOL __ahdecl (*ah_fillKeyTxDesc) (struct ath_hal *, struct ath_desc *, HAL_KEY_TYPE); + HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_desc*); + void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, a_uint32_t *); + void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); + HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const a_uint8_t*); + void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); + void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, + a_uint32_t filter0, a_uint32_t filter1); + + a_uint32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); + u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); + void __ahdecl(*ah_resetTsf)(struct ath_hal*); + + /* Target receive Functions */ + a_uint32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); + void __ahdecl(*ah_setRxDP)(struct ath_hal*, a_uint32_t rxdp); + HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, + a_uint32_t size, a_uint32_t flags); + HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *, + a_uint32_t phyAddr, struct ath_desc *next, u_int64_t tsf); + HAL_STATUS __ahdecl(*ah_procRxDescFast)(struct ath_hal *ah, + struct ath_desc *ds, a_uint32_t pa, + struct ath_desc *nds, + struct ath_rx_status *rx_stats); + HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); + void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); + void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); + void __ahdecl(*ah_enableReceive)(struct ath_hal*); + + /* Interrupt functions */ + HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); + HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); + HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); + HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); +}; + + +extern struct ath_hal * __ahdecl ath_hal_attach_tgt(a_uint32_t devid, HAL_SOFTC, + adf_os_device_t dev, HAL_BUS_HANDLE sh, + a_uint32_t flags, HAL_STATUS* status); + +extern const HAL_RATE_TABLE * __ahdecl ath_hal_getratetable(struct ath_hal *, + a_uint32_t mode); + +extern a_uint16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, + const HAL_RATE_TABLE *rates, + a_uint32_t frameLen, + a_uint16_t rateix, + HAL_BOOL shortPreamble); +#endif /* _ATH_AH_H_ */ diff --git a/target_firmware/wlan/ah_desc.h b/target_firmware/wlan/ah_desc.h new file mode 100755 index 0000000..0a4c673 --- /dev/null +++ b/target_firmware/wlan/ah_desc.h @@ -0,0 +1,144 @@ +#ifndef _DEV_ATH_DESC_H +#define _DEV_ATH_DESC_H + +#include +#include + +#define HAL_TXSTAT_ALTRATE 0x80 +#define ts_rssi ts_rssi_combined + +struct ath_tx_status { + a_uint32_t ts_tstamp; + a_uint16_t ts_seqnum; + a_uint8_t ts_status; + a_uint8_t ts_flags; + a_uint8_t ts_rate; + int8_t ts_rssi_combined; + int8_t ts_rssi_ctl0; + int8_t ts_rssi_ctl1; + int8_t ts_rssi_ctl2; + int8_t ts_rssi_ext0; + int8_t ts_rssi_ext1; + int8_t ts_rssi_ext2; + a_uint8_t ts_shortretry; + a_uint8_t ts_longretry; + a_uint8_t ts_virtcol; + a_uint8_t ts_antenna; + a_uint32_t ba_low; + a_uint32_t ba_high; + a_uint32_t evm0; + a_uint32_t evm1; + a_uint32_t evm2; +}; + +#define HAL_TXERR_XRETRY 0x01 +#define HAL_TXERR_FILT 0x02 +#define HAL_TXERR_FIFO 0x04 +#define HAL_TXERR_XTXOP 0x08 +#define HAL_TXERR_TIMER_EXPIRED 0x10 + +#define HAL_TX_BA 0x01 +#define HAL_TX_PWRMGMT 0x02 +#define HAL_TX_DESC_CFG_ERR 0x04 +#define HAL_TX_DATA_UNDERRUN 0x08 +#define HAL_TX_DELIM_UNDERRUN 0x10 +#define HAL_TX_SW_FILTERED 0x80 + +struct ath_rx_status { + a_uint64_t rs_tstamp; + a_uint16_t rs_datalen; + a_uint8_t rs_status; + a_uint8_t rs_phyerr; + int8_t rs_rssi_combined; + int8_t rs_rssi_ctl0; + int8_t rs_rssi_ctl1; + int8_t rs_rssi_ctl2; + int8_t rs_rssi_ext0; + int8_t rs_rssi_ext1; + int8_t rs_rssi_ext2; + a_uint8_t rs_keyix; + a_uint8_t rs_rate; + a_uint8_t rs_antenna; + a_uint8_t rs_more; + a_uint8_t rs_isaggr; + a_uint8_t rs_moreaggr; + a_uint8_t rs_num_delims; + a_uint8_t rs_flags; + a_uint8_t rs_dummy; + a_uint32_t evm0; + a_uint32_t evm1; + a_uint32_t evm2; +}; + +#define rs_rssi rs_rssi_combined + +#define HAL_RXERR_CRC 0x01 +#define HAL_RXERR_PHY 0x02 +#define HAL_RXERR_FIFO 0x04 +#define HAL_RXERR_DECRYPT 0x08 +#define HAL_RXERR_MIC 0x10 + +#define HAL_RX_MORE 0x01 +#define HAL_RX_MORE_AGGR 0x02 +#define HAL_RX_GI 0x04 +#define HAL_RX_2040 0x08 +#define HAL_RX_DELIM_CRC_PRE 0x10 +#define HAL_RX_DELIM_CRC_POST 0x20 +#define HAL_RX_DECRYPT_BUSY 0x40 + + + +#define HAL_RXKEYIX_INVALID ((a_uint8_t) -1) + +#define HAL_TXKEYIX_INVALID ((a_uint32_t) -1) + +/* + * The following definitions are passed directly + * the hardware and managed by the HAL. Drivers + * should not touch those elements marked opaque. + */ +#define ATH_GENERIC_DESC \ + a_uint32_t ds_link; \ + a_uint32_t ds_data; \ + a_uint32_t ds_ctl0; \ + a_uint32_t ds_ctl1; + +struct ath_desc { + ATH_GENERIC_DESC +} adf_os_packed; + +struct ath_rx_desc { + ATH_GENERIC_DESC + a_uint32_t ds_hw[9]; + adf_nbuf_t ds_nbuf; + adf_os_dma_map_t ds_dmap; + adf_os_dmamap_info_t ds_dmap_info; + adf_os_dma_addr_t ds_daddr; + asf_tailq_entry(ath_rx_desc) ds_list; +} adf_os_packed; + +struct ath_tx_desc { + ATH_GENERIC_DESC + a_uint32_t ds_hw[20]; + union { + struct ath_tx_status tx; + } ds_us; +} adf_os_packed; + +#define ds_txstat ds_us.tx + + +#define HAL_TXDESC_CLRDMASK 0x0001 +#define HAL_TXDESC_NOACK 0x0002 +#define HAL_TXDESC_RTSENA 0x0004 +#define HAL_TXDESC_CTSENA 0x0008 +#define HAL_TXDESC_INTREQ 0x0010 +#define HAL_TXDESC_VEOL 0x0020 +#define HAL_TXDESC_EXT_ONLY 0x0040 +#define HAL_TXDESC_EXT_AND_CTL 0x0080 +#define HAL_TXDESC_VMF 0x0100 + + +#define HAL_RXDESC_INTREQ 0x0020 + +#endif diff --git a/target_firmware/wlan/ah_internal.h b/target_firmware/wlan/ah_internal.h new file mode 100755 index 0000000..36d96bd --- /dev/null +++ b/target_firmware/wlan/ah_internal.h @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * Copyright (c) 2002-2005 Atheros Communications, Inc. + * All rights reserved. + * + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/hal/main/ah_internal.h#2 $ + */ +#ifndef _ATH_AH_INTERAL_H_ +#define _ATH_AH_INTERAL_H_ + +#include + +#define IEEE80211_AMPDU_LIMIT_MAX (64 * 1024 - 1) + +#define AH_NULL 0 +#define AH_MIN(a,b) ((a)<(b)?(a):(b)) +#define AH_MAX(a,b) ((a)>(b)?(a):(b)) + +/* + * Common assertion interface. Note: it is a bad idea to generate + * an assertion failure for any recoverable event. Instead catch + * the violation and, if possible, fix it up or recover from it; either + * with an error return value or a diagnostic messages. System software + * does not panic unless the situation is hopeless. + */ +#ifdef AH_ASSERT +#define HALASSERT(_x) do { \ + adf_os_assert(_x) \ + } while (0) +#else +#define HALASSERT(_x) +#endif /* AH_ASSERT */ + +#ifndef NBBY +#define NBBY 8 /* number of bits/byte */ +#endif + +#define IEEE80211_ADDR_LEN 6 + +/* + * Internal form of a HAL_CHANNEL. Note that the structure + * must be defined such that you can cast references to a + * HAL_CHANNEL so don't shuffle the first two members. + */ +typedef struct { + a_uint16_t channel; /* NB: must be first for casting */ + a_uint32_t channelFlags; + a_uint8_t privFlags; + int8_t maxRegTxPower; + int8_t maxTxPower; + int8_t minTxPower; /* as above... */ + a_uint8_t regClassId; /* Regulatory class id */ + HAL_BOOL bssSendHere; + a_uint8_t gainI; + HAL_BOOL iqCalValid; + HAL_BOOL oneTimeCalsDone; + int8_t iCoff; + int8_t qCoff; + a_int16_t rawNoiseFloor; + a_int16_t finalNoiseFloor; + int8_t antennaMax; + a_uint32_t regDmnFlags; /* Flags for channel use in reg */ + a_uint32_t conformanceTestLimit; /* conformance test limit from reg domain */ + a_uint16_t mainSpur; /* cached spur value for this cahnnel */ + u_int64_t ah_tsf_last; /* tsf @ which time accured is computed */ + u_int64_t ah_channel_time; /* time on the channel */ + u_int64_t dfsTsf; /* Tsf when channel leaves NOL */ +} HAL_CHANNEL_INTERNAL; + +typedef struct { + a_uint32_t halChanSpreadSupport : 1, + halSleepAfterBeaconBroken : 1, + halCompressSupport : 1, + halBurstSupport : 1, + halFastFramesSupport : 1, + halChapTuningSupport : 1, + halTurboGSupport : 1, + halTurboPrimeSupport : 1, + halXrSupport : 1, + halMicAesCcmSupport : 1, + halMicCkipSupport : 1, + halMicTkipSupport : 1, + halCipherAesCcmSupport : 1, + halCipherCkipSupport : 1, + halCipherTkipSupport : 1, + halPSPollBroken : 1, + halVEOLSupport : 1, + halBssIdMaskSupport : 1, + halMcastKeySrchSupport : 1, + halTsfAddSupport : 1, + halChanHalfRate : 1, + halChanQuarterRate : 1, + halHTSupport : 1, + halRxStbcSupport : 1, + halTxStbcSupport : 1, + halGTTSupport : 1, + halFastCCSupport : 1, + halExtChanDfsSupport : 1, + halUseCombinedRadarRssi : 1, + halCSTSupport : 1, + halRifsRxSupport : 1, + halRifsTxSupport : 1, +#ifdef MAGPIE_MERLIN + halforcePpmSupport : 1, + halAutoSleepSupport : 1, + hal4kbSplitTransSupport : 1, + halEnhancedPmSupport : 1, + halMbssidAggrSupport : 1, + halTkipWepHtRateSupport : 1, +#endif + halRfSilentSupport : 1; + a_uint32_t halWirelessModes; + a_uint16_t halTotalQueues; + a_uint16_t halKeyCacheSize; + a_uint16_t halLow5GhzChan, halHigh5GhzChan; + a_uint16_t halLow2GhzChan, halHigh2GhzChan; + a_uint16_t halNumMRRetries; + a_uint8_t halTxChainMask; + a_uint8_t halRxChainMask; + a_uint16_t halRtsAggrLimit; + a_uint16_t halJapanRegCap; + a_uint8_t halNumGpioPins; +} HAL_CAPABILITIES; + + +#if !defined(_NET_IF_IEEE80211_H_) && !defined(_NET80211__IEEE80211_H_) +/* + * Stuff that would naturally come from _ieee80211.h + */ +#define IEEE80211_ADDR_LEN 6 +#define IEEE80211_WEP_KEYLEN 5 /* 40bit */ +#define IEEE80211_WEP_IVLEN 3 /* 24bit */ +#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ +#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ +#define IEEE80211_CRC_LEN 4 +#define IEEE80211_MTU 1500 +#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ + (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) + +#define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */ + +enum { + IEEE80211_T_DS, /* direct sequence spread spectrum */ + IEEE80211_T_FH, /* frequency hopping */ + IEEE80211_T_OFDM, /* frequency division multiplexing */ + IEEE80211_T_TURBO, /* high rate DS */ + IEEE80211_T_HT, /* HT - full GI */ + IEEE80211_T_MAX +}; +#define IEEE80211_T_CCK IEEE80211_T_DS /* more common nomenclatur */ +#endif /* _NET_IF_IEEE80211_H_ */ + +/* NB: these are defined privately until XR support is announced */ +enum { + ATHEROS_T_XR = IEEE80211_T_MAX, /* extended range */ +}; + +struct ath_hal_private { + struct ath_hal h; + + a_uint32_t ah_macVersion; + a_uint16_t ah_macRev; + a_uint16_t ah_phyRev; + + HAL_CAPABILITIES ah_caps; /* device capabilities */ + HAL_CHANNEL_INTERNAL *ah_curchan; /* current channel */ +}; + +#define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah)) + +#define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \ + (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20)) +#define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B) +#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_108G|CHANNEL_G)) == CHANNEL_G) || \ + (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20)) +#define IS_CHAN_108G(_c)(((_c)->channelFlags & CHANNEL_108G) == CHANNEL_108G) +#define IS_CHAN_T(_c) (((_c)->channelFlags & CHANNEL_T) == CHANNEL_T) +#define IS_CHAN_X(_c) (((_c)->channelFlags & CHANNEL_X) == CHANNEL_X) +#define IS_CHAN_PUREG(_c) \ + (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG) +#define IS_CHAN_NA(_c) (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) +#define IS_CHAN_NG(_c) (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) + +#define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0) +#define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0) +#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) +#define IS_CHAN_XR(_c) (((_c)->channelFlags & CHANNEL_XR) != 0) +#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) +#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) +#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) +#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) +#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) +#define IS_CHAN_HT(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0) +#define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0) +#define IS_CHAN_HT40(_c) (((_c)->channelFlags & CHANNEL_HT40) != 0) + +#define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) + +/* + * Register manipulation macros that expect bit field defines + * to follow the convention that an _S suffix is appended for + * a shift count, while the field mask has no suffix. + */ +#define SM(_v, _f) (((_v) << _f##_S) & _f) +#define MS(_v, _f) (((_v) & _f) >> _f##_S) +#define OS_REG_RMW_FIELD(_a, _r, _f, _v) \ + OS_REG_WRITE(_a, _r, \ + (OS_REG_READ(_a, _r) &~ _f) | (((_v) << _f##_S) & _f)) +#define OS_REG_RMW(_a, _r, _set, _clr) \ + OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set)) +#define OS_REG_SET_BIT(_a, _r, _f) \ + OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | _f) +#define OS_REG_CLR_BIT(_a, _r, _f) \ + OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ _f) + + +/* wait for the register contents to have the specified value */ +extern HAL_BOOL ath_hal_wait(struct ath_hal *, a_uint32_t reg, + a_uint32_t mask, a_uint32_t val); + +extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list); + +/* allocate and free memory */ +extern void *ath_hal_malloc(size_t); +extern void ath_hal_free(void *); + +/* + * Generic get/set capability support. Each chip overrides + * this routine to support chip-specific capabilities. + */ +extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah, + HAL_CAPABILITY_TYPE type, a_uint32_t capability, + a_uint32_t *result); +extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah, + HAL_CAPABILITY_TYPE type, a_uint32_t capability, + a_uint32_t setting, HAL_STATUS *status); + +#endif /* _ATH_AH_INTERAL_H_ */ diff --git a/target_firmware/wlan/ah_osdep.c b/target_firmware/wlan/ah_osdep.c new file mode 100755 index 0000000..bfcc608 --- /dev/null +++ b/target_firmware/wlan/ah_osdep.c @@ -0,0 +1,130 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ah.h" +#include +#include "ah_osdep.h" + +a_uint32_t __ahdecl +ath_hal_getuptime(struct ath_hal *ah) +{ + return adf_os_getuptime(); +} + +struct ath_hal * +_ath_hal_attach_tgt(a_uint32_t devid, HAL_SOFTC sc, + adf_os_device_t dev,HAL_BUS_HANDLE sh, a_uint32_t flags, void* s) +{ + HAL_STATUS status; + struct ath_hal *ah = ath_hal_attach_tgt(devid,sc,dev,sh, flags, &status); + adf_os_print(" ath_hal = %p \n",ah); + *(HAL_STATUS *)s = status; + return ah; +} + +void +ath_hal_detach(struct ath_hal *ah) +{ + (*ah->ah_detach)(ah); +} + +extern void *global_hdl; + +/* + * Memory-mapped device register read/write. These are here + * as routines when debugging support is enabled and/or when + * explicitly configured to use function calls. The latter is + * for architectures that might need to do something before + * referencing memory (e.g. remap an i/o window). + * + * NB: see the comments in ah_osdep.h about byte-swapping register + * reads and writes to understand what's going on below. + */ +void __ahdecl +ath_hal_reg_write_target(struct ath_hal *ah, a_uint32_t reg, a_uint32_t val) +{ + adf_os_reg_write32(ah->ah_dev, reg, val); +} + +a_uint32_t __ahdecl +ath_hal_reg_read_target(struct ath_hal *ah, a_uint32_t reg) +{ + a_uint32_t val; + + val = adf_os_reg_read32(ah->ah_dev, reg); + + return val; +} + +/* + * Delay n microseconds. + */ +void __ahdecl +ath_hal_delay(a_int32_t n) +{ + adf_os_udelay(n); +} + +/* + * Allocate/free memory. + */ +void * __ahdecl +ath_hal_malloc(adf_os_size_t size) +{ + void *p; + + p = adf_os_mem_alloc(size); + if (p) + adf_os_mem_zero(p, size); + + return p; +} + +void __ahdecl +ath_hal_free(void* p) +{ + adf_os_mem_free(p); +} + +void __ahdecl +ath_hal_memzero(void *dst, adf_os_size_t n) +{ + adf_os_mem_set(dst, 0, n); +} + +void * __ahdecl +ath_hal_memcpy(void *dst, void *src, adf_os_size_t n) +{ + adf_os_mem_copy(dst, src, n); + return 0; +} + +/* + * Print/log message support. + */ +void __ahdecl +ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap) +{ +} + +enum { + DEV_ATH = 9, /* XXX must match driver */ +}; + +adf_os_module_dep(hal, adf_net); +adf_os_module_dep(hal, hal); +adf_os_virt_module_name(hal); diff --git a/target_firmware/wlan/ah_osdep.h b/target_firmware/wlan/ah_osdep.h new file mode 100755 index 0000000..54b2a9b --- /dev/null +++ b/target_firmware/wlan/ah_osdep.h @@ -0,0 +1,191 @@ +/*- + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros + * Communications, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. The materials contained herein are unmodified and are used + * unmodified. + * 2. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following NO + * ''WARRANTY'' disclaimer below (''Disclaimer''), without + * modification. + * 3. Redistributions in binary form must reproduce at minimum a + * disclaimer similar to the Disclaimer below and any redistribution + * must be conditioned upon including a substantially similar + * Disclaimer requirement for further binary redistribution. + * 4. Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote + * product derived from this software without specific prior written + * permission. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, + * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE + * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. + * + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/hal/main/linux/ah_osdep.h#1 $ + */ +#ifndef _ATH_AH_OSDEP_H_ +#define _ATH_AH_OSDEP_H_ +/* + * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. + */ + +/* + * Starting with 2.6.4 the kernel supports a configuration option + * to pass parameters in registers. If this is enabled we must + * mark all function interfaces in+out of the HAL to pass parameters + * on the stack as this is the convention used internally (for + * maximum portability). + * + * XXX A lot of functions have __ahdecl in their definition but not declaration + * So compile breaks. + * Since This is only an issue for i386 which has regparam enabled, instead of + * changing the vanilla FC3 kernel, for now, remove the regparm + * disabling. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* CONFIG_REGPARM has been removed from 2.6.20 onwards. + * Since this is relevant only for i386 architectures, changing check to + * i386. + */ + +#ifdef __adf_i386__ +#define __ahdecl __attribute__((regparm(0))) +#else +#define __ahdecl +#endif +#ifndef adf_os_packed +#define adf_os_packed __attribute__((__packed__)) +#endif +#ifdef __FreeBSD__ +/* + * When building the HAL proper we use no GPL-contaminated include + * files and must define these types ourself. Beware of these being + * mismatched against the contents of + */ +/* NB: arm defaults to unsigned so be explicit */ +/* cometothis later when seperating os deps */ +typedef __va_list va_list; +// typedef void *va_list; +#define va_start(ap, last) \ + __builtin_stdarg_start((ap), (last)) + +#define va_end(ap) \ + __builtin_va_end(ap) +#endif + +/* + * Linux/BSD gcc compatibility shims. + */ +#ifdef TODO //freebsd has definition +#define __printflike(_a,_b) \ + __attribute__ ((__format__ (__printf__, _a, _b))) +#endif +#ifndef __va_list +#define __va_list va_list +#endif +#ifdef TODO //freebsd has definition +#define OS_INLINE __inline +#endif + +typedef void* HAL_SOFTC; +typedef a_int32_t HAL_BUS_TAG; +typedef void* HAL_BUS_HANDLE; +typedef a_uint32_t HAL_BUS_ADDR; /* XXX architecture dependent */ + +/* + * Delay n microseconds. + */ +extern void __ahdecl ath_hal_delay(a_int32_t); +#define OS_DELAY(_n) ath_hal_delay(_n) + +extern void* __ahdecl ath_hal_ioremap(a_uint32_t addr, a_uint32_t len); +#define OS_REMAP(_addr, _len) ath_hal_ioremap(_addr, _len) + +#define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n)) +extern void __ahdecl ath_hal_memzero(void *, size_t); +#define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n) +extern void * __ahdecl ath_hal_memcpy(void *, void *, size_t); + +#ifndef abs +#define abs(_a) __builtin_abs(_a) +#endif + +struct ath_hal; +extern a_uint32_t __ahdecl ath_hal_getuptime(struct ath_hal *); +#define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah) + +/* + * Byte order/swapping support. + */ +#define AH_LITTLE_ENDIAN 1234 +#define AH_BIG_ENDIAN 4321 + +#if AH_BYTE_ORDER == AH_BIG_ENDIAN +/* + * This could be optimized but since we only use it for + * a few registers there's little reason to do so. + */ +#ifndef __bswap32 +static inline a_uint32_t +__bswap32(a_uint32_t _x) +{ + return ((a_uint32_t)( + (((const a_uint8_t *)(&_x))[0] ) | + (((const a_uint8_t *)(&_x))[1]<< 8) | + (((const a_uint8_t *)(&_x))[2]<<16) | + (((const a_uint8_t *)(&_x))[3]<<24)) + ); +} +#endif +#ifndef __bswap16 +#define __bswap16(_x) ( (a_uint16_t)( (((const a_uint8_t *)(&_x))[0] ) |\ + ( ( (const a_uint8_t *)( &_x ) )[1]<< 8) ) ) +#endif +#else +#ifndef __bswap32 +#define __bswap32(_x) (_x) +#endif +#ifndef __bswap16 +#define __bswap16(_x) (_x) +#endif +#endif + +#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write_target(_ah, _reg, _val) +#define OS_REG_READ(_ah, _reg) ath_hal_reg_read_target(_ah, _reg) + +extern void __ahdecl ath_hal_reg_write_target(struct ath_hal *ah, + a_uint32_t reg, a_uint32_t val); +extern a_uint32_t __ahdecl ath_hal_reg_read_target(struct ath_hal *ah, a_uint32_t reg); + +#define AH_USE_EEPROM 0x00000001 +extern struct ath_hal *_ath_hal_attach_tgt( a_uint32_t,HAL_SOFTC,adf_os_device_t,HAL_BUS_HANDLE, + a_uint32_t flags, void* status); +extern void ath_hal_detach(struct ath_hal *); +#endif /* _ATH_AH_OSDEP_H_ */ diff --git a/target_firmware/wlan/ar5416.h b/target_firmware/wlan/ar5416.h new file mode 100755 index 0000000..9fb0df8 --- /dev/null +++ b/target_firmware/wlan/ar5416.h @@ -0,0 +1,83 @@ +#include + +extern HAL_STATUS ar5416GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE, + a_uint32_t, a_uint32_t *); +extern const HAL_RATE_TABLE *ar5416GetRateTable(struct ath_hal *, a_uint32_t mode); +extern HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah); +extern HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *); +extern HAL_INT ar5416GetInterrupts(struct ath_hal *ah); +extern HAL_INT ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints); +extern a_uint32_t ar5416Get11nExtBusy(struct ath_hal *ah); +extern HAL_HT_RXCLEAR ar5416Get11nRxClear(struct ath_hal *ah); +extern void ar5416Set11nRxClear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); +extern a_uint32_t ar5416GetTsf32(struct ath_hal *ah); +extern u_int64_t ar5416GetTsf64(struct ath_hal *ah); +extern void ar5416ResetTsf(struct ath_hal *ah); +extern void ar5416Detach(struct ath_hal *ah); + +typedef enum Ar5416_Rates { + rate6mb, rate9mb, rate12mb, rate18mb, + rate24mb, rate36mb, rate48mb, rate54mb, + rate1l, rate2l, rate2s, rate5_5l, + rate5_5s, rate11l, rate11s, rateXr, + rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, + rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, + rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, + rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, + rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, + Ar5416RateSize +} AR5416_RATES; + +#ifdef MAGPIE_MERLIN +#define AR_SREV_HOWL(ah) ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_VERSION_HOWL) +#define IS_5416_HOWL AR_SREV_HOWL + +#define AR5416_RATES_OFDM_OFFSET 0 +#define AR5416_RATES_CCK_OFFSET 8 +#define AR5416_RATES_HT20_OFFSET 16 +#define AR5416_RATES_HT40_OFFSET 24 + +/* Delta from which to start power to pdadc table */ + +#define AR5416_PWR_TABLE_OFFSET -5 +#define AR5416_LEGACY_CHAINMASK 1 +#define AR5416_1_CHAINMASK 1 +#define AR5416_2LOHI_CHAINMASK 5 +#define AR5416_2LOMID_CHAINMASK 3 +#define AR5416_3_CHAINMASK 7 + +#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) + +#else // For Owl + +#endif // MAGPIE_MERLIN + +#define AR5416_LEGACY_CHAINMASK 1 + +#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) + +/* + * Various fifo fill before Tx start, in 64-byte units + * i.e. put the frame in the air while still DMAing + */ +#define MIN_TX_FIFO_THRESHOLD 0x1 +#define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1) +#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD + +struct ath_hal_5416 +{ + struct ath_hal_private ah_priv; /* base class */ + a_uint16_t ah_antennaSwitchSwap; /* Controls mapping of OID request */ + a_uint32_t ah_maskReg; /* copy of AR_IMR */ + + a_uint32_t ah_slottime; /* user-specified slot time */ + a_int16_t ah_txPowerIndexOffset; + + a_uint32_t ah_intrTxqs; + void *ah_cal_mem; + a_uint16_t ah_ratesArray[Ar5416RateSize]; +#ifdef MAGPIE_MERLIN + /* HT CWM state */ + HAL_HT_CWM ah_htcwm; +#endif +}; diff --git a/target_firmware/wlan/ar5416Phy.c b/target_firmware/wlan/ar5416Phy.c new file mode 100755 index 0000000..29408dd --- /dev/null +++ b/target_firmware/wlan/ar5416Phy.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2000-2002 Atheros Communications, Inc., All Rights Reserved + * + */ + +#ident "$Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/ratectrl11n/ar5416Phy.c#5 $" + +#include "ratectrl.h" +#include "ratectrl11n.h" + +#define SHORT_PRE 1 +#define LONG_PRE 0 + +#define WLAN_PHY_HT_20_SS WLAN_RC_PHY_HT_20_SS +#define WLAN_PHY_HT_20_SS_HGI WLAN_RC_PHY_HT_20_SS_HGI +#define WLAN_PHY_HT_20_DS WLAN_RC_PHY_HT_20_DS +#define WLAN_PHY_HT_20_DS_HGI WLAN_RC_PHY_HT_20_DS_HGI +#define WLAN_PHY_HT_40_SS WLAN_RC_PHY_HT_40_SS +#define WLAN_PHY_HT_40_DS WLAN_RC_PHY_HT_40_DS +#define WLAN_PHY_HT_40_DS_HGI WLAN_RC_PHY_HT_40_DS_HGI +#define WLAN_PHY_HT_40_SS_HGI WLAN_RC_PHY_HT_40_SS_HGI + + +/* TRUE_ALL_11N - valid for 20/40/Legacy, TRUE - Legacy only, TRUE_20 - HT 20 only, TRUE_40 - HT 40 only */ +/* 4ms frame limit not used for NG mode. The values filled for HT are the 64K max aggregate limit */ + +#ifndef MAGPIE_MERLIN // K2 + +RATE_TABLE_11N ar5416_11ngRateTable = { + + 54, /* number of rates - should match the no. of rows below */ + 100, /* probe interval */ + 50, /* rssi reduce interval */ + WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ + {/* Multiple Single */ + /* stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/ + /* valid valid Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ + /* 1 Mb [0] */ { TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 1000, 900, 0x1b, 0x00, 2, 0, 0, 1, 0, 0, 0, 0, 3, 7, 0, TRUE }, + /* 2 Mb [1] */ { TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 2000, 1900, 0x1a, 0x04, 4, 1, 1, 1, 1, 1, 1, 1, 3, 7, 0, FALSE}, + /* 5.5 Mb [2] */ { TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 5500, 4900, 0x19, 0x04, 11, 2, 2, 2, 2, 2, 2, 2, 3, 7, 0, FALSE}, + /* 11 Mb [3] */ { TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 11000, 8100, 0x18, 0x04, 22, 3, 3, 2, 3, 3, 3, 3, 3, 7, 0, TRUE}, + /* 6 Mb [4] */ { FALSE, FALSE, WLAN_PHY_OFDM, 6000, 5400, 0x0b, 0x00, 12, 4, 2, 1, 4, 4, 4, 4, 3, 7, 0, FALSE}, + /* 9 Mb [5] */ { FALSE, FALSE, WLAN_PHY_OFDM, 9000, 7800, 0x0f, 0x00, 18, 4, 3, 1, 5, 5, 5, 5, 3, 7, 0, FALSE}, + /* 12 Mb [6] */ { TRUE, TRUE, WLAN_PHY_OFDM, 12000, 10100, 0x0a, 0x00, 24, 6, 4, 1, 6, 6, 6, 6, 3, 7, 0, FALSE}, + /* 18 Mb [7] */ { TRUE, TRUE, WLAN_PHY_OFDM, 18000, 14100, 0x0e, 0x00, 36, 6, 6, 2, 7, 7, 7, 7, 3, 7, 0, FALSE}, + /* 24 Mb [8] */ { TRUE, TRUE, WLAN_PHY_OFDM, 24000, 17700, 0x09, 0x00, 48, 8, 10, 3, 8, 8, 8, 8, 3, 7, 0, TRUE}, + /* 36 Mb [9] */ { TRUE, TRUE, WLAN_PHY_OFDM, 36000, 23700, 0x0d, 0x00, 72, 8, 14, 3, 9, 9, 9, 9, 3, 7, 0, FALSE}, + /* 48 Mb [10] */ { TRUE, TRUE, WLAN_PHY_OFDM, 48000, 27400, 0x08, 0x00, 96, 8, 20, 3, 10, 10, 10, 10, 1, 1, 0, FALSE}, + /* 54 Mb [11] */ { TRUE, TRUE, WLAN_PHY_OFDM, 54000, 30900, 0x0c, 0x00, 108, 8, 23, 3, 11, 11, 11, 11, 1, 1, 0, TRUE}, + /* 6.5 Mb [12] */ { FALSE, FALSE, WLAN_PHY_HT_20_SS,6500, 6400, 0x80, 0x00, 0, 4, 2, 3, 12, 33, 12, 33, 3, 7, 3216, TRUE}, + /* 13 Mb [13] */ { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,13000, 12700, 0x81, 0x00, 1, 6, 4, 3, 13, 34, 13, 34, 3, 7, 6434, TRUE}, + /* 19.5 Mb [14] */ { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,19500, 18800, 0x82, 0x00, 2, 6, 6, 3, 14, 35, 14, 35, 3, 7, 9650, FALSE}, + /* 26 Mb [15] */ { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,26000, 25000, 0x83, 0x00, 3, 8, 10, 3, 15, 36, 15, 36, 3, 7, 12868, FALSE}, + /* 39 Mb [16] */ { TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,39000, 36700, 0x84, 0x00, 4, 8, 14, 3, 16, 37, 17, 38, 3, 7, 19304, TRUE}, + /* 43.3 Mb [17] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS_HGI,43300, 39200, 0x84, 0x00, 4, 8, 14, 3, 16, 37, 17, 38, 3, 7, 21460, TRUE}, + /* 52 Mb [18] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS,52000, 48100, 0x85, 0x00, 5, 8, 20, 3, 18, 39, 19, 40, 1, 1, 25740, FALSE}, + /* 57.8 Mb [19] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS_HGI,57800, 52300, 0x85, 0x00, 5, 8, 20, 3, 18, 39, 19, 40, 1, 1, 28620, FALSE}, + /* 58.5 Mb [20] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS,58500, 53500, 0x86, 0x00, 6, 8, 23, 3, 20, 41, 21, 42, 1, 1, 28956, FALSE}, + /* 65 Mb [21] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS_HGI,65000, 58800, 0x86, 0x00, 6, 8, 23, 3, 20, 41, 21, 42, 1, 1, 32200, FALSE}, + /* 65 Mb [22] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS,65000, 58801, 0x87, 0x00, 7, 8, 25, 3, 22, 43, 23, 44, 1, 1, 32200, TRUE}, + /* 72.2 Mb [23] */ { FALSE, TRUE_20, WLAN_PHY_HT_20_SS_HGI,72200, 65400, 0x87, 0x00, 7, 8, 25, 3, 22, 43, 23, 44, 1, 1, 35750, TRUE}, + /* 52 Mb [24] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS,52000, 48100, 0x8b, 0x00, 11, 8, 10, 3, 24, 45, 24, 45, 3, 7, 25736, FALSE}, + /* 78 Mb [25] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS,78000, 69500, 0x8c, 0x00, 12, 8, 14, 3, 25, 46, 26, 47, 3, 7, 38600, TRUE}, + /* 86.7 Mb [26] */ { FALSE, FALSE, WLAN_PHY_HT_20_DS_HGI,86700, 78400, 0x8c, 0x00, 12, 8, 14, 3, 25, 46, 26, 47, 3, 7, 42890, TRUE}, + /* 104 Mb [27] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS,104000,89500, 0x8d, 0x00, 13, 8, 20, 3, 27, 48, 28, 49, 3, 5, 51472, FALSE}, + /* 115.6Mb [28] */ { FALSE, FALSE, WLAN_PHY_HT_20_DS_HGI,115600,103900,0x8d, 0x00, 13, 8, 20, 3, 27, 48, 28, 49, 3, 5, 57190, FALSE}, + /* 117 Mb [29] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS,117000,105200,0x8e, 0x00, 14, 8, 23, 3, 29, 50, 30, 51, 3, 5, 57890, FALSE}, + /* 130 Mb [30] */ { FALSE, FALSE, WLAN_PHY_HT_20_DS_HGI,130000,116090,0x8e, 0x00, 14, 8, 23, 3, 29, 50, 30, 51, 3, 5, 64320, FALSE}, + /* 130 Mb [31] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS,130000,116100,0x8f, 0x00, 15, 8, 25, 3, 31, 52, 32, 53, 3, 5, 64320, TRUE}, + /* 144.4Mb [32] */ { TRUE_20, FALSE, WLAN_PHY_HT_20_DS_HGI,144400,128100,0x8f, 0x00, 15, 8, 25, 3, 31, 52, 32, 53, 3, 5, 71490, TRUE}, + /* 13.5 Mb [33] */ { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,13500, 13200, 0x80, 0x00, 0, 8, 2, 3, 12, 33, 33, 33, 3, 7, 6684, TRUE}, + /* 27.0 Mb [34] */ { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,27500, 25900, 0x81, 0x00, 1, 8, 4, 3, 13, 34, 34, 34, 3, 7, 13368, TRUE}, + /* 40.5 Mb [35] */ { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,40500, 38600, 0x82, 0x00, 2, 8, 6, 3, 14, 35, 35, 35, 3, 7, 20052, FALSE}, + /* 54 Mb [36] */ { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,54000, 49800, 0x83, 0x00, 3, 8, 10, 3, 15, 36, 36, 36, 3, 7, 26738, FALSE}, + /* 81 Mb [37] */ { TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,81500, 72200, 0x84, 0x00, 4, 8, 14, 3, 16, 37, 38, 38, 3, 7, 40104, TRUE}, + /* 90 Mb [38] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI,90000, 81500, 0x84, 0x00, 4, 8, 14, 3, 16, 37, 38, 38, 3, 7, 44590, TRUE}, + /* 108 Mb [39] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS,108000,92900, 0x85, 0x00, 5, 8, 20, 3, 18, 39, 40, 40, 1, 1, 53476, FALSE}, + /* 120 Mb [40] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI,120000,102100,0x85, 0x00, 5, 8, 20, 3, 18, 39, 40, 40, 1, 1, 59450, FALSE}, + /* 121.5Mb [41] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS,121500,102700,0x86, 0x00, 6, 8, 23, 3, 20, 41, 42, 42, 1, 1, 60156, FALSE}, + /* 135 Mb [42] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI,135000,111900,0x86, 0x00, 6, 8, 23, 3, 20, 41, 42, 42, 1, 1, 66840, FALSE}, + /* 135 Mb [43] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS,135000,112000,0x87, 0x00, 7, 8, 25, 3, 22, 43, 44, 44, 1, 1, 66840, TRUE}, + /* 150 Mb [44] */ { FALSE, TRUE_40, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 22, 43, 44, 44, 1, 1, 74200, TRUE}, + /* 108 Mb [45] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,108000,92500, 0x8b, 0x00, 11, 8, 10, 3, 24, 45, 45, 45, 3, 7, 53440, FALSE}, + /* 162 Mb [46] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,162000,130300,0x8c, 0x00, 12, 8, 14, 3, 25, 46, 47, 47, 3, 7, 80160, TRUE}, + /* 180 Mb [47] */ { FALSE, FALSE, WLAN_PHY_HT_40_DS_HGI,180000,156900,0x8c, 0x00, 12, 8, 14, 3, 25, 46, 47, 47, 3, 7, 89090, TRUE}, + /* 216 Mb [48] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,216000,162800,0x8d, 0x00, 13, 8, 20, 3, 27, 48, 49, 49, 3, 5, 106880, FALSE}, + /* 240 Mb [49] */ { FALSE, FALSE, WLAN_PHY_HT_40_DS_HGI,240000,178000,0x8d, 0x00, 13, 8, 20, 3, 27, 48, 49, 49, 3, 5, 118790, FALSE}, + /* 243 Mb [50] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,243000,178200,0x8e, 0x00, 14, 8, 23, 3, 29, 50, 51, 51, 3, 5, 120240, FALSE}, + /* 270 Mb [51] */ { FALSE, FALSE, WLAN_PHY_HT_40_DS_HGI,270000,192050,0x8e, 0x00, 14, 8, 23, 3, 29, 50, 51, 51, 3, 5, 133600, FALSE}, + /* 270 Mb [52] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS,270000,192100,0x8f, 0x00, 15, 8, 23, 3, 31, 52, 53, 53, 3, 5, 133600, FALSE}, + /* 300 Mb [53] */ { TRUE_40, FALSE, WLAN_PHY_HT_40_DS_HGI,300000,207000,0x8f, 0x00, 15, 8, 25, 3, 31, 52, 53, 53, 3, 5, 148400, TRUE}, + /* Multiple Single */ + /* stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/ + /* valid valid Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ + }, +}; + +#else + +RATE_TABLE_11N ar5416_11ngRateTable = { + + 46, /* number of rates - should match the no. of rows below */ + 50, /* probe interval */ + 50, /* rssi reduce interval */ + WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ + {/* Multiple Single Single */ + /* stream stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/ + /* valid valid STBC Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ + /* 1 Mb [0] */ { TRUE_ALL_11N, TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 1000, 900, 0x1b, 0x00, 2, 0, 0, 1, 0, 0, 0, 0, 3, 7, 0, TRUE }, + /* 2 Mb [1] */ { TRUE_ALL_11N, TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 2000, 1900, 0x1a, 0x04, 4, 1, 1, 1, 1, 1, 1, 1, 3, 7, 0, FALSE}, + /* 5.5 Mb [2] */ { TRUE_ALL_11N, TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 5500, 4900, 0x19, 0x04, 11, 2, 2, 2, 2, 2, 2, 2, 3, 7, 0, FALSE}, + /* 11 Mb [3] */ { TRUE_ALL_11N, TRUE_ALL_11N, TRUE_ALL_11N, WLAN_PHY_CCK, 11000, 8100, 0x18, 0x04, 22, 3, 3, 2, 3, 3, 3, 3, 3, 7, 0, TRUE}, + /* 6 Mb [4] */ { FALSE, FALSE, FALSE, WLAN_PHY_OFDM, 6000, 5400, 0x0b, 0x00, 12, 4, 2, 1, 4, 4, 4, 4, 3, 7, 0, FALSE}, + /* 9 Mb [5] */ { FALSE, FALSE, FALSE, WLAN_PHY_OFDM, 9000, 7800, 0x0f, 0x00, 18, 4, 3, 1, 5, 5, 5, 5, 3, 7, 0, FALSE}, + /* 12 Mb [6] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 12000, 10100, 0x0a, 0x00, 24, 6, 4, 1, 6, 6, 6, 6, 3, 7, 0, FALSE}, + /* 18 Mb [7] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 18000, 14100, 0x0e, 0x00, 36, 6, 6, 2, 7, 7, 7, 7, 3, 7, 0, FALSE}, + /* 24 Mb [8] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 24000, 17700, 0x09, 0x00, 48, 8, 10, 3, 8, 8, 8, 8, 3, 7, 0, TRUE}, + /* 36 Mb [9] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 36000, 23700, 0x0d, 0x00, 72, 8, 14, 3, 9, 9, 9, 9, 3, 7, 0, FALSE}, + /* 48 Mb [10] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 48000, 27400, 0x08, 0x00, 96, 8, 20, 3, 10, 10, 10, 10, 1, 1, 0, FALSE}, + /* 54 Mb [11] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 54000, 30900, 0x0c, 0x00, 108, 8, 23, 3, 11, 11, 11, 11, 1, 1, 0, TRUE}, + /* 6.5 Mb [12] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_SS,6500, 6400, 0x80, 0x00, 0, 4, 2, 3, 12, 28, 12, 28, 3, 7, 3216, TRUE}, + /* 13 Mb [13] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,13000, 12700, 0x81, 0x00, 1, 6, 4, 3, 13, 29, 13, 29, 3, 7, 6434, TRUE}, + /* 19.5 Mb [14] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,19500, 18800, 0x82, 0x00, 2, 6, 6, 3, 14, 30, 14, 30, 3, 7, 9650, FALSE}, + /* 26 Mb [15] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,26000, 25000, 0x83, 0x00, 3, 8, 10, 3, 15, 31, 15, 31, 3, 7, 12868, FALSE}, + /* 39 Mb [16] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,39000, 36700, 0x84, 0x00, 4, 8, 14, 3, 16, 32, 16, 32, 3, 7, 19304, TRUE}, + /* 52 Mb [17] */ { FALSE, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,52000, 48100, 0x85, 0x00, 5, 8, 20, 3, 17, 33, 17, 33, 1, 1, 25740, FALSE}, + /* 58.5 Mb [18] */ { FALSE, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,58500, 53500, 0x86, 0x00, 6, 8, 23, 3, 18, 34, 18, 34, 1, 1, 28956, FALSE}, + /* 65 Mb [19] */ { FALSE, TRUE_20, FALSE, WLAN_PHY_HT_20_SS,65000, 59000, 0x87, 0x00, 7, 8, 25, 3, 19, 35, 19, 36, 1, 1, 32180, TRUE}, + /* 13 Mb [20] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,13000, 12700, 0x88, 0x00, 8, 4, 2, 3, 20, 37, 20, 37, 3, 7, 6430, TRUE}, + /* 26 Mb [21] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,26000, 24800, 0x89, 0x00, 9, 6, 4, 3, 21, 38, 21, 38, 3, 7, 12860, FALSE}, + /* 39 Mb [22] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,39000, 36600, 0x8a, 0x00, 10, 6, 6, 3, 22, 39, 22, 39, 3, 7, 19300, TRUE}, + /* 52 Mb [23] */ { TRUE_20, FALSE, FALSE, WLAN_PHY_HT_20_DS,52000, 48100, 0x8b, 0x00, 11, 8, 10, 3, 23, 40, 23, 40, 3, 7, 25736, FALSE}, + /* 78 Mb [24] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,78000, 69500, 0x8c, 0x00, 12, 8, 14, 3, 24, 41, 24, 41, 3, 7, 38600, TRUE}, + /* 104 Mb [25] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,104000,89500, 0x8d, 0x00, 13, 8, 20, 3, 25, 42, 25, 42, 3, 5, 51472, FALSE}, + /* 117 Mb [26] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,117000,98900, 0x8e, 0x00, 14, 8, 23, 3, 26, 43, 26, 44, 3, 5, 57890, FALSE}, + /* 130 Mb [27] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,130000,108300,0x8f, 0x00, 15, 8, 25, 3, 27, 44, 27, 45, 3, 5, 64320, TRUE}, + /* 13.5 Mb [28] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,13500, 13200, 0x80, 0x00, 0, 8, 2, 3, 12, 28, 28, 28, 3, 7, 6684, TRUE}, + /* 27.0 Mb [29] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,27500, 25900, 0x81, 0x00, 1, 8, 4, 3, 13, 29, 29, 29, 3, 7, 13368, TRUE}, + /* 40.5 Mb [30] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,40500, 38600, 0x82, 0x00, 2, 8, 6, 3, 14, 30, 30, 30, 3, 7, 20052, FALSE}, + /* 54 Mb [31] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,54000, 49800, 0x83, 0x00, 3, 8, 10, 3, 15, 31, 31, 31, 3, 7, 26738, FALSE}, + /* 81 Mb [32] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,81500, 72200, 0x84, 0x00, 4, 8, 14, 3, 16, 32, 32, 32, 3, 7, 40104, TRUE}, + /* 108 Mb [33] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,108000,92900, 0x85, 0x00, 5, 8, 20, 3, 17, 33, 33, 33, 1, 1, 53476, FALSE}, + /* 121.5Mb [34] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,121500,102700,0x86, 0x00, 6, 8, 23, 3, 18, 34, 34, 34, 1, 1, 60156, FALSE}, + /* 135 Mb [35] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS,135000,112000,0x87, 0x00, 7, 8, 25, 3, 19, 35, 36, 36, 1, 1, 66840, TRUE}, + /* 150 Mb [36] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 19, 35, 36, 36, 1, 1, 74200, TRUE}, + /* 27 Mb [37] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,27000, 25800, 0x88, 0x00, 8, 8, 2, 3, 20, 37, 37, 37, 3, 7, 13360, TRUE}, + /* 54 Mb [38] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,54000, 49800, 0x89, 0x00, 9, 8, 4, 3, 21, 38, 38, 38, 3, 7, 26720, FALSE}, + /* 81 Mb [39] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,81000, 71900, 0x8a, 0x00, 10, 8, 6, 3, 22, 39, 39, 39, 3, 7, 40080, TRUE}, + /* 108 Mb [40] */ { TRUE_40, FALSE, FALSE, WLAN_PHY_HT_40_DS,108000,92500, 0x8b, 0x00, 11, 8, 10, 3, 23, 40, 40, 40, 3, 7, 53440, FALSE}, + /* 162 Mb [41] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,162000,130300,0x8c, 0x00, 12, 8, 14, 3, 24, 41, 41, 41, 3, 7, 80160, TRUE}, + /* 216 Mb [42] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,216000,162800,0x8d, 0x00, 13, 8, 20, 3, 25, 42, 42, 42, 3, 5, 106880, FALSE}, + /* 243 Mb [43] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,243000,178200,0x8e, 0x00, 14, 8, 23, 3, 26, 43, 43, 43, 3, 5, 120240, FALSE}, + /* 270 Mb [44] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,270000,192100,0x8f, 0x00, 15, 8, 23, 3, 27, 44, 45, 45, 3, 5, 133600, FALSE}, + /* 300 Mb [45] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS_HGI,300000,207000,0x8f, 0x00, 15, 8, 25, 3, 27, 44, 45, 45, 3, 5, 148400, TRUE}, + /* Multiple Single */ + /* stream stream short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for*/ + /* valid valid Kbps uKbps RC Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ + }, +}; + +#ifdef ATH_SUPPORT_A_MODE +//static RATE_TABLE_11N ar5416_11naRateTable = { +RATE_TABLE_11N ar5416_11naRateTable = { + + 42, /* number of rates */ + 50, /* probe interval */ + 50, /* rssi reduce interval */ + WLAN_RC_HT_FLAG, /* Phy rates allowed initially */ + {/* Multiple Single Single*/ + /* stream stream stream rate short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for */ + /* valid valid STBC Kbps uKbps Code Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ + /* 6 Mb [0] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 6000, 5400, 0x0b, 0x00, 12, 0, 2, 1, 0, 0, 0, 0, 3, 7, 0, TRUE}, + /* 9 Mb [1] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 9000, 7800, 0x0f, 0x00, 18, 0, 3, 1, 1, 1, 1, 1, 3, 7, 0, FALSE}, + /* 12 Mb [2] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 12000, 10000, 0x0a, 0x00, 24, 2, 4, 2, 2, 2, 2, 2, 3, 7, 0, TRUE}, + /* 18 Mb [3] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 18000, 13900, 0x0e, 0x00, 36, 2, 6, 2, 3, 3, 3, 3, 3, 7, 0, FALSE}, + /* 24 Mb [4] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 24000, 17300, 0x09, 0x00, 48, 4, 10, 3, 4, 4, 4, 4, 3, 7, 0, TRUE}, + /* 36 Mb [5] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 36000, 23000, 0x0d, 0x00, 72, 4, 14, 3, 5, 5, 5, 5, 3, 7, 0, FALSE}, + /* 48 Mb [6] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 48000, 27400, 0x08, 0x00, 96, 4, 20, 3, 6, 6, 6, 6, 1, 1, 0, FALSE}, + /* 54 Mb [7] */ { TRUE, TRUE, TRUE, WLAN_PHY_OFDM, 54000, 29300, 0x0c, 0x00, 108, 4, 23, 3, 7, 7, 7, 7, 1, 1, 0, TRUE}, + /* 6.5 Mb [8] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS, 6500, 6400, 0x80, 0x00, 0, 0, 2, 3, 8, 24, 8, 24, 3, 7, 3216, TRUE}, + /* 13 Mb [9] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,13000, 12700, 0x81, 0x00, 1, 2, 4, 3, 9, 25, 9, 25, 3, 7, 6434, TRUE}, + /* 19.5 Mb [10] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,19500, 18800, 0x82, 0x00, 2, 2, 6, 3, 10, 26, 10, 26, 3, 7, 9650, FALSE}, + /* 26 Mb [11] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,26000, 25000, 0x83, 0x00, 3, 4, 10, 3, 11, 27, 11, 27, 3, 7, 12868, FALSE}, + /* 39 Mb [12] */ { TRUE_20, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,39000, 36700, 0x84, 0x00, 4, 4, 14, 3, 12, 28, 12, 28, 3, 7, 19304, TRUE}, + /* 52 Mb [13] */ { FALSE, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,52000, 48100, 0x85, 0x00, 5, 4, 20, 3, 13, 29, 13, 29, 1, 1, 25740, FALSE}, + /* 58.5 Mb [14] */ { FALSE, TRUE_20, TRUE_20, WLAN_PHY_HT_20_SS,58500, 53500, 0x86, 0x00, 6, 4, 23, 3, 14, 30, 14, 30, 1, 1, 28956, FALSE}, + /* 65 Mb [15] */ { FALSE, TRUE_20, FALSE, WLAN_PHY_HT_20_SS,65000, 59000, 0x87, 0x00, 7, 4, 25, 3, 15, 31, 15, 32, 1, 1, 32180, TRUE}, + /* 13 Mb [16] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,13000, 12700, 0x88, 0x00, 8, 0, 2, 3, 16, 33, 16, 33, 3, 7, 6430, TRUE}, + /* 26 Mb [17] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,26000, 24800, 0x89, 0x00, 9, 2, 4, 3, 17, 34, 17, 34, 3, 7, 12860, FALSE}, + /* 39 Mb [18] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_20_DS,39000, 36600, 0x8a, 0x00, 10, 2, 6, 3, 18, 35, 18, 35, 3, 7, 19300, TRUE}, + /* 52 Mb [19] */ { TRUE_20, FALSE, FALSE, WLAN_PHY_HT_20_DS,52000, 48100, 0x8b, 0x00, 11, 4, 10, 3, 19, 36, 19, 36, 3, 7, 25736, FALSE}, + /* 78 Mb [20] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,78000, 69500, 0x8c, 0x00, 12, 4, 14, 3, 20, 37, 20, 37, 3, 7, 38600, TRUE}, + /* 104 Mb [21] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,104000,89500, 0x8d, 0x00, 13, 4, 20, 3, 21, 38, 21, 38, 3, 5, 51472, FALSE}, + /* 117 Mb [22] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,117000,98900, 0x8e, 0x00, 14, 4, 23, 3, 22, 39, 22, 39, 3, 5, 57890, FALSE}, + /* 130 Mb [23] */ { TRUE_20, FALSE, TRUE_20, WLAN_PHY_HT_20_DS,130000,108300,0x8f, 0x00, 15, 4, 25, 3, 23, 40, 23, 41, 3, 5, 64320, TRUE}, + /* 13.5 Mb [24] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,13500, 13200, 0x80, 0x00, 0, 0, 2, 3, 8, 24, 24, 24, 3, 7, 6684, TRUE}, + /* 27.0 Mb [25] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,27500, 25900, 0x81, 0x00, 1, 2, 4, 3, 9, 25, 25, 25, 3, 7, 13368, TRUE}, + /* 40.5 Mb [26] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,40500, 38600, 0x82, 0x00, 2, 2, 6, 3, 10, 26, 26, 26, 3, 7, 20052, FALSE}, + /* 54 Mb [27] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,54000, 49800, 0x83, 0x00, 3, 4, 10, 3, 11, 27, 27, 27, 3, 7, 26738, FALSE}, + /* 81 Mb [28] */ { TRUE_40, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,81500, 72200, 0x84, 0x00, 4, 4, 14, 3, 12, 28, 28, 28, 3, 7, 40104, TRUE}, + /* 108 Mb [29] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,108000,92900, 0x85, 0x00, 5, 4, 20, 3, 13, 29, 29, 29, 1, 1, 53476, FALSE}, + /* 121.5Mb [30] */ { FALSE, TRUE_40, TRUE_40, WLAN_PHY_HT_40_SS,121500,102700,0x86, 0x00, 6, 4, 23, 3, 14, 30, 30, 30, 1, 1, 60156, FALSE}, + /* 135 Mb [31] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS,135000,112000,0x87, 0x00, 7, 4, 25, 3, 15, 31, 32, 32, 1, 1, 66840, TRUE}, + /* 150 Mb [32] */ { FALSE, TRUE_40, FALSE, WLAN_PHY_HT_40_SS_HGI,150000,122000,0x87, 0x00, 7, 8, 25, 3, 15, 31, 32, 32, 1, 1, 65535, TRUE}, + /* 27 Mb [33] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,27000, 25800, 0x88, 0x00, 8, 0, 2, 3, 16, 33, 33, 33, 3, 7, 13360, TRUE}, + /* 54 Mb [34] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,54000, 49800, 0x89, 0x00, 9, 2, 4, 3, 17, 34, 34, 34, 3, 7, 26720, FALSE}, + /* 81 Mb [35] */ { FALSE, FALSE, FALSE, WLAN_PHY_HT_40_DS,81000, 71900, 0x8a, 0x00, 10, 2, 6, 3, 18, 35, 35, 35, 3, 7, 40080, TRUE}, + /* 108 Mb [36] */ { TRUE_40, FALSE, FALSE, WLAN_PHY_HT_40_DS,108000,92500, 0x8b, 0x00, 11, 4, 10, 3, 19, 36, 36, 36, 3, 7, 53440, FALSE}, + /* 162 Mb [37] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,162000,130300,0x8c, 0x00, 12, 4, 14, 3, 20, 37, 37, 37, 3, 7, 80160, TRUE}, + /* 216 Mb [38] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,216000,162800,0x8d, 0x00, 13, 4, 20, 3, 21, 38, 38, 38, 3, 5, 106880, FALSE}, + /* 243 Mb [39] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,243000,178200,0x8e, 0x00, 14, 4, 23, 3, 22, 39, 39, 39, 3, 5, 120240, FALSE}, + /* 270 Mb [40] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS,270000,192100,0x8f, 0x00, 15, 4, 25, 3, 23, 40, 41, 41, 3, 5, 133600, TRUE}, + /* 300 Mb [41] */ { TRUE_40, FALSE, TRUE_40, WLAN_PHY_HT_40_DS_HGI,300000,207000,0x8f, 0x00, 15, 4, 25, 3, 23, 40, 41, 41, 3, 5, 148400, TRUE}, + /* stream stream rate short dot11 ctrl RssiAck RssiAck Base CW40 SGI Ht tx chain 4ms tx valid for */ + /* valid valid Kbps uKbps Code Preamble Rate Rate ValidMin DeltaMin Idx Idx Idx Idx mask limit UAPSD */ + }, +}; +#endif //ATH_SUPPORT_A_MODE + +#endif //#ifdef MAGPIE_MERLIN // MAGPIE_MERLIN + +void +ar5416AttachRateTables(struct atheros_softc *sc) +{ + sc->hwRateTable[WIRELESS_MODE_11NG] = &ar5416_11ngRateTable; +#ifdef ATH_SUPPORT_A_MODE + sc->hwRateTable[WIRELESS_MODE_11NA] = &ar5416_11naRateTable; +#endif +} diff --git a/target_firmware/wlan/ar5416_hw.c b/target_firmware/wlan/ar5416_hw.c new file mode 100644 index 0000000..3045ab6 --- /dev/null +++ b/target_firmware/wlan/ar5416_hw.c @@ -0,0 +1,1114 @@ +#include "opt_ah.h" +#include "ah.h" +#include "ah_internal.h" +#include "ar5416.h" +#include "ar5416reg.h" +#include "ar5416phy.h" +#include "ar5416desc.h" + +#define N(a) (sizeof(a)/sizeof(a[0])) +#define AR_INTR_SPURIOUS 0xffffffff +#define ar5416_desc ar5416_desc_20 +#define AR5416_ABORT_LOOPS 1000 +#define AR5416_ABORT_WAIT 5 +#define AR5416DESC AR5416DESC_20 +#define AR5416DESC_CONST AR5416DESC_CONST_20 + +/*****************/ +/* Attach/Detach */ +/*****************/ + +static const struct ath_hal_private ar5416hal_10 = {{ + .ah_getRateTable = ar5416GetRateTable, + .ah_detach = ar5416Detach, + + /* Transmit functions */ + .ah_updateTxTrigLevel = ar5416UpdateTxTrigLevel, + .ah_getTxDP = ar5416GetTxDP, + .ah_setTxDP = ar5416SetTxDP, + .ah_numTxPending = ar5416NumTxPending, + .ah_startTxDma = ar5416StartTxDma, + .ah_stopTxDma = ar5416StopTxDma, + + .ah_getTxIntrQueue = ar5416GetTxIntrQueue, + .ah_abortTxDma = ar5416AbortTxDma, + + /* Misc Functions */ + .ah_getCapability = ar5416GetCapability, + .ah_getTsf32 = ar5416GetTsf32, + .ah_getTsf64 = ar5416GetTsf64, + .ah_resetTsf = ar5416ResetTsf, + .ah_setRxFilter = ar5416SetRxFilter, + + /* RX Functions */ + .ah_getRxDP = ar5416GetRxDP, + .ah_setRxDP = ar5416SetRxDP, + .ah_stopDmaReceive = ar5416StopDmaReceive, + .ah_enableReceive = ar5416EnableReceive, + .ah_startPcuReceive = ar5416StartPcuReceive, + .ah_stopPcuReceive = ar5416StopPcuReceive, + + /* Interrupt Functions */ + .ah_isInterruptPending = ar5416IsInterruptPending, + .ah_getPendingInterrupts = ar5416GetPendingInterrupts, + .ah_getInterrupts = ar5416GetInterrupts, + .ah_setInterrupts = ar5416SetInterrupts, + }, +}; + +void ar5416Detach(struct ath_hal *ah) +{ + HALASSERT(ah != AH_NULL); + ath_hal_free(ah); +} + +struct ath_hal * +ar5416Attach(a_uint32_t devid,HAL_SOFTC sc, adf_os_device_t dev, + HAL_BUS_HANDLE sh, a_uint32_t flags, HAL_STATUS *status) +{ + struct ath_hal_5416 *ahp; + struct ath_hal *ah; + + ahp = ath_hal_malloc(sizeof (struct ath_hal_5416)); + if (ahp == AH_NULL) { + *status = HAL_ENOMEM; + return AH_NULL; + } + ah = &ahp->ah_priv.h; + + OS_MEMCPY(&ahp->ah_priv, &ar5416hal_10, sizeof(struct ath_hal_private)); + + ah->ah_dev = dev; + ah->ah_sc = sc; + ah->ah_sh = sh; + + /* If its a Owl 2.0 chip then change the hal structure to + point to the Owl 2.0 ar5416_hal_20 structure */ + if(1) { + ah->ah_set11nTxDesc = ar5416Set11nTxDesc_20; + ah->ah_set11nRateScenario = ar5416Set11nRateScenario_20; + ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst_20; + ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle_20; + ah->ah_set11nAggrLast = ar5416Set11nAggrLast_20; + ah->ah_clr11nAggr = ar5416Clr11nAggr_20; + ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration_20; + ah->ah_setupRxDesc = ar5416SetupRxDesc_20; + ah->ah_procRxDescFast = ar5416ProcRxDescFast_20; + ah->ah_updateCTSForBursting = NULL; + ah->ah_setupTxDesc = ar5416SetupTxDesc_20; + ah->ah_reqTxIntrDesc = ar5416IntrReqTxDesc_20; + ah->ah_fillTxDesc = ar5416FillTxDesc_20; + ah->ah_fillKeyTxDesc = ar5416FillKeyTxDesc_20; + ah->ah_procTxDesc = ar5416ProcTxDesc_20; + ah->ah_set11nVirtualMoreFrag = ar5416Set11nVirtualMoreFrag_20; + } + + return ah; +} + +/**********************/ +/* Interrupt Handling */ +/**********************/ + +HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah) +{ + a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE); + /* + * Some platforms trigger our ISR before applying power to + * the card, so make sure. + */ + return ((host_isr != AR_INTR_SPURIOUS) && (host_isr & AR_INTR_MAC_IRQ)); +} + +HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked) +{ + a_uint32_t isr; +#ifndef AR9100 + HAL_BOOL fatal_int = AH_FALSE; + a_uint32_t sync_cause; + + if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { + if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) { + *masked = 0; + return AH_FALSE; + } + } else { + *masked = 0; + return AH_FALSE; + } +#endif + isr = OS_REG_READ(ah, AR_ISR_RAC); + if (isr == 0xffffffff) { + *masked = 0; + return AH_FALSE; + } + + *masked = isr & HAL_INT_COMMON; + +#ifdef AR5416_INT_MITIGATION + if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) { + *masked |= HAL_INT_RX; + } + if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM)) { + *masked |= HAL_INT_TX; + } +#endif + + if (isr & AR_ISR_BCNMISC) { + a_uint32_t s2_s; + + s2_s = OS_REG_READ(ah, AR_ISR_S2_S); + + if (s2_s & AR_ISR_S2_GTT) { + *masked |= HAL_INT_GTT; + } + + if (s2_s & AR_ISR_S2_CST) { + *masked |= HAL_INT_CST; + } + } + + if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) + *masked |= HAL_INT_RX; + if (isr & (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | AR_ISR_TXEOL)) { + struct ath_hal_5416 *ahp = AH5416(ah); + a_uint32_t s0_s, s1_s; + + *masked |= HAL_INT_TX; + s0_s = OS_REG_READ(ah, AR_ISR_S0_S); + s1_s = OS_REG_READ(ah, AR_ISR_S1_S); + ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); + ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); + ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); + ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); + } + +#ifndef AR9100 + sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); + fatal_int = ((sync_cause != AR_INTR_SPURIOUS) && + (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ? + AH_TRUE : AH_FALSE; + + if (AH_TRUE == fatal_int) { + OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); + (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); + } +#endif + return AH_TRUE; +} + +HAL_INT ar5416GetInterrupts(struct ath_hal *ah) +{ + return AH5416(ah)->ah_maskReg; +} + +HAL_INT +ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + a_uint32_t omask = ahp->ah_maskReg; + a_uint32_t mask; + + if (omask & HAL_INT_GLOBAL) { + OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE); + (void) OS_REG_READ(ah, AR_IER); + } + + mask = ints & HAL_INT_COMMON; + if (ints & HAL_INT_TX) { +#ifdef AR5416_INT_MITIGATION + mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM; +#else + mask |= AR_IMR_TXOK; + mask |= AR_IMR_TXDESC; +#endif + mask |= AR_IMR_TXERR; + mask |= AR_IMR_TXEOL; + } + if (ints & HAL_INT_RX) { + mask |= AR_IMR_RXERR; +#ifdef AR5416_INT_MITIGATION + mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; +#else + mask |= AR_IMR_RXOK | AR_IMR_RXDESC; +#endif + } + + if (ints & (HAL_INT_GTT | HAL_INT_CST)) { + mask |= AR_IMR_BCNMISC; + } + + OS_REG_WRITE(ah, AR_IMR, mask); + (void) OS_REG_READ(ah, AR_IMR); + ahp->ah_maskReg = ints; + + /* Re-enable interrupts if they were enabled before. */ + if (ints & HAL_INT_GLOBAL) { + OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE); + /* See explanation above... */ + (void) OS_REG_READ(ah, AR_IER); + } + + OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ); + OS_REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); + OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_ALL); + + return omask; +} + +/****************/ +/* Capabilities */ +/****************/ + +HAL_STATUS ar5416GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, + a_uint32_t capability, a_uint32_t *result) + +{ + HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; +#ifndef MAGPIE_MERLIN // K2 + pCap->halRxStbcSupport = 1; /* K2 supports STBC Rx only */ + pCap->halTxStbcSupport = 0; +#else + pCap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */ + pCap->halTxStbcSupport = 1; +#endif + + switch (type) { +#ifdef MAGPIE_MERLIN + case HAL_CAP_RX_STBC: + { + *result = pCap->halRxStbcSupport; + return HAL_OK; + } + case HAL_CAP_TX_STBC: + { + *result = pCap->halTxStbcSupport; + return HAL_OK; + } +#endif + default: + return ath_hal_getcapability(ah, type, capability, result); + } +} + +/****************/ +/* TSF Handling */ +/****************/ + +u_int64_t ar5416GetTsf64(struct ath_hal *ah) +{ + u_int64_t tsf; + + tsf = OS_REG_READ(ah, AR_TSF_U32); + tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); + + return tsf; +} + +a_uint32_t ar5416GetTsf32(struct ath_hal *ah) +{ + return OS_REG_READ(ah, AR_TSF_L32); +} + +void ar5416ResetTsf(struct ath_hal *ah) +{ + a_int32_t count; + + count = 0; + + while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { + count++; + if (count > 10) { + break; + } + OS_DELAY(10); + } + OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); +} + +/******/ +/* RX */ +/******/ + +a_uint32_t ar5416GetRxDP(struct ath_hal *ath) +{ + return OS_REG_READ(ath, AR_RXDP); +} + + +void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp) +{ + OS_REG_WRITE(ah, AR_RXDP, rxdp); + HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); +} + +void ar5416SetMulticastFilter(struct ath_hal *ah, a_uint32_t filter0, a_uint32_t filter1) +{ + OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); + OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); +} + +HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *ah, a_uint32_t ix) +{ + a_uint32_t val; + + if (ix >= 64) + return AH_FALSE; + if (ix >= 32) { + val = OS_REG_READ(ah, AR_MCAST_FIL1); + OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); + } else { + val = OS_REG_READ(ah, AR_MCAST_FIL0); + OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<= 64) + return AH_FALSE; + if (ix >= 32) { + val = OS_REG_READ(ah, AR_MCAST_FIL1); + OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); + } else { + val = OS_REG_READ(ah, AR_MCAST_FIL0); + OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<ds_ctl1 = size & AR_BufLen; + if (flags & HAL_RXDESC_INTREQ) + ads->ds_ctl1 |= AR_RxIntrReq; + + /* this should be enough */ + ads->ds_rxstatus8 &= ~AR_RxDone; + + return AH_TRUE; +} + +HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t pa, struct ath_desc *nds, + struct ath_rx_status *rx_stats) +{ + struct ar5416_desc ads; + struct ar5416_desc *adsp = AR5416DESC(ds); + struct ar5416_desc *ands = AR5416DESC(nds); + + if ((adsp->ds_rxstatus8 & AR_RxDone) == 0) + return HAL_EINPROGRESS; + /* + * Given the use of a self-linked tail be very sure that the hw is + * done with this descriptor; the hw may have done this descriptor + * once and picked it up again...make sure the hw has moved on. + */ + if ((ands->ds_rxstatus8 & AR_RxDone) == 0 + && OS_REG_READ(ah, AR_RXDP) == pa) + return HAL_EINPROGRESS; + + /* + * Now we need to get the stats from the descriptor. Since desc are + * uncached, lets make a copy of the stats first. Note that, since we + * touch most of the rx stats, a memcpy would always be more efficient + * + * Next we fill in all values in a caller passed stack variable. + * This reduces the number of uncached accesses. + * Do this copy here, after the check so that when the checks fail, we + * dont end up copying the entire stats uselessly. + */ + ads.u.rx = adsp->u.rx; + + rx_stats->rs_status = 0; + rx_stats->rs_flags = 0; + + rx_stats->rs_datalen = ads.ds_rxstatus1 & AR_DataLen; + rx_stats->rs_tstamp = ads.AR_RcvTimestamp; + + /* XXX what about KeyCacheMiss? */ + rx_stats->rs_rssi_combined = + MS(ads.ds_rxstatus4, AR_RxRSSICombined); + rx_stats->rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00); + rx_stats->rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01); + rx_stats->rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02); + rx_stats->rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10); + rx_stats->rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11); + rx_stats->rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12); + if (ads.ds_rxstatus8 & AR_RxKeyIdxValid) + rx_stats->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx); + else + rx_stats->rs_keyix = HAL_RXKEYIX_INVALID; + /* NB: caller expected to do rate table mapping */ + rx_stats->rs_rate = RXSTATUS_RATE(ah, (&ads)); + rx_stats->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0; + + rx_stats->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0; + rx_stats->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0; + rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0; + rx_stats->rs_flags |= (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0; + + if (ads.ds_rxstatus8 & AR_PreDelimCRCErr) + rx_stats->rs_flags |= HAL_RX_DELIM_CRC_PRE; + if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) + rx_stats->rs_flags |= HAL_RX_DELIM_CRC_POST; + if (ads.ds_rxstatus8 & AR_DecryptBusyErr) + rx_stats->rs_flags |= HAL_RX_DECRYPT_BUSY; + + if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) { + /* + * These four bits should not be set together. The + * 5416 spec states a Michael error can only occur if + * DecryptCRCErr not set (and TKIP is used). Experience + * indicates however that you can also get Michael errors + * when a CRC error is detected, but these are specious. + * Consequently we filter them out here so we don't + * confuse and/or complicate drivers. + */ + if (ads.ds_rxstatus8 & AR_CRCErr) + rx_stats->rs_status |= HAL_RXERR_CRC; + else if (ads.ds_rxstatus8 & AR_PHYErr) { + a_uint32_t phyerr; + + rx_stats->rs_status |= HAL_RXERR_PHY; + phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode); + rx_stats->rs_phyerr = phyerr; + } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr) + rx_stats->rs_status |= HAL_RXERR_DECRYPT; + else if (ads.ds_rxstatus8 & AR_MichaelErr) + rx_stats->rs_status |= HAL_RXERR_MIC; + } + rx_stats->evm0=ads.AR_RxEVM0; + rx_stats->evm1=ads.AR_RxEVM1; + rx_stats->evm2=ads.AR_RxEVM2; + + return HAL_OK; +} + +/******/ +/* TX */ +/******/ + +HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + a_uint32_t txcfg, curLevel, newLevel; + HAL_INT omask; + + /* + * Disable interrupts while futzing with the fifo level. + */ + omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL); + + txcfg = OS_REG_READ(ah, AR_TXCFG); + curLevel = MS(txcfg, AR_FTRIG); + newLevel = curLevel; + + if (bIncTrigLevel) { + if (curLevel < MAX_TX_FIFO_THRESHOLD) + newLevel ++; + } else if (curLevel > MIN_TX_FIFO_THRESHOLD) + newLevel--; + if (newLevel != curLevel) + OS_REG_WRITE(ah, AR_TXCFG, + (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG)); + + /* re-enable chip interrupts */ + ar5416SetInterrupts(ah, omask); + + return (newLevel != curLevel); +} + +a_uint32_t ar5416GetTxDP(struct ath_hal *ah, a_uint32_t q) +{ + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); + return OS_REG_READ(ah, AR_QTXDP(q)); +} + +HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp) +{ + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); + HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); + + /* + * Make sure that TXE is deasserted before setting the TXDP. If TXE + * is still asserted, setting TXDP will have no effect. + */ + HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0); + + OS_REG_WRITE(ah, AR_QTXDP(q), txdp); + + return AH_TRUE; +} + +HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q) +{ + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); + HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); + + /* Check to be sure we're not enabling a q that has its TXD bit set. */ + HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0); + + OS_REG_WRITE(ah, AR_Q_TXE, 1 << q); + + return AH_TRUE; +} + +a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q) +{ + a_uint32_t npend; + + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); + HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); + + npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; + if (npend == 0) { + /* + * Pending frame count (PFC) can momentarily go to zero + * while TXE remains asserted. In other words a PFC of + * zero is not sufficient to say that the queue has stopped. + */ + if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) + npend = 1; + } +#ifdef DEBUG + if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) { + if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) { + isrPrintf("RTSD on CAB queue\n"); + /* Clear the ReadyTime shutdown status bits */ + OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q); + } + } +#endif + return npend; +} + +HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah) +{ + a_int32_t i, q; + + /* + * set txd on all queues + */ + OS_REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); + + /* + * set tx abort bits + */ + OS_REG_SET_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF)); + OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); + OS_REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); + + /* + * wait on all tx queues + */ + for (q = 0; q < AR_NUM_QCU; q++) { + for (i = 0; i < AR5416_ABORT_LOOPS; i++) { + if (!ar5416NumTxPending(ah, q)) + break; + + OS_DELAY(AR5416_ABORT_WAIT); + } + if (i == AR5416_ABORT_LOOPS) { + return AH_FALSE; + } + } + + /* + * clear tx abort bits + */ + OS_REG_CLR_BIT(ah, AR_PCU_MISC, (AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF)); + OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); + OS_REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); + + /* + * clear txd + */ + OS_REG_WRITE(ah, AR_Q_TXD, 0); + + return AH_TRUE; +} + +HAL_BOOL ar5416StopTxDma(struct ath_hal*ah, a_uint32_t q) +{ + a_uint32_t i; + + HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues); + + HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE); + + OS_REG_WRITE(ah, AR_Q_TXD, 1 << q); + for (i = 1000; i != 0; i--) { + if (ar5416NumTxPending(ah, q) == 0) + break; + OS_DELAY(100); /* XXX get actual value */ + } + + OS_REG_WRITE(ah, AR_Q_TXD, 0); + return (i != 0); +} + +void ar5416GetTxIntrQueue(struct ath_hal *ah, a_uint32_t *txqs) +{ + struct ath_hal_5416 *ahp = AH5416(ah); + *txqs &= ahp->ah_intrTxqs; + ahp->ah_intrTxqs &= ~(*txqs); +} + +void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + ads->ds_ctl0 |= AR_TxIntrReq; +} + +HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t pktLen, + a_uint32_t hdrLen, + HAL_PKT_TYPE type, + a_uint32_t txPower, + a_uint32_t txRate0, a_uint32_t txTries0, + a_uint32_t keyIx, + a_uint32_t antMode, + a_uint32_t flags, + a_uint32_t rtsctsRate, + a_uint32_t rtsctsDuration, + a_uint32_t compicvLen, + a_uint32_t compivLen, + a_uint32_t comp) +{ +#define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA) + + struct ar5416_desc *ads = AR5416DESC(ds); + struct ath_hal_5416 *ahp = AH5416(ah); + + (void) hdrLen; + + ads->ds_txstatus9 &= ~AR_TxDone; + + HALASSERT(txTries0 != 0); + HALASSERT(isValidPktType(type)); + HALASSERT(isValidTxRate(txRate0)); + HALASSERT((flags & RTSCTS) != RTSCTS); + + if (txPower > 63) + txPower=63; + + ads->ds_ctl0 = (pktLen & AR_FrameLen) + | (txPower << AR_XmitPower_S) + | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0) + | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) + | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0); + + ads->ds_ctl1 = (type << AR_FrameType_S) + | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0); + ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0); + ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S); + + ads->ds_ctl7 = SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel0) + | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel1) + | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel2) + | SM(AR5416_LEGACY_CHAINMASK, AR_ChainSel3); + + if (keyIx != HAL_TXKEYIX_INVALID) { + /* XXX validate key index */ + ads->ds_ctl1 |= SM(keyIx, AR_DestIdx); + ads->ds_ctl0 |= AR_DestIdxValid; + } + + if (flags & RTSCTS) { + if (!isValidTxRate(rtsctsRate)) { + return AH_FALSE; + } + /* XXX validate rtsctsDuration */ + ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0) + | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0); + ads->ds_ctl2 |= SM(rtsctsDuration, AR_BurstDur); + ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S); + } + return AH_TRUE; + +#undef RTSCTS +} + +HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, + const struct ath_desc *ds0) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + + HALASSERT((segLen &~ AR_BufLen) == 0); + + if (firstSeg) { + /* + * First descriptor, don't clobber xmit control data + * setup by ar5416SetupTxDesc. + */ + ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore); + } else if (lastSeg) { + /* + * Last descriptor in a multi-descriptor frame, + * copy the multi-rate transmit parameters from + * the first frame for processing on completion. + */ + ads->ds_ctl0 = 0; + ads->ds_ctl1 = segLen; + ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2; + ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3; + } else { + /* + * Intermediate descriptor in a multi-descriptor frame. + */ + ads->ds_ctl0 = 0; + ads->ds_ctl1 = segLen | AR_TxMore; + ads->ds_ctl2 = 0; + ads->ds_ctl3 = 0; + } + ads->ds_txstatus0 = ads->ds_txstatus1 = 0; + + return AH_TRUE; +} + +HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_desc *ds, + HAL_KEY_TYPE keyType) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + + ads->ds_ctl6 = SM(keyType, AR_EncrType); + return AH_TRUE; +} + +HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_desc *gds) +{ + struct ar5416_desc *ads = AR5416DESC(gds); + struct ath_tx_desc *ds = (struct ath_tx_desc *)gds; + + if ((ads->ds_txstatus9 & AR_TxDone) == 0) + return HAL_EINPROGRESS; + + ads->ds_txstatus9 &= ~AR_TxDone; + + /* Update software copies of the HW status */ + ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum); + ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp; + ds->ds_txstat.ts_status = 0; + ds->ds_txstat.ts_flags = 0; + + if (ads->ds_txstatus1 & AR_ExcessiveRetries) + ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY; + if (ads->ds_txstatus1 & AR_Filtered) + ds->ds_txstat.ts_status |= HAL_TXERR_FILT; + if (ads->ds_txstatus1 & AR_FIFOUnderrun) + ds->ds_txstat.ts_status |= HAL_TXERR_FIFO; + if (ads->ds_txstatus9 & AR_TxOpExceeded) + ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP; + if (ads->ds_txstatus1 & AR_TxTimerExpired) + ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED; + + if (ads->ds_txstatus1 & AR_DescCfgErr) + ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR; + if (ads->ds_txstatus1 & AR_TxDataUnderrun) { + ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN; + ar5416UpdateTxTrigLevel(ah, AH_TRUE); + } + if (ads->ds_txstatus1 & AR_TxDelimUnderrun) { + ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN; + ar5416UpdateTxTrigLevel(ah, AH_TRUE); + } + if (ads->ds_txstatus0 & AR_TxBaStatus) { + ds->ds_txstat.ts_flags |= HAL_TX_BA; + ds->ds_txstat.ba_low = ads->AR_BaBitmapLow; + ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh; + } + + /* + * Extract the transmit rate used and mark the rate as + * ``alternate'' if it wasn't the series 0 rate. + */ + ds->ds_txstat.ts_rate = MS(ads->ds_txstatus9, AR_FinalTxIdx); + ds->ds_txstat.ts_rssi_combined = + MS(ads->ds_txstatus5, AR_TxRSSICombined); + ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00); + ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01); + ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02); + ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10); + ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11); + ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12); + ds->ds_txstat.evm0 = ads->AR_TxEVM0; + ds->ds_txstat.evm1 = ads->AR_TxEVM1; + ds->ds_txstat.evm2 = ads->AR_TxEVM2; + ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt); + ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt); + ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt); + ds->ds_txstat.ts_antenna = 0; /* ignored for owl */ + + return HAL_OK; +} + +void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower, + a_uint32_t keyIx, HAL_KEY_TYPE keyType, + a_uint32_t flags) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + struct ath_hal_5416 *ahp = AH5416(ah); + + HALASSERT(isValidPktType(type)); + HALASSERT(isValidKeyType(keyType)); + + if (txPower > 63) + txPower = 63; + + ads->ds_ctl0 = (pktLen & AR_FrameLen) + | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0) + | SM(txPower, AR_XmitPower) + | (flags & HAL_TXDESC_RTSENA ? AR_RTSEnable : 0) + | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0) + | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0) + | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0) + | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0) + | (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0); + + ads->ds_ctl1 = (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0) + | SM(type, AR_FrameType) + | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0) + | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0) + | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0); + + ads->ds_ctl6 = SM(keyType, AR_EncrType); +} + +#ifdef MAGPIE_MERLIN + +void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, + a_uint32_t rtsctsDuration, + HAL_11N_RATE_SERIES series[], a_uint32_t nseries, + a_uint32_t flags) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + struct ar5416_desc_20 *ads_20 = AR5416DESC_20(ds); + a_uint32_t ds_ctl0; + a_int16_t txpower; + a_uint32_t count; + struct ath_hal_private *ahpriv = AH_PRIVATE(ah); + + HALASSERT(nseries == 4); + (void)nseries; + + /* + * Rate control settings override + */ + ds_ctl0 = ads->ds_ctl0; + + if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { + if (flags & HAL_TXDESC_RTSENA) { + ds_ctl0 &= ~AR_CTSEnable; + ds_ctl0 |= AR_RTSEnable; + } else { + ds_ctl0 &= ~AR_RTSEnable; + ds_ctl0 |= AR_CTSEnable; + } + } else { + ds_ctl0 = (ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable)); + } + + ads->ds_ctl0 = ds_ctl0; + + ads->ds_ctl2 = set11nTries(series, 0) + | set11nTries(series, 1) + | set11nTries(series, 2) + | set11nTries(series, 3) + | (durUpdateEn ? AR_DurUpdateEn : 0); + + ads->ds_ctl3 = set11nRate(series, 0) + | set11nRate(series, 1) + | set11nRate(series, 2) + | set11nRate(series, 3); + + ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) + | set11nPktDurRTSCTS(series, 1); + + ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) + | set11nPktDurRTSCTS(series, 3); + + ads->ds_ctl7 = set11nRateFlags(series, 0) + | set11nRateFlags(series, 1) + | set11nRateFlags(series, 2) + | set11nRateFlags(series, 3) + | SM(rtsctsRate, AR_RTSCTSRate); +} + +#else + +void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, + a_uint32_t rtsctsDuration, + HAL_11N_RATE_SERIES series[], a_uint32_t nseries, + a_uint32_t flags) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + a_uint32_t ds_ctl0; + + HALASSERT(nseries == 4); + (void)nseries; + + /* + * Rate control settings override + */ + if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) { + ds_ctl0 = ads->ds_ctl0; + + if (flags & HAL_TXDESC_RTSENA) { + ds_ctl0 &= ~AR_CTSEnable; + ds_ctl0 |= AR_RTSEnable; + } else { + ds_ctl0 &= ~AR_RTSEnable; + ds_ctl0 |= AR_CTSEnable; + } + + ads->ds_ctl0 = ds_ctl0; + } + + ads->ds_ctl2 = set11nTries(series, 0) + | set11nTries(series, 1) + | set11nTries(series, 2) + | set11nTries(series, 3) + | (durUpdateEn ? AR_DurUpdateEn : 0); + + ads->ds_ctl3 = set11nRate(series, 0) + | set11nRate(series, 1) + | set11nRate(series, 2) + | set11nRate(series, 3); + + ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0) + | set11nPktDurRTSCTS(series, 1); + + ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2) + | set11nPktDurRTSCTS(series, 3); + + ads->ds_ctl7 = set11nRateFlags(series, 0) + | set11nRateFlags(series, 1) + | set11nRateFlags(series, 2) + | set11nRateFlags(series, 3) + | SM(rtsctsRate, AR_RTSCTSRate); +} + +#endif + +void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_desc *ds, a_uint32_t aggrLen, + a_uint32_t numDelims) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + + ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); + + ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim); + ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) | + SM(numDelims, AR_PadDelim); +} + +void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_desc *ds, a_uint32_t numDelims) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + a_uint32_t ctl6; + + ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr); + + /* + * We use a stack variable to manipulate ctl6 to reduce uncached + * read modify, modfiy, write. + */ + ctl6 = ads->ds_ctl6; + ctl6 &= ~AR_PadDelim; + ctl6 |= SM(numDelims, AR_PadDelim); + ads->ds_ctl6 = ctl6; +} + +void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_desc *ds) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + + ads->ds_ctl1 |= AR_IsAggr; + ads->ds_ctl1 &= ~AR_MoreAggr; + ads->ds_ctl6 &= ~AR_PadDelim; +} + +void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_desc *ds) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + + ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr); +} + +void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t burstDuration) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + + ads->ds_ctl2 &= ~AR_BurstDur; + ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur); +} + +void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t vmf) +{ + struct ar5416_desc *ads = AR5416DESC(ds); + + if (vmf) { + ads->ds_ctl0 |= AR_VirtMoreFrag; + } else { + ads->ds_ctl0 &= ~AR_VirtMoreFrag; + } +} diff --git a/target_firmware/wlan/ar5416_phy.c b/target_firmware/wlan/ar5416_phy.c new file mode 100755 index 0000000..fc7c042 --- /dev/null +++ b/target_firmware/wlan/ar5416_phy.c @@ -0,0 +1,295 @@ +#include "opt_ah.h" +#include "ah.h" +#include "ah_internal.h" +#include "ar5416.h" + +#ifdef MAGPIE_MERLIN + +#define OFDM IEEE80211_T_OFDM +#define CCK IEEE80211_T_CCK +#define TURBO IEEE80211_T_TURBO +#define XR ATHEROS_T_XR +#define HT IEEE80211_T_HT + +HAL_RATE_TABLE ar5416_11a_table = { + 8, /* number of rates */ + { 0 }, + { + /* short ctrl */ + /* valid rateCode Preamble dot11Rate Rate */ + /* 6 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 6000, 0x0b, 0x00, (0x80|12), 0 }, + /* 9 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 9000, 0x0f, 0x00, 18, 0 }, + /* 12 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 12000, 0x0a, 0x00, (0x80|24), 2 }, + /* 18 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 18000, 0x0e, 0x00, 36, 2 }, + /* 24 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 24000, 0x09, 0x00, (0x80|48), 4 }, + /* 36 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 36000, 0x0d, 0x00, 72, 4 }, + /* 48 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 48000, 0x08, 0x00, 96, 4 }, + /* 54 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 54000, 0x0c, 0x00, 108, 4 } + }, +}; + +HAL_RATE_TABLE ar5416_11b_table = { + 4, /* number of rates */ + { 0 }, + { + /* short ctrl */ + /* valid rateCode Preamble dot11Rate Rate */ + /* 1 Mb */ { AH_TRUE, CCK, 60, 60, 60, 1000, 0x1b, 0x00, (0x80| 2), 0 }, + /* 2 Mb */ { AH_TRUE, CCK, 60, 60, 60, 2000, 0x1a, 0x04, (0x80| 4), 1 }, + /* 5.5 Mb */ { AH_TRUE, CCK, 60, 60, 60, 5500, 0x19, 0x04, (0x80|11), 1 }, + /* 11 Mb */ { AH_TRUE, CCK, 60, 60, 60, 11000, 0x18, 0x04, (0x80|22), 1 } + }, +}; + +HAL_RATE_TABLE ar5416_11g_table = { + 12, /* number of rates */ + { 0 }, + { + /* short ctrl */ + /* valid rateCode Preamble dot11Rate Rate */ + /* 1 Mb */ { AH_TRUE, CCK, 60, 60, 60, 1000, 0x1b, 0x00, (0x80| 2), 0 }, + /* 2 Mb */ { AH_TRUE, CCK, 60, 60, 60, 2000, 0x1a, 0x04, (0x80| 4), 1 }, + /* 5.5 Mb */ { AH_TRUE, CCK, 60, 60, 60, 5500, 0x19, 0x04, (0x80|11), 2 }, + /* 11 Mb */ { AH_TRUE, CCK, 60, 60, 60, 11000, 0x18, 0x04, (0x80|22), 3 }, + /* Hardware workaround - remove rates 6, 9 from rate ctrl */ + /* 6 Mb */ { AH_FALSE, OFDM, 60, 60, 60, 6000, 0x0b, 0x00, 12, 4 }, + /* 9 Mb */ { AH_FALSE, OFDM, 60, 60, 60, 9000, 0x0f, 0x00, 18, 4 }, + /* 12 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 12000, 0x0a, 0x00, 24, 6 }, + /* 18 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 18000, 0x0e, 0x00, 36, 6 }, + /* 24 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 24000, 0x09, 0x00, 48, 8 }, + /* 36 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 36000, 0x0d, 0x00, 72, 8 }, + /* 48 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 48000, 0x08, 0x00, 96, 8 }, + /* 54 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 54000, 0x0c, 0x00, 108, 8 } + }, +}; + +HAL_RATE_TABLE ar5416_11ng_table = { + + 28, /* number of rates */ + { -1 }, + { + /* short ctrl */ + /* valid rateCode Preamble dot11Rate Rate */ + /* 1 Mb */ { AH_TRUE, CCK, 60, 60, 60, 1000, 0x1b, 0x00, (0x80| 2), 0 }, + /* 2 Mb */ { AH_TRUE, CCK, 60, 60, 60, 2000, 0x1a, 0x04, (0x80| 4), 1 }, + /* 5.5 Mb */ { AH_TRUE, CCK, 60, 60, 60, 5500, 0x19, 0x04, (0x80|11), 2 }, + /* 11 Mb */ { AH_TRUE, CCK, 60, 60, 60, 11000, 0x18, 0x04, (0x80|22), 3 }, + /* Hardware workaround - remove rates 6, 9 from rate ctrl */ + /* 6 Mb */ { AH_FALSE, OFDM, 60, 60, 60, 6000, 0x0b, 0x00, 12, 4 }, + /* 9 Mb */ { AH_FALSE, OFDM, 60, 60, 60, 9000, 0x0f, 0x00, 18, 4 }, + /* 12 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 12000, 0x0a, 0x00, 24, 6 }, + /* 18 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 18000, 0x0e, 0x00, 36, 6 }, + /* 24 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 24000, 0x09, 0x00, 48, 8 }, + /* 36 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 36000, 0x0d, 0x00, 72, 8 }, + /* 48 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 48000, 0x08, 0x00, 96, 8 }, + /* 54 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 54000, 0x0c, 0x00, 108, 8 }, + /* 6.5 Mb */ { AH_TRUE, HT, 60,60, 60, 6500, 0x80, 0x00, 0, 4 }, + /* 13 Mb */ { AH_TRUE, HT, 60, 60, 60, 13000, 0x81, 0x00, 1, 6 }, + /*19.5 Mb */ { AH_TRUE, HT, 60,60, 60, 19500, 0x82, 0x00, 2, 6 }, + /* 26 Mb */ { AH_TRUE, HT, 60, 60, 60, 26000, 0x83, 0x00, 3, 8 }, + /* 39 Mb */ { AH_TRUE, HT, 60, 60, 60, 39000, 0x84, 0x00, 4, 8 }, + /* 52 Mb */ { AH_TRUE, HT, 60, 60, 60, 52000, 0x85, 0x00, 5, 8 }, + /*58.5 Mb */ { AH_TRUE, HT, 60,60,60, 58500, 0x86, 0x00, 6, 8 }, + /* 65 Mb */ { AH_TRUE, HT, 60, 60, 60, 65000, 0x87, 0x00, 7, 8 }, + /* 13 Mb */ { AH_TRUE, HT, 60, 60, 60, 13000, 0x88, 0x00, 8, 4 }, + /* 26 Mb */ { AH_TRUE, HT, 60, 60, 60, 26000, 0x89, 0x00, 9, 6 }, + /* 39 Mb */ { AH_TRUE, HT, 60, 60, 60, 39000, 0x8a, 0x00, 10, 6 }, + /* 52 Mb */ { AH_TRUE, HT, 60, 60, 60, 52000, 0x8b, 0x00, 11, 8 }, + /* 78 Mb */ { AH_TRUE, HT, 60, 60, 60, 78000, 0x8c, 0x00, 12, 8 }, + /* 104 Mb */ { AH_TRUE, HT, 60, 60, 60, 104000, 0x8d, 0x00, 13, 8 }, + /* 117 Mb */ { AH_TRUE, HT, 60, 60, 60, 117000, 0x8e, 0x00, 14, 8 }, + /* 130 Mb */ { AH_TRUE, HT, 60, 60, 60, 130000, 0x8f, 0x00, 15, 8 }, + }, +}; + +HAL_RATE_TABLE ar5416_11na_table = { + + 24, /* number of rates */ + { -1 }, + { + /* short ctrl */ + /* valid rateCode Preamble dot11Rate Rate */ + /* 6 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 6000, 0x0b, 0x00, (0x80|12), 0 }, + /* 9 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 9000, 0x0f, 0x00, 18, 0 }, + /* 12 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 12000, 0x0a, 0x00, (0x80|24), 2 }, + /* 18 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 18000, 0x0e, 0x00, 36, 2 }, + /* 24 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 24000, 0x09, 0x00, (0x80|48), 4 }, + /* 36 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 36000, 0x0d, 0x00, 72, 4 }, + /* 48 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 48000, 0x08, 0x00, 96, 4 }, + /* 54 Mb */ { AH_TRUE, OFDM, 60, 60, 60, 54000, 0x0c, 0x00, 108, 4 }, + /* 6.5 Mb */ { AH_TRUE, HT, 60, 60, 60, 6500, 0x80, 0x00, 0, 0 }, + /* 13 Mb */ { AH_TRUE, HT, 60, 60, 60, 13000, 0x81, 0x00, 1, 2 }, + /*19.5 Mb */ { AH_TRUE, HT, 60, 60, 60, 19500, 0x82, 0x00, 2, 2 }, + /* 26 Mb */ { AH_TRUE, HT, 60, 60, 60, 26000, 0x83, 0x00, 3, 4 }, + /* 39 Mb */ { AH_TRUE, HT, 60, 60, 60, 39000, 0x84, 0x00, 4, 4 }, + /* 52 Mb */ { AH_TRUE, HT, 60, 60, 60, 52000, 0x85, 0x00, 5, 4 }, + /*58.5 Mb */ { AH_TRUE, HT, 60, 60, 60, 58500, 0x86, 0x00, 6, 4 }, + /* 65 Mb */ { AH_TRUE, HT, 60, 60, 60, 65000, 0x87, 0x00, 7, 4 }, + /* 13 Mb */ { AH_TRUE, HT, 60, 60, 60, 13000, 0x88, 0x00, 8, 0 }, + /* 26 Mb */ { AH_TRUE, HT, 60, 60, 60, 26000, 0x89, 0x00, 9, 2 }, + /* 39 Mb */ { AH_TRUE, HT, 60, 60, 60, 39000, 0x8a, 0x00, 10, 2 }, + /* 52 Mb */ { AH_TRUE, HT, 60, 60, 60, 52000, 0x8b, 0x00, 11, 4 }, + /* 78 Mb */ { AH_TRUE, HT, 60, 60, 60, 78000, 0x8c, 0x00, 12, 4 }, + /* 104 Mb */ { AH_TRUE, HT, 60, 60, 60, 104000, 0x8d, 0x00, 13, 4 }, + /* 117 Mb */ { AH_TRUE, HT, 60, 60, 60, 117000, 0x8e, 0x00, 14, 4 }, + /* 130 Mb */ { AH_TRUE, HT, 60, 60, 60, 130000, 0x8f, 0x00, 15, 4 }, + }, +}; + +adf_os_export_symbol(ar5416_11na_table); + +#undef OFDM +#undef CCK +#undef TURBO +#undef XR +#undef HT +#undef HT_HGI + +const HAL_RATE_TABLE * +ar5416GetRateTable(struct ath_hal *ah, a_uint32_t mode) +{ + HAL_RATE_TABLE *rt; + switch (mode) { + case HAL_MODE_11A: + rt = &ar5416_11a_table; + break; + case HAL_MODE_11B: + rt = &ar5416_11b_table; + break; + case HAL_MODE_11G: + rt = &ar5416_11g_table; + break; + case HAL_MODE_11NG: + rt = &ar5416_11ng_table; + break; + case HAL_MODE_11NA: + rt = &ar5416_11na_table; + break; + default: + return AH_NULL; + } + + return rt; +} + +#else + +#define OFDM IEEE80211_T_OFDM +#define CCK IEEE80211_T_CCK +#define TURBO IEEE80211_T_TURBO +#define XR ATHEROS_T_XR +#define HT IEEE80211_T_HT + +HAL_RATE_TABLE ar5416_11ng_table = { + + 33, /* number of rates */ + { -1 }, + { + /* short ctrl */ + /* valid rateCode Preamble dot11Rate Rate */ + /*[ 0] 1 Mb */ { AH_TRUE, CCK, 1000, 0x1b, 0x00, (0x80| 2), 0 }, + /*[ 1] 2 Mb */ { AH_TRUE, CCK, 2000, 0x1a, 0x04, (0x80| 4), 1 }, + /*[ 2] 5.5 Mb */ { AH_TRUE, CCK, 5500, 0x19, 0x04, (0x80|11), 2 }, + /*[ 3] 11 Mb */ { AH_TRUE, CCK, 11000, 0x18, 0x04, (0x80|22), 3 }, + /* Hardware workaround - remove rates 6, 9 from rate ctrl */ + /*[ 4] 6 Mb */ { AH_FALSE, OFDM, 6000, 0x0b, 0x00, 12, 4 }, + /*[ 5] 9 Mb */ { AH_FALSE, OFDM, 9000, 0x0f, 0x00, 18, 4 }, + /*[ 6] 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, 24, 6 }, + /*[ 7] 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 6 }, + /*[ 8] 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, 48, 8 }, + /*[ 9] 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 8 }, + /*[10] 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 8 }, + /*[11] 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 8 }, + /*[12] 6.5 Mb */ { AH_TRUE, HT, 6500, 0x80, 0x00, 0, 4 }, + /*[13] 13 Mb */ { AH_TRUE, HT, 13000, 0x81, 0x00, 1, 6 }, + /*[14]19.5 Mb */ { AH_TRUE, HT, 19500, 0x82, 0x00, 2, 6 }, + /*[15] 26 Mb */ { AH_TRUE, HT, 26000, 0x83, 0x00, 3, 8 }, + /*[16] 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 8 }, + /*[17] 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 8 }, + /*[18] 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 8 }, + /*[19] 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 8 }, + /*[20]58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 8 }, + /*[21]58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 8 }, + /*[22] 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 8 }, + /*[23] 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 8 }, + /*[24] 52 Mb */ { AH_TRUE, HT, 52000, 0x8b, 0x00, 11, 8 }, + /*[25] 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 8 }, + /*[26] 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 8 }, + /*[27] 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 8 }, + /*[28] 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 8 }, + /*[29] 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 8 }, + /*[30] 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 8 }, + /*[31] 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 8 }, + /*[32] 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 8 }, + }, +}; + +#ifdef ATH_SUPPORT_A_MODE + +HAL_RATE_TABLE ar5416_11na_table = { + + 28, /* number of rates */ + { -1 }, + { + /* short ctrl */ + /* valid rateCode Preamble dot11Rate Rate */ + /*[ 0] 6 Mb */ { AH_TRUE, OFDM, 6000, 0x0b, 0x00, (0x80|12), 0 }, + /*[ 1] 9 Mb */ { AH_TRUE, OFDM, 9000, 0x0f, 0x00, 18, 0 }, + /*[ 2] 12 Mb */ { AH_TRUE, OFDM, 12000, 0x0a, 0x00, (0x80|24), 2 }, + /*[ 3] 18 Mb */ { AH_TRUE, OFDM, 18000, 0x0e, 0x00, 36, 2 }, + /*[ 4] 24 Mb */ { AH_TRUE, OFDM, 24000, 0x09, 0x00, (0x80|48), 4 }, + /*[ 5] 36 Mb */ { AH_TRUE, OFDM, 36000, 0x0d, 0x00, 72, 4 }, + /*[ 6] 48 Mb */ { AH_TRUE, OFDM, 48000, 0x08, 0x00, 96, 4 }, + /*[ 7] 54 Mb */ { AH_TRUE, OFDM, 54000, 0x0c, 0x00, 108, 4 }, + /*[ 8] 6.5 Mb */ { AH_TRUE, HT, 6500, 0x80, 0x00, 0, 0 }, + /*[ 9] 13 Mb */ { AH_TRUE, HT, 13000, 0x81, 0x00, 1, 2 }, + /*[10]19.5 Mb */ { AH_TRUE, HT, 19500, 0x82, 0x00, 2, 2 }, + /*[11] 26 Mb */ { AH_TRUE, HT, 26000, 0x83, 0x00, 3, 4 }, + /*[12] 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 4 }, + /*[13] 39 Mb */ { AH_TRUE, HT, 39000, 0x84, 0x00, 4, 4 }, + /*[14] 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 4 }, + /*[15] 52 Mb */ { AH_TRUE, HT, 52000, 0x85, 0x00, 5, 4 }, + /*[16]58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 4 }, + /*[17]58.5 Mb */ { AH_TRUE, HT, 58500, 0x86, 0x00, 6, 4 }, + /*[18] 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 4 }, + /*[19] 65 Mb */ { AH_TRUE, HT, 65000, 0x87, 0x00, 7, 4 }, + /*[20] 52 Mb */ { AH_TRUE, HT, 52000, 0x8b, 0x00, 11, 4 }, + /*[21] 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 4 }, + /*[22] 78 Mb */ { AH_TRUE, HT, 78000, 0x8c, 0x00, 12, 4 }, + /*[23] 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 4 }, + /*[24] 104 Mb */ { AH_TRUE, HT, 104000, 0x8d, 0x00, 13, 4 }, + /*[25] 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 4 }, + /*[26] 117 Mb */ { AH_TRUE, HT, 117000, 0x8e, 0x00, 14, 4 }, + /*[27] 130 Mb */ { AH_TRUE, HT, 130000, 0x8f, 0x00, 15, 4 }, + }, +}; +#endif + +#undef OFDM +#undef CCK +#undef TURBO +#undef XR +#undef HT +#undef HT_HGI + +const HAL_RATE_TABLE * +ar5416GetRateTable(struct ath_hal *ah, a_uint32_t mode) +{ + HAL_RATE_TABLE *rt; + switch (mode) { + case HAL_MODE_11NG: + rt = &ar5416_11ng_table; + break; +#ifdef ATH_SUPPORT_A_MODE + case HAL_MODE_11NA: + rt = &ar5416_11na_table; + break; +#endif + default: + return AH_NULL; + } + + return rt; +} + +#endif diff --git a/target_firmware/wlan/ar5416desc.h b/target_firmware/wlan/ar5416desc.h new file mode 100755 index 0000000..9bc5931 --- /dev/null +++ b/target_firmware/wlan/ar5416desc.h @@ -0,0 +1,465 @@ +#ifndef _ATH_AR5416_DESC_H_ +#define _ATH_AR5416_DESC_H_ + +#define ds_ctl8 u.tx.ctl8 +#define ds_ctl9 u.tx.ctl9 +#define ds_ctl10 u.tx.ctl10 +#define ds_ctl11 u.tx.ctl11 + +struct ar5416_desc_20 { + a_uint32_t ds_link; /* link pointer */ + a_uint32_t ds_data; /* data buffer pointer */ + a_uint32_t ds_ctl0; /* DMA control 0 */ + a_uint32_t ds_ctl1; /* DMA control 1 */ + union { + struct { + a_uint32_t ctl2; + a_uint32_t ctl3; + a_uint32_t ctl4; + a_uint32_t ctl5; + a_uint32_t ctl6; + a_uint32_t ctl7; + a_uint32_t ctl8; + a_uint32_t ctl9; + a_uint32_t ctl10; + a_uint32_t ctl11; + a_uint32_t status0; + a_uint32_t status1; + a_uint32_t status2; + a_uint32_t status3; + a_uint32_t status4; + a_uint32_t status5; + a_uint32_t status6; + a_uint32_t status7; + a_uint32_t status8; + a_uint32_t status9; + } tx; + struct { /* rx desc has 2 control words + 9 status words */ + a_uint32_t status0; + a_uint32_t status1; + a_uint32_t status2; + a_uint32_t status3; + a_uint32_t status4; + a_uint32_t status5; + a_uint32_t status6; + a_uint32_t status7; + a_uint32_t status8; + } rx; + } u; +} adf_os_packed; + +#define AR5416DESC_20(_ds) ((struct ar5416_desc_20 *)(_ds)) +#define AR5416DESC_CONST_20(_ds) ((const struct ar5416_desc_20 *)(_ds)) + +#define ds_ctl2 u.tx.ctl2 +#define ds_ctl3 u.tx.ctl3 +#define ds_ctl4 u.tx.ctl4 +#define ds_ctl5 u.tx.ctl5 +#define ds_ctl6 u.tx.ctl6 +#define ds_ctl7 u.tx.ctl7 + +#define ds_txstatus0 u.tx.status0 +#define ds_txstatus1 u.tx.status1 +#define ds_txstatus2 u.tx.status2 +#define ds_txstatus3 u.tx.status3 +#define ds_txstatus4 u.tx.status4 +#define ds_txstatus5 u.tx.status5 +#define ds_txstatus6 u.tx.status6 +#define ds_txstatus7 u.tx.status7 +#define ds_txstatus8 u.tx.status8 +#define ds_txstatus9 u.tx.status9 + +#define ds_rxstatus0 u.rx.status0 +#define ds_rxstatus1 u.rx.status1 +#define ds_rxstatus2 u.rx.status2 +#define ds_rxstatus3 u.rx.status3 +#define ds_rxstatus4 u.rx.status4 +#define ds_rxstatus5 u.rx.status5 +#define ds_rxstatus6 u.rx.status6 +#define ds_rxstatus7 u.rx.status7 +#define ds_rxstatus8 u.rx.status8 + +/*********** + * TX Desc * + ***********/ + +/* ds_ctl0 */ +#define AR_FrameLen 0x00000fff +#define AR_VirtMoreFrag 0x00001000 +#define AR_TxCtlRsvd00 0x0000e000 + +#define AR_XmitPower 0x003f0000 +#define AR_XmitPower_S 16 + +#define AR_RTSEnable 0x00400000 +#define AR_VEOL 0x00800000 +#define AR_ClrDestMask 0x01000000 +#define AR_TxCtlRsvd01 0x1e000000 +#define AR_TxIntrReq 0x20000000 +#define AR_DestIdxValid 0x40000000 +#define AR_CTSEnable 0x80000000 + +/* ds_ctl1 */ +#define AR_BufLen 0x00000fff +#define AR_TxMore 0x00001000 +#define AR_DestIdx 0x000fe000 +#define AR_DestIdx_S 13 +#define AR_FrameType 0x00f00000 +#define AR_FrameType_S 20 +#define AR_NoAck 0x01000000 +#define AR_InsertTS 0x02000000 +#define AR_CorruptFCS 0x04000000 +#define AR_ExtOnly 0x08000000 +#define AR_ExtAndCtl 0x10000000 +#define AR_MoreAggr 0x20000000 +#define AR_IsAggr 0x40000000 +#define AR_MoreRifs 0x80000000 + +/* ds_ctl2 */ +#define AR_BurstDur 0x00007fff +#define AR_BurstDur_S 0 +#define AR_DurUpdateEn 0x00008000 +#define AR_XmitDataTries0 0x000f0000 +#define AR_XmitDataTries0_S 16 +#define AR_XmitDataTries1 0x00f00000 +#define AR_XmitDataTries1_S 20 +#define AR_XmitDataTries2 0x0f000000 +#define AR_XmitDataTries2_S 24 +#define AR_XmitDataTries3 0xf0000000 +#define AR_XmitDataTries3_S 28 + +/* ds_ctl3 */ +#define AR_XmitRate0 0x000000ff +#define AR_XmitRate0_S 0 +#define AR_XmitRate1 0x0000ff00 +#define AR_XmitRate1_S 8 +#define AR_XmitRate2 0x00ff0000 +#define AR_XmitRate2_S 16 +#define AR_XmitRate3 0xff000000 +#define AR_XmitRate3_S 24 + +/* ds_ctl4 */ +#define AR_PacketDur0 0x00007fff +#define AR_PacketDur0_S 0 +#define AR_RTSCTSQual0 0x00008000 +#define AR_PacketDur1 0x7fff0000 +#define AR_PacketDur1_S 16 +#define AR_RTSCTSQual1 0x80000000 + +/* ds_ctl5 */ +#define AR_PacketDur2 0x00007fff +#define AR_PacketDur2_S 0 +#define AR_RTSCTSQual2 0x00008000 +#define AR_PacketDur3 0x7fff0000 +#define AR_PacketDur3_S 16 +#define AR_RTSCTSQual3 0x80000000 + +/* ds_ctl6 */ +#define AR_AggrLen 0x0000ffff +#define AR_AggrLen_S 0 +#define AR_TxCtlRsvd60 0x00030000 +#define AR_PadDelim 0x03fc0000 +#define AR_PadDelim_S 18 +#define AR_EncrType 0x1c000000 +#define AR_EncrType_S 26 +#define AR_TxCtlRsvd61 0xf0000000 + +/* ds_ctl 7 */ +#define AR_2040_0 0x00000001 +#define AR_GI0 0x00000002 +#define AR_ChainSel0 0x0000001c +#define AR_ChainSel0_S 2 +#define AR_2040_1 0x00000020 +#define AR_GI1 0x00000040 +#define AR_ChainSel1 0x00000380 +#define AR_ChainSel1_S 7 +#define AR_2040_2 0x00000400 +#define AR_GI2 0x00000800 +#define AR_ChainSel2 0x00007000 +#define AR_ChainSel2_S 12 +#define AR_2040_3 0x00008000 +#define AR_GI3 0x00010000 +#define AR_ChainSel3 0x000e0000 +#define AR_ChainSel3_S 17 +#define AR_RTSCTSRate 0x0ff00000 +#define AR_RTSCTSRate_S 20 +#define AR_TxCtlRsvd70 0xf0000000 +#define AR_STBC0 0x10000000 +#define AR_STBC1 0x20000000 +#define AR_STBC2 0x40000000 +#define AR_STBC3 0x80000000 + +#ifdef MAGPIE_MERLIN +/* ds_ctl 8 */ +#define AR_TxCtlRsvd80 0xffffffff + +/* ds_ctl 9 */ +#define AR_TxCtlRsvd90 0x00ffffff +#define AR_XmitPower1 0x3f000000 +#define AR_XmitPower1_S 24 +#define AR_TxCtlRsvd91 0xc0000000 + +/* ds_ctl 10 */ +#define AR_TxCtlRsvd100 0x00ffffff +#define AR_XmitPower2 0x3f000000 +#define AR_XmitPower2_S 24 +#define AR_TxCtlRsvd101 0xc0000000 + +/* ds_ctl 11 */ +#define AR_TxCtlRsvd110 0x00ffffff +#define AR_XmitPower3 0x3f000000 +#define AR_XmitPower3_S 24 +#define AR_TxCtlRsvd111 0xc0000000 + +#endif +/************* + * TX Status * + *************/ + +/* ds_status0 */ +#define AR_TxRSSIAnt00 0x000000ff +#define AR_TxRSSIAnt00_S 0 +#define AR_TxRSSIAnt01 0x0000ff00 +#define AR_TxRSSIAnt01_S 8 +#define AR_TxRSSIAnt02 0x00ff0000 +#define AR_TxRSSIAnt02_S 16 +#define AR_TxStatusRsvd00 0x3f000000 +#define AR_TxBaStatus 0x40000000 +#define AR_TxStatusRsvd01 0x80000000 + +/* ds_status1 */ +#define AR_FrmXmitOK 0x00000001 +#define AR_ExcessiveRetries 0x00000002 +#define AR_FIFOUnderrun 0x00000004 +#define AR_Filtered 0x00000008 +#define AR_RTSFailCnt 0x000000f0 +#define AR_RTSFailCnt_S 4 +#define AR_DataFailCnt 0x00000f00 +#define AR_DataFailCnt_S 8 +#define AR_VirtRetryCnt 0x0000f000 +#define AR_VirtRetryCnt_S 12 +#define AR_TxDelimUnderrun 0x00010000 +#define AR_TxDataUnderrun 0x00020000 +#define AR_DescCfgErr 0x00040000 +#define AR_TxTimerExpired 0x00080000 +#define AR_TxStatusRsvd10 0xfff00000 + +/* ds_status2 */ +#define AR_SendTimestamp ds_txstatus2 + +/* ds_status3 */ +#define AR_BaBitmapLow ds_txstatus3 + +/* ds_status4 */ +#define AR_BaBitmapHigh ds_txstatus4 + +/* ds_status5 */ +#define AR_TxRSSIAnt10 0x000000ff +#define AR_TxRSSIAnt10_S 0 +#define AR_TxRSSIAnt11 0x0000ff00 +#define AR_TxRSSIAnt11_S 8 +#define AR_TxRSSIAnt12 0x00ff0000 +#define AR_TxRSSIAnt12_S 16 +#define AR_TxRSSICombined 0xff000000 +#define AR_TxRSSICombined_S 24 + +/* ds_status6 */ +#define AR_TxEVM0 ds_txstatus5 + +/* ds_status7 */ +#define AR_TxEVM1 ds_txstatus6 + +/* ds_status8 */ +#define AR_TxEVM2 ds_txstatus7 + +/* ds_status9 */ +#define AR_TxDone 0x00000001 +#define AR_SeqNum 0x00001ffe +#define AR_SeqNum_S 1 +#define AR_TxStatusRsvd80 0x0001e000 +#define AR_TxOpExceeded 0x00020000 +#define AR_TxStatusRsvd81 0x001c0000 +#define AR_FinalTxIdx 0x00600000 +#define AR_FinalTxIdx_S 21 +#define AR_TxStatusRsvd82 0x01800000 +#define AR_PowerMgmt 0x02000000 +#define AR_TxStatusRsvd83 0xfc000000 + +/*********** + * RX Desc * + ***********/ + +/* ds_ctl0 */ +#define AR_RxCTLRsvd00 0xffffffff + +/* ds_ctl1 */ +#define AR_BufLen 0x00000fff +#define AR_RxCtlRsvd00 0x00001000 +#define AR_RxIntrReq 0x00002000 +#define AR_RxCtlRsvd01 0xffffc000 + +/************* + * Rx Status * + *************/ + +/* ds_status0 */ +#define AR_RxRSSIAnt00 0x000000ff +#define AR_RxRSSIAnt00_S 0 +#define AR_RxRSSIAnt01 0x0000ff00 +#define AR_RxRSSIAnt01_S 8 +#define AR_RxRSSIAnt02 0x00ff0000 +#define AR_RxRSSIAnt02_S 16 +#define AR_RxRate 0xff000000 +#define AR_RxRate_S 24 +#define AR_RxStatusRsvd00 0xff000000 + +/* ds_status1 */ +#define AR_DataLen 0x00000fff +#define AR_RxMore 0x00001000 +#define AR_NumDelim 0x003fc000 +#define AR_NumDelim_S 14 +#define AR_RxStatusRsvd10 0xff800000 + +/* ds_status2 */ +#define AR_RcvTimestamp ds_rxstatus2 + +/* ds_status3 */ +#define AR_GI 0x00000001 +#define AR_2040 0x00000002 +#define AR_Parallel40 0x00000004 +#define AR_Parallel40_S 2 +#define AR_RxStatusRsvd30 0x000000f8 +#define AR_RxAntenna 0xffffff00 +#define AR_RxAntenna_S 8 + +/* ds_status4 */ +#define AR_RxRSSIAnt10 0x000000ff +#define AR_RxRSSIAnt10_S 0 +#define AR_RxRSSIAnt11 0x0000ff00 +#define AR_RxRSSIAnt11_S 8 +#define AR_RxRSSIAnt12 0x00ff0000 +#define AR_RxRSSIAnt12_S 16 +#define AR_RxRSSICombined 0xff000000 +#define AR_RxRSSICombined_S 24 + +/* ds_status5 */ +#define AR_RxEVM0 ds_rxstatus4 + +/* ds_status6 */ +#define AR_RxEVM1 ds_rxstatus5 + +/* ds_status7 */ +#define AR_RxEVM2 ds_rxstatus6 + +/* ds_status8 */ +#define AR_RxDone 0x00000001 +#define AR_RxFrameOK 0x00000002 +#define AR_CRCErr 0x00000004 +#define AR_DecryptCRCErr 0x00000008 +#define AR_PHYErr 0x00000010 +#define AR_MichaelErr 0x00000020 +#define AR_PreDelimCRCErr 0x00000040 +#define AR_RxStatusRsvd70 0x00000080 +#define AR_RxKeyIdxValid 0x00000100 +#define AR_KeyIdx 0x0000fe00 +#define AR_KeyIdx_S 9 +#define AR_PHYErrCode 0x0000ff00 +#define AR_PHYErrCode_S 8 +#define AR_RxMoreAggr 0x00010000 +#define AR_RxAggr 0x00020000 +#define AR_PostDelimCRCErr 0x00040000 +#define AR_RxStatusRsvd71 0x3ff80000 +#define AR_DecryptBusyErr 0x40000000 +#define AR_KeyMiss 0x80000000 + +#define RXSTATUS_RATE(ah, ads) (MS(ads->ds_rxstatus0, AR_RxRate)) +#define VALID_TX_RATES \ + ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)| \ + (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)| \ + (1<<0x1d)|(1<<0x18)|(1<<0x1c)) +#define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES) + +#define set11nTries(_series, _index) \ + (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) + +#define set11nRate(_series, _index) \ + (SM((_series)[_index].Rate, AR_XmitRate##_index)) + +#define set11nPktDurRTSCTS(_series, _index) \ + (SM((_series)[_index].PktDuration, AR_PacketDur##_index) |\ + ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\ + AR_RTSCTSQual##_index : 0)) + +#define set11nRateFlags(_series, _index) \ + ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \ + |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_GI##_index : 0) \ + |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_STBC##_index : 0) \ + |SM((_series)[_index].ChSel, AR_ChainSel##_index) + +#define set11nTxPower(_index, _txpower) \ + SM(_txpower, AR_XmitPower##_index) + +extern HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *, + HAL_BOOL IncTrigLevel); +extern a_uint32_t ar5416GetTxDP(struct ath_hal *ah, a_uint32_t q); +extern HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp); +extern HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q); +extern a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q); +extern HAL_BOOL ar5416StopTxDma(struct ath_hal *ah, a_uint32_t q); +extern HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah); +extern void ar5416GetTxIntrQueue(struct ath_hal *ah, a_uint32_t *); +extern HAL_BOOL ar5416SetGlobalTxTimeout(struct ath_hal *, a_uint32_t); +extern a_uint32_t ar5416GetGlobalTxTimeout(struct ath_hal *); +extern HAL_BOOL ar5416AbortTxDma(struct ath_hal *ah); +extern a_uint32_t ar5416GetRxDP(struct ath_hal *ath); +extern void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp); +extern void ar5416EnableReceive(struct ath_hal *ah); +extern HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah); +extern void ar5416StartPcuReceive(struct ath_hal *ah); +extern void ar5416StopPcuReceive(struct ath_hal *ah); +extern void ar5416AbortPcuReceive(struct ath_hal *ah); +extern void ar5416SetMulticastFilter(struct ath_hal *ah, + a_uint32_t filter0, a_uint32_t filter1); +extern HAL_BOOL ar5416ClrMulticastFilterIndex(struct ath_hal *, a_uint32_t ix); +extern HAL_BOOL ar5416SetMulticastFilterIndex(struct ath_hal *, a_uint32_t ix); +extern a_uint32_t ar5416GetRxFilter(struct ath_hal *ah); +extern void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits); +extern HAL_BOOL ar5416UpdateCTSForBursting_20(struct ath_hal *, struct ath_desc *, + struct ath_desc *,struct ath_desc *, struct ath_desc *, + a_uint32_t, a_uint32_t); +extern HAL_BOOL ar5416SetupTxDesc_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t pktLen, a_uint32_t hdrLen, HAL_PKT_TYPE type, a_uint32_t txPower, + a_uint32_t txRate0, a_uint32_t txTries0, + a_uint32_t keyIx, a_uint32_t antMode, a_uint32_t flags, + a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration, + a_uint32_t compicvLen, a_uint32_t compivLen, a_uint32_t comp); +extern HAL_BOOL ar5416FillTxDesc_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, + const struct ath_desc *ds0); +extern HAL_BOOL ar5416FillKeyTxDesc_20(struct ath_hal *ah, struct ath_desc *,HAL_KEY_TYPE); +extern HAL_STATUS ar5416ProcTxDesc_20(struct ath_hal *ah, struct ath_desc *); + +extern void ar5416IntrReqTxDesc_20(struct ath_hal *ah, struct ath_desc *ds); +extern void ar5416Set11nTxDesc_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t pktLen, HAL_PKT_TYPE type, a_uint32_t txPower, + a_uint32_t keyIx, HAL_KEY_TYPE keyType, a_uint32_t flags); +extern void ar5416Set11nRateScenario_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t durUpdateEn, a_uint32_t rtsctsRate, a_uint32_t rtsctsDuration, HAL_11N_RATE_SERIES series[], + a_uint32_t nseries, a_uint32_t flags); +extern void ar5416Set11nAggrFirst_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t aggrLen, a_uint32_t numDelims); +extern void ar5416Set11nAggrMiddle_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t numDelims); +extern void ar5416Set11nAggrLast_20(struct ath_hal *ah, struct ath_desc *ds); +extern void ar5416Clr11nAggr_20(struct ath_hal *ah, struct ath_desc *ds); +extern void ar5416Set11nBurstDuration_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t burstDuration); +extern void ar5416Set11nVirtualMoreFrag_20(struct ath_hal *ah, struct ath_desc *ds, + a_uint32_t vmf); +extern HAL_BOOL ar5416SetupRxDesc_20(struct ath_hal *, + struct ath_desc *, a_uint32_t size, a_uint32_t flags); +extern HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, + struct ath_desc *, a_uint32_t, + struct ath_desc *, + struct ath_rx_status *); +#endif diff --git a/target_firmware/wlan/ar5416phy.h b/target_firmware/wlan/ar5416phy.h new file mode 100755 index 0000000..5a89821 --- /dev/null +++ b/target_firmware/wlan/ar5416phy.h @@ -0,0 +1,425 @@ +/* + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * Copyright (c) 2002-2005 Atheros Communications, Inc. + * All rights reserved. + * + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/hal/main/ar5416/ar5416phy.h#1 $ + */ +#ifndef _DEV_ATH_AR5416PHY_H_ +#define _DEV_ATH_AR5416PHY_H_ + +/* PHY registers */ +#define AR_PHY_BASE 0x9800 /* base address of phy regs */ +#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) + +#define AR_PHY_TEST 0x9800 /* PHY test control */ +#define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */ +#define RFSILENT_BB 0x00002000 /* shush bb */ + +/* TX99_11N_CHANGE begin */ +#define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */ +#define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */ +#define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */ +#define AR_PHY_TESTCTRL_TXSRC_ALT_S 7 +#define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */ +#define AR_PHY_TESTCTRL_TXSRC_SRC_S 1 +/* TX99_11N_CHANGE end */ + + +#define AR_PHY_TURBO 0x9804 /* frame control register */ +#define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */ +#define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */ +#define AR_PHY_FC_DYN2040_EN 0x00000004 /* Enable dyn 20/40 mode */ +#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */ +#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz)*/ +#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */ +#define AR_PHY_FC_HT_EN 0x00000040 /* ht enable */ +#define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ +#define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ +#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ + +#define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */ +#define AR_PHY_TIMING2_USE_FORCE 0x00001000 +#define AR_PHY_TIMING2_FORCE_VAL 0x00000fff + +#define AR_PHY_TIMING3 0x9814 /* Timing control 3 */ +#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 +#define AR_PHY_TIMING3_DSC_MAN_S 17 +#define AR_PHY_TIMING3_DSC_EXP 0x0001E000 +#define AR_PHY_TIMING3_DSC_EXP_S 13 + +#define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */ +#define AR_PHY_CHIP_ID_REV_0 0x80 /* 5416 Rev 0 (owl 1.0) BB */ +#define AR_PHY_CHIP_ID_REV_1 0x81 /* 5416 Rev 1 (owl 2.0) BB */ +#define AR_PHY_CHIP_ID_SOWL_REV_0 0xb0 /* 9160 Rev 0 (sowl 1.0) BB */ + +#define AR_PHY_ACTIVE 0x981C /* activation register */ +#define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */ +#define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */ + +#define AR_PHY_RF_CTL2 0x9824 +#define AR_PHY_TX_END_DATA_START 0x000000FF +#define AR_PHY_TX_END_DATA_START_S 0 +#define AR_PHY_TX_END_PA_ON 0x0000FF00 +#define AR_PHY_TX_END_PA_ON_S 8 + + +#define AR_PHY_RF_CTL3 0x9828 +#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 +#define AR_PHY_TX_END_TO_A2_RX_ON_S 16 + +#define AR_PHY_ADC_CTL 0x982C +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003 +#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 +#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 +#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 /* BB Rev 4.2+ only */ +#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 /* BB Rev 4.2+ only */ +#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000 +#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16 + +#define AR_PHY_ADC_SERIAL_CTL 0x9830 +#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 +#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 + +#define AR_PHY_RF_CTL4 0x9834 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 +#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 +#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 +#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF +#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 + +/* TX99_11N_CHANGE begin */ +#define AR_PHY_BB_XP_PA_CTL 0x9838 +#define AR_PHY_BB_XPAA_ACTIVE_HIGH 0x00000001 +#define AR_PHY_BB_XPAB_ACTIVE_HIGH 0x00000002 +#define AR_PHY_BB_XPAB_ACTIVE_HIGH_S 1 + +#define AR_PHY_TSTDAC_CONST 0x983C +#define AR_PHY_TSTDAC_CONST_Q 0x0003FE00 +#define AR_PHY_TSTDAC_CONST_Q_S 9 +#define AR_PHY_TSTDAC_CONST_I 0x000001FF +/* TX99_11N_CHANGE end */ + +#define AR_PHY_SETTLING 0x9844 +#define AR_PHY_SETTLING_SWITCH 0x00003F80 +#define AR_PHY_SETTLING_SWITCH_S 7 + +#define AR_PHY_RXGAIN 0x9848 +#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 +#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 +#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 +#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 + +#define AR_PHY_DESIRED_SZ 0x9850 +#define AR_PHY_DESIRED_SZ_ADC 0x000000FF +#define AR_PHY_DESIRED_SZ_ADC_S 0 +#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 +#define AR_PHY_DESIRED_SZ_PGA_S 8 +#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 +#define AR_PHY_DESIRED_SZ_TOT_DES_S 20 + +#define AR_PHY_FIND_SIG 0x9858 +#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 +#define AR_PHY_FIND_SIG_FIRSTEP_S 12 +#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 +#define AR_PHY_FIND_SIG_FIRPWR_S 18 + +#define AR_PHY_AGC_CTL1 0x985C +#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80 +#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 +#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000 +#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15 + +#define AR_PHY_AGC_CONTROL 0x9860 /* chip calibration and noise floor setting */ +#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */ +#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calculation */ + +#define AR_PHY_CCA 0x9864 +#define AR_PHY_MINCCA_PWR 0x0FF80000 +#define AR_PHY_MINCCA_PWR_S 19 +#define AR_PHY_CCA_THRESH62 0x0007F000 +#define AR_PHY_CCA_THRESH62_S 12 + +#define AR_PHY_SFCORR_LOW 0x986C +#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 +#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 +#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 +#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 + +#define AR_PHY_SFCORR 0x9868 +#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F +#define AR_PHY_SFCORR_M2COUNT_THR_S 0 +#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 +#define AR_PHY_SFCORR_M1_THRESH_S 17 +#define AR_PHY_SFCORR_M2_THRESH 0x7F000000 +#define AR_PHY_SFCORR_M2_THRESH_S 24 + +#define AR_PHY_SLEEP_CTR_CONTROL 0x9870 +#define AR_PHY_SLEEP_CTR_LIMIT 0x9874 +#define AR_PHY_SLEEP_SCAL 0x9878 + +#define AR_PHY_PLL_CTL 0x987c /* PLL control register */ +#define AR_PHY_PLL_CTL_40 0xaa /* 40 MHz */ +#define AR_PHY_PLL_CTL_40_5413 0x04 +#define AR_PHY_PLL_CTL_44 0xab /* 44 MHz for 11b, 11g */ +#define AR_PHY_PLL_CTL_44_2133 0xeb /* 44 MHz for 11b, 11g */ +#define AR_PHY_PLL_CTL_40_2133 0xea /* 40 MHz for 11a, turbos */ + +#define AR_PHY_RX_DELAY 0x9914 /* analog pow-on time (100ns) */ +#define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */ + +#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) /* timing control */ +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */ +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 /* shift for Q_COFF */ +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 /* Mask for sin_theta for i correction */ +#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */ +#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 /* enable IQ correction */ +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 /* Mask for max number of samples (logarithmic) */ +#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ +#define AR_PHY_TIMING_CTRL4_DO_IQCAL 0x10000 /* perform IQ calibration */ + +#define AR_PHY_TIMING5 0x9924 +#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE +#define AR_PHY_TIMING5_CYCPWR_THR1_S 1 + +#define AR_PHY_POWER_TX_RATE1 0x9934 +#define AR_PHY_POWER_TX_RATE2 0x9938 +#define AR_PHY_POWER_TX_RATE_MAX 0x993c +#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 + +#define AR_PHY_FRAME_CTL 0x9944 +#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038 +#define AR_PHY_FRAME_CTL_TX_CLIP_S 3 + +#define AR_PHY_TXPWRADJ 0x994C /* BB Rev 4.2+ only */ +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0 +#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000 +#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18 + +#define AR_PHY_RADAR_0 0x9954 /* radar detection settings */ +#define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */ +#define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */ +#define AR_PHY_RADAR_0_INBAND_S 1 +#define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */ +#define AR_PHY_RADAR_0_PRSSI_S 6 +#define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */ +#define AR_PHY_RADAR_0_HEIGHT_S 12 +#define AR_PHY_RADAR_0_RRSSI 0x00FC0000 /* Radar rssi threshold */ +#define AR_PHY_RADAR_0_RRSSI_S 18 +#define AR_PHY_RADAR_0_FIRPWR 0x7F000000 /* Radar firpwr threshold */ +#define AR_PHY_RADAR_0_FIRPWR_S 24 + +#define AR_PHY_RADAR_1 0x9958 /* AR5413+ radar settigns */ +#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 /* enable to check radar relative power */ +#define AR_PHY_RADAR_1_USE_FIR128 0x00400000 /* enable to use the average inband power + * measured over 128 cycles + */ +#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 /* relative pwr thresh */ +#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 +#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 /* Enable to block radar check if weak + * OFDM sig or pkt is immediately after + * tx to rx transition + */ +#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 /* Enable to use max rssi */ +#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 /* Enable to use pulse relative step check */ +#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 /* Pulse relative step threshold */ +#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 +#define AR_PHY_RADAR_1_MAXLEN 0x000000FF /* Max length of radar pulse */ +#define AR_PHY_RADAR_1_MAXLEN_S 0 + +#define AR_PHY_SWITCH_CHAIN_0 0x9960 +#define AR_PHY_SWITCH_COM 0x9964 + +#define AR_PHY_SIGMA_DELTA 0x996C /* AR5312 only */ +#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 +#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0 +#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8 +#define AR_PHY_SIGMA_DELTA_FILT2_S 3 +#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00 +#define AR_PHY_SIGMA_DELTA_FILT1_S 8 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000 +#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13 + +#define AR_PHY_RESTART 0x9970 /* restart */ +#define AR_PHY_RESTART_DIV_GC 0x001C0000 /* bb_ant_fast_div_gc_limit */ +#define AR_PHY_RESTART_DIV_GC_S 18 + +#define AR_PHY_RFBUS_REQ 0x997C +#define AR_PHY_RFBUS_REQ_EN 0x00000001 + +#define AR_PHY_RX_CHAINMASK 0x99a4 + +#define AR_PHY_EXT_CCA 0x99bc +#define AR_PHY_EXT_CCA_THRESH62 0x007F0000 // [22:16] not replicated +#define AR_PHY_EXT_CCA_THRESH62_S 16 +#define AR_PHY_EXT_MINCCA_PWR 0xFF800000 +#define AR_PHY_EXT_MINCCA_PWR_S 23 + +#define AR_PHY_HALFGI 0x99D0 /* Timing control 3 */ +#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 +#define AR_PHY_HALFGI_DSC_MAN_S 4 +#define AR_PHY_HALFGI_DSC_EXP 0x0000000F +#define AR_PHY_HALFGI_DSC_EXP_S 0 + +#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 + +#define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */ +#define AR_PHY_REFCLKDLY 0x99f4 +#define AR_PHY_REFCLKPD 0x99f8 + +#define AR_PHY_CALMODE 0x99f0 +/* PHY IQ calibration results */ +#define AR_PHY_IQCAL_RES_PWR_MEAS_I(_i) (0x9c10 + ((_i) << 12)) /* power measurement for I */ +#define AR_PHY_IQCAL_RES_PWR_MEAS_Q(_i) (0x9c14 + ((_i) << 12)) /* power measurement for Q */ +#define AR_PHY_IQCAL_RES_IQ_CORR_MEAS(_i) (0x9c18 + ((_i) << 12)) /* IQ correlation measurement */ + +#define AR_PHY_CURRENT_RSSI 0x9c1c /* rssi of current frame rx'd */ + +#define AR_PHY_RFBUS_GRANT 0x9C20 +#define AR_PHY_RFBUS_GRANT_EN 0x00000001 + +#define AR_PHY_MODE 0xA200 /* Mode register */ +#define AR_PHY_MODE_AR2133 0x08 /* AR2133 */ +#define AR_PHY_MODE_AR5111 0x00 /* AR5111/AR2111 */ +#define AR_PHY_MODE_AR5112 0x08 /* AR5112*/ +#define AR_PHY_MODE_DYNAMIC 0x04 /* dynamic CCK/OFDM mode */ +#define AR_PHY_MODE_RF2GHZ 0x02 /* 2.4 GHz */ +#define AR_PHY_MODE_RF5GHZ 0x00 /* 5 GHz */ +#define AR_PHY_MODE_CCK 0x01 /* CCK */ +#define AR_PHY_MODE_OFDM 0x00 /* OFDM */ + +#define AR_PHY_CCK_TX_CTRL 0xA204 +#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 + +#define AR_PHY_CCK_DETECT 0xA208 +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F +#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 // [12:6] settling time for antenna switch +#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 +#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 + +#define AR_PHY_GAIN_2GHZ 0xA20C +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000 +#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 +#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F +#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 + +#define AR_PHY_CCK_RXCTRL4 0xA21C +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000 +#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 + +#define AR_PHY_DAG_CTRLCCK 0xA228 +#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 /* BB Rev 4.2+ only */ +#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 /* BB Rev 4.2+ only */ +#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 /* BB Rev 4.2+ only */ + +#define AR_PHY_POWER_TX_RATE3 0xA234 +#define AR_PHY_POWER_TX_RATE4 0xA238 + +#define AR_PHY_SCRM_SEQ_XR 0xA23C +#define AR_PHY_HEADER_DETECT_XR 0xA240 +#define AR_PHY_CHIRP_DETECTED_XR 0xA244 +#define AR_PHY_BLUETOOTH 0xA254 + +#define AR_PHY_TPCRG1 0xA258 /* ar2413 power control */ +#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 +#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 + +#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 +#define AR_PHY_TPCRG1_PD_GAIN_1_S 16 +#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 +#define AR_PHY_TPCRG1_PD_GAIN_2_S 18 +#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 +#define AR_PHY_TPCRG1_PD_GAIN_3_S 20 +// + +#define AR_PHY_ANALOG_SWAP 0xa268 +#define AR_PHY_SWAP_ALT_CHAIN 0x00000040 + +#define AR_PHY_TPCRG5 0xA26C /* ar2413 power control */ +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F +#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 +#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 + +#define AR_PHY_POWER_TX_RATE5 0xA38C +#define AR_PHY_POWER_TX_RATE6 0xA390 + +#define AR_PHY_CAL_CHAINMASK 0xA39C + +#define AR_PHY_POWER_TX_SUB 0xA3C8 +#define AR_PHY_POWER_TX_RATE7 0xA3CC +#define AR_PHY_POWER_TX_RATE8 0xA3D0 +#define AR_PHY_POWER_TX_RATE9 0xA3D4 + +#define AR_PHY_CH1_CCA 0xa864 +#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000 +#define AR_PHY_CH1_MINCCA_PWR_S 19 + +#define AR_PHY_CH2_CCA 0xb864 +#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000 +#define AR_PHY_CH2_MINCCA_PWR_S 19 + +#define AR_PHY_CH1_EXT_CCA 0xa9bc +#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 +#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 + +#define AR_PHY_CH2_EXT_CCA 0xb9bc +#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 +#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 + + +#ifdef MAGPIE_MERLIN + +#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 + +#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* Enable noise floor calibration to happen */ +#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* Don't update noise floor automatically */ + +#define AR9280_PHY_MINCCA_PWR 0x1FF00000 +#define AR9280_PHY_MINCCA_PWR_S 20 +#define AR9280_PHY_CCA_THRESH62 0x000FF000 +#define AR9280_PHY_CCA_THRESH62_S 12 + +#define AR_PHY_CCA_MAX_GOOD_VALUE -85 +#define AR_PHY_CCA_MAX_HIGH_VALUE -62 +#define AR_PHY_CCA_MIN_BAD_VALUE -121 + +#define AR_PHY_SYNTH_CONTROL 0x9874 +#define AR9280_PHY_CURRENT_RSSI 0x9c3c + +#define AR9280_PHY_CURRENT_RSSI 0x9c3c + +#define AR_PHY_XPA_CFG 0xA3D8 +#define AR_PHY_FORCE_XPA_CFG 0x000000001 +#define AR_PHY_FORCE_XPA_CFG_S 0 + +#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000 +#define AR9280_PHY_CH1_MINCCA_PWR_S 20 + +#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 +#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16 + +#endif + + + +#endif /* _DEV_ATH_AR5416PHY_H_ */ diff --git a/target_firmware/wlan/ar5416reg.h b/target_firmware/wlan/ar5416reg.h new file mode 100755 index 0000000..39baade --- /dev/null +++ b/target_firmware/wlan/ar5416reg.h @@ -0,0 +1,1561 @@ +#ifndef _DEV_ATH_AR5416REG_H +#define _DEV_ATH_AR5416REG_H + +/* DMA Control and Interrupt Registers */ +#define AR_CR 0x0008 // MAC Control Register - only write values of 1 have effect +#define AR_CR_RXE 0x00000004 // Receive enable +#define AR_CR_RXD 0x00000020 // Receive disable +#define AR_CR_SWI 0x00000040 // One-shot software interrupt + +#define AR_RXDP 0x000C // MAC receive queue descriptor pointer + +#define AR_CFG 0x0014 // MAC configuration and status register +#define AR_CFG_SWTD 0x00000001 // byteswap tx descriptor words +#define AR_CFG_SWTB 0x00000002 // byteswap tx data buffer words +#define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words +#define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words +#define AR_CFG_SWRG 0x00000010 // byteswap register access data words +#define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc) +#define AR_CFG_PHOK 0x00000100 // PHY OK status +#define AR_CFG_CLK_GATE_DIS 0x00000400 // Clock gating disable +#define AR_CFG_EEBS 0x00000200 // EEPROM busy +#define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue full threshold +#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 // Shift for PCI core master request queue full threshold + +#define AR_MIRT 0x0020 // Mac Interrupt rate threshold register +#define AR_MIRT_VAL 0x0000ffff // in uS +#define AR_MIRT_VAL_S 16 + +#define AR_IER 0x0024 // MAC Interrupt enable register +#define AR_IER_ENABLE 0x00000001 // Global interrupt enable +#define AR_IER_DISABLE 0x00000000 // Global interrupt disable + +#define AR_TIMT 0x0028 // Mac Tx Interrupt mitigation threshold +#define AR_TIMT_LAST 0x0000ffff // Last packet threshold +#define AR_TIMT_LAST_S 0 +#define AR_TIMT_FIRST 0xffff0000 // First packet threshold +#define AR_TIMT_FIRST_S 16 + +#define AR_RIMT 0x002C // Mac Rx Interrupt mitigation threshold +#define AR_RIMT_LAST 0x0000ffff // Last packet threshold +#define AR_RIMT_LAST_S 0 +#define AR_RIMT_FIRST 0xffff0000 // First packet threshold +#define AR_RIMT_FIRST_S 16 + +#define AR_DMASIZE_4B 0x00000000 // DMA size 4 bytes (TXCFG + RXCFG) +#define AR_DMASIZE_8B 0x00000001 // DMA size 8 bytes +#define AR_DMASIZE_16B 0x00000002 // DMA size 16 bytes +#define AR_DMASIZE_32B 0x00000003 // DMA size 32 bytes +#define AR_DMASIZE_64B 0x00000004 // DMA size 64 bytes +#define AR_DMASIZE_128B 0x00000005 // DMA size 128 bytes +#define AR_DMASIZE_256B 0x00000006 // DMA size 256 bytes +#define AR_DMASIZE_512B 0x00000007 // DMA size 512 bytes + +#define AR_TXCFG 0x0030 // MAC tx DMA size config register +#define AR_TXCFG_DMASZ_MASK 0x00000003 +#define AR_TXCFG_DMASZ_4B 0 +#define AR_TXCFG_DMASZ_8B 1 +#define AR_TXCFG_DMASZ_16B 2 +#define AR_TXCFG_DMASZ_32B 3 +#define AR_TXCFG_DMASZ_64B 4 +#define AR_TXCFG_DMASZ_128B 5 +#define AR_TXCFG_DMASZ_256B 6 +#define AR_TXCFG_DMASZ_512B 7 +#define AR_FTRIG 0x000003F0 // Mask for Frame trigger level +#define AR_FTRIG_S 4 // Shift for Frame trigger level +#define AR_FTRIG_IMMED 0x00000000 // bytes in PCU TX FIFO before air +#define AR_FTRIG_64B 0x00000010 // default +#define AR_FTRIG_128B 0x00000020 +#define AR_FTRIG_192B 0x00000030 +#define AR_FTRIG_256B 0x00000040 // 5 bits total +#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 + +#define AR_RXCFG 0x0034 // MAC rx DMA size config register +#define AR_RXCFG_CHIRP 0x00000008 // Only double chirps +#define AR_RXCFG_ZLFDMA 0x00000010 // Enable DMA of zero-length frame +#define AR_RXCFG_DMASZ_MASK 0x00000007 +#define AR_RXCFG_DMASZ_4B 0 +#define AR_RXCFG_DMASZ_8B 1 +#define AR_RXCFG_DMASZ_16B 2 +#define AR_RXCFG_DMASZ_32B 3 +#define AR_RXCFG_DMASZ_64B 4 +#define AR_RXCFG_DMASZ_128B 5 +#define AR_RXCFG_DMASZ_256B 6 +#define AR_RXCFG_DMASZ_512B 7 + +#define AR_MIBC 0x0040 // MAC MIB control register +#define AR_MIBC_COW 0x00000001 // counter overflow warning +#define AR_MIBC_FMC 0x00000002 // freeze MIB counters +#define AR_MIBC_CMC 0x00000004 // clear MIB counters +#define AR_MIBC_MCS 0x00000008 // MIB counter strobe increment all + +#define AR_TOPS 0x0044 // MAC timeout prescale count +#define AR_TOPS_MASK 0x0000FFFF // Mask for timeout prescale + +#define AR_RXNPTO 0x0048 // MAC no frame received timeout +#define AR_RXNPTO_MASK 0x000003FF // Mask for no frame received timeout + +#define AR_TXNPTO 0x004C // MAC no frame trasmitted timeout +#define AR_TXNPTO_MASK 0x000003FF // Mask for no frame transmitted timeout +#define AR_TXNPTO_QCU_MASK 0x000FFC00 // Mask indicating the set of QCUs + // for which frame completions will cause + // a reset of the no frame transmitted timeout + +#define AR_RPGTO 0x0050 // MAC receive frame gap timeout +#define AR_RPGTO_MASK 0x000003FF // Mask for receive frame gap timeout + +#define AR_RPCNT 0x0054 // MAC receive frame count limit +#define AR_RPCNT_MASK 0x0000001F // Mask for receive frame count limit + +#define AR_MACMISC 0x0058 // MAC miscellaneous control/status register +#define AR_MACMISC_PCI_EXT_FORCE 0x00000010 //force msb to 10 to ahb +#define AR_MACMISC_DMA_OBS 0x000001E0 // Mask for DMA observation bus mux select +#define AR_MACMISC_DMA_OBS_S 5 // Shift for DMA observation bus mux select +#define AR_MACMISC_MISC_OBS 0x00000E00 // Mask for MISC observation bus mux select +#define AR_MACMISC_MISC_OBS_S 9 // Shift for MISC observation bus mux select +#define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 // Mask for MAC observation bus mux select (lsb) +#define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 // Shift for MAC observation bus mux select (lsb) +#define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 // Mask for MAC observation bus mux select (msb) +#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 // Shift for MAC observation bus mux select (msb) + +#define AR_GTXTO 0x0064 // MAC global transmit timeout +#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) +#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) +#define AR_GTXTO_TIMEOUT_LIMIT_S 16 // Shift for timeout limit + +#define AR_GTTM 0x0068 // MAC global transmit timeout mode +#define AR_GTTM_USEC 0x00000001 // usec strobe +#define AR_GTTM_IGNORE_IDLE 0x00000002 // ignore channel idle +#define AR_GTTM_RESET_IDLE 0x00000004 // reset counter on channel idle low +#define AR_GTTM_CST_USEC 0x00000008 // CST usec strobe + +#define AR_CST 0x006C // MAC carrier sense timeout +#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF // Mask for timeout counter (in TUs) +#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 // Mask for timeout limit (in TUs) +#define AR_CST_TIMEOUT_LIMIT_S 16 // Shift for timeout limit + +#define AR_SREV_VERSION_HOWL 0x014 + +#define AR_SREV_5416_V20_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_20_OR_LATER(_ah)) +#define AR_SREV_5416_V22_OR_LATER(_ah) (AR_SREV_HOWL((_ah)) || AR_SREV_OWL_22_OR_LATER(_ah)) + +#ifdef AR5416_EMULATION +/* XXX - AR5416 Emulation only + * XXX - TODO - remove when emulation complete + */ +#define AR_EMU 0x0070 // MAC - special emulation only register +#define AR_EMU_RATETHROT 0x00000001 // rate throttling (enabled = 1) +#define AR_EMU_CTL 0x00000002 // ctl channel busy (busy = 1) +#define AR_EMU_EXT 0x00000004 // ext channel busy (busy = 1) +#define AR_EMU_HALF_RATE 0x00000080 // run at half-rate for encryption +#define AR_EMU_VERSION 0xFFFFFF00 // Mask for version (read only) +#define AR_EMU_VERSION_S 8 // Shift for timeout limit + +#endif //AR5416_EMULATION + +/* Interrupt Status Registers */ +#define AR_ISR 0x0080 // MAC Primary interrupt status register +#define AR_ISR_RXOK 0x00000001 // At least one frame received sans errors +#define AR_ISR_RXDESC 0x00000002 // Receive interrupt request +#define AR_ISR_RXERR 0x00000004 // Receive error interrupt +#define AR_ISR_RXNOPKT 0x00000008 // No frame received within timeout clock +#define AR_ISR_RXEOL 0x00000010 // Received descriptor empty interrupt +#define AR_ISR_RXORN 0x00000020 // Receive FIFO overrun interrupt +#define AR_ISR_TXOK 0x00000040 // Transmit okay interrupt +#define AR_ISR_TXDESC 0x00000080 // Transmit interrupt request +#define AR_ISR_TXERR 0x00000100 // Transmit error interrupt +#define AR_ISR_TXNOPKT 0x00000200 // No frame transmitted interrupt +#define AR_ISR_TXEOL 0x00000400 // Transmit descriptor empty interrupt +#define AR_ISR_TXURN 0x00000800 // Transmit FIFO underrun interrupt +#define AR_ISR_MIB 0x00001000 // MIB interrupt - see MIBC +#define AR_ISR_SWI 0x00002000 // Software interrupt +#define AR_ISR_RXPHY 0x00004000 // PHY receive error interrupt +#define AR_ISR_RXKCM 0x00008000 // Key-cache miss interrupt +#define AR_ISR_SWBA 0x00010000 // Software beacon alert interrupt +#define AR_ISR_BRSSI 0x00020000 // Beacon threshold interrupt +#define AR_ISR_BMISS 0x00040000 // Beacon missed interrupt +#define AR_ISR_BNR 0x00100000 // Beacon not ready interrupt +#define AR_ISR_RXCHIRP 0x00200000 // Phy received a 'chirp' +#define AR_ISR_BCNMISC 0x00800000 // In venice 'or' of TIM CABEND DTIMSYNC BCNTO CABTO DTIM bits from ISR_S2 +#define AR_ISR_TIM 0x00800000 // TIM interrupt +#define AR_ISR_QCBROVF 0x02000000 // QCU CBR overflow interrupt +#define AR_ISR_QCBRURN 0x04000000 // QCU CBR underrun interrupt +#define AR_ISR_QTRIG 0x08000000 // QCU scheduling trigger interrupt +#define AR_ISR_GENTMR 0x10000000 // OR of generic timer bits in ISR 5 + +#ifdef AR5416_INT_MITIGATION +#define AR_ISR_TXMINTR 0x00080000 // Maximum interrupt transmit rate +#define AR_ISR_RXMINTR 0x01000000 // Maximum interrupt receive rate +#define AR_ISR_TXINTM 0x40000000 // Tx interrupt after mitigation +#define AR_ISR_RXINTM 0x80000000 // Rx interrupt after mitigation +#endif + +#define AR_ISR_S0 0x0084 // MAC Secondary interrupt status register 0 +#define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) +#define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) +#define AR_ISR_S0_QCU_TXDESC 0x03FF0000 // Mask for TXDESC (QCU 0-9) +#define AR_ISR_S0_QCU_TXDESC_S 16 // Shift for TXDESC (QCU 0-9) + +#define AR_ISR_S1 0x0088 // MAC Secondary interrupt status register 1 +#define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) +#define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) +#define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) +#define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) + +#define AR_ISR_S2 0x008c // MAC Secondary interrupt status register 2 +#define AR_ISR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9) +#define AR_ISR_S2_CST 0x00400000 // Carrier sense timeout +#define AR_ISR_S2_GTT 0x00800000 // Global transmit timeout +#define AR_ISR_S2_TIM 0x01000000 // TIM +#define AR_ISR_S2_CABEND 0x02000000 // CABEND +#define AR_ISR_S2_DTIMSYNC 0x04000000 // DTIMSYNC +#define AR_ISR_S2_BCNTO 0x08000000 // BCNTO +#define AR_ISR_S2_CABTO 0x10000000 // CABTO +#define AR_ISR_S2_DTIM 0x20000000 // DTIM +#define AR_ISR_S2_TSFOOR 0x40000000 // Rx TSF out of range +#define AR_ISR_S2_TBTT_TIME 0x80000000 // TBTT-referenced timer + +#define AR_ISR_S3 0x0090 // MAC Secondary interrupt status register 3 +#define AR_ISR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9) +#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9) + +#define AR_ISR_S4 0x0094 // MAC Secondary interrupt status register 4 +#define AR_ISR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9) +#define AR_ISR_S4_RESV0 0xFFFFFC00 // Reserved + +#define AR_ISR_S5 0x0098 // MAC Secondary interrupt status register 5 +#define AR_ISR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7) +#define AR_ISR_S5_TIMER_THRESH 0x0007FE00 // Mask for timer threshold(0-7) +#define AR_ISR_S5_GENTIMER7 0x80 //Timer 7 does not have a dedicated function + +/* Interrupt Mask Registers */ +#define AR_IMR 0x00a0 // MAC Primary interrupt mask register +#define AR_IMR_RXOK 0x00000001 // At least one frame received sans errors +#define AR_IMR_RXDESC 0x00000002 // Receive interrupt request +#define AR_IMR_RXERR 0x00000004 // Receive error interrupt +#define AR_IMR_RXNOPKT 0x00000008 // No frame received within timeout clock +#define AR_IMR_RXEOL 0x00000010 // Received descriptor empty interrupt +#define AR_IMR_RXORN 0x00000020 // Receive FIFO overrun interrupt +#define AR_IMR_TXOK 0x00000040 // Transmit okay interrupt +#define AR_IMR_TXDESC 0x00000080 // Transmit interrupt request +#define AR_IMR_TXERR 0x00000100 // Transmit error interrupt +#define AR_IMR_TXNOPKT 0x00000200 // No frame transmitted interrupt +#define AR_IMR_TXEOL 0x00000400 // Transmit descriptor empty interrupt +#define AR_IMR_TXURN 0x00000800 // Transmit FIFO underrun interrupt +#define AR_IMR_MIB 0x00001000 // MIB interrupt - see MIBC +#define AR_IMR_SWI 0x00002000 // Software interrupt +#define AR_IMR_RXPHY 0x00004000 // PHY receive error interrupt +#define AR_IMR_RXKCM 0x00008000 // Key-cache miss interrupt +#define AR_IMR_SWBA 0x00010000 // Software beacon alert interrupt +#define AR_IMR_BRSSI 0x00020000 // Beacon threshold interrupt +#define AR_IMR_BMISS 0x00040000 // Beacon missed interrupt +#define AR_IMR_BNR 0x00100000 // BNR interrupt +#define AR_IMR_RXCHIRP 0x00200000 // RXCHIRP interrupt +#define AR_IMR_BCNMISC 0x00800000 // Venice: BCNMISC +#define AR_IMR_TIM 0x00800000 // TIM interrupt +#define AR_IMR_QCBROVF 0x02000000 // QCU CBR overflow interrupt +#define AR_IMR_QCBRURN 0x04000000 // QCU CBR underrun interrupt +#define AR_IMR_QTRIG 0x08000000 // QCU scheduling trigger interrupt +#define AR_IMR_GENTMR 0x10000000 // Generic timer interrupt + +#ifdef AR5416_INT_MITIGATION +#define AR_IMR_TXMINTR 0x00080000 // Maximum interrupt transmit rate +#define AR_IMR_RXMINTR 0x01000000 // Maximum interrupt receive rate +#define AR_IMR_TXINTM 0x40000000 // Tx interrupt after mitigation +#define AR_IMR_RXINTM 0x80000000 // Rx interrupt after mitigation +#endif + +#define AR_IMR_S0 0x00a4 // MAC Secondary interrupt mask register 0 +#define AR_IMR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) +#define AR_IMR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) +#define AR_IMR_S0_QCU_TXDESC 0x03FF0000 // Mask for TXDESC (QCU 0-9) +#define AR_IMR_S0_QCU_TXDESC_S 16 // Shift for TXDESC (QCU 0-9) + +#define AR_IMR_S1 0x00a8 // MAC Secondary interrupt mask register 1 +#define AR_IMR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) +#define AR_IMR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) +#define AR_IMR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) +#define AR_IMR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) + +#define AR_IMR_S2 0x00ac // MAC Secondary interrupt mask register 2 +#define AR_IMR_S2_QCU_TXURN 0x000003FF // Mask for TXURN (QCU 0-9) +#define AR_IMR_S2_QCU_TXURN_S 0 // Shift for TXURN (QCU 0-9) +#define AR_IMR_S2_CST 0x00400000 // Carrier sense timeout +#define AR_IMR_S2_GTT 0x00800000 // Global transmit timeout +#define AR_IMR_S2_TIM 0x01000000 // TIM +#define AR_IMR_S2_CABEND 0x02000000 // CABEND +#define AR_IMR_S2_DTIMSYNC 0x04000000 // DTIMSYNC +#define AR_IMR_S2_BCNTO 0x08000000 // BCNTO +#define AR_IMR_S2_CABTO 0x10000000 // CABTO +#define AR_IMR_S2_DTIM 0x20000000 // DTIM +#define AR_IMR_S2_TSFOOR 0x40000000 // TSF overrun + +#define AR_IMR_S3 0x00b0 // MAC Secondary interrupt mask register 3 +#define AR_IMR_S3_QCU_QCBROVF 0x000003FF // Mask for QCBROVF (QCU 0-9) +#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 // Mask for QCBRURN (QCU 0-9) +#define AR_IMR_S3_QCU_QCBRURN_S 16 // Shift for QCBRURN (QCU 0-9) + +#define AR_IMR_S4 0x00b4 // MAC Secondary interrupt mask register 4 +#define AR_IMR_S4_QCU_QTRIG 0x000003FF // Mask for QTRIG (QCU 0-9) +#define AR_IMR_S4_RESV0 0xFFFFFC00 // Reserved + +#define AR_IMR_S5 0x00b8 // MAC Secondary interrupt mask register 5 +#define AR_IMR_S5_TIMER_TRIG 0x000000FF // Mask for timer trigger (0-7) +#define AR_IMR_S5_TIMER_THRESH 0x0000FF00 // Mask for timer threshold(0-7) +#define AR_IMR_S5_GENTIMER7 0x80 //Timer 7 does not have a dedicated function + +/* Interrupt status registers (read-and-clear access secondary shadow copies) */ +#define AR_ISR_RAC 0x00c0 // MAC Primary interrupt status register + // read-and-clear access +#define AR_ISR_S0_S 0x00c4 // MAC Secondary interrupt status register 0 + +/* Interrupt status registers (read-and-clear access secondary shadow copies) */ +#define AR_ISR_RAC 0x00c0 // MAC Primary interrupt status register + // read-and-clear access +#define AR_ISR_S0_S 0x00c4 // MAC Secondary interrupt status register 0 + // shadow copy +#define AR_ISR_S0_QCU_TXOK 0x000003FF // Mask for TXOK (QCU 0-9) +#define AR_ISR_S0_QCU_TXOK_S 0 // Shift for TXOK (QCU 0-9) +#define AR_ISR_S0_QCU_TXDESC 0x03FF0000 // Mask for TXDESC (QCU 0-9) +#define AR_ISR_S0_QCU_TXDESC_S 16 // Shift for TXDESC (QCU 0-9) + +#define AR_ISR_S1_S 0x00c8 // MAC Secondary interrupt status register 1 + // shadow copy +#define AR_ISR_S1_QCU_TXERR 0x000003FF // Mask for TXERR (QCU 0-9) +#define AR_ISR_S1_QCU_TXERR_S 0 // Shift for TXERR (QCU 0-9) +#define AR_ISR_S1_QCU_TXEOL 0x03FF0000 // Mask for TXEOL (QCU 0-9) +#define AR_ISR_S1_QCU_TXEOL_S 16 // Shift for TXEOL (QCU 0-9) + +#define AR_ISR_S2_S 0x00cc // MAC Secondary interrupt status register 2 + // shadow copy +#define AR_ISR_S3_S 0x00d0 // MAC Secondary interrupt status register 3 + // shadow copy +#define AR_ISR_S4_S 0x00d4 // MAC Secondary interrupt status register 4 + // shadow copy +#define AR_ISR_S5_S 0x00d8 // MAC Secondary interrupt status register 5 + // shadow copy +#define AR_DMADBG_0 0x00e0 // MAC DMA Debug Registers +#define AR_DMADBG_1 0x00e4 +#define AR_DMADBG_2 0x00e8 +#define AR_DMADBG_3 0x00ec +#define AR_DMADBG_4 0x00f0 +#define AR_DMADBG_5 0x00f4 +#define AR_DMADBG_6 0x00f8 +#define AR_DMADBG_7 0x00fc + +/* QCU registers */ +#define AR_NUM_QCU 10 // Only use QCU 0-9 for forward QCU compatibility +#define AR_QCU_0 0x0001 +#define AR_QCU_1 0x0002 +#define AR_QCU_2 0x0004 +#define AR_QCU_3 0x0008 +#define AR_QCU_4 0x0010 +#define AR_QCU_5 0x0020 +#define AR_QCU_6 0x0040 +#define AR_QCU_7 0x0080 +#define AR_QCU_8 0x0100 +#define AR_QCU_9 0x0200 + +#define AR_Q0_TXDP 0x0800 // MAC Transmit Queue descriptor pointer +#define AR_Q1_TXDP 0x0804 // MAC Transmit Queue descriptor pointer +#define AR_Q2_TXDP 0x0808 // MAC Transmit Queue descriptor pointer +#define AR_Q3_TXDP 0x080c // MAC Transmit Queue descriptor pointer +#define AR_Q4_TXDP 0x0810 // MAC Transmit Queue descriptor pointer +#define AR_Q5_TXDP 0x0814 // MAC Transmit Queue descriptor pointer +#define AR_Q6_TXDP 0x0818 // MAC Transmit Queue descriptor pointer +#define AR_Q7_TXDP 0x081c // MAC Transmit Queue descriptor pointer +#define AR_Q8_TXDP 0x0820 // MAC Transmit Queue descriptor pointer +#define AR_Q9_TXDP 0x0824 // MAC Transmit Queue descriptor pointer +#define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) + +#define AR_Q_TXE 0x0840 // MAC Transmit Queue enable +#define AR_Q_TXE_M 0x000003FF // Mask for TXE (QCU 0-9) + +#define AR_Q_TXD 0x0880 // MAC Transmit Queue disable +#define AR_Q_TXD_M 0x000003FF // Mask for TXD (QCU 0-9) + +#define AR_Q0_CBRCFG 0x08c0 // MAC CBR configuration +#define AR_Q1_CBRCFG 0x08c4 // MAC CBR configuration +#define AR_Q2_CBRCFG 0x08c8 // MAC CBR configuration +#define AR_Q3_CBRCFG 0x08cc // MAC CBR configuration +#define AR_Q4_CBRCFG 0x08d0 // MAC CBR configuration +#define AR_Q5_CBRCFG 0x08d4 // MAC CBR configuration +#define AR_Q6_CBRCFG 0x08d8 // MAC CBR configuration +#define AR_Q7_CBRCFG 0x08dc // MAC CBR configuration +#define AR_Q8_CBRCFG 0x08e0 // MAC CBR configuration +#define AR_Q9_CBRCFG 0x08e4 // MAC CBR configuration +#define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) +#define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF // Mask for CBR interval (us) +#define AR_Q_CBRCFG_INTERVAL_S 0 // Shift for CBR interval (us) +#define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 // Mask for CBR overflow threshold +#define AR_Q_CBRCFG_OVF_THRESH_S 24 // Shift for CBR overflow threshold + +#define AR_Q0_RDYTIMECFG 0x0900 // MAC ReadyTime configuration +#define AR_Q1_RDYTIMECFG 0x0904 // MAC ReadyTime configuration +#define AR_Q2_RDYTIMECFG 0x0908 // MAC ReadyTime configuration +#define AR_Q3_RDYTIMECFG 0x090c // MAC ReadyTime configuration +#define AR_Q4_RDYTIMECFG 0x0910 // MAC ReadyTime configuration +#define AR_Q5_RDYTIMECFG 0x0914 // MAC ReadyTime configuration +#define AR_Q6_RDYTIMECFG 0x0918 // MAC ReadyTime configuration +#define AR_Q7_RDYTIMECFG 0x091c // MAC ReadyTime configuration +#define AR_Q8_RDYTIMECFG 0x0920 // MAC ReadyTime configuration +#define AR_Q9_RDYTIMECFG 0x0924 // MAC ReadyTime configuration +#define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) +#define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF // Mask for ReadyTime duration (us) +#define AR_Q_RDYTIMECFG_DURATION_S 0 // Shift for ReadyTime duration (us) +#define AR_Q_RDYTIMECFG_EN 0x01000000 // ReadyTime enable + +#define AR_Q_ONESHOTARM_SC 0x0940 // MAC OneShotArm set control +#define AR_Q_ONESHOTARM_SC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_SC (QCU 0-9) +#define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 // Reserved + +#define AR_Q_ONESHOTARM_CC 0x0980 // MAC OneShotArm clear control +#define AR_Q_ONESHOTARM_CC_M 0x000003FF // Mask for #define AR_Q_ONESHOTARM_CC (QCU 0-9) +#define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 // Reserved + +#define AR_Q0_MISC 0x09c0 // MAC Miscellaneous QCU settings +#define AR_Q1_MISC 0x09c4 // MAC Miscellaneous QCU settings +#define AR_Q2_MISC 0x09c8 // MAC Miscellaneous QCU settings +#define AR_Q3_MISC 0x09cc // MAC Miscellaneous QCU settings +#define AR_Q4_MISC 0x09d0 // MAC Miscellaneous QCU settings +#define AR_Q5_MISC 0x09d4 // MAC Miscellaneous QCU settings +#define AR_Q6_MISC 0x09d8 // MAC Miscellaneous QCU settings +#define AR_Q7_MISC 0x09dc // MAC Miscellaneous QCU settings +#define AR_Q8_MISC 0x09e0 // MAC Miscellaneous QCU settings +#define AR_Q9_MISC 0x09e4 // MAC Miscellaneous QCU settings +#define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) +#define AR_Q_MISC_FSP 0x0000000F // Mask for Frame Scheduling Policy +#define AR_Q_MISC_FSP_ASAP 0 // ASAP +#define AR_Q_MISC_FSP_CBR 1 // CBR +#define AR_Q_MISC_FSP_DBA_GATED 2 // DMA Beacon Alert gated +#define AR_Q_MISC_FSP_TIM_GATED 3 // TIM gated +#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 // Beacon-sent-gated +#define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 // Beacon-received-gated +#define AR_Q_MISC_ONE_SHOT_EN 0x00000010 // OneShot enable +#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 // Disable CBR expired counter incr (empty q) +#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 // Disable CBR expired counter incr (empty beacon q) +#define AR_Q_MISC_BEACON_USE 0x00000080 // Beacon use indication +#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 // CBR expired counter limit enable +#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 // Enable TXE cleared on ReadyTime expired or VEOL +#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 // Reset CBR expired counter +#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 // DCU frame early termination request control +#define AR_Q_MISC_RESV0 0xFFFFF000 // Reserved + +#define AR_Q0_STS 0x0a00 // MAC Miscellaneous QCU status +#define AR_Q1_STS 0x0a04 // MAC Miscellaneous QCU status +#define AR_Q2_STS 0x0a08 // MAC Miscellaneous QCU status +#define AR_Q3_STS 0x0a0c // MAC Miscellaneous QCU status +#define AR_Q4_STS 0x0a10 // MAC Miscellaneous QCU status +#define AR_Q5_STS 0x0a14 // MAC Miscellaneous QCU status +#define AR_Q6_STS 0x0a18 // MAC Miscellaneous QCU status +#define AR_Q7_STS 0x0a1c // MAC Miscellaneous QCU status +#define AR_Q8_STS 0x0a20 // MAC Miscellaneous QCU status +#define AR_Q9_STS 0x0a24 // MAC Miscellaneous QCU status +#define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) +#define AR_Q_STS_PEND_FR_CNT 0x00000003 // Mask for Pending Frame Count +#define AR_Q_STS_RESV0 0x000000FC // Reserved +#define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 // Mask for CBR expired counter +#define AR_Q_STS_RESV1 0xFFFF0000 // Reserved + +#define AR_Q_RDYTIMESHDN 0x0a40 // MAC ReadyTimeShutdown status +#define AR_Q_RDYTIMESHDN_M 0x000003FF // Mask for ReadyTimeShutdown status (QCU 0-9) + +/* DCU registers */ +#define AR_NUM_DCU 10 // Only use 10 DCU's for forward QCU/DCU compatibility +#define AR_DCU_0 0x0001 +#define AR_DCU_1 0x0002 +#define AR_DCU_2 0x0004 +#define AR_DCU_3 0x0008 +#define AR_DCU_4 0x0010 +#define AR_DCU_5 0x0020 +#define AR_DCU_6 0x0040 +#define AR_DCU_7 0x0080 +#define AR_DCU_8 0x0100 +#define AR_DCU_9 0x0200 + +#define AR_D0_QCUMASK 0x1000 // MAC QCU Mask +#define AR_D1_QCUMASK 0x1004 // MAC QCU Mask +#define AR_D2_QCUMASK 0x1008 // MAC QCU Mask +#define AR_D3_QCUMASK 0x100c // MAC QCU Mask +#define AR_D4_QCUMASK 0x1010 // MAC QCU Mask +#define AR_D5_QCUMASK 0x1014 // MAC QCU Mask +#define AR_D6_QCUMASK 0x1018 // MAC QCU Mask +#define AR_D7_QCUMASK 0x101c // MAC QCU Mask +#define AR_D8_QCUMASK 0x1020 // MAC QCU Mask +#define AR_D9_QCUMASK 0x1024 // MAC QCU Mask +#define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) +#define AR_D_QCUMASK 0x000003FF // Mask for QCU Mask (QCU 0-9) +#define AR_D_QCUMASK_RESV0 0xFFFFFC00 // Reserved + +#define AR_D_TXBLK_CMD 0x1038 /* DCU transmit filter cmd (w/only) */ +#define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) /* DCU transmit filter data */ + +#define AR_D0_LCL_IFS 0x1040 // MAC DCU-specific IFS settings +#define AR_D1_LCL_IFS 0x1044 // MAC DCU-specific IFS settings +#define AR_D2_LCL_IFS 0x1048 // MAC DCU-specific IFS settings +#define AR_D3_LCL_IFS 0x104c // MAC DCU-specific IFS settings +#define AR_D4_LCL_IFS 0x1050 // MAC DCU-specific IFS settings +#define AR_D5_LCL_IFS 0x1054 // MAC DCU-specific IFS settings +#define AR_D6_LCL_IFS 0x1058 // MAC DCU-specific IFS settings +#define AR_D7_LCL_IFS 0x105c // MAC DCU-specific IFS settings +#define AR_D8_LCL_IFS 0x1060 // MAC DCU-specific IFS settings +#define AR_D9_LCL_IFS 0x1064 // MAC DCU-specific IFS settings +#define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) +#define AR_D_LCL_IFS_CWMIN 0x000003FF // Mask for CW_MIN +#define AR_D_LCL_IFS_CWMIN_S 0 // Shift for CW_MIN +#define AR_D_LCL_IFS_CWMAX 0x000FFC00 // Mask for CW_MAX +#define AR_D_LCL_IFS_CWMAX_S 10 // Shift for CW_MAX +#define AR_D_LCL_IFS_AIFS 0x0FF00000 // Mask for AIFS +#define AR_D_LCL_IFS_AIFS_S 20 // Shift for AIFS + /* + * Note: even though this field is 8 bits wide the + * maximum supported AIFS value is 0xfc. Setting the AIFS value + * to 0xfd 0xfe or 0xff will not work correctly and will cause + * the DCU to hang. + */ +#define AR_D_LCL_IFS_RESV0 0xF0000000 // Reserved + +#define AR_D0_RETRY_LIMIT 0x1080 // MAC Retry limits +#define AR_D1_RETRY_LIMIT 0x1084 // MAC Retry limits +#define AR_D2_RETRY_LIMIT 0x1088 // MAC Retry limits +#define AR_D3_RETRY_LIMIT 0x108c // MAC Retry limits +#define AR_D4_RETRY_LIMIT 0x1090 // MAC Retry limits +#define AR_D5_RETRY_LIMIT 0x1094 // MAC Retry limits +#define AR_D6_RETRY_LIMIT 0x1098 // MAC Retry limits +#define AR_D7_RETRY_LIMIT 0x109c // MAC Retry limits +#define AR_D8_RETRY_LIMIT 0x10a0 // MAC Retry limits +#define AR_D9_RETRY_LIMIT 0x10a4 // MAC Retry limits +#define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) +#define AR_D_RETRY_LIMIT_FR_SH 0x0000000F // Mask for frame short retry limit +#define AR_D_RETRY_LIMIT_FR_SH_S 0 // Shift for frame short retry limit +#define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 // Mask for station short retry limit +#define AR_D_RETRY_LIMIT_STA_SH_S 8 // Shift for station short retry limit +#define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 // Mask for station short retry limit +#define AR_D_RETRY_LIMIT_STA_LG_S 14 // Shift for station short retry limit +#define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 // Reserved + +#define AR_D0_CHNTIME 0x10c0 // MAC ChannelTime settings +#define AR_D1_CHNTIME 0x10c4 // MAC ChannelTime settings +#define AR_D2_CHNTIME 0x10c8 // MAC ChannelTime settings +#define AR_D3_CHNTIME 0x10cc // MAC ChannelTime settings +#define AR_D4_CHNTIME 0x10d0 // MAC ChannelTime settings +#define AR_D5_CHNTIME 0x10d4 // MAC ChannelTime settings +#define AR_D6_CHNTIME 0x10d8 // MAC ChannelTime settings +#define AR_D7_CHNTIME 0x10dc // MAC ChannelTime settings +#define AR_D8_CHNTIME 0x10e0 // MAC ChannelTime settings +#define AR_D9_CHNTIME 0x10e4 // MAC ChannelTime settings +#define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) +#define AR_D_CHNTIME_DUR 0x000FFFFF // Mask for ChannelTime duration (us) +#define AR_D_CHNTIME_DUR_S 0 // Shift for ChannelTime duration (us) +#define AR_D_CHNTIME_EN 0x00100000 // ChannelTime enable +#define AR_D_CHNTIME_RESV0 0xFFE00000 // Reserved + +#define AR_D0_MISC 0x1100 // MAC Miscellaneous DCU-specific settings +#define AR_D1_MISC 0x1104 // MAC Miscellaneous DCU-specific settings +#define AR_D2_MISC 0x1108 // MAC Miscellaneous DCU-specific settings +#define AR_D3_MISC 0x110c // MAC Miscellaneous DCU-specific settings +#define AR_D4_MISC 0x1110 // MAC Miscellaneous DCU-specific settings +#define AR_D5_MISC 0x1114 // MAC Miscellaneous DCU-specific settings +#define AR_D6_MISC 0x1118 // MAC Miscellaneous DCU-specific settings +#define AR_D7_MISC 0x111c // MAC Miscellaneous DCU-specific settings +#define AR_D8_MISC 0x1120 // MAC Miscellaneous DCU-specific settings +#define AR_D9_MISC 0x1124 // MAC Miscellaneous DCU-specific settings +#define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) +#define AR_D_MISC_BKOFF_THRESH 0x0000003F // Mask for Backoff threshold setting +#define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 // End of tx series station RTS/data failure count reset policy +#define AR_D_MISC_CW_RESET_EN 0x00000080 // End of tx series CW reset enable +#define AR_D_MISC_FRAG_WAIT_EN 0x00000100 // Fragment Starvation Policy +#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 // Backoff during a frag burst +#define AR_D_MISC_CW_BKOFF_EN 0x00001000 // Use binary exponential CW backoff +#define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 // Mask for Virtual collision handling policy +#define AR_D_MISC_VIR_COL_HANDLING_S 14 // Shift for Virtual collision handling policy +#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 // Normal +#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 // Ignore +#define AR_D_MISC_BEACON_USE 0x00010000 // Beacon use indication +#define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 // Mask for DCU arbiter lockout control +#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 // Shift for DCU arbiter lockout control +#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 // No lockout +#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 // Intra-frame +#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 // Global +#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 // DCU arbiter lockout ignore control +#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 // Sequence number increment disable +#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 // Post-frame backoff disable +#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 // Virtual coll. handling policy +#define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 // Initiate Retry procedure on Blown IFS +#define AR_D_MISC_RESV0 0xFF000000 // Reserved + +#define AR_D_SEQNUM 0x1140 // MAC Frame sequence number control/status + +#define AR_D_GBL_IFS_SIFS 0x1030 // MAC DCU-global IFS settings: SIFS duration +#define AR_D_GBL_IFS_SIFS_M 0x0000FFFF // Mask for SIFS duration (core clocks) +#define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF // Reserved + +#define AR_D_TXBLK_BASE 0x1038 // MAC DCU-global transmit filter bits +#define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF // Mask for bitmask +#define AR_D_TXBLK_WRITE_BITMASK_S 0 // Shift for bitmask +#define AR_D_TXBLK_WRITE_SLICE 0x000F0000 // Mask for slice +#define AR_D_TXBLK_WRITE_SLICE_S 16 // Shift for slice +#define AR_D_TXBLK_WRITE_DCU 0x00F00000 // Mask for DCU number +#define AR_D_TXBLK_WRITE_DCU_S 20 // Shift for DCU number +#define AR_D_TXBLK_WRITE_COMMAND 0x0F000000 // Mask for command +#define AR_D_TXBLK_WRITE_COMMAND_S 24 // Shift for command + +#define AR_D_GBL_IFS_SLOT 0x1070 // MAC DCU-global IFS settings: slot duration +#define AR_D_GBL_IFS_SLOT_M 0x0000FFFF // Mask for Slot duration (core clocks) +#define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 // Reserved + +#define AR_D_GBL_IFS_EIFS 0x10b0 // MAC DCU-global IFS settings: EIFS duration +#define AR_D_GBL_IFS_EIFS_M 0x0000FFFF // Mask for Slot duration (core clocks) +#define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 // Reserved + +#define AR_D_GBL_IFS_MISC 0x10f0 // MAC DCU-global IFS settings: Miscellaneous +#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 // Mask forLFSR slice select +#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 // Turbo mode indication +#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 // Mask for microsecond duration +#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 // Mask for DCU arbiter delay +#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 // Random LSFR slice disable +#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 // Slot transmission window length mask +#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 // Force transmission on slot boundaries +#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 // Ignore backoff + +#define AR_D_FPCTL 0x1230 // DCU frame prefetch settings +#define AR_D_FPCTL_DCU 0x0000000F // Mask for DCU for which prefetch is enabled +#define AR_D_FPCTL_DCU_S 0 // Shift for DCU for which prefetch is enabled +#define AR_D_FPCTL_PREFETCH_EN 0x00000010 // Enable prefetch for normal (non-burst) operation +#define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0 // Mask for Burst frame prefetch per DCU +#define AR_D_FPCTL_BURST_PREFETCH_S 5 // Shift for Burst frame prefetch per DCU + +#define AR_D_TXPSE 0x1270 // MAC DCU transmit pause control/status +#define AR_D_TXPSE_CTRL 0x000003FF // Mask of DCUs to pause (DCUs 0-9) +#define AR_D_TXPSE_RESV0 0x0000FC00 // Reserved +#define AR_D_TXPSE_STATUS 0x00010000 // Transmit pause status +#define AR_D_TXPSE_RESV1 0xFFFE0000 // Reserved + +#define AR_D_TXSLOTMASK 0x12f0 // MAC DCU transmission slot mask +#define AR_D_TXSLOTMASK_NUM 0x0000000F // slot numbers + +#define AR_MAC_LED 0x1f04 /* LED control */ +#define AR_MAC_SCLK_RATE_IND 0x00000003 /* sleep clock indication */ +#define AR_MAC_SCLK_RATE_IND_S 0 +#define AR_MAC_SCLK_32MHZ 0x00000000 /* Sleep clock rate */ +#define AR_MAC_SCLK_4MHZ 0x00000001 /* Sleep clock rate */ +#define AR_MAC_SCLK_1MHZ 0x00000002 /* Sleep clock rate */ +#define AR_MAC_SCLK_32KHZ 0x00000003 /* Sleep clock rate */ +#define AR_MAC_LED_BLINK_SLOW 0x00000008 /* LED slowest blink rate mode */ +#define AR_MAC_LED_BLINK_THRESH_SEL 0x00000070 /* LED blink threshold select */ +#define AR_MAC_LED_MODE_SEL 0x00000380 /* LED mode select */ +#define AR_MAC_LED_MODE_SEL_S 7 +#define AR_MAC_LED_MODE_PROP 0 /* Blink prop to filtered tx/rx */ +#define AR_MAC_LED_MODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ +#define AR_MAC_LED_MODE_SPLIT 2 /* Blink power for tx/net for rx */ +#define AR_MAC_LED_MODE_RAND 3 /* Blink randomly */ +#define AR_MAC_LED_ASSOC_CTL 0x00000c00 +#define AR_MAC_LED_ASSOC_NONE 0x00000000 /* STA is not associated or trying */ +#define AR_MAC_LED_ASSOC_ACTIVE 0x00000400 /* STA is associated */ +#define AR_MAC_LED_ASSOC_PENDING 0x00000800 /* STA is trying to associate */ + +#define AR_MAC_SLEEP 0x1ff0 +#define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 // mac is now awake +#define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 // mac is now asleep + +// DMA & PCI Registers in PCI space (usable during sleep) +#define AR_RC 0x4000 // Warm reset control register +#define AR_RC_AHB 0x00000001 // ahb reset +#define AR_RC_APB 0x00000002 // apb reset + +#define AR_WA 0x4004 // PCI express work-arounds + +#define AR_PM_STATE 0x4008 // power management state +#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 //for wow + +#define AR_HOST_TIMEOUT 0x4018 // dma xfer timeout +#define AR_HOST_APB_TIMEOUT 0x0000FFFF // apb bus timeout +#define AR_HOST_LB_TIMEOUT 0xFFFF0000 // local bus timeout + +#define AR_EEPROM 0x401c // eeprom info +#define AR_EEPROM_ABSENT 0x00000100 +#define AR_EEPROM_CORRUPT 0x00000200 +#define AR_EEPROM_PROT_MASK 0x03FFFC00 +#define AR_EEPROM_PROT_MASK_S 10 + +// Protect Bits RP is read protect WP is write protect +#define EEPROM_PROTECT_RP_0_31 0x0001 +#define EEPROM_PROTECT_WP_0_31 0x0002 +#define EEPROM_PROTECT_RP_32_63 0x0004 +#define EEPROM_PROTECT_WP_32_63 0x0008 +#define EEPROM_PROTECT_RP_64_127 0x0010 +#define EEPROM_PROTECT_WP_64_127 0x0020 +#define EEPROM_PROTECT_RP_128_191 0x0040 +#define EEPROM_PROTECT_WP_128_191 0x0080 +#define EEPROM_PROTECT_RP_192_255 0x0100 +#define EEPROM_PROTECT_WP_192_255 0x0200 +#define EEPROM_PROTECT_RP_256_511 0x0400 +#define EEPROM_PROTECT_WP_256_511 0x0800 +#define EEPROM_PROTECT_RP_512_1023 0x1000 +#define EEPROM_PROTECT_WP_512_1023 0x2000 +#define EEPROM_PROTECT_RP_1024_2047 0x4000 +#define EEPROM_PROTECT_WP_1024_2047 0x8000 + +#ifdef AR9100 +#define AR_SREV 0x0600 /*mac silicon rev (expanded from 8 bits to 16 bits for Sowl) */ +#define AR_SREV_ID 0x00000FFF /* Mask to read SREV info */ +#else +#define AR_SREV 0x4020 // mac silicon rev +#define AR_SREV_ID 0x000000FF /* Mask to read SREV info */ +#endif +#define AR_SREV_VERSION 0x000000F0 /* Mask for Chip version */ +#define AR_SREV_VERSION_S 4 /* Mask to shift Major Rev Info */ +#define AR_SREV_REVISION 0x00000007 /* Mask for Chip revision level */ +/* Sowl extension to SREV. AR_SREV_ID must be 0xFF */ +#define AR_SREV_ID2 0xFFFFFFFF /* Mask to read SREV info */ +#define AR_SREV_VERSION2 0xFFFC0000 /* Mask for Chip version */ +#define AR_SREV_VERSION2_S 18 /* Mask to shift Major Rev Info */ +#define AR_SREV_TYPE2 0x0003F000 /* Mask for Chip type */ +#define AR_SREV_TYPE2_S 12 /* Mask to shift Major Rev Info */ +#define AR_SREV_TYPE2_CHAIN 0x00001000 /* chain mode (1 = 3 chains, 0 = 2 chains) */ +#define AR_SREV_TYPE2_HOST_MODE 0x00002000 /* host mode (1 = PCI, 0 = PCIe) */ +#define AR_SREV_REVISION2 0x00000F00 +#define AR_SREV_REVISION2_S 8 + +#define AR_SREV_VERSION_OWL_PCI 0xD +#define AR_SREV_VERSION_OWL_PCIE 0xC + +#define AR_SREV_REVISION_OWL_10 0 /* Owl 1.0 */ +#define AR_SREV_REVISION_OWL_20 1 /* Owl 2.0/2.1 */ +#define AR_SREV_REVISION_OWL_22 2 /* Owl 2.2 */ +#ifdef AR9100 +#define AR_SREV_VERSION_SOWL 0x43 +#else +#define AR_SREV_VERSION_SOWL 0x1F +#endif +#define AR_SREV_REVISION_SOWL_10 0 /* Sowl 1.0 */ +#define AR_SREV_REVISION_SOWL_11 1 /* Sowl 1.1 */ + +#define AR_SREV_VERSION_MERLIN 0x2f /* Merlin Version,0x2F for fusion_merlin branch */ +#define AR_SREV_REVISION_MERLIN_10 0 /* Merlin 1.0 */ +#define AR_SREV_REVISION_MERLIN_20 1 /* Merlin 2.0 */ +#define AR_SREV_REVISION_MERLIN_21 2 /* Merlin 2.1 */ + +#define AR_SREV_OWL_10(_ah) (((_ah)->ah_macVersion == AR_SREV_VERSION_OWL_PCI) || \ + ((_ah)->ah_macVersion == AR_SREV_VERSION_OWL_PCIE)) + +#define AR_SREV_OWL_20_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_SOWL) || \ + (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_20)) +#define AR_SREV_OWL_22_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_SOWL) || \ + (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_OWL_22)) +#define AR_SREV_SOWL_10_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_SOWL)) + +#define AR_SREV_MERLIN(_ah) ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_MERLIN)) +#define AR_SREV_MERLIN_10_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion >= AR_SREV_VERSION_MERLIN)) +#define AR_SREV_MERLIN_20(_ah) ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_MERLIN) && \ + (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_MERLIN_20)) +#define AR_SREV_MERLIN_20_OR_LATER(_ah) ((AH_PRIVATE((_ah))->ah_macVersion > AR_SREV_VERSION_MERLIN) || \ + ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_MERLIN) && \ + (AH_PRIVATE((_ah))->ah_macRev >= AR_SREV_REVISION_MERLIN_20))) + +#define AR_SREV_SOWL(_ah) ((AH_PRIVATE((_ah))->ah_macVersion == AR_SREV_VERSION_SOWL)) +#define AR_SREV_SOWL_11(_ah) (AR_SREV_SOWL(_ah) && (AH_PRIVATE((_ah))->ah_macRev == AR_SREV_REVISION_SOWL_11)) + +#define AR_RADIO_SREV_MAJOR 0xf0 +#define AR_RAD5133_SREV_MAJOR 0xc0 /* Fowl: 2+5G/3x3 */ +#define AR_RAD2133_SREV_MAJOR 0xd0 /* Fowl: 2G/3x3 */ +#define AR_RAD5122_SREV_MAJOR 0xe0 /* Fowl: 5G/2x2 */ +#define AR_RAD2122_SREV_MAJOR 0xf0 /* Fowl: 2+5G/2x2 */ + +#define AR_AHB_MODE 0x4024 // ahb mode for dma +#define AR_AHB_EXACT_WR_EN 0x00000000 // write exact bytes +#define AR_AHB_BUF_WR_EN 0x00000001 // buffer write upto cacheline +#define AR_AHB_EXACT_RD_EN 0x00000000 // read exact bytes +#define AR_AHB_CACHELINE_RD_EN 0x00000002 // read upto end of cacheline +#define AR_AHB_PREFETCH_RD_EN 0x00000004 // prefetch upto page boundary +#define AR_AHB_PAGE_SIZE_1K 0x00000000 // set page-size as 1k +#define AR_AHB_PAGE_SIZE_2K 0x00000008 // set page-size as 2k +#define AR_AHB_PAGE_SIZE_4K 0x00000010 // set page-size as 4k + +#define AR_INTR_RTC_IRQ 0x00000001 // rtc in shutdown state +#define AR_INTR_MAC_IRQ 0x00000002 // pending mac interrupt +#define AR_INTR_EEP_PROT_ACCESS 0x00000004 // eeprom protected area access +#define AR_INTR_MAC_AWAKE 0x00020000 // mac is awake +#define AR_INTR_MAC_ASLEEP 0x00040000 // mac is asleep +/* TODO: fill in other values */ +#define AR_INTR_GPIO 0x3FF00000 // gpio interrupted +#define AR_INTR_GPIO_S 20 + +#define AR_INTR_SYNC_CAUSE_CLR 0x4028 // clear interrupt +#define AR_INTR_SYNC_CAUSE 0x4028 // check pending interrupts +#define AR_INTR_SYNC_ENABLE 0x402c // enable interrupts +#define AR_INTR_ASYNC_MASK 0x4030 // asynchronous interrupt mask +#define AR_INTR_SYNC_MASK 0x4034 // synchronous interrupt mask +#define AR_INTR_ASYNC_CAUSE 0x4038 // check pending interrupts +#define AR_INTR_ASYNC_ENABLE 0x403c // enable interrupts + + +/* + * synchronous interrupt signals + */ +enum { + AR_INTR_SYNC_RTC_IRQ = 0x00000001, + AR_INTR_SYNC_MAC_IRQ = 0x00000002, + AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, + AR_INTR_SYNC_APB_TIMEOUT = 0x00000008, + AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, + AR_INTR_SYNC_HOST1_FATAL = 0x00000020, + AR_INTR_SYNC_HOST1_PERR = 0x00000040, + AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, + AR_INTR_SYNC_RADM_CPL_EP = 0x00000100, + AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, + AR_INTR_SYNC_RADM_CPL_DLP_ABORT = 0x00000400, + AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, + AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, + AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, + AR_INTR_SYNC_PM_ACCESS = 0x00004000, + AR_INTR_SYNC_MAC_AWAKE = 0x00008000, + AR_INTR_SYNC_MAC_ASLEEP = 0x00010000, + AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, + AR_INTR_SYNC_ALL = 0x0003FFFF, +}; + +#define AR_NUM_GPIO 10 // Ten numbered 0 to 9. + +#ifdef MAGPIE_MERLIN + +#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 // enable interrupts: bits 18..31 +#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 // enable interrupts: bits 18..31 + +/* PCIe defines */ +#define AR_PCIE_SERDES 0x4040 +#define AR_PCIE_SERDES2 0x4044 +#define AR_PCIE_PM_CTRL 0x4014 +#define AR_PCIE_PM_CTRL_ENA 0x00080000 + +#define AR928X_NUM_GPIO 10 // Ten numbered 0 to 9 for Merlin. + +#define AR_GPIO_IN_OUT 0x4048 // GPIO input / output register + +#define AR_GPIO_IN_VAL 0x0FFFC000 +#define AR_GPIO_IN_VAL_S 14 +#define AR928X_GPIO_IN_VAL 0x000FFC00 // added for Merlin +#define AR928X_GPIO_IN_VAL_S 10 // added for Merlin + +/* Added for Merlin */ +#define AR_GPIO_OE_OUT 0x404c // GPIO output register +#define AR_GPIO_OE_OUT_DRV 0x3 // 2 bit field mask, shifted by 2*bitpos +#define AR_GPIO_OE_OUT_DRV_NO 0x0 // tristate +#define AR_GPIO_OE_OUT_DRV_LOW 0x1 // drive if low +#define AR_GPIO_OE_OUT_DRV_HI 0x2 // drive if high +#define AR_GPIO_OE_OUT_DRV_ALL 0x3 // drive always +/* 4050-405C added for Merlin */ +#define AR_GPIO_INTR_POL 0x4050 // GPIO interrup polarity: 0 == high level, 1 == lo level +#define AR_GPIO_INTR_POL_VAL 0x00001FFF // bits 13:0 correspond to gpio 13:0 +#define AR_GPIO_INTR_POL_VAL_S 0 // bits 13:0 correspond to gpio 13:0 + +#define AR_GPIO_INPUT_EN_VAL 0x4054 // GPIO input enable and value +#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 // default value for rfsilent_bb_l +#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 +#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 // 0 == set rfsilent_bb_l to default, 1 == connect rfsilent_bb_l to baseband +#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 +#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 +#define AR_GPIO_JTAG_DISABLE 0x00020000 // 1 == disable JTAG + +#define AR_GPIO_INPUT_MUX1 0x4058 + +#define AR_GPIO_INPUT_MUX2 0x405c +#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f // bits 0..3: input mux for clk25 input +#define AR_GPIO_INPUT_MUX2_CLK25_S 0 // bits 0..3: input mux for clk25 input +#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 // bits 4..7: input mux for rfsilent_bb_l input +#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 // bits 4..7: input mux for rfsilent_bb_l input +#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 // bits 8..11: input mux for RTC Reset input +#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 // bits 8..11: input mux for RTC Reset input + +#define AR_GPIO_OUTPUT_MUX1 0x4060 +/* 4064-4068 added for Merlin */ +#define AR_GPIO_OUTPUT_MUX2 0x4064 +#define AR_GPIO_OUTPUT_MUX3 0x4068 + +#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 +#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 +#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 +#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 +#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 + +#define AR_INPUT_STATE 0x406c + +#define AR_GPIO_PDPU 0x4088 + +/* 4094 added for Merlin */ +#define AR_PCIE_MSI 0x4094 +#define AR_PCIE_MSI_ENABLE 0x00000001 + +// RTC register +#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ + +// AR9280: rf long shift registers +#define AR_AN_RF2G1_CH0 0x7810 +#define AR_AN_RF2G1_CH0_OB 0x03800000 +#define AR_AN_RF2G1_CH0_OB_S 23 +#define AR_AN_RF2G1_CH0_DB 0x1C000000 +#define AR_AN_RF2G1_CH0_DB_S 26 + +#define AR_AN_RF5G1_CH0 0x7818 +#define AR_AN_RF5G1_CH0_OB5 0x00070000 +#define AR_AN_RF5G1_CH0_OB5_S 16 +#define AR_AN_RF5G1_CH0_DB5 0x00380000 +#define AR_AN_RF5G1_CH0_DB5_S 19 + +#define AR_AN_RF2G1_CH1 0x7834 +#define AR_AN_RF2G1_CH1_OB 0x03800000 +#define AR_AN_RF2G1_CH1_OB_S 23 +#define AR_AN_RF2G1_CH1_DB 0x1C000000 +#define AR_AN_RF2G1_CH1_DB_S 26 + +#define AR_AN_RF5G1_CH1 0x783C +#define AR_AN_RF5G1_CH1_OB5 0x00070000 +#define AR_AN_RF5G1_CH1_OB5_S 16 +#define AR_AN_RF5G1_CH1_DB5 0x00380000 +#define AR_AN_RF5G1_CH1_DB5_S 19 + +#define AR_AN_TOP2 0x7894 +#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 +#define AR_AN_TOP2_XPABIAS_LVL_S 30 +#define AR_AN_TOP2_LOCALBIAS 0x00200000 +#define AR_AN_TOP2_LOCALBIAS_S 21 +#define AR_AN_TOP2_PWDCLKIND 0x00400000 +#define AR_AN_TOP2_PWDCLKIND_S 22 + +#define AR_AN_SYNTH9 0x7868 +#define AR_AN_SYNTH9_REFDIVA 0xf8000000 +#define AR_AN_SYNTH9_REFDIVA_S 27 + +#endif // MAGPIE_MERLIN + + +#define AR_GPIO_IN 0x4048 // GPIO input register + +#define AR_GPIO_INTR_OUT 0x404c // GPIO output register +#define AR_GPIO_OUT_CTRL 0x000003FF // 0 = out, 1 = in +#define AR_GPIO_OUT_VAL 0x000FFC00 +#define AR_GPIO_OUT_VAL_S 10 +#define AR_GPIO_INTR_CTRL 0x3FF00000 +#define AR_GPIO_INTR_CTRL_S 20 + +#define AR_GPIO_OUTPUT_MUX1 0x4060 + +#define AR_EEPROM_STATUS_DATA 0x407c +#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff +#define AR_EEPROM_STATUS_DATA_VAL_S 0 +#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 +#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 +#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 +#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 + +#define AR_OBS 0x4080 + +// RTC registers +/* Sowl */ +#define AR_RTC_SOWL_PLL_DIV 0x000003ff +#define AR_RTC_SOWL_PLL_DIV_S 0 +#define AR_RTC_SOWL_PLL_REFDIV 0x00003C00 +#define AR_RTC_SOWL_PLL_REFDIV_S 10 +#define AR_RTC_SOWL_PLL_CLKSEL 0x0000C000 +#define AR_RTC_SOWL_PLL_CLKSEL_S 14 + +#ifndef AR9100 +#define AR_RTC_RC 0x7000 /* reset control */ +#define AR_RTC_RC_M 0x00000003 +#define AR_RTC_RC_MAC_WARM 0x00000001 +#define AR_RTC_RC_MAC_COLD 0x00000002 +#define AR_RTC_PLL_CONTROL 0x7014 +/* Owl */ +#define AR_RTC_PLL_DIV 0x0000001f +#define AR_RTC_PLL_DIV_S 0 +#define AR_RTC_PLL_DIV2 0x00000020 +#define AR_RTC_PLL_REFDIV_5 0x000000c0 +#define AR_RTC_PLL_CLKSEL_S 8 +#define AR_RTC_PLL_CLKSEL 0x00000300 + +#define AR_RTC_RESET 0x7040 /* reset RTC */ + +#define AR_RTC_STATUS 0x7044 /* system sleep status */ +#define AR_RTC_STATUS_M 0x0000000f +#define AR_RTC_STATUS_SHUTDOWN 0x00000001 +#define AR_RTC_STATUS_ON 0x00000002 +#define AR_RTC_STATUS_SLEEP 0x00000004 +#define AR_RTC_STATUS_WAKEUP 0x00000008 + +#define AR_RTC_SLEEP_CLK 0x7048 +#define AR_RTC_FORCE_DERIVED_CLK 0x2 + +#define AR_RTC_FORCE_WAKE 0x704c /* control MAC force wake */ +#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ +#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ + +#define AR_RTC_INTR_CAUSE 0x7050 /* RTC interrupt cause/clear */ +#define AR_RTC_INTR_ENABLE 0x7054 /* RTC interrupt enable */ +#define AR_RTC_INTR_MASK 0x7058 /* RTC interrupt mask */ +#else +#define AR_SEQ_MASK 0x8060 /* MAC AES mute mask */ + +#define AR_RTC_BASE 0x00020000 +#define AR_RTC_RC (AR_RTC_BASE + 0x0000) /* reset control */ +#define AR_RTC_RC_M 0x00000003 +#define AR_RTC_RC_MAC_WARM 0x00000001 +#define AR_RTC_RC_MAC_COLD 0x00000002 +#define AR_RTC_RC_COLD_RESET 0x00000004 +#define AR_RTC_RC_WARM_RESET 0x00000008 + +#define AR_RTC_PLL_CONTROL (AR_RTC_BASE + 0x0014) +#define AR_RTC_PLL_DIV 0x0000001f +#define AR_RTC_PLL_DIV_S 0 +#define AR_RTC_PLL_DIV2 0x00000020 +#define AR_RTC_PLL_REFDIV_5 0x000000c0 +#define AR_RTC_PLL_CLKSEL_S 8 +#define AR_RTC_PLL_CLKSEL 0x00000300 + +#define AR_RTC_RESET (AR_RTC_BASE + 0x0040) /* reset RTC */ +#define AR_RTC_RESET_EN 0x00000001 /* Reset RTC bit */ + +#define AR_RTC_STATUS (AR_RTC_BASE + 0x0044) /* system sleep status */ +#define AR_RTC_PM_STATUS_M 0x0000000f /* Pwr Mgmt Status is the last 4 bits */ +#define AR_RTC_STATUS_M 0x0000003f /* RTC Status is the last 6 bits */ +#define AR_RTC_STATUS_SHUTDOWN 0x00000001 +#define AR_RTC_STATUS_ON 0x00000002 +#define AR_RTC_STATUS_SLEEP 0x00000004 +#define AR_RTC_STATUS_WAKEUP 0x00000008 + +#define AR_RTC_SLEEP_CLK (AR_RTC_BASE + 0x0048) +#define AR_RTC_FORCE_DERIVED_CLK 0x2 + +#define AR_RTC_FORCE_WAKE (AR_RTC_BASE + 0x004c) /* control MAC force wake */ +#define AR_RTC_FORCE_WAKE_EN 0x00000001 /* enable force wake */ +#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 /* auto-wake on MAC interrupt */ + +#define AR_RTC_INTR_CAUSE (AR_RTC_BASE + 0x0050) /* RTC interrupt cause/clear */ +#define AR_RTC_INTR_ENABLE (AR_RTC_BASE + 0x0054) /* RTC interrupt enable */ +#define AR_RTC_INTR_MASK (AR_RTC_BASE + 0x0058) /* RTC interrupt mask */ + +#endif //HOWL + +// MAC PCU Registers +#define AR_STA_ID0 0x8000 // MAC station ID0 - low 32 bits +#define AR_STA_ID1 0x8004 // MAC station ID1 - upper 16 bits +#define AR_STA_ID1_SADH_MASK 0x0000FFFF // Mask for 16 msb of MAC addr +#define AR_STA_ID1_STA_AP 0x00010000 // Device is AP +#define AR_STA_ID1_ADHOC 0x00020000 // Device is ad-hoc +#define AR_STA_ID1_PWR_SAV 0x00040000 // Power save in generated frames +#define AR_STA_ID1_KSRCHDIS 0x00080000 // Key search disable +#define AR_STA_ID1_PCF 0x00100000 // Observe PCF +#define AR_STA_ID1_USE_DEFANT 0x00200000 // Use default antenna +#define AR_STA_ID1_DEFANT_UPDATE 0x00400000 // Update default ant w/TX antenna +#define AR_STA_ID1_RTS_USE_DEF 0x00800000 // Use default antenna to send RTS +#define AR_STA_ID1_ACKCTS_6MB 0x01000000 // Use 6Mb/s rate for ACK & CTS +#define AR_STA_ID1_BASE_RATE_11B 0x02000000 // Use 11b base rate for ACK & CTS +#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 // default ant for generated frames +#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 // Enable Michael +#define AR_STA_ID1_KSRCH_MODE 0x10000000 // Look-up unique key when !keyID +#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 // Don't replace seq num +#define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 // IV endian-ness in CBC nonce +#define AR_STA_ID1_MCAST_KSRCH 0x80000000 // Adhoc key search enable + +#define AR_BSS_ID0 0x8008 // MAC BSSID low 32 bits +#define AR_BSS_ID1 0x800C // MAC BSSID upper 16 bits / AID +#define AR_BSS_ID1_U16 0x0000FFFF // Mask for upper 16 bits of BSSID +#define AR_BSS_ID1_AID 0x07FF0000 // Mask for association ID +#define AR_BSS_ID1_AID_S 16 // Shift for association ID + +#define AR_BCN_RSSI_AVE 0x8010 // MAC Beacon average RSSI +#define AR_BCN_RSSI_AVE_MASK 0x00000FFF // Beacon RSSI mask + +#define AR_TIME_OUT 0x8014 // MAC ACK & CTS time-out +#define AR_TIME_OUT_ACK 0x00003FFF // Mask for ACK time-out +#define AR_TIME_OUT_ACK_S 0 +#define AR_TIME_OUT_CTS 0x3FFF0000 // Mask for CTS time-out +#define AR_TIME_OUT_CTS_S 16 + +#define AR_RSSI_THR 0x8018 // beacon RSSI warning / bmiss threshold +#define AR_RSSI_THR_MASK 0x000000FF // Beacon RSSI warning threshold +#define AR_RSSI_THR_BM_THR 0x0000FF00 // Mask for Missed beacon threshold +#define AR_RSSI_THR_BM_THR_S 8 // Shift for Missed beacon threshold +#define AR_RSSI_BCN_WEIGHT 0x1F000000 // RSSI average weight +#define AR_RSSI_BCN_WEIGHT_S 24 +#define AR_RSSI_BCN_RSSI_RST 0x20000000 // Reset RSSI value + +#define AR_USEC 0x801c // MAC transmit latency register +#define AR_USEC_USEC 0x0000007F // Mask for clock cycles in 1 usec +#define AR_USEC_TX_LAT 0x007FC000 // tx latency to start of SIGNAL (usec) +#define AR_USEC_TX_LAT_S 14 // tx latency to start of SIGNAL (usec) +#define AR_USEC_RX_LAT 0x1F800000 // rx latency to start of SIGNAL (usec) +#define AR_USEC_RX_LAT_S 23 // rx latency to start of SIGNAL (usec) + +#define AR_RESET_TSF 0x8020 +#define AR_RESET_TSF_ONCE 0x01000000 // reset tsf once ; self-clears bit + +#define AR_MAX_CFP_DUR 0x8038 // MAC maximum CFP duration +#define AR_CFP_VAL 0x0000FFFF // CFP value in uS + +#define AR_RX_FILTER 0x803C // MAC receive filter register +#define AR_RX_FILTER_ALL 0x00000000 // Disallow all frames +#define AR_RX_UCAST 0x00000001 // Allow unicast frames +#define AR_RX_MCAST 0x00000002 // Allow multicast frames +#define AR_RX_BCAST 0x00000004 // Allow broadcast frames +#define AR_RX_CONTROL 0x00000008 // Allow control frames +#define AR_RX_BEACON 0x00000010 // Allow beacon frames +#define AR_RX_PROM 0x00000020 // Promiscuous mode all packets +#define AR_RX_PROBE_REQ 0x00000080 // Any probe request frameA +#define AR_RX_MY_BEACON 0x00000200 // Any beacon frame with matching BSSID +#define AR_RX_COMPR_BAR 0x00000400 // Compressed directed block ack request +#define AR_RX_COMPR_BA 0x00000800 // Compressed directed block ack +#define AR_RX_UNCOM_BA_BAR 0x00001000 // Uncompressed directed BA or BAR + +#if 0 +#define AR_RX_XR_POLL 0x00000040 // Allow XR Poll frames +#endif +#define AR_RX_PROBE_REQ 0x00000080 // Allow probe request frames +#define AR_RX_MY_BEACON 0x00000200 // Allow beacons with matching BSSID + +#define AR_MCAST_FIL0 0x8040 // MAC multicast filter lower 32 bits +#define AR_MCAST_FIL1 0x8044 // MAC multicast filter upper 32 bits + +#define AR_DIAG_SW 0x8048 // MAC PCU control register +#define AR_DIAG_CACHE_ACK 0x00000001 // disable ACK when no valid key +#define AR_DIAG_ACK_DIS 0x00000002 // disable ACK generation +#define AR_DIAG_CTS_DIS 0x00000004 // disable CTS generation +#define AR_DIAG_ENCRYPT_DIS 0x00000008 // disable encryption +#define AR_DIAG_DECRYPT_DIS 0x00000010 // disable decryption +#define AR_DIAG_RX_DIS 0x00000020 // disable receive +#define AR_DIAG_LOOP_BACK 0x00000040 // enable loopback +#define AR_DIAG_CORR_FCS 0x00000080 // corrupt FCS +#define AR_DIAG_CHAN_INFO 0x00000100 // dump channel info +#if 0 +#define AR_DIAG_EN_SCRAMSD 0x00000200 // enable fixed scrambler seed +#endif +#define AR_DIAG_SCRAM_SEED 0x0001FE00 // Mask for fixed scrambler seed +#define AR_DIAG_SCRAM_SEED_S 8 // Shift for fixed scrambler seed +#define AR_DIAG_FRAME_NV0 0x00020000 // accept w/protocol version !0 +#define AR_DIAG_OBS_PT_SEL1 0x000C0000 // observation point select +#define AR_DIAG_OBS_PT_SEL1_S 18 // Shift for observation point select +#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 // force rx_clear high +#define AR_DIAG_IGNORE_VIRT_CS 0x00200000 // ignore virtual carrier sense +#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 // force channel idle high +#define AR_DIAG_EIFS_CTRL_ENA 0x00800000 // use framed and ~wait_wep if 0 +#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 // dual chain channel info +#define AR_DIAG_RX_ABORT 0x02000000 // abort rx +#define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 // saturate cycle cnts (no shift) +#define AR_DIAG_OBS_PT_SEL2 0x08000000 // Mask for observation point sel +#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 // force rx_clear (ctl) low (i.e. busy) +#define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 // force rx_clear (ext) low (i.e. busy) + +#define AR_TSF_L32 0x804c // MAC local clock lower 32 bits +#define AR_TSF_U32 0x8050 // MAC local clock upper 32 bits + +#define AR_TST_ADDAC 0x8054 // ADDAC test register +#define AR_DEF_ANTENNA 0x8058 // default antenna register +#if 0 +#define AR_DEF_ANT_CHN_SEL 0x4 // Default Ant Chain Select bit +#define AR_DEF_ANT_CHN0_ANT 0x1 // Def Ant Chain 0 Antenna Select bit +#define AR_DEF_ANT_CHN1_ANT 0x2 // Def Ant Chain 1 Antenna Select bit +#endif + +#define AR_AES_MUTE_MASK0 0x805c // MAC AES mute mask +#define AR_AES_MUTE_MASK0_FC 0x0000FFFF // frame ctrl mask bits +#define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 // qos ctrl mask bits +#define AR_AES_MUTE_MASK0_QOS_S 16 + +#define AR_AES_MUTE_MASK1 0x8060 // MAC AES mute mask +#define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF // seq + frag mask bits + +#define AR_GATED_CLKS 0x8064 // control clock domain +#define AR_GATED_CLKS_TX 0x00000002 +#define AR_GATED_CLKS_RX 0x00000004 +#define AR_GATED_CLKS_REG 0x00000008 + +#define AR_OBS_BUS_CTRL 0x8068 // select a bus for observation +#define AR_OBS_BUS_SEL_1 0x00040000 +#define AR_OBS_BUS_SEL_2 0x00080000 +#define AR_OBS_BUS_SEL_3 0x000C0000 +#define AR_OBS_BUS_SEL_4 0x08040000 +#define AR_OBS_BUS_SEL_5 0x08080000 + +#define AR_OBS_BUS_1 0x806c // mac debug observation bus +#define AR_OBS_BUS_1_PCU 0x00000001 +#define AR_OBS_BUS_1_RX_END 0x00000002 +#define AR_OBS_BUS_1_RX_WEP 0x00000004 +#define AR_OBS_BUS_1_RX_BEACON 0x00000008 +#define AR_OBS_BUS_1_RX_FILTER 0x00000010 +#define AR_OBS_BUS_1_TX_HCF 0x00000020 +#define AR_OBS_BUS_1_QUIET_TIME 0x00000040 +#define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 +#define AR_OBS_BUS_1_TX_HOLD 0x00000100 +#define AR_OBS_BUS_1_TX_FRAME 0x00000200 +#define AR_OBS_BUS_1_RX_FRAME 0x00000400 +#define AR_OBS_BUS_1_RX_CLEAR 0x00000800 +#define AR_OBS_BUS_1_WEP_STATE 0x0003F000 +#define AR_OBS_BUS_1_WEP_STATE_S 12 +#define AR_OBS_BUS_1_RX_STATE 0x01F00000 +#define AR_OBS_BUS_1_RX_STATE_S 20 +#define AR_OBS_BUS_1_TX_STATE 0x7E000000 +#define AR_OBS_BUS_1_TX_STATE_S 25 + +#define AR_LAST_TSTP 0x8080 // MAC Time stamp of the last beacon received +#define AR_NAV 0x8084 // MAC current NAV value +#define AR_RTS_OK 0x8088 // MAC RTS exchange success counter +#define AR_RTS_FAIL 0x808c // MAC RTS exchange failure counter +#define AR_ACK_FAIL 0x8090 // MAC ACK failure counter +#define AR_FCS_FAIL 0x8094 // FCS check failure counter +#define AR_BEACON_CNT 0x8098 // Valid beacon counter + +#if 0 +#define AR_XRMODE 0x80c0 // Extended range mode +#define AR_XRMODE_XR_POLL_TYPE_M 0x00000003 // poll type mask +#define AR_XRMODE_XR_POLL_TYPE_S 0 +#define AR_XRMODE_XR_POLL_SUBTYPE_M 0x0000003c // poll type mask +#define AR_XRMODE_XR_POLL_SUBTYPE_S 2 +#define AR_XRMODE_XR_WAIT_FOR_POLL 0x00000080 // wait for poll sta only +#define AR_XRMODE_XR_FRAME_HOLD_M 0xfff00000 // cycles hold for chirps +#define AR_XRMODE_XR_FRAME_HOLD_S 20 + +#define AR_XRDEL 0x80c4 // Extended range delay +#define AR_XRDEL_SLOT_DELAY_M 0x0000ffff // cycles +#define AR_XRDEL_SLOT_DELAY_S 0 +#define AR_XRDEL_CHIRP_DATA_DELAY_M 0xffff0000 // cycles +#define AR_XRDEL_CHIRP_DATA_DELAY_S 16 + +#define AR_XRTO 0x80c8 // Extended range timeout +#define AR_XRTO_CHIRP_TO_M 0x0000ffff // cycles +#define AR_XRTO_CHIRP_TO_S 0 +#define AR_XRTO_POLL_TO_M 0xffff0000 // cycles +#define AR_XRTO_POLL_TO_S 16 + +#define AR_XRCRP 0x80cc // Extended range chirp +#define AR_XRCRP_SEND_CHIRP 0x00000001 // generate stand alone chirp +#define AR_XRCRP_CHIRP_GAP_M 0xffff0000 // cycles +#define AR_XRCRP_CHIRP_GAP_S 16 + +#define AR_XRSTMP 0x80d0 // Extended range stomp +#define AR_XRSTMP_RX_ABORT_RSSI 0x00000001 // stomp low rssi receive +#define AR_XRSTMP_RX_ABORT_BSSID 0x00000002 // stomp foreign bssid receive +#define AR_XRSTMP_TX_STOMP_RSSI 0x00000004 // xmit stomp low rssi receive +#define AR_XRSTMP_TX_STOMP_BSSID 0x00000008 // xmit stomp foreign bssid rx +#define AR_XRSTMP_TX_STOMP_DATA 0x00000010 // xmit stomp receive data +#define AR_XRSTMP_RX_ABORT_DATA 0x00000020 // stomp receive data +#define AR_XRSTMP_TX_RSSI_THRESH_M 0x0000FF00 // threshold for tx stomp +#define AR_XRSTMP_TX_RSSI_THRESH_S 8 +#define AR_XRSTMP_RX_RSSI_THRESH_M 0x00FF0000 // threshold for tx stomp +#define AR_XRSTMP_RX_RSSI_THRESH_S 16 +#endif + +#define AR_SLEEP1 0x80d4 // Enhanced sleep control 1 +#if 0 +#define AR_SLEEP1_NEXT_DTIM_M 0x0007ffff // Absolute time(1/8TU) for next dtim mask +#define AR_SLEEP1_NEXT_DTIM_S 0 // Absolute time(1/8TU) for next dtim shift +#endif +#define AR_SLEEP1_ASSUME_DTIM 0x00080000 // Assume DTIM on missed beacon +#if 0 +#define AR_SLEEP1_ENH_SLEEP_ENABLE 0x00100000 // Enables Venice sleep logic +#endif +#define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 // Cab timeout(TU) mask +#define AR_SLEEP1_CAB_TIMEOUT_S 21 // Cab timeout(TU) shift + +#define AR_SLEEP2 0x80d8 // Enhanced sleep control 2 +#if 0 +#define AR_SLEEP2_NEXT_TIM_M 0x0007ffff // Absolute time(1/8TU) for next tim/beacon mask +#define AR_SLEEP2_NEXT_TIM_S 0 // Absolute time(1/8TU) for next tim/beacon shift +#endif +#define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 // Beacon timeout(TU) mask +#define AR_SLEEP2_BEACON_TIMEOUT_S 21 // Beacon timeout(TU) shift + +#if 0 +#define AR_SLEEP3 0x80dc // Enhanced sleep control 3 +#define AR_SLEEP3_TIM_PERIOD_M 0x0000ffff // Tim/Beacon period(TU) mask +#define AR_SLEEP3_TIM_PERIOD_S 0 // Tim/Beacon period(TU) shift +#define AR_SLEEP3_DTIM_PERIOD_M 0xffff0000 // DTIM period(TU) mask +#define AR_SLEEP3_DTIM_PERIOD_S 16 // DTIM period(TU) shift +#endif + +#define AR_BSSMSKL 0x80e0 // BSSID mask lower 32 bits +#define AR_BSSMSKU 0x80e4 // BSSID mask upper 16 bits + +#define AR_TPC 0x80e8 // Transmit power control for gen frames +#define AR_TPC_ACK 0x0000003f // ack frames mask +#define AR_TPC_ACK_S 0x00 // ack frames shift +#define AR_TPC_CTS 0x00003f00 // cts frames mask +#define AR_TPC_CTS_S 0x08 // cts frames shift +#define AR_TPC_CHIRP 0x003f0000 // chirp frames mask +#define AR_TPC_CHIRP_S 0x16 // chirp frames shift + +#define AR_TFCNT 0x80ec // Profile count transmit frames +#define AR_RFCNT 0x80f0 // Profile count receive frames +#define AR_RCCNT 0x80f4 // Profile count receive clear +#define AR_CCCNT 0x80f8 // Profile count cycle counter + +#define AR_QUIET1 0x80fc // Quiet time programming for TGh +#if 0 +#define AR_QUIET1_NEXT_QUIET_S 0 // TSF of next quiet period (TU) +#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff +#define AR_QUIET1_QUIET_ENABLE 0x00010000 // Enable Quiet time operation +#endif +#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 // ack/cts in quiet period +#define AR_QUIET2 0x8100 // More Quiet programming +#if 0 +#define AR_QUIET2_QUIET_PERIOD_S 0 // Periodicity of quiet period (TU) +#define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff +#endif +#define AR_QUIET2_QUIET_DURATION_S 16 // quiet period (TU) +#define AR_QUIET2_QUIET_DURATION 0xffff0000 + +#define AR_TSF_PARM 0x8104 // TSF parameters +#define AR_TSF_INCREMENT_M 0x000000ff +#define AR_TSF_INCREMENT_S 0x00 + +#define AR_QOS_NO_ACK 0x8108 // locate no_ack in qos +#define AR_QOS_NO_ACK_TWO_BIT 0x0000000f // 2 bit sentinel for no-ack +#define AR_QOS_NO_ACK_TWO_BIT_S 0 +#define AR_QOS_NO_ACK_BIT_OFF 0x00000070 // offset for no-ack +#define AR_QOS_NO_ACK_BIT_OFF_S 4 +#define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 // from end of header +#define AR_QOS_NO_ACK_BYTE_OFF_S 7 + +#define AR_PHY_ERR 0x810c // Phy errors to be filtered + /* XXX validate! XXX */ +#define AR_PHY_ERR_DCHIRP 0x00000008 // Bit 3 enables double chirp +#define AR_PHY_ERR_RADAR 0x00000020 // Bit 5 is Radar signal +#define AR_PHY_ERR_OFDM_TIMING 0x00020000 // Bit 17 is false detect for OFDM +#define AR_PHY_ERR_CCK_TIMING 0x02000000 // Bit 25 is false detect for CCK + +#define AR_RXFIFO_CFG 0x8114 + + /* XXX sub-fields? XXX */ +#define AR_MIC_QOS_CONTROL 0x8118 +#define AR_MIC_QOS_SELECT 0x811c + +#define AR_PCU_MISC 0x8120 // PCU Miscellaneous Mode +#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 // force bssid to match +#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 // tx/rx mic key are together +#define AR_PCU_TX_ADD_TSF 0x00000008 // add tx_tsf + int_tsf +#define AR_PCU_CCK_SIFS_MODE 0x00000010 // assume 11b sifs programmed +#define AR_PCU_RX_ANT_UPDT 0x00000800 // KC_RX_ANT_UPDATE +#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 // enforce txop / tbtt +#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 // count bmiss's when sleeping +#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 // use rx_clear to count sifs +#define AR_PCU_FORCE_QUIET_COLL 0x00040000 // kill xmit for channel change +#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 +#define AR_PCU_TBTT_PROTECT 0x00200000 // no xmit upto tbtt + 20 uS +#define AR_PCU_CLEAR_VMF 0x01000000 // clear vmf mode (fast cc) +#define AR_PCU_CLEAR_BA_VALID 0x04000000 // clear ba state + + +#define AR_FILT_OFDM 0x8124 +#define AR_FILT_OFDM_COUNT 0x00FFFFFF // count of filtered ofdm + +#define AR_FILT_CCK 0x8128 +#define AR_FILT_CCK_COUNT 0x00FFFFFF // count of filtered cck + +#define AR_PHY_ERR_1 0x812c +#define AR_PHY_ERR_1_COUNT 0x00FFFFFF // phy errs that pass mask_1 +#define AR_PHY_ERR_MASK_1 0x8130 // mask for err_1_count + +#define AR_PHY_ERR_2 0x8134 +#define AR_PHY_ERR_2_COUNT 0x00FFFFFF // phy errs that pass mask_2 +#define AR_PHY_ERR_MASK_2 0x8138 // mask for err_2_count + +#define AR_PHY_COUNTMAX (3 << 22) // Max counted before intr +#define AR_MIBCNT_INTRMASK (3 << 22) // Mask top 2 bits of counters + +#define AR_TSF_THRESHOLD 0x813c // interrupt if rx_tsf-int_tsf +#define AR_TSF_THRESHOLD_VAL 0x0000FFFF // exceeds threshold + +#define AR_PHY_ERR_EIFS_MASK 0x8144 // phy_errs causing eifs delay + +#define AR_PHY_ERR_3 0x8168 +#define AR_PHY_ERR_3_COUNT 0x00FFFFFF // phy errs that pass mask_3 +#define AR_PHY_ERR_MASK_3 0x816c // mask for err_3_count + +#define AR_BT_COEX_MODE 0x8170 +#define AR_BT_TIME_EXTEND 0x000000ff +#define AR_BT_TIME_EXTEND_S 0 +#define AR_BT_TXSTATE_EXTEND 0x00000100 +#define AR_BT_TXSTATE_EXTEND_S 8 +#define AR_BT_TX_FRAME_EXTEND 0x00000200 +#define AR_BT_TX_FRAME_EXTEND_S 9 +#define AR_BT_MODE 0x00000c00 +#define AR_BT_MODE_S 10 +#define AR_BT_QUIET 0x00001000 +#define AR_BT_QUIET_S 12 +#define AR_BT_QCU_THRESH 0x0001e000 +#define AR_BT_QCU_THRESH_S 13 +#define AR_BT_RX_CLEAR_POLARITY 0x00020000 +#define AR_BT_RX_CLEAR_POLARITY_S 17 +#define AR_BT_PRIORITY_TIME 0x00fc0000 +#define AR_BT_PRIORITY_TIME_S 18 +#define AR_BT_FIRST_SLOT_TIME 0xff000000 +#define AR_BT_FIRST_SLOT_TIME_S 24 + +#define AR_BT_COEX_WEIGHT 0x8174 +#define AR_BT_BT_WGHT 0x0000ffff +#define AR_BT_BT_WGHT_S 0 +#define AR_BT_WL_WGHT 0xffff0000 +#define AR_BT_WL_WGHT_S 16 + +#define AR_TXSIFS 0x81d0 +#define AR_TXSIFS_TIME 0x000000FF // uS in SIFS +#define AR_TXSIFS_TX_LATENCY 0x00000F00 // uS for transmission thru bb +#define AR_TXSIFS_TX_LATENCY_S 8 +#define AR_TXSIFS_ACK_SHIFT 0x00007000 // chan width for ack +#define AR_TXSIFS_ACK_SHIFT_S 12 + +#define AR_TXOP_X 0x81ec // txop for legacy non-qos +#define AR_TXOP_X_VAL 0x000000FF + + /* on-demand subfields */ +#define AR_TXOP_0_3 0x81f0 // txop for various tid's +#define AR_TXOP_4_7 0x81f4 +#define AR_TXOP_8_11 0x81f8 +#define AR_TXOP_12_15 0x81fc + +#if 0 +#define AR_KC_MASK 0x81c4 // MAC Key Cache Mask for words 0x10 0x14 + // 0 is write allow 1 is write blocked +#define AR_KC_MASK_TYPE_M 0x00000007 // MAC Key Cache Type Mask +#define AR_KC_MASK_LAST_TX_ANT 0x00000008 // MAC Key Cache Last Tx Ant Mask +#define AR_KC_MASK_ASYNC_MASK_M 0x000001f0 // MAC Key Cache Async Rate Offset Mask +#define AR_KC_MASK_UPDT_BF 0x00000200 // MAC Key Cache Update Bf coef Mask +#define AR_KC_MASK_RX_CHAIN0_ACK 0x00000400 // MAC Key Cache Ack Ant Ch 0 Mask +#define AR_KC_MASK_RX_CHAIN1_ACK 0x00000800 // MAC Key Cache Ack Ant Ch 1 Mask +#define AR_KC_MASK_TX_CHAIN0_SEL 0x00001000 // MAC Key Cache Tx Sel Ant Ch 0 Mask +#define AR_KC_MASK_TX_CHAIN1_SEL 0x00002000 // MAC Key Cache Tx Sel Ant Ch 1 Mask +#define AR_KC_MASK_CHAIN_SEL 0x00004000 // MAC Key Cache Chain Sel Mask +#define AR_KC_MASK_WORD_10 0x00010000 // MAC Key Cache Word 0x10 Mask +#endif + +/* generic timers based on tsf - all uS */ +#define AR_NEXT_TBTT_TIMER 0x8200 +#define AR_NEXT_DMA_BEACON_ALERT 0x8204 +#define AR_NEXT_SWBA 0x8208 +#define AR_NEXT_CFP 0x8208 +#define AR_NEXT_HCF 0x820C +#define AR_NEXT_TIM 0x8210 +#define AR_NEXT_DTIM 0x8214 +#define AR_NEXT_QUIET_TIMER 0x8218 +#define AR_NEXT_NDP_TIMER 0x821C + +#define AR_BEACON_PERIOD 0x8220 +#define AR_DMA_BEACON_PERIOD 0x8224 +#define AR_SWBA_PERIOD 0x8228 +#define AR_HCF_PERIOD 0x822C +#define AR_TIM_PERIOD 0x8230 +#define AR_DTIM_PERIOD 0x8234 +#define AR_QUIET_PERIOD 0x8238 +#define AR_NDP_PERIOD 0x823C + +#define AR_TIMER_MODE 0x8240 +#define AR_TBTT_TIMER_EN 0x00000001 +#define AR_DBA_TIMER_EN 0x00000002 +#define AR_SWBA_TIMER_EN 0x00000004 +#define AR_HCF_TIMER_EN 0x00000008 +#define AR_TIM_TIMER_EN 0x00000010 +#define AR_DTIM_TIMER_EN 0x00000020 +#define AR_QUIET_TIMER_EN 0x00000040 +#define AR_NDP_TIMER_EN 0x00000080 +#define AR_TIMER_OVERFLOW_INDEX 0x00000700 +#define AR_TIMER_OVERFLOW_INDEX_S 8 +#define AR_TIMER_THRESH 0xFFFFF000 +#define AR_TIMER_THRESH_S 12 + +#define AR_SLP32_MODE 0x8244 +#define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF // rising <-> falling edge +#define AR_SLP32_ENA 0x00100000 +#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 // tsf update in progress + +#define AR_SLP32_WAKE 0x8248 +#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF // time to wake crystal + +#define AR_SLP32_INC 0x824c +#define AR_SLP32_TST_INC 0x000FFFFF + +#define AR_SLP_CNT 0x8250 // 32kHz cycles for which mac is asleep +#define AR_SLP_CYCLE_CNT 0x8254 // absolute number of 32kHz cycles + +#define AR_SLP_MIB_CTRL 0x8258 +#define AR_SLP_MIB_CLEAR 0x00000001 // clear pending +#define AR_SLP_MIB_PENDING 0x00000002 // clear counters + +#ifdef AR5416_EMULATION +// MAC trace buffer registers (emulation only) +#define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 +#define AR_MAC_PCU_LOGIC_ANALYZER_CTL 0x0000000F +#define AR_MAC_PCU_LOGIC_ANALYZER_HOLD 0x00000001 +#define AR_MAC_PCU_LOGIC_ANALYZER_CLEAR 0x00000002 +#define AR_MAC_PCU_LOGIC_ANALYZER_STATE 0x00000004 +#define AR_MAC_PCU_LOGIC_ANALYZER_ENABLE 0x00000008 +#define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL 0x000000F0 +#define AR_MAC_PCU_LOGIC_ANALYZER_QCU_SEL_S 4 +#define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR 0x0003FF00 +#define AR_MAC_PCU_LOGIC_ANALYZER_INT_ADDR_S 8 + +#define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE 0xFFFC0000 +#define AR_MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_S 18 +#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20614 0x00040000 +#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 +#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20803 0x40000000 + +#define AR_MAC_PCU_LOGIC_ANALYZER_32L 0x8268 +#define AR_MAC_PCU_LOGIC_ANALYZER_16U 0x826C + +#define AR_MAC_PCU_TRACE_REG_START 0xE000 +#define AR_MAC_PCU_TRACE_REG_END 0xFFFC +#define AR_MAC_PCU_TRACE_BUFFER_LENGTH (AR_MAC_PCU_TRACE_REG_END - AR_MAC_PCU_TRACE_REG_START + sizeof(a_uint32_t)) +#endif // AR5416_EMULATION + +#define AR_2040_MODE 0x8318 +#define AR_2040_JOINED_RX_CLEAR 0x00000001 // use ctl + ext rx_clear for cca + +/* Additional cycle counter. See also AR_CCCNT */ +#define AR_EXTRCCNT 0x8328 // extension channel rx clear count + // counts number of cycles rx_clear (ext) is low (i.e. busy) + // when the MAC is not actively transmitting/receiving + +#define AR_SELFGEN_MASK 0x832c + + +#if 0 +#define AR_FRM_TYPE_CAP_TBL 0x8500 // Frame Type Capabilities Table +#define AR_FRM_TYPE_CAP_SIZE 64 // Frame Type Cap. Table Size +#define AR_FTC_BF_RX_UPDT_NORM 0x00000001 // BFCOEF_RX_UPDATE_NORMAL +#define AR_FTC_BF_RX_UPDT_SELF 0x00000002 // BFCOEF_RX_UPDATE_SELF_GEN +#define AR_FTC_BF_TX_ENB_NORM 0x00000004 // BFCOEF_TX_ENABLE_NORMAL +#define AR_FTC_BF_TX_ENB_SELF 0x00000008 // BFCOEF_TX_ENABLE_SELF_GEN +#define AR_FTC_BF_TX_ENB_GEN 0x00000010 // BFCOEF_TX_ENABLE_GEN +#define AR_FTC_BF_TX_ENB_MCAST 0x00000020 // BFCOEF_TX_ENABLE_MCAST + + // rate duration registers - used for Multi-rate retry. +#define AR_RATE_DURATION_0 0x8700 // 32 registers from 0x8700 to 0x87CC +#define AR_RATE_DURATION_31 0x87CC +#endif + +#define AR_KEYTABLE_0 0x8800 /* MAC Key Cache */ +#define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) +#define AR_KEY_CACHE_SIZE 128 +#define AR_RSVD_KEYTABLE_ENTRIES 4 +#define AR_KEY_TYPE 0x00000007 // MAC Key Type Mask +#define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */ +#define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */ +#define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */ +#define AR_KEYTABLE_TYPE_TKIP 0x00000004 /* TKIP and Michael */ +#define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES/OCB 128 bit key */ +#define AR_KEYTABLE_TYPE_CCM 0x00000006 /* AES/CCM 128 bit key */ +#define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */ +#define AR_KEYTABLE_ANT 0x00000008 /* previous transmit antenna */ +#define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */ +#define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */ +#define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */ +#define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */ +#define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */ +#define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */ +#define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) /* key type */ +#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */ +#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */ + +#define BT_WGHT 0xff55 +#define STOMP_ALL_WLAN_WGHT 0xfcfc +#define STOMP_LOW_WLAN_WGHT 0xa8a8 +#define STOMP_NONE_WLAN_WGHT 0x0000 +#endif diff --git a/target_firmware/wlan/ieee80211.h b/target_firmware/wlan/ieee80211.h new file mode 100755 index 0000000..8fc53ea --- /dev/null +++ b/target_firmware/wlan/ieee80211.h @@ -0,0 +1,1248 @@ +/*- + * Copyright (c) 2001 Atsushi Onoe + * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/net80211/ieee80211.h,v 1.8 2004/12/31 22:44:26 sam Exp $ + */ +#ifndef _NET80211_IEEE80211_H_ +#define _NET80211_IEEE80211_H_ + +/* + * 802.11 protocol definitions. + */ + +#define IEEE80211_ADDR_LEN 6 /* size of 802.11 address */ +/* is 802.11 address multicast/broadcast? */ +#define IEEE80211_IS_MULTICAST(_a) (*(_a) & 0x01) + +#ifdef __CARRIER_PLATFORM__ +#include +#endif + +/* IEEE 802.11 PLCP header */ +struct ieee80211_plcp_hdr { + a_uint16_t i_sfd; + a_uint8_t i_signal; + a_uint8_t i_service; + a_uint16_t i_length; + a_uint16_t i_crc; +} adf_os_packed; + +#define IEEE80211_PLCP_SFD 0xF3A0 +#define IEEE80211_PLCP_SERVICE 0x00 + +/* + * generic definitions for IEEE 802.11 frames + */ +struct ieee80211_frame { + a_uint8_t i_fc[2]; + a_uint8_t i_dur[2]; + a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; + a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; + a_uint8_t i_addr3[IEEE80211_ADDR_LEN]; + a_uint8_t i_seq[2]; + /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */ + /* see below */ +} adf_os_packed; + +struct ieee80211_qosframe { + a_uint8_t i_fc[2]; + a_uint8_t i_dur[2]; + a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; + a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; + a_uint8_t i_addr3[IEEE80211_ADDR_LEN]; + a_uint8_t i_seq[2]; + a_uint8_t i_qos[2]; + /* possibly followed by addr4[IEEE80211_ADDR_LEN]; */ + /* see below */ +} adf_os_packed; + +struct ieee80211_qoscntl { + a_uint8_t i_qos[2]; +}; + +struct ieee80211_frame_addr4 { + a_uint8_t i_fc[2]; + a_uint8_t i_dur[2]; + a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; + a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; + a_uint8_t i_addr3[IEEE80211_ADDR_LEN]; + a_uint8_t i_seq[2]; + a_uint8_t i_addr4[IEEE80211_ADDR_LEN]; +} adf_os_packed; + + +struct ieee80211_qosframe_addr4 { + a_uint8_t i_fc[2]; + a_uint8_t i_dur[2]; + a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; + a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; + a_uint8_t i_addr3[IEEE80211_ADDR_LEN]; + a_uint8_t i_seq[2]; + a_uint8_t i_addr4[IEEE80211_ADDR_LEN]; + a_uint8_t i_qos[2]; +} adf_os_packed; + +struct ieee80211_ctlframe_addr2 { + a_uint8_t i_fc[2]; + a_uint8_t i_aidordur[2]; /* AID or duration */ + a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; + a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; +} adf_os_packed; + +#define IEEE80211_FC0_VERSION_MASK 0x03 +#define IEEE80211_FC0_VERSION_SHIFT 0 +#define IEEE80211_FC0_VERSION_0 0x00 +#define IEEE80211_FC0_TYPE_MASK 0x0c +#define IEEE80211_FC0_TYPE_SHIFT 2 +#define IEEE80211_FC0_TYPE_MGT 0x00 +#define IEEE80211_FC0_TYPE_CTL 0x04 +#define IEEE80211_FC0_TYPE_DATA 0x08 + +#define IEEE80211_FC0_SUBTYPE_MASK 0xf0 +#define IEEE80211_FC0_SUBTYPE_SHIFT 4 +/* for TYPE_MGT */ +#define IEEE80211_FC0_SUBTYPE_ASSOC_REQ 0x00 +#define IEEE80211_FC0_SUBTYPE_ASSOC_RESP 0x10 +#define IEEE80211_FC0_SUBTYPE_REASSOC_REQ 0x20 +#define IEEE80211_FC0_SUBTYPE_REASSOC_RESP 0x30 +#define IEEE80211_FC0_SUBTYPE_PROBE_REQ 0x40 +#define IEEE80211_FC0_SUBTYPE_PROBE_RESP 0x50 +#define IEEE80211_FC0_SUBTYPE_BEACON 0x80 +#define IEEE80211_FC0_SUBTYPE_ATIM 0x90 +#define IEEE80211_FC0_SUBTYPE_DISASSOC 0xa0 +#define IEEE80211_FC0_SUBTYPE_AUTH 0xb0 +#define IEEE80211_FC0_SUBTYPE_DEAUTH 0xc0 +#define IEEE80211_FC0_SUBTYPE_ACTION 0xd0 +/* for TYPE_CTL */ +#define IEEE80211_FC0_SUBTYPE_BAR 0x80 +#define IEEE80211_FC0_SUBTYPE_PS_POLL 0xa0 +#define IEEE80211_FC0_SUBTYPE_RTS 0xb0 +#define IEEE80211_FC0_SUBTYPE_CTS 0xc0 +#define IEEE80211_FC0_SUBTYPE_ACK 0xd0 +#define IEEE80211_FC0_SUBTYPE_CF_END 0xe0 +#define IEEE80211_FC0_SUBTYPE_CF_END_ACK 0xf0 +/* for TYPE_DATA (bit combination) */ +#define IEEE80211_FC0_SUBTYPE_DATA 0x00 +#define IEEE80211_FC0_SUBTYPE_CF_ACK 0x10 +#define IEEE80211_FC0_SUBTYPE_CF_POLL 0x20 +#define IEEE80211_FC0_SUBTYPE_CF_ACPL 0x30 +#define IEEE80211_FC0_SUBTYPE_NODATA 0x40 +#define IEEE80211_FC0_SUBTYPE_CFACK 0x50 +#define IEEE80211_FC0_SUBTYPE_CFPOLL 0x60 +#define IEEE80211_FC0_SUBTYPE_CF_ACK_CF_ACK 0x70 +#define IEEE80211_FC0_SUBTYPE_QOS 0x80 +#define IEEE80211_FC0_SUBTYPE_QOS_NULL 0xc0 + +#define IEEE80211_FC1_DIR_MASK 0x03 +#define IEEE80211_FC1_DIR_NODS 0x00 /* STA->STA */ +#define IEEE80211_FC1_DIR_TODS 0x01 /* STA->AP */ +#define IEEE80211_FC1_DIR_FROMDS 0x02 /* AP ->STA */ +#define IEEE80211_FC1_DIR_DSTODS 0x03 /* AP ->AP */ + +#define IEEE80211_FC1_MORE_FRAG 0x04 +#define IEEE80211_FC1_RETRY 0x08 +#define IEEE80211_FC1_PWR_MGT 0x10 +#define IEEE80211_FC1_MORE_DATA 0x20 +#define IEEE80211_FC1_WEP 0x40 +#define IEEE80211_FC1_ORDER 0x80 + +#define IEEE80211_SEQ_FRAG_MASK 0x000f +#define IEEE80211_SEQ_FRAG_SHIFT 0 +#define IEEE80211_SEQ_SEQ_MASK 0xfff0 +#define IEEE80211_SEQ_SEQ_SHIFT 4 + +#define IEEE80211_SEQ_LEQ(a,b) ((a_int32_t)((a)-(b)) <= 0) + +#define IEEE80211_NWID_LEN 32 + +#define IEEE80211_QOS_TXOP 0x00ff + +#define IEEE80211_QOS_AMSDU 0x80 +#define IEEE80211_QOS_AMSDU_S 7 +#define IEEE80211_QOS_ACKPOLICY 0x60 +#define IEEE80211_QOS_ACKPOLICY_S 5 +#define IEEE80211_QOS_EOSP 0x10 +#define IEEE80211_QOS_EOSP_S 4 +#define IEEE80211_QOS_TID 0x0f + +/* + * Country/Region Codes from MS WINNLS.H + * Numbering from ISO 3166 + * XXX belongs elsewhere + */ +enum CountryCode { + CTRY_ALBANIA = 8, /* Albania */ + CTRY_ALGERIA = 12, /* Algeria */ + CTRY_ARGENTINA = 32, /* Argentina */ + CTRY_ARMENIA = 51, /* Armenia */ + CTRY_AUSTRALIA = 36, /* Australia */ + CTRY_AUSTRIA = 40, /* Austria */ + CTRY_AZERBAIJAN = 31, /* Azerbaijan */ + CTRY_BAHRAIN = 48, /* Bahrain */ + CTRY_BELARUS = 112, /* Belarus */ + CTRY_BELGIUM = 56, /* Belgium */ + CTRY_BELIZE = 84, /* Belize */ + CTRY_BOLIVIA = 68, /* Bolivia */ + CTRY_BOSNIA_HERZEGOWINA = 70, /* Bosnia and Herzegowina */ + CTRY_BRAZIL = 76, /* Brazil */ + CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */ + CTRY_BULGARIA = 100, /* Bulgaria */ + CTRY_CANADA = 124, /* Canada */ + CTRY_CHILE = 152, /* Chile */ + CTRY_CHINA = 156, /* People's Republic of China */ + CTRY_COLOMBIA = 170, /* Colombia */ + CTRY_COSTA_RICA = 188, /* Costa Rica */ + CTRY_CROATIA = 191, /* Croatia */ + CTRY_CYPRUS = 196, + CTRY_CZECH = 203, /* Czech Republic */ + CTRY_DENMARK = 208, /* Denmark */ + CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */ + CTRY_ECUADOR = 218, /* Ecuador */ + CTRY_EGYPT = 818, /* Egypt */ + CTRY_EL_SALVADOR = 222, /* El Salvador */ + CTRY_ESTONIA = 233, /* Estonia */ + CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */ + CTRY_FINLAND = 246, /* Finland */ + CTRY_FRANCE = 250, /* France */ + CTRY_FRANCE2 = 255, /* France2 */ + CTRY_GEORGIA = 268, /* Georgia */ + CTRY_GERMANY = 276, /* Germany */ + CTRY_GREECE = 300, /* Greece */ + CTRY_GUATEMALA = 320, /* Guatemala */ + CTRY_HONDURAS = 340, /* Honduras */ + CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */ + CTRY_HUNGARY = 348, /* Hungary */ + CTRY_ICELAND = 352, /* Iceland */ + CTRY_INDIA = 356, /* India */ + CTRY_INDONESIA = 360, /* Indonesia */ + CTRY_IRAN = 364, /* Iran */ + CTRY_IRAQ = 368, /* Iraq */ + CTRY_IRELAND = 372, /* Ireland */ + CTRY_ISRAEL = 376, /* Israel */ + CTRY_ITALY = 380, /* Italy */ + CTRY_JAMAICA = 388, /* Jamaica */ + CTRY_JAPAN = 392, /* Japan */ + CTRY_JAPAN1 = 393, /* Japan (JP1) */ + CTRY_JAPAN2 = 394, /* Japan (JP0) */ + CTRY_JAPAN3 = 395, /* Japan (JP1-1) */ + CTRY_JAPAN4 = 396, /* Japan (JE1) */ + CTRY_JAPAN5 = 397, /* Japan (JE2) */ + CTRY_JAPAN6 = 399, /* Japan (JP6) */ + CTRY_JAPAN7 = 4007, /* Japan */ + CTRY_JAPAN8 = 4008, /* Japan */ + CTRY_JAPAN9 = 4009, /* Japan */ + CTRY_JAPAN10 = 4010, /* Japan */ + CTRY_JAPAN11 = 4011, /* Japan */ + CTRY_JAPAN12 = 4012, /* Japan */ + CTRY_JAPAN13 = 4013, /* Japan */ + CTRY_JAPAN14 = 4014, /* Japan */ + CTRY_JAPAN15 = 4015, /* Japan */ + CTRY_JAPAN16 = 4016, /* Japan */ + CTRY_JAPAN17 = 4017, /* Japan */ + CTRY_JAPAN18 = 4018, /* Japan */ + CTRY_JAPAN19 = 4019, /* Japan */ + CTRY_JAPAN20 = 4020, /* Japan */ + CTRY_JAPAN21 = 4021, /* Japan */ + CTRY_JAPAN22 = 4022, /* Japan */ + CTRY_JAPAN23 = 4023, /* Japan */ + CTRY_JAPAN24 = 4024, /* Japan */ + CTRY_JORDAN = 400, /* Jordan */ + CTRY_KAZAKHSTAN = 398, /* Kazakhstan */ + CTRY_KENYA = 404, /* Kenya */ + CTRY_KOREA_NORTH = 408, /* North Korea */ + CTRY_KOREA_ROC = 410, /* South Korea */ + CTRY_KOREA_ROC2 = 411, /* South Korea */ + CTRY_KUWAIT = 414, /* Kuwait */ + CTRY_LATVIA = 428, /* Latvia */ + CTRY_LEBANON = 422, /* Lebanon */ + CTRY_LIBYA = 434, /* Libya */ + CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */ + CTRY_LITHUANIA = 440, /* Lithuania */ + CTRY_LUXEMBOURG = 442, /* Luxembourg */ + CTRY_MACAU = 446, /* Macau */ + CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */ + CTRY_MALAYSIA = 458, /* Malaysia */ + CTRY_MEXICO = 484, /* Mexico */ + CTRY_MONACO = 492, /* Principality of Monaco */ + CTRY_MOROCCO = 504, /* Morocco */ + CTRY_NETHERLANDS = 528, /* Netherlands */ + CTRY_NEW_ZEALAND = 554, /* New Zealand */ + CTRY_NICARAGUA = 558, /* Nicaragua */ + CTRY_NORWAY = 578, /* Norway */ + CTRY_OMAN = 512, /* Oman */ + CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */ + CTRY_PANAMA = 591, /* Panama */ + CTRY_PARAGUAY = 600, /* Paraguay */ + CTRY_PERU = 604, /* Peru */ + CTRY_PHILIPPINES = 608, /* Republic of the Philippines */ + CTRY_POLAND = 616, /* Poland */ + CTRY_PORTUGAL = 620, /* Portugal */ + CTRY_PUERTO_RICO = 630, /* Puerto Rico */ + CTRY_QATAR = 634, /* Qatar */ + CTRY_ROMANIA = 642, /* Romania */ + CTRY_RUSSIA = 643, /* Russia */ + CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */ + CTRY_SINGAPORE = 702, /* Singapore */ + CTRY_SLOVAKIA = 703, /* Slovak Republic */ + CTRY_SLOVENIA = 705, /* Slovenia */ + CTRY_SOUTH_AFRICA = 710, /* South Africa */ + CTRY_SPAIN = 724, /* Spain */ + CTRY_SRI_LANKA = 144, /* Sri Lanka */ + CTRY_SWEDEN = 752, /* Sweden */ + CTRY_SWITZERLAND = 756, /* Switzerland */ + CTRY_SYRIA = 760, /* Syria */ + CTRY_TAIWAN = 158, /* Taiwan */ + CTRY_THAILAND = 764, /* Thailand */ + CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */ + CTRY_TUNISIA = 788, /* Tunisia */ + CTRY_TURKEY = 792, /* Turkey */ + CTRY_UAE = 784, /* U.A.E. */ + CTRY_UKRAINE = 804, /* Ukraine */ + CTRY_UNITED_KINGDOM = 826, /* United Kingdom */ + CTRY_UNITED_STATES = 840, /* United States */ + CTRY_UNITED_STATES_FCC49 = 842, /* United States (Public Safety)*/ + CTRY_URUGUAY = 858, /* Uruguay */ + CTRY_UZBEKISTAN = 860, /* Uzbekistan */ + CTRY_VENEZUELA = 862, /* Venezuela */ + CTRY_VIET_NAM = 704, /* Viet Nam */ + CTRY_YEMEN = 887, /* Yemen */ + CTRY_ZIMBABWE = 716, /* Zimbabwe */ + CTRY_AUSTRALIA2 = 5000, /* Australia */ + CTRY_CANADA2 = 5001 /* Canada */ +}; + +/* + * Country information element. + */ +#define IEEE80211_COUNTRY_MAX_TRIPLETS (83) +struct ieee80211_ie_country { + a_uint8_t country_id; + a_uint8_t country_len; + a_uint8_t country_str[3]; + a_uint8_t country_triplet[IEEE80211_COUNTRY_MAX_TRIPLETS*3]; +} adf_os_packed; + +/* does frame have QoS sequence control data */ +#define IEEE80211_QOS_HAS_SEQ(wh) \ + (((wh)->i_fc[0] & \ + (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_QOS)) == \ + (IEEE80211_FC0_TYPE_DATA | IEEE80211_FC0_SUBTYPE_QOS)) + +#define WME_QOSINFO_COUNT 0x0f /* Mask for Param Set Count field */ +/* + * WME/802.11e information element. + */ +struct ieee80211_ie_wme { + a_uint8_t wme_id; /* IEEE80211_ELEMID_VENDOR */ + a_uint8_t wme_len; /* length in bytes */ + a_uint8_t wme_oui[3]; /* 0x00, 0x50, 0xf2 */ + a_uint8_t wme_type; /* OUI type */ + a_uint8_t wme_subtype; /* OUI subtype */ + a_uint8_t wme_version; /* spec revision */ + a_uint8_t wme_info; /* QoS info */ +} adf_os_packed; + +/* + * WME/802.11e Tspec Element + */ +struct ieee80211_wme_tspec { + a_uint8_t ts_id; + a_uint8_t ts_len; + a_uint8_t ts_oui[3]; + a_uint8_t ts_oui_type; + a_uint8_t ts_oui_subtype; + a_uint8_t ts_version; + a_uint8_t ts_tsinfo[3]; + a_uint8_t ts_nom_msdu[2]; + a_uint8_t ts_max_msdu[2]; + a_uint8_t ts_min_svc[4]; + a_uint8_t ts_max_svc[4]; + a_uint8_t ts_inactv_intv[4]; + a_uint8_t ts_susp_intv[4]; + a_uint8_t ts_start_svc[4]; + a_uint8_t ts_min_rate[4]; + a_uint8_t ts_mean_rate[4]; + a_uint8_t ts_max_burst[4]; + a_uint8_t ts_min_phy[4]; + a_uint8_t ts_peak_rate[4]; + a_uint8_t ts_delay[4]; + a_uint8_t ts_surplus[2]; + a_uint8_t ts_medium_time[2]; +} adf_os_packed; + +/* + * WME AC parameter field + */ + +struct ieee80211_wme_acparams { + a_uint8_t acp_aci_aifsn; + a_uint8_t acp_logcwminmax; + a_uint16_t acp_txop; +} adf_os_packed; + +#define IEEE80211_WME_PARAM_LEN 24 +#define WME_NUM_AC 4 /* 4 AC categories */ + +#define WME_PARAM_ACI 0x60 /* Mask for ACI field */ +#define WME_PARAM_ACI_S 5 /* Shift for ACI field */ +#define WME_PARAM_ACM 0x10 /* Mask for ACM bit */ +#define WME_PARAM_ACM_S 4 /* Shift for ACM bit */ +#define WME_PARAM_AIFSN 0x0f /* Mask for aifsn field */ +#define WME_PARAM_AIFSN_S 0 /* Shift for aifsn field */ +#define WME_PARAM_LOGCWMIN 0x0f /* Mask for CwMin field (in log) */ +#define WME_PARAM_LOGCWMIN_S 0 /* Shift for CwMin field */ +#define WME_PARAM_LOGCWMAX 0xf0 /* Mask for CwMax field (in log) */ +#define WME_PARAM_LOGCWMAX_S 4 /* Shift for CwMax field */ + +#define WME_AC_TO_TID(_ac) ( \ + ((_ac) == WME_AC_VO) ? 6 : \ + ((_ac) == WME_AC_VI) ? 5 : \ + ((_ac) == WME_AC_BK) ? 1 : \ + 0) + +#define TID_TO_WME_AC(_tid) ( \ + (((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ + (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ + (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ + WME_AC_VO) + +/* + * WME Parameter Element + */ + +struct ieee80211_wme_param { + a_uint8_t param_id; + a_uint8_t param_len; + a_uint8_t param_oui[3]; + a_uint8_t param_oui_type; + a_uint8_t param_oui_sybtype; + a_uint8_t param_version; + a_uint8_t param_qosInfo; + a_uint8_t param_reserved; + struct ieee80211_wme_acparams params_acParams[WME_NUM_AC]; +} adf_os_packed; + +/* + * WME U-APSD qos info field defines + */ +#define WME_CAPINFO_UAPSD_EN 0x00000080 +#define WME_CAPINFO_UAPSD_VO 0x00000001 +#define WME_CAPINFO_UAPSD_VI 0x00000002 +#define WME_CAPINFO_UAPSD_BK 0x00000004 +#define WME_CAPINFO_UAPSD_BE 0x00000008 +#define WME_CAPINFO_UAPSD_ACFLAGS_SHIFT 0 +#define WME_CAPINFO_UAPSD_ACFLAGS_MASK 0xF +#define WME_CAPINFO_UAPSD_MAXSP_SHIFT 5 +#define WME_CAPINFO_UAPSD_MAXSP_MASK 0x3 +#define WME_CAPINFO_IE_OFFSET 8 +#define WME_UAPSD_MAXSP(_qosinfo) (((_qosinfo) >> WME_CAPINFO_UAPSD_MAXSP_SHIFT) & WME_CAPINFO_UAPSD_MAXSP_MASK) +#define WME_UAPSD_AC_ENABLED(_ac, _qosinfo) ( (1<<(3 - (_ac))) & \ + (((_qosinfo) >> WME_CAPINFO_UAPSD_ACFLAGS_SHIFT) & WME_CAPINFO_UAPSD_ACFLAGS_MASK) ) + +/* + * Atheros Advanced Capability information element. + */ +struct ieee80211_ie_athAdvCap { + a_uint8_t athAdvCap_id; /* IEEE80211_ELEMID_VENDOR */ + a_uint8_t athAdvCap_len; /* length in bytes */ + a_uint8_t athAdvCap_oui[3]; /* 0x00, 0x03, 0x7f */ + a_uint8_t athAdvCap_type; /* OUI type */ + a_uint8_t athAdvCap_subtype; /* OUI subtype */ + a_uint8_t athAdvCap_version; /* spec revision */ + a_uint8_t athAdvCap_capability; /* Capability info */ + a_uint16_t athAdvCap_defKeyIndex; +} adf_os_packed; + +/* + * Atheros Extended Capability information element. + */ +struct ieee80211_ie_ath_extcap { + a_uint8_t ath_extcap_id; /* IEEE80211_ELEMID_VENDOR */ + a_uint8_t ath_extcap_len; /* length in bytes */ + a_uint8_t ath_extcap_oui[3]; /* 0x00, 0x03, 0x7f */ + a_uint8_t ath_extcap_type; /* OUI type */ + a_uint8_t ath_extcap_subtype; /* OUI subtype */ + a_uint8_t ath_extcap_version; /* spec revision */ + a_uint32_t ath_extcap_data; /* Data */ +} adf_os_packed; + +/* + * Atheros XR information element. + */ +struct ieee80211_xr_param { + a_uint8_t param_id; + a_uint8_t param_len; + a_uint8_t param_oui[3]; + a_uint8_t param_oui_type; + a_uint8_t param_oui_sybtype; + a_uint8_t param_version; + a_uint8_t param_Info; + a_uint8_t param_base_bssid[IEEE80211_ADDR_LEN]; + a_uint8_t param_xr_bssid[IEEE80211_ADDR_LEN]; + a_uint16_t param_xr_beacon_interval; + a_uint8_t param_base_ath_capability; + a_uint8_t param_xr_ath_capability; +} adf_os_packed; + +/* + * Management Action Frames + */ + +/* generic frame format */ +struct ieee80211_action { + a_uint8_t ia_category; + a_uint8_t ia_action; +} adf_os_packed; + +/* categories */ +#define IEEE80211_ACTION_CAT_QOS 0 /* qos */ +#define IEEE80211_ACTION_CAT_BA 3 /* BA */ +#define IEEE80211_ACTION_CAT_HT 7 /* HT per IEEE802.11n-D1.06 */ + +/* HT actions */ +#define IEEE80211_ACTION_HT_TXCHWIDTH 0 /* recommended transmission channel width */ +#define IEEE80211_ACTION_HT_SMPOWERSAVE 1 /* Spatial Multiplexing (SM) Power Save */ + + +/* HT - recommended transmission channel width */ +struct ieee80211_action_ht_txchwidth { + struct ieee80211_action at_header; + a_uint8_t at_chwidth; +} adf_os_packed; + +#define IEEE80211_A_HT_TXCHWIDTH_20 0 +#define IEEE80211_A_HT_TXCHWIDTH_2040 1 + + +/* HT - Spatial Multiplexing (SM) Power Save */ +struct ieee80211_action_ht_smpowersave { + struct ieee80211_action as_header; + a_uint8_t as_control; +} adf_os_packed; + +/* values defined for 'as_control' field per 802.11n-D1.06 */ +#define IEEE80211_A_HT_SMPOWERSAVE_DISABLED 0x00 /* SM Power Save Disabled, SM packets ok */ +#define IEEE80211_A_HT_SMPOWERSAVE_ENABLED 0x01 /* SM Power Save Enabled bit */ +#define IEEE80211_A_HT_SMPOWERSAVE_MODE 0x02 /* SM Power Save Mode bit */ +#define IEEE80211_A_HT_SMPOWERSAVE_RESERVED 0xFC /* SM Power Save Reserved bits */ + +/* values defined for SM Power Save Mode bit */ +#define IEEE80211_A_HT_SMPOWERSAVE_STATIC 0x00 /* Static, SM packets not ok */ +#define IEEE80211_A_HT_SMPOWERSAVE_DYNAMIC 0x02 /* Dynamic, SM packets ok if preceded by RTS */ + +/* BA actions */ +#define IEEE80211_ACTION_BA_ADDBA_REQUEST 0 /* ADDBA request */ +#define IEEE80211_ACTION_BA_ADDBA_RESPONSE 1 /* ADDBA response */ +#define IEEE80211_ACTION_BA_DELBA 2 /* DELBA */ + +struct ieee80211_ba_parameterset { +#if _BYTE_ORDER == _BIG_ENDIAN + a_uint16_t buffersize : 10, /* B6-15 buffer size */ + tid : 4, /* B2-5 TID */ + bapolicy : 1, /* B1 block ack policy */ + reserved0 : 1; /* B0 reserved */ +#else + a_uint16_t reserved0 : 1, /* B0 reserved */ + bapolicy : 1, /* B1 block ack policy */ + tid : 4, /* B2-5 TID */ + buffersize : 10; /* B6-15 buffer size */ +#endif +} adf_os_packed; + +#define IEEE80211_BA_POLICY_DELAYED 0 +#define IEEE80211_BA_POLICY_IMMEDIATE 1 + +struct ieee80211_ba_seqctrl { + a_uint16_t startseq; +} adf_os_packed; + +struct ieee80211_delba_parameterset { +#if _BYTE_ORDER == _BIG_ENDIAN + a_uint16_t tid : 4, /* B12-15 tid */ + initiator : 1, /* B11 initiator */ + reserved0 : 11; /* B0-10 reserved */ +#else + a_uint16_t reserved0 : 11, /* B0-10 reserved */ + initiator : 1, /* B11 initiator */ + tid : 4; /* B12-15 tid */ +#endif +} adf_os_packed; + +/* BA - ADDBA request */ +struct ieee80211_action_ba_addbarequest { + struct ieee80211_action rq_header; + a_uint8_t rq_dialogtoken; + struct ieee80211_ba_parameterset rq_baparamset; + a_uint16_t rq_batimeout; /* in TUs */ + struct ieee80211_ba_seqctrl rq_basequencectrl; +} adf_os_packed; + +/* BA - ADDBA response */ +struct ieee80211_action_ba_addbaresponse { + struct ieee80211_action rs_header; + a_uint8_t rs_dialogtoken; + a_uint16_t rs_statuscode; + struct ieee80211_ba_parameterset rs_baparamset; + a_uint16_t rs_batimeout; /* in TUs */ +} adf_os_packed; + +/* BA - DELBA */ +struct ieee80211_action_ba_delba { + struct ieee80211_action dl_header; + struct ieee80211_delba_parameterset dl_delbaparamset; + a_uint16_t dl_reasoncode; +} adf_os_packed; + +/* + * Control frames. + */ +struct ieee80211_frame_min { + a_uint8_t i_fc[2]; + a_uint8_t i_dur[2]; + a_uint8_t i_addr1[IEEE80211_ADDR_LEN]; + a_uint8_t i_addr2[IEEE80211_ADDR_LEN]; + /* FCS */ +} adf_os_packed; + +/* + * BAR frame format + */ +#define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */ +#define IEEE80211_BAR_CTL_TID_S 12 /* tid shift */ +#define IEEE80211_BAR_CTL_NOACK 0x0001 /* no-ack policy */ +#define IEEE80211_BAR_CTL_COMBA 0x0004 /* compressed block-ack */ +struct ieee80211_frame_bar { + a_uint8_t i_fc[2]; + a_uint8_t i_dur[2]; + a_uint8_t i_ra[IEEE80211_ADDR_LEN]; + a_uint8_t i_ta[IEEE80211_ADDR_LEN]; + a_uint16_t i_ctl; + a_uint16_t i_seq; + /* FCS */ +} adf_os_packed; + +struct ieee80211_frame_rts { + a_uint8_t i_fc[2]; + a_uint8_t i_dur[2]; + a_uint8_t i_ra[IEEE80211_ADDR_LEN]; + a_uint8_t i_ta[IEEE80211_ADDR_LEN]; + /* FCS */ +} adf_os_packed; + +struct ieee80211_frame_cts { + a_uint8_t i_fc[2]; + a_uint8_t i_dur[2]; + a_uint8_t i_ra[IEEE80211_ADDR_LEN]; + /* FCS */ +} adf_os_packed; + +struct ieee80211_frame_ack { + a_uint8_t i_fc[2]; + a_uint8_t i_dur[2]; + a_uint8_t i_ra[IEEE80211_ADDR_LEN]; + /* FCS */ +} adf_os_packed; + +struct ieee80211_frame_pspoll { + a_uint8_t i_fc[2]; + a_uint8_t i_aid[2]; + a_uint8_t i_bssid[IEEE80211_ADDR_LEN]; + a_uint8_t i_ta[IEEE80211_ADDR_LEN]; + /* FCS */ +} adf_os_packed; + +struct ieee80211_frame_cfend { /* NB: also CF-End+CF-Ack */ + a_uint8_t i_fc[2]; + a_uint8_t i_dur[2]; /* should be zero */ + a_uint8_t i_ra[IEEE80211_ADDR_LEN]; + a_uint8_t i_bssid[IEEE80211_ADDR_LEN]; + /* FCS */ +} adf_os_packed; + +/* + * BEACON management packets + * + * octet timestamp[8] + * octet beacon interval[2] + * octet capability information[2] + * information element + * octet elemid + * octet length + * octet information[length] + */ + +typedef a_uint8_t *ieee80211_mgt_beacon_t; + +#define IEEE80211_BEACON_INTERVAL(beacon) \ + ((beacon)[8] | ((beacon)[9] << 8)) +#define IEEE80211_BEACON_CAPABILITY(beacon) \ + ((beacon)[10] | ((beacon)[11] << 8)) + +#define IEEE80211_CAPINFO_ESS 0x0001 +#define IEEE80211_CAPINFO_IBSS 0x0002 +#define IEEE80211_CAPINFO_CF_POLLABLE 0x0004 +#define IEEE80211_CAPINFO_CF_POLLREQ 0x0008 +#define IEEE80211_CAPINFO_PRIVACY 0x0010 +#define IEEE80211_CAPINFO_SHORT_PREAMBLE 0x0020 +#define IEEE80211_CAPINFO_PBCC 0x0040 +#define IEEE80211_CAPINFO_CHNL_AGILITY 0x0080 +/* bits 8-9 are reserved (8 now for specturm management) */ +#define IEEE80211_CAPINFO_SPECTRUM_MGMT 0x0100 +#define IEEE80211_CAPINFO_SHORT_SLOTTIME 0x0400 +#define IEEE80211_CAPINFO_RSN 0x0800 +/* bit 12 is reserved */ +#define IEEE80211_CAPINFO_DSSSOFDM 0x2000 +/* bits 14-15 are reserved */ + +/* + * 802.11i/WPA information element (maximally sized). + */ +struct ieee80211_ie_wpa { + a_uint8_t wpa_id; /* IEEE80211_ELEMID_VENDOR */ + a_uint8_t wpa_len; /* length in bytes */ + a_uint8_t wpa_oui[3]; /* 0x00, 0x50, 0xf2 */ + a_uint8_t wpa_type; /* OUI type */ + a_uint16_t wpa_version; /* spec revision */ + a_uint32_t wpa_mcipher[1]; /* multicast/group key cipher */ + a_uint16_t wpa_uciphercnt; /* # pairwise key ciphers */ + a_uint32_t wpa_uciphers[8];/* ciphers */ + a_uint16_t wpa_authselcnt; /* authentication selector cnt*/ + a_uint32_t wpa_authsels[8];/* selectors */ + a_uint16_t wpa_caps; /* 802.11i capabilities */ + a_uint16_t wpa_pmkidcnt; /* 802.11i pmkid count */ + a_uint16_t wpa_pmkids[8]; /* 802.11i pmkids */ +} adf_os_packed; + +#ifndef _BYTE_ORDER +#error "Don't know native byte order" +#endif + +#ifndef IEEE80211N_IE +/* Temporary vendor specific IE for 11n pre-standard interoperability */ +#define HT_OUI 0x4c9000 +#endif + +struct ieee80211_ie_htcap_cmn { + a_uint16_t hc_cap; /* HT capabilities */ +#if _BYTE_ORDER == _BIG_ENDIAN + a_uint8_t hc_reserved : 3, /* B5-7 reserved */ + hc_mpdudensity : 3, /* B2-4 MPDU density (aka Minimum MPDU Start Spacing) */ + hc_maxampdu : 2; /* B0-1 maximum rx A-MPDU factor */ +#else + a_uint8_t hc_maxampdu : 2, /* B0-1 maximum rx A-MPDU factor */ + hc_mpdudensity : 3, /* B2-4 MPDU density (aka Minimum MPDU Start Spacing) */ + hc_reserved : 3; /* B5-7 reserved */ +#endif + a_uint8_t hc_mcsset[16]; /* supported MCS set */ + a_uint16_t hc_extcap; /* extended HT capabilities */ + a_uint32_t hc_txbf; /* txbf capabilities */ + a_uint8_t hc_antenna; /* antenna capabilities */ +} adf_os_packed; + +/* + * 802.11n HT Capability IE + */ +struct ieee80211_ie_htcap { + a_uint8_t hc_id; /* element ID */ + a_uint8_t hc_len; /* length in bytes */ + struct ieee80211_ie_htcap_cmn hc_ie; +} adf_os_packed; + +/* + * Temporary vendor private HT Capability IE + */ +struct vendor_ie_htcap { + a_uint8_t hc_id; /* element ID */ + a_uint8_t hc_len; /* length in bytes */ + a_uint8_t hc_oui[3]; + a_uint8_t hc_ouitype; + struct ieee80211_ie_htcap_cmn hc_ie; +} adf_os_packed; + +/* HT capability flags */ +#define IEEE80211_HTCAP_C_ADVCODING 0x0001 +#define IEEE80211_HTCAP_C_CHWIDTH40 0x0002 +#define IEEE80211_HTCAP_C_SMPOWERSAVE_STATIC 0x0000 /* Capable of SM Power Save (Static) */ +#define IEEE80211_HTCAP_C_SMPOWERSAVE_DYNAMIC 0x0004 /* Capable of SM Power Save (Dynamic) */ +#define IEEE80211_HTCAP_C_SM_RESERVED 0x0008 /* Reserved */ +#define IEEE80211_HTCAP_C_SM_ENABLED 0x000c /* SM enabled, no SM Power Save */ +#define IEEE80211_HTCAP_C_GREENFIELD 0x0010 +#define IEEE80211_HTCAP_C_SHORTGI20 0x0020 +#define IEEE80211_HTCAP_C_SHORTGI40 0x0040 +#define IEEE80211_HTCAP_C_TXSTBC 0x0080 +#define IEEE80211_HTCAP_C_RXSTBC 0x0100 /* 2 bits */ +#define IEEE80211_HTCAP_C_DELAYEDBLKACK 0x0400 +#define IEEE80211_HTCAP_C_MAXAMSDUSIZE 0x0800 /* 1 = 8K, 0 = 3839B */ +#define IEEE80211_HTCAP_C_DSSSCCK40 0x1000 +#define IEEE80211_HTCAP_C_PSMP 0x2000 +#define IEEE80211_HTCAP_C_INTOLERANT40 0x4000 +#define IEEE80211_HTCAP_C_LSIGTXOPPROT 0x8000 + +#define IEEE80211_HTCAP_C_SM_MASK 0x000c /* Spatial Multiplexing (SM) capabitlity bitmask */ + +/* B0-1 maximum rx A-MPDU factor 2^(13+Max Rx A-MPDU Factor) */ +enum { + IEEE80211_HTCAP_MAXRXAMPDU_8192, /* 2 ^ 13 */ + IEEE80211_HTCAP_MAXRXAMPDU_16384, /* 2 ^ 14 */ + IEEE80211_HTCAP_MAXRXAMPDU_32768, /* 2 ^ 15 */ + IEEE80211_HTCAP_MAXRXAMPDU_65536, /* 2 ^ 16 */ +}; +#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13 + +/* B2-4 MPDU density (usec) */ +enum { + IEEE80211_HTCAP_MPDUDENSITY_NA, /* No time restriction */ + IEEE80211_HTCAP_MPDUDENSITY_0_25, /* 1/4 usec */ + IEEE80211_HTCAP_MPDUDENSITY_0_5, /* 1/2 usec */ + IEEE80211_HTCAP_MPDUDENSITY_1, /* 1 usec */ + IEEE80211_HTCAP_MPDUDENSITY_2, /* 2 usec */ + IEEE80211_HTCAP_MPDUDENSITY_4, /* 4 usec */ + IEEE80211_HTCAP_MPDUDENSITY_8, /* 8 usec */ + IEEE80211_HTCAP_MPDUDENSITY_16, /* 16 usec */ +}; + +/* HT extended capability flags */ +#define IEEE80211_HTCAP_EXTC_PCO 0x0001 +#define IEEE80211_HTCAP_EXTC_TRANS_TIME_RSVD 0x0000 +#define IEEE80211_HTCAP_EXTC_TRANS_TIME_400 0x0002 /* 20-40 switch time */ +#define IEEE80211_HTCAP_EXTC_TRANS_TIME_1500 0x0004 /* in us */ +#define IEEE80211_HTCAP_EXTC_TRANS_TIME_5000 0x0006 +#define IEEE80211_HTCAP_EXTC_RSVD_1 0x00f8 +#define IEEE80211_HTCAP_EXTC_MCS_FEEDBACK_NONE 0x0000 +#define IEEE80211_HTCAP_EXTC_MCS_FEEDBACK_RSVD 0x0100 +#define IEEE80211_HTCAP_EXTC_MCS_FEEDBACK_UNSOL 0x0200 +#define IEEE80211_HTCAP_EXTC_MCS_FEEDBACK_FULL 0x0300 +#define IEEE80211_HTCAP_EXTC_RSVD_2 0xfc00 + +struct ieee80211_ie_htinfo_cmn { + a_uint8_t hi_ctrlchannel; /* control channel */ +#if _BYTE_ORDER == _BIG_ENDIAN + a_uint8_t hi_serviceinterval : 3, /* B5-7 svc interval granularity */ + hi_ctrlaccess : 1, /* B4 controlled access only */ + hi_rifsmode : 1, /* B3 rifs mode */ + hi_txchwidth : 1, /* B2 recommended xmiss width set */ + hi_extchoff : 2; /* B0-1 extension channel offset */ +#else + a_uint8_t hi_extchoff : 2, /* B0-1 extension channel offset */ + hi_txchwidth : 1, /* B2 recommended xmiss width set */ + hi_rifsmode : 1, /* B3 rifs mode */ + hi_ctrlaccess : 1, /* B4 controlled access only */ + hi_serviceinterval : 3; /* B5-7 svc interval granularity */ +#endif +#if _BYTE_ORDER == _BIG_ENDIAN + a_uint8_t hi_reserved0 : 3, /* B5-7 Reserved */ + hi_obssnonhtpresent: 1, /* B4 OBSS Non-HT STAs Present */ + hi_txburstlimit : 1, /* B3 Transmit Burst Limit */ + hi_nongfpresent : 1, /* B2 Non-greenfield STAs present */ + hi_opmode : 2; /* B0-1 Operating Mode */ +#else + a_uint8_t hi_opmode : 2, /* B0-1 Operating Mode */ + hi_nongfpresent : 1, /* B2 Non-greenfield STAs present */ + hi_txburstlimit : 1, /* B3 Transmit Burst Limit */ + hi_obssnonhtpresent: 1, /* B4 OBSS Non-HT STAs Present */ + hi_reserved0 : 3; /* B5-7 Reserved */ +#endif + a_uint8_t hi_reserved1; + a_uint16_t hi_miscflags; + + a_uint8_t hi_basicmcsset[16]; /* basic MCS set */ +} adf_os_packed; + +/* + * 802.11n HT Information IE + */ +struct ieee80211_ie_htinfo { + a_uint8_t hi_id; /* element ID */ + a_uint8_t hi_len; /* length in bytes */ + struct ieee80211_ie_htinfo_cmn hi_ie; +} adf_os_packed; + +/* + * Temporary vendor private HT Information IE + */ +struct vendor_ie_htinfo { + a_uint8_t hi_id; /* element ID */ + a_uint8_t hi_len; /* length in bytes */ + a_uint8_t hi_oui[3]; + a_uint8_t hi_ouitype; + struct ieee80211_ie_htinfo_cmn hi_ie; +} adf_os_packed; + +/* extension channel offset (2 bit signed number) */ +enum { + IEEE80211_HTINFO_EXTOFFSET_NA = 0, /* 0 no extension channel is present */ + IEEE80211_HTINFO_EXTOFFSET_ABOVE = 1, /* +1 extension channel above control channel */ + IEEE80211_HTINFO_EXTOFFSET_UNDEF = 2, /* -2 undefined */ + IEEE80211_HTINFO_EXTOFFSET_BELOW = 3 /* -1 extension channel below control channel*/ +}; + +/* recommended transmission width set */ +enum { + IEEE80211_HTINFO_TXWIDTH_20, + IEEE80211_HTINFO_TXWIDTH_2040 +}; + +/* operating flags */ +#define IEEE80211_HTINFO_OPMODE_PURE 0x00 /* no protection */ +#define IEEE80211_HTINFO_OPMODE_MIXED_PROT_OPT 0x01 /* prot optional (legacy device maybe present) */ +#define IEEE80211_HTINFO_OPMODE_MIXED_PROT_40 0x02 /* prot required (20 MHz) */ +#define IEEE80211_HTINFO_OPMODE_MIXED_PROT_ALL 0x03 /* prot required (legacy devices present) */ +#define IEEE80211_HTINFO_OPMODE_MASK 0x03 /* For protection 0x00-0x03 */ + +/* Non-greenfield STAs present */ +enum { + IEEE80211_HTINFO_NON_GF_NOT_PRESENT, /* Non-greenfield STAs not present */ + IEEE80211_HTINFO_NON_GF_PRESENT, /* Non-greenfield STAs present */ +}; + +/* Transmit Burst Limit */ +enum { + IEEE80211_HTINFO_TXBURST_UNLIMITED, /* Transmit Burst is unlimited */ + IEEE80211_HTINFO_TXBURST_LIMITED, /* Transmit Burst is limited */ +}; + +/* OBSS Non-HT STAs present */ +enum { + IEEE80211_HTINFO_OBBSS_NONHT_NOT_PRESENT, /* OBSS Non-HT STAs not present */ + IEEE80211_HTINFO_OBBSS_NONHT_PRESENT, /* OBSS Non-HT STAs present */ +}; + +/* misc flags */ +#define IEEE80211_HTINFO_BASICSTBCMCS 0x007F /* B0-6 basic STBC MCS */ +#define IEEE80211_HTINFO_DUALSTBCPROT 0x0080 /* B7 dual stbc protection */ +#define IEEE80211_HTINFO_SECONDARYBEACON 0x0100 /* B8 secondary beacon */ +#define IEEE80211_HTINFO_LSIGTXOPPROT 0x0200 /* B9 lsig txop prot full support */ +#define IEEE80211_HTINFO_PCOACTIVE 0x0400 /* B10 pco active */ +#define IEEE80211_HTINFO_PCOPHASE 0x0800 /* B11 pco phase */ + +/* RIFS mode */ +enum { + IEEE80211_HTINFO_RIFSMODE_PROHIBITED, /* use of rifs prohibited */ + IEEE80211_HTINFO_RIFSMODE_ALLOWED, /* use of rifs permitted */ +}; + +/* + * Management information element payloads. + */ + +enum { + IEEE80211_ELEMID_SSID = 0, + IEEE80211_ELEMID_RATES = 1, + IEEE80211_ELEMID_FHPARMS = 2, + IEEE80211_ELEMID_DSPARMS = 3, + IEEE80211_ELEMID_CFPARMS = 4, + IEEE80211_ELEMID_TIM = 5, + IEEE80211_ELEMID_IBSSPARMS = 6, + IEEE80211_ELEMID_COUNTRY = 7, + IEEE80211_ELEMID_REQINFO = 10, + IEEE80211_ELEMID_CHALLENGE = 16, + /* 17-31 reserved for challenge text extension */ + IEEE80211_ELEMID_PWRCNSTR = 32, + IEEE80211_ELEMID_PWRCAP = 33, + IEEE80211_ELEMID_TPCREQ = 34, + IEEE80211_ELEMID_TPCREP = 35, + IEEE80211_ELEMID_SUPPCHAN = 36, + IEEE80211_ELEMID_CHANSWITCHANN = 37, + IEEE80211_ELEMID_MEASREQ = 38, + IEEE80211_ELEMID_MEASREP = 39, + IEEE80211_ELEMID_QUIET = 40, + IEEE80211_ELEMID_IBSSDFS = 41, + IEEE80211_ELEMID_ERP = 42, + IEEE80211_ELEMID_HTCAP_ANA = 45, + IEEE80211_ELEMID_RSN = 48, + IEEE80211_ELEMID_XRATES = 50, + IEEE80211_ELEMID_HTCAP = 51, + IEEE80211_ELEMID_HTINFO = 52, + IEEE80211_ELEMID_EXTCHANSWITCHANN = 60, /* Fix this later as per ANA definition */ + IEEE80211_ELEMID_HTINFO_ANA = 61, + IEEE80211_ELEMID_TPC = 150, + IEEE80211_ELEMID_CCKM = 156, + IEEE80211_ELEMID_VENDOR = 221, /* vendor private */ +}; + +#define IEEE80211_CHANSWITCHANN_BYTES 5 +#define IEEE80211_EXTCHANSWITCHANN_BYTES 6 + +struct ieee80211_tim_ie { + a_uint8_t tim_ie; /* IEEE80211_ELEMID_TIM */ + a_uint8_t tim_len; + a_uint8_t tim_count; /* DTIM count */ + a_uint8_t tim_period; /* DTIM period */ + a_uint8_t tim_bitctl; /* bitmap control */ + a_uint8_t tim_bitmap[1]; /* variable-length bitmap */ +} adf_os_packed; + +struct ieee80211_country_ie { + a_uint8_t ie; /* IEEE80211_ELEMID_COUNTRY */ + a_uint8_t len; + a_uint8_t cc[3]; /* ISO CC+(I)ndoor/(O)utdoor */ + struct { + a_uint8_t schan; /* starting channel */ + a_uint8_t nchan; /* number channels */ + a_uint8_t maxtxpwr; /* tx power cap */ + } band[4] adf_os_packed; /* up to 4 sub bands */ +} adf_os_packed; + +#define IEEE80211_CHALLENGE_LEN 128 + +#define IEEE80211_SUPPCHAN_LEN 26 + +#define IEEE80211_RATE_BASIC 0x80 +#define IEEE80211_RATE_VAL 0x7f + +/* EPR information element flags */ +#define IEEE80211_ERP_NON_ERP_PRESENT 0x01 +#define IEEE80211_ERP_USE_PROTECTION 0x02 +#define IEEE80211_ERP_LONG_PREAMBLE 0x04 + +/* Atheros private advanced capabilities info */ +#define ATHEROS_CAP_TURBO_PRIME 0x01 +#define ATHEROS_CAP_COMPRESSION 0x02 +#define ATHEROS_CAP_FAST_FRAME 0x04 +/* bits 3-6 reserved */ +#define ATHEROS_CAP_BOOST 0x80 + +#define ATH_OUI 0x7f0300 /* Atheros OUI */ +#define ATH_OUI_TYPE 0x01 +#define ATH_OUI_SUBTYPE 0x01 +#define ATH_OUI_VERSION 0x00 +#define ATH_OUI_TYPE_XR 0x03 +#define ATH_OUI_VER_XR 0x01 +#define ATH_OUI_EXTCAP_TYPE 0x04 /* Atheros Extended Cap Type */ +#define ATH_OUI_EXTCAP_SUBTYPE 0x01 /* Atheros Extended Cap Sub-type */ +#define ATH_OUI_EXTCAP_VERSION 0x00 /* Atheros Extended Cap Version */ + +#define WPA_OUI 0xf25000 +#define WPA_OUI_TYPE 0x01 +#define WPA_VERSION 1 /* current supported version */ + +#define WSC_OUI 0x0050f204 + +#define WPA_CSE_NULL 0x00 +#define WPA_CSE_WEP40 0x01 +#define WPA_CSE_TKIP 0x02 +#define WPA_CSE_CCMP 0x04 +#define WPA_CSE_WEP104 0x05 + +#define WPA_ASE_NONE 0x00 +#define WPA_ASE_8021X_UNSPEC 0x01 +#define WPA_ASE_8021X_PSK 0x02 + +#define RSN_OUI 0xac0f00 +#define RSN_VERSION 1 /* current supported version */ + +#define RSN_CSE_NULL 0x00 +#define RSN_CSE_WEP40 0x01 +#define RSN_CSE_TKIP 0x02 +#define RSN_CSE_WRAP 0x03 +#define RSN_CSE_CCMP 0x04 +#define RSN_CSE_WEP104 0x05 + +#define RSN_ASE_NONE 0x00 +#define RSN_ASE_8021X_UNSPEC 0x01 +#define RSN_ASE_8021X_PSK 0x02 + +#define RSN_CAP_PREAUTH 0x01 + +#define WME_OUI 0xf25000 +#define WME_OUI_TYPE 0x02 +#define WME_INFO_OUI_SUBTYPE 0x00 +#define WME_PARAM_OUI_SUBTYPE 0x01 +#define WME_VERSION 1 + +/* WME stream classes */ +#define WME_AC_BE 0 /* best effort */ +#define WME_AC_BK 1 /* background */ +#define WME_AC_VI 2 /* video */ +#define WME_AC_VO 3 /* voice */ + +/* + * AUTH management packets + * + * octet algo[2] + * octet seq[2] + * octet status[2] + * octet chal.id + * octet chal.length + * octet chal.text[253] + */ + +typedef a_uint8_t *ieee80211_mgt_auth_t; + +#define IEEE80211_AUTH_ALGORITHM(auth) \ + ((auth)[0] | ((auth)[1] << 8)) +#define IEEE80211_AUTH_TRANSACTION(auth) \ + ((auth)[2] | ((auth)[3] << 8)) +#define IEEE80211_AUTH_STATUS(auth) \ + ((auth)[4] | ((auth)[5] << 8)) + +#define IEEE80211_AUTH_ALG_OPEN 0x0000 +#define IEEE80211_AUTH_ALG_SHARED 0x0001 +#define IEEE80211_AUTH_ALG_LEAP 0x0080 + +enum { + IEEE80211_AUTH_OPEN_REQUEST = 1, + IEEE80211_AUTH_OPEN_RESPONSE = 2, +}; + +enum { + IEEE80211_AUTH_SHARED_REQUEST = 1, + IEEE80211_AUTH_SHARED_CHALLENGE = 2, + IEEE80211_AUTH_SHARED_RESPONSE = 3, + IEEE80211_AUTH_SHARED_PASS = 4, +}; + +/* + * Reason codes + * + * Unlisted codes are reserved + */ + +enum { + IEEE80211_REASON_UNSPECIFIED = 1, + IEEE80211_REASON_AUTH_EXPIRE = 2, + IEEE80211_REASON_AUTH_LEAVE = 3, + IEEE80211_REASON_ASSOC_EXPIRE = 4, + IEEE80211_REASON_ASSOC_TOOMANY = 5, + IEEE80211_REASON_NOT_AUTHED = 6, + IEEE80211_REASON_NOT_ASSOCED = 7, + IEEE80211_REASON_ASSOC_LEAVE = 8, + IEEE80211_REASON_ASSOC_NOT_AUTHED = 9, + + IEEE80211_REASON_RSN_REQUIRED = 11, + IEEE80211_REASON_RSN_INCONSISTENT = 12, + IEEE80211_REASON_IE_INVALID = 13, + IEEE80211_REASON_MIC_FAILURE = 14, + + IEEE80211_STATUS_SUCCESS = 0, + IEEE80211_STATUS_UNSPECIFIED = 1, + IEEE80211_STATUS_CAPINFO = 10, + IEEE80211_STATUS_NOT_ASSOCED = 11, + IEEE80211_STATUS_OTHER = 12, + IEEE80211_STATUS_ALG = 13, + IEEE80211_STATUS_SEQUENCE = 14, + IEEE80211_STATUS_CHALLENGE = 15, + IEEE80211_STATUS_TIMEOUT = 16, + IEEE80211_STATUS_TOOMANY = 17, + IEEE80211_STATUS_BASIC_RATE = 18, + IEEE80211_STATUS_SP_REQUIRED = 19, + IEEE80211_STATUS_PBCC_REQUIRED = 20, + IEEE80211_STATUS_CA_REQUIRED = 21, + IEEE80211_STATUS_TOO_MANY_STATIONS = 22, + IEEE80211_STATUS_RATES = 23, + IEEE80211_STATUS_SHORTSLOT_REQUIRED = 25, + IEEE80211_STATUS_DSSSOFDM_REQUIRED = 26, + IEEE80211_STATUS_REFUSED = 37, + IEEE80211_STATUS_INVALID_PARAM = 38, +}; + +#define IEEE80211_WEP_KEYLEN 5 /* 40bit */ +#define IEEE80211_WEP_IVLEN 3 /* 24bit */ +#define IEEE80211_WEP_KIDLEN 1 /* 1 octet */ +#define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */ +#define IEEE80211_WEP_NKID 4 /* number of key ids */ + +/* + * 802.11i defines an extended IV for use with non-WEP ciphers. + * When the EXTIV bit is set in the key id byte an additional + * 4 bytes immediately follow the IV for TKIP. For CCMP the + * EXTIV bit is likewise set but the 8 bytes represent the + * CCMP header rather than IV+extended-IV. + */ +#define IEEE80211_WEP_EXTIV 0x20 +#define IEEE80211_WEP_EXTIVLEN 4 /* extended IV length */ +#define IEEE80211_WEP_MICLEN 8 /* trailing MIC */ +#define IEEE80211_WEP_ICVLEN 4 +#define IEEE80211_WAPI_MICLEN 16 /* trailing MIC */ +#define IEEE80211_WAPI_IVLEN 16 + +#define IEEE80211_CRC_LEN 4 + +/* + * Maximum acceptable MTU is: + * IEEE80211_MAX_LEN - WEP overhead - CRC - + * QoS overhead - RSN/WPA overhead + * Min is arbitrarily chosen > IEEE80211_MIN_LEN. The default + * mtu is Ethernet-compatible; it's set by ether_ifattach. + */ +#define IEEE80211_MTU_MAX 2290 +#define IEEE80211_MTU_MIN 32 + +#define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \ + (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) +#define IEEE80211_ACK_LEN \ + (sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN) +#define IEEE80211_MIN_LEN \ + (sizeof(struct ieee80211_frame_min) + IEEE80211_CRC_LEN) + +/* An 802.11 data frame can be one of three types: +1. An unaggregated frame: The maximum length of an unaggregated data frame is 2324 bytes + headers. +2. A data frame that is part of an AMPDU: The maximum length of an AMPDU may be upto 65535 bytes, but data frame is limited to 2324 bytes + header. +3. An AMSDU: The maximum length of an AMSDU is eihther 3839 or 7095 bytes. +The maximum frame length supported by hardware is 4095 bytes. +A length of 3839 bytes is chosen here to support unaggregated data frames, any size AMPDUs and 3839 byte AMSDUs. +*/ +#define IEEE80211N_MAX_FRAMELEN 3839 +#define IEEE80211N_MAX_LEN (IEEE80211N_MAX_FRAMELEN + IEEE80211_CRC_LEN + \ + (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN)) + +#define IEEE80211_TX_CHAINMASK_MIN 1 +#define IEEE80211_TX_CHAINMASK_MAX 7 + +#define IEEE80211_RX_CHAINMASK_MIN 1 +#define IEEE80211_RX_CHAINMASK_MAX 7 + +/* + * The 802.11 spec says at most 2007 stations may be + * associated at once. For most AP's this is way more + * than is feasible so we use a default of 128. This + * number may be overridden by the driver and/or by + * user configuration. + */ +#define IEEE80211_AID_MAX 2007 +#define IEEE80211_AID_DEF 128 + +#define IEEE80211_AID(b) ((b) &~ 0xc000) + +/* + * RTS frame length parameters. The default is specified in + * the 802.11 spec. The max may be wrong for jumbo frames. + */ +#define IEEE80211_RTS_DEFAULT 512 +#define IEEE80211_RTS_MIN 1 +#define IEEE80211_RTS_MAX 2346 + +/* + * Regulatory extention identifier for country IE. + */ +#define IEEE80211_REG_EXT_ID 201 + +#endif /* _NET80211_IEEE80211_H_ */ diff --git a/target_firmware/wlan/ieee80211_linux.h b/target_firmware/wlan/ieee80211_linux.h new file mode 100755 index 0000000..840360b --- /dev/null +++ b/target_firmware/wlan/ieee80211_linux.h @@ -0,0 +1,9 @@ +#define _LITTLE_ENDIAN 1234 /* LSB first: i386, vax */ +#define _BIG_ENDIAN 4321 /* MSB first: 68000, ibm, net */ +#if defined(ADF_LITTLE_ENDIAN_MACHINE) +#define _BYTE_ORDER _LITTLE_ENDIAN +#elif defined(ADF_BIG_ENDIAN_MACHINE) +#define _BYTE_ORDER _BIG_ENDIAN +#else +#error "Please fix asm/byteorder.h" +#endif diff --git a/target_firmware/wlan/ieee80211_node.h b/target_firmware/wlan/ieee80211_node.h new file mode 100755 index 0000000..cba72ba --- /dev/null +++ b/target_firmware/wlan/ieee80211_node.h @@ -0,0 +1,27 @@ +#ifndef _NET80211_IEEE80211_NODE_H_ +#define _NET80211_IEEE80211_NODE_H_ + +#include "_ieee80211.h" +#include "ieee80211.h" +#include /* for proto macros on node */ +#include + +#define IEEE80211_NODE_HASHSIZE 32 + +/* Node Table information for the Target */ + +struct ieee80211_node_table { + asf_tailq_head(, ieee80211_node) nt_node; /* information of all nodes */ + asf_list_head(, ieee80211_node) nt_hash[IEEE80211_NODE_HASHSIZE]; + asf_list_head(, ieee80211_wds_addr) nt_wds_hash[IEEE80211_NODE_HASHSIZE]; +}; + +#define IEEE80211_KEYBUF_SIZE 16 +#define IEEE80211_TID_SIZE 17 +#define IEEE80211_MICBUF_SIZE (8+8) /* space for both tx+rx keys */ + +struct ieee80211_key_target { + a_int32_t dummy ; +}; + +#endif diff --git a/target_firmware/wlan/ieee80211_output.c b/target_firmware/wlan/ieee80211_output.c new file mode 100755 index 0000000..43bfeda --- /dev/null +++ b/target_firmware/wlan/ieee80211_output.c @@ -0,0 +1,103 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "ieee80211_var.h" + +#include "_ieee80211.h" +#include "ieee80211.h" +#include + +a_status_t +ieee80211_tgt_crypto_encap(struct ieee80211_frame *wh, + struct ieee80211_node_target *ni, + a_uint8_t keytype) +{ +#define CRYPTO_KEY_TYPE_AES 2 +#define CRYPTO_KEY_TYPE_TKIP 3 +#define CRYPTO_KEY_TYPE_WAPI 4 +#define IEEE80211_WLAN_HDR_LEN 24 + + a_uint8_t *iv = NULL; + a_uint16_t tmp; + a_uint16_t offset = IEEE80211_WLAN_HDR_LEN; + a_uint8_t b1, b2; + + if (IEEE80211_QOS_HAS_SEQ(wh)) + offset += 4; // pad for 4 byte alignment + + iv = (a_uint8_t *) wh; + iv = iv + offset; + + switch (keytype) { + case CRYPTO_KEY_TYPE_AES: + ni->ni_iv16++; + if (ni->ni_iv16 == 0) + { + ni->ni_iv32++; + } + + *iv++ = (a_uint8_t) ni->ni_iv16; + *iv++ = (a_uint8_t) (ni->ni_iv16 >> 8); + *iv++ = 0x00; + *iv++ |= 0x20; + + tmp = (a_uint16_t) ni->ni_iv32; + *iv++ = (a_uint8_t) tmp; + *iv++ = (a_uint8_t) (tmp >> 8); + + tmp = (a_uint16_t) (ni->ni_iv32 >> 16); + *iv++ = (a_uint8_t) tmp; + *iv = (a_uint8_t) (tmp >> 8); + break; + case CRYPTO_KEY_TYPE_TKIP: + ni->ni_iv16++; + if (ni->ni_iv16 == 0) + { + ni->ni_iv32++; + } + + b1 = (a_uint8_t) (ni->ni_iv16 >> 8); + b2 = (b1 | 0x20) & 0x7f; + + *iv++ = b1; + *iv++ = b2; + + *iv++ = (a_uint8_t) ni->ni_iv16; + *iv++ |= 0x20; + + tmp = (a_uint16_t) ni->ni_iv32; + *iv++ = (a_uint8_t) tmp; + *iv++ = (a_uint8_t) (tmp >> 8); + + tmp = (a_uint16_t) (ni->ni_iv32 >> 16); + *iv++ = (a_uint8_t) tmp; + *iv = (a_uint8_t) (tmp >> 8); + break; + default: + break; + } + + return 1; + +#undef CRYPTO_KEY_TYPE_TKIP +#undef CRYPTO_KEY_TYPE_AES +#undef CRYPTO_KEY_TYPE_WAPI +#undef IEEE80211_WLAN_HDR_LEN +} + +adf_os_export_symbol(ieee80211_tgt_crypto_encap); + +#undef IEEE80211_ADDR_LEN diff --git a/target_firmware/wlan/ieee80211_proto.h b/target_firmware/wlan/ieee80211_proto.h new file mode 100755 index 0000000..59ba664 --- /dev/null +++ b/target_firmware/wlan/ieee80211_proto.h @@ -0,0 +1,22 @@ + +#ifndef _NET80211_IEEE80211_PROTO_H_ +#define _NET80211_IEEE80211_PROTO_H_ + + +#define IEEE80211_TXOP_TO_US(_txop) (a_uint32_t)(_txop) << 5 + + +/* + * 802.11 protocol implementation definitions. + */ + +enum ieee80211_state { + IEEE80211_S_INIT = 0, /* default state */ + IEEE80211_S_SCAN = 1, /* scanning */ + IEEE80211_S_JOIN = 2, /* join */ + IEEE80211_S_AUTH = 3, /* try to authenticate */ + IEEE80211_S_ASSOC = 4, /* try to assoc */ + IEEE80211_S_RUN = 5, /* associated */ +}; + +#endif diff --git a/target_firmware/wlan/ieee80211_var.h b/target_firmware/wlan/ieee80211_var.h new file mode 100755 index 0000000..48f040d --- /dev/null +++ b/target_firmware/wlan/ieee80211_var.h @@ -0,0 +1,209 @@ +#ifndef _NET80211_IEEE80211_VAR_H_ +#define _NET80211_IEEE80211_VAR_H_ + +#include"ieee80211_linux.h" +#include +#include"_ieee80211.h" +#include"ieee80211.h" +#include"ieee80211_node.h" +#include + +#define ieee80211_tgt_free_nbuf( _nbuf) adf_nbuf_free( _nbuf) +/* + * Built-in implementation for local skb free. Only interesting for platforms + * that pass skbs between OS instances. + */ +#define ieee80211_tgt_free_local_nbuf( _nbuf) ieee80211_tgt_free_nbuf( _nbuf) + + +#define IEEE80211_ADDR_EQ(a1,a2) (adf_os_mem_cmp(a1,a2,IEEE80211_ADDR_LEN) == 0) +#define IEEE80211_ADDR_COPY(dst,src) adf_os_mem_copy(dst, src, IEEE80211_ADDR_LEN) + +/* ic_flags */ +#define IEEE80211_F_FF 0x00000001 /* CONF: ATH FF enabled */ +#define IEEE80211_F_TURBOP 0x00000002 /* CONF: ATH Turbo enabled*/ +#define IEEE80211_F_PROMISC 0x00000004 /* STATUS: promiscuous mode */ +#define IEEE80211_F_ALLMULTI 0x00000008 /* STATUS: all multicast mode */ +/* NB: this is intentionally setup to be IEEE80211_CAPINFO_PRIVACY */ +#define IEEE80211_F_PRIVACY 0x00000010 /* CONF: privacy enabled */ +#define IEEE80211_F_PUREG 0x00000020 /* CONF: 11g w/o 11b sta's */ +#define IEEE80211_F_XRUPDATE 0x00000040 /* CONF: update beacon XR element*/ +#define IEEE80211_F_SCAN 0x00000080 /* STATUS: scanning */ +#define IEEE80211_F_XR 0x00000100 /* CONF: operate in XR mode */ +#define IEEE80211_F_SIBSS 0x00000200 /* STATUS: start IBSS */ +/* NB: this is intentionally setup to be IEEE80211_CAPINFO_SHORT_SLOTTIME */ +#define IEEE80211_F_SHSLOT 0x00000400 /* STATUS: use short slot time*/ +#define IEEE80211_F_PMGTON 0x00000800 /* CONF: Power mgmt enable */ +#define IEEE80211_F_DESBSSID 0x00001000 /* CONF: des_bssid is set */ +#define IEEE80211_F_WME 0x00002000 /* CONF: enable WME use */ +#define IEEE80211_F_BGSCAN 0x00004000 /* CONF: bg scan enabled */ +#define IEEE80211_F_SWRETRY 0x00008000 /* CONF: sw tx retry enabled */ +#define IEEE80211_F_TXPOW_FIXED 0x00010000 /* TX Power: fixed rate */ +#define IEEE80211_F_IBSSON 0x00020000 /* CONF: IBSS creation enable */ +#define IEEE80211_F_SHPREAMBLE 0x00040000 /* STATUS: use short preamble */ +#define IEEE80211_F_DATAPAD 0x00080000 /* CONF: do alignment pad */ +#define IEEE80211_F_USEPROT 0x00100000 /* STATUS: protection enabled */ +#define IEEE80211_F_USEBARKER 0x00200000 /* STATUS: use barker preamble*/ +#define IEEE80211_F_TIMUPDATE 0x00400000 /* STATUS: update beacon tim */ +#define IEEE80211_F_WPA1 0x00800000 /* CONF: WPA enabled */ +#define IEEE80211_F_WPA2 0x01000000 /* CONF: WPA2 enabled */ +#define IEEE80211_F_WPA 0x01800000 /* CONF: WPA/WPA2 enabled */ +#define IEEE80211_F_DROPUNENC 0x02000000 /* CONF: drop unencrypted */ +#define IEEE80211_F_COUNTERM 0x04000000 /* CONF: TKIP countermeasures */ +#define IEEE80211_F_HIDESSID 0x08000000 /* CONF: hide SSID in beacon */ +#define IEEE80211_F_NOBRIDGE 0x10000000 /* CONF: disable internal bridge */ +#define IEEE80211_F_WMEUPDATE 0x20000000 /* STATUS: update beacon wme */ +#define IEEE80211_F_DOTH 0x40000000 /* enable 11.h */ +#define IEEE80211_F_CHANSWITCH 0x80000000 /* force chanswitch */ + +/* ic_flags_ext */ +#define IEEE80211_FEXT_WDS 0x00000001 /* CONF: 4 addr allowed */ +#define IEEE80211_FEXT_COUNTRYIE 0x00000002 /* CONF: enable country IE */ +#define IEEE80211_FEXT_SCAN_PENDING 0x00000004 /* STATE: scan pending */ +#define IEEE80211_FEXT_BGSCAN 0x00000008 /* STATE: enable full bgscan completion */ +#define IEEE80211_FEXT_UAPSD 0x00000010 /* CONF: enable U-APSD */ +#define IEEE80211_FEXT_SLEEP 0x00000020 /* STATUS: sleeping */ +#define IEEE80211_FEXT_EOSPDROP 0x00000040 /* drop uapsd EOSP frames for test */ +#define IEEE80211_FEXT_MARKDFS 0x00000080 /* Enable marking of dfs interfernce */ +#define IEEE80211_FEXT_REGCLASS 0x00000100 /* CONF: send regclassids in country ie */ +#define IEEE80211_FEXT_MARKDFS 0x00000080 /* Enable marking of dfs interfernce */ +#define IEEE80211_FEXT_ERPUPDATE 0x00000200 /* STATUS: update ERP element */ +#define IEEE80211_FEXT_SWBMISS 0x00000400 /* CONF: use software beacon timer */ +#define IEEE80211_FEXT_BLKDFSCHAN 0x00000800 /* CONF: block the use of DFS channels */ +#define IEEE80211_FEXT_APPIE_UPDATE 0x00001000 /* STATE: beacon APP IE updated */ +#define IEEE80211_FAST_CC 0x00002000 /* CONF: Fast channel change */ +#define IEEE80211_C_AMPDU 0x00004000 /* CONF: A-MPDU supported */ +#define IEEE80211_C_AMSDU 0x00008000 /* CONF: A-MSDU supported */ +#define IEEE80211_C_HTPROT 0x00010000 /* CONF: HT traffic protected */ +#define IEEE80211_C_RESET 0x00020000 /* CONF: Reset once */ +#define IEEE80211_F_NONHT_AP 0x00040000 /* STATUS: HT traffic protected */ +#define IEEE80211_FEXT_HTUPDATE 0x00080000 /* STATUS: update HT element */ +#define IEEE80211_C_WDS_AUTODETECT 0x00100000 /* CONF: WDS auto Detect/DELBA */ +#define IEEE80211_C_RB 0x00200000 /* CONF: RB control */ +#define IEEE80211_C_RB_DETECT 0x00400000 /* CONF: RB auto detection */ +#define IEEE80211_C_NO_HTIE 0x00800000 /* CONF: No HT IE sending/parsing */ + +/* ic_caps */ +#define IEEE80211_C_WEP 0x00000001 /* CAPABILITY: WEP available */ +#define IEEE80211_C_TKIP 0x00000002 /* CAPABILITY: TKIP available */ +#define IEEE80211_C_AES 0x00000004 /* CAPABILITY: AES OCB avail */ +#define IEEE80211_C_AES_CCM 0x00000008 /* CAPABILITY: AES CCM avail */ +#define IEEE80211_C_CKIP 0x00000020 /* CAPABILITY: CKIP available */ +#define IEEE80211_C_FF 0x00000040 /* CAPABILITY: ATH FF avail */ +#define IEEE80211_C_TURBOP 0x00000080 /* CAPABILITY: ATH Turbo avail*/ +#define IEEE80211_C_IBSS 0x00000100 /* CAPABILITY: IBSS available */ +#define IEEE80211_C_PMGT 0x00000200 /* CAPABILITY: Power mgmt */ +#define IEEE80211_C_HOSTAP 0x00000400 /* CAPABILITY: HOSTAP avail */ +#define IEEE80211_C_AHDEMO 0x00000800 /* CAPABILITY: Old Adhoc Demo */ +#define IEEE80211_C_SWRETRY 0x00001000 /* CAPABILITY: sw tx retry */ +#define IEEE80211_C_TXPMGT 0x00002000 /* CAPABILITY: tx power mgmt */ +#define IEEE80211_C_SHSLOT 0x00004000 /* CAPABILITY: short slottime */ +#define IEEE80211_C_SHPREAMBLE 0x00008000 /* CAPABILITY: short preamble */ +#define IEEE80211_C_MONITOR 0x00010000 /* CAPABILITY: monitor mode */ +#define IEEE80211_C_TKIPMIC 0x00020000 /* CAPABILITY: TKIP MIC avail */ +#define IEEE80211_C_WPA1 0x00800000 /* CAPABILITY: WPA1 avail */ +#define IEEE80211_C_WPA2 0x01000000 /* CAPABILITY: WPA2 avail */ +#define IEEE80211_C_WPA 0x01800000 /* CAPABILITY: WPA1+WPA2 avail*/ +#define IEEE80211_C_BURST 0x02000000 /* CAPABILITY: frame bursting */ +#define IEEE80211_C_WME 0x04000000 /* CAPABILITY: WME avail */ +#define IEEE80211_C_WDS 0x08000000 /* CAPABILITY: 4-addr support */ +#define IEEE80211_C_WME_TKIPMIC 0x10000000 /* CAPABILITY: TKIP MIC for QoS frame */ +#define IEEE80211_C_BGSCAN 0x20000000 /* CAPABILITY: bg scanning */ +#define IEEE80211_C_UAPSD 0x40000000 /* CAPABILITY: UAPSD */ +#define IEEE80211_C_FASTCC 0x80000000 /* CAPABILITY: fast channel change */ + +/* XXX protection/barker? */ + +#define IEEE80211_C_CRYPTO 0x0000002f /* CAPABILITY: crypto alg's */ + +/* Atheros ABOLT definitions */ +#define IEEE80211_ABOLT_TURBO_G 0x01 /* Legacy Turbo G */ +#define IEEE80211_ABOLT_TURBO_PRIME 0x02 /* Turbo Prime */ +#define IEEE80211_ABOLT_COMPRESSION 0x04 /* Compression */ +#define IEEE80211_ABOLT_FAST_FRAME 0x08 /* Fast Frames */ +#define IEEE80211_ABOLT_BURST 0x10 /* Bursting */ +#define IEEE80211_ABOLT_WME_ELE 0x20 /* WME based cwmin/max/burst tuning */ +#define IEEE80211_ABOLT_XR 0x40 /* XR */ +#define IEEE80211_ABOLT_AR 0x80 /* AR switches out based on adjaced non-turbo traffic */ + +/* Atheros Advanced Capabilities ABOLT definition */ +#define IEEE80211_ABOLT_ADVCAP (IEEE80211_ABOLT_TURBO_PRIME | \ + IEEE80211_ABOLT_COMPRESSION | \ + IEEE80211_ABOLT_FAST_FRAME | \ + IEEE80211_ABOLT_XR | \ + IEEE80211_ABOLT_AR | \ + IEEE80211_ABOLT_BURST | \ + IEEE80211_ABOLT_WME_ELE) + +/* check if a capability was negotiated for use */ +#define IEEE80211_ATH_CAP(vap, ni, bit) \ + ((ni)->ni_ath_flags & (vap)->iv_ath_cap & (bit)) + +/* flags to VAP create function */ +#define IEEE80211_VAP_XR 0x10000 /* create a XR VAP without registering net device with OS*/ + +/* HT flags */ +#define IEEE80211_HTF_SHORTGI 0x0001 + + +/*************** Utility Routines ***/ +/* + * Return the size of the 802.11 header for a management or data frame. + */ +static __inline a_int32_t +ieee80211_hdrsize(const void *data) +{ + const struct ieee80211_frame *wh = data; + a_int32_t size = sizeof(struct ieee80211_frame); + + /* NB: we don't handle control frames */ + adf_os_assert((wh->i_fc[0]&IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL); + if ((wh->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) + size += IEEE80211_ADDR_LEN; + if (IEEE80211_QOS_HAS_SEQ(wh)) + size += sizeof(a_uint16_t); + return size; +} + +/* + * Return the size of the 802.11 header for a management or data frame. + */ +static __inline a_int32_t +ieee80211_hdrsize_padding(const void *data) +{ + const struct ieee80211_frame *wh = data; + a_int32_t size = sizeof(struct ieee80211_frame); + a_int32_t is4addr = (wh->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS; + a_int32_t is_qos = IEEE80211_QOS_HAS_SEQ(wh); + + /* NB: we don't handle control frames */ + adf_os_assert((wh->i_fc[0]&IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL); + if (is4addr) + size += IEEE80211_ADDR_LEN; + if (is_qos) + size += sizeof(a_uint16_t); + if (is4addr && is_qos) + size += sizeof(a_uint16_t); + return size; +} + +/* + * Like ieee80211_hdrsize, but handles any type of frame. + */ +static __inline a_int32_t +ieee80211_anyhdrsize(const void *data) +{ + const struct ieee80211_frame *wh = data; + + if ((wh->i_fc[0]&IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) { + switch (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) { + case IEEE80211_FC0_SUBTYPE_CTS: + case IEEE80211_FC0_SUBTYPE_ACK: + return sizeof(struct ieee80211_frame_ack); + } + return sizeof(struct ieee80211_frame_min); + } else + return ieee80211_hdrsize(data); +} + +#endif diff --git a/target_firmware/wlan/if_ath.c b/target_firmware/wlan/if_ath.c new file mode 100755 index 0000000..789725b --- /dev/null +++ b/target_firmware/wlan/if_ath.c @@ -0,0 +1,1936 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "if_ethersubr.h" +#include "if_llc.h" +#include "ieee80211_var.h" +#include "ieee80211_proto.h" +#include "if_athrate.h" +#include "if_athvar.h" +#include "ah_desc.h" + +static a_int32_t ath_numrxbufs = -1; +static a_int32_t ath_numrxdescs = -1; + +#if defined(PROJECT_MAGPIE) +uint32_t *init_htc_handle = 0; +#endif + +#define RX_ENDPOINT_ID 3 +#define ATH_CABQ_HANDLING_THRESHOLD 9000 +#define UAPSDQ_NUM 9 +#define CABQ_NUM 8 + +void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id, A_UINT8 *buffer, a_int32_t Length); +void owl_tgt_tx_tasklet(TQUEUE_ARG data); +static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt); +void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length); +static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen); +extern struct ath_buf * ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh); +extern void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt); +extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val); +extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq, owl_txq_state_t txqstate); +void owl_tgt_node_init(struct ath_node_target * an); +void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf); +void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host); + +/*************/ +/* Utilities */ +/*************/ + +#undef adf_os_cpu_to_le16 + +static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x) +{ + return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8)); +} + +/* + * Extend a 32 bit TSF to 64 bit, taking wrapping into account. + */ +static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp) +{ + u_int64_t tsf; + u_int32_t tsf_low; + u_int64_t tsf64; + + tsf = ath_hal_gettsf64(sc->sc_ah); + tsf_low = tsf & 0xffffffff; + tsf64 = (tsf & ~0xffffffffULL) | rstamp; + + if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000)) + tsf64 -= 0x100000000ULL; + + if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000)) + tsf64 += 0x100000000ULL; + + return tsf64; +} + +static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode) +{ + struct ath_hal *ah = sc->sc_ah; + const HAL_RATE_TABLE *rt; + + switch (mode) { + case IEEE80211_MODE_11NA: + sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11NA); + break; + case IEEE80211_MODE_11NG: + sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11NG); + break; + default: + return 0; + } + rt = sc->sc_rates[mode]; + if (rt == NULL) + return 0; + + return 1; +} + +static void ath_setcurmode(struct ath_softc_tgt *sc, + enum ieee80211_phymode mode) +{ + const HAL_RATE_TABLE *rt; + a_int32_t i; + + adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); + + rt = sc->sc_rates[mode]; + adf_os_assert(rt != NULL); + + for (i = 0; i < rt->rateCount; i++) { + sc->sc_rixmap[rt->info[i].rateCode] = i; + } + + sc->sc_currates = rt; + sc->sc_curmode = mode; + sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0); + +} + +void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id, + A_UINT8 *buffer, a_int32_t Length) +{ + adf_nbuf_t netbuf = ADF_NBUF_NULL; + a_uint8_t *pData; + + netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT, + sizeof(WMI_CMD_HDR) + Length); + + if (netbuf == ADF_NBUF_NULL) { + adf_os_print("Buf null\n"); + return; + } + + if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) { + pData = adf_nbuf_put_tail(netbuf, Length); + adf_os_mem_copy(pData, buffer, Length); + } + + WMI_SendEvent(handle, netbuf, evt_id, 0, Length); +} + +void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo, + A_UINT8 *buffer, a_int32_t Length) +{ + adf_nbuf_t netbuf = ADF_NBUF_NULL; + A_UINT8 *pData; + + netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY, + sizeof(WMI_CMD_HDR) + Length); + + if (netbuf == ADF_NBUF_NULL) { + adf_os_assert(0); + return; + } + + if (Length != 0 && buffer != NULL) { + pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length); + adf_os_mem_copy(pData, buffer, Length); + } + + WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length); +} + +static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index) +{ + a_int32_t i; + + for (i = 0; i < TARGET_NODE_MAX; i++) { + if(sc->sc_sta[i].ni.ni_vapindex == vap_index) + sc->sc_sta[i].an_valid = 0; + } +} + +a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp) +{ + if (sc->sc_curmode == IEEE80211_MODE_11NG) + return avp->av_minrateidx[0]; + else if (sc->sc_curmode == IEEE80211_MODE_11NA) + return avp->av_minrateidx[1]; + + return 0; +} + +/******/ +/* RX */ +/******/ + +static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc, + a_uint32_t size, a_uint32_t align) +{ + adf_nbuf_t skb; + + skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF, + RX_HEADER_SPACE, align); + return skb; +} + +static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds) +{ + struct ath_hal *ah = sc->sc_ah; + struct ath_rx_desc *ds_held; + a_uint8_t *anbdata; + a_uint32_t anblen; + + if (!sc->sc_rxdesc_held) { + sc->sc_rxdesc_held = ds; + return 0; + } + + ds_held = sc->sc_rxdesc_held; + sc->sc_rxdesc_held = ds; + ds = ds_held; + + if (ds->ds_nbuf == ADF_NBUF_NULL) { + ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz); + if (ds->ds_nbuf == ADF_NBUF_NULL) { + sc->sc_rxdesc_held = ds; + sc->sc_rx_stats.ast_rx_nobuf++; + return ENOMEM; + } + adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE); + adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info); + ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr; + } + + ds->ds_link = 0; + adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen); + + ath_hal_setuprxdesc(ah, ds, + adf_nbuf_tailroom(ds->ds_nbuf), + 0); + + if (sc->sc_rxlink == NULL) { + ath_hal_putrxbuf(ah, ds->ds_daddr); + } + else { + *sc->sc_rxlink = ds->ds_daddr; + } + sc->sc_rxlink = &ds->ds_link; + ath_hal_rxena(ah); + + return 0; +} + +static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf) +{ + struct ath_rx_desc *ds; + adf_nbuf_t buf_tmp; + adf_nbuf_queue_t nbuf_head; + + adf_nbuf_split_to_frag(buf, &nbuf_head); + ds = asf_tailq_first(&sc->sc_rxdesc_idle); + + while (ds) { + struct ath_rx_desc *ds_tmp; + buf_tmp = adf_nbuf_queue_remove(&nbuf_head); + + if (buf_tmp == NULL) { + break; + } + + BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp); + + ds_tmp = ds; + ds = asf_tailq_next(ds, ds_list); + + ath_rxdesc_init(sc, ds_tmp); + + asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list); + asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list); + } +} + +static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx; + + if (Endpt == RX_ENDPOINT_ID) { + sc->sc_rx_stats.ast_rx_done++; + ath_rx_complete(sc, buf); + } +} + +static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc) +{ + struct ath_hal *ah = sc->sc_ah; + struct ath_rx_buf *bf = NULL; + struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp; + a_int32_t retval; + a_uint32_t cnt = 0; + a_uint16_t frame_len = 0; + a_uint64_t tsf; + +#define PA2DESC(_sc, _pa) \ + ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ + ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) + + tsf = ath_hal_gettsf64(ah); + bf = asf_tailq_first(&sc->sc_rxbuf); + + ds = asf_tailq_first(&sc->sc_rxdesc); + ds_head = ds; + + while(ds) { + ++cnt; + + if (cnt == ath_numrxbufs - 1) { + adf_os_print("VERY LONG PACKET!!!!!\n"); + ds_tail = ds; + ds_tmp = ds_head; + while (ds_tmp) { + struct ath_rx_desc *ds_rmv; + adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE); + ds_rmv = ds_tmp; + ds_tmp = asf_tailq_next(ds_tmp, ds_list); + + if (ds_tmp == NULL) { + adf_os_print("ds_tmp is NULL\n"); + adf_os_assert(0); + } + + BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf); + ds_rmv->ds_nbuf = ADF_NBUF_NULL; + + if (ath_rxdesc_init(sc, ds_rmv) == 0) { + asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list); + asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list); + } + else { + asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list); + asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list); + } + + if (ds_rmv == ds_tail) { + break; + } + } + break; + } + + if (ds->ds_link == NULL) { + break; + } + + if (bf->bf_status & ATH_BUFSTATUS_DONE) { + continue; + } + + retval = ath_hal_rxprocdescfast(ah, ds, ds->ds_daddr, + PA2DESC(sc, ds->ds_link), &bf->bf_rx_status); + if (HAL_EINPROGRESS == retval) { + break; + } + + if (adf_nbuf_len(ds->ds_nbuf) == 0) { + adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen); + } + + frame_len += bf->bf_rx_status.rs_datalen; + + if (bf->bf_rx_status.rs_more == 0) { + adf_nbuf_queue_t nbuf_head; + adf_nbuf_queue_init(&nbuf_head); + + cnt = 0; + + ds_tail = ds; + ds = asf_tailq_next(ds, ds_list); + + ds_tmp = ds_head; + ds_head = asf_tailq_next(ds_tail, ds_list); + + while (ds_tmp) { + struct ath_rx_desc *ds_rmv; + + adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE); + adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf); + ds_tmp->ds_nbuf = ADF_NBUF_NULL; + + ds_rmv = ds_tmp; + ds_tmp = asf_tailq_next(ds_tmp, ds_list); + if (ds_tmp == NULL) { + adf_os_assert(0); + } + + if (ath_rxdesc_init(sc, ds_rmv) == 0) { + asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list); + asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list); + } else { + asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list); + asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list); + } + + if (ds_rmv == ds_tail) { + break; + } + } + + + bf->bf_rx_status.rs_datalen = frame_len; + frame_len = 0; + + bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head); + + bf->bf_status |= ATH_BUFSTATUS_DONE; + + bf = asf_tailq_next(bf, bf_list); + } + else { + ds = asf_tailq_next(ds, ds_list); + } + } + +#undef PA2DESC +} + +static a_int32_t ath_startrecv(struct ath_softc_tgt *sc) +{ + struct ath_hal *ah = sc->sc_ah; + struct ath_rx_desc *ds; + + sc->sc_rxbufsize = 1024+512+128; + sc->sc_rxlink = NULL; + + sc->sc_rxdesc_held = NULL; + + asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) { + a_int32_t error = ath_rxdesc_init(sc, ds); + if (error != 0) { + return error; + } + } + + ds = asf_tailq_first(&sc->sc_rxdesc); + ath_hal_putrxbuf(ah, ds->ds_daddr); + + return 0; +} + +static void ath_tgt_rx_tasklet(TQUEUE_ARG data) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data; + struct ath_rx_buf *bf = NULL; + struct ath_hal *ah = sc->sc_ah; + struct rx_frame_header *rxhdr; + struct ieee80211_frame *wh; + struct ath_rx_status *rxstats; + adf_nbuf_t skb = ADF_NBUF_NULL; + + do { + bf = asf_tailq_first(&sc->sc_rxbuf); + if (bf == NULL) { + break; + } + + if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) { + break; + } + + skb = bf->bf_skb; + if (skb == NULL) { + continue; + } + + asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list); + + bf->bf_skb = NULL; + + rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb, + sizeof(struct rx_frame_header)); + rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]); + adf_os_mem_copy(rxstats, &(bf->bf_rx_status), + sizeof(struct ath_rx_status)); + + rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp); + + HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb); + sc->sc_rx_stats.ast_rx_send++; + + next_buf: + bf->bf_status &= ~ATH_BUFSTATUS_DONE; + asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list); + + } while(1); + + sc->sc_imask |= HAL_INT_RX; + ath_hal_intrset(ah, sc->sc_imask); +} + +/*******************/ +/* Beacon Handling */ +/*******************/ + +/* + * Setup the beacon frame for transmit. + * FIXME: Short Preamble. + */ +static void ath_beacon_setup(struct ath_softc_tgt *sc, + struct ath_buf *bf, + struct ath_vap_target *avp) +{ + adf_nbuf_t skb = bf->bf_skb; + struct ath_hal *ah = sc->sc_ah; + struct ath_desc *ds; + a_int32_t flags, antenna; + const HAL_RATE_TABLE *rt; + a_uint8_t rix, rate; + HAL_11N_RATE_SERIES series[4] = {{ 0 }}; + + flags = HAL_TXDESC_NOACK; + + ds = bf->bf_desc; + ds->ds_link = 0; + ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr; + + rix = ath_get_minrateidx(sc, avp); + rt = sc->sc_currates; + rate = rt->info[rix].rateCode; + + ath_hal_setuptxdesc(ah, ds + , adf_nbuf_len(skb) + IEEE80211_CRC_LEN + , sizeof(struct ieee80211_frame) + , HAL_PKT_TYPE_BEACON + , MAX_RATE_POWER + , rate, 1 + , HAL_TXKEYIX_INVALID + , 0 + , flags + , 0 + , 0 + , 0 + , 0 + , ATH_COMP_PROC_NO_COMP_NO_CCS); + + ath_hal_filltxdesc(ah, ds + , asf_roundup(adf_nbuf_len(skb), 4) + , AH_TRUE + , AH_TRUE + , ds); + + series[0].Tries = 1; + series[0].Rate = rate; + series[0].ChSel = sc->sc_ic.ic_tx_chainmask; + series[0].RateFlags = 0; + ath_hal_set11n_ratescenario(ah, ds, 0, 0, 0, series, 4, 0); +} + +static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr, + adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt) +{ + struct ath_hal *ah = sc->sc_ah; + struct ath_tx_buf *bf; + a_uint8_t vap_index, *anbdata; + ath_beacon_hdr_t *bhdr; + struct ieee80211vap_target *vap; + a_uint32_t anblen; + struct ieee80211_frame *wh; + + if (!bc_hdr) { + adf_nbuf_peek_header(nbuf, &anbdata, &anblen); + bhdr = (ath_beacon_hdr_t *)anbdata; + } else { + adf_os_print("found bc_hdr! 0x%x\n", bc_hdr); + } + + vap_index = bhdr->vap_index; + adf_os_assert(vap_index < TARGET_VAP_MAX); + vap = &sc->sc_vap[vap_index]; + + wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf, + sizeof(ath_beacon_hdr_t)); + + bf = sc->sc_vap[vap_index].av_bcbuf; + adf_os_assert(bf); + bf->bf_endpt = EndPt; + + if (bf->bf_skb) { + adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE); + adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t)); + ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb); + } + + bf->bf_skb = nbuf; + + adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE); + adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info); + + ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]); + ath_hal_stoptxdma(ah, sc->sc_bhalq); + ath_hal_puttxbuf(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf)); + ath_hal_txstart(ah, sc->sc_bhalq); +} + +/******/ +/* TX */ +/******/ + +static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq) +{ + struct ath_hal *ah = sc->sc_ah; + + (void) ath_hal_stoptxdma(ah, txq->axq_qnum); +} + +static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq) +{ + owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED); +} + +static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq) +{ + owltgt_txq_drain(sc, txq); +} + +static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq) +{ + struct ath_hal *ah = sc->sc_ah; + a_uint16_t i; + struct ath_txq *txq = NULL; + struct ath_atx_tid *tid = NULL; + + ath_tx_status_clear(sc); + sc->sc_tx_draining = 1; + + (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); + + for (i = 0; i < HAL_NUM_TX_QUEUES; i++) + if (ATH_TXQ_SETUP(sc, i)) + ath_tx_stopdma(sc, ATH_TXQ(sc, i)); + + for (i = 0; i < HAL_NUM_TX_QUEUES; i++) + if (ATH_TXQ_SETUP(sc, i)) { + owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED); + + txq = ATH_TXQ(sc,i); + while (!asf_tailq_empty(&txq->axq_tidq)){ + TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem); + if(tid == NULL) + break; + tid->sched = AH_FALSE; + ath_tgt_tid_drain(sc,tid); + } + } + + sc->sc_tx_draining = 0; +} + +static void ath_tgt_txq_setup(struct ath_softc_tgt *sc) +{ + a_int32_t qnum; + struct ath_txq *txq; + + sc->sc_txqsetup=0; + + for (qnum=0;qnumsc_txq[qnum]; + txq->axq_qnum = qnum; + txq->axq_link = NULL; + asf_tailq_init(&txq->axq_q); + txq->axq_depth = 0; + txq->axq_linkbuf = NULL; + asf_tailq_init(&txq->axq_tidq); + sc->sc_txqsetup |= 1<sc_uapsdq = &sc->sc_txq[UAPSDQ_NUM]; + sc->sc_cabq = &sc->sc_txq[CABQ_NUM]; + + sc->sc_ac2q[WME_AC_BE] = &sc->sc_txq[0]; + sc->sc_ac2q[WME_AC_BK] = &sc->sc_txq[1]; + sc->sc_ac2q[WME_AC_VI] = &sc->sc_txq[2]; + sc->sc_ac2q[WME_AC_VO] = &sc->sc_txq[3]; + + return; +#undef N +} + +static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, + adf_nbuf_t buf, void *ServiceCtx) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx; + + ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt); +} + +static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, + adf_nbuf_t buf, void *ServiceCtx) +{ +} + +static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, + adf_nbuf_t buf, void *ServiceCtx) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx; + + ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt); +} + +static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt, + adf_nbuf_t hdr_buf, adf_nbuf_t buf, + void *ServiceCtx) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx; + struct ath_tx_buf *bf; + a_uint8_t *data; + a_uint32_t len; + ath_data_hdr_t *dh; + struct ath_node_target *an; + struct ath_atx_tid *tid; + + if (!hdr_buf) { + adf_nbuf_peek_header(buf, &data, &len); + adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t)); + } else { + adf_nbuf_peek_header(hdr_buf, &data, &len); + } + + adf_os_assert(len >= sizeof(ath_data_hdr_t)); + dh = (ath_data_hdr_t *)data; + + an = &sc->sc_sta[dh->ni_index]; + tid = ATH_AN_2_TID(an, dh->tidno); + + sc->sc_tx_stats.tx_tgt++; + + bf = ath_tgt_tx_prepare(sc, buf, dh); + if (!bf) { + ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf); + return; + } + + bf->bf_endpt = EndPt; + bf->bf_cookie = dh->cookie; + + if (tid->flag & TID_AGGR_ENABLED) + ath_tgt_handle_aggr(sc, bf); + else + ath_tgt_handle_normal(sc, bf); +} + +static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf, + adf_nbuf_t buf, void *ServiceCtx) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx; + struct ath_hal *ah = sc->sc_ah; + a_uint64_t tsf; + a_uint32_t tmp; + +#ifdef ATH_ENABLE_CABQ + tsf = ath_hal_gettsf64(ah); + tmp = tsf - sc->sc_swba_tsf; + + if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) { + HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf); + return; + } + + tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx); +#endif +} + +/***********************/ +/* Descriptor Handling */ +/***********************/ + +static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc, + struct ath_descdma *dd, ath_bufhead *head, + const char *name, a_int32_t nbuf, a_int32_t ndesc, + a_uint32_t bfSize, a_uint32_t descSize) +{ +#define DS2PHYS(_dd, _ds) \ + ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) + + struct ath_desc *ds; + struct ath_buf *bf; + a_int32_t i, bsize, error; + a_uint8_t *bf_addr; + a_uint8_t *ds_addr; + + dd->dd_name = name; + dd->dd_desc_len = descSize * nbuf * ndesc; + + dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev, + dd->dd_desc_len, 1, &dd->dd_desc_dmamap); + dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap); + if (dd->dd_desc == NULL) { + error = -ENOMEM; + goto fail; + } + ds = dd->dd_desc; + + bsize = bfSize * nbuf; + bf = adf_os_mem_alloc(bsize); + if (bf == NULL) { + error = -ENOMEM; + goto fail2; + } + adf_os_mem_set(bf, 0, bsize); + dd->dd_bufptr = bf; + + bf_addr = (a_uint8_t *)bf; + ds_addr = (a_uint8_t *)ds; + + asf_tailq_init(head); + + for (i = 0; i < nbuf; i++) { + a_int32_t j; + + if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) { + goto fail2; + } + + bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds; + for (j = 0; j < ndesc; j++) + ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize))); + + ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0)); + + adf_nbuf_queue_init(&bf->bf_skbhead); + asf_tailq_insert_tail(head, bf, bf_list); + + bf_addr += bfSize; + ds_addr += (ndesc * descSize); + bf = (struct ath_buf *)bf_addr; + ds = (struct ath_desc *)ds_addr; + } + + return 0; +fail2: + adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len, + 1, dd->dd_desc, dd->dd_desc_dmamap); +fail: + adf_os_mem_set(dd, 0, sizeof(*dd)); + adf_os_assert(0); + return error; + +#undef DS2PHYS +} + +static void ath_descdma_cleanup(struct ath_softc_tgt *sc, + struct ath_descdma *dd, + ath_bufhead *head, a_int32_t dir) +{ + struct ath_tx_buf *bf; + struct ieee80211_node *ni; + + asf_tailq_foreach(bf, head, bf_list) { + if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) { + adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir); + while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) { + ath_free_rx_skb(sc, + adf_nbuf_queue_remove(&bf->bf_skbhead)); + } + bf->bf_skb = NULL; + } else if (bf->bf_skb != NULL) { + adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir); + ath_free_rx_skb(sc, bf->bf_skb); + bf->bf_skb = NULL; + } + + adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap); + + ni = bf->bf_node; + bf->bf_node = NULL; + } + + adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len, + 1, dd->dd_desc, dd->dd_desc_dmamap); + + asf_tailq_init(head); + adf_os_mem_free(dd->dd_bufptr); + adf_os_mem_set(dd, 0, sizeof(*dd)); +} + +static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc) +{ +#define DS2PHYS(_dd, _ds) \ + ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) + + a_int32_t error; + struct ath_tx_buf *bf; + + if(ath_numrxbufs == -1) + ath_numrxbufs = ATH_RXBUF; + + if (ath_numrxdescs == -1) + ath_numrxdescs = ATH_RXDESC; + + error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, + "rx", ath_numrxdescs, 1, + sizeof(struct ath_rx_buf), + sizeof(struct ath_rx_desc)); + if (error != 0) + return error; + + a_uint32_t i; + struct ath_descdma *dd = &sc->sc_rxdma; + struct ath_rx_desc *ds = dd->dd_desc; + struct ath_rx_desc *ds_prev = NULL; + + asf_tailq_init(&sc->sc_rxdesc); + asf_tailq_init(&sc->sc_rxdesc_idle); + + for (i = 0; i < ath_numrxdescs; i++, ds++) { + + if (ds->ds_nbuf != ADF_NBUF_NULL) { + ds->ds_nbuf = ADF_NBUF_NULL; + } + + if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) { + adf_os_assert(0); + } + + ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds); + + if (ds_prev) { + ds_prev->ds_link = ds->ds_daddr; + } + + ds->ds_link = 0; + ds_prev = ds; + + asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list); + } + + error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, + "tx", ATH_TXBUF + 1, ATH_TXDESC, + sizeof(struct ath_tx_buf), + sizeof(struct ath_tx_desc)); + if (error != 0) { + ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, + ADF_OS_DMA_FROM_DEVICE); + return error; + } + + error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, + "beacon", ATH_BCBUF, 1, + sizeof(struct ath_tx_buf), + sizeof(struct ath_tx_desc)); + if (error != 0) { + ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf, + ADF_OS_DMA_TO_DEVICE); + ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, + ADF_OS_DMA_FROM_DEVICE); + return error; + } + + bf = asf_tailq_first(&sc->sc_txbuf); + bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0; + asf_tailq_remove(&sc->sc_txbuf, bf, bf_list); + + sc->sc_txbuf_held = bf; + + return 0; + +#undef DS2PHYS +} + +static void ath_desc_free(struct ath_softc_tgt *sc) +{ + asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list); + + sc->sc_txbuf_held = NULL; + + if (sc->sc_txdma.dd_desc_len != 0) + ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf, + ADF_OS_DMA_TO_DEVICE); + if (sc->sc_rxdma.dd_desc_len != 0) + ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, + ADF_OS_DMA_FROM_DEVICE); +} + +/**********************/ +/* Interrupt Handling */ +/**********************/ + +adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl; + struct ath_hal *ah = sc->sc_ah; + struct ieee80211com_target *ic = &sc->sc_ic; + HAL_INT status; + + if (sc->sc_invalid) + return ADF_OS_IRQ_NONE; + + if (!ath_hal_intrpend(ah)) + return ADF_OS_IRQ_NONE; + + ath_hal_getisr(ah, &status); + + status &= sc->sc_imask; + + if (status & HAL_INT_FATAL) { + ath_hal_intrset(ah, 0); + ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq); + } else { + if (status & HAL_INT_SWBA) { + WMI_SWBA_EVENT swbaEvt; + struct ath_txq *txq = ATH_TXQ(sc, 8); + + swbaEvt.tsf = ath_hal_gettsf64(ah); + swbaEvt.beaconPendingCount = ath_hal_numtxpending(ah, sc->sc_bhalq); + sc->sc_swba_tsf = ath_hal_gettsf64(ah); + + wmi_event(sc->tgt_wmi_handle, + WMI_SWBA_EVENTID, + &swbaEvt, + sizeof(WMI_SWBA_EVENT)); + + ath_tx_draintxq(sc, txq); + } + + if (status & HAL_INT_RXORN) + sc->sc_int_stats.ast_rxorn++; + + if (status & HAL_INT_RXEOL) + sc->sc_int_stats.ast_rxeol++; + + if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) { + if (status & HAL_INT_RX) + sc->sc_int_stats.ast_rx++; + + ath_uapsd_processtriggers(sc); + + sc->sc_imask &= ~HAL_INT_RX; + ath_hal_intrset(ah, sc->sc_imask); + + ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq); + } + + if (status & HAL_INT_TXURN) { + sc->sc_int_stats.ast_txurn++; + ath_hal_updatetxtriglevel(ah, AH_TRUE); + } + + ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq); + + if (status & HAL_INT_BMISS) { + ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq); + } + + if (status & HAL_INT_GTT) + sc->sc_int_stats.ast_txto++; + + if (status & HAL_INT_CST) + sc->sc_int_stats.ast_cst++; + } + + return ADF_OS_IRQ_HANDLED; +} + +static void ath_fatal_tasklet(TQUEUE_ARG data ) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data; + + wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0); +} + +static void ath_bmiss_tasklet(TQUEUE_ARG data) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data; + + wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0); +} + +/****************/ +/* WMI Commands */ +/****************/ + +static void ath_enable_intr_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_hal *ah = sc->sc_ah; + a_uint32_t intr; + + if (data) + intr = (*(a_uint32_t *)data); + + intr = adf_os_ntohl(intr); + + if (intr & HAL_INT_SWBA) { + sc->sc_imask |= HAL_INT_SWBA; + } else { + sc->sc_imask &= ~HAL_INT_SWBA; + } + + if (intr & HAL_INT_BMISS) { + sc->sc_imask |= HAL_INT_BMISS; + } + + ath_hal_intrset(ah, sc->sc_imask); + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0); +} + +static void ath_init_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_hal *ah = sc->sc_ah; + a_uint32_t stbcsupport; + + sc->sc_imask = HAL_INT_RX | HAL_INT_TX + | HAL_INT_RXEOL | HAL_INT_RXORN + | HAL_INT_FATAL | HAL_INT_GLOBAL; + + sc->sc_imask |= HAL_INT_GTT; + + if (ath_hal_htsupported(ah)) + sc->sc_imask |= HAL_INT_CST; + +#ifdef MAGPIE_MERLIN + if (ath_hal_txstbcsupport(ah, &stbcsupport)) + sc->sc_txstbcsupport = stbcsupport; + + if (ath_hal_rxstbcsupport(ah, &stbcsupport)) + sc->sc_rxstbcsupport = stbcsupport; +#endif + adf_os_setup_intr(sc->sc_dev, ath_intr); + ath_hal_intrset(ah, sc->sc_imask); + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo, + A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + + struct fusion_stats { + a_uint32_t ast_rx; + a_uint32_t ast_rxorn; + a_uint32_t ast_rxeol; + a_uint32_t ast_txurn; + a_uint32_t ast_txto; + a_uint32_t ast_cst; + }; + + struct fusion_stats stats; + + stats.ast_rx = sc->sc_int_stats.ast_rx; + stats.ast_rxorn = sc->sc_int_stats.ast_rxorn; + stats.ast_rxeol = sc->sc_int_stats.ast_rxeol; + stats.ast_txurn = sc->sc_int_stats.ast_txurn; + stats.ast_txto = sc->sc_int_stats.ast_txto; + stats.ast_cst = sc->sc_int_stats.ast_cst; + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats)); +} + +static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo, + A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + + struct fusion_stats { + a_uint32_t ast_tx_xretries; + a_uint32_t ast_tx_fifoerr; + a_uint32_t ast_tx_filtered; + a_uint32_t ast_tx_timer_exp; + a_uint32_t ast_tx_shortretry; + a_uint32_t ast_tx_longretry; + + a_uint32_t tx_qnull; + a_uint32_t tx_noskbs; + a_uint32_t tx_nobufs; + }; + + struct fusion_stats stats; + + stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries; + stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr; + stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered; + stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp; + stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry; + stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry; + stats.tx_qnull = sc->sc_tx_stats.tx_qnull; + stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs; + stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs; + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats)); +} + +static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo, + A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + + struct fusion_stats { + a_uint32_t ast_rx_nobuf; + a_uint32_t ast_rx_send; + a_uint32_t ast_rx_done; + }; + + struct fusion_stats stats; + + stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf; + stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send; + stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done; + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats)); +} + +static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo, + A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct wmi_fw_version ver; + + ver.major = ATH_VERSION_MAJOR; + ver.minor = ATH_VERSION_MINOR; + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver)); +} + +static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo, + A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_aggr_info *aggr = (struct ath_aggr_info *)data; + a_uint8_t nodeindex = aggr->nodeindex; + a_uint8_t tidno = aggr->tidno; + struct ath_node_target *an = NULL ; + struct ath_atx_tid *tid = NULL; + + if (nodeindex >= TARGET_NODE_MAX) { + goto done; + } + + an = &sc->sc_sta[nodeindex]; + if (!an->an_valid) { + goto done; + } + + if (tidno >= WME_NUM_TID) { + adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n", + __FUNCTION__, tidno, nodeindex); + goto done; + } + + tid = ATH_AN_2_TID(an, tidno); + + if (aggr->aggr_enable) { + tid->flag |= TID_AGGR_ENABLED; + } else if ( tid->flag & TID_AGGR_ENABLED ) { + tid->flag &= ~TID_AGGR_ENABLED; + ath_tgt_tx_cleanup(sc, an, tid, 1); + } +done: + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo, + A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ieee80211com_target *ic = (struct ieee80211com_target * )data; + struct ieee80211com_target *ictgt = &sc->sc_ic ; + + adf_os_mem_copy(ictgt, ic, sizeof(struct ieee80211com_target)); + + ictgt->ic_ampdu_limit = adf_os_ntohl(ic->ic_ampdu_limit); + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, + A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ieee80211vap_target *vap; + a_uint8_t vap_index; + + vap = (struct ieee80211vap_target *)data; + + vap->iv_rtsthreshold = adf_os_ntohs(vap->iv_rtsthreshold); + vap->iv_opmode = adf_os_ntohl(vap->iv_opmode); + + vap_index = vap->iv_vapindex; + + adf_os_assert(sc->sc_vap[vap_index].av_valid == 0); + + adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap, + VAP_TARGET_SIZE); + + sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf)); + sc->sc_vap[vap_index].av_valid = 1; + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_node_create_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ieee80211_node_target *node; + a_uint8_t vap_index; + a_uint8_t node_index; + + node = (struct ieee80211_node_target *)data; + + node_index = node->ni_nodeindex; + + node->ni_htcap = adf_os_ntohs(node->ni_htcap); + node->ni_flags = adf_os_ntohs(node->ni_flags); + node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu); + + adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node, + NODE_TARGET_SIZE); + + vap_index = sc->sc_sta[node_index].ni.ni_vapindex; + sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap); + if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1) + sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index; + + sc->sc_sta[node_index].an_valid = 1; + sc->sc_sta[node_index].ni.ni_txseqmgmt = 0; + sc->sc_sta[node_index].ni.ni_iv16 = 0; + sc->sc_sta[node_index].ni.ni_iv32 = 0; + + owl_tgt_node_init(&sc->sc_sta[node_index]); + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + a_uint8_t node_index; + a_uint8_t *nodedata; + + nodedata = (a_uint8_t *)data; + node_index = *nodedata; + sc->sc_sta[node_index].an_valid = 0; + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_node_update_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ieee80211_node_target *node; + a_uint8_t vap_index; + a_uint8_t node_index; + + node = (struct ieee80211_node_target *)data; + + node_index = node->ni_nodeindex; + + node->ni_htcap = adf_os_ntohs(node->ni_htcap); + node->ni_flags = adf_os_ntohs(node->ni_flags); + node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu); + + adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node, + NODE_TARGET_SIZE); + + vap_index = sc->sc_sta[node_index].ni.ni_vapindex; + sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap); + + sc->sc_sta[node_index].ni.ni_txseqmgmt = 0; + sc->sc_sta[node_index].ni.ni_iv16 = 0; + sc->sc_sta[node_index].ni.ni_iv32 = 0; + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_hal *ah = sc->sc_ah; + a_uint32_t addr; + a_uint32_t val[32]; + int i; + + for (i = 0; i < datalen; i += sizeof(a_int32_t)) { + addr = *(a_uint32_t *)(data + i); + addr = adf_os_ntohl(addr); + + if ((addr & 0xffffe000) == 0x2000) { + /* SEEPROM */ + ath_hal_reg_read_target(ah, addr); + if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) { + adf_os_print("SEEPROM Read fail: 0x%08x\n", addr); + } + val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff); + } else if (addr > 0xffff) { + val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr; + } else + val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr); + + val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]); + } + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen); +} + +static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_hal *ah = sc->sc_ah; + int i; + struct registerWrite { + a_uint32_t reg; + a_uint32_t val; + }*t; + + for (i = 0; i < datalen; i += sizeof(struct registerWrite)) { + t = (struct registerWrite *)(data+i); + + if( t->reg > 0xffff ) { + a_uint32_t *pReg = (a_uint32_t *)t->reg; + + *pReg = t->val; + +#if defined(PROJECT_K2) + if( t->reg == 0x50040 ) { + static uint8_t flg=0; + + if( flg == 0 ) { + A_CLOCK_INIT(117); + A_UART_HWINIT(117*1000*1000, 19200); + flg = 1; + } + } +#endif + } else { +#if defined(PROJECT_K2) + if( t->reg == 0x7014 ) { + static uint8_t resetPLL = 0; + a_uint32_t *pReg; + + if( resetPLL == 0 ) { + t->reg = 0x50044; + pReg = (a_uint32_t *)t->reg; + *pReg = 0; + ath_hal_reg_write_target(ah, 0x786c, + ath_hal_reg_read_target(ah,0x786c) | 0x6000000); + ath_hal_reg_write_target(ah, 0x786c, + ath_hal_reg_read_target(ah,0x786c) & (~0x6000000)); + *pReg = 0x20; + resetPLL = 1; + } + t->reg = 0x7014; + } +#elif defined(PROJECT_MAGPIE) && !defined (FPGA) + if( t->reg == 0x7014 ){ + static uint8_t resetPLL = 0; + + if( resetPLL == 0 ) { + ath_hal_reg_write_target(ah, 0x7890, + ath_hal_reg_read_target(ah,0x7890) | 0x1800000); + ath_hal_reg_write_target(ah, 0x7890, + ath_hal_reg_read_target(ah,0x7890) & (~0x1800000)); + resetPLL = 1; + } + } +#endif + ath_hal_reg_write_target(ah,t->reg,t->val); + } + } + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_vap_delete_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + a_uint8_t vap_index; + + vap_index = *(a_uint8_t *)data; + + sc->sc_vap[vap_index].av_valid = 0; + sc->sc_vap[vap_index].av_bcbuf = NULL; + ath_node_vdelete_tgt(sc, vap_index); + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_disable_intr_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_hal *ah = sc->sc_ah; + + ath_hal_intrset(ah, 0); + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0); +} + +static void ath_flushrecv_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_buf *bf; + + asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list) + if (bf->bf_skb != NULL) { + adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, + ADF_OS_DMA_FROM_DEVICE); + ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead)); + bf->bf_skb = NULL; + } + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, + A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + a_uint32_t q = *(a_uint32_t *)data; + struct ath_txq *txq = NULL; + + q = adf_os_ntohl(q); + txq = ATH_TXQ(sc, q); + + ath_tx_draintxq(sc, txq); + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_draintxq_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data; + + ath_draintxq(Context, b); + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + + ath_hal_aborttxdma(sc->sc_ah); + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_aborttxq_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + a_uint16_t i; + + for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { + if (ATH_TXQ_SETUP(sc, i)) + ath_tx_draintxq(sc, ATH_TXQ(sc,i)); + } + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_hal *ah = sc->sc_ah; + a_uint32_t q; + + if (data) + q = *(a_uint32_t *)data; + + q = adf_os_ntohl(q); + ath_hal_stoptxdma(ah, q); + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_startrecv_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + + ath_startrecv(sc); + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_stoprecv_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_hal *ah = sc->sc_ah; + + ath_hal_stoppcurecv(ah); + ath_hal_setrxfilter(ah, 0); + ath_hal_stopdmarecv(ah); + + sc->sc_rxlink = NULL; + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void ath_setcurmode_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + a_uint16_t mode; + struct ath_hal *ah = sc->sc_ah; + + mode= *((a_uint16_t *)data); + mode = adf_os_ntohs(mode); + + ath_setcurmode(sc, mode); + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static a_uint32_t ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, + A_UINT8 *data, a_int32_t datalen) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct ath_hal *ah = sc->sc_ah; + + ath_desc_free(sc); + ath_hal_detach(ah); + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); + adf_os_mem_free(sc); +} + +static void handle_echo_command(void *pContext, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length) +{ + wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length); +} + +static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length) + +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer; + + a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag); + + ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap, + wmi_data->vap_state, + capflag, + &wmi_data->rs); + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer; + + a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag); + + ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index], + wmi_data->isNew, + capflag, + &wmi_data->rs); + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length) +{ + adf_os_assert(0); +} + +static void ath_rc_mask_tgt(void *Context, A_UINT16 Command, + A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context; + struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer; + int idx, band, i; + + idx = wmi_data->vap_index; + band = wmi_data->band; + + sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask); + + if (sc->sc_vap[idx].av_rate_mask[band]) { + for (i = 0; i < RATE_TABLE_SIZE; i++) { + if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) { + sc->sc_vap[idx].av_minrateidx[band] = i; + break; + } + } + } else { + sc->sc_vap[idx].av_minrateidx[band] = 0; + } + + wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0); +} + +static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] = +{ + {handle_echo_command, WMI_ECHO_CMDID, 0}, + {dispatch_magpie_sys_cmds, WMI_ACCESS_MEMORY_CMDID, 0}, + {ath_get_tgt_version, WMI_GET_FW_VERSION, 0}, + {ath_disable_intr_tgt, WMI_DISABLE_INTR_CMDID, 0}, + {ath_enable_intr_tgt, WMI_ENABLE_INTR_CMDID, 0}, + {ath_init_tgt, WMI_ATH_INIT_CMDID, 0}, + {ath_aborttxq_tgt, WMI_ABORT_TXQ_CMDID, 0}, + {ath_stop_tx_dma_tgt, WMI_STOP_TX_DMA_CMDID, 0}, + {ath_aborttx_dma_tgt, WMI_ABORT_TX_DMA_CMDID, 0}, + {ath_tx_draintxq_tgt, WMI_DRAIN_TXQ_CMDID, 0}, + {ath_draintxq_tgt, WMI_DRAIN_TXQ_ALL_CMDID, 0}, + {ath_startrecv_tgt, WMI_START_RECV_CMDID, 0}, + {ath_stoprecv_tgt, WMI_STOP_RECV_CMDID, 0}, + {ath_flushrecv_tgt, WMI_FLUSH_RECV_CMDID, 0}, + {ath_setcurmode_tgt, WMI_SET_MODE_CMDID, 0}, + {ath_node_create_tgt, WMI_NODE_CREATE_CMDID, 0}, + {ath_node_cleanup_tgt, WMI_NODE_REMOVE_CMDID, 0}, + {ath_vap_delete_tgt, WMI_VAP_REMOVE_CMDID, 0}, + {ath_vap_create_tgt, WMI_VAP_CREATE_CMDID, 0}, + {ath_hal_reg_read_tgt, WMI_REG_READ_CMDID, 0}, + {ath_hal_reg_write_tgt, WMI_REG_WRITE_CMDID, 0}, + {handle_rc_state_change_cmd, WMI_RC_STATE_CHANGE_CMDID, 0}, + {handle_rc_rate_update_cmd, WMI_RC_RATE_UPDATE_CMDID, 0}, + {ath_ic_update_tgt, WMI_TARGET_IC_UPDATE_CMDID, 0}, + {ath_enable_aggr_tgt, WMI_TX_AGGR_ENABLE_CMDID, 0}, + {ath_detach_tgt, WMI_TGT_DETACH_CMDID, 0}, + {ath_node_update_tgt, WMI_NODE_UPDATE_CMDID, 0}, + {ath_int_stats_tgt, WMI_INT_STATS_CMDID, 0}, + {ath_tx_stats_tgt, WMI_TX_STATS_CMDID, 0}, + {ath_rx_stats_tgt, WMI_RX_STATS_CMDID, 0}, + {ath_rc_mask_tgt, WMI_BITRATE_MASK_CMDID, 0}, +}; + +/*****************/ +/* Init / Deinit */ +/*****************/ + +static void htc_setup_comp(void) +{ +} + +static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService, + HTC_ENDPOINT_ID eid, + A_UINT8 *pDataIn, + a_int32_t LengthIn, + A_UINT8 *pDataOut, + a_int32_t *pLengthOut) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx; + + switch(pService->ServiceID) { + case WMI_CONTROL_SVC: + sc->wmi_command_ep= eid; + break; + case WMI_BEACON_SVC: + sc->beacon_ep= eid; + break; + case WMI_CAB_SVC: + sc->cab_ep= eid; + break; + case WMI_UAPSD_SVC: + sc->uapsd_ep= eid; + break; + case WMI_MGMT_SVC: + sc->mgmt_ep= eid; + break; + case WMI_DATA_VO_SVC: + sc->data_VO_ep = eid; + break; + case WMI_DATA_VI_SVC: + sc->data_VI_ep = eid; + break; + case WMI_DATA_BE_SVC: + sc->data_BE_ep = eid; + break; + case WMI_DATA_BK_SVC: + sc->data_BK_ep = eid; + break; + default: + adf_os_assert(0); + } + + return HTC_SERVICE_SUCCESS; +} + +static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc, + int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg) +{ + svc->ProcessRecvMsg = recvMsg; + svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler; + svc->ProcessConnect = tgt_ServiceConnect; + svc->MaxSvcMsgSize = 1600; + svc->TrailerSpcCheckLimit = 0; + svc->ServiceID = svcId; + svc->ServiceCtx = sc; + HTC_RegisterService(sc->tgt_htc_handle, svc); +} + +static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc) +{ + HTC_CONFIG htc_conf; + WMI_SVC_CONFIG wmiConfig; + WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl; + + /* Init dynamic buf pool */ + sc->pool_handle = BUF_Pool_init(sc->sc_hdl); + + /* Init target-side HIF */ + sc->tgt_hif_handle = HIF_init(0); + + /* Init target-side HTC */ + htc_conf.HIFHandle = sc->tgt_hif_handle; + htc_conf.CreditSize = 320; + htc_conf.CreditNumber = ATH_TXBUF; + htc_conf.OSHandle = sc->sc_hdl; + htc_conf.PoolHandle = sc->pool_handle; + sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf); +#if defined(PROJECT_MAGPIE) + init_htc_handle = sc->tgt_htc_handle; +#endif + + tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler); + tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler); + tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler); + tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler); + tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler); + tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler); + tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler); + tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler); + + /* Init target-side WMI */ + Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE)); + adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE)); + Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries); + Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries; + + adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG)); + wmiConfig.HtcHandle = sc->tgt_htc_handle; + wmiConfig.PoolHandle = sc->pool_handle; + wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY; + wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS; + + sc->tgt_wmi_handle = WMI_Init(&wmiConfig); + Magpie_Sys_Commands_Tbl->pContext = sc; + WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl); + + HTC_NotifyTargetInserted(sc->tgt_htc_handle); + + /* Start HTC messages exchange */ + HTC_Ready(sc->tgt_htc_handle); +} + +a_int32_t ath_tgt_attach(a_uint32_t devid,a_uint32_t mem_start, + struct ath_softc_tgt *sc, adf_os_device_t osdev) +{ + struct ath_hal *ah; + HAL_STATUS status; + a_int32_t error = 0, i, flags = 0; + a_uint8_t csz; + + adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz); + + if (csz == 0) + csz = 16; + sc->sc_cachelsz = csz << 2; + + sc->sc_dev = osdev; + sc->sc_hdl = osdev; + + ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc); + ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc); + ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc); + ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc); + + flags |= AH_USE_EEPROM; + ah = _ath_hal_attach_tgt(devid,sc,sc->sc_dev,mem_start, flags, &status); + if (ah == NULL) { + error = ENXIO; + goto bad; + } + sc->sc_ah = ah; + + tgt_hif_htc_wmi_init(sc); + + sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1; + + ath_rate_setup(sc, IEEE80211_MODE_11NA); + ath_rate_setup(sc, IEEE80211_MODE_11NG); + + sc->sc_rc = ath_rate_attach(sc); + if (sc->sc_rc == NULL) { + error = EIO; + goto bad2; + } + + for (i=0; i < TARGET_NODE_MAX; i++) { + sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space); + } + + error = ath_desc_alloc(sc); + if (error != 0) { + goto bad; + } + + BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664); + + ath_tgt_txq_setup(sc); + sc->sc_imask =0; + ath_hal_intrset(ah,0); + + return 0; +bad: +bad2: + ath_desc_free(sc); + if (ah) + ath_hal_detach(ah); +} + +static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc) +{ + HTC_NotifyTargetDetached(sc->tgt_htc_handle); + + WMI_Shutdown(sc->tgt_wmi_handle); + HTC_Shutdown(sc->tgt_htc_handle); + HIF_shutdown(sc->tgt_hif_handle); + BUF_Pool_shutdown(sc->pool_handle); +} + +a_int32_t ath_detach(struct ath_softc_tgt *sc) +{ + tgt_hif_htc_wmi_shutdown(sc); +} diff --git a/target_firmware/wlan/if_ath_pci.c b/target_firmware/wlan/if_ath_pci.c new file mode 100755 index 0000000..8f37c08 --- /dev/null +++ b/target_firmware/wlan/if_ath_pci.c @@ -0,0 +1,208 @@ +/*- + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting + * Copyright (c) 2004 Atheros Communications, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/madwifi/ath/if_ath_pci.c#1 $ + */ + +#ifndef EXPORT_SYMTAB +#define EXPORT_SYMTAB +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include "if_athvar.h" +#include "if_ath_pci.h" + +extern a_int32_t ath_tgt_attach(a_uint32_t devid,a_uint32_t mem_start, + struct ath_softc_tgt *sc, adf_os_device_t osdev); +extern a_int32_t ath_detach(void *); +extern adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl); + +struct ath_pci_softc { + struct ath_softc_tgt aps_sc; +#ifdef CONFIG_PM + u32 ps_pmstate[16]; +#endif +}; + +/* + * User a static table of PCI id's for now. While this is the + * "new way" to do things, we may want to switch back to having + * the HAL check them by defining a probe method. + */ +#ifdef ATH_SUPPORT_XB_ONLY +static adf_os_pci_dev_id_t ath_pci_id_table[] = { + { 0x168c, 0x0024, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* PCI-E (XB) */ + { 0 }, +}; +#else + +static adf_os_pci_dev_id_t ath_pci_id_table[] = { + { 0x168c, 0x0007, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0x168c, 0x0012, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0x168c, 0x0013, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0xa727, 0x0013, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* 3com */ + { 0x10b7, 0x0013, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* 3com 3CRDAG675 */ + { 0x168c, 0x1014, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* IBM minipci 5212 */ + { 0x168c, 0x101a, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* some Griffin-Lite */ + { 0x168c, 0x0015, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0x168c, 0x0016, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0x168c, 0x0017, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0x168c, 0x0018, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0x168c, 0x0019, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0x168c, 0x001a, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0x168c, 0x001b, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0x168c, 0x001c, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0x168c, 0x001d, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, + { 0x168c, 0xff1d, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* owl emulation */ + { 0x168c, 0xff1c, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* owl emulation */ + { 0x168c, 0x0023, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* PCI (MB/CB) */ + { 0x168c, 0x0024, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* PCI-E (XB) */ + { 0x168c, 0x0027, ADF_OS_PCI_ANY_ID, ADF_OS_PCI_ANY_ID }, /* Sowl PCI */ + { 0 }, +}; +#endif + +void bus_read_cachesize(struct ath_softc *sc, a_uint8_t *csz); +void exit_ath_pci(void); +a_int32_t init_ath_pci(void); + +static adf_drv_handle_t +ath_pci_probe(adf_os_resource_t *res,a_int32_t count, adf_os_attach_data_t *data, + adf_os_device_t osdev) +{ + struct ath_pci_softc *sc; + a_uint8_t csz = 32; + adf_os_pci_dev_id_t *id = (adf_os_pci_dev_id_t *)data; + + adf_os_pci_config_write8(osdev, ATH_PCI_CACHE_LINE_SIZE, csz); + adf_os_pci_config_write8(osdev, ATH_PCI_LATENCY_TIMER, 0xa8); + + sc = adf_os_mem_alloc(sizeof(struct ath_pci_softc)); + + if (sc == NULL) { + adf_os_print("ath_pci: no memory for device state\n"); + goto bad2; + } + adf_os_mem_set(sc, 0, sizeof(struct ath_pci_softc)); + + /* + * Mark the device as detached to avoid processing + * interrupts until setup is complete. + */ + sc->aps_sc.sc_invalid = 1; + + adf_os_print("ath_pci_probe %x\n",id->device); + + if (ath_tgt_attach(id->device, res->start, &sc->aps_sc, osdev) != 0) + goto bad3; + + /* ready to process interrupts */ + sc->aps_sc.sc_invalid = 0; + adf_os_setup_intr(osdev, ath_intr); + return (adf_drv_handle_t)sc; +bad3: +bad2: + return NULL; +} + +static void +ath_pci_remove(adf_drv_handle_t hdl) +{ + struct ath_softc_tgt *sc = hdl; + + ath_detach((struct ath_softc_tgt *)hdl); + adf_os_free_intr(sc->sc_dev); +} + +static void +ath_pci_suspend(adf_drv_handle_t hdl, adf_os_pm_t pm) +{ +} + +static void +ath_pci_resume(adf_drv_handle_t hdl) +{ +} + +static char *dev_info = "ath_pci_tgt"; + +void +bus_read_cachesize(struct ath_softc *sc, a_uint8_t *csz) +{ + *csz = adf_os_cache_line_size(); +} + +static adf_drv_info_t ath_drv_info = adf_os_pci_set_drv_info(ath_pci_tgt,&ath_pci_id_table[0], ath_pci_probe, ath_pci_remove, ath_pci_suspend, ath_pci_resume); + +a_int32_t +init_ath_pci(void) +{ + return adf_net_register_drv( &ath_drv_info ); +} + +void +exit_ath_pci(void) +{ + adf_net_unregister_drv("ath_pci"); +} + +adf_os_pci_module_init(init_ath_pci); +adf_os_pci_module_exit(exit_ath_pci); +adf_os_module_dep(ath_pci_tgt, adf_net); +adf_os_module_dep(ath_pci_tgt, hal); +adf_os_module_dep(ath_pci_tgt, ath_pci); +adf_os_module_dep(ath_pci_tgt, wlan_tgt); +adf_os_module_dep(ath_pci_tgt, htc_tgt); +adf_os_module_dep(ath_pci_tgt, inproc_hif); diff --git a/target_firmware/wlan/if_ath_pci.h b/target_firmware/wlan/if_ath_pci.h new file mode 100755 index 0000000..dc5a1da --- /dev/null +++ b/target_firmware/wlan/if_ath_pci.h @@ -0,0 +1,46 @@ +/*- + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting + * Copyright (c) 2004 Atheros Communications, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/madwifi/ath/if_ath_pci.h#1 $ + */ + +#ifndef _DEV_ATH_PCI_H_ +#define _DEV_ATH_PCI_H_ + +#define ATH_PCI_CACHE_LINE_SIZE 0x0c +#define ATH_PCI_LATENCY_TIMER 0x0d + +#endif /* _DEV_ATH_PCI_H_ */ diff --git a/target_firmware/wlan/if_athrate.h b/target_firmware/wlan/if_athrate.h new file mode 100755 index 0000000..1ca50b1 --- /dev/null +++ b/target_firmware/wlan/if_athrate.h @@ -0,0 +1,117 @@ +/*- + * Copyright (c) 2004 Sam Leffler, Errno Consulting + * Copyright (c) 2004 Video54 Technologies, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/madwifi/ath/if_athrate.h#2 $ + */ +#ifndef _ATH_RATECTRL_H_ +#define _ATH_RATECTRL_H_ + +struct ath_softc; +struct ath_softc_tgt; +struct ath_node; +struct ath_node_target; +struct ath_desc; +struct ieee80211vap; +struct ieee80211com_target; + +struct ath_ratectrl { + size_t arc_space; /* space required for per-node state */ +}; + +#define ATH_RC_DS_FLAG 0x01 +#define ATH_RC_CW40_FLAG 0x02 +#define ATH_RC_HT40_SGI_FLAG 0x04 +#define ATH_RC_HT_FLAG 0x08 +#define ATH_RC_RTSCTS_FLAG 0x10 +#define ATH_RC_TX_STBC_FLAG 0x20 /* TX STBC */ +#define ATH_RC_RX_STBC_FLAG 0xC0 /* RX STBC ,2 bits */ +#define ATH_RC_RX_STBC_FLAG_S 6 +#define ATH_RC_WEP_TKIP_FLAG 0x100 /* WEP/TKIP encryption */ + +enum ath_rc_cwmode{ + ATH_RC_CW20_MODE, + ATH_RC_CW40_MODE, +}; + +#define ATH_RC_PROBE_ALLOWED 0x00000001 +#define ATH_RC_MINRATE_LASTRATE 0x00000002 + +struct ath_rc_series { + a_uint8_t rix; + a_uint8_t tries; + u_int8_t tx_chainmask; + a_uint8_t flags; + a_uint32_t max4msframelen; + a_uint32_t txrateKbps; +}; + +/* + * Attach/detach a rate control module. + */ +struct ath_ratectrl *ath_rate_attach(struct ath_softc_tgt *); +void ath_rate_detach(struct ath_ratectrl *); + +/* + * Return the transmit info for a data packet. If multi-rate state + * is to be setup then try0 should contain a value other than ATH_TXMATRY + * and ath_rate_setupxtxdesc will be called after deciding if the frame + * can be transmitted with multi-rate retry. + */ +void ath_rate_findrate(struct ath_softc_tgt *sc, + struct ath_node_target *an, + a_int32_t shortPreamble, + size_t frameLen, + a_int32_t numTries, + a_int32_t numRates, + a_int32_t stepDnInc, + a_uint32_t rcflag, + struct ath_rc_series series[], + a_int32_t *isProbe); +/* + * Update rate control state for a packet associated with the + * supplied transmit descriptor. The routine is invoked both + * for packets that were successfully sent and for those that + * failed (consult the descriptor for details). + */ +void ath_rate_tx_complete(struct ath_softc_tgt *, struct ath_node_target *, + struct ath_tx_desc *, struct ath_rc_series series[], + a_int32_t nframes, a_int32_t nbad); + + +void ath_rate_stateupdate(struct ath_softc_tgt *sc, struct ath_node_target *an, + enum ath_rc_cwmode cwmode); + +#endif /* _ATH_RATECTRL_H_ */ diff --git a/target_firmware/wlan/if_athvar.h b/target_firmware/wlan/if_athvar.h new file mode 100755 index 0000000..b57c4e0 --- /dev/null +++ b/target_firmware/wlan/if_athvar.h @@ -0,0 +1,530 @@ +#ifndef _DEV_ATH_ATHVAR_H +#define _DEV_ATH_ATHVAR_H + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ah.h" + +#include "ieee80211_var.h" +#include "ieee80211_node.h" +#include "if_athrate.h" +#include +#include +#include +#include +#include +#include + +#define tq_struct adf_os_bh_t +#define ATH_INIT_TQUEUE(a,b,c,d) adf_os_init_bh((a),(b),(c),(void *)(d)) +#define ATH_SCHEDULE_TQUEUE(a,b) adf_os_sched_bh((a),(b)) +typedef void * TQUEUE_ARG; + +#define ATH_MIN(a,b) ((a) < (b) ? (a) : (b)) +#define ATH_AC_2_TXQ(_sc, _ac) (_sc)->sc_ac2q[(_ac)] +#define TID_TO_ACTXQ(tidno) sc->sc_ac2q[ TID_TO_WME_AC(tidno)] + +#define RATE_TABLE_SIZE 32 + +#define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1) + +#define IEEE80211_SEQ_MAX 4096 +#define SEQNO_FROM_BF_SEQNO(_x) (_x >> IEEE80211_SEQ_SEQ_SHIFT) +#define BAW_WITHIN(_start, _bawsz, _seqno) \ + ((((_seqno) - (_start)) & 4095) < (_bawsz)) + +#define __stats(sc, _x) sc->sc_tx_stats._x ++ +#define __statsn(sc, _x, _n) sc->sc_tx_stats._x += _n + +#define IS_HT_RATE(_rate) ((_rate) & 0x80) + +typedef enum { + ATH_TGT_AGGR_DONE, + ATH_TGT_AGGR_BAW_CLOSED, + ATH_TGT_AGGR_LIMITED, + ATH_AGGR_SHORTPKT, + ATH_AGGR_8K_LIMITED, +} ATH_AGGR_STATUS; + +#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ + ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) + +#define ATH_DS_BA_SEQ(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_seqnum +#define ATH_DS_BA_BITMAP(_ds) (&((struct ath_tx_desc *)_ds)->ds_us.tx.ba_low) +#define ATH_DS_TX_BA(_ds) (((struct ath_tx_desc *)_ds)->ds_us.tx.ts_flags & HAL_TX_BA) +#define ATH_DS_TX_STATUS(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_status +#define ATH_DS_TX_FLAGS(_ds) ((struct ath_tx_desc *)_ds)->ds_us.tx.ts_flags +#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) + +#define ATH_AGGR_DELIM_SZ 4 +#define ATH_AGGR_MINPLEN 256 +#define ATH_AGGR_ENCRYPTDELIM 10 + +#define ATH_AGGR_GET_NDELIM(_len) \ + (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ + (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) + +#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) +#define OWLMAX_RETRIES 10 +#define OWLMAX_BAR_RETRIES 10 + +#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) +#define ATH_TXDESC 1 + +#define ATH_TXMAXTRY 11 +#define TARGET_NODE_MAX ATH_NODE_MAX +#define TARGET_VAP_MAX ATH_VAP_MAX + +#define ATH_NODE_TARGET(_n) ((struct ath_node *)(_n)) + +#define MAX_RATE_POWER 63 +#define ATH_COMP_PROC_NO_COMP_NO_CCS 3 + +#define ATH_BUFSTATUS_DONE 0x00000001 /* hw processing complete, desc processed by hal */ + +#define ATH_AGGR_MIN_QDEPTH 1 + +struct ath_softc_tgt; +struct ath_buf; +struct ath_txq; + +#define ATH_TXQ(_sc, _qi) (&(_sc)->sc_txq[(_qi)]) +#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<pool_handle, POOL_ID_WLAN_RX_BUF, _skb) +#define ath_free_tx_skb(_htc_handle, endpt, _skb) HTC_ReturnBuffers(_htc_handle, endpt, _skb); + +typedef void (*ath_txq_add_fn_t)(struct ath_softc_tgt *sc, struct ath_buf *bf); +typedef void (*ath_tx_comp_fn_t)(struct ath_softc_tgt *sc, struct ath_buf *bf); + +struct ath_buf_state { + ath_tx_comp_fn_t bfs_comp; /* completion function */ + ath_txq_add_fn_t bfs_txq_add; /* txq buffer add function */ + a_uint16_t bfs_pktlen; /* pktlen including crc */ + a_uint16_t bfs_seqno; /* sequence nuber */ + a_uint8_t bfs_hdrlen; /* header length */ + a_uint8_t bfs_keyix; /* key index */ + a_uint8_t bfs_atype; /* packet type */ + a_uint8_t bfs_ndelim; /* # delims for padding */ + a_uint8_t bfs_nframes; /* # frames in aggregate */ + a_uint8_t bfs_tidno; /* tid of the buffer */ + a_uint16_t bfs_al; /* length of aggregate */ + struct ath_rc_series bfs_rcs[4]; /* rate series */ + struct ath_txq *bfs_txq; /* transmit h/w queue */ + a_uint8_t bfs_protmode; /* protection mode */ + a_uint8_t bfs_keytype; /* encr key type */ + a_uint8_t bfs_retries; /* current retries */ + a_uint32_t bfs_ismcast : 1; /* is multicast */ + a_uint32_t bfs_shpream : 1; /* use short preamble */ + a_uint32_t bfs_isaggr : 1; /* is an aggregate */ + a_uint32_t bfs_isretried: 1; /* is retried */ +}; + +#define bf_comp bf_state.bfs_comp +#define bf_txq_add bf_state.bfs_txq_add +#define bf_pktlen bf_state.bfs_pktlen +#define bf_hdrlen bf_state.bfs_hdrlen +#define bf_keyix bf_state.bfs_keyix +#define bf_atype bf_state.bfs_atype +#define bf_seqno bf_state.bfs_seqno +#define bf_ndelim bf_state.bfs_ndelim +#define bf_nframes bf_state.bfs_nframes +#define bf_al bf_state.bfs_al +#define bf_tidno bf_state.bfs_tidno +#define bf_rcs bf_state.bfs_rcs +#define bf_txq bf_state.bfs_txq +#define bf_protmode bf_state.bfs_protmode +#define bf_keytype bf_state.bfs_keytype +#define bf_ismcast bf_state.bfs_ismcast +#define bf_shpream bf_state.bfs_shpream +#define bf_isaggr bf_state.bfs_isaggr +#define bf_isretried bf_state.bfs_isretried +#define bf_retries bf_state.bfs_retries + +#define ATH_GENERIC_BUF \ + asf_tailq_entry(ath_buf) bf_list; \ + struct ath_buf *bf_next; \ + struct ath_desc *bf_desc; \ + struct ath_desc *bf_descarr; \ + adf_os_dma_map_t bf_dmamap; \ + adf_os_dmamap_info_t bf_dmamap_info; \ + struct ieee80211_node_target *bf_node; \ + adf_nbuf_queue_t bf_skbhead; \ + adf_nbuf_t bf_skb; \ + struct ath_desc *bf_lastds; + +struct ath_buf +{ + ATH_GENERIC_BUF +}; + +struct ath_tx_buf +{ + ATH_GENERIC_BUF + struct ath_buf_state bf_state; + a_uint16_t bf_flags; + HTC_ENDPOINT_ID bf_endpt; + a_uint16_t al_delta; + a_uint8_t bf_cookie; +}; + +struct ath_rx_buf +{ + ATH_GENERIC_BUF + a_uint32_t bf_status; + struct ath_rx_status bf_rx_status; +}; + +#define ATH_BUF_GET_DESC_PHY_ADDR(bf) bf->bf_desc +#define ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, idx) (adf_os_dma_addr_t)(&bf->bf_descarr[idx]) +#define ATH_BUF_SET_DESC_PHY_ADDR(bf, addr) +#define ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, idx, addr) + +typedef asf_tailq_head(ath_deschead_s, ath_rx_desc) ath_deschead; +typedef asf_tailq_head(ath_bufhead_s, ath_buf) ath_bufhead; + +#define WME_NUM_TID 8 +#define WME_BA_BMP_SIZE 64 +#define WME_MAX_BA WME_BA_BMP_SIZE +#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) +#define TID_CLEANUP_INPROGRES 0x1 +#define TID_AGGR_ENABLED 0x2 +#define TID_REINITIALIZE 0x4 + +#define TAILQ_DEQ(_q, _elm, _field) do { \ + (_elm) = asf_tailq_first((_q)); \ + if (_elm) { \ + asf_tailq_remove((_q), (_elm), _field); \ + } \ + } while (0) + +#define TX_BUF_BITMAP_SIZE 32 +#define TX_BUF_BITMAP_SET(bitmap, i) bitmap[i>>5] |= ((a_uint32_t)1 << (i&0x1f)) +#define TX_BUF_BITMAP_CLR(bitmap, i) bitmap[i>>5] &= (~((a_uint32_t)1 << (i&0x1f))) +#define TX_BUF_BITMAP_IS_SET(bitmap, i) ((bitmap[i>>5] & ((a_uint32_t)1 << (i&0x1f))) != 0) + +typedef struct ath_atx_tid { + a_int32_t tidno; + a_uint16_t seq_start; + a_uint16_t seq_next; + a_uint16_t baw_size; + a_int32_t baw_head; + a_int32_t baw_tail; + a_uint32_t tx_buf_bitmap[ATH_TID_MAX_BUFS/TX_BUF_BITMAP_SIZE]; + asf_tailq_entry(ath_atx_tid) tid_qelem; + asf_tailq_head(ath_tid_rbq,ath_buf) buf_q; + a_int8_t paused; + a_int8_t sched; + a_uint8_t flag; + a_int8_t incomp; + struct ath_node_target *an; +} ath_atx_tid_t; + +struct ath_node_target { + struct ieee80211_node_target ni; + struct ath_atx_tid tid[WME_NUM_TID]; + a_int8_t an_valid; + void *an_rcnode; +}; + +struct ath_descdma { + const a_int8_t *dd_name; + struct ath_desc *dd_desc; + adf_os_dma_map_t dd_desc_dmamap; + adf_os_dma_addr_t dd_desc_paddr; + adf_os_size_t dd_desc_len; + struct ath_buf *dd_bufptr; +}; + +struct ath_txq { + a_uint32_t axq_qnum; + a_uint32_t *axq_link; + asf_tailq_head(,ath_buf) axq_q; + a_uint32_t axq_depth; + struct ath_buf *axq_linkbuf; + asf_tailq_head(,ath_atx_tid) axq_tidq; +}; + +struct wmi_rc_rate_mask_cmd { + a_uint8_t vap_index; + a_uint8_t band; + a_uint32_t mask; + a_uint16_t pad; +} POSTPACK; + +struct ath_vap_target { + struct ieee80211vap_target av_vap; + struct ath_txq av_mcastq; + struct ath_buf *av_bcbuf; + a_uint32_t av_rate_mask[2]; /* 0 - 2G, 1 - 5G */ + a_uint8_t av_minrateidx[2]; /* 0 - 2G, 1 - 5G */ + a_int8_t av_valid; +}; + +#define ATH_RXBUF_RESET(bf) \ + bf->bf_status=0 + +struct ath_softc_tgt +{ + /* Target-side HTC/HIF/WMI related data structure */ + pool_handle_t pool_handle; + hif_handle_t tgt_hif_handle; + htc_handle_t tgt_htc_handle; + wmi_handle_t tgt_wmi_handle; + + /* Target HTC Service IDs */ + HTC_SERVICE htc_beacon_service; + HTC_SERVICE htc_cab_service; + HTC_SERVICE htc_uapsd_service; + HTC_SERVICE htc_mgmt_service; + HTC_SERVICE htc_data_VO_service; + HTC_SERVICE htc_data_VI_service; + HTC_SERVICE htc_data_BE_service; + HTC_SERVICE htc_data_BK_service; + + + /* Target HTC Endpoint IDs */ + HTC_ENDPOINT_ID wmi_command_ep; + HTC_ENDPOINT_ID beacon_ep; + HTC_ENDPOINT_ID cab_ep; + HTC_ENDPOINT_ID uapsd_ep; + HTC_ENDPOINT_ID mgmt_ep; + HTC_ENDPOINT_ID data_VO_ep; + HTC_ENDPOINT_ID data_VI_ep; + HTC_ENDPOINT_ID data_BE_ep; + HTC_ENDPOINT_ID data_BK_ep; + + adf_os_handle_t sc_hdl; + adf_os_device_t sc_dev; + a_uint8_t sc_bhalq; + struct ath_ratectrl *sc_rc; + + a_uint32_t sc_invalid : 1, + sc_txstbcsupport : 1, + sc_rxstbcsupport : 2, + sc_tx_draining : 1, + sc_enable_coex : 1; + + a_int32_t sc_rxbufsize; + a_uint16_t sc_cachelsz; + + struct ath_interrupt_stats sc_int_stats; + struct ath_tx_stats sc_tx_stats; + struct ath_rx_stats sc_rx_stats; + + const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; + const HAL_RATE_TABLE *sc_currates; + + a_uint8_t sc_rixmap[256]; + + enum ieee80211_phymode sc_curmode; + + a_uint8_t sc_protrix; + HAL_INT sc_imask; + + tq_struct sc_rxtq; + tq_struct sc_bmisstq; + tq_struct sc_txtotq; + tq_struct sc_fataltq; + + ath_bufhead sc_rxbuf; + + ath_deschead sc_rxdesc_idle; + ath_deschead sc_rxdesc; + struct ath_desc *sc_rxdesc_held; + + struct ath_buf *sc_txbuf_held; + + struct ath_descdma sc_rxdma; + struct ath_descdma sc_txdma; + struct ath_descdma sc_bdma; + + a_uint32_t *sc_rxlink; + ath_bufhead sc_txbuf; + a_uint8_t sc_txqsetup; + + struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; + struct ath_txq *sc_ac2q[WME_NUM_AC]; + tq_struct sc_txtq; + + struct ath_hal *sc_ah; + struct ath_txq *sc_cabq; + struct ath_txq *sc_uapsdq; + struct ath_node_target sc_sta[TARGET_NODE_MAX]; + struct ath_vap_target sc_vap[TARGET_VAP_MAX]; + struct ieee80211com_target sc_ic; + + ath_bufhead sc_bbuf; + a_uint64_t sc_swba_tsf; + + WMI_TXSTATUS_EVENT tx_status[2]; +}; + +#define SM(_v, _f) (((_v) << _f##_S) & _f) +#define MS(_v, _f) (((_v) & _f) >> _f##_S) + +#define ATH9K_HTC_TXSTAT_ACK 1<<0 +#define ATH9K_HTC_TXSTAT_FILT 1<<1 +#define ATH9K_HTC_TXSTAT_RTC_CTS 1<<2 +#define ATH9K_HTC_TXSTAT_MCS 1<<3 +#define ATH9K_HTC_TXSTAT_CW40 1<<4 +#define ATH9K_HTC_TXSTAT_SGI 1<<5 + +#define ATH9K_HTC_TXSTAT_RATE 0x0f +#define ATH9K_HTC_TXSTAT_RATE_S 0 +#define ATH9K_HTC_TXSTAT_EPID 0xf0 +#define ATH9K_HTC_TXSTAT_EPID_S 4 + +#define TAILQ_INSERTQ_HEAD(head, tq, field) do { \ + if ((head)->tqh_first) { \ + *(tq)->tqh_last = (head)->tqh_first; \ + (head)->tqh_first->field.tqe_prev = (tq)->tqh_last; \ + } else { \ + (head)->tqh_last = (tq)->tqh_last; \ + } \ + (head)->tqh_first = (tq)->tqh_first; \ + (tq)->tqh_first->field.tqe_prev = &(head)->tqh_first; \ + } while (0) + +#define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \ + asf_tailq_insert_tail( &(_tq)->axq_q, (_elm), _field); \ + (_tq)->axq_depth++; \ + (_tq)->axq_linkbuf = (_elm); \ + } while (0) +#define ATH_TXQ_REMOVE_HEAD(_tq, _elm, _field) do { \ + asf_tailq_remove(&(_tq)->axq_q, (_elm), _field); \ + (_tq)->axq_depth--; \ + } while (0) + +struct ieee80211_rate { + struct ieee80211_rateset rates; + struct ieee80211_rateset htrates; +} __attribute__((packed)); + +struct wmi_rc_state_change_cmd { + a_uint8_t vap_index; + a_uint8_t vap_state; + a_uint8_t pad[2]; + a_uint32_t capflag; + struct ieee80211_rate rs; +} __attribute__((packed)); + +struct wmi_rc_rate_update_cmd { + a_uint8_t node_index; + a_uint8_t isNew; + a_uint8_t pad[2]; + a_uint32_t capflag; + struct ieee80211_rate rs; +} __attribute__((packed)); + +typedef enum { + OWL_TXQ_ACTIVE = 0, + OWL_TXQ_STOPPED, + OWL_TXQ_FILTERED, +} owl_txq_state_t; + +a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp); + +#define ath_hal_getratetable(_ah, _mode) \ + ((*(_ah)->ah_getRateTable)((_ah), (_mode))) +#define ath_hal_intrset(_ah, _mask) \ + ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) +#define ath_hal_intrpend(_ah) \ + ((*(_ah)->ah_isInterruptPending)((_ah))) +#define ath_hal_getisr(_ah, _pmask) \ + ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) +#define ath_hal_updatetxtriglevel(_ah, _inc) \ + ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) +#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ + ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) +#define ath_hal_rxprocdescfast(_ah, _ds, _dspa, _dsnext, _rx_stats) \ + ((*(_ah)->ah_procRxDescFast)((_ah), (_ds), (_dspa), (_dsnext), (_rx_stats))) +#define ath_hal_stoptxdma(_ah, _qnum) \ + ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) +#define ath_hal_aborttxdma(_ah) \ + ((*(_ah)->ah_abortTxDma)(_ah)) +#define ath_hal_set11n_txdesc(_ah, _ds, _pktlen, _type, _txpower,\ + _keyix, _keytype, _flags) \ + ((*(_ah)->ah_set11nTxDesc)(_ah, _ds, _pktlen, _type, _txpower, _keyix,\ + _keytype, _flags)) +#define ath_hal_set11n_ratescenario(_ah, _ds, _durupdate, _rtsctsrate, _rtsctsduration, \ + _series, _nseries, _flags) \ + ((*(_ah)->ah_set11nRateScenario)(_ah, _ds, _durupdate, _rtsctsrate, _rtsctsduration,\ + _series, _nseries, _flags)) +#define ath_hal_clr11n_aggr(_ah, _ds) \ + ((*(_ah)->ah_clr11nAggr)(_ah, _ds)) +#define ath_hal_set11n_burstduration(_ah, _ds, _burstduration) \ + ((*(_ah)->ah_set11nBurstDuration)(_ah, _ds, _burstduration)) +#define ath_hal_set11n_virtualmorefrag(_ah, _ds, _vmf) \ + ((*(_ah)->ah_set11nVirtualMoreFrag)(_ah, _ds, _vmf)) +#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ + _txr0, _txtr0, _keyix, _ant, _flags, \ + _rtsrate, _rtsdura, \ + _compicvlen, _compivlen, _comp) \ + ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ + (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ + (_flags), (_rtsrate), (_rtsdura), \ + (_compicvlen), (_compivlen), (_comp))) +#define ath_hal_fillkeytxdesc(_ah, _ds, _keytype) \ + ((*(_ah)->ah_fillKeyTxDesc)((_ah), (_ds), (_keytype))) +#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ + ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) +#define ath_hal_txprocdesc(_ah, _ds) \ + ((*(_ah)->ah_procTxDesc)((_ah), (_ds))) +#define ath_hal_putrxbuf(_ah, _bufaddr) \ + ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) +#define ath_hal_rxena(_ah) \ + ((*(_ah)->ah_enableReceive)((_ah))) +#define ath_hal_stopdmarecv(_ah) \ + ((*(_ah)->ah_stopDmaReceive)((_ah))) +#define ath_hal_stoppcurecv(_ah) \ + ((*(_ah)->ah_stopPcuReceive)((_ah))) +#define ath_hal_htsupported(_ah) \ + (ath_hal_getcapability(_ah, HAL_CAP_HT, 0, NULL) == HAL_OK) +#define ath_hal_rxstbcsupport(_ah, _rxstbc) \ + (ath_hal_getcapability(_ah, HAL_CAP_RX_STBC, 0, _rxstbc) == HAL_OK) +#define ath_hal_txstbcsupport(_ah, _txstbc) \ + (ath_hal_getcapability(_ah, HAL_CAP_TX_STBC, 0, _txstbc) == HAL_OK) +#define ath_hal_getrtsaggrlimit(_ah, _pv) \ + (ath_hal_getcapability(_ah, HAL_CAP_RTS_AGGR_LIMIT, 0, _pv) == HAL_OK) +#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ + ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) + #define ath_hal_txstart(_ah, _q) \ + ((*(_ah)->ah_startTxDma)((_ah), (_q))) +#define ath_hal_setrxfilter(_ah, _filter) \ + ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) +#define ath_hal_gettsf64(_ah) \ + ((*(_ah)->ah_getTsf64)((_ah))) +#define ath_hal_intrset(_ah, _mask) \ + ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) +#define ath_hal_getcapability(_ah, _cap, _param, _result) \ + ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) +#define ath_hal_set11n_aggr_first(_ah, _ds, _aggrlen, _numdelims) \ + ((*(_ah)->ah_set11nAggrFirst)(_ah, _ds, _aggrlen, _numdelims)) +#define ath_hal_set11n_aggr_middle(_ah, _ds, _numdelims) \ + ((*(_ah)->ah_set11nAggrMiddle)(_ah, _ds, _numdelims)) +#define ath_hal_set11n_aggr_last(_ah, _ds) \ + ((*(_ah)->ah_set11nAggrLast)(_ah, _ds)) +#define ath_hal_numtxpending(_ah, _q) \ + ((*(_ah)->ah_numTxPending)((_ah), (_q))) + +#endif /* _DEV_ATH_ATHVAR_H */ diff --git a/target_firmware/wlan/if_ethersubr.h b/target_firmware/wlan/if_ethersubr.h new file mode 100755 index 0000000..32d5068 --- /dev/null +++ b/target_firmware/wlan/if_ethersubr.h @@ -0,0 +1,79 @@ +/*- + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/madwifi/net80211/if_ethersubr.h#1 $ + */ + +#ifndef _NET_IF_ETHERSUBR_H_ +#define _NET_IF_ETHERSUBR_H_ + +#define ETHER_ADDR_LEN 6 /* length of an Ethernet address */ +#define ETHER_TYPE_LEN 2 /* length of the Ethernet type field */ +#define ETHER_CRC_LEN 4 /* length of the Ethernet CRC */ +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN) +#define ETHER_MAX_LEN 1518 + +#define ETHERMTU (ETHER_MAX_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) + +/* + * Structure of a 10Mb/s Ethernet header. + */ +/* struct ether_header { */ +/* u_char ether_dhost[ETHER_ADDR_LEN]; */ +/* u_char ether_shost[ETHER_ADDR_LEN]; */ +/* u_short ether_type; */ +/* } adf_os_packed; */ + +#ifndef ETHERTYPE_PAE +#define ETHERTYPE_PAE 0x888e /* EAPOL PAE/802.1x */ +#endif +#ifndef ETHERTYPE_IP +#define ETHERTYPE_IP 0x0800 /* IP protocol */ +#endif + +/* + * Structure of a 48-bit Ethernet address. + */ +/* struct ether_addr { */ +/* u_char octet[ETHER_ADDR_LEN]; */ +/* } adf_os_packed; */ + +#define ETHER_IS_MULTICAST(addr) (*(addr) & 0x01) /* is address mcast/bcast? */ + +#define VLAN_PRI_SHIFT 13 /* Shift to find VLAN user priority */ +#define VLAN_PRI_MASK 7 /* Mask for user priority bits in VLAN */ + + +#endif /* _NET_IF_ETHERSUBR_H_ */ diff --git a/target_firmware/wlan/if_llc.h b/target_firmware/wlan/if_llc.h new file mode 100755 index 0000000..4fc7ee3 --- /dev/null +++ b/target_firmware/wlan/if_llc.h @@ -0,0 +1,198 @@ +/*- + * Copyright (c) 2002-2004 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/madwifi/net80211/if_llc.h#1 $ + * $NetBSD: if_llc.h,v 1.12 1999/11/19 20:41:19 thorpej Exp $ + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/madwifi/net80211/if_llc.h#1 $ + */ + +/* + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)if_llc.h 8.1 (Berkeley) 6/10/93 + * $FreeBSD: src/sys/net/if_llc.h,v 1.9 2002/09/23 06:25:08 alfred Exp $ + */ + +#ifndef _NET_IF_LLC_H_ +#define _NET_IF_LLC_H_ + +/* + * IEEE 802.2 Link Level Control headers, for use in conjunction with + * 802.{3,4,5} media access control methods. + * + * Headers here do not use bit fields due to shortcommings in many + * compilers. + */ + +struct llc { + a_uint8_t llc_dsap; + a_uint8_t llc_ssap; + union { + struct { + a_uint8_t control; + a_uint8_t format_id; + a_uint8_t class; + a_uint8_t window_x2; + } type_u adf_os_packed; + struct { + a_uint8_t num_snd_x2; + a_uint8_t num_rcv_x2; + } type_i adf_os_packed; + struct { + a_uint8_t control; + a_uint8_t num_rcv_x2; + } type_s adf_os_packed; + struct { + a_uint8_t control; + /* + * We cannot put the following fields in a structure because + * the structure rounding might cause padding. + */ + a_uint8_t frmr_rej_pdu0; + a_uint8_t frmr_rej_pdu1; + a_uint8_t frmr_control; + a_uint8_t frmr_control_ext; + a_uint8_t frmr_cause; + } type_frmr adf_os_packed; + struct { + a_uint8_t control; + a_uint8_t org_code[3]; + a_uint16_t ether_type; + } type_snap adf_os_packed; + struct { + a_uint8_t control; + a_uint8_t control_ext; + } type_raw adf_os_packed; + } llc_un /* XXX adf_os_packed ??? */; +} adf_os_packed; + +struct frmrinfo { + a_uint8_t frmr_rej_pdu0; + a_uint8_t frmr_rej_pdu1; + a_uint8_t frmr_control; + a_uint8_t frmr_control_ext; + a_uint8_t frmr_cause; +} adf_os_packed; + +#define llc_control llc_un.type_u.control +#define llc_control_ext llc_un.type_raw.control_ext +#define llc_fid llc_un.type_u.format_id +#define llc_class llc_un.type_u.class +#define llc_window llc_un.type_u.window_x2 +#define llc_frmrinfo llc_un.type_frmr.frmr_rej_pdu0 +#define llc_frmr_pdu0 llc_un.type_frmr.frmr_rej_pdu0 +#define llc_frmr_pdu1 llc_un.type_frmr.frmr_rej_pdu1 +#define llc_frmr_control llc_un.type_frmr.frmr_control +#define llc_frmr_control_ext llc_un.type_frmr.frmr_control_ext +#define llc_frmr_cause llc_un.type_frmr.frmr_cause +#define llc_snap llc_un.type_snap + +/* + * Don't use sizeof(struct llc_un) for LLC header sizes + */ +#define LLC_ISFRAMELEN 4 +#define LLC_UFRAMELEN 3 +#define LLC_FRMRLEN 7 +#define LLC_SNAPFRAMELEN 8 + +/* + * Unnumbered LLC format commands + */ +#define LLC_UI 0x3 +#define LLC_UI_P 0x13 +#define LLC_DISC 0x43 +#define LLC_DISC_P 0x53 +#define LLC_UA 0x63 +#define LLC_UA_P 0x73 +#define LLC_TEST 0xe3 +#define LLC_TEST_P 0xf3 +#define LLC_FRMR 0x87 +#define LLC_FRMR_P 0x97 +#define LLC_DM 0x0f +#define LLC_DM_P 0x1f +#define LLC_XID 0xaf +#define LLC_XID_P 0xbf +#define LLC_SABME 0x6f +#define LLC_SABME_P 0x7f + +/* + * Supervisory LLC commands + */ +#define LLC_RR 0x01 +#define LLC_RNR 0x05 +#define LLC_REJ 0x09 + +/* + * Info format - dummy only + */ +#define LLC_INFO 0x00 + +/* + * ISO PDTR 10178 contains among others + */ +#define LLC_X25_LSAP 0x7e +#define LLC_SNAP_LSAP 0xaa +#define LLC_ISO_LSAP 0xfe + +#endif /* _NET_IF_LLC_H_ */ diff --git a/target_firmware/wlan/if_owl.c b/target_firmware/wlan/if_owl.c new file mode 100755 index 0000000..e7f4e28 --- /dev/null +++ b/target_firmware/wlan/if_owl.c @@ -0,0 +1,2164 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "if_ethersubr.h" +#include "if_llc.h" + +#ifdef USE_HEADERLEN_RESV +#include +#endif + +#include +#include "if_athrate.h" +#include "if_athvar.h" +#include "ah_desc.h" +#include "if_ath_pci.h" + +#define ath_tgt_free_skb adf_nbuf_free + +#define OFDM_PLCP_BITS 22 +#define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) +#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) +#define L_STF 8 +#define L_LTF 8 +#define L_SIG 4 +#define HT_SIG 8 +#define HT_STF 4 +#define HT_LTF(_ns) (4 * (_ns)) +#define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us +#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us + +static a_uint16_t bits_per_symbol[][2] = { + /* 20MHz 40MHz */ + { 26, 54 }, // 0: BPSK + { 52, 108 }, // 1: QPSK 1/2 + { 78, 162 }, // 2: QPSK 3/4 + { 104, 216 }, // 3: 16-QAM 1/2 + { 156, 324 }, // 4: 16-QAM 3/4 + { 208, 432 }, // 5: 64-QAM 2/3 + { 234, 486 }, // 6: 64-QAM 3/4 + { 260, 540 }, // 7: 64-QAM 5/6 + { 52, 108 }, // 8: BPSK + { 104, 216 }, // 9: QPSK 1/2 + { 156, 324 }, // 10: QPSK 3/4 + { 208, 432 }, // 11: 16-QAM 1/2 + { 312, 648 }, // 12: 16-QAM 3/4 + { 416, 864 }, // 13: 64-QAM 2/3 + { 468, 972 }, // 14: 64-QAM 3/4 + { 520, 1080 }, // 15: 64-QAM 5/6 +}; + +void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq, + owl_txq_state_t txqstate); +static void ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, struct ath_txq *txq, + struct ath_buf *bf, struct ath_desc *lastds); +void ath_rate_findrate_11n_Hardcoded(struct ath_softc_tgt *sc, + struct ath_rc_series series[]); +void ath_buf_set_rate_Hardcoded(struct ath_softc_tgt *sc, + struct ath_tx_buf *bf) ; +static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc, + struct ath_tx_buf *bf, ath_data_hdr_t *dh); +static void ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); +static void ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); +static void ath_update_stats(struct ath_softc_tgt *sc, struct ath_buf *bf); +void adf_print_buf(adf_nbuf_t buf); +static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid); + +struct ath_buf * ath_tgt_tx_prepare(struct ath_softc_tgt *sc, + adf_nbuf_t skb, ath_data_hdr_t *dh); +void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); +struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb); + +void ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); + +static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid); +static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid); + +static struct ath_node_target * owltarget_findnode(struct tx_frame_heade *dh, + struct ath_softc_tgt *sc, + struct adf_nbuf_t *skb); +extern a_int32_t ath_chainmask_sel_logic(void *); +static a_int32_t ath_get_pktlen(struct ath_buf *bf, a_int32_t hdrlen); +static void ath_tgt_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); + +typedef void (*ath_ft_set_atype_t)(struct ath_softc_tgt *sc, struct ath_buf *bf); + +static void +ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); + +static void +ath_bar_tx(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, struct ath_tx_buf *bf); +static void +ath_tx_update_baw(ath_atx_tid_t *tid, int seqno); +static void +ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, + ath_bufhead *bf_q, struct ath_tx_buf **bar); + +static void +ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid); + +void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf); +static inline void ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); +static void ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); +static void ath_update_aggr_stats(struct ath_softc_tgt *sc, struct ath_tx_desc *ds, + int nframes, int nbad); +static inline void ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid); +static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf); + +int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc, + struct ath_buf *bf,int datatype, + ath_atx_tid_t *tid, int is_burst); + +struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb) +{ + a_uint8_t *anbdata; + a_uint32_t anblen; + + adf_nbuf_peek_header(skb, &anbdata, &anblen); + + return((struct ieee80211_frame *)anbdata); +} + +#undef adf_os_cpu_to_le16 + +static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x) +{ + return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8)); +} + +static inline void +ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid) +{ + struct ath_txq *txq; + + txq = TID_TO_ACTXQ(tid->tidno); + tid->paused = 0; + + if (asf_tailq_empty(&tid->buf_q)) + return; + + ath_tgt_tx_enqueue(txq, tid); + ath_tgt_txq_schedule(sc, txq); +} + +static inline void +ath_aggr_pause_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid) +{ + tid->paused =1; +} + +static a_uint32_t ath_pkt_duration(struct ath_softc_tgt *sc, + a_uint8_t rix, struct ath_tx_buf *bf, + a_int32_t width, a_int32_t half_gi) +{ + const HAL_RATE_TABLE *rt = sc->sc_currates; + a_uint32_t nbits, nsymbits, duration, nsymbols; + a_uint8_t rc; + a_int32_t streams; + a_int32_t pktlen; + + pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_pktlen; + rc = rt->info[rix].rateCode; + + if (!IS_HT_RATE(rc)) + return ath_hal_computetxtime(sc->sc_ah, rt, pktlen, rix, + bf->bf_shpream); + + nbits = (pktlen << 3) + OFDM_PLCP_BITS; + nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; + nsymbols = (nbits + nsymbits - 1) / nsymbits; + + if (!half_gi) + duration = SYMBOL_TIME(nsymbols); + else + duration = SYMBOL_TIME_HALFGI(nsymbols); + + streams = HT_RC_2_STREAMS(rc); + duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); + + return duration; +} + +static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_buf *bf) +{ + adf_nbuf_t skb = bf->bf_skb; + + skb = adf_nbuf_queue_first(&bf->bf_skbhead); + adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE); +} + +static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_buf *bf) +{ + adf_nbuf_t skb = bf->bf_skb; + + skb = adf_nbuf_queue_first(&bf->bf_skbhead); + adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE); +} + +static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ath_desc *ds0, *ds = bf->bf_desc; + a_uint8_t i; + + ds0 = ds; + adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info); + + for (i = 0; i < bf->bf_dmamap_info.nsegs; i++, ds++) { + + ds->ds_data = bf->bf_dmamap_info.dma_segs[i].paddr; + + if (i == (bf->bf_dmamap_info.nsegs - 1)) { + ds->ds_link = 0; + bf->bf_lastds = ds; + } else + ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1); + + ath_hal_filltxdesc(sc->sc_ah, ds + , bf->bf_dmamap_info.dma_segs[i].len + , i == 0 + , i == (bf->bf_dmamap_info.nsegs - 1) + , ds0); + } +} + +static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ath_desc *ds0, *ds = bf->bf_desc; + adf_nbuf_t skb; + adf_nbuf_queue_t skbhead; + a_int32_t i, dscnt = 0; + + switch (bf->bf_protmode) { + case IEEE80211_PROT_RTSCTS: + bf->bf_flags |= HAL_TXDESC_RTSENA; + break; + case IEEE80211_PROT_CTSONLY: + bf->bf_flags |= HAL_TXDESC_CTSENA; + break; + default: + break; + } + + ath_hal_set11n_txdesc(sc->sc_ah, ds + , bf->bf_pktlen + , bf->bf_atype + , 60 + , bf->bf_keyix + , bf->bf_keytype + , bf->bf_flags | HAL_TXDESC_INTREQ); + + ath_filltxdesc(sc, bf); +} + +static struct ath_buf *ath_buf_toggle(struct ath_softc_tgt *sc, + struct ath_tx_buf *bf, + a_uint8_t retry) +{ + struct ath_tx_buf *tmp = NULL; + adf_nbuf_t buf = NULL; + + adf_os_assert(sc->sc_txbuf_held != NULL); + + tmp = sc->sc_txbuf_held; + + if (retry) { + ath_dma_unmap(sc, bf); + adf_nbuf_queue_init(&tmp->bf_skbhead); + buf = adf_nbuf_queue_remove(&bf->bf_skbhead); + adf_os_assert(buf); + adf_nbuf_queue_add(&tmp->bf_skbhead, buf); + + adf_os_assert(adf_nbuf_queue_len(&bf->bf_skbhead) == 0); + + tmp->bf_next = bf->bf_next; + tmp->bf_endpt = bf->bf_endpt; + tmp->bf_tidno = bf->bf_tidno; + tmp->bf_skb = bf->bf_skb; + tmp->bf_node = bf->bf_node; + tmp->bf_isaggr = bf->bf_isaggr; + tmp->bf_flags = bf->bf_flags; + tmp->bf_state = bf->bf_state; + tmp->bf_retries = bf->bf_retries; + tmp->bf_comp = bf->bf_comp; + tmp->bf_nframes = bf->bf_nframes; + tmp->bf_cookie = bf->bf_cookie; + + bf->bf_isaggr = 0; + bf->bf_next = NULL; + bf->bf_skb = NULL; + bf->bf_node = NULL; + bf->bf_flags = 0; + bf->bf_comp = NULL; + + bf->bf_retries = 0; + bf->bf_nframes = 0; + + ath_dma_map(sc, tmp); + ath_tx_tgt_setds(sc, tmp); + } + + sc->sc_txbuf_held = bf; + + return tmp; +} + +static void ath_tgt_skb_free(struct ath_softc_tgt *sc, + adf_nbuf_queue_t *head, + HTC_ENDPOINT_ID endpt) +{ + adf_nbuf_t tskb; + + while (adf_nbuf_queue_len(head) != 0) { + tskb = adf_nbuf_queue_remove(head); + ath_free_tx_skb(sc->tgt_htc_handle,endpt,tskb); + } +} + +static void ath_buf_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + ath_dma_unmap(sc, bf); + ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt); + bf->bf_skb = NULL; + bf->bf_node = NULL; + bf = ath_buf_toggle(sc, bf, 0); + if (bf != NULL) { + asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list); + } +} + +static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ath_hal *ah = sc->sc_ah; + const HAL_RATE_TABLE *rt; + struct ath_desc *ds = bf->bf_desc; + HAL_11N_RATE_SERIES series[4]; + a_int32_t i, flags; + a_uint8_t rix, cix, rtsctsrate; + a_uint32_t aggr_limit_with_rts; + a_uint32_t ctsduration = 0; + a_int32_t prot_mode = AH_FALSE; + + rt = sc->sc_currates; + rix = bf->bf_rcs[0].rix; + flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)); + cix = rt->info[sc->sc_protrix].controlRate; + + if (bf->bf_protmode != IEEE80211_PROT_NONE && + (rt->info[rix].phy == IEEE80211_T_OFDM || + rt->info[rix].phy == IEEE80211_T_HT) && + (bf->bf_flags & HAL_TXDESC_NOACK) == 0) { + cix = rt->info[sc->sc_protrix].controlRate; + prot_mode = AH_TRUE; + } else { + if (ath_hal_htsupported(ah) && (!bf->bf_ismcast)) + flags = HAL_TXDESC_RTSENA; + + for (i = 4; i--;) { + if (bf->bf_rcs[i].tries) { + cix = rt->info[bf->bf_rcs[i].rix].controlRate; + break; + } + + } + } + + ath_hal_getrtsaggrlimit(sc->sc_ah, &aggr_limit_with_rts); + + if (bf->bf_isaggr && aggr_limit_with_rts && + bf->bf_al > aggr_limit_with_rts) { + flags &= ~(HAL_TXDESC_RTSENA); + } + + adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4); + + for (i = 0; i < 4; i++) { + if (!bf->bf_rcs[i].tries) + continue; + + rix = bf->bf_rcs[i].rix; + + series[i].Rate = rt->info[rix].rateCode | + (bf->bf_shpream ? rt->info[rix].shortPreamble : 0); + + series[i].Tries = bf->bf_rcs[i].tries; +#ifdef MAGPIE_MERLIN + series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ? + HAL_RATESERIES_RTS_CTS : 0 ) | + ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ? + HAL_RATESERIES_2040 : 0 ) | + ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ? + HAL_RATESERIES_HALFGI : 0 ) | + ((bf->bf_rcs[i].flags & ATH_RC_TX_STBC_FLAG) ? + HAL_RATESERIES_STBC: 0); +#else + series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ? + HAL_RATESERIES_RTS_CTS : 0 ) | + ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ? + HAL_RATESERIES_2040 : 0 ) | + ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ? + HAL_RATESERIES_HALFGI : 0 ); +#endif + series[i].PktDuration = ath_pkt_duration(sc, rix, bf, + (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0, + (bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG)); + + series[i].ChSel = sc->sc_ic.ic_tx_chainmask; + + if (prot_mode) + series[i].RateFlags |= HAL_RATESERIES_RTS_CTS; + + if (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG) + series[i].RateFlags |= HAL_RATESERIES_RTS_CTS; + } + + rtsctsrate = rt->info[cix].rateCode | + (bf->bf_shpream ? rt->info[cix].shortPreamble : 0); + + ath_hal_set11n_ratescenario(ah, ds, 1, + rtsctsrate, ctsduration, + series, 4, + flags); +} + +static void ath_tgt_rate_findrate(struct ath_softc_tgt *sc, + struct ath_node_target *an, + a_int32_t shortPreamble, + size_t frameLen, + a_int32_t numTries, + a_int32_t numRates, + a_int32_t stepDnInc, + a_uint32_t rcflag, + struct ath_rc_series series[], + a_int32_t *isProbe) +{ + ath_rate_findrate(sc, an, 1, frameLen, 10, 4, 1, + ATH_RC_PROBE_ALLOWED, series, isProbe); +} + +static void owl_tgt_tid_init(struct ath_atx_tid *tid) +{ + int i; + + tid->seq_start = tid->seq_next = 0; + tid->baw_size = WME_MAX_BA; + tid->baw_head = tid->baw_tail = 0; + tid->paused = 0; + tid->flag = 0; + tid->sched = AH_FALSE; + + asf_tailq_init(&tid->buf_q); + + for (i = 0; i < ATH_TID_MAX_BUFS; i++) { + TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, i); + } +} + +static void owl_tgt_tid_cleanup(struct ath_softc_tgt *sc, + struct ath_atx_tid *tid) +{ + tid->incomp--; + if (tid->incomp) { + return; + } + + tid->flag &= ~TID_CLEANUP_INPROGRES; + + if (tid->flag & TID_REINITIALIZE) { + adf_os_print("TID REINIT DONE for tid %p\n", tid); + tid->flag &= ~TID_REINITIALIZE; + owl_tgt_tid_init(tid); + } else { + ath_aggr_resume_tid(sc, tid); + } +} + +void owl_tgt_node_init(struct ath_node_target * an) +{ + struct ath_atx_tid *tid; + int tidno, i; + + for (tidno = 0, tid = &an->tid[tidno]; tidno < WME_NUM_TID;tidno++, tid++) { + tid->tidno = tidno; + tid->an = an; + + if ( tid->flag & TID_CLEANUP_INPROGRES ) { + tid->flag |= TID_REINITIALIZE; + adf_os_print("tid[%p]->incomp is not 0: %d\n", + tid, tid->incomp); + } else { + owl_tgt_tid_init(tid); + } + } +} + +void ath_tx_status_clear(struct ath_softc_tgt *sc) +{ + int i; + + for (i = 0; i < 2; i++) { + sc->tx_status[i].cnt = 0; + } +} + +struct WMI_TXSTATUS_EVENT* ath_tx_status_get(struct ath_softc_tgt *sc) +{ + WMI_TXSTATUS_EVENT *txs = NULL; + int i; + + for (i = 0; i < 2; i++) { + if (sc->tx_status[i].cnt < HTC_MAX_TX_STATUS) { + txs = &sc->tx_status[i]; + break; + } + } + + return txs; +} + +void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ath_tx_desc *ds = bf->bf_lastds; + WMI_TXSTATUS_EVENT *txs; + + if (sc->sc_tx_draining) + return; + + txs = ath_tx_status_get(sc); + if (txs == NULL) + return; + + txs->txstatus[txs->cnt].cookie = bf->bf_cookie; + txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID); + + if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) + txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_FILT; + + if (!(ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) && + !(ds->ds_txstat.ts_status & HAL_TXERR_FIFO) && + !(ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) && + !(ds->ds_txstat.ts_status & HAL_TXERR_FILT)) + txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK; + + ath_tx_status_update_rate(sc, bf->bf_rcs, ds->ds_txstat.ts_rate, txs); + + txs->cnt++; +} + +void ath_tx_status_update_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, + struct ath_tx_desc *ds, struct ath_rc_series rcs[], + int txok) +{ + WMI_TXSTATUS_EVENT *txs; + + if (sc->sc_tx_draining) + return; + + txs = ath_tx_status_get(sc); + if (txs == NULL) + return; + + txs->txstatus[txs->cnt].cookie = bf->bf_cookie; + txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID); + + if (txok) + txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK; + + if (rcs) + ath_tx_status_update_rate(sc, rcs, ds->ds_txstat.ts_rate, txs); + + txs->cnt++; +} + +void ath_tx_status_send(struct ath_softc_tgt *sc) +{ + int i; + + if (sc->sc_tx_draining) + return; + + for (i = 0; i < 2; i++) { + if (sc->tx_status[i].cnt) { + wmi_event(sc->tgt_wmi_handle, WMI_TXSTATUS_EVENTID, + &sc->tx_status[i], sizeof(WMI_TXSTATUS_EVENT)); + /* FIXME: Handle failures. */ + sc->tx_status[i].cnt = 0; + } + } +} + +static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq) +{ + ath_hal_intrset(sc->sc_ah, sc->sc_imask & ~HAL_INT_SWBA); + owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE); + ath_hal_intrset(sc->sc_ah, sc->sc_imask); +} + +void owl_tgt_tx_tasklet(TQUEUE_ARG data) +{ + struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data; + a_int32_t i; + a_uint32_t qcumask = ((1 << HAL_NUM_TX_QUEUES) - 1); + struct ath_txq *txq; + ath_data_hdr_t *dh; + + ath_tx_status_clear(sc); + + for (i = 0; i < (HAL_NUM_TX_QUEUES - 6); i++) { + txq = ATH_TXQ(sc, i); + + if (ATH_TXQ_SETUP(sc, i)) { + if (txq == sc->sc_cabq) + owltgt_tx_process_cabq(sc, txq); + else + owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE); + } + } + + ath_tx_status_send(sc); +} + +void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq, + owl_txq_state_t txqstate) +{ + struct ath_tx_buf *bf; + struct ath_tx_desc *ds; + HAL_STATUS status; + + for (;;) { + if (asf_tailq_empty(&txq->axq_q)) { + txq->axq_link = NULL; + txq->axq_linkbuf = NULL; + break; + } + + bf = asf_tailq_first(&txq->axq_q); + + ds = bf->bf_lastds; + status = ath_hal_txprocdesc(sc->sc_ah, ds); + + if (status == HAL_EINPROGRESS) { + if (txqstate == OWL_TXQ_ACTIVE) + break; + else if (txqstate == OWL_TXQ_STOPPED) { + __stats(sc, tx_stopfiltered); + ds->ds_txstat.ts_flags = 0; + ds->ds_txstat.ts_status = HAL_OK; + } else { + ds->ds_txstat.ts_flags = HAL_TX_SW_FILTERED; + } + } + + ATH_TXQ_REMOVE_HEAD(txq, bf, bf_list); + if ((asf_tailq_empty(&txq->axq_q))) { + __stats(sc, tx_qnull); + txq->axq_link = NULL; + txq->axq_linkbuf = NULL; + } + + if (bf->bf_comp) { + bf->bf_comp(sc, bf); + } else { + ath_tx_status_update(sc, bf); + ath_buf_comp(sc, bf); + } + + if (txqstate == OWL_TXQ_ACTIVE) { + ath_tgt_txq_schedule(sc, txq); + } + } +} + +static struct ieee80211_frame* ATH_SKB2_WH(adf_nbuf_t skb) +{ + a_uint8_t *anbdata; + a_uint32_t anblen; + + adf_nbuf_peek_header(skb, &anbdata, &anblen); + return((struct ieee80211_frame *)anbdata); +} + +void +ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid) +{ + struct ath_tx_buf *bf; + + while (!asf_tailq_empty(&tid->buf_q)) { + TAILQ_DEQ(&tid->buf_q, bf, bf_list); + ath_tx_freebuf(sc, bf); + } + + tid->seq_next = tid->seq_start; + tid->baw_tail = tid->baw_head; +} + +static void ath_tgt_tx_comp_normal(struct ath_softc_tgt *sc, + struct ath_tx_buf *bf) +{ + struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); + struct ath_desc *ds = bf->bf_lastds; + ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); + + if (tid->flag & TID_CLEANUP_INPROGRES) { + owl_tgt_tid_cleanup(sc, tid); + } + + if (bf->bf_node) { + ath_tx_uc_comp(sc, bf); + } + + ath_tx_freebuf(sc, bf); +} + +static struct ieee80211_node_target * ath_tgt_find_node(struct ath_softc_tgt *sc, + a_int32_t node_index) +{ + struct ath_node_target *an; + a_int32_t i; + struct ieee80211_node_target *ni; + + if (node_index > TARGET_NODE_MAX) + return NULL; + + an = &sc->sc_sta[node_index]; + ni = &an->ni; + + if (an->an_valid) { + if (ni->ni_vap == NULL) { + return NULL; + } + return ni; + } + + return NULL; +} + +static struct ath_buf* ath_buf_alloc(struct ath_softc_tgt *sc) +{ + struct ath_tx_buf *bf = NULL; + + bf = asf_tailq_first(&sc->sc_txbuf); + if (bf != NULL) { + adf_os_mem_set(&bf->bf_state, 0, sizeof(struct ath_buf_state)); + asf_tailq_remove(&sc->sc_txbuf, bf, bf_list); + } else { + adf_os_assert(0); + } + + return bf; +} + +struct ath_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, + adf_nbuf_t skb, ath_data_hdr_t *dh) +{ + struct ath_tx_buf *bf; + struct ath_txq *txq; + struct ieee80211_node_target *ni; + a_uint32_t flags = adf_os_ntohl(dh->flags); + struct ath_atx_tid *tid; + + ni = ath_tgt_find_node(sc, dh->ni_index); + if (ni == NULL) + return NULL; + + tid = ATH_AN_2_TID(ATH_NODE_TARGET(ni), dh->tidno); + if (tid->flag & TID_REINITIALIZE) { + adf_os_print("drop frame due to TID reinit\n"); + return NULL; + } + + bf = ath_buf_alloc(sc); + if (!bf) { + __stats(sc, tx_nobufs); + return NULL; + } + + bf->bf_tidno = dh->tidno; + bf->bf_txq = TID_TO_ACTXQ(bf->bf_tidno); + bf->bf_keytype = dh->keytype; + bf->bf_keyix = dh->keyix; + bf->bf_protmode = dh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY); + bf->bf_node = (struct ath_node_target *)ni; + + adf_nbuf_queue_add(&bf->bf_skbhead, skb); + skb = adf_nbuf_queue_first(&(bf->bf_skbhead)); + + if (adf_nbuf_queue_len(&(bf->bf_skbhead)) == 0) { + __stats(sc, tx_noskbs); + return NULL; + } + + adf_os_assert(skb); + + bf->bf_skb = skb; + + ath_tgt_txbuf_setup(sc, bf, dh); + ath_dma_map(sc, bf); + ath_tx_tgt_setds(sc, bf); + + return bf; +} + +static void ath_tgt_tx_seqno_normal(struct ath_tx_buf *bf) +{ + struct ieee80211_node_target *ni = bf->bf_node; + struct ath_node_target *an = ATH_NODE_TARGET(ni); + struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb); + struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno); + + u_int8_t fragno = (wh->i_seq[0] & 0xf); + + INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX); + + bf->bf_seqno = (tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); + + *(u_int16_t *)wh->i_seq = adf_os_cpu_to_le16(bf->bf_seqno); + wh->i_seq[0] |= fragno; + + if (!(wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)) + INCR(tid->seq_next, IEEE80211_SEQ_MAX); +} + +static a_int32_t ath_key_setup(struct ieee80211_node_target *ni, + struct ath_tx_buf *bf) +{ + struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb); + const struct ieee80211_cipher *cip; + struct ieee80211_key *k; + + if (!(wh->i_fc[1] & IEEE80211_FC1_WEP)) { + bf->bf_keytype = HAL_KEY_TYPE_CLEAR; + bf->bf_keyix = HAL_TXKEYIX_INVALID; + return 0; + } + + switch (bf->bf_keytype) { + case HAL_KEY_TYPE_WEP: + bf->bf_pktlen += IEEE80211_WEP_ICVLEN; + break; + case HAL_KEY_TYPE_AES: + bf->bf_pktlen += IEEE80211_WEP_MICLEN; + break; + case HAL_KEY_TYPE_TKIP: + bf->bf_pktlen += IEEE80211_WEP_ICVLEN; + break; + default: + break; + } + + if (bf->bf_keytype == HAL_KEY_TYPE_AES || + bf->bf_keytype == HAL_KEY_TYPE_TKIP) + ieee80211_tgt_crypto_encap(wh, ni, bf->bf_keytype); + + return 0; +} + +static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ath_hal *ah = sc->sc_ah; + struct ath_txq *txq; + struct ath_node_target *an; + HAL_STATUS status; + static a_int32_t count = 0,i; + volatile a_int32_t txe_val; + + adf_os_assert(bf); + + txq = bf->bf_txq; + + status = ath_hal_txprocdesc(sc->sc_ah, bf->bf_lastds); + + ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); + + if (txq->axq_link == NULL) { + ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf)); + } else { + *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf); + + txe_val = OS_REG_READ(ah, 0x840); + if (!(txe_val & (1<< txq->axq_qnum))) + ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf)); + } + + txq->axq_link = &bf->bf_lastds->ds_link; + ath_hal_txstart(ah, txq->axq_qnum); +} + +static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc, + struct ath_tx_buf *bf, + ath_data_hdr_t *dh) + +{ + struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); + struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb); + struct ieee80211_node_target *ni = (struct ieee80211_node_target *)an; + struct ieee80211vap_target *vap = ni->ni_vap; + struct ieee80211com_target *ic = &sc->sc_ic; + a_int32_t retval, fragno = 0; + a_uint32_t flags = adf_os_ntohl(dh->flags); + + ath_tgt_tx_seqno_normal(bf); + + bf->bf_txq_add = ath_tgt_txq_add_ucast; + bf->bf_hdrlen = ieee80211_anyhdrsize(wh); + bf->bf_pktlen = ath_get_pktlen(bf, bf->bf_hdrlen); + bf->bf_ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); + + if ((retval = ath_key_setup(bf->bf_node, bf)) < 0) + return retval; + + if (flags & ATH_SHORT_PREAMBLE) + bf->bf_shpream = AH_TRUE; + else + bf->bf_shpream = AH_FALSE; + + bf->bf_flags = HAL_TXDESC_CLRDMASK; + bf->bf_atype = HAL_PKT_TYPE_NORMAL; + + return 0; +} + +static a_int32_t +ath_get_pktlen(struct ath_buf *bf, a_int32_t hdrlen) +{ + adf_nbuf_t skb = bf->bf_skb; + a_int32_t pktlen; + + skb = adf_nbuf_queue_first(&bf->bf_skbhead); + pktlen = adf_nbuf_len(skb); + + pktlen -= (hdrlen & 3); + pktlen += IEEE80211_CRC_LEN; + + return pktlen; +} + +void +ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ath_node_target *an = bf->bf_node; + struct ath_rc_series rcs[4]; + struct ath_rc_series mrcs[4]; + a_int32_t shortPreamble = 0; + a_int32_t isProbe = 0; + + adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4 ); + adf_os_mem_set(mrcs, 0, sizeof(struct ath_rc_series)*4 ); + + if (!bf->bf_ismcast) { + ath_tgt_rate_findrate(sc, an, shortPreamble, + 0, 0, 0, 0, 0, + rcs, &isProbe); + memcpy(bf->bf_rcs, rcs, sizeof(rcs)); + } else { + mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0; + mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0; + mrcs[0].rix = 0; + mrcs[0].tries = 1; + mrcs[0].flags = 0; + memcpy(bf->bf_rcs, mrcs, sizeof(mrcs)); + } + + ath_buf_set_rate(sc, bf); + bf->bf_txq_add(sc, bf); +} + +static void +ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + a_int32_t i ; + struct ath_desc *bfd = NULL; + + for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) { + ath_hal_clr11n_aggr(sc->sc_ah, bfd); + ath_hal_set11n_burstduration(sc->sc_ah, bfd, 0); + ath_hal_set11n_virtualmorefrag(sc->sc_ah, bfd, 0); + } + + ath_dma_unmap(sc, bf); + + ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt); + + bf->bf_skb = NULL; + bf->bf_comp = NULL; + bf->bf_node = NULL; + bf->bf_next = NULL; + bf = ath_buf_toggle(sc, bf, 0); + bf->bf_retries = 0; + bf->bf_isretried = 0; + + if (bf != NULL) + asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list); +} + +static void +ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + ath_tx_status_update(sc, bf); + ath_update_stats(sc, bf); + ath_rate_tx_complete(sc, ATH_NODE_TARGET(bf->bf_node), + bf->bf_lastds, bf->bf_rcs, 1, 0); +} + +static void +ath_update_stats(struct ath_softc_tgt *sc, struct ath_buf *bf) +{ + struct ieee80211_node_target *ni = bf->bf_node; + struct ath_tx_desc *ds = bf->bf_desc; + struct ath_node_target *an = ATH_NODE_TARGET(ni); + u_int32_t sr, lr; + struct ieee80211_cb *cb; + + if (ds->ds_txstat.ts_status == 0) { + if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) + sc->sc_tx_stats.ast_tx_altrate++; + } else { + if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) + sc->sc_tx_stats.ast_tx_xretries++; + if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) + sc->sc_tx_stats.ast_tx_fifoerr++; + if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) + sc->sc_tx_stats.ast_tx_filtered++; + if (ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) + sc->sc_tx_stats.ast_tx_timer_exp++; + } + sr = ds->ds_txstat.ts_shortretry; + lr = ds->ds_txstat.ts_longretry; + sc->sc_tx_stats.ast_tx_shortretry += sr; + sc->sc_tx_stats.ast_tx_longretry += lr; +} + +void +ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb, + HTC_ENDPOINT_ID endpt) +{ + struct ieee80211_node_target *ni; + struct ieee80211vap_target *vap; + struct ath_vap_target *avp; + struct ath_hal *ah = sc->sc_ah; + a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data; + a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration, fval; + a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len; + struct ath_desc *ds=NULL, *ds0=NULL; + struct ath_txq *txq=NULL; + struct ath_tx_buf *bf; + HAL_PKT_TYPE atype; + const HAL_RATE_TABLE *rt; + HAL_BOOL shortPreamble; + struct ieee80211_frame *wh; + struct ath_rc_series rcs[4]; + HAL_11N_RATE_SERIES series[4]; + ath_mgt_hdr_t *mh; + struct ieee80211com_target *ic = &sc->sc_ic; + a_int8_t keyix; + + if (!hdr_buf) { + adf_nbuf_peek_header(skb, &data, &len); + adf_nbuf_pull_head(skb, sizeof(ath_mgt_hdr_t)); + } else { + adf_nbuf_peek_header(hdr_buf, &data, &len); + } + + adf_os_assert(len >= sizeof(ath_mgt_hdr_t)); + + mh = (ath_mgt_hdr_t *)data; + adf_nbuf_peek_header(skb, &data, &len); + wh = (struct ieee80211_frame *)data; + + adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4); + adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES)*4); + + bf = asf_tailq_first(&sc->sc_txbuf); + if (!bf) + goto fail; + + asf_tailq_remove(&sc->sc_txbuf, bf, bf_list); + + ni = ath_tgt_find_node(sc, mh->ni_index); + if (!ni) + goto fail; + + bf->bf_endpt = endpt; + bf->bf_cookie = mh->cookie; + bf->bf_protmode = mh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY); + txq = &sc->sc_txq[1]; + iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; + ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); + hdrlen = ieee80211_anyhdrsize(wh); + pktlen = len; + keyix = HAL_TXKEYIX_INVALID; + pktlen -= (hdrlen & 3); + pktlen += IEEE80211_CRC_LEN; + + if (iswep) + keyix = mh->keyix; + + adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE); + + bf->bf_skb = skb; + adf_nbuf_queue_add(&bf->bf_skbhead, skb); + + ds = bf->bf_desc; + rt = sc->sc_currates; + adf_os_assert(rt != NULL); + + if (mh->flags == ATH_SHORT_PREAMBLE) + shortPreamble = AH_TRUE; + else + shortPreamble = AH_FALSE; + + flags = HAL_TXDESC_CLRDMASK; + + switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { + case IEEE80211_FC0_TYPE_MGT: + subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; + + if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) + atype = HAL_PKT_TYPE_PROBE_RESP; + else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) + atype = HAL_PKT_TYPE_ATIM; + else + atype = HAL_PKT_TYPE_NORMAL; + + break; + default: + atype = HAL_PKT_TYPE_NORMAL; + break; + } + + avp = &sc->sc_vap[mh->vap_index]; + + rcs[0].rix = ath_get_minrateidx(sc, avp); + rcs[0].tries = ATH_TXMAXTRY; + rcs[0].flags = 0; + + adf_os_mem_copy(bf->bf_rcs, rcs, sizeof(rcs)); + rix = rcs[0].rix; + try0 = rcs[0].tries; + txrate = rt->info[rix].rateCode; + + if (shortPreamble){ + txrate |= rt->info[rix].shortPreamble; + } + + vap = ni->ni_vap; + bf->bf_node = ni; + + if (ismcast) { + flags |= HAL_TXDESC_NOACK; + try0 = 1; + } else if (pktlen > vap->iv_rtsthreshold) { + flags |= HAL_TXDESC_RTSENA; + cix = rt->info[rix].controlRate; + } + + if ((bf->bf_protmode != IEEE80211_PROT_NONE) && + rt->info[rix].phy == IEEE80211_T_OFDM && + (flags & HAL_TXDESC_NOACK) == 0) { + cix = rt->info[sc->sc_protrix].controlRate; + sc->sc_tx_stats.ast_tx_protect++; + } + + *(a_uint16_t *)&wh->i_seq[0] = adf_os_cpu_to_le16(ni->ni_txseqmgmt << + IEEE80211_SEQ_SEQ_SHIFT); + INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX); + + ctsduration = 0; + if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { + adf_os_assert(cix != 0xff); + ctsrate = rt->info[cix].rateCode; + if (shortPreamble) { + ctsrate |= rt->info[cix].shortPreamble; + if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ + ctsduration += rt->info[cix].spAckDuration; + if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ + ctsduration += rt->info[cix].spAckDuration; + } else { + if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ + ctsduration += rt->info[cix].lpAckDuration; + if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ + ctsduration += rt->info[cix].lpAckDuration; + } + ctsduration += ath_hal_computetxtime(ah, + rt, pktlen, rix, shortPreamble); + try0 = 1; + } else + ctsrate = 0; + + flags |= HAL_TXDESC_INTREQ; + + ath_hal_setuptxdesc(ah, ds + , pktlen + , hdrlen + , atype + , 60 + , txrate, try0 + , keyix + , 0 + , flags + , ctsrate + , ctsduration + , icvlen + , ivlen + , ATH_COMP_PROC_NO_COMP_NO_CCS); + + bf->bf_flags = flags; + + /* + * Set key type in tx desc while sending the encrypted challenge to AP + * in Auth frame 3 of Shared Authentication, owl needs this. + */ + if (iswep && (keyix != HAL_TXKEYIX_INVALID) && + (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH) + ath_hal_fillkeytxdesc(ah, ds, mh->keytype); + + ath_filltxdesc(sc, bf); + + for (i=0; i<4; i++) { + series[i].Tries = 2; + series[i].Rate = txrate; + series[i].ChSel = sc->sc_ic.ic_tx_chainmask; + series[i].RateFlags = 0; + } + ath_hal_set11n_ratescenario(ah, ds, 0, ctsrate, ctsduration, series, 4, 0); + ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds); + + return; +fail: + HTC_ReturnBuffers(sc->tgt_htc_handle, endpt, skb); + return; +} + +static void +ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, + struct ath_txq *txq, struct ath_buf *bf, + struct ath_desc *lastds) +{ + struct ath_hal *ah = sc->sc_ah; + + ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); + + if (txq->axq_link == NULL) { + ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf)); + } else { + *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf); + } + + txq->axq_link = &lastds->ds_link; + ath_hal_txstart(ah, txq->axq_qnum); +} + +void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + ath_atx_tid_t *tid; + struct ath_node_target *an; + struct ath_desc *ds; + struct ath_txq *txq = bf->bf_txq; + a_bool_t queue_frame; + + an = (struct ath_node_target *)bf->bf_node; + adf_os_assert(an); + + tid = &an->tid[bf->bf_tidno]; + adf_os_assert(tid); + + bf->bf_comp = ath_tgt_tx_comp_normal; + INCR(tid->seq_start, IEEE80211_SEQ_MAX); + ath_tgt_tx_send_normal(sc, bf); +} + +static void +ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid) +{ + if (tid->paused) + return; + + if (tid->sched) + return; + + tid->sched = AH_TRUE; + asf_tailq_insert_tail(&txq->axq_tidq, tid, tid_qelem); +} + +static void +ath_tgt_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) +{ + struct ath_atx_tid *tid; + u_int8_t bdone; + HAL_STATUS status; + u_int8_t smps_mode; + struct ieee80211_node *ieee_node; + u_int32_t aggr_limit_with_rts; + + bdone = AH_FALSE; + + do { + TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem); + + if (tid == NULL) + return; + + tid->sched = AH_FALSE; + + if (tid->paused) + continue; + + if (!(tid->flag & TID_AGGR_ENABLED)) + ath_tgt_tx_sched_normal(sc,tid); + else + ath_tgt_tx_sched_aggr(sc,tid); + + bdone = AH_TRUE; + + if (!asf_tailq_empty(&tid->buf_q)) { + ath_tgt_tx_enqueue(txq, tid); + } + + } while (!asf_tailq_empty(&txq->axq_tidq) && !bdone); +} + +void +ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + ath_atx_tid_t *tid; + struct ath_node_target *an; + struct ath_desc *ds; + struct ath_txq *txq = bf->bf_txq; + a_bool_t queue_frame, within_baw; + + an = (struct ath_node_target *)bf->bf_node; + adf_os_assert(an); + + tid = &an->tid[bf->bf_tidno]; + adf_os_assert(tid); + + bf->bf_comp = ath_tgt_tx_comp_aggr; + + within_baw = BAW_WITHIN(tid->seq_start, tid->baw_size, + SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); + + queue_frame = ( (txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) || + (!asf_tailq_empty(&tid->buf_q)) || + (tid->paused) || (!within_baw) ); + + if (queue_frame) { + asf_tailq_insert_tail(&tid->buf_q, bf, bf_list); + ath_tgt_tx_enqueue(txq, tid); + } else { + ath_tx_addto_baw(tid, bf); + __stats(sc, txaggr_nframes); + ath_tgt_tx_send_normal(sc, bf); + } +} + +static void +ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid) +{ + struct ath_buf *bf; + struct ath_txq *txq =TID_TO_ACTXQ(tid->tidno);; + + do { + if (asf_tailq_empty(&tid->buf_q)) + break; + + bf = asf_tailq_first(&tid->buf_q); + asf_tailq_remove(&tid->buf_q, bf, bf_list); + ath_tgt_tx_send_normal(sc, bf); + + } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH); +} + +static void +ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid) +{ + struct ath_tx_buf *bf, *bf_last; + ATH_AGGR_STATUS status; + ath_bufhead bf_q; + struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno); + struct ath_desc *ds = NULL; + int i; + + + if (asf_tailq_empty(&tid->buf_q)) + return; + + do { + if (asf_tailq_empty(&tid->buf_q)) + break; + + asf_tailq_init(&bf_q); + + status = ath_tgt_tx_form_aggr(sc, tid, &bf_q); + + if (asf_tailq_empty(&bf_q)) + break; + + bf = asf_tailq_first(&bf_q); + bf_last = asf_tailq_last(&bf_q, ath_bufhead_s); + + if (bf->bf_nframes == 1) { + + if(bf->bf_retries == 0) + __stats(sc, txaggr_single); + bf->bf_isaggr = 0; + bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs -1]); + bf->bf_lastds->ds_link = 0; + bf->bf_next = NULL; + + for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++) + ath_hal_clr11n_aggr(sc->sc_ah, ds); + + ath_buf_set_rate(sc, bf); + bf->bf_txq_add(sc, bf); + + continue; + } + + bf_last->bf_next = NULL; + bf_last->bf_lastds->ds_link = 0; + bf_last->bf_ndelim = 0; + + bf->bf_isaggr = 1; + ath_buf_set_rate(sc, bf); + ath_hal_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al, + bf->bf_ndelim); + bf->bf_lastds = bf_last->bf_lastds; + + for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++) + ath_hal_set11n_aggr_last(sc->sc_ah, &bf_last->bf_descarr[i]); + + if (status == ATH_AGGR_8K_LIMITED) { + adf_os_assert(0); + break; + } + + bf->bf_txq_add(sc, bf); + } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && + status != ATH_TGT_AGGR_BAW_CLOSED); +} + +static u_int32_t ath_lookup_rate(struct ath_softc_tgt *sc, + struct ath_node_target *an, + struct ath_tx_buf *bf) +{ + int i, prate; + u_int32_t max4msframelen, frame_length; + u_int16_t aggr_limit, legacy=0; + const HAL_RATE_TABLE *rt = sc->sc_currates; + struct ieee80211_node_target *ieee_node = (struct ieee80211_node_target *)an; + + if (bf->bf_ismcast) { + bf->bf_rcs[1].tries = bf->bf_rcs[2].tries = bf->bf_rcs[3].tries = 0; + bf->bf_rcs[0].rix = 0xb; + bf->bf_rcs[0].tries = ATH_TXMAXTRY - 1; + bf->bf_rcs[0].flags = 0; + } else { + ath_tgt_rate_findrate(sc, an, AH_TRUE, 0, ATH_TXMAXTRY-1, 4, 1, + ATH_RC_PROBE_ALLOWED, bf->bf_rcs, &prate); + } + + max4msframelen = IEEE80211_AMPDU_LIMIT_MAX; + + for (i = 0; i < 4; i++) { + if (bf->bf_rcs[i].tries) { + frame_length = bf->bf_rcs[i].max4msframelen; + + if (rt->info[bf->bf_rcs[i].rix].phy != IEEE80211_T_HT) { + legacy = 1; + break; + } + + max4msframelen = ATH_MIN(max4msframelen, frame_length); + } + } + + if (prate || legacy) + return 0; + + if (sc->sc_ic.ic_enable_coex) + aggr_limit = ATH_MIN((max4msframelen*3)/8, sc->sc_ic.ic_ampdu_limit); + else + aggr_limit = ATH_MIN(max4msframelen, sc->sc_ic.ic_ampdu_limit); + + if (ieee_node->ni_maxampdu) + aggr_limit = ATH_MIN(aggr_limit, ieee_node->ni_maxampdu); + + return aggr_limit; +} + +int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, + ath_bufhead *bf_q) +{ + struct ath_tx_buf *bf_first ,*bf_prev = NULL; + int nframes = 0, rl = 0;; + struct ath_desc *ds = NULL; + struct ath_tx_buf *bf; + u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta; + u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0; + + bf_first = asf_tailq_first(&tid->buf_q); + + do { + bf = asf_tailq_first(&tid->buf_q); + adf_os_assert(bf); + + if (!BAW_WITHIN(tid->seq_start, tid->baw_size, + SEQNO_FROM_BF_SEQNO(bf->bf_seqno))) { + + bf_first->bf_al= al; + bf_first->bf_nframes = nframes; + return ATH_TGT_AGGR_BAW_CLOSED; + } + + if (!rl) { + aggr_limit = ath_lookup_rate(sc, tid->an, bf); + rl = 1; + } + + al_delta = ATH_AGGR_DELIM_SZ + bf->bf_pktlen; + + if (nframes && (aggr_limit < (al + bpad + al_delta + prev_al))) { + bf_first->bf_al= al; + bf_first->bf_nframes = nframes; + return ATH_TGT_AGGR_LIMITED; + } + +#ifdef PROJECT_K2 + if ((nframes + prev_frames) >= ATH_MIN((h_baw), 17)) { +#else + if ((nframes + prev_frames) >= ATH_MIN((h_baw), 22)) { +#endif + bf_first->bf_al= al; + bf_first->bf_nframes = nframes; + return ATH_TGT_AGGR_LIMITED; + } + + ath_tx_addto_baw(tid, bf); + asf_tailq_remove(&tid->buf_q, bf, bf_list); + asf_tailq_insert_tail(bf_q, bf, bf_list); + nframes ++; + + adf_os_assert(bf); + + adf_os_assert(bf->bf_comp == ath_tgt_tx_comp_aggr); + + al += bpad + al_delta; + bf->bf_ndelim = ATH_AGGR_GET_NDELIM(bf->bf_pktlen); + + switch (bf->bf_keytype) { + case HAL_KEY_TYPE_AES: + bf->bf_ndelim += ATH_AGGR_ENCRYPTDELIM; + break; + case HAL_KEY_TYPE_WEP: + case HAL_KEY_TYPE_TKIP: + bf->bf_ndelim += 64; + break; + case HAL_KEY_TYPE_WAPI: + bf->bf_ndelim += 12; + break; + default: + break; + } + + bpad = PADBYTES(al_delta) + (bf->bf_ndelim << 2); + + if (bf_prev) { + bf_prev->bf_next = bf; + bf_prev->bf_lastds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR(bf); + } + bf_prev = bf; + + for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++) + ath_hal_set11n_aggr_middle(sc->sc_ah, ds, bf->bf_ndelim); + + } while (!asf_tailq_empty(&tid->buf_q)); + + bf_first->bf_al= al; + bf_first->bf_nframes = nframes; + + return ATH_TGT_AGGR_DONE; +} + +void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf) +{ + int index, cindex; + + if (bf->bf_isretried) { + return; + } + + index = ATH_BA_INDEX(tid->seq_start, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); + cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); + + TX_BUF_BITMAP_SET(tid->tx_buf_bitmap, cindex); + + if (index >= ((tid->baw_tail - tid->baw_head) & (ATH_TID_MAX_BUFS - 1))) { + tid->baw_tail = cindex; + INCR(tid->baw_tail, ATH_TID_MAX_BUFS); + } +} + +void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); + ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); + struct ath_tx_desc lastds; + struct ath_tx_desc *ds = &lastds; + struct ath_rc_series rcs[4]; + u_int16_t seq_st; + u_int32_t *ba; + int ba_index; + int nbad = 0; + int nframes = bf->bf_nframes; + struct ath_buf *bf_next; + ath_bufhead bf_q; + int tx_ok = 1; + struct ath_buf *bar = NULL; + struct ath_txq *txq; + + txq = bf->bf_txq; + + if (tid->flag & TID_CLEANUP_INPROGRES) { + ath_tx_comp_cleanup(sc, bf); + return; + } + + adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc)); + adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs)); + + if (ds->ds_txstat.ts_flags == HAL_TX_SW_FILTERED) { + adf_os_assert(0); + return; + } + + if (!bf->bf_isaggr) { + ath_tx_comp_unaggr(sc, bf); + return; + } + + __stats(sc, tx_compaggr); + + asf_tailq_init(&bf_q); + + seq_st = ATH_DS_BA_SEQ(ds); + ba = ATH_DS_BA_BITMAP(ds); + tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK); + + if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) { + ath_tx_comp_aggr_error(sc, bf, tid); + return; + } + + if (tx_ok && !ATH_DS_TX_BA(ds)) { + __stats(sc, txaggr_babug); + adf_os_print("BA Bug?\n"); + ath_tx_comp_aggr_error(sc, bf, tid); + return; + } + + while (bf) { + ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); + bf_next = bf->bf_next; + + if (tx_ok && ATH_BA_ISSET(ba, ba_index)) { + __stats(sc, txaggr_compgood); + ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); + ath_tx_status_update_aggr(sc, bf, ds, rcs, 1); + ath_tx_freebuf(sc, bf); + } else { + ath_tx_retry_subframe(sc, bf, &bf_q, &bar); + nbad ++; + } + bf = bf_next; + } + + ath_update_aggr_stats(sc, ds, nframes, nbad); + ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad); + + if (bar) { + ath_bar_tx(sc, tid, bar); + } + + if (!asf_tailq_empty(&bf_q)) { + __stats(sc, txaggr_prepends); + TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list); + ath_tgt_tx_enqueue(txq, tid); + } +} + +static void +ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, + ath_atx_tid_t *tid) +{ + + + struct ath_tx_desc lastds; + struct ath_desc *ds = &lastds; + struct ath_rc_series rcs[4]; + struct ath_buf *bar = NULL; + struct ath_buf *bf_next; + int nframes = bf->bf_nframes; + ath_bufhead bf_q; + struct ath_txq *txq; + + asf_tailq_init(&bf_q); + txq = bf->bf_txq; + + adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc)); + adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs)); + + while (bf) { + bf_next = bf->bf_next; + ath_tx_retry_subframe(sc, bf, &bf_q, &bar); + bf = bf_next; + } + + ath_update_aggr_stats(sc, ds, nframes, nframes); + ath_rate_tx_complete(sc, tid->an, ds, rcs, nframes, nframes); + + if (bar) { + ath_bar_tx(sc, tid, bar); + } + + if (!asf_tailq_empty(&bf_q)) { + __stats(sc, txaggr_prepends); + TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list); + ath_tgt_tx_enqueue(txq, tid); + } +} + +static void +ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + + struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); + ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); + struct ath_tx_desc lastds; + struct ath_tx_desc *ds = &lastds; + struct ath_rc_series rcs[4]; + u_int16_t seq_st; + u_int32_t *ba; + int ba_index; + int nbad = 0; + int nframes = bf->bf_nframes; + struct ath_buf *bf_next; + int tx_ok = 1; + + adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc)); + adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs)); + + seq_st = ATH_DS_BA_SEQ(ds); + ba = ATH_DS_BA_BITMAP(ds); + tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK); + + if (!bf->bf_isaggr) { + ath_update_stats(sc, bf); + + __stats(sc, tx_compunaggr); + + ath_tx_status_update(sc, bf); + + ath_tx_freebuf(sc, bf); + + if (tid->flag & TID_CLEANUP_INPROGRES) { + owl_tgt_tid_cleanup(sc, tid); + + } + + return; + } + + while (bf) { + ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); + bf_next = bf->bf_next; + + ath_tx_status_update_aggr(sc, bf, ds, rcs, 0); + + ath_tx_freebuf(sc, bf); + + tid->incomp--; + if (!tid->incomp) { + tid->flag &= ~TID_CLEANUP_INPROGRES; + ath_aggr_resume_tid(sc, tid); + break; + } + + bf = bf_next; + } + + ath_update_aggr_stats(sc, ds, nframes, nbad); + ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad); +} + +static void +ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, + ath_bufhead *bf_q, struct ath_tx_buf **bar) +{ + + struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); + ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); + struct ath_desc *ds = NULL; + int i = 0; + + __stats(sc, txaggr_compretries); + + for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) { + ath_hal_clr11n_aggr(sc->sc_ah, ds); + ath_hal_set11n_burstduration(sc->sc_ah, ds, 0); + ath_hal_set11n_virtualmorefrag(sc->sc_ah, ds, 0); + } + + if (bf->bf_retries >= OWLMAX_RETRIES) { + __stats(sc, txaggr_xretries); + ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); + ath_tx_status_update_aggr(sc, bf, bf->bf_lastds, NULL, 0); + + if (!*bar) + *bar = bf; + else + ath_tx_freebuf(sc, bf); + return; + } + + if (!bf->bf_next) { + __stats(sc, txaggr_errlast); + bf = ath_buf_toggle(sc, bf, 1); + } else + bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs - 1]); + + ath_tx_set_retry(sc, bf); + asf_tailq_insert_tail(bf_q, bf, bf_list); +} + +static void +ath_update_aggr_stats(struct ath_softc_tgt *sc, + struct ath_tx_desc *ds, int nframes, + int nbad) +{ + + u_int8_t status = ATH_DS_TX_STATUS(ds); + u_int8_t txflags = ATH_DS_TX_FLAGS(ds); + + __statsn(sc, txaggr_longretries, ds->ds_txstat.ts_longretry); + __statsn(sc, txaggr_shortretries, ds->ds_txstat.ts_shortretry); + + if (txflags & HAL_TX_DESC_CFG_ERR) + __stats(sc, txaggr_desc_cfgerr); + + if (txflags & HAL_TX_DATA_UNDERRUN) + __stats(sc, txaggr_data_urun); + + if (txflags & HAL_TX_DELIM_UNDERRUN) + __stats(sc, txaggr_delim_urun); + + if (!status) { + return; + } + + if (status & HAL_TXERR_XRETRY) + __stats(sc, txaggr_compxretry); + + if (status & HAL_TXERR_FILT) + __stats(sc, txaggr_filtered); + + if (status & HAL_TXERR_FIFO) + __stats(sc, txaggr_fifo); + + if (status & HAL_TXERR_XTXOP) + __stats(sc, txaggr_xtxop); + + if (status & HAL_TXERR_TIMER_EXPIRED) + __stats(sc, txaggr_timer_exp); +} + +static void +ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); + ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); + struct ath_desc *ds = bf->bf_lastds; + + ath_update_stats(sc, bf); + ath_rate_tx_complete(sc, an, ds, bf->bf_rcs, 1, 0); + + if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) { + ath_tx_retry_unaggr(sc, bf); + return; + } + __stats(sc, tx_compunaggr); + + ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); + ath_tx_status_update(sc, bf); + ath_tx_freebuf(sc, bf); +} + +static inline void +ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); + ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); + struct ath_txq *txq; + + txq = bf->bf_txq; + + if (bf->bf_retries >= OWLMAX_RETRIES) { + __stats(sc, txunaggr_xretry); + ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); + ath_tx_status_update(sc, bf); + ath_bar_tx(sc, tid, bf); + return; + } + + __stats(sc, txunaggr_compretries); + if (!bf->bf_lastds->ds_link) { + __stats(sc, txunaggr_errlast); + bf = ath_buf_toggle(sc, bf, 1); + } + + ath_tx_set_retry(sc, bf); + asf_tailq_insert_head(&tid->buf_q, bf, bf_list); + ath_tgt_tx_enqueue(txq, tid); +} + +static void +ath_tx_update_baw(ath_atx_tid_t *tid, int seqno) +{ + int index; + int cindex; + + index = ATH_BA_INDEX(tid->seq_start, seqno); + cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); + + TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, cindex); + + while (tid->baw_head != tid->baw_tail && + (!TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head))) { + INCR(tid->seq_start, IEEE80211_SEQ_MAX); + INCR(tid->baw_head, ATH_TID_MAX_BUFS); + } +} + +static void ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ieee80211_frame *wh; + + __stats(sc, txaggr_retries); + + bf->bf_isretried = 1; + bf->bf_retries ++; + wh = ATH_SKB_2_WH(bf->bf_skb); + wh->i_fc[1] |= IEEE80211_FC1_RETRY; +} + +void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an, + ath_atx_tid_t *tid, a_uint8_t discard_all) +{ + struct ath_tx_buf *bf; + struct ath_tx_buf *bf_next; + struct ath_txq *txq; + + txq = TID_TO_ACTXQ(tid->tidno); + + bf = asf_tailq_first(&tid->buf_q); + + while (bf) { + if (discard_all || bf->bf_isretried) { + bf_next = asf_tailq_next(bf, bf_list); + TAILQ_DEQ(&tid->buf_q, bf, bf_list); + if (bf->bf_isretried) + ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno)); + ath_tx_freebuf(sc, bf); + bf = bf_next; + continue; + } + bf->bf_comp = ath_tgt_tx_comp_normal; + bf = asf_tailq_next(bf, bf_list); + } + + ath_aggr_pause_tid(sc, tid); + + while (tid->baw_head != tid->baw_tail) { + if (TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head)) { + tid->incomp++; + tid->flag |= TID_CLEANUP_INPROGRES; + TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, tid->baw_head); + } + INCR(tid->baw_head, ATH_TID_MAX_BUFS); + INCR(tid->seq_start, IEEE80211_SEQ_MAX); + } + + if (!(tid->flag & TID_CLEANUP_INPROGRES)) { + ath_aggr_resume_tid(sc, tid); + } +} + +/******************/ +/* BAR Management */ +/******************/ + +static void ath_tgt_delba_send(struct ath_softc_tgt *sc, + struct ieee80211_node_target *ni, + a_uint8_t tidno, a_uint8_t initiator, + a_uint16_t reasoncode) +{ + struct ath_node_target *an = ATH_NODE_TARGET(ni); + ath_atx_tid_t *tid = ATH_AN_2_TID(an, tidno); + struct wmi_data_delba wmi_delba; + + tid->flag &= ~TID_AGGR_ENABLED; + + ath_tgt_tx_cleanup(sc, an, tid, 1); + + wmi_delba.ni_nodeindex = ni->ni_nodeindex; + wmi_delba.tidno = tid->tidno; + wmi_delba.initiator = 1; + wmi_delba.reasoncode = IEEE80211_REASON_UNSPECIFIED; + + __stats(sc, txbar_xretry); + wmi_event(sc->tgt_wmi_handle, + WMI_DELBA_EVENTID, + &wmi_delba, + sizeof(wmi_delba)); +} + +static void ath_bar_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node); + ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno); + + if (bf->bf_retries >= OWLMAX_BAR_RETRIES) { + ath_tgt_delba_send(sc, bf->bf_node, tid->tidno, 1, + IEEE80211_REASON_UNSPECIFIED); + ath_tgt_tid_drain(sc, tid); + + bf->bf_comp = NULL; + ath_buf_comp(sc, bf); + return; + } + + __stats(sc, txbar_compretries); + + if (!bf->bf_lastds->ds_link) { + __stats(sc, txbar_errlast); + bf = ath_buf_toggle(sc, bf, 1); + } + + bf->bf_lastds->ds_link = 0; + + ath_tx_set_retry(sc, bf); + ath_tgt_txq_add_ucast(sc, bf); +} + +static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf) +{ + struct ath_desc *ds = bf->bf_lastds; + struct ath_node_target *an; + ath_atx_tid_t *tid; + struct ath_txq *txq; + + an = (struct ath_node_target *)bf->bf_node; + tid = &an->tid[bf->bf_tidno]; + txq = TID_TO_ACTXQ(tid->tidno); + + if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) { + ath_bar_retry(sc, bf); + return; + } + + ath_aggr_resume_tid(sc, tid); + + bf->bf_comp = NULL; + ath_buf_comp(sc, bf); +} + +static void ath_bar_tx(struct ath_softc_tgt *sc, + ath_atx_tid_t *tid, struct ath_tx_buf *bf) +{ + adf_nbuf_t skb; + struct ieee80211_frame_bar *bar; + u_int8_t min_rate; + struct ath_desc *ds, *ds0; + HAL_11N_RATE_SERIES series[4]; + int i = 0; + adf_nbuf_queue_t skbhead; + a_uint8_t *anbdata; + a_uint32_t anblen; + + __stats(sc, tx_bars); + + memset(&series, 0, sizeof(series)); + + ath_aggr_pause_tid(sc, tid); + + skb = adf_nbuf_queue_remove(&bf->bf_skbhead); + adf_nbuf_peek_header(skb, &anbdata, &anblen); + adf_nbuf_trim_tail(skb, anblen); + bar = (struct ieee80211_frame_bar *) anbdata; + + min_rate = 0x0b; + + ath_dma_unmap(sc, bf); + adf_nbuf_queue_add(&bf->bf_skbhead, skb); + + bar->i_fc[1] = IEEE80211_FC1_DIR_NODS; + bar->i_fc[0] = IEEE80211_FC0_VERSION_0 | + IEEE80211_FC0_TYPE_CTL | + IEEE80211_FC0_SUBTYPE_BAR; + bar->i_ctl = tid->tidno << IEEE80211_BAR_CTL_TID_S | + IEEE80211_BAR_CTL_COMBA; + bar->i_seq = adf_os_cpu_to_le16(tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT); + + bf->bf_seqno = tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT; + + adf_nbuf_put_tail(skb, sizeof(struct ieee80211_frame_bar)); + + bf->bf_comp = ath_bar_tx_comp; + bf->bf_tidno = tid->tidno; + bf->bf_node = &tid->an->ni; + ath_dma_map(sc, bf); + adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info); + + ds = bf->bf_desc; + ath_hal_setuptxdesc(sc->sc_ah, ds + , adf_nbuf_len(skb) + IEEE80211_CRC_LEN + , 0 + , HAL_PKT_TYPE_NORMAL + , ATH_MIN(60, 60) + , min_rate + , ATH_TXMAXTRY + , bf->bf_keyix + , 0 + , HAL_TXDESC_INTREQ + | HAL_TXDESC_CLRDMASK + , 0, 0, 0, 0 + , ATH_COMP_PROC_NO_COMP_NO_CCS); + + skbhead = bf->bf_skbhead; + bf->bf_isaggr = 0; + bf->bf_next = NULL; + + for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) { + ath_hal_clr11n_aggr(sc->sc_ah, ds0); + } + + ath_filltxdesc(sc, bf); + + for (i = 0 ; i < 4; i++) { + series[i].Tries = ATH_TXMAXTRY; + series[i].Rate = min_rate; + series[i].ChSel = sc->sc_ic.ic_tx_chainmask; + } + + ath_hal_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 0, 0, 0, series, 4, 4); + ath_tgt_txq_add_ucast(sc, bf); +} diff --git a/target_firmware/wlan/include/athdefs.h b/target_firmware/wlan/include/athdefs.h new file mode 100755 index 0000000..61cc22c --- /dev/null +++ b/target_firmware/wlan/include/athdefs.h @@ -0,0 +1,84 @@ +#ifndef __ATHDEFS_H__ +#define __ATHDEFS_H__ + +/* + * This file contains definitions that may be used across both + * Host and Target software. Nothing here is module-dependent + * or platform-dependent. + */ + +/* + * Generic error codes that can be used by hw, sta, ap, sim, dk + * and any other environments. Since these are enums, feel free to + * add any more codes that you need. + */ + +typedef enum { + A_ERROR = -1, /* Generic error return */ + A_OK = 0, /* success */ + /* Following values start at 1 */ + A_DEVICE_NOT_FOUND, /* not able to find PCI device */ + A_NO_MEMORY, /* not able to allocate memory, not available */ + A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */ + A_NO_FREE_DESC, /* no free descriptors available */ + A_BAD_ADDRESS, /* address does not match descriptor */ + A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */ + A_REGS_NOT_MAPPED, /* registers not correctly mapped */ + A_EPERM, /* Not superuser */ + A_EACCES, /* Access denied */ + A_ENOENT, /* No such entry, search failed, etc. */ + A_EEXIST, /* The object already exists (can't create) */ + A_EFAULT, /* Bad address fault */ + A_EBUSY, /* Object is busy */ + A_EINVAL, /* Invalid parameter */ + A_EMSGSIZE, /* Inappropriate message buffer length */ + A_ECANCELED, /* Operation canceled */ + A_ENOTSUP, /* Operation not supported */ + A_ECOMM, /* Communication error on send */ + A_EPROTO, /* Protocol error */ + A_ENODEV, /* No such device */ + A_EDEVNOTUP, /* device is not UP */ + A_NO_RESOURCE, /* No resources for requested operation */ + A_HARDWARE, /* Hardware failure */ + A_PENDING, /* Asynchronous routine; will send up results la + ter (typically in callback) */ + A_EBADCHANNEL, /* The channel cannot be used */ + A_DECRYPT_ERROR, /* Decryption error */ + A_PHY_ERROR, /* RX PHY error */ + A_CONSUMED /* Object was consumed */ +} A_STATUS; + +#define A_SUCCESS(x) (x == A_OK) +#define A_FAILED(x) (!A_SUCCESS(x)) + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef NULL +#define NULL ((void *)0) +#endif + +/* + * The following definition is WLAN specific definition + */ +typedef enum { + MODE_11A = 0, /* 11a Mode */ + MODE_11G = 1, /* 11g + 11b Mode */ + MODE_11B = 2, /* 11b Mode */ + MODE_11GONLY = 3, /* 11g only Mode */ + MODE_UNKNOWN = 4, + MODE_MAX = 4 +} WLAN_PHY_MODE; + +typedef enum { + WLAN_11A_CAPABILITY = 1, + WLAN_11G_CAPABILITY = 2, + WLAN_11AG_CAPABILITY = 3, +} WLAN_CAPABILITY; + +#endif /* __ATHDEFS_H__ */ diff --git a/target_firmware/wlan/include/htc.h b/target_firmware/wlan/include/htc.h new file mode 100755 index 0000000..9b1b269 --- /dev/null +++ b/target_firmware/wlan/include/htc.h @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + */ + +#ifndef __HTC_H__ +#define __HTC_H__ + +#ifndef ATH_TARGET +#endif + +#define A_OFFSETOF(type,field) ((int)(&(((type *)NULL)->field))) + +#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \ + (((a_uint16_t)(((a_uint8_t *)(p))[(highbyte)])) << 8 | (a_uint16_t)(((a_uint8_t *)(p))[(lowbyte)])) + +/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a + * structure using only the type and field name. + * Use these macros if there is the potential for unaligned buffer accesses. */ +#define A_GET_UINT16_FIELD(p,type,field) \ + ASSEMBLE_UNALIGNED_UINT16(p, \ + A_OFFSETOF(type,field) + 1, \ + A_OFFSETOF(type,field)) + +#define A_SET_UINT16_FIELD(p,type,field,value) \ + { \ + ((a_uint8_t *)(p))[A_OFFSETOF(type,field)] = (a_uint8_t)((value) >> 8); \ + ((a_uint8_t *)(p))[A_OFFSETOF(type,field) + 1] = (a_uint8_t)(value); \ + } + +#define A_GET_UINT8_FIELD(p,type,field) \ + ((a_uint8_t *)(p))[A_OFFSETOF(type,field)] + +#define A_SET_UINT8_FIELD(p,type,field,value) \ + ((a_uint8_t *)(p))[A_OFFSETOF(type,field)] = (value) + +/****** DANGER DANGER *************** + * + * The frame header length and message formats defined herein were + * selected to accommodate optimal alignment for target processing. This reduces code + * size and improves performance. + * + * Any changes to the header length may alter the alignment and cause exceptions + * on the target. When adding to the message structures insure that fields are + * properly aligned. + * + */ + +/* endpoint defines */ +typedef enum +{ + ENDPOINT_UNUSED = -1, + ENDPOINT0 = 0, /* this is reserved for the control endpoint */ + ENDPOINT1 = 1, + ENDPOINT2 = 2, + ENDPOINT3 = 3, + ENDPOINT4, + ENDPOINT5, + ENDPOINT6, + ENDPOINT7, + ENDPOINT8, + ENDPOINT_MAX = 22 /* maximum number of endpoints for this firmware build, max application + endpoints = (ENDPOINT_MAX - 1) */ +} HTC_ENDPOINT_ID; + +/* HTC frame header */ +typedef PREPACK struct _HTC_FRAME_HDR{ + /* do not remove or re-arrange these fields, these are minimally required + * to take advantage of 4-byte lookaheads in some hardware implementations */ + a_uint8_t EndpointID; + a_uint8_t Flags; + a_uint16_t PayloadLen; /* length of data (including trailer) that follows the header */ + + /***** end of 4-byte lookahead ****/ + + a_uint8_t ControlBytes[4]; + + /* message payload starts after the header */ + +} POSTPACK HTC_FRAME_HDR; + +/* frame header flags */ +#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0) +#define HTC_FLAGS_RECV_TRAILER (1 << 1) +#define HTC_FLAGS_CREDIT_REDISTRIBUTION (1 << 2) + +#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR)) +#define HTC_MAX_TRAILER_LENGTH 255 +#define HTC_MAX_PAYLOAD_LENGTH (2048 - sizeof(HTC_FRAME_HDR)) + +/* HTC control message IDs */ +typedef enum { + HTC_MSG_READY_ID = 1, + HTC_MSG_CONNECT_SERVICE_ID = 2, + HTC_MSG_CONNECT_SERVICE_RESPONSE_ID = 3, + HTC_MSG_SETUP_COMPLETE_ID = 4, + HTC_MSG_CONFIG_PIPE_ID = 5, + HTC_MSG_CONFIG_PIPE_RESPONSE_ID = 6, +} HTC_MSG_IDS; + +#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256 + +/* base message ID header */ +typedef PREPACK struct { + a_uint16_t MessageID; +} POSTPACK HTC_UNKNOWN_MSG; + +/* HTC ready message + * direction : target-to-host */ +typedef PREPACK struct { + a_uint16_t MessageID; /* ID */ + a_uint16_t CreditCount; /* number of credits the target can offer */ + a_uint16_t CreditSize; /* size of each credit */ + a_uint8_t MaxEndpoints; /* maximum number of endpoints the target has resources for */ + a_uint8_t _Pad1; +} POSTPACK HTC_READY_MSG; + +#define HTC_SERVICE_META_DATA_MAX_LENGTH 128 + +/* connect service + * direction : host-to-target */ +typedef PREPACK struct { + a_uint16_t MessageID; + a_uint16_t ServiceID; /* service ID of the service to connect to */ + a_uint16_t ConnectionFlags; /* connection flags */ + a_uint8_t DownLinkPipeID; + a_uint8_t UpLinkPipeID; + +#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when + the host needs credits */ +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3) +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2 +#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3 + + a_uint8_t ServiceMetaLength; /* length of meta data that follows */ + a_uint8_t _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_MSG; + +/* connect response + * direction : target-to-host */ +typedef PREPACK struct { + a_uint16_t MessageID; + a_uint16_t ServiceID; /* service ID that the connection request was made */ + a_uint8_t Status; /* service connection status */ + a_uint8_t EndpointID; /* assigned endpoint ID */ + a_uint16_t MaxMsgSize; /* maximum expected message size on this endpoint */ + a_uint8_t ServiceMetaLength; /* length of meta data that follows */ + a_uint8_t _Pad1; + + /* service-specific meta data starts after the header */ + +} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG; + +typedef PREPACK struct { + a_uint16_t MessageID; + /* currently, no other fields */ +} POSTPACK HTC_SETUP_COMPLETE_MSG; + +/* config pipe + * direction : host-to-target */ +typedef PREPACK struct { + a_uint16_t MessageID; + a_uint8_t PipeID; /* Pipe ID of the service to connect to */ + a_uint8_t CreditCount; /* CreditCount */ + //a_uint8_t _Pad1; +} POSTPACK HTC_CONFIG_PIPE_MSG; + +/* config pipe + * direction : host-to-target */ +typedef PREPACK struct { + a_uint16_t MessageID; + a_uint8_t PipeID; /* Pipe ID of the service to connect to */ + a_uint8_t Status; /* status */ + //a_uint8_t _Pad1; +} POSTPACK HTC_CONFIG_PIPE_RESPONSE_MSG; + +/* connect response status codes */ +#define HTC_SERVICE_SUCCESS 0 /* success */ +#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */ +#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */ +#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */ +#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more + endpoints */ + +/* shihhung: config pipe response status code */ +#define HTC_CONFIGPIPE_SUCCESS 0 +#define HTC_CONFIGPIPE_NOSUCHPIPE 1 +#define HTC_CONFIGPIPE_NORESOURCE 2 + +/* report record IDs */ +typedef enum { + HTC_RECORD_NULL = 0, + HTC_RECORD_CREDITS = 1, + HTC_RECORD_LOOKAHEAD = 2, +} HTC_RPT_IDS; + +typedef PREPACK struct { + a_uint8_t RecordID; /* Record ID */ + a_uint8_t Length; /* Length of record */ +} POSTPACK HTC_RECORD_HDR; + +typedef PREPACK struct { + a_uint8_t EndpointID; /* Endpoint that owns these credits */ + a_uint8_t Credits; /* credits to report since last report */ +} POSTPACK HTC_CREDIT_REPORT; + +typedef PREPACK struct { + a_uint8_t PreValid; /* pre valid guard */ + a_uint8_t LookAhead[4]; /* 4 byte lookahead */ + a_uint8_t PostValid; /* post valid guard */ + + /* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes. + * The PreValid bytes must equal the inverse of the PostValid byte */ + +} POSTPACK HTC_LOOKAHEAD_REPORT; + +#ifndef ATH_TARGET +//#include "athendpack.h" +#endif + +#endif /* __HTC_H__ */ diff --git a/target_firmware/wlan/include/htc_services.h b/target_firmware/wlan/include/htc_services.h new file mode 100755 index 0000000..a21a7dc --- /dev/null +++ b/target_firmware/wlan/include/htc_services.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2007 Atheros Communications Inc. + * All rights reserved. + */ + +#ifndef __HTC_SERVICES_H__ +#define __HTC_SERVICES_H__ + +/* Current service IDs */ + +typedef enum { + RSVD_SERVICE_GROUP = 0, + WMI_SERVICE_GROUP = 1, + + HTC_TEST_GROUP = 254, + HTC_SERVICE_GROUP_LAST = 255 +} HTC_SERVICE_GROUP_IDS; + +#define MAKE_SERVICE_ID(group,index) \ + (int)(((int)group << 8) | (int)(index)) + +/* NOTE: service ID of 0x0000 is reserved and should never be used */ +#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1) +#define HTC_LOOPBACK_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,2) +#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0) + +#define WMI_BEACON_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1) +#define WMI_CAB_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2) + +#define WMI_UAPSD_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3) +#define WMI_MGMT_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4) + +#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,5) +#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,6) + +#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,7) +#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,8) + +/* raw stream service (i.e. flash, tcmd, calibration apps) */ +#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0) + +#endif /*HTC_SERVICES_H_*/ diff --git a/target_firmware/wlan/include/k2/wlan_cfg.h b/target_firmware/wlan/include/k2/wlan_cfg.h new file mode 100755 index 0000000..2f90417 --- /dev/null +++ b/target_firmware/wlan/include/k2/wlan_cfg.h @@ -0,0 +1,56 @@ +#ifndef _WLAN_CFG_H_ +#define _WLAN_CFG_H_ + +/************************** ATH configurations **************************/ +#ifdef _DEBUG_BUILD_ +#ifdef RX_SCATTER +#define ATH_RXDESC 30 /* number of RX descriptors */ +#endif + +#ifdef RX_SCATTER +#define ATH_RXBUF ATH_RXDESC /* number of RX buffers */ +#else +#define ATH_RXBUF 15 /* number of RX buffers */ +#endif +#define ATH_TXBUF 26 /* number of TX buffers */ + +#else + +#ifdef RX_SCATTER +#define ATH_RXDESC 11 /* number of RX descriptors */ +#endif // end of _DEBUG_BUILD + +#ifdef RX_SCATTER +#define ATH_RXBUF ATH_RXDESC /* number of RX buffers */ +#else +#define ATH_RXBUF 15 /* number of RX buffers */ +#endif +#define ATH_TXBUF 30 /* number of TX buffers */ +#endif + +#ifdef FUSION_USB_FW +#undef ATH_RXBUF +#undef ATH_TXBUF + +#define ATH_RXBUF 11 +#define ATH_TXBUF 33 +#endif + +#define ATH_BCBUF 1 /* number of beacon buffers */ +#define ATH_WMI_MAX_CMD_REPLY 2 +#define ATH_WMI_MAX_EVENTS 8 + +//#define ATH_DISABLE_RC /* Use fixed rate instead of rate control */ +#define ATH_BUF_OPTIMIZATION +#define ATH_NO_VIRTUAL_MEMORY +#define ATH_SUPPORT_XB_ONLY +#define ATH_ENABLE_WLAN_FOR_K2 + +#define ATH_VERSION_MAJOR 1 +#define ATH_VERSION_MINOR 3 + +/************************** HAL configurations **************************/ + +#define HAL_DESC_OPTIMIZATION + +#endif /* _WLAN_CFG_H_ */ diff --git a/target_firmware/wlan/include/magpie/wlan_cfg.h b/target_firmware/wlan/include/magpie/wlan_cfg.h new file mode 100755 index 0000000..415e29f --- /dev/null +++ b/target_firmware/wlan/include/magpie/wlan_cfg.h @@ -0,0 +1,41 @@ +#ifndef _WLAN_CFG_H_ +#define _WLAN_CFG_H_ + +/************************** ATH configurations **************************/ +#ifdef RX_SCATTER +#define ATH_RXDESC 40 /* number of RX descriptors */ +#endif + +#ifdef RX_SCATTER +#define ATH_RXBUF 40 /* number of RX buffers */ +#else +#define ATH_RXBUF 20 /* number of RX buffers */ +#endif +#define ATH_TXBUF 45 /* number of TX buffers */ +#define ATH_BCBUF 1 /* number of beacon buffers */ +#define ATH_WMI_MAX_CMD_REPLY 2 +#define ATH_WMI_MAX_EVENTS 8 + +#ifdef FUSION_USB_FW +#undef ATH_RXBUF +#undef ATH_RXDESC + +#define ATH_RXDESC 20 +#define ATH_RXBUF 20 +#endif +//#define ATH_DISABLE_RC /* Use fixed rate instead of rate control */ + +#define ATH_BUF_OPTIMIZATION +#define ATH_NO_VIRTUAL_MEMORY + +//#define ATH_SUPPORT_XB_ONLY +#define ATH_SUPPORT_A_MODE + +#define ATH_VERSION_MAJOR 1 +#define ATH_VERSION_MINOR 3 + +/************************** HAL configurations **************************/ + +#define HAL_DESC_OPTIMIZATION + +#endif /* _WLAN_CFG_H_ */ diff --git a/target_firmware/wlan/include/wlan_hdr.h b/target_firmware/wlan/include/wlan_hdr.h new file mode 100755 index 0000000..1fd1272 --- /dev/null +++ b/target_firmware/wlan/include/wlan_hdr.h @@ -0,0 +1,202 @@ +#ifndef _WLAN_HDR_H +#define _WLAN_HDR_H + +/* Please make sure the size of ALL headers is on word alignment */ + +#define M_FF 0x02 /* fast frame */ + +#define RX_STATS_SIZE 10 + +struct rx_frame_header { + a_uint32_t rx_stats[RX_STATS_SIZE]; +}; + +#define ATH_DATA_TYPE_AGGR 0x1 +#define ATH_DATA_TYPE_NON_AGGR 0x2 +#define ATH_SHORT_PREAMBLE 0x1 + +typedef struct _mgt_header { + a_uint8_t ni_index; + a_uint8_t vap_index; + a_uint8_t tidno; + a_uint8_t flags; + a_int8_t keytype; + a_int8_t keyix; + a_uint8_t cookie; + a_uint8_t pad; +} POSTPACK ath_mgt_hdr_t; + +typedef struct _beacon_header { + a_uint8_t vap_index; + a_uint8_t len_changed; + a_uint16_t reserved; +} ath_beacon_hdr_t; + +#define M_LINK0 0x01 /* frame needs WEP encryption */ +#define M_UAPSD 0x08 /* frame flagged for u-apsd handling */ + +/* Tx frame header flags definition */ +//Reserved bit-0 for selfCTS +//Reserved bit-1 for RTS +#define TFH_FLAGS_USE_MIN_RATE 0x100 + +typedef struct __data_header { + a_uint8_t datatype; + a_uint8_t ni_index; + a_uint8_t vap_index; + a_uint8_t tidno; + a_uint32_t flags; + a_int8_t keytype; + a_int8_t keyix; + a_uint8_t cookie; + a_uint8_t pad; +} POSTPACK ath_data_hdr_t; + +#define RX_HEADER_SPACE HTC_HDR_LENGTH + sizeof(struct rx_frame_header) + +struct ieee80211com_target { + a_uint32_t ic_ampdu_limit; + a_uint8_t ic_ampdu_subframes; + a_uint8_t ic_enable_coex; + a_uint8_t ic_tx_chainmask; + a_uint8_t pad; +}; + +#define ATH_NODE_MAX 8 /* max no. of nodes */ +#define ATH_VAP_MAX 2 /* max no. of vaps */ + +#define VAP_TARGET_SIZE 12 + +struct ieee80211vap_target +{ + a_uint8_t iv_vapindex; + a_uint8_t iv_opmode; /* enum ieee80211_opmode */ + a_uint8_t iv_myaddr[IEEE80211_ADDR_LEN]; + a_uint8_t iv_ath_cap; + a_uint16_t iv_rtsthreshold; + a_uint8_t pad; + + /* Internal */ + a_uint8_t iv_nodeindex; + struct ieee80211_node_target *iv_bss; +}; + +/* NB: this must have the same value as IEEE80211_FC1_PWR_MGT */ +#define IEEE80211_NODE_PWR_MGT 0x0010 /* power save mode enabled */ +#define IEEE80211_NODE_AREF 0x0020 /* authentication ref held */ +#define IEEE80211_NODE_UAPSD 0x0040 /* U-APSD power save enabled */ +#define IEEE80211_NODE_UAPSD_TRIG 0x0080 /* U-APSD triggerable state */ +#define IEEE80211_NODE_UAPSD_SP 0x0100 /* U-APSD SP in progress */ +#define IEEE80211_NODE_ATH 0x0200 /* Atheros Owl or follow-on device */ +#define IEEE80211_NODE_OWL_WORKAROUND 0x0400 /* Owl WDS workaround needed*/ +#define IEEE80211_NODE_WDS 0x0800 /* WDS link */ + +#define NODE_TARGET_SIZE 22 + +struct ieee80211_node_target +{ + a_uint8_t ni_macaddr[IEEE80211_ADDR_LEN]; + a_uint8_t ni_bssid[IEEE80211_ADDR_LEN]; + a_uint8_t ni_nodeindex; + a_uint8_t ni_vapindex; + a_uint8_t ni_is_vapnode; + a_uint16_t ni_flags; + a_uint16_t ni_htcap; + a_uint16_t ni_maxampdu; + a_uint8_t pad; + + /* + * Internal. + * Should move to ath_node_target later on ... + */ + a_uint16_t ni_txseqmgmt; + a_uint16_t ni_iv16; + a_uint32_t ni_iv32; + struct ieee80211vap_target *ni_vap; +}; + +struct ath_interrupt_stats { + a_uint32_t ast_rx; + a_uint32_t ast_rxorn; + a_uint32_t ast_rxeol; + a_uint32_t ast_txurn; + a_uint32_t ast_txto; + a_uint32_t ast_cst; +}; + +struct ath_tx_stats { + a_uint32_t ast_tx_xretries; /* tx failed 'cuz too many retries */ + a_uint32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ + a_uint32_t ast_tx_filtered; /* tx failed 'cuz xmit filtered */ + a_uint32_t ast_tx_timer_exp; /* tx timer expired */ + a_uint32_t ast_tx_shortretry; /* tx on-chip retries (short) */ + a_uint32_t ast_tx_longretry; /* tx on-chip retries (long) */ + + a_uint32_t ast_tx_rts; /* tx frames with rts enabled */ + a_uint32_t ast_tx_altrate; /* tx frames with alternate rate */ + a_uint32_t ast_tx_protect; /* tx frames with protection */ + + a_uint32_t tx_tgt; /* tx data pkts recieved on target */ + a_uint32_t tx_qnull; /* txq empty occurences */ + + a_uint32_t txaggr_nframes; /* no. of frames aggregated */ + a_uint32_t tx_compunaggr; /* tx unaggregated frame completions */ + a_uint32_t tx_compaggr; /* tx aggregated completions */ + a_uint32_t txaggr_retries; /* tx retries of sub frames */ + a_uint32_t txaggr_single; /* tx frames not aggregated */ + a_uint32_t txaggr_compgood; /* tx aggr good completions */ + a_uint32_t txaggr_compretries; /* tx aggr unacked subframes */ + a_uint32_t txaggr_prepends; /* tx aggr old frames requeued */ + a_uint32_t txaggr_data_urun; /* data underrun for an aggregate */ + a_uint32_t txaggr_delim_urun; /* delimiter underrun for an aggr */ + a_uint32_t txaggr_errlast; /* tx aggr: last sub-frame failed */ + a_uint32_t txaggr_longretries; /* tx aggr h/w long retries */ + a_uint32_t txaggr_babug; /* tx aggr : BA bug */ + a_uint32_t txaggr_compxretry; /* tx aggr excessive retries */ + a_uint32_t txaggr_shortretries;/* tx aggr h/w short retries */ + a_uint32_t txaggr_timer_exp; /* tx aggr : tx timer expired */ + a_uint32_t txunaggr_compretries; /* tx non-aggr unacked subframes */ + a_uint32_t txaggr_filtered; /* filtered aggr packet */ + a_uint32_t txaggr_fifo; /* fifo underrun of aggregate */ + a_uint32_t txaggr_xtxop; /* txop exceeded for an aggregate */ + a_uint32_t txaggr_desc_cfgerr; /* aggr descriptor config error */ + a_uint32_t txunaggr_errlast; /* tx non-aggr: last frame failed */ + a_uint32_t txunaggr_xretry; /* tx unaggregated excessive retries */ + a_uint32_t txaggr_xretries; /* tx excessive retries of aggr */ + + a_uint32_t tx_stopfiltered; /* tx pkts filtered for requeueing */ + a_uint32_t tx_noskbs; /* tx no skbs for encapsulations */ + a_uint32_t tx_nobufs; /* tx no descriptors */ + + a_uint32_t tx_bars; /* tx bars sent */ + a_uint32_t txbar_xretry; /* tx bars excessively retried */ + a_uint32_t txbar_compretries; /* tx bars retried */ + a_uint32_t txbar_errlast; /* tx bars last frame failed */ +}; + +struct ath_rx_stats { + a_uint32_t ast_rx_nobuf; /* rx setup failed 'cuz no skbuff */ + a_uint32_t ast_rx_send; + a_uint32_t ast_rx_done; +}; + +struct ath_aggr_info { + a_uint8_t nodeindex; + a_uint8_t tidno; + a_uint8_t aggr_enable; + a_uint8_t padding; +}; + +struct wmi_data_delba { + a_uint8_t ni_nodeindex; + a_uint8_t tidno; + a_uint8_t initiator; + a_uint8_t reasoncode; +}; + +struct wmi_fw_version { + a_uint16_t major; + a_uint16_t minor; +}; + +#endif diff --git a/target_firmware/wlan/include/wmi.h b/target_firmware/wlan/include/wmi.h new file mode 100755 index 0000000..bf68eda --- /dev/null +++ b/target_firmware/wlan/include/wmi.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2004-2006 Atheros Communications Inc. + * All rights reserved. + * + * This file contains the definitions of the WMI protocol specified in the + * Wireless Module Interface (WMI). It includes definitions of all the + * commands and events. Commands are messages from the host to the WM. + * Events and Replies are messages from the WM to the host. + * + * Ownership of correctness in regards to WMI commands + * belongs to the host driver and the WM is not required to validate + * parameters for value, proper range, or any other checking. + * + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/include/wmi.h#6 $ + * + */ + +#ifndef _WMI_H_ +#define _WMI_H_ + +#include "athdefs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define HTC_PROTOCOL_VERSION 0x0002 +#define HTC_PROTOCOL_REVISION 0x0000 + +#define WMI_PROTOCOL_VERSION 0x0002 +#define WMI_PROTOCOL_REVISION 0x0000 + +#define ATH_MAC_LEN 6 /* length of mac in bytes */ +#define WMI_CMD_MAX_LEN 100 +#define WMI_CONTROL_MSG_MAX_LEN 256 +#define WMI_OPT_CONTROL_MSG_MAX_LEN 1536 +#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600) +#define RFC1042OUI {0x00, 0x00, 0x00} + +#define IP_ETHERTYPE 0x0800 + +#define WMI_IMPLICIT_PSTREAM 0xFF +#define WMI_MAX_THINSTREAM 15 + +struct host_app_area_s { + a_uint32_t wmi_protocol_ver; +}; + +/* + * Data Path + */ +typedef PREPACK struct { + a_uint8_t dstMac[ATH_MAC_LEN]; + a_uint8_t srcMac[ATH_MAC_LEN]; + a_uint16_t typeOrLen; +} POSTPACK ATH_MAC_HDR; + +typedef PREPACK struct { + a_uint8_t dsap; + a_uint8_t ssap; + a_uint8_t cntl; + a_uint8_t orgCode[3]; + a_uint16_t etherType; +} POSTPACK ATH_LLC_SNAP_HDR; + +typedef enum { + DATA_MSGTYPE = 0x0, + CNTL_MSGTYPE, + SYNC_MSGTYPE, + OPT_MSGTYPE, +} WMI_MSG_TYPE; + + +typedef PREPACK struct { + a_int8_t rssi; + a_uint8_t info; /* WMI_MSG_TYPE in lower 2 bits - b1b0 */ + /* UP in next 3 bits - b4b3b2 */ +#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03 +#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0 +#define WMI_DATA_HDR_UP_MASK 0x07 +#define WMI_DATA_HDR_UP_SHIFT 2 +#define WMI_DATA_HDR_IS_MSG_TYPE(h, t) (((h)->info & (WMI_DATA_HDR_MSG_TYPE_MASK)) == (t)) +} POSTPACK WMI_DATA_HDR; + + +#define WMI_DATA_HDR_SET_MSG_TYPE(h, t) (h)->info = (((h)->info & ~(WMI_DATA_HDR_MSG_TYPE_MASK << WMI_DATA_HDR_MSG_TYPE_SHIFT)) | (t << WMI_DATA_HDR_MSG_TYPE_SHIFT)) +#define WMI_DATA_HDR_SET_UP(h, p) (h)->info = (((h)->info & ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT)) | (p << WMI_DATA_HDR_UP_SHIFT)) + +/* + * Control Path + */ +typedef PREPACK struct { + a_uint16_t commandId; + a_uint16_t seqNo; +} POSTPACK WMI_CMD_HDR; /* used for commands and events */ + +/* + * List of Commnands + */ +typedef enum { + WMI_ECHO_CMDID = 0x0001, + WMI_ACCESS_MEMORY_CMDID, + + /* Commands to Target */ + WMI_GET_FW_VERSION, + WMI_DISABLE_INTR_CMDID, + WMI_ENABLE_INTR_CMDID, + WMI_ATH_INIT_CMDID, + WMI_ABORT_TXQ_CMDID, + WMI_STOP_TX_DMA_CMDID, + WMI_ABORT_TX_DMA_CMDID, + WMI_DRAIN_TXQ_CMDID, + WMI_DRAIN_TXQ_ALL_CMDID, + WMI_START_RECV_CMDID, + WMI_STOP_RECV_CMDID, + WMI_FLUSH_RECV_CMDID, + WMI_SET_MODE_CMDID, + WMI_NODE_CREATE_CMDID, + WMI_NODE_REMOVE_CMDID, + WMI_VAP_REMOVE_CMDID, + WMI_VAP_CREATE_CMDID, + WMI_REG_READ_CMDID, + WMI_REG_WRITE_CMDID, + WMI_RC_STATE_CHANGE_CMDID, + WMI_RC_RATE_UPDATE_CMDID, + WMI_TARGET_IC_UPDATE_CMDID, + WMI_TX_AGGR_ENABLE_CMDID, + WMI_TGT_DETACH_CMDID, + WMI_NODE_UPDATE_CMDID, + WMI_INT_STATS_CMDID, + WMI_TX_STATS_CMDID, + WMI_RX_STATS_CMDID, + WMI_BITRATE_MASK_CMDID, +} WMI_COMMAND_ID; + +/* + * Frame Types + */ +typedef enum { + WMI_FRAME_BEACON = 0, + WMI_FRAME_PROBE_REQ, + WMI_FRAME_PROBE_RESP, + WMI_FRAME_ASSOC_REQ, + WMI_FRAME_ASSOC_RESP, + WMI_NUM_MGMT_FRAME +} WMI_MGMT_FRAME_TYPE; + +/* + * Connect Command + */ +typedef enum { + INFRA_NETWORK = 0x01, + ADHOC_NETWORK = 0x02, + ADHOC_CREATOR = 0x04, + OPT_NETWORK = 0x08, +} NETWORK_TYPE; + +typedef enum { + OPEN_AUTH = 0x01, + SHARED_AUTH = 0x02, + LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */ +} DOT11_AUTH_MODE; + +typedef enum { + NONE_AUTH = 0x01, + WPA_AUTH = 0x02, + WPA_PSK_AUTH = 0x03, + WPA2_AUTH = 0x04, + WPA2_PSK_AUTH = 0x05, + WPA_AUTH_CCKM = 0x06, + WPA2_AUTH_CCKM = 0x07, +} AUTH_MODE; + +typedef enum { + NONE_CRYPT = 0x01, + WEP_CRYPT = 0x02, + TKIP_CRYPT = 0x03, + AES_CRYPT = 0x04, +} CRYPTO_TYPE; + +#define WMI_MIN_CRYPTO_TYPE NONE_CRYPT +#define WMI_MAX_CRYPTO_TYPE (AES_CRYPT + 1) + +#define WMI_MIN_KEY_INDEX 0 +#define WMI_MAX_KEY_INDEX 3 + +#define WMI_MAX_KEY_LEN 32 + +#define WMI_MAX_SSID_LEN 32 + +typedef enum { + CONNECT_ASSOC_POLICY_USER = 0x0001, + CONNECT_SEND_REASSOC = 0x0002, + CONNECT_IGNORE_WPAx_GROUP_CIPHER = 0x0004, + CONNECT_PROFILE_MATCH_DONE = 0x0008, + CONNECT_IGNORE_AAC_BEACON = 0x0010, + CONNECT_CSA_FOLLOW_BSS = 0x0020, +} WMI_CONNECT_CTRL_FLAGS_BITS; + +#define DEFAULT_CONNECT_CTRL_FLAGS (CONNECT_CSA_FOLLOW_BSS) + +/* + * WMI_ECHO_CMDID + */ +#define WMI_ECHOCMD_MSG_MAX_LEN 53//64 - HTC_HDR_LENGTH + sizeof(WMI_CMD_HDR) - 1 + +typedef PREPACK struct { + a_uint8_t msgSize; + a_uint8_t msgData[1]; +} POSTPACK WMI_ECHO_CMD; + +/* + * WMI_ACCESS_MEMORY_CMDID + */ +#define WMI_ACCESS_MEMORY_MAX_TUPLES 8 + +typedef PREPACK struct { + a_uint16_t addressL; + a_uint16_t addressH; + a_uint16_t valueL; + a_uint16_t valueH; +} POSTPACK WMI_AVT; + +typedef PREPACK struct { + a_uint16_t tupleNumL; + a_uint16_t tupleNumH; + WMI_AVT avt[1]; +} POSTPACK WMI_ACCESS_MEMORY_CMD; + +/* + * List of Events (target to host) + */ +typedef enum { + WMI_TGT_RDY_EVENTID = 0x1001, + WMI_SWBA_EVENTID, + WMI_FATAL_EVENTID, + WMI_TXTO_EVENTID, + WMI_BMISS_EVENTID, + WMI_DELBA_EVENTID, + WMI_TXSTATUS_EVENTID +} WMI_EVENT_ID; + +typedef PREPACK struct { + a_uint64_t tsf; + a_uint8_t beaconPendingCount; +} POSTPACK WMI_SWBA_EVENT; + +typedef PREPACK struct { + a_uint8_t cookie; + a_uint8_t ts_rate; + a_uint8_t ts_flags; +} POSTPACK __WMI_TXSTATUS_EVENT; + +#define HTC_MAX_TX_STATUS 12 + +typedef PREPACK struct { + a_uint8_t cnt; + __WMI_TXSTATUS_EVENT txstatus[HTC_MAX_TX_STATUS]; +} POSTPACK WMI_TXSTATUS_EVENT; + +#ifndef ATH_TARGET +//#include "athendpack.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _WMI_H_ */ diff --git a/target_firmware/wlan/queue.h b/target_firmware/wlan/queue.h new file mode 100755 index 0000000..34bf4b7 --- /dev/null +++ b/target_firmware/wlan/queue.h @@ -0,0 +1,567 @@ +/* + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)queue.h 8.5 (Berkeley) 8/20/94 + * $FreeBSD: src/sys/sys/queue.h,v 1.58 2004/04/07 04:19:49 imp Exp $ + * $Id: //depot/sw/branches/fusion_usb/target_firmware/wlan/target/madwifi/include/sys/queue.h#1 $ + */ + +#ifndef _SYS_QUEUE_H_ +#define _SYS_QUEUE_H_ + +/* + * This file defines four types of data structures: singly-linked lists, + * singly-linked tail queues, lists and tail queues. + * + * A singly-linked list is headed by a single forward pointer. The elements + * are singly linked for minimum space and pointer manipulation overhead at + * the expense of O(n) removal for arbitrary elements. New elements can be + * added to the list after an existing element or at the head of the list. + * Elements being removed from the head of the list should use the explicit + * macro for this purpose for optimum efficiency. A singly-linked list may + * only be traversed in the forward direction. Singly-linked lists are ideal + * for applications with large datasets and few or no removals or for + * implementing a LIFO queue. + * + * A singly-linked tail queue is headed by a pair of pointers, one to the + * head of the list and the other to the tail of the list. The elements are + * singly linked for minimum space and pointer manipulation overhead at the + * expense of O(n) removal for arbitrary elements. New elements can be added + * to the list after an existing element, at the head of the list, or at the + * end of the list. Elements being removed from the head of the tail queue + * should use the explicit macro for this purpose for optimum efficiency. + * A singly-linked tail queue may only be traversed in the forward direction. + * Singly-linked tail queues are ideal for applications with large datasets + * and few or no removals or for implementing a FIFO queue. + * + * A list is headed by a single forward pointer (or an array of forward + * pointers for a hash table header). The elements are doubly linked + * so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before + * or after an existing element or at the head of the list. A list + * may only be traversed in the forward direction. + * + * A tail queue is headed by a pair of pointers, one to the head of the + * list and the other to the tail of the list. The elements are doubly + * linked so that an arbitrary element can be removed without a need to + * traverse the list. New elements can be added to the list before or + * after an existing element, at the head of the list, or at the end of + * the list. A tail queue may be traversed in either direction. + * + * For details on the use of these macros, see the queue(3) manual page. + * + * + * SLIST LIST STAILQ TAILQ + * _HEAD + + + + + * _HEAD_INITIALIZER + + + + + * _ENTRY + + + + + * _INIT + + + + + * _EMPTY + + + + + * _FIRST + + + + + * _NEXT + + + + + * _PREV - - - + + * _LAST - - + + + * _FOREACH + + + + + * _FOREACH_SAFE + + + + + * _FOREACH_REVERSE - - - + + * _FOREACH_REVERSE_SAFE - - - + + * _INSERT_HEAD + + + + + * _INSERT_BEFORE - + - + + * _INSERT_AFTER + + + + + * _INSERT_TAIL - - + + + * _CONCAT - - + + + * _REMOVE_HEAD + - + - + * _REMOVE + + + + + * + */ +#define QUEUE_MACRO_DEBUG 0 +#if QUEUE_MACRO_DEBUG +/* Store the last 2 places the queue element or head was altered */ +struct qm_trace { + char * lastfile; + a_int32_t lastline; + char * prevfile; + a_int32_t prevline; +}; + +#define TRACEBUF struct qm_trace trace; +#define TRASHIT(x) do {(x) = (void *)-1;} while (0) + +#define QMD_TRACE_HEAD(head) do { \ + (head)->trace.prevline = (head)->trace.lastline; \ + (head)->trace.prevfile = (head)->trace.lastfile; \ + (head)->trace.lastline = __LINE__; \ + (head)->trace.lastfile = __FILE__; \ +} while (0) + +#define QMD_TRACE_ELEM(elem) do { \ + (elem)->trace.prevline = (elem)->trace.lastline; \ + (elem)->trace.prevfile = (elem)->trace.lastfile; \ + (elem)->trace.lastline = __LINE__; \ + (elem)->trace.lastfile = __FILE__; \ +} while (0) + +#else +#define QMD_TRACE_ELEM(elem) +#define QMD_TRACE_HEAD(head) +#define TRACEBUF +#define TRASHIT(x) +#endif /* QUEUE_MACRO_DEBUG */ + +/* + * Singly-linked List declarations. + */ +#define SLIST_HEAD(name, type) \ +struct name { \ + struct type *slh_first; /* first element */ \ +} + +#define SLIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define SLIST_ENTRY(type) \ +struct { \ + struct type *sle_next; /* next element */ \ +} + +/* + * Singly-linked List functions. + */ +#define SLIST_EMPTY(head) ((head)->slh_first == NULL) + +#define SLIST_FIRST(head) ((head)->slh_first) + +#define SLIST_FOREACH(var, head, field) \ + for ((var) = SLIST_FIRST((head)); \ + (var); \ + (var) = SLIST_NEXT((var), field)) + +#define SLIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = SLIST_FIRST((head)); \ + (var) && ((tvar) = SLIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define SLIST_FOREACH_PREVPTR(var, varp, head, field) \ + for ((varp) = &SLIST_FIRST((head)); \ + ((var) = *(varp)) != NULL; \ + (varp) = &SLIST_NEXT((var), field)) + +#define SLIST_INIT(head) do { \ + SLIST_FIRST((head)) = NULL; \ +} while (0) + +#define SLIST_INSERT_AFTER(slistelm, elm, field) do { \ + SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field); \ + SLIST_NEXT((slistelm), field) = (elm); \ +} while (0) + +#define SLIST_INSERT_HEAD(head, elm, field) do { \ + SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \ + SLIST_FIRST((head)) = (elm); \ +} while (0) + +#define SLIST_NEXT(elm, field) ((elm)->field.sle_next) + +#define SLIST_REMOVE(head, elm, type, field) do { \ + if (SLIST_FIRST((head)) == (elm)) { \ + SLIST_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = SLIST_FIRST((head)); \ + while (SLIST_NEXT(curelm, field) != (elm)) \ + curelm = SLIST_NEXT(curelm, field); \ + SLIST_NEXT(curelm, field) = \ + SLIST_NEXT(SLIST_NEXT(curelm, field), field); \ + } \ +} while (0) + +#define SLIST_REMOVE_HEAD(head, field) do { \ + SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field); \ +} while (0) + +/* + * Singly-linked Tail queue declarations. + */ +#define STAILQ_HEAD(name, type) \ +struct name { \ + struct type *stqh_first;/* first element */ \ + struct type **stqh_last;/* addr of last next element */ \ +} + +#define STAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).stqh_first } + +#define STAILQ_ENTRY(type) \ +struct { \ + struct type *stqe_next; /* next element */ \ +} + +/* + * Singly-linked Tail queue functions. + */ +#define STAILQ_CONCAT(head1, head2) do { \ + if (!STAILQ_EMPTY((head2))) { \ + *(head1)->stqh_last = (head2)->stqh_first; \ + (head1)->stqh_last = (head2)->stqh_last; \ + STAILQ_INIT((head2)); \ + } \ +} while (0) + +#define STAILQ_EMPTY(head) ((head)->stqh_first == NULL) + +#define STAILQ_FIRST(head) ((head)->stqh_first) + +#define STAILQ_FOREACH(var, head, field) \ + for((var) = STAILQ_FIRST((head)); \ + (var); \ + (var) = STAILQ_NEXT((var), field)) + + +#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = STAILQ_FIRST((head)); \ + (var) && ((tvar) = STAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define STAILQ_INIT(head) do { \ + STAILQ_FIRST((head)) = NULL; \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do { \ + if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ + STAILQ_NEXT((tqelm), field) = (elm); \ +} while (0) + +#define STAILQ_INSERT_HEAD(head, elm, field) do { \ + if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ + STAILQ_FIRST((head)) = (elm); \ +} while (0) + +#define STAILQ_INSERT_TAIL(head, elm, field) do { \ + STAILQ_NEXT((elm), field) = NULL; \ + *(head)->stqh_last = (elm); \ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ +} while (0) + +#define STAILQ_LAST(head, type, field) \ + (STAILQ_EMPTY((head)) ? \ + NULL : \ + ((struct type *) \ + ((char *)((head)->stqh_last) - asf_offsetof(struct type, field)))) + +#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next) + +#define STAILQ_REMOVE(head, elm, type, field) do { \ + if (STAILQ_FIRST((head)) == (elm)) { \ + STAILQ_REMOVE_HEAD((head), field); \ + } \ + else { \ + struct type *curelm = STAILQ_FIRST((head)); \ + while (STAILQ_NEXT(curelm, field) != (elm)) \ + curelm = STAILQ_NEXT(curelm, field); \ + if ((STAILQ_NEXT(curelm, field) = \ + STAILQ_NEXT(STAILQ_NEXT(curelm, field), field)) == NULL)\ + (head)->stqh_last = &STAILQ_NEXT((curelm), field);\ + } \ +} while (0) + + +#define STAILQ_REMOVE_AFTER(head, elm, field) do { \ + if (STAILQ_NEXT(elm, field)) { \ + if ((STAILQ_NEXT(elm, field) = \ + STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL)\ + (head)->stqh_last = &STAILQ_NEXT((elm), field); \ + } \ +} while (0) + + +#define STAILQ_REMOVE_HEAD(head, field) do { \ + if ((STAILQ_FIRST((head)) = \ + STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL) \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +#define STAILQ_REMOVE_HEAD_UNTIL(head, elm, field) do { \ + if ((STAILQ_FIRST((head)) = STAILQ_NEXT((elm), field)) == NULL) \ + (head)->stqh_last = &STAILQ_FIRST((head)); \ +} while (0) + +/* + * List declarations. + */ +#define LIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define ATH_LIST_HEAD(name, type) \ +struct name { \ + struct type *lh_first; /* first element */ \ +} + +#define LIST_HEAD_INITIALIZER(head) \ + { NULL } + +#define LIST_ENTRY(type) \ +struct { \ + struct type *le_next; /* next element */ \ + struct type **le_prev; /* address of previous next element */ \ +} + +/* + * List functions. + */ + +#define LIST_EMPTY(head) ((head)->lh_first == NULL) + +#define LIST_FIRST(head) ((head)->lh_first) + +#define LIST_FOREACH(var, head, field) \ + for ((var) = LIST_FIRST((head)); \ + (var); \ + (var) = LIST_NEXT((var), field)) + +#define LIST_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = LIST_FIRST((head)); \ + (var) && ((tvar) = LIST_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define LIST_INIT(head) do { \ + LIST_FIRST((head)) = NULL; \ +} while (0) + +#define LIST_INSERT_AFTER(listelm, elm, field) do { \ + if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\ + LIST_NEXT((listelm), field)->field.le_prev = \ + &LIST_NEXT((elm), field); \ + LIST_NEXT((listelm), field) = (elm); \ + (elm)->field.le_prev = &LIST_NEXT((listelm), field); \ +} while (0) + +#define LIST_INSERT_BEFORE(listelm, elm, field) do { \ + (elm)->field.le_prev = (listelm)->field.le_prev; \ + LIST_NEXT((elm), field) = (listelm); \ + *(listelm)->field.le_prev = (elm); \ + (listelm)->field.le_prev = &LIST_NEXT((elm), field); \ +} while (0) + +#define LIST_INSERT_HEAD(head, elm, field) do { \ + if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL) \ + LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\ + LIST_FIRST((head)) = (elm); \ + (elm)->field.le_prev = &LIST_FIRST((head)); \ +} while (0) + +#define LIST_NEXT(elm, field) ((elm)->field.le_next) + +#define LIST_REMOVE(elm, field) do { \ + if (LIST_NEXT((elm), field) != NULL) \ + LIST_NEXT((elm), field)->field.le_prev = \ + (elm)->field.le_prev; \ + *(elm)->field.le_prev = LIST_NEXT((elm), field); \ +} while (0) + +/* + * Tail queue declarations. + */ +#define TAILQ_HEAD(name, type) \ +struct name { \ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ + TRACEBUF \ +} + +#define TAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).tqh_first } + +#define TAILQ_ENTRY(type) \ +struct { \ + struct type *tqe_next; /* next element */ \ + struct type **tqe_prev; /* address of previous next element */ \ + TRACEBUF \ +} + +/* + * Tail queue functions. + */ +#define TAILQ_CONCAT(head1, head2, field) do { \ + if (!TAILQ_EMPTY(head2)) { \ + *(head1)->tqh_last = (head2)->tqh_first; \ + (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ + (head1)->tqh_last = (head2)->tqh_last; \ + TAILQ_INIT((head2)); \ + QMD_TRACE_HEAD(head); \ + QMD_TRACE_HEAD(head2); \ + } \ +} while (0) + +#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) + +#define TAILQ_FIRST(head) ((head)->tqh_first) + +#define TAILQ_FOREACH(var, head, field) \ + for ((var) = TAILQ_FIRST((head)); \ + (var); \ + (var) = TAILQ_NEXT((var), field)) + +#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \ + for ((var) = TAILQ_FIRST((head)); \ + (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \ + (var) = (tvar)) + +#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var); \ + (var) = TAILQ_PREV((var), headname, field)) + +#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \ + for ((var) = TAILQ_LAST((head), headname); \ + (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \ + (var) = (tvar)) + +#define TAILQ_INIT(head) do { \ + TAILQ_FIRST((head)) = NULL; \ + (head)->tqh_last = &TAILQ_FIRST((head)); \ + QMD_TRACE_HEAD(head); \ +} while (0) + +#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\ + TAILQ_NEXT((elm), field)->field.tqe_prev = \ + &TAILQ_NEXT((elm), field); \ + else { \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_HEAD(head); \ + } \ + TAILQ_NEXT((listelm), field) = (elm); \ + (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \ + QMD_TRACE_ELEM(&(elm)->field); \ + QMD_TRACE_ELEM(&listelm->field); \ +} while (0) + +#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + TAILQ_NEXT((elm), field) = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ + (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_ELEM(&(elm)->field); \ + QMD_TRACE_ELEM(&listelm->field); \ +} while (0) + +#define TAILQ_INSERT_HEAD(head, elm, field) do { \ + if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \ + TAILQ_FIRST((head))->field.tqe_prev = \ + &TAILQ_NEXT((elm), field); \ + else \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + TAILQ_FIRST((head)) = (elm); \ + (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \ + QMD_TRACE_HEAD(head); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + +#define TAILQ_INSERT_TAIL(head, elm, field) do { \ + TAILQ_NEXT((elm), field) = NULL; \ + (elm)->field.tqe_prev = (head)->tqh_last; \ + *(head)->tqh_last = (elm); \ + (head)->tqh_last = &TAILQ_NEXT((elm), field); \ + QMD_TRACE_HEAD(head); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + +#define TAILQ_LAST(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) + +#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) + +#define TAILQ_PREV(elm, headname, field) \ + (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) + +#define TAILQ_REMOVE(head, elm, field) do { \ + if ((TAILQ_NEXT((elm), field)) != NULL) \ + TAILQ_NEXT((elm), field)->field.tqe_prev = \ + (elm)->field.tqe_prev; \ + else { \ + (head)->tqh_last = (elm)->field.tqe_prev; \ + QMD_TRACE_HEAD(head); \ + } \ + *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \ + TRASHIT((elm)->field.tqe_next); \ + TRASHIT((elm)->field.tqe_prev); \ + QMD_TRACE_ELEM(&(elm)->field); \ +} while (0) + + +#ifdef _KERNEL + +/* + * XXX insque() and remque() are an old way of handling certain queues. + * They bogusly assumes that all queue heads look alike. + */ + +struct quehead { + struct quehead *qh_link; + struct quehead *qh_rlink; +}; + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) + +static __inline void +insque(void *a, void *b) +{ + struct quehead *element = (struct quehead *)a, + *head = (struct quehead *)b; + + element->qh_link = head->qh_link; + element->qh_rlink = head; + head->qh_link = element; + element->qh_link->qh_rlink = element; +} + +static __inline void +remque(void *a) +{ + struct quehead *element = (struct quehead *)a; + + element->qh_link->qh_rlink = element->qh_rlink; + element->qh_rlink->qh_link = element->qh_link; + element->qh_rlink = 0; +} + +#else /* !(__GNUC__ || __INTEL_COMPILER) */ + +void insque(void *a, void *b); +void remque(void *a); + +#endif /* __GNUC__ || __INTEL_COMPILER */ + +#endif /* _KERNEL */ + +#endif /* !_SYS_QUEUE_H_ */ diff --git a/target_firmware/wlan/ratectrl.h b/target_firmware/wlan/ratectrl.h new file mode 100755 index 0000000..87f9b1b --- /dev/null +++ b/target_firmware/wlan/ratectrl.h @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2000-2002 Atheros Communications, Inc., All Rights Reserved + * + * Definitions for core driver + * This is a common header file for all platforms and operating systems. + */ +#ifndef _RATECTRL_H_ +#define _RATECTRL_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "if_athrate.h" +#include "if_athvar.h" + +#define FALSE 0 +#define TRUE 1 + +typedef int8_t A_RSSI; +typedef int32_t A_RSSI32; +typedef u_int8_t WLAN_PHY; + +#ifndef INLINE +#define INLINE __inline +#endif + +#ifndef A_MIN +#define A_MIN(a,b) ((a)<(b)?(a):(b)) +#endif + +#ifndef A_MAX +#define A_MAX(a,b) ((a)>(b)?(a):(b)) +#endif + +/* + * Use the hal os glue code to get ms time; we supply + * a null arg because we know it's not needed. + */ +#define A_MS_TICKGET() OS_GETUPTIME(NULL) +#define A_MEM_ZERO(p,s) OS_MEMZERO(p,s) + +#define WLAN_PHY_OFDM IEEE80211_T_OFDM +#define WLAN_PHY_TURBO IEEE80211_T_TURBO +#define WLAN_PHY_CCK IEEE80211_T_CCK +#define WLAN_PHY_XR (IEEE80211_T_TURBO+1) + +enum { + WLAN_RC_PHY_CCK, + WLAN_RC_PHY_OFDM, + WLAN_RC_PHY_TURBO, + WLAN_RC_PHY_XR, + WLAN_RC_PHY_HT_20_SS, + WLAN_RC_PHY_HT_20_DS, + WLAN_RC_PHY_HT_40_SS, + WLAN_RC_PHY_HT_40_DS, + WLAN_RC_PHY_HT_20_SS_HGI, + WLAN_RC_PHY_HT_20_DS_HGI, + WLAN_RC_PHY_HT_40_SS_HGI, + WLAN_RC_PHY_HT_40_DS_HGI, + WLAN_RC_PHY_MAX +}; + +#define IS_CHAN_TURBO(_c) (((_c)->channelFlags & CHANNEL_TURBO) != 0) +#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) + +#define PKTLOG_RATE_CTL_FIND(_sc, log_data, flags) ath_log_rcfind(_sc, log_data, flags); +#define PKTLOG_RATE_CTL_UPDATE(_sc, log_data, flags) ath_log_rcupdate(_sc, log_data, flags); +#define ASSERT(condition) + +#define WIRELESS_MODE_11NA IEEE80211_MODE_11NA +#define WIRELESS_MODE_11NG IEEE80211_MODE_11NG +#define WIRELESS_MODE_MAX IEEE80211_MODE_MAX + +#define RX_FLIP_THRESHOLD 3 /* XXX */ + +#ifdef MAGPIE_MERLIN +#define MAX_TX_RATE_TBL 46 +#define MAX_TX_RATE_PHY 48 +#else +#define MAX_TX_RATE_TBL 54//46 +#define MAX_TX_RATE_PHY 56//48 +#endif + +/* + * State structures for new rate adaptation code + * + * NOTE: Modifying these structures will impact + * the Perl script that parses packet logging data. + * See the packet logging module for more information. + */ +typedef struct TxRateCrtlState_s { + A_UINT8 per; /* recent estimate of packet error rate (%) */ +} TxRateCtrlState; + +typedef struct TxRateCtrl_s { + TxRateCtrlState state[MAX_TX_RATE_TBL]; /* state for each rate */ + A_UINT8 rateTableSize; /* rate table size */ + A_UINT8 probeRate; /* rate we are probing at */ + A_UINT32 rssiTime; /* msec timestamp for last ack rssi */ + A_UINT32 probeTime; /* msec timestamp for last probe */ + A_UINT8 hwMaxRetryPktCnt; /* num packets since we got HW max retry error */ + A_UINT8 maxValidRate; /* maximum number of valid rate */ + A_UINT8 validRateIndex[MAX_TX_RATE_TBL]; /* rc Index is valid for this Sib */ + A_UINT32 perDownTime; /* msec timstamp for last PER down step */ + A_UINT8 rcPhyMode; + A_UINT8 rateMaxPhy; /* Phy index for the max rate */ +} TX_RATE_CTRL; + +typedef struct phy_rate_ctrl { + /* 11n state */ + A_UINT8 validPhyRateCount[WLAN_RC_PHY_MAX]; /* valid rate count */ + A_UINT8 validPhyRateIndex[WLAN_RC_PHY_MAX][MAX_TX_RATE_TBL]; /* index */ +}PHY_STATE_CTRL; + +/* per-node state */ +struct atheros_node { + TX_RATE_CTRL txRateCtrl; /* rate control state proper */ + A_UINT32 lastRateKbps; /* last rate in Kb/s */ + A_UINT32 htcap; /* ht capabilites */ + A_UINT8 singleStream :1, /* When TRUE, only single stream Tx possible */ + stbc :2; /* Rx stbc capability */ + +}; + +#define ATH_NODE_ATHEROS(an) (an->an_rcnode) + +/* + * Rate Table structure for various modes - 'b', 'a', 'g', 'xr'; + * order of fields in info structure is important because hardcoded + * structures are initialized within the hal for these + */ + +typedef struct { + int rateCount; + A_UINT8 rateCodeToIndex[RATE_TABLE_SIZE]; /* backward mapping */ + struct { + int valid; /* Valid for use in rate control */ + WLAN_PHY phy; /* CCK/OFDM/TURBO/XR */ + A_UINT16 rateKbps; /* Rate in Kbits per second */ + A_UINT16 userRateKbps; /* User rate in KBits per second */ + A_UINT8 rateCode; /* rate that goes into hw descriptors */ + A_UINT8 shortPreamble; /* Mask for enabling short preamble in rate code for CCK */ + A_UINT8 dot11Rate; /* Value that goes into supported rates info element of MLME */ + A_UINT8 controlRate; /* Index of next lower basic rate, used for duration computation */ + A_RSSI rssiAckValidMin; /* Rate control related information */ + A_RSSI rssiAckDeltaMin; /* Rate control related information */ + A_UINT16 lpAckDuration; /* long preamble ACK duration */ + A_UINT16 spAckDuration; /* short preamble ACK duration*/ + A_UINT32 max4msFrameLen; /* Maximum frame length(bytes) for 4ms tx duration */ + struct { + A_UINT32 word4Retries; + A_UINT32 word5Rates; + } normalSched; + struct { + A_UINT32 word4Retries; + A_UINT32 word5Rates; + } shortSched; + struct { + A_UINT32 word4Retries; + A_UINT32 word5Rates; + } probeSched; + struct { + A_UINT32 word4Retries; + A_UINT32 word5Rates; + } probeShortSched; + struct { + A_UINT32 word4Retries; + A_UINT32 word5Rates; + } uapsd_normalSched; + struct { + A_UINT32 word4Retries; + A_UINT32 word5Rates; + } uapsd_shortSched; +#ifdef ATH_REMOVE_5G_RATE_TABLE +#ifdef ATH_REMOVE_TURBO_RATE_TABLE +#ifdef ATH_REMOVE_XR_RATE_TABLE + } info[12]; +#else +} info[32]; +#endif +#else +} info[32]; +#endif +#else +} info[32]; +#endif +A_UINT32 probeInterval; /* interval for ratectrl to probe for + other rates */ +A_UINT32 rssiReduceInterval; /* interval for ratectrl to reduce RSSI */ +A_UINT8 regularToTurboThresh; /* upperbound on regular (11a or 11g) + mode's rate before switching to turbo*/ +A_UINT8 turboToRegularThresh; /* lowerbound on turbo mode's rate before + switching to regular */ +A_UINT8 pktCountThresh; /* mode switch recommendation criterion: + number of consecutive packets sent at + rate beyond the rate threshold */ +A_UINT8 initialRateMax; /* the initial rateMax value used in + rcSibUpdate() */ +A_UINT8 numTurboRates; /* number of Turbo rates in the rateTable */ +A_UINT8 xrToRegularThresh; /* threshold to switch to Normal mode */ +} RATE_TABLE; + +/* per-device state */ +struct atheros_softc { + struct ath_ratectrl arc; + /* phy tables that contain rate control data */ + void *hwRateTable[WIRELESS_MODE_MAX]; + A_UINT32 tx_chainmask; + A_UINT32 currentTxRateKbps; + A_UINT32 currentTxRateIndex; +}; + +/* + * Update the SIB's rate control information + * + * This should be called when the supported rates change + * (e.g. SME operation, wireless mode change) + * + * It will determine which rates are valid for use. + */ +void +rcSibUpdate(struct ath_softc_tgt *sc, + struct ath_node_target *an, + A_BOOL keepState, + struct ieee80211_rateset *pRateSet); + +/* + * This routine is called to initialize the rate control parameters + * in the SIB. It is called initially during system initialization + * or when a station is associated with the AP. + */ +void rcSibInit(struct ath_softc_tgt *, struct ath_node_target *); + +/* + * Determines and returns the new Tx rate index. + */ +A_UINT16 rcRateFind(struct ath_softc_tgt *, struct atheros_node *, + A_UINT32 frameLen,const RATE_TABLE *pRateTable); + +struct fusion_rate_info { + A_UINT32 txrate; + A_UINT8 rssi; + A_UINT8 per; +}; + +void ar5416AttachRateTables(struct atheros_softc *sc); + +#endif /* _RATECTRL_H_ */ diff --git a/target_firmware/wlan/ratectrl11n.h b/target_firmware/wlan/ratectrl11n.h new file mode 100755 index 0000000..fa44f7c --- /dev/null +++ b/target_firmware/wlan/ratectrl11n.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2000-2002 Atheros Communications, Inc., All Rights Reserved + * + * Definitions for core driver + * This is a common header file for all platforms and operating systems. + */ +#ifndef _RATECTRL11N_H_ +#define _RATECTRL11N_H_ + +/* HT 20/40 rates. If 20 bit is enabled then that rate is + * used only in 20 mode. If both 20/40 bits are enabled + * then that rate can be used for both 20 and 40 mode */ + +#define TRUE_20 0x2 +#define TRUE_40 0x4 +#define TRUE_2040 (TRUE_20|TRUE_40) +#define TRUE_ALL_11N (TRUE_2040|TRUE) + +enum { + WLAN_RC_DS = 0x01, + WLAN_RC_40 = 0x02, + WLAN_RC_SGI = 0x04, + WLAN_RC_HT = 0x08, +}; + +typedef enum { + WLAN_RC_LEGACY = 0, + WLAN_RC_HT_LNPHY = 1, + WLAN_RC_HT_PLPHY = 2, + WLAN_RC_MAX = 3 +} WLAN_RC_VERS; + +#define WLAN_RC_PHY_DS(_phy) ((_phy == WLAN_RC_PHY_HT_20_DS) \ + || (_phy == WLAN_RC_PHY_HT_40_DS) \ + || (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \ + || (_phy == WLAN_RC_PHY_HT_40_DS_HGI)) +#define WLAN_RC_PHY_40(_phy) ((_phy == WLAN_RC_PHY_HT_40_SS) \ + || (_phy == WLAN_RC_PHY_HT_40_DS) \ + || (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \ + || (_phy == WLAN_RC_PHY_HT_40_DS_HGI)) +#define WLAN_RC_PHY_20(_phy) ((_phy == WLAN_RC_PHY_HT_20_SS) \ + || (_phy == WLAN_RC_PHY_HT_20_DS) \ + || (_phy == WLAN_RC_PHY_HT_20_SS_HGI) \ + || (_phy == WLAN_RC_PHY_HT_20_DS_HGI)) +#define WLAN_RC_PHY_SGI(_phy) ((_phy == WLAN_RC_PHY_HT_20_SS_HGI) \ + || (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \ + || (_phy == WLAN_RC_PHY_HT_40_SS_HGI) \ + || (_phy == WLAN_RC_PHY_HT_40_DS_HGI)) + +#define WLAN_RC_PHY_HT(_phy) (_phy >= WLAN_RC_PHY_HT_20_SS) + +/* Returns the capflag mode */ + +#define WLAN_RC_CAP_MODE(capflag) (((capflag & WLAN_RC_HT_FLAG)? \ + (capflag & WLAN_RC_40_FLAG)?TRUE_40:TRUE_20: \ + TRUE)) + +/* Return TRUE if flag supports HT20 && client supports HT20 or + * return TRUE if flag supports HT40 && client supports HT40. + * This is used becos some rates overlap between HT20/HT40. + */ + +#define WLAN_RC_PHY_HT_VALID(flag, capflag) (((flag & TRUE_20) && !(capflag \ + & WLAN_RC_40_FLAG)) || ((flag & TRUE_40) && \ + (capflag & WLAN_RC_40_FLAG))) + +#define WLAN_RC_DS_FLAG (0x01) +#define WLAN_RC_40_FLAG (0x02) +#define WLAN_RC_HT40_SGI_FLAG (0x04) +#define WLAN_RC_HT_FLAG (0x08) +#define WLAN_RC_STBC_FLAG (0x30) /* 2 bits */ +#define WLAN_RC_STBC_FLAG_S ( 4) +#define WLAN_RC_WEP_TKIP_FLAG (0x100) + +/* Index into the rate table */ +#define INIT_RATE_MAX_20 23 +#define INIT_RATE_MAX_40 40 + +/* + * Rate Table structure for various modes - 'b', 'a', 'g', 'xr'; + * order of fields in info structure is important because hardcoded + * structures are initialized within the hal for these + */ + +#ifndef MAGPIE_MERLIN // K2 +#define RATE_TABLE_11N_SIZE 54 +#else +#define RATE_TABLE_11N_SIZE 64 +#endif + +#define MAX_SUPPORTED_MCS 128 + +typedef struct regDataLenTable { + A_UINT8 numEntries; + A_UINT16 frameLenRateIndex[RATE_TABLE_11N_SIZE]; +} REG_DATALEN_TABLE; + +typedef struct { + A_BOOL valid; /* Valid for use in rate control */ + A_BOOL validSingleStream;/* Valid for use in rate control for single stream operation */ +#ifdef MAGPIE_MERLIN + A_BOOL validSTBC; /* Valid for use in rate control for single stream operation */ +#endif + WLAN_PHY phy; /* CCK/OFDM/TURBO/XR */ + A_UINT32 rateKbps; /* Rate in Kbits per second */ + A_UINT32 userRateKbps; /* User rate in KBits per second */ + A_UINT8 rateCode; /* rate that goes into hw descriptors */ + A_UINT8 shortPreamble; /* Mask for enabling short preamble in rate code for CCK */ + A_UINT8 dot11Rate; /* Value that goes into supported rates info element of MLME */ + A_UINT8 controlRate; /* Index of next lower basic rate, used for duration computation */ + A_RSSI rssiAckValidMin; /* Rate control related information */ + A_RSSI rssiAckDeltaMin; /* Rate control related information */ + A_UINT8 baseIndex; /* base rate index */ + A_UINT8 cw40Index; /* 40cap rate index */ + A_UINT8 sgiIndex; /* shortgi rate index */ + A_UINT8 htIndex; /* shortgi rate index */ + A_UINT8 txChainMask_2ch; /* transmit chain mask */ + A_UINT8 txChainMask_3ch; /* transmit chain mask */ + A_UINT32 max4msframelen; /* Maximum frame length(bytes) for 4ms tx duration */ + A_BOOL uapsdvalid; /* Valid for UAPSD nodes */ +} rc11n_info_t; + +typedef struct { + A_UINT8 rateCount; + A_UINT8 probeInterval; /* interval for ratectrl to probe for other rates */ + A_UINT8 rssiReduceInterval; /* interval for ratectrl to reduce RSSI */ + A_UINT8 initialRateMax; /* the initial rateMax value used in rcSibUpdate() */ + rc11n_info_t info[]; +} RATE_TABLE_11N; + +/* + * Update the SIB's rate control information + * + * This should be called when the supported rates change + * (e.g. SME operation, wireless mode change) + * + * It will determine which rates are valid for use. + */ +void rcSibUpdate_11n(struct ath_softc_tgt *, + struct ath_node_target *, + A_UINT32 capflag, + A_BOOL keepState, + struct ieee80211_rate *rs); + +/* + * Determines and returns the new Tx rate index. + */ +void rcRateFind_11n(struct ath_softc_tgt *sc, + struct ath_node_target *an, + int numTries, + int numRates, + int stepDnInc, + unsigned int rcflag, + struct ath_rc_series series[], + int *isProbe); + +/* + * This routine is called by the Tx interrupt service routine to give + * the status of previous frames. + */ +void rcUpdate_11n(struct ath_softc_tgt *sc, + struct ath_node_target *an, + A_UINT8 curTxAnt, + int finalTSIdx, + int Xretries, + struct ath_rc_series rcs[], + int nFrames, + int nBad, + int sh_lo_retry); + +void ath_tx_status_update_rate(struct ath_softc_tgt *sc, + struct ath_rc_series rcs[], + int series, + WMI_TXSTATUS_EVENT *txs); + +#endif /* _RATECTRL11N_H_ */ diff --git a/target_firmware/wlan/ratectrl_11n_ln.c b/target_firmware/wlan/ratectrl_11n_ln.c new file mode 100755 index 0000000..7e62e27 --- /dev/null +++ b/target_firmware/wlan/ratectrl_11n_ln.c @@ -0,0 +1,1252 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include "ah_desc.h" + +#include "ratectrl.h" +#include "ratectrl11n.h" + +INLINE A_RSSI median(A_RSSI a, A_RSSI b, A_RSSI c); + +static void ath_rate_newassoc_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew, + unsigned int capflag, struct ieee80211_rate *rs); + + +static void ath_rate_tx_complete_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, + struct ath_tx_desc *ds, + struct ath_rc_series rcs[], int nframes, + int nbad); + +static void ath_rate_findrate_11n(struct ath_softc_tgt *sc, + struct ath_node_target *an, + size_t frameLen, + int numTries, + int numRates, + int stepDnInc, + unsigned int rcflag, + struct ath_rc_series series[], + int *isProbe); + +static void +rcSortValidRates(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc) +{ + A_UINT8 i,j; + + for (i=pRc->maxValidRate-1; i > 0; i--) { + for (j=0; j <= i-1; j++) { +#ifdef MAGPIE_MERLIN + if (pRateTable->info[pRc->validRateIndex[j]].rateKbps > + pRateTable->info[pRc->validRateIndex[j+1]].rateKbps) +#else + // K2 + if (pRateTable->info[pRc->validRateIndex[j]].userRateKbps > + pRateTable->info[pRc->validRateIndex[j+1]].userRateKbps) +#endif + { + A_UINT8 tmp=0; + tmp = pRc->validRateIndex[j]; + pRc->validRateIndex[j] = pRc->validRateIndex[j+1]; + pRc->validRateIndex[j+1] = tmp; + } + } + } +} + +/* Access functions for validTxRateMask */ + +static void +rcInitValidTxMask(TX_RATE_CTRL *pRc) +{ + A_UINT8 i; + + for (i = 0; i < pRc->rateTableSize; i++) { + pRc->validRateIndex[i] = FALSE; + } +} + +static INLINE void +rcSetValidTxMask(TX_RATE_CTRL *pRc, A_UINT8 index, A_BOOL validTxRate) +{ + ASSERT(index < pRc->rateTableSize); + pRc->validRateIndex[index] = validTxRate ? TRUE : FALSE; + +} + +static INLINE A_BOOL +rcIsValidTxMask(TX_RATE_CTRL *pRc, A_UINT8 index) +{ + ASSERT(index < pRc->rateTableSize); + return (pRc->validRateIndex[index]); +} + +/* Iterators for validTxRateMask */ +static INLINE A_BOOL +rcGetNextValidTxRate(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc, + A_UINT8 curValidTxRate, A_UINT8 *pNextIndex) +{ + A_UINT8 i; + + for (i = 0; i < pRc->maxValidRate-1; i++) { + if (pRc->validRateIndex[i] == curValidTxRate) { + *pNextIndex = pRc->validRateIndex[i+1]; + return TRUE; + } + } + + /* No more valid rates */ + *pNextIndex = 0; + + return FALSE; +} + +static INLINE A_BOOL +rcGetNextLowerValidTxRate(const RATE_TABLE_11N *pRateTable, TX_RATE_CTRL *pRc, + A_UINT8 curValidTxRate, A_UINT8 *pNextIndex) +{ + A_INT8 i; + + for (i = 1; i < pRc->maxValidRate ; i++) { + if (pRc->validRateIndex[i] == curValidTxRate) { + *pNextIndex = pRc->validRateIndex[i-1]; + return TRUE; + } + } + + return FALSE; +} + +/* Return true only for single stream */ + +static A_BOOL +rcIsValidPhyRate(A_UINT32 phy, A_UINT32 capflag, A_BOOL ignoreCW) +{ + if (WLAN_RC_PHY_HT(phy) && !(capflag & WLAN_RC_HT_FLAG)) { + return FALSE; + } + + if (WLAN_RC_PHY_DS(phy) && !(capflag & WLAN_RC_DS_FLAG)) { + return FALSE; + } + if (WLAN_RC_PHY_SGI(phy) && !(capflag & WLAN_RC_HT40_SGI_FLAG)) { + return FALSE; + } + + if (!ignoreCW && WLAN_RC_PHY_HT(phy)) { + if (WLAN_RC_PHY_40(phy) && !(capflag & WLAN_RC_40_FLAG)) { + return FALSE; + } + + if (!WLAN_RC_PHY_40(phy) && (capflag & WLAN_RC_40_FLAG)) { + return FALSE; + } + } + + return TRUE; +} + +/* + * Initialize the Valid Rate Index from valid entries in Rate Table + */ +static A_UINT8 rcSibInitValidRates(const RATE_TABLE_11N *pRateTable, + TX_RATE_CTRL *pRc, + A_UINT32 capflag, + PHY_STATE_CTRL *pPhyStateCtrl) +{ + A_UINT8 i, hi = 0; + A_UINT8 singleStream = (capflag & WLAN_RC_DS_FLAG) ? 0 : 1; + A_UINT8 valid; + + for (i = 0; i < pRateTable->rateCount; i++) { + if (singleStream) { + valid = pRateTable->info[i].validSingleStream; + } else { + valid = pRateTable->info[i].valid; + } + + if (valid == TRUE) { + A_UINT32 phy = pRateTable->info[i].phy; + + if (!rcIsValidPhyRate(phy, capflag, FALSE)) + continue; + + pPhyStateCtrl->validPhyRateIndex[phy][pPhyStateCtrl->validPhyRateCount[phy]] = i; + pPhyStateCtrl->validPhyRateCount[phy] += 1; + + rcSetValidTxMask(pRc, i, TRUE); + + hi = A_MAX(hi, i); + } + } + + return hi; +} + +/* + * Initialize the Valid Rate Index from Rate Set + */ +static A_UINT8 +rcSibSetValidRates(const RATE_TABLE_11N *pRateTable, + TX_RATE_CTRL *pRc, + struct ieee80211_rateset *pRateSet, + A_UINT32 capflag, + struct ath_node_target *an, + PHY_STATE_CTRL *pPhyStateCtrl) +{ + A_UINT8 i, j, hi = 0; + A_UINT8 singleStream = (capflag & WLAN_RC_DS_FLAG) ? 0 : 1; + A_UINT32 valid; + struct atheros_node *pSib = ATH_NODE_ATHEROS(an); + + /* Use intersection of working rates and valid rates */ + for (i = 0; i < pRateSet->rs_nrates; i++) { + for (j = 0; j < pRateTable->rateCount; j++) { + A_UINT32 phy = pRateTable->info[j].phy; + +#ifdef MAGPIE_MERLIN + if (pSib->stbc) { + valid = pRateTable->info[j].validSTBC; + } else if (singleStream) { +#else + if (singleStream) { +#endif + valid = pRateTable->info[j].validSingleStream; + } else { + valid = pRateTable->info[j].valid; + } + + /* + * We allow a rate only if its valid and the capflag matches one of + * the validity (TRUE/TRUE_20/TRUE_40) flags + */ + + if (((pRateSet->rs_rates[i] & 0x7F) == + (pRateTable->info[j].dot11Rate & 0x7F)) + && ((valid & WLAN_RC_CAP_MODE(capflag)) == + WLAN_RC_CAP_MODE(capflag)) && !WLAN_RC_PHY_HT(phy)) { + if (!rcIsValidPhyRate(phy, capflag, FALSE)) + continue; + + pPhyStateCtrl->validPhyRateIndex[phy][pPhyStateCtrl->validPhyRateCount[phy]] = j; + pPhyStateCtrl->validPhyRateCount[phy] += 1; + + rcSetValidTxMask(pRc, j, TRUE); + hi = A_MAX(hi, j); + } + } + } + + return hi; +} + +static A_UINT8 +rcSibSetValidHtRates(const RATE_TABLE_11N *pRateTable, + TX_RATE_CTRL *pRc, + A_UINT8 *pMcsSet, + A_UINT32 capflag, + struct ath_node_target *an, + PHY_STATE_CTRL *pPhyStateCtrl) +{ + A_UINT8 i, j, hi = 0; + A_UINT8 singleStream = (capflag & WLAN_RC_DS_FLAG) ? 0 : 1; + A_UINT8 valid; + struct atheros_node *pSib = ATH_NODE_ATHEROS(an); + + /* Use intersection of working rates and valid rates */ + for (i = 0; i < ((struct ieee80211_rateset *)pMcsSet)->rs_nrates; i++) { + for (j = 0; j < pRateTable->rateCount; j++) { + A_UINT32 phy = pRateTable->info[j].phy; + +#ifdef MAGPIE_MERLIN + if (pSib->stbc) { + valid = pRateTable->info[j].validSTBC; + } else if (singleStream) { +#else + if (singleStream) { +#endif + valid = pRateTable->info[j].validSingleStream; + } else { + valid = pRateTable->info[j].valid; + } + + if (((((struct ieee80211_rateset *)pMcsSet)->rs_rates[i] & 0x7F) + != (pRateTable->info[j].dot11Rate & 0x7F)) + || !WLAN_RC_PHY_HT(phy) + || !WLAN_RC_PHY_HT_VALID(valid, capflag) + || ((pRateTable->info[j].dot11Rate == 15) && + (valid & TRUE_20) && + (capflag & WLAN_RC_WEP_TKIP_FLAG)) ) + { + continue; + } + + if (!rcIsValidPhyRate(phy, capflag, FALSE)) + continue; + + pPhyStateCtrl->validPhyRateIndex[phy][pPhyStateCtrl->validPhyRateCount[phy]] = j; + pPhyStateCtrl->validPhyRateCount[phy] += 1; + + rcSetValidTxMask(pRc, j, TRUE); + hi = A_MAX(hi, j); + } + } + + return hi; +} + +/* + * Update the SIB's rate control information + * + * This should be called when the supported rates change + * (e.g. SME operation, wireless mode change) + * + * It will determine which rates are valid for use. + */ +static void +rcSibUpdate_ht(struct ath_softc_tgt *sc, struct ath_node_target *an, + A_UINT32 capflag, A_BOOL keepState, struct ieee80211_rate *pRateSet) +{ + RATE_TABLE_11N *pRateTable = 0; + struct atheros_node *pSib = ATH_NODE_ATHEROS(an); + struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc; + A_UINT8 *phtMcs = (A_UINT8*)&pRateSet->htrates; + TX_RATE_CTRL *pRc = (TX_RATE_CTRL *)(pSib); + PHY_STATE_CTRL mPhyCtrlState; + + A_UINT8 i, j, k, hi = 0, htHi = 0; + + pRateTable = (RATE_TABLE_11N*)asc->hwRateTable[sc->sc_curmode]; + + /* Initial rate table size. Will change depending on the working rate set */ + pRc->rateTableSize = MAX_TX_RATE_TBL; + + /* Initialize thresholds according to the global rate table */ + for (i = 0 ; (i < pRc->rateTableSize) && (!keepState); i++) { + pRc->state[i].per = 0; + } + + /* Determine the valid rates */ + rcInitValidTxMask(pRc); + + for (i = 0; i < WLAN_RC_PHY_MAX; i++) { + for (j = 0; j < MAX_TX_RATE_PHY; j++) { + mPhyCtrlState.validPhyRateIndex[i][j] = 0; + } + mPhyCtrlState.validPhyRateCount[i] = 0; + } + + pRc->rcPhyMode = (capflag & WLAN_RC_40_FLAG); + + if (pRateSet == NULL || !pRateSet->rates.rs_nrates) { + /* No working rate, just initialize valid rates */ + hi = rcSibInitValidRates(pRateTable, pRc, capflag, &mPhyCtrlState); + } else { + /* Use intersection of working rates and valid rates */ + hi = rcSibSetValidRates(pRateTable, pRc, &(pRateSet->rates), + capflag, an, &mPhyCtrlState); + + if (capflag & WLAN_RC_HT_FLAG) { + htHi = rcSibSetValidHtRates(pRateTable, pRc, phtMcs, + capflag, an, &mPhyCtrlState); + } + + hi = A_MAX(hi, htHi); + } + + pRc->rateTableSize = hi + 1; + pRc->rateMaxPhy = 0; + + ASSERT(pRc->rateTableSize <= MAX_TX_RATE_TBL); + + for (i = 0, k = 0; i < WLAN_RC_PHY_MAX; i++) { + for (j = 0; j < mPhyCtrlState.validPhyRateCount[i]; j++) { + pRc->validRateIndex[k++] = mPhyCtrlState.validPhyRateIndex[i][j]; + } + + if (!rcIsValidPhyRate(i, pRateTable->initialRateMax, TRUE) || + !mPhyCtrlState.validPhyRateCount[i]) + continue; + + pRc->rateMaxPhy = mPhyCtrlState.validPhyRateIndex[i][j-1]; + } + + ASSERT(pRc->rateTableSize <= MAX_TX_RATE_TBL); + ASSERT(k <= MAX_TX_RATE_TBL); + + pRc->rateMaxPhy = pRc->validRateIndex[k-4]; + pRc->maxValidRate = k; + + rcSortValidRates(pRateTable, pRc); +} + +void +rcSibUpdate_11n(struct ath_softc_tgt *sc, struct ath_node_target *pSib, + A_UINT32 capflag, A_BOOL keepState, struct ieee80211_rate *pRateSet) +{ + rcSibUpdate_ht(sc, + pSib, + ((capflag & ATH_RC_DS_FLAG) ? WLAN_RC_DS_FLAG : 0) | + ((capflag & ATH_RC_HT40_SGI_FLAG) ? WLAN_RC_HT40_SGI_FLAG : 0) | + ((capflag & ATH_RC_HT_FLAG) ? WLAN_RC_HT_FLAG : 0) | + ((capflag & ATH_RC_CW40_FLAG) ? WLAN_RC_40_FLAG : 0) | + ((capflag & ATH_RC_TX_STBC_FLAG) ? WLAN_RC_STBC_FLAG : 0), + keepState, + pRateSet); +} + +/* + * Return the median of three numbers + */ +INLINE A_RSSI median(A_RSSI a, A_RSSI b, A_RSSI c) +{ + if (a >= b) { + if (b >= c) { + return b; + } else if (a > c) { + return c; + } else { + return a; + } + } else { + if (a >= c) { + return a; + } else if (b >= c) { + return c; + } else { + return b; + } + } +} + +static A_UINT8 +rcRateFind_ht(struct ath_softc_tgt *sc, struct atheros_node *pSib, + const RATE_TABLE_11N *pRateTable, A_BOOL probeAllowed, A_BOOL *isProbing) +{ + A_UINT32 dt; + A_UINT32 bestThruput, thisThruput; + A_UINT32 nowMsec; + A_UINT8 rate, nextRate, bestRate; + A_RSSI rssiLast, rssiReduce = 0; + A_UINT8 maxIndex, minIndex; + A_INT8 index; + TX_RATE_CTRL *pRc = NULL; + + pRc = (TX_RATE_CTRL *)(pSib ? (pSib) : NULL); + + *isProbing = FALSE; + + /* + * Age (reduce) last ack rssi based on how old it is. + * The bizarre numbers are so the delta is 160msec, + * meaning we divide by 16. + * 0msec <= dt <= 25msec: don't derate + * 25msec <= dt <= 185msec: derate linearly from 0 to 10dB + * 185msec <= dt: derate by 10dB + */ + + nowMsec = A_MS_TICKGET(); + dt = nowMsec - pRc->rssiTime; + + /* + * Now look up the rate in the rssi table and return it. + * If no rates match then we return 0 (lowest rate) + */ + + bestThruput = 0; + maxIndex = pRc->maxValidRate-1; + + minIndex = 0; + bestRate = minIndex; + + /* + * Try the higher rate first. It will reduce memory moving time + * if we have very good channel characteristics. + */ + for (index = maxIndex; index >= minIndex ; index--) { + A_UINT8 perThres; + + rate = pRc->validRateIndex[index]; + if (rate > pRc->rateMaxPhy) { + continue; + } + + /* if the best throughput is already larger than the userRateKbps.. + * then we could skip of rest of calculation.. + */ + if( bestThruput >= pRateTable->info[rate].userRateKbps) + break; + + /* + * For TCP the average collision rate is around 11%, + * so we ignore PERs less than this. This is to + * prevent the rate we are currently using (whose + * PER might be in the 10-15 range because of TCP + * collisions) looking worse than the next lower + * rate whose PER has decayed close to 0. If we + * used to next lower rate, its PER would grow to + * 10-15 and we would be worse off then staying + * at the current rate. + */ + perThres = pRc->state[rate].per; + if ( perThres < 12 ) { + perThres = 12; + } + + thisThruput = pRateTable->info[rate].userRateKbps * (100 - perThres); + if (bestThruput <= thisThruput) { + bestThruput = thisThruput; + bestRate = rate; + } + } + + rate = bestRate; + + /* + * Must check the actual rate (rateKbps) to account for non-monoticity of + * 11g's rate table + */ + + if (rate >= pRc->rateMaxPhy && probeAllowed) { + rate = pRc->rateMaxPhy; + + /* Probe the next allowed phy state */ + /* FIXME: Check to make sure ratMax is checked properly */ + if (rcGetNextValidTxRate( pRateTable, pRc, rate, &nextRate) && + (nowMsec - pRc->probeTime > pRateTable->probeInterval) && + (pRc->hwMaxRetryPktCnt >= 1)) + { + rate = nextRate; + pRc->probeRate = rate; + pRc->probeTime = nowMsec; + pRc->hwMaxRetryPktCnt = 0; + *isProbing = TRUE; + + } + } + + /* + * Make sure rate is not higher than the allowed maximum. + * We should also enforce the min, but I suspect the min is + * normally 1 rather than 0 because of the rate 9 vs 6 issue + * in the old code. + */ + if (rate > (pRc->rateTableSize - 1)) { + rate = pRc->rateTableSize - 1; + } + + /* record selected rate, which is used to decide if we want to do fast frame */ + if (!(*isProbing) && pSib) { + pSib->lastRateKbps = pRateTable->info[rate].rateKbps; + ((struct atheros_softc*)sc->sc_rc)->currentTxRateKbps = pSib->lastRateKbps; + ((struct atheros_softc*)sc->sc_rc)->currentTxRateIndex = rate; + } + + return rate; +} + +static void +rcRateSetseries(const RATE_TABLE_11N *pRateTable , + struct ath_rc_series *series, + A_UINT8 tries, A_UINT8 rix, + A_BOOL rtsctsenable, A_UINT32 chainmask,int stbc) +{ + series->tries = tries; + series->flags = (rtsctsenable? ATH_RC_RTSCTS_FLAG : 0) | + (WLAN_RC_PHY_DS(pRateTable->info[rix].phy) ? ATH_RC_DS_FLAG : 0) | + (WLAN_RC_PHY_40(pRateTable->info[rix].phy) ? ATH_RC_CW40_FLAG : 0) | + (WLAN_RC_PHY_SGI(pRateTable->info[rix].phy) ? ATH_RC_HT40_SGI_FLAG : 0); +#ifdef MAGPIE_MERLIN + if (stbc) { + /* For now, only single stream STBC is supported */ + if (pRateTable->info[rix].rateCode >= 0x80 && + pRateTable->info[rix].rateCode <= 0x87) + { + series->flags |= ATH_RC_TX_STBC_FLAG; + } + } +#endif + series->rix = pRateTable->info[rix].baseIndex; + series->max4msframelen = pRateTable->info[rix].max4msframelen; + series->txrateKbps = pRateTable->info[rix].rateKbps; + + /* If the hardware is capable of multiple transmit chains (chainmask is 3, 5 or 7), + * then choose the number of transmit chains dynamically based on entries in the rate table. + */ +#ifndef ATH_ENABLE_WLAN_FOR_K2 + if(chainmask == 7) + series->tx_chainmask = pRateTable->info[rix].txChainMask_3ch; + else if(chainmask == 1) + series->tx_chainmask = 1; + else + series->tx_chainmask = pRateTable->info[rix].txChainMask_2ch; /*Chainmask is 3 or 5*/ +#else + series->tx_chainmask = 1; +#endif +} + +static A_UINT8 +rcRateGetIndex(struct ath_softc_tgt *sc, struct ath_node_target *an, + const RATE_TABLE_11N *pRateTable , + A_UINT8 rix, A_UINT16 stepDown, A_UINT16 minRate) +{ + A_UINT32 j; + A_UINT8 nextIndex; + struct atheros_node *pSib = ATH_NODE_ATHEROS(an); + TX_RATE_CTRL *pRc = (TX_RATE_CTRL *)(pSib); + + if (minRate) { + for (j = RATE_TABLE_11N_SIZE; j > 0; j-- ) { + if (rcGetNextLowerValidTxRate(pRateTable, pRc, rix, &nextIndex)) { + rix = nextIndex; + } else { + break; + } + } + } else { + for (j = stepDown; j > 0; j-- ) { + if (rcGetNextLowerValidTxRate(pRateTable, pRc, rix, &nextIndex)) { + rix = nextIndex; + } else { + break; + } + } + } + + return rix; +} + +void rcRateFind_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, + int numTries, int numRates, int stepDnInc, + unsigned int rcflag, struct ath_rc_series series[], int *isProbe) +{ + A_UINT8 i = 0; + A_UINT8 tryPerRate = 0; + struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc; + RATE_TABLE_11N *pRateTable = (RATE_TABLE_11N *)asc->hwRateTable[sc->sc_curmode]; + struct atheros_node *asn = ATH_NODE_ATHEROS(an); + A_UINT8 rix, nrix; + A_UINT8 dot11Rate; + A_UINT8 rateCode; + WLAN_PHY phy; + + rix = rcRateFind_ht(sc, asn, pRateTable, (rcflag & ATH_RC_PROBE_ALLOWED) ? 1 : 0, + isProbe); + nrix = rix; + + if ((rcflag & ATH_RC_PROBE_ALLOWED) && (*isProbe)) { + /* set one try for probe rates. For the probes don't enable rts */ + rcRateSetseries(pRateTable, &series[i++], 1, nrix, + FALSE, asc->tx_chainmask, asn->stbc); + + /* + * Get the next tried/allowed rate. No RTS for the next series + * after the probe rate + */ + nrix = rcRateGetIndex( sc, an, pRateTable, nrix, 1, FALSE); + } + + tryPerRate = (numTries/numRates); + + /* Set the choosen rate. No RTS for first series entry. */ + rcRateSetseries(pRateTable, &series[i++], tryPerRate, + nrix, FALSE, asc->tx_chainmask, asn->stbc); + + /* Fill in the other rates for multirate retry */ + for (; i < numRates; i++) { + A_UINT8 tryNum; + A_UINT8 minRate; + + tryNum = ((i + 1) == numRates) ? numTries - (tryPerRate * i) : tryPerRate ; + minRate = (((i + 1) == numRates) && (rcflag & ATH_RC_MINRATE_LASTRATE)) ? 1 : 0; + + nrix = rcRateGetIndex(sc, an, pRateTable, nrix, stepDnInc, minRate); + + /* All other rates in the series have RTS enabled */ + rcRateSetseries(pRateTable, &series[i], tryNum, + nrix, TRUE, asc->tx_chainmask, asn->stbc); + } + + /* + * BUG 26545: + * Change rate series to enable aggregation when operating at lower MCS rates. + * When first rate in series is MCS2 in HT40 @ 2.4GHz, series should look like: + * {MCS2, MCS1, MCS0, MCS0}. + * When first rate in series is MCS3 in HT20 @ 2.4GHz, series should look like: + * {MCS3, MCS2, MCS1, MCS1} + * So, set fourth rate in series to be same as third one for above conditions. + */ + if (sc->sc_curmode == IEEE80211_MODE_11NG) { + dot11Rate = pRateTable->info[rix].dot11Rate; + phy = pRateTable->info[rix].phy; + if (i == 4 && + ((dot11Rate == 2 && phy == WLAN_RC_PHY_HT_40_SS) || + (dot11Rate == 3 && phy == WLAN_RC_PHY_HT_20_SS))) + { + series[3].rix = series[2].rix; + series[3].flags = series[2].flags; + series[3].max4msframelen = series[2].max4msframelen; + } + } + + /* + * 2009/02/06 + * AP91 Kite: NetGear OTA location-4 downlink. + * Enable RTS/CTS at MCS 3-0 for downlink throughput. + */ + if (sc->sc_curmode == IEEE80211_MODE_11NG) { + dot11Rate = pRateTable->info[rix].dot11Rate; + if (dot11Rate <= 3 ) { + series[0].flags |= ATH_RC_RTSCTS_FLAG; + } + } +} + +static void +rcUpdate_ht(struct ath_softc_tgt *sc, struct ath_node_target *an, int txRate, + A_BOOL Xretries, int retries, A_UINT8 curTxAnt, + A_UINT16 nFrames, A_UINT16 nBad) +{ + TX_RATE_CTRL *pRc; + A_UINT32 nowMsec = A_MS_TICKGET(); + A_BOOL stateChange = FALSE; + A_UINT8 lastPer; + int rate,count; + struct atheros_node *pSib = ATH_NODE_ATHEROS(an); + struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc; + RATE_TABLE_11N *pRateTable = (RATE_TABLE_11N *)asc->hwRateTable[sc->sc_curmode]; + u_int32_t txRateKbps; + + static A_UINT32 nRetry2PerLookup[10] = { + 100 * 0 / 1, // 0 + 100 * 1 / 4, // 25 + 100 * 1 / 2, // 50 + 100 * 3 / 4, // 75 + 100 * 4 / 5, // 80 + 100 * 5 / 6, // 83.3 + 100 * 6 / 7, // 85.7 + 100 * 7 / 8, // 87.5 + 100 * 8 / 9, // 88.8 + 100 * 9 / 10 // 90 + }; + + if (!pSib) + return; + + pRc = (TX_RATE_CTRL *)(pSib); + + ASSERT(retries >= 0 && retries < MAX_TX_RETRIES); + ASSERT(txRate >= 0); + + if (txRate < 0) { + return; + } + + lastPer = pRc->state[txRate].per; + + if (Xretries) { + /* Update the PER. */ + if (Xretries == 1) { + pRc->state[txRate].per += 30; + if (pRc->state[txRate].per > 100) { + pRc->state[txRate].per = 100; + } + } else { + /* Xretries == 2 */ + + count = sizeof(nRetry2PerLookup) / sizeof(nRetry2PerLookup[0]); + if (retries >= count) { + retries = count - 1; + } + + /* new_PER = 7/8*old_PER + 1/8*(currentPER) */ + pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per - + (pRc->state[txRate].per / 8) + ((100) / 8)); + } + + /* Xretries == 1 or 2 */ + + if (pRc->probeRate == txRate) + pRc->probeRate = 0; + } else { + /* Xretries == 0 */ + + /* + * Update the PER. Make sure it doesn't index out of array's bounds. + */ + count = sizeof(nRetry2PerLookup) / sizeof(nRetry2PerLookup[0]); + if (retries >= count) { + retries = count - 1; + } + + if (nBad) { + /* new_PER = 7/8*old_PER + 1/8*(currentPER) */ + /* + * Assuming that nFrames is not 0. The current PER + * from the retries is 100 * retries / (retries+1), + * since the first retries attempts failed, and the + * next one worked. For the one that worked, nBad + * subframes out of nFrames wored, so the PER for + * that part is 100 * nBad / nFrames, and it contributes + * 100 * nBad / (nFrames * (retries+1)) to the above + * PER. The expression below is a simplified version + * of the sum of these two terms. + */ + if (nFrames > 0) + pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per - + (pRc->state[txRate].per / 8) + + ((100*(retries*nFrames + nBad)/(nFrames*(retries+1))) / 8)); + } else { + /* new_PER = 7/8*old_PER + 1/8*(currentPER) */ + + pRc->state[txRate].per = (A_UINT8)(pRc->state[txRate].per - + (pRc->state[txRate].per / 8) + (nRetry2PerLookup[retries] / 8)); + } + + /* + * If we got at most one retry then increase the max rate if + * this was a probe. Otherwise, ignore the probe. + */ + + if (pRc->probeRate && pRc->probeRate == txRate) { + if (retries > 0 || 2 * nBad > nFrames) { + /* + * Since we probed with just a single attempt, + * any retries means the probe failed. Also, + * if the attempt worked, but more than half + * the subframes were bad then also consider + * the probe a failure. + */ + pRc->probeRate = 0; + } else { + pRc->rateMaxPhy = pRc->probeRate; + + if (pRc->state[pRc->probeRate].per > 30) { + pRc->state[pRc->probeRate].per = 20; + } + + pRc->probeRate = 0; + + /* + * Since this probe succeeded, we allow the next probe + * twice as soon. This allows the maxRate to move up + * faster if the probes are succesful. + */ + pRc->probeTime = nowMsec - pRateTable->probeInterval / 2; + } + } + + if (retries > 0) { + /* + * Don't update anything. We don't know if this was because + * of collisions or poor signal. + * + * Later: if rssiAck is close to pRc->state[txRate].rssiThres + * and we see lots of retries, then we could increase + * pRc->state[txRate].rssiThres. + */ + pRc->hwMaxRetryPktCnt = 0; + } else { + /* + * It worked with no retries. First ignore bogus (small) + * rssiAck values. + */ + if (txRate == pRc->rateMaxPhy && pRc->hwMaxRetryPktCnt < 255) { + pRc->hwMaxRetryPktCnt++; + } + + } + } + + /* For all cases */ + + ASSERT((pRc->rateMaxPhy >= 0 && pRc->rateMaxPhy <= pRc->rateTableSize && + pRc->rateMaxPhy != INVALID_RATE_MAX)); + + /* + * If this rate looks bad (high PER) then stop using it for + * a while (except if we are probing). + */ + if (pRc->state[txRate].per >= 55 && txRate > 0 && + pRateTable->info[txRate].rateKbps <= + pRateTable->info[pRc->rateMaxPhy].rateKbps) + { + rcGetNextLowerValidTxRate(pRateTable, pRc, (A_UINT8) txRate, + &pRc->rateMaxPhy); + + /* Don't probe for a little while. */ + pRc->probeTime = nowMsec; + } + + /* Make sure the rates below this have lower PER */ + /* Monotonicity is kept only for rates below the current rate. */ + if (pRc->state[txRate].per < lastPer) { + for (rate = txRate - 1; rate >= 0; rate--) { + if (pRateTable->info[rate].phy != pRateTable->info[txRate].phy) { + break; + } + + if (pRc->state[rate].per > pRc->state[rate+1].per) { + pRc->state[rate].per = pRc->state[rate+1].per; + } + } + } + + /* Maintain monotonicity for rates above the current rate*/ + for (rate = txRate; rate < pRc->rateTableSize - 1; rate++) { + if (pRc->state[rate+1].per < pRc->state[rate].per) { + pRc->state[rate+1].per = pRc->state[rate].per; + } + } + + /* Every so often, we reduce the thresholds and PER (different for CCK and OFDM). */ + if (nowMsec - pRc->perDownTime >= pRateTable->rssiReduceInterval) { + for (rate = 0; rate < pRc->rateTableSize; rate++) { + pRc->state[rate].per = 7*pRc->state[rate].per/8; + } + + pRc->perDownTime = nowMsec; + } +} + +/* + * This routine is called by the Tx interrupt service routine to give + * the status of previous frames. + */ +void rcUpdate_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, + A_UINT8 curTxAnt, + int finalTSIdx, int Xretries, + struct ath_rc_series rcs[], int nFrames, + int nBad, int long_retry) +{ + A_UINT32 series = 0; + A_UINT32 rix; + struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc; + RATE_TABLE_11N *pRateTable = (RATE_TABLE_11N *)asc->hwRateTable[sc->sc_curmode]; + struct atheros_node *pSib = ATH_NODE_ATHEROS(an); + TX_RATE_CTRL *pRc = (TX_RATE_CTRL *)(pSib); + A_UINT8 flags; + + if (!an) { + adf_os_assert(0); + return; + } + + ASSERT (rcs[0].tries != 0); + + /* + * If the first rate is not the final index, there are intermediate rate failures + * to be processed. + */ + if (finalTSIdx != 0) { + + /* Process intermediate rates that failed.*/ + for (series = 0; series < finalTSIdx ; series++) { + if (rcs[series].tries != 0) { + flags = rcs[series].flags; + /* If HT40 and we have switched mode from 40 to 20 => don't update */ + if ((flags & ATH_RC_CW40_FLAG) && + (pRc->rcPhyMode != (flags & ATH_RC_CW40_FLAG))) { + return; + } + if ((flags & ATH_RC_CW40_FLAG) && (flags & ATH_RC_HT40_SGI_FLAG)) { + rix = pRateTable->info[rcs[series].rix].htIndex; + } else if (flags & ATH_RC_HT40_SGI_FLAG) { + rix = pRateTable->info[rcs[series].rix].sgiIndex; + } else if (flags & ATH_RC_CW40_FLAG) { + rix = pRateTable->info[rcs[series].rix].cw40Index; + } else { + rix = pRateTable->info[rcs[series].rix].baseIndex; + } + + /* FIXME:XXXX, too many args! */ + rcUpdate_ht(sc, an, rix, Xretries? 1 : 2, rcs[series].tries, + curTxAnt, nFrames, nFrames); + } + } + } else { + /* + * Handle the special case of MIMO PS burst, where the second aggregate is sent + * out with only one rate and one try. Treating it as an excessive retry penalizes + * the rate inordinately. + */ + if (rcs[0].tries == 1 && Xretries == 1) { + Xretries = 2; + } + } + + flags = rcs[series].flags; + /* If HT40 and we have switched mode from 40 to 20 => don't update */ + if ((flags & ATH_RC_CW40_FLAG) && + (pRc->rcPhyMode != (flags & ATH_RC_CW40_FLAG))) { + return; + } + if ((flags & ATH_RC_CW40_FLAG) && (flags & ATH_RC_HT40_SGI_FLAG)) { + rix = pRateTable->info[rcs[series].rix].htIndex; + } else if (flags & ATH_RC_HT40_SGI_FLAG) { + rix = pRateTable->info[rcs[series].rix].sgiIndex; + } else if (flags & ATH_RC_CW40_FLAG) { + rix = pRateTable->info[rcs[series].rix].cw40Index; + } else { + rix = pRateTable->info[rcs[series].rix].baseIndex; + } + + /* FIXME:XXXX, too many args! */ + rcUpdate_ht(sc, an, rix, Xretries, long_retry, curTxAnt, + nFrames, nBad); +} + +void ath_tx_status_update_rate(struct ath_softc_tgt *sc, + struct ath_rc_series rcs[], + int series, + WMI_TXSTATUS_EVENT *txs) +{ + struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc; + RATE_TABLE_11N *pRateTable = (RATE_TABLE_11N *)asc->hwRateTable[sc->sc_curmode]; + + /* HT Rate */ + if (pRateTable->info[rcs[series].rix].rateCode & 0x80) { + txs->txstatus[txs->cnt].ts_rate |= SM(pRateTable->info[rcs[series].rix].dot11Rate, + ATH9K_HTC_TXSTAT_RATE); + txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_MCS; + + if (rcs[series].flags & ATH_RC_CW40_FLAG) + txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_CW40; + + if (rcs[series].flags & ATH_RC_HT40_SGI_FLAG) + txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_SGI; + + } else { + txs->txstatus[txs->cnt].ts_rate |= SM(rcs[series].rix, ATH9K_HTC_TXSTAT_RATE); + } + + if (rcs[series].flags & ATH_RC_RTSCTS_FLAG) + txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_RTC_CTS; + +} + +struct ath_ratectrl * +ath_rate_attach(struct ath_softc_tgt *sc) +{ + struct atheros_softc *asc; + + asc = adf_os_mem_alloc(sizeof(struct atheros_softc)); + if (asc == NULL) + return NULL; + + adf_os_mem_set(asc, 0, sizeof(struct atheros_softc)); + asc->arc.arc_space = sizeof(struct atheros_node); + + ar5416AttachRateTables(asc); + + asc->tx_chainmask = 1; + + return &asc->arc; +} + +void +ath_rate_detach(struct ath_ratectrl *rc) +{ + adf_os_mem_free(rc); +} + +void +ath_rate_findrate(struct ath_softc_tgt *sc, + struct ath_node_target *an, + int shortPreamble, + size_t frameLen, + int numTries, + int numRates, + int stepDnInc, + unsigned int rcflag, + struct ath_rc_series series[], + int *isProbe) +{ + struct ieee80211vap *vap = an->ni.ni_vap; + struct atheros_node *oan = ATH_NODE_ATHEROS(an); + struct atheros_softc *asc = (struct atheros_softc *) sc->sc_rc; + RATE_TABLE *pRateTable = (RATE_TABLE *)asc->hwRateTable[sc->sc_curmode]; + u_int32_t *retrySched; + + *isProbe = 0; + + if (!numRates || !numTries) { + return; + } + + ath_rate_findrate_11n(sc, an, frameLen, numTries, numRates, stepDnInc, + rcflag, series, isProbe); +} + +#define MS(_v, _f) (((_v) & _f) >> _f##_S) + +void +ath_rate_tx_complete(struct ath_softc_tgt *sc, + struct ath_node_target *an, + struct ath_tx_desc *ds, + struct ath_rc_series rcs[], + int nframes, int nbad) +{ + struct atheros_softc *asc = (struct atheros_softc *) sc->sc_rc; + const RATE_TABLE *pRateTable = (RATE_TABLE *)asc->hwRateTable[sc->sc_curmode]; + u_int8_t txRate = ds->ds_txstat.ts_rate &~ HAL_TXSTAT_ALTRATE; + + ath_rate_tx_complete_11n(sc, an, ds, rcs, nframes, nbad); +} + +void +ath_rate_newassoc(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew, + unsigned int capflag, struct ieee80211_rate *rs) +{ + ath_rate_newassoc_11n(sc, an, isnew, capflag, rs); +} + +void ath_rate_node_update(struct ath_softc_tgt *sc, + struct ath_node_target *an, + a_int32_t isnew, + a_uint32_t capflag, + struct ieee80211_rate *rs) +{ + struct ieee80211_node_target *ni = &an->ni; + + ath_rate_newassoc(sc, ATH_NODE_TARGET(ni), isnew, capflag, rs); +} + +static int init_ath_rate_atheros(void); +static void exit_ath_rate_atheros(void); + +void +ath_rate_newstate(struct ath_softc_tgt *sc, + struct ieee80211vap_target *vap, + enum ieee80211_state state, + a_uint32_t capflag, + struct ieee80211_rate *rs) +{ + struct ieee80211_node_target *ni = vap->iv_bss; + struct atheros_softc *asc = (struct atheros_softc *) sc->sc_rc; + + asc->tx_chainmask = sc->sc_ic.ic_tx_chainmask; + ath_rate_newassoc(sc, ni, 1, capflag, rs); +} + +static void +ath_rate_findrate_11n(struct ath_softc_tgt *sc, + struct ath_node_target *an, + size_t frameLen, + int numTries, + int numRates, + int stepDnInc, + unsigned int rcflag, + struct ath_rc_series series[], + int *isProbe) +{ + struct ieee80211vap *vap = an->ni.ni_vap; + struct atheros_node *oan = ATH_NODE_ATHEROS(an); + + *isProbe = 0; + if (!numRates || !numTries) { + return; + } + + rcRateFind_11n(sc, an, numTries, numRates, stepDnInc, rcflag, series, isProbe); +} + +static void +ath_rate_tx_complete_11n(struct ath_softc_tgt *sc, + struct ath_node_target *an, + struct ath_tx_desc *ds, + struct ath_rc_series rcs[], + int nframes, int nbad) +{ + int finalTSIdx = ds->ds_txstat.ts_rate; + int tx_status = 0; + + if ((ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) || + (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) || + (ds->ds_txstat.ts_flags & HAL_TX_DATA_UNDERRUN) || + (ds->ds_txstat.ts_flags & HAL_TX_DELIM_UNDERRUN)) { + tx_status = 1; + } + + rcUpdate_11n(sc, an, + ds->ds_txstat.ts_antenna, finalTSIdx, + tx_status, rcs, nframes , nbad, + ds->ds_txstat.ts_longretry); +} + +static void +ath_rate_newassoc_11n(struct ath_softc_tgt *sc, struct ath_node_target *an, int isnew, + unsigned int capflag, struct ieee80211_rate *rs) +{ + struct ieee80211vap *vap = an->ni.ni_vap; + + if (isnew) { + struct atheros_node *oan = ATH_NODE_ATHEROS(an); + + oan->htcap = ((capflag & ATH_RC_DS_FLAG) ? WLAN_RC_DS_FLAG : 0) | + ((capflag & ATH_RC_HT40_SGI_FLAG) ? WLAN_RC_HT40_SGI_FLAG : 0) | + ((capflag & ATH_RC_HT_FLAG) ? WLAN_RC_HT_FLAG : 0) | + ((capflag & ATH_RC_CW40_FLAG) ? WLAN_RC_40_FLAG : 0) | + ((capflag & ATH_RC_WEP_TKIP_FLAG) ? WLAN_RC_WEP_TKIP_FLAG : 0); + +#ifdef MAGPIE_MERLIN + /* Rx STBC is a 2-bit mask. Needs to convert from ath definition to wlan definition. */ + + oan->htcap |= (((capflag & ATH_RC_RX_STBC_FLAG) >> ATH_RC_RX_STBC_FLAG_S) + << WLAN_RC_STBC_FLAG_S); + + /* If only one chain is enabled, do not do stbc. */ + if (sc->sc_txstbcsupport) { + oan->stbc = (capflag & ATH_RC_RX_STBC_FLAG) >> ATH_RC_RX_STBC_FLAG_S; + } else { + oan->stbc = 0; + } + +#endif + rcSibUpdate_11n(sc, an, oan->htcap, 0, rs); + } +} + +void ath_rate_mcs2rate(struct ath_softc_tgt *sc,a_uint8_t sgi, a_uint8_t ht40, + a_uint8_t rateCode, a_uint32_t *txrate, a_uint32_t *rxrate) +{ + int idx; + struct atheros_softc *asc = (struct atheros_softc*)sc->sc_rc; + RATE_TABLE_11N *pRateTable = (RATE_TABLE_11N *)asc->hwRateTable[sc->sc_curmode]; + a_uint32_t rateKbps = 0; + + *txrate = asc->currentTxRateKbps; + + /* look 11NA table for rateKbps*/ + for (idx = 0; idx < pRateTable->rateCount && !rateKbps; ++idx) { + if (pRateTable->info[idx].rateCode == rateCode) { + if(ht40 && sgi) { + if(pRateTable->info[idx].valid == TRUE_40 && + pRateTable->info[idx].phy == WLAN_RC_PHY_HT_40_DS_HGI) + rateKbps = pRateTable->info[idx].rateKbps; + } else if (ht40) { + if (pRateTable->info[idx].valid == TRUE_40)/* HT40 only*/ + rateKbps = pRateTable->info[idx].rateKbps; + } else { + if (pRateTable->info[idx].valid != FALSE) + rateKbps = pRateTable->info[idx].rateKbps; + } + } + } + + *rxrate = rateKbps; +} diff --git a/toolchain/inst/xtensa-elf/include/xtensa/config/core.h b/toolchain/inst/xtensa-elf/include/xtensa/config/core.h new file mode 100644 index 0000000..01bcfdd --- /dev/null +++ b/toolchain/inst/xtensa-elf/include/xtensa/config/core.h @@ -0,0 +1,1222 @@ +/* + * xtensa/config/core.h -- HAL definitions dependent on CORE configuration + * + * This header file is sometimes referred to as the "compile-time HAL" or CHAL. + * It pulls definitions tailored for a specific Xtensa processor configuration. + * + * Sources for binaries meant to be configuration-independent generally avoid + * including this file (they may use the configuration-specific HAL library). + * It is normal for the HAL library source itself to include this file. + */ + +/* + * Copyright (c) 2005-2007 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + + +#ifndef XTENSA_CONFIG_CORE_H +#define XTENSA_CONFIG_CORE_H + +/* CONFIGURATION INDEPENDENT DEFINITIONS: */ +#ifdef __XTENSA__ +#include +#else +#include "../hal.h" +#endif + +/* CONFIGURATION SPECIFIC DEFINITIONS: */ +#ifdef __XTENSA__ +#include +#include +#include +#else +#include "core-isa.h" +#include "core-matmap.h" +#include "tie.h" +#endif + +#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) +#ifdef __XTENSA__ +#include +#else +#include "tie-asm.h" +#endif +#endif /*_ASMLANGUAGE or __ASSEMBLER__*/ + + +/*---------------------------------------------------------------------- + GENERAL + ----------------------------------------------------------------------*/ + +/* + * Separators for macros that expand into arrays. + * These can be predefined by files that #include this one, + * when different separators are required. + */ +/* Element separator for macros that expand into 1-dimensional arrays: */ +#ifndef XCHAL_SEP +#define XCHAL_SEP , +#endif +/* Array separator for macros that expand into 2-dimensional arrays: */ +#ifndef XCHAL_SEP2 +#define XCHAL_SEP2 },{ +#endif + + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#if XCHAL_HAVE_BE +# define XCHAL_HAVE_LE 0 +# define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN +#else +# define XCHAL_HAVE_LE 1 +# define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN +#endif + + + +/*---------------------------------------------------------------------- + INTERRUPTS + ----------------------------------------------------------------------*/ + +/* Indexing macros: */ +#define _XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK +#define XCHAL_INTLEVEL_MASK(n) _XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */ +#define _XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK +#define XCHAL_INTLEVEL_ANDBELOW_MASK(n) _XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */ +#define _XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM +#define XCHAL_INTLEVEL_NUM(n) _XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */ +#define _XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL +#define XCHAL_INT_LEVEL(n) _XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */ +#define _XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE +#define XCHAL_INT_TYPE(n) _XCHAL_INT_TYPE(n) /* n = 0 .. 31 */ +#define _XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT +#define XCHAL_TIMER_INTERRUPT(n) _XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */ + + +#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS +#define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */ +#define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */ +/* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */ + +/* These values are constant for existing Xtensa processor implementations: */ +#define XCHAL_INTLEVEL0_MASK 0x00000000 +#define XCHAL_INTLEVEL8_MASK 0x00000000 +#define XCHAL_INTLEVEL9_MASK 0x00000000 +#define XCHAL_INTLEVEL10_MASK 0x00000000 +#define XCHAL_INTLEVEL11_MASK 0x00000000 +#define XCHAL_INTLEVEL12_MASK 0x00000000 +#define XCHAL_INTLEVEL13_MASK 0x00000000 +#define XCHAL_INTLEVEL14_MASK 0x00000000 +#define XCHAL_INTLEVEL15_MASK 0x00000000 + +/* Array of masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \ + XCHAL_SEP XCHAL_INTLEVEL1_MASK \ + XCHAL_SEP XCHAL_INTLEVEL2_MASK \ + XCHAL_SEP XCHAL_INTLEVEL3_MASK \ + XCHAL_SEP XCHAL_INTLEVEL4_MASK \ + XCHAL_SEP XCHAL_INTLEVEL5_MASK \ + XCHAL_SEP XCHAL_INTLEVEL6_MASK \ + XCHAL_SEP XCHAL_INTLEVEL7_MASK \ + XCHAL_SEP XCHAL_INTLEVEL8_MASK \ + XCHAL_SEP XCHAL_INTLEVEL9_MASK \ + XCHAL_SEP XCHAL_INTLEVEL10_MASK \ + XCHAL_SEP XCHAL_INTLEVEL11_MASK \ + XCHAL_SEP XCHAL_INTLEVEL12_MASK \ + XCHAL_SEP XCHAL_INTLEVEL13_MASK \ + XCHAL_SEP XCHAL_INTLEVEL14_MASK \ + XCHAL_SEP XCHAL_INTLEVEL15_MASK + +/* These values are constant for existing Xtensa processor implementations: */ +#define XCHAL_INTLEVEL0_ANDBELOW_MASK 0x00000000 +#define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK +#define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK + +/* Mask of all low-priority interrupts: */ +#define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK + +/* Mask of all interrupts masked by PS.EXCM (or CEXCM): */ +#define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL) + +/* Array of masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \ + XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK + +#if 0 /*XCHAL_HAVE_NMI*/ +/* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */ +# define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1) +#endif + +/* Array of levels of each possible interrupt: */ +#define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \ + XCHAL_SEP XCHAL_INT1_LEVEL \ + XCHAL_SEP XCHAL_INT2_LEVEL \ + XCHAL_SEP XCHAL_INT3_LEVEL \ + XCHAL_SEP XCHAL_INT4_LEVEL \ + XCHAL_SEP XCHAL_INT5_LEVEL \ + XCHAL_SEP XCHAL_INT6_LEVEL \ + XCHAL_SEP XCHAL_INT7_LEVEL \ + XCHAL_SEP XCHAL_INT8_LEVEL \ + XCHAL_SEP XCHAL_INT9_LEVEL \ + XCHAL_SEP XCHAL_INT10_LEVEL \ + XCHAL_SEP XCHAL_INT11_LEVEL \ + XCHAL_SEP XCHAL_INT12_LEVEL \ + XCHAL_SEP XCHAL_INT13_LEVEL \ + XCHAL_SEP XCHAL_INT14_LEVEL \ + XCHAL_SEP XCHAL_INT15_LEVEL \ + XCHAL_SEP XCHAL_INT16_LEVEL \ + XCHAL_SEP XCHAL_INT17_LEVEL \ + XCHAL_SEP XCHAL_INT18_LEVEL \ + XCHAL_SEP XCHAL_INT19_LEVEL \ + XCHAL_SEP XCHAL_INT20_LEVEL \ + XCHAL_SEP XCHAL_INT21_LEVEL \ + XCHAL_SEP XCHAL_INT22_LEVEL \ + XCHAL_SEP XCHAL_INT23_LEVEL \ + XCHAL_SEP XCHAL_INT24_LEVEL \ + XCHAL_SEP XCHAL_INT25_LEVEL \ + XCHAL_SEP XCHAL_INT26_LEVEL \ + XCHAL_SEP XCHAL_INT27_LEVEL \ + XCHAL_SEP XCHAL_INT28_LEVEL \ + XCHAL_SEP XCHAL_INT29_LEVEL \ + XCHAL_SEP XCHAL_INT30_LEVEL \ + XCHAL_SEP XCHAL_INT31_LEVEL + +/* Array of types of each possible interrupt: */ +#define XCHAL_INT_TYPES XCHAL_INT0_TYPE \ + XCHAL_SEP XCHAL_INT1_TYPE \ + XCHAL_SEP XCHAL_INT2_TYPE \ + XCHAL_SEP XCHAL_INT3_TYPE \ + XCHAL_SEP XCHAL_INT4_TYPE \ + XCHAL_SEP XCHAL_INT5_TYPE \ + XCHAL_SEP XCHAL_INT6_TYPE \ + XCHAL_SEP XCHAL_INT7_TYPE \ + XCHAL_SEP XCHAL_INT8_TYPE \ + XCHAL_SEP XCHAL_INT9_TYPE \ + XCHAL_SEP XCHAL_INT10_TYPE \ + XCHAL_SEP XCHAL_INT11_TYPE \ + XCHAL_SEP XCHAL_INT12_TYPE \ + XCHAL_SEP XCHAL_INT13_TYPE \ + XCHAL_SEP XCHAL_INT14_TYPE \ + XCHAL_SEP XCHAL_INT15_TYPE \ + XCHAL_SEP XCHAL_INT16_TYPE \ + XCHAL_SEP XCHAL_INT17_TYPE \ + XCHAL_SEP XCHAL_INT18_TYPE \ + XCHAL_SEP XCHAL_INT19_TYPE \ + XCHAL_SEP XCHAL_INT20_TYPE \ + XCHAL_SEP XCHAL_INT21_TYPE \ + XCHAL_SEP XCHAL_INT22_TYPE \ + XCHAL_SEP XCHAL_INT23_TYPE \ + XCHAL_SEP XCHAL_INT24_TYPE \ + XCHAL_SEP XCHAL_INT25_TYPE \ + XCHAL_SEP XCHAL_INT26_TYPE \ + XCHAL_SEP XCHAL_INT27_TYPE \ + XCHAL_SEP XCHAL_INT28_TYPE \ + XCHAL_SEP XCHAL_INT29_TYPE \ + XCHAL_SEP XCHAL_INT30_TYPE \ + XCHAL_SEP XCHAL_INT31_TYPE + +/* Array of masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \ + XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \ + XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \ + XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \ + XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \ + XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \ + XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR + +/* Interrupts that can be cleared using the INTCLEAR special register: */ +#define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR) +/* Interrupts that can be triggered using the INTSET special register: */ +#define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE + +/* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */ +#define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER1_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER2_INTERRUPT \ + XCHAL_SEP XCHAL_TIMER3_INTERRUPT + + + +/* For backward compatibility and for the array macros, define macros for + * each unconfigured interrupt number (unfortunately, the value of + * XTHAL_INTTYPE_UNCONFIGURED is not zero): */ +#if XCHAL_NUM_INTERRUPTS == 0 +# define XCHAL_INT0_LEVEL 0 +# define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 1 +# define XCHAL_INT1_LEVEL 0 +# define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 2 +# define XCHAL_INT2_LEVEL 0 +# define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 3 +# define XCHAL_INT3_LEVEL 0 +# define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 4 +# define XCHAL_INT4_LEVEL 0 +# define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 5 +# define XCHAL_INT5_LEVEL 0 +# define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 6 +# define XCHAL_INT6_LEVEL 0 +# define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 7 +# define XCHAL_INT7_LEVEL 0 +# define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 8 +# define XCHAL_INT8_LEVEL 0 +# define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 9 +# define XCHAL_INT9_LEVEL 0 +# define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 10 +# define XCHAL_INT10_LEVEL 0 +# define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 11 +# define XCHAL_INT11_LEVEL 0 +# define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 12 +# define XCHAL_INT12_LEVEL 0 +# define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 13 +# define XCHAL_INT13_LEVEL 0 +# define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 14 +# define XCHAL_INT14_LEVEL 0 +# define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 15 +# define XCHAL_INT15_LEVEL 0 +# define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 16 +# define XCHAL_INT16_LEVEL 0 +# define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 17 +# define XCHAL_INT17_LEVEL 0 +# define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 18 +# define XCHAL_INT18_LEVEL 0 +# define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 19 +# define XCHAL_INT19_LEVEL 0 +# define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 20 +# define XCHAL_INT20_LEVEL 0 +# define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 21 +# define XCHAL_INT21_LEVEL 0 +# define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 22 +# define XCHAL_INT22_LEVEL 0 +# define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 23 +# define XCHAL_INT23_LEVEL 0 +# define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 24 +# define XCHAL_INT24_LEVEL 0 +# define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 25 +# define XCHAL_INT25_LEVEL 0 +# define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 26 +# define XCHAL_INT26_LEVEL 0 +# define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 27 +# define XCHAL_INT27_LEVEL 0 +# define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 28 +# define XCHAL_INT28_LEVEL 0 +# define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 29 +# define XCHAL_INT29_LEVEL 0 +# define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 30 +# define XCHAL_INT30_LEVEL 0 +# define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif +#if XCHAL_NUM_INTERRUPTS <= 31 +# define XCHAL_INT31_LEVEL 0 +# define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED +#endif + + +/* + * Masks and levels corresponding to each *external* interrupt. + */ + +#define XCHAL_EXTINT0_MASK (1 << XCHAL_EXTINT0_NUM) +#define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM) +#define XCHAL_EXTINT1_MASK (1 << XCHAL_EXTINT1_NUM) +#define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM) +#define XCHAL_EXTINT2_MASK (1 << XCHAL_EXTINT2_NUM) +#define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM) +#define XCHAL_EXTINT3_MASK (1 << XCHAL_EXTINT3_NUM) +#define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM) +#define XCHAL_EXTINT4_MASK (1 << XCHAL_EXTINT4_NUM) +#define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM) +#define XCHAL_EXTINT5_MASK (1 << XCHAL_EXTINT5_NUM) +#define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM) +#define XCHAL_EXTINT6_MASK (1 << XCHAL_EXTINT6_NUM) +#define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM) +#define XCHAL_EXTINT7_MASK (1 << XCHAL_EXTINT7_NUM) +#define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM) +#define XCHAL_EXTINT8_MASK (1 << XCHAL_EXTINT8_NUM) +#define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM) +#define XCHAL_EXTINT9_MASK (1 << XCHAL_EXTINT9_NUM) +#define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM) +#define XCHAL_EXTINT10_MASK (1 << XCHAL_EXTINT10_NUM) +#define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM) +#define XCHAL_EXTINT11_MASK (1 << XCHAL_EXTINT11_NUM) +#define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM) +#define XCHAL_EXTINT12_MASK (1 << XCHAL_EXTINT12_NUM) +#define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM) +#define XCHAL_EXTINT13_MASK (1 << XCHAL_EXTINT13_NUM) +#define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM) +#define XCHAL_EXTINT14_MASK (1 << XCHAL_EXTINT14_NUM) +#define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM) +#define XCHAL_EXTINT15_MASK (1 << XCHAL_EXTINT15_NUM) +#define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM) +#define XCHAL_EXTINT16_MASK (1 << XCHAL_EXTINT16_NUM) +#define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM) +#define XCHAL_EXTINT17_MASK (1 << XCHAL_EXTINT17_NUM) +#define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM) +#define XCHAL_EXTINT18_MASK (1 << XCHAL_EXTINT18_NUM) +#define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM) +#define XCHAL_EXTINT19_MASK (1 << XCHAL_EXTINT19_NUM) +#define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM) +#define XCHAL_EXTINT20_MASK (1 << XCHAL_EXTINT20_NUM) +#define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM) +#define XCHAL_EXTINT21_MASK (1 << XCHAL_EXTINT21_NUM) +#define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM) +#define XCHAL_EXTINT22_MASK (1 << XCHAL_EXTINT22_NUM) +#define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM) +#define XCHAL_EXTINT23_MASK (1 << XCHAL_EXTINT23_NUM) +#define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM) +#define XCHAL_EXTINT24_MASK (1 << XCHAL_EXTINT24_NUM) +#define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM) +#define XCHAL_EXTINT25_MASK (1 << XCHAL_EXTINT25_NUM) +#define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM) +#define XCHAL_EXTINT26_MASK (1 << XCHAL_EXTINT26_NUM) +#define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM) +#define XCHAL_EXTINT27_MASK (1 << XCHAL_EXTINT27_NUM) +#define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM) +#define XCHAL_EXTINT28_MASK (1 << XCHAL_EXTINT28_NUM) +#define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM) +#define XCHAL_EXTINT29_MASK (1 << XCHAL_EXTINT29_NUM) +#define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM) +#define XCHAL_EXTINT30_MASK (1 << XCHAL_EXTINT30_NUM) +#define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM) +#define XCHAL_EXTINT31_MASK (1 << XCHAL_EXTINT31_NUM) +#define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM) + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +/* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */ +#define XCHAL_HAVE_OLD_EXC_ARCH XCHAL_HAVE_XEA1 /* (DEPRECATED) 1 if old exception architecture (XEA1), 0 otherwise (eg. XEA2) */ +#define XCHAL_HAVE_EXCM XCHAL_HAVE_XEA2 /* (DEPRECATED) 1 if PS.EXCM bit exists (currently equals XCHAL_HAVE_TLBS) */ +#ifdef XCHAL_USER_VECTOR_VADDR +#define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR +#define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR +#endif +#ifdef XCHAL_USER_VECTOR_PADDR +# define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR +# define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR +#endif +#ifdef XCHAL_KERNEL_VECTOR_VADDR +# define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR +# define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR +#endif +#ifdef XCHAL_KERNEL_VECTOR_PADDR +# define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR +# define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR +#endif + +#if 0 +#if XCHAL_HAVE_DEBUG +# define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) +/* This one should only get defined if the corresponding intlevel paddr macro exists: */ +# define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL_VECTOR_PADDR(XCHAL_DEBUGLEVEL) +#endif +#endif + +/* Indexing macros: */ +#define _XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR +#define XCHAL_INTLEVEL_VECTOR_VADDR(n) _XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */ + +/* + * General Exception Causes + * (values of EXCCAUSE special register set by general exceptions, + * which vector to the user, kernel, or double-exception vectors). + * + * DEPRECATED. Please use the equivalent EXCCAUSE_xxx macros + * defined in . (Note that these have slightly + * different names, they don't just have the XCHAL_ prefix removed.) + */ +#define XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION 0 /* Illegal Instruction */ +#define XCHAL_EXCCAUSE_SYSTEM_CALL 1 /* System Call */ +#define XCHAL_EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 /* Instruction Fetch Error */ +#define XCHAL_EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ +#define XCHAL_EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ +#define XCHAL_EXCCAUSE_ALLOCA 5 /* Stack Extension Assist */ +#define XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ +#define XCHAL_EXCCAUSE_SPECULATION 7 /* Speculation */ +#define XCHAL_EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ +#define XCHAL_EXCCAUSE_UNALIGNED 9 /* Unaligned Load Store */ +/*10..15 reserved*/ +#define XCHAL_EXCCAUSE_ITLB_MISS 16 /* ITlb Miss Exception */ +#define XCHAL_EXCCAUSE_ITLB_MULTIHIT 17 /* ITlb Mutltihit Exception */ +#define XCHAL_EXCCAUSE_ITLB_PRIVILEGE 18 /* ITlb Privilege Exception */ +#define XCHAL_EXCCAUSE_ITLB_SIZE_RESTRICTION 19 /* ITlb Size Restriction Exception */ +#define XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 /* Fetch Cache Attribute Exception */ +/*21..23 reserved*/ +#define XCHAL_EXCCAUSE_DTLB_MISS 24 /* DTlb Miss Exception */ +#define XCHAL_EXCCAUSE_DTLB_MULTIHIT 25 /* DTlb Multihit Exception */ +#define XCHAL_EXCCAUSE_DTLB_PRIVILEGE 26 /* DTlb Privilege Exception */ +#define XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION 27 /* DTlb Size Restriction Exception */ +#define XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 /* Load Cache Attribute Exception */ +#define XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 /* Store Cache Attribute Exception */ +/*30..31 reserved*/ +#define XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED 32 /* Coprocessor 0 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR1_DISABLED 33 /* Coprocessor 1 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR2_DISABLED 34 /* Coprocessor 2 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR3_DISABLED 35 /* Coprocessor 3 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR4_DISABLED 36 /* Coprocessor 4 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR5_DISABLED 37 /* Coprocessor 5 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR6_DISABLED 38 /* Coprocessor 6 disabled */ +#define XCHAL_EXCCAUSE_COPROCESSOR7_DISABLED 39 /* Coprocessor 7 disabled */ +#define XCHAL_EXCCAUSE_FLOATING_POINT 40 /* Floating Point Exception */ +/*40..63 reserved*/ + + +/* + * Miscellaneous special register fields. + * + * For each special register, and each field within each register: + * XCHAL__VALIDMASK is the set of bits defined in the register. + * XCHAL___BITS is the number of bits in the field. + * XCHAL___NUM is 2^bits, the number of possible values + * of the field. + * XCHAL___SHIFT is the position of the field within + * the register, starting from the least significant bit. + * + * DEPRECATED. Please use the equivalent macros defined in + * . (Note that these have different names.) + */ + +/* DBREAKC (special register number 160): */ +#define XCHAL_DBREAKC_VALIDMASK 0xC000003F +#define XCHAL_DBREAKC_MASK_BITS 6 +#define XCHAL_DBREAKC_MASK_NUM 64 +#define XCHAL_DBREAKC_MASK_SHIFT 0 +#define XCHAL_DBREAKC_MASK_MASK 0x0000003F +#define XCHAL_DBREAKC_LOADBREAK_BITS 1 +#define XCHAL_DBREAKC_LOADBREAK_NUM 2 +#define XCHAL_DBREAKC_LOADBREAK_SHIFT 30 +#define XCHAL_DBREAKC_LOADBREAK_MASK 0x40000000 +#define XCHAL_DBREAKC_STOREBREAK_BITS 1 +#define XCHAL_DBREAKC_STOREBREAK_NUM 2 +#define XCHAL_DBREAKC_STOREBREAK_SHIFT 31 +#define XCHAL_DBREAKC_STOREBREAK_MASK 0x80000000 +/* PS (special register number 230): */ +#define XCHAL_PS_VALIDMASK 0x00070F3F +#define XCHAL_PS_INTLEVEL_BITS 4 +#define XCHAL_PS_INTLEVEL_NUM 16 +#define XCHAL_PS_INTLEVEL_SHIFT 0 +#define XCHAL_PS_INTLEVEL_MASK 0x0000000F +#define XCHAL_PS_EXCM_BITS 1 +#define XCHAL_PS_EXCM_NUM 2 +#define XCHAL_PS_EXCM_SHIFT 4 +#define XCHAL_PS_EXCM_MASK 0x00000010 +#define XCHAL_PS_UM_BITS 1 +#define XCHAL_PS_UM_NUM 2 +#define XCHAL_PS_UM_SHIFT 5 +#define XCHAL_PS_UM_MASK 0x00000020 +#define XCHAL_PS_RING_BITS 2 +#define XCHAL_PS_RING_NUM 4 +#define XCHAL_PS_RING_SHIFT 6 +#define XCHAL_PS_RING_MASK 0x000000C0 +#define XCHAL_PS_OWB_BITS 4 +#define XCHAL_PS_OWB_NUM 16 +#define XCHAL_PS_OWB_SHIFT 8 +#define XCHAL_PS_OWB_MASK 0x00000F00 +#define XCHAL_PS_CALLINC_BITS 2 +#define XCHAL_PS_CALLINC_NUM 4 +#define XCHAL_PS_CALLINC_SHIFT 16 +#define XCHAL_PS_CALLINC_MASK 0x00030000 +#define XCHAL_PS_WOE_BITS 1 +#define XCHAL_PS_WOE_NUM 2 +#define XCHAL_PS_WOE_SHIFT 18 +#define XCHAL_PS_WOE_MASK 0x00040000 +/* EXCCAUSE (special register number 232): */ +#define XCHAL_EXCCAUSE_VALIDMASK 0x0000003F +#define XCHAL_EXCCAUSE_BITS 6 +#define XCHAL_EXCCAUSE_NUM 64 +#define XCHAL_EXCCAUSE_SHIFT 0 +#define XCHAL_EXCCAUSE_MASK 0x0000003F +/* DEBUGCAUSE (special register number 233): */ +#define XCHAL_DEBUGCAUSE_VALIDMASK 0x0000003F +#define XCHAL_DEBUGCAUSE_ICOUNT_BITS 1 +#define XCHAL_DEBUGCAUSE_ICOUNT_NUM 2 +#define XCHAL_DEBUGCAUSE_ICOUNT_SHIFT 0 +#define XCHAL_DEBUGCAUSE_ICOUNT_MASK 0x00000001 +#define XCHAL_DEBUGCAUSE_IBREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_IBREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_IBREAK_SHIFT 1 +#define XCHAL_DEBUGCAUSE_IBREAK_MASK 0x00000002 +#define XCHAL_DEBUGCAUSE_DBREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_DBREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_DBREAK_SHIFT 2 +#define XCHAL_DEBUGCAUSE_DBREAK_MASK 0x00000004 +#define XCHAL_DEBUGCAUSE_BREAK_BITS 1 +#define XCHAL_DEBUGCAUSE_BREAK_NUM 2 +#define XCHAL_DEBUGCAUSE_BREAK_SHIFT 3 +#define XCHAL_DEBUGCAUSE_BREAK_MASK 0x00000008 +#define XCHAL_DEBUGCAUSE_BREAKN_BITS 1 +#define XCHAL_DEBUGCAUSE_BREAKN_NUM 2 +#define XCHAL_DEBUGCAUSE_BREAKN_SHIFT 4 +#define XCHAL_DEBUGCAUSE_BREAKN_MASK 0x00000010 +#define XCHAL_DEBUGCAUSE_DEBUGINT_BITS 1 +#define XCHAL_DEBUGCAUSE_DEBUGINT_NUM 2 +#define XCHAL_DEBUGCAUSE_DEBUGINT_SHIFT 5 +#define XCHAL_DEBUGCAUSE_DEBUGINT_MASK 0x00000020 + + + + +/*---------------------------------------------------------------------- + TIMERS + ----------------------------------------------------------------------*/ + +/*#define XCHAL_HAVE_TIMERS XCHAL_HAVE_CCOUNT*/ + + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_IROM XCHAL_NUM_INSTROM /* (DEPRECATED) */ +#define XCHAL_NUM_IRAM XCHAL_NUM_INSTRAM /* (DEPRECATED) */ +#define XCHAL_NUM_DROM XCHAL_NUM_DATAROM /* (DEPRECATED) */ +#define XCHAL_NUM_DRAM XCHAL_NUM_DATARAM /* (DEPRECATED) */ + +#define XCHAL_IROM0_VADDR XCHAL_INSTROM0_VADDR /* (DEPRECATED) */ +#define XCHAL_IROM0_PADDR XCHAL_INSTROM0_PADDR /* (DEPRECATED) */ +#define XCHAL_IROM0_SIZE XCHAL_INSTROM0_SIZE /* (DEPRECATED) */ +#define XCHAL_IROM1_VADDR XCHAL_INSTROM1_VADDR /* (DEPRECATED) */ +#define XCHAL_IROM1_PADDR XCHAL_INSTROM1_PADDR /* (DEPRECATED) */ +#define XCHAL_IROM1_SIZE XCHAL_INSTROM1_SIZE /* (DEPRECATED) */ +#define XCHAL_IRAM0_VADDR XCHAL_INSTRAM0_VADDR /* (DEPRECATED) */ +#define XCHAL_IRAM0_PADDR XCHAL_INSTRAM0_PADDR /* (DEPRECATED) */ +#define XCHAL_IRAM0_SIZE XCHAL_INSTRAM0_SIZE /* (DEPRECATED) */ +#define XCHAL_IRAM1_VADDR XCHAL_INSTRAM1_VADDR /* (DEPRECATED) */ +#define XCHAL_IRAM1_PADDR XCHAL_INSTRAM1_PADDR /* (DEPRECATED) */ +#define XCHAL_IRAM1_SIZE XCHAL_INSTRAM1_SIZE /* (DEPRECATED) */ +#define XCHAL_DROM0_VADDR XCHAL_DATAROM0_VADDR /* (DEPRECATED) */ +#define XCHAL_DROM0_PADDR XCHAL_DATAROM0_PADDR /* (DEPRECATED) */ +#define XCHAL_DROM0_SIZE XCHAL_DATAROM0_SIZE /* (DEPRECATED) */ +#define XCHAL_DROM1_VADDR XCHAL_DATAROM1_VADDR /* (DEPRECATED) */ +#define XCHAL_DROM1_PADDR XCHAL_DATAROM1_PADDR /* (DEPRECATED) */ +#define XCHAL_DROM1_SIZE XCHAL_DATAROM1_SIZE /* (DEPRECATED) */ +#define XCHAL_DRAM0_VADDR XCHAL_DATARAM0_VADDR /* (DEPRECATED) */ +#define XCHAL_DRAM0_PADDR XCHAL_DATARAM0_PADDR /* (DEPRECATED) */ +#define XCHAL_DRAM0_SIZE XCHAL_DATARAM0_SIZE /* (DEPRECATED) */ +#define XCHAL_DRAM1_VADDR XCHAL_DATARAM1_VADDR /* (DEPRECATED) */ +#define XCHAL_DRAM1_PADDR XCHAL_DATARAM1_PADDR /* (DEPRECATED) */ +#define XCHAL_DRAM1_SIZE XCHAL_DATARAM1_SIZE /* (DEPRECATED) */ + + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + + +/* Max for both I-cache and D-cache (used for general alignment): */ +#if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE +# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH +# define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE +#else +# define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH +# define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE +#endif + +#define XCHAL_ICACHE_SETSIZE (1< XCHAL_DCACHE_SETWIDTH +# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH +# define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE +#else +# define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH +# define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE +#endif + +/* Instruction cache tag bits: */ +#define XCHAL_ICACHE_TAG_V_SHIFT 0 +#define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */ +#if XCHAL_ICACHE_WAYS > 1 +# define XCHAL_ICACHE_TAG_F_SHIFT 1 +# define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */ +#else +# define XCHAL_ICACHE_TAG_F_SHIFT 0 +# define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */ +#endif +#if XCHAL_ICACHE_LINE_LOCKABLE +# define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1) +# define XCHAL_ICACHE_TAG_L (1 << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */ +#else +# define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT +# define XCHAL_ICACHE_TAG_L 0 /* no lock bit */ +#endif +/* Data cache tag bits: */ +#define XCHAL_DCACHE_TAG_V_SHIFT 0 +#define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */ +#if XCHAL_DCACHE_WAYS > 1 +# define XCHAL_DCACHE_TAG_F_SHIFT 1 +# define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */ +#else +# define XCHAL_DCACHE_TAG_F_SHIFT 0 +# define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */ +#endif +#if XCHAL_DCACHE_IS_WRITEBACK +# define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1) +# define XCHAL_DCACHE_TAG_D (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */ +#else +# define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT +# define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */ +#endif +#if XCHAL_DCACHE_LINE_LOCKABLE +# define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1) +# define XCHAL_DCACHE_TAG_L (1 << XCHAL_DCACHE_TAG_D_SHIFT) /* lock bit */ +#else +# define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT +# define XCHAL_DCACHE_TAG_L 0 /* no lock bit */ +#endif + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See for more details. */ + +#define XCHAL_HAVE_MMU XCHAL_HAVE_TLBS /* (DEPRECATED; use XCHAL_HAVE_TLBS instead; will be removed in future release) */ + +/* Indexing macros: */ +#define _XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what +#define XCHAL_ITLB_SET(n,what) _XCHAL_ITLB_SET(n, _ ## what ) +#define _XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what +#define XCHAL_ITLB_SET_E(n,i,what) _XCHAL_ITLB_SET_E(n,i, _ ## what ) +#define _XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what +#define XCHAL_DTLB_SET(n,what) _XCHAL_DTLB_SET(n, _ ## what ) +#define _XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what +#define XCHAL_DTLB_SET_E(n,i,what) _XCHAL_DTLB_SET_E(n,i, _ ## what ) +/* + * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES) + * to get the value of XCHAL_ITLB_SET_ENTRIES where is the first auto-refill set. + */ + +/* Number of entries per autorefill way: */ +#define XCHAL_ITLB_ARF_ENTRIES (1< 0 && XCHAL_DTLB_ARF_WAYS > 0 && XCHAL_MMU_RINGS >= 2 +# define XCHAL_HAVE_PTP_MMU 1 /* have full MMU (with page table [autorefill] and protection) */ +#else +# define XCHAL_HAVE_PTP_MMU 0 /* don't have full MMU */ +#endif +#endif + +/* + * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings: + */ +#if XCHAL_HAVE_PTP_MMU +#define XCHAL_KSEG_CACHED_VADDR 0xD0000000 /* virt.addr of kernel RAM cached static map */ +#define XCHAL_KSEG_CACHED_PADDR 0x00000000 /* phys.addr of kseg_cached */ +#define XCHAL_KSEG_CACHED_SIZE 0x08000000 /* size in bytes of kseg_cached (assumed power of 2!!!) */ +#define XCHAL_KSEG_BYPASS_VADDR 0xD8000000 /* virt.addr of kernel RAM bypass (uncached) static map */ +#define XCHAL_KSEG_BYPASS_PADDR 0x00000000 /* phys.addr of kseg_bypass */ +#define XCHAL_KSEG_BYPASS_SIZE 0x08000000 /* size in bytes of kseg_bypass (assumed power of 2!!!) */ + +#define XCHAL_KIO_CACHED_VADDR 0xE0000000 /* virt.addr of kernel I/O cached static map */ +#define XCHAL_KIO_CACHED_PADDR 0xF0000000 /* phys.addr of kio_cached */ +#define XCHAL_KIO_CACHED_SIZE 0x10000000 /* size in bytes of kio_cached (assumed power of 2!!!) */ +#define XCHAL_KIO_BYPASS_VADDR 0xF0000000 /* virt.addr of kernel I/O bypass (uncached) static map */ +#define XCHAL_KIO_BYPASS_PADDR 0xF0000000 /* phys.addr of kio_bypass */ +#define XCHAL_KIO_BYPASS_SIZE 0x10000000 /* size in bytes of kio_bypass (assumed power of 2!!!) */ + +#define XCHAL_SEG_MAPPABLE_VADDR 0x00000000 /* start of largest non-static-mapped virtual addr area */ +#define XCHAL_SEG_MAPPABLE_SIZE 0xD0000000 /* size in bytes of " */ +/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */ +#endif + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +/* Data alignment required if used for instructions: */ +#if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH +# define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH +#else +# define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH +#endif + +/* + * Names kept for backward compatibility. + * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases + * under which they are released. In the T10##.# era there was no distinction.) + */ +#define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR +#define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR +#define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME + + + + +/*---------------------------------------------------------------------- + COPROCESSORS and EXTRA STATE + ----------------------------------------------------------------------*/ + +#define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE +#define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN +#define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE +#define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN + +#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) + +#define xchal_extratie_load xchal_ncptie_load +#define xchal_extratie_store xchal_ncptie_store +#define xchal_extratie_load_a2 xchal_ncptie_load_a2 +#define xchal_extratie_store_a2 xchal_ncptie_store_a2 +#define xchal_extra_load xchal_ncp_load +#define xchal_extra_store xchal_ncp_store +#define xchal_extra_load_a2 xchal_ncp_load_a2 +#define xchal_extra_store_a2 xchal_ncp_store_a2 +#define xchal_extra_load_funcbody xchal_ncp_load_a2 +#define xchal_extra_store_funcbody xchal_ncp_store_a2 + +/* Empty placeholder macros for undefined coprocessors: */ +# ifndef XCHAL_CP0_NAME +# define xchal_cp0_store_a2 xchal_cp0_store a2, a3 +# define xchal_cp0_load_a2 xchal_cp0_load a2, a3 + .macro xchal_cp0_store ptr tmp + .endm + .macro xchal_cp0_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP1_NAME +# define xchal_cp1_store_a2 xchal_cp1_store a2, a3 +# define xchal_cp1_load_a2 xchal_cp1_load a2, a3 + .macro xchal_cp1_store ptr tmp + .endm + .macro xchal_cp1_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP2_NAME +# define xchal_cp2_store_a2 xchal_cp2_store a2, a3 +# define xchal_cp2_load_a2 xchal_cp2_load a2, a3 + .macro xchal_cp2_store ptr tmp + .endm + .macro xchal_cp2_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP3_NAME +# define xchal_cp3_store_a2 xchal_cp3_store a2, a3 +# define xchal_cp3_load_a2 xchal_cp3_load a2, a3 + .macro xchal_cp3_store ptr tmp + .endm + .macro xchal_cp3_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP4_NAME +# define xchal_cp4_store_a2 xchal_cp4_store a2, a3 +# define xchal_cp4_load_a2 xchal_cp4_load a2, a3 + .macro xchal_cp4_store ptr tmp + .endm + .macro xchal_cp4_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP5_NAME +# define xchal_cp5_store_a2 xchal_cp5_store a2, a3 +# define xchal_cp5_load_a2 xchal_cp5_load a2, a3 + .macro xchal_cp5_store ptr tmp + .endm + .macro xchal_cp5_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP6_NAME +# define xchal_cp6_store_a2 xchal_cp6_store a2, a3 +# define xchal_cp6_load_a2 xchal_cp6_load a2, a3 + .macro xchal_cp6_store ptr tmp + .endm + .macro xchal_cp6_load ptr tmp + .endm +# endif +# ifndef XCHAL_CP7_NAME +# define xchal_cp7_store_a2 xchal_cp7_store a2, a3 +# define xchal_cp7_load_a2 xchal_cp7_load a2, a3 + .macro xchal_cp7_store ptr tmp + .endm + .macro xchal_cp7_load ptr tmp + .endm +# endif + + /******************** + * Macros to create functions that save and restore the state of *any* TIE + * coprocessor (by dynamic index). + */ + + /* + * Macro that expands to the body of a function + * that stores the selected coprocessor's state (registers etc). + * Entry: a2 = ptr to save area in which to save cp state + * a3 = coprocessor number + * Exit: any register a2-a15 (?) may have been clobbered. + */ + .macro xchal_cpi_store_funcbody +# ifdef XCHAL_CP0_NAME + bnez a3, 99f + xchal_cp0_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP1_NAME + bnei a3, 1, 99f + xchal_cp1_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP2_NAME + bnei a3, 2, 99f + xchal_cp2_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP3_NAME + bnei a3, 3, 99f + xchal_cp3_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP4_NAME + bnei a3, 4, 99f + xchal_cp4_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP5_NAME + bnei a3, 5, 99f + xchal_cp5_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP6_NAME + bnei a3, 6, 99f + xchal_cp6_store_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP7_NAME + bnei a3, 7, 99f + xchal_cp7_store_a2 + j 90f +99: +# endif +90: + .endm + + /* + * Macro that expands to the body of a function + * that loads the selected coprocessor's state (registers etc). + * Entry: a2 = ptr to save area from which to restore cp state + * a3 = coprocessor number + * Exit: any register a2-a15 (?) may have been clobbered. + */ + .macro xchal_cpi_load_funcbody +# ifdef XCHAL_CP0_NAME + bnez a3, 99f + xchal_cp0_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP1_NAME + bnei a3, 1, 99f + xchal_cp1_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP2_NAME + bnei a3, 2, 99f + xchal_cp2_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP3_NAME + bnei a3, 3, 99f + xchal_cp3_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP4_NAME + bnei a3, 4, 99f + xchal_cp4_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP5_NAME + bnei a3, 5, 99f + xchal_cp5_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP6_NAME + bnei a3, 6, 99f + xchal_cp6_load_a2 + j 90f +99: +# endif +# ifdef XCHAL_CP7_NAME + bnei a3, 7, 99f + xchal_cp7_load_a2 + j 90f +99: +# endif +90: + .endm + +#endif /*_ASMLANGUAGE or __ASSEMBLER__*/ + + +/* Other default macros for undefined coprocessors: */ +#ifndef XCHAL_CP0_NAME +# define XCHAL_CP0_SA_SIZE 0 +# define XCHAL_CP0_SA_ALIGN 1 +# define XCHAL_CP0_NAME 0 +# define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP1_NAME +# define XCHAL_CP1_SA_SIZE 0 +# define XCHAL_CP1_SA_ALIGN 1 +# define XCHAL_CP1_NAME 0 +# define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP2_NAME +# define XCHAL_CP2_SA_SIZE 0 +# define XCHAL_CP2_SA_ALIGN 1 +# define XCHAL_CP2_NAME 0 +# define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP3_NAME +# define XCHAL_CP3_SA_SIZE 0 +# define XCHAL_CP3_SA_ALIGN 1 +# define XCHAL_CP3_NAME 0 +# define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP4_NAME +# define XCHAL_CP4_SA_SIZE 0 +# define XCHAL_CP4_SA_ALIGN 1 +# define XCHAL_CP4_NAME 0 +# define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP5_NAME +# define XCHAL_CP5_SA_SIZE 0 +# define XCHAL_CP5_SA_ALIGN 1 +# define XCHAL_CP5_NAME 0 +# define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP6_NAME +# define XCHAL_CP6_SA_SIZE 0 +# define XCHAL_CP6_SA_ALIGN 1 +# define XCHAL_CP6_NAME 0 +# define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */ +#endif +#ifndef XCHAL_CP7_NAME +# define XCHAL_CP7_SA_SIZE 0 +# define XCHAL_CP7_SA_ALIGN 1 +# define XCHAL_CP7_NAME 0 +# define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0 +# define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */ +#endif + +/* Indexing macros: */ +#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE +#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */ +#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN +#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */ + +#define XCHAL_CPEXTRA_SA_SIZE_TOR2 XCHAL_CPEXTRA_SA_SIZE /* Tor2Beta only - do not use */ + +/* Link-time HAL global variables that report coprocessor numbers by name + (names are case-preserved from the original TIE): */ +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +# define _XCJOIN(a,b) a ## b +# define XCJOIN(a,b) _XCJOIN(a,b) +# ifdef XCHAL_CP0_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT); +# endif +# ifdef XCHAL_CP1_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT); +# endif +# ifdef XCHAL_CP2_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT); +# endif +# ifdef XCHAL_CP3_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT); +# endif +# ifdef XCHAL_CP4_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT); +# endif +# ifdef XCHAL_CP5_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT); +# endif +# ifdef XCHAL_CP6_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT); +# endif +# ifdef XCHAL_CP7_NAME +extern const unsigned char XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT); +extern const unsigned int XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT); +# endif +#endif + + + + +/*---------------------------------------------------------------------- + DERIVED + ----------------------------------------------------------------------*/ + +#if XCHAL_HAVE_BE +#define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */ +#define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */ +#define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */ +#else +#define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */ +#define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */ +#define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */ +#endif +/* Belongs in xtensa/hal.h: */ +#define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */ + + +/* + * Because information as to exactly which hardware version is targeted + * by a given software build is not always available, compile-time HAL + * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE): + * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases + * under which they are released. In the T10##.# era there was no distinction.) + */ +#if XCHAL_HW_CONFIGID_RELIABLE +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0) +#else +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \ + : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \ + : XTHAL_MAYBE ) +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ + : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \ + : XTHAL_MAYBE ) +# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \ + ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) +#endif + +/* + * Specific errata: + */ + +/* + * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1; + * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled): + */ +#define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \ + (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \ + || XCHAL_HW_RELEASE_AT(1050,0))) + + + +#endif /*XTENSA_CONFIG_CORE_H*/ diff --git a/toolchain/inst/xtensa-elf/include/xtensa/corebits.h b/toolchain/inst/xtensa-elf/include/xtensa/corebits.h new file mode 100644 index 0000000..9fbb994 --- /dev/null +++ b/toolchain/inst/xtensa-elf/include/xtensa/corebits.h @@ -0,0 +1,149 @@ +/* + * xtensa/corebits.h - Xtensa Special Register field positions, masks, values. + * + * (In previous releases, these were defined in specreg.h, a generated file. + * This file is not generated, ie. it is processor configuration independent.) + */ + +/* $Id: //depot/rel/BadgerPass/Xtensa/OS/include/xtensa/corebits.h#3 $ */ + +/* + * Copyright (c) 2005-2007 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef XTENSA_COREBITS_H +#define XTENSA_COREBITS_H + +/* EXCCAUSE register fields: */ +#define EXCCAUSE_EXCCAUSE_SHIFT 0 +#define EXCCAUSE_EXCCAUSE_MASK 0x3F +/* EXCCAUSE register values: */ +/* + * General Exception Causes + * (values of EXCCAUSE special register set by general exceptions, + * which vector to the user, kernel, or double-exception vectors). + */ +#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */ +#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */ +#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */ +# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ +# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ +# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */ +#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */ +#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ +#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */ +#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */ +#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */ +/* Reserved 10..11 */ +#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */ +#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */ +#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */ +#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */ +#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */ +#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */ +/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */ +#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */ +/* Reserved 21..23 */ +#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */ +#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */ +#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */ +/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */ +#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */ +#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */ +/* Reserved 30..31 */ +#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */ +#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */ +#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */ +#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */ +#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */ +#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */ +#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */ +#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */ +#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */ +/*#define EXCCAUSE_FLOATING_POINT 40*/ /* Floating Point Exception (not implemented) */ +/* Reserved 40..63 */ + +/* PS register fields: */ +#define PS_WOE_SHIFT 18 +#define PS_WOE_MASK 0x00040000 +#define PS_WOE PS_WOE_MASK +#define PS_CALLINC_SHIFT 16 +#define PS_CALLINC_MASK 0x00030000 +#define PS_CALLINC(n) (((n)&3)<4) 0 2 or >3 (TBD) + * T1030.0 0 1 (HAL beta) + * T1030.{1,2} 0 3 Equivalent to first release. + * T1030.n (n>=3) 0 >= 3 (TBD) + * T1040.n 1040 n Full CHAL available from T1040.2 + * T1050.n 1050 n . + * 6.0.n 6000 n Xtensa Tools v6 (RA-200x.n) + * 7.0.n 7000 n Xtensa Tools v7 (RB-200x.n) + * 7.1.n 7010 n Xtensa Tools v7.1 (RB-200x.(n+2)) + * + * + * Note: there is a distinction between the software version with + * which something is compiled (accessible using XTHAL_RELEASE_* macros) + * and the software version with which the HAL library was compiled + * (accessible using Xthal_release_* global variables). This + * distinction is particularly relevant for vendors that distribute + * configuration-independent binaries (eg. an OS), where their customer + * might link it with a HAL of a different Xtensa software version. + * In this case, it may be appropriate for the OS to verify at run-time + * whether XTHAL_RELEASE_* and Xthal_release_* are compatible. + * [Guidelines as to which version is compatible with which are not + * currently provided explicitly, but might be inferred from reading + * OSKit documentation for all releases -- compatibility is also highly + * dependent on which HAL features are used. Each version is usually + * backward compatible, with very few exceptions if any.] + * + * Notes: + * Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only. + * Tornado 2.0.2 supported in T1040.2+, T1050, and 6.0. + * Compile-time HAL port of NucleusPlus supported by T1040.2 and later. + */ + +/* Version comparison operators (among major/minor pairs): */ +#define XTHAL_REL_GE(maja,mina, majb,minb) ((maja) > (majb) || \ + ((maja) == (majb) && (mina) >= (minb))) +#define XTHAL_REL_GT(maja,mina, majb,minb) ((maja) > (majb) || \ + ((maja) == (majb) && (mina) > (minb))) +#define XTHAL_REL_LE(maja,mina, majb,minb) ((maja) < (majb) || \ + ((maja) == (majb) && (mina) <= (minb))) +#define XTHAL_REL_LT(maja,mina, majb,minb) ((maja) < (majb) || \ + ((maja) == (majb) && (mina) < (minb))) +#define XTHAL_REL_EQ(maja,mina, majb,minb) ((maja) == (majb) && (mina) == (minb)) + +/* Fuzzy (3-way) logic operators: */ +#define XTHAL_MAYBE -1 /* 0=NO, 1=YES, -1=MAYBE */ +#define XTHAL_FUZZY_AND(a,b) (((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE) +#define XTHAL_FUZZY_OR(a,b) (((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE) +#define XTHAL_FUZZY_NOT(a) (((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE) + + +/* + * Architectural limit, independent of configuration: + */ +#define XTHAL_MAX_CPS 8 /* max number of coprocessors (0..7) */ + +/* Misc: */ +#define XTHAL_LITTLEENDIAN 0 +#define XTHAL_BIGENDIAN 1 + + + +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------------------------------------------------------------- + HAL + ----------------------------------------------------------------------*/ + +/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */ +extern const unsigned int Xthal_rev_no; + + +/*---------------------------------------------------------------------- + Optional/Custom Processor State + ----------------------------------------------------------------------*/ + +/* save & restore the extra processor state */ +extern void xthal_save_extra(void *base); +extern void xthal_restore_extra(void *base); + +extern void xthal_save_cpregs(void *base, int); +extern void xthal_restore_cpregs(void *base, int); +/* versions specific to each coprocessor id */ +extern void xthal_save_cp0(void *base); +extern void xthal_save_cp1(void *base); +extern void xthal_save_cp2(void *base); +extern void xthal_save_cp3(void *base); +extern void xthal_save_cp4(void *base); +extern void xthal_save_cp5(void *base); +extern void xthal_save_cp6(void *base); +extern void xthal_save_cp7(void *base); +extern void xthal_restore_cp0(void *base); +extern void xthal_restore_cp1(void *base); +extern void xthal_restore_cp2(void *base); +extern void xthal_restore_cp3(void *base); +extern void xthal_restore_cp4(void *base); +extern void xthal_restore_cp5(void *base); +extern void xthal_restore_cp6(void *base); +extern void xthal_restore_cp7(void *base); +/* pointers to each of the functions above */ +extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS]; +extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS]; +/* similarly for non-windowed ABI (may be same or different) */ +extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS]; +extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS]; + +/*extern void xthal_save_all_extra(void *base);*/ +/*extern void xthal_restore_all_extra(void *base);*/ + +/* space for processor state */ +extern const unsigned int Xthal_extra_size; +extern const unsigned int Xthal_extra_align; +extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS]; +extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS]; +extern const unsigned int Xthal_all_extra_size; +extern const unsigned int Xthal_all_extra_align; +/* coprocessor names */ +extern const char * const Xthal_cp_names[XTHAL_MAX_CPS]; + +/* initialize the extra processor */ +/*extern void xthal_init_extra(void);*/ +/* initialize the TIE coprocessor */ +/*extern void xthal_init_cp(int);*/ + +/* initialize the extra processor */ +extern void xthal_init_mem_extra(void *); +/* initialize the TIE coprocessor */ +extern void xthal_init_mem_cp(void *, int); + +/* the number of TIE coprocessors contiguous from zero (for Tor2) */ +extern const unsigned int Xthal_num_coprocessors; + +/* actual number of coprocessors */ +extern const unsigned char Xthal_cp_num; +/* index of highest numbered coprocessor, plus one */ +extern const unsigned char Xthal_cp_max; +/* index of highest allowed coprocessor number, per cfg, plus one */ +/*extern const unsigned char Xthal_cp_maxcfg;*/ +/* bitmask of which coprocessors are present */ +extern const unsigned int Xthal_cp_mask; + +/* read & write extra state register */ +/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/ +/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/ + +/* read & write a TIE coprocessor register */ +/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/ +/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/ + +/* return coprocessor number based on register */ +/*extern int xthal_which_cp(unsigned reg);*/ + + +/*---------------------------------------------------------------------- + Register Windows + ----------------------------------------------------------------------*/ + +/* number of registers in register window */ +extern const unsigned int Xthal_num_aregs; +extern const unsigned char Xthal_num_aregs_log2; + + +/*---------------------------------------------------------------------- + Cache + ----------------------------------------------------------------------*/ + +/* size of the cache lines in log2(bytes) */ +extern const unsigned char Xthal_icache_linewidth; +extern const unsigned char Xthal_dcache_linewidth; +/* size of the cache lines in bytes (2^linewidth) */ +extern const unsigned short Xthal_icache_linesize; +extern const unsigned short Xthal_dcache_linesize; + +/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */ +extern const unsigned int Xthal_icache_size; +extern const unsigned int Xthal_dcache_size; +/* cache features */ +extern const unsigned char Xthal_dcache_is_writeback; + +/* invalidate the caches */ +extern void xthal_icache_region_invalidate( void *addr, unsigned size ); +extern void xthal_dcache_region_invalidate( void *addr, unsigned size ); +extern void xthal_icache_line_invalidate(void *addr); +extern void xthal_dcache_line_invalidate(void *addr); +/* write dirty data back */ +extern void xthal_dcache_region_writeback( void *addr, unsigned size ); +extern void xthal_dcache_line_writeback(void *addr); +/* write dirty data back and invalidate */ +extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size ); +extern void xthal_dcache_line_writeback_inv(void *addr); + +/* sync icache and memory */ +extern void xthal_icache_sync( void ); +/* sync dcache and memory */ +extern void xthal_dcache_sync( void ); + + +/*---------------------------------------------------------------------- + Debug + ----------------------------------------------------------------------*/ + +/* 1 if debug option configured, 0 if not: */ +extern const int Xthal_debug_configured; + +/* Set (plant) and remove software breakpoint, both synchronizing cache: */ +extern unsigned int xthal_set_soft_break(void *addr); +extern void xthal_remove_soft_break(void *addr, unsigned int); + + +/*---------------------------------------------------------------------- + Disassembler + ----------------------------------------------------------------------*/ + +/* Max expected size of the return buffer for a disassembled instruction (hint only): */ +#define XTHAL_DISASM_BUFSIZE 80 + +/* Disassembly option bits for selecting what to return: */ +#define XTHAL_DISASM_OPT_ADDR 0x0001 /* display address */ +#define XTHAL_DISASM_OPT_OPHEX 0x0002 /* display opcode bytes in hex */ +#define XTHAL_DISASM_OPT_OPCODE 0x0004 /* display opcode name (mnemonic) */ +#define XTHAL_DISASM_OPT_PARMS 0x0008 /* display parameters */ +#define XTHAL_DISASM_OPT_ALL 0x0FFF /* display everything */ + +/* routine to get a string for the disassembled instruction */ +extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr, + char *buffer, unsigned buflen, unsigned options ); + +/* routine to get the size of the next instruction. Returns 0 for + illegal instruction */ +extern int xthal_disassemble_size( unsigned char *instr_buf ); + + +/*---------------------------------------------------------------------- + Instruction/Data RAM/ROM Access + ----------------------------------------------------------------------*/ + +extern void* xthal_memcpy(void *dst, const void *src, unsigned len); +extern void* xthal_bcopy(const void *src, void *dst, unsigned len); + + +/*---------------------------------------------------------------------- + MP Synchronization + ----------------------------------------------------------------------*/ + +extern int xthal_compare_and_set( int *addr, int test_val, int compare_val ); + +/*extern const char Xthal_have_s32c1i;*/ + + +/*---------------------------------------------------------------------- + Miscellaneous + ----------------------------------------------------------------------*/ + +extern const unsigned int Xthal_release_major; +extern const unsigned int Xthal_release_minor; +extern const char * const Xthal_release_name; +extern const char * const Xthal_release_internal; + +extern const unsigned char Xthal_memory_order; +extern const unsigned char Xthal_have_windowed; +extern const unsigned char Xthal_have_density; +extern const unsigned char Xthal_have_booleans; +extern const unsigned char Xthal_have_loops; +extern const unsigned char Xthal_have_nsa; +extern const unsigned char Xthal_have_minmax; +extern const unsigned char Xthal_have_sext; +extern const unsigned char Xthal_have_clamps; +extern const unsigned char Xthal_have_mac16; +extern const unsigned char Xthal_have_mul16; +extern const unsigned char Xthal_have_fp; +extern const unsigned char Xthal_have_speculation; +extern const unsigned char Xthal_have_threadptr; + +extern const unsigned char Xthal_have_pif; +extern const unsigned short Xthal_num_writebuffer_entries; + +extern const unsigned int Xthal_build_unique_id; +/* Version info for hardware targeted by software upgrades: */ +extern const unsigned int Xthal_hw_configid0; +extern const unsigned int Xthal_hw_configid1; +extern const unsigned int Xthal_hw_release_major; +extern const unsigned int Xthal_hw_release_minor; +extern const char * const Xthal_hw_release_name; +extern const char * const Xthal_hw_release_internal; + +#ifdef __cplusplus +} +#endif +#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ + + + + + +/**************************************************************************** + Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + Constant Definitions (shared with assembly) + ----------------------------------------------------------------------*/ + +/* + * Architectural limits, independent of configuration. + * Note that these are ISA-defined limits, not micro-architecture implementation + * limits enforced by the Xtensa Processor Generator (which may be stricter than + * these below). + */ +#define XTHAL_MAX_INTERRUPTS 32 /* max number of interrupts (0..31) */ +#define XTHAL_MAX_INTLEVELS 16 /* max number of interrupt levels (0..15) */ + /* (as of T1040, implementation limit is 7: 0..6) */ +#define XTHAL_MAX_TIMERS 4 /* max number of timers (CCOMPARE0..CCOMPARE3) */ + /* (as of T1040, implementation limit is 3: 0..2) */ + +/* Interrupt types: */ +#define XTHAL_INTTYPE_UNCONFIGURED 0 +#define XTHAL_INTTYPE_SOFTWARE 1 +#define XTHAL_INTTYPE_EXTERN_EDGE 2 +#define XTHAL_INTTYPE_EXTERN_LEVEL 3 +#define XTHAL_INTTYPE_TIMER 4 +#define XTHAL_INTTYPE_NMI 5 +#define XTHAL_INTTYPE_WRITE_ERROR 6 +#define XTHAL_MAX_INTTYPES 7 /* number of interrupt types */ + +/* Timer related: */ +#define XTHAL_TIMER_UNCONFIGURED -1 /* Xthal_timer_interrupt[] value for non-existent timers */ +#define XTHAL_TIMER_UNASSIGNED XTHAL_TIMER_UNCONFIGURED /* (for backwards compatibility only) */ + +/* Local Memory ECC/Parity: */ +#define XTHAL_MEMEP_PARITY 1 +#define XTHAL_MEMEP_ECC 2 +/* Flags parameter to xthal_memep_inject_error(): */ +#define XTHAL_MEMEP_F_LOCAL 0 /* local memory (default) */ +#define XTHAL_MEMEP_F_DCACHE_DATA 4 /* data cache data */ +#define XTHAL_MEMEP_F_DCACHE_TAG 5 /* data cache tag */ +#define XTHAL_MEMEP_F_ICACHE_DATA 6 /* instruction cache data */ +#define XTHAL_MEMEP_F_ICACHE_TAG 7 /* instruction cache tag */ +#define XTHAL_MEMEP_F_CORRECTABLE 16 /* inject correctable error + (default is non-corr.) */ + + +/* Access Mode bits (tentative): */ /* bit abbr unit short_name PPC equ - Description */ +#define XTHAL_AMB_EXCEPTION 0 /* 001 E EX fls: EXception none + exception on any access (aka "illegal") */ +#define XTHAL_AMB_HITCACHE 1 /* 002 C CH fls: use Cache on Hit ~(I CI) + [or H HC] way from tag match; + [or U UC] (ISA: same except Isolate case) */ +#define XTHAL_AMB_ALLOCATE 2 /* 004 A AL fl?: ALlocate none + [or F FI fill] refill cache on miss, way from LRU + (ISA: Read/Write Miss Refill) */ +#define XTHAL_AMB_WRITETHRU 3 /* 008 W WT --s: WriteThrough W WT + store immediately to memory (ISA: same) */ +#define XTHAL_AMB_ISOLATE 4 /* 010 I IS fls: ISolate none + use cache regardless of hit-vs-miss, + way from vaddr (ISA: use-cache-on-miss+hit) */ +#define XTHAL_AMB_GUARD 5 /* 020 G GU ?l?: GUard G * + non-speculative; spec/replay refs not permitted */ +#if 0 +#define XTHAL_AMB_COHERENT 6 /* 040 M MC ?ls: Mem/MP Coherent M + on read, other CPU/bus-master may need to supply data; + on write, maybe redirect to or flush other CPU dirty line; etc */ +#define XTHAL_AMB_ORDERED x /* 000 O OR fls: ORdered G * + mem accesses cannot be out of order */ +#define XTHAL_AMB_FUSEWRITES x /* 000 F FW --s: FuseWrites none + allow combining/merging multiple writes + (to same datapath data unit) into one + (implied by writeback) */ +#define XTHAL_AMB_TRUSTED x /* 000 T TR ?l?: TRusted none + memory will not bus error (if it does, + handle as fatal imprecise interrupt) */ +#define XTHAL_AMB_PREFETCH x /* 000 P PR fl?: PRefetch none + on refill, read line+1 into prefetch buffers */ +#define XTHAL_AMB_STREAM x /* 000 S ST ???: STreaming none + access one of N stream buffers */ +#endif /*0*/ + +#define XTHAL_AM_EXCEPTION (1< = bit is set + * '-' = bit is clear + * '.' = bit is irrelevant / don't care, as follows: + * E=1 makes all others irrelevant + * W,F relevant only for stores + * "2345" + * Indicates which Xtensa releases support the corresponding + * access mode. Releases for each character column are: + * 2 = prior to T1020.2: T1015 (V1.5), T1020.0, T1020.1 + * 3 = T1020.2 and later: T1020.2+, T1030 + * 4 = T1040 + * 5 = T1050 (maybe), LX1, LX2, LX2.1 + * 7 = LX2.2 + * And the character column contents are: + * = support by release(s) + * "." = unsupported by release(s) + * "?" = support unknown + */ + /* FOMGIWACE 23457 */ +/* For instruction fetch: */ +#define XTHAL_FAM_EXCEPTION 0x001 /* ........E 23457 exception */ +#define XTHAL_FAM_ISOLATE 0x012 /* .---I.-C- ..... isolate */ +#define XTHAL_FAM_BYPASS 0x000 /* .----.--- 23457 bypass */ +#define XTHAL_FAM_NACACHED 0x002 /* .----.-C- ..... cached no-allocate (frozen) */ +#define XTHAL_FAM_CACHED 0x006 /* .----.AC- 23457 cached */ +/* For data load: */ +#define XTHAL_LAM_EXCEPTION 0x001 /* ........E 23457 exception */ +#define XTHAL_LAM_ISOLATE 0x012 /* .---I.-C- 23457 isolate */ +#define XTHAL_LAM_BYPASS 0x000 /* .O---.--- 2.... bypass speculative */ +#define XTHAL_LAM_BYPASSG 0x020 /* .O-G-.--- .3457 bypass guarded */ +#define XTHAL_LAM_NACACHED 0x002 /* .O---.-C- 2.... cached no-allocate speculative */ +#define XTHAL_LAM_NACACHEDG 0x022 /* .O-G-.-C- .3457 cached no-allocate guarded */ +#define XTHAL_LAM_CACHED 0x006 /* .----.AC- 23457 cached speculative */ +#define XTHAL_LAM_CACHEDG 0x026 /* .?-G-.AC- ..... cached guarded */ +#define XTHAL_LAM_CACHEDM 0x046 /* .-M--.AC- ....7 cached MP-coherent (experimental) */ +/* For data store: */ +#define XTHAL_SAM_EXCEPTION 0x001 /* ........E 23457 exception */ +#define XTHAL_SAM_ISOLATE 0x032 /* .--GI--C- 23457 isolate */ +#define XTHAL_SAM_BYPASS 0x028 /* -O-G-W--- 23457 bypass */ +/*efine XTHAL_SAM_BYPASSF 0x028*/ /* F--G-W--- ..... bypass write-combined */ +#define XTHAL_SAM_WRITETHRU 0x02A /* -O-G-W-C- 23457 writethrough */ +/*efine XTHAL_SAM_WRITETHRUF 0x02A*/ /* F--G-W-C- ..... writethrough write-combined */ +#define XTHAL_SAM_WRITEALLOC 0x02E /* -O-G-WAC- ..... writethrough-allocate */ +/*efine XTHAL_SAM_WRITEALLOCF 0x02E*/ /* F--G-WAC- ..... writethrough-allocate write-combined */ +#define XTHAL_SAM_WRITEBACK 0x066 /* F-MG--AC- ...57 writeback (MP-coherent if configured) */ + +#if 0 +/* + Cache attribute encoding for CACHEATTR (per ISA): + (Note: if this differs from ISA Ref Manual, ISA has precedence) + + Inst-fetches Loads Stores + ------------- ------------ ------------- +0x0 FCA_EXCEPTION ?LCA_NACACHED_G* SCA_WRITETHRU "uncached" (cached no-allocate) +0x1 FCA_CACHED LCA_CACHED SCA_WRITETHRU cached +0x2 FCA_BYPASS LCA_BYPASS_G* SCA_BYPASS bypass +0x3 FCA_CACHED LCA_CACHED SCA_WRITEALLOCF write-allocate + or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) +0x4 FCA_CACHED LCA_CACHED SCA_WRITEBACK write-back + or LCA_EXCEPTION SCA_EXCEPTION (if unimplemented) +0x5..D FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION (reserved) +0xE FCA_EXCEPTION LCA_ISOLATE SCA_ISOLATE isolate +0xF FCA_EXCEPTION LCA_EXCEPTION SCA_EXCEPTION illegal + * Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G) +*/ +#endif /*0*/ + + +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +#ifdef __cplusplus +extern "C" { +#endif + + +/*---------------------------------------------------------------------- + Register Windows + ----------------------------------------------------------------------*/ + +/* This spill any live register windows (other than the caller's): + * (NOTE: current implementation require privileged code, but + * a user-callable implementation is possible.) */ +extern void xthal_window_spill( void ); + + +/*---------------------------------------------------------------------- + Optional/Custom Processor State + ----------------------------------------------------------------------*/ + +/* validate & invalidate the TIE register file */ +extern void xthal_validate_cp(int); +extern void xthal_invalidate_cp(int); + +/* read and write cpenable register */ +extern void xthal_set_cpenable(unsigned); +extern unsigned xthal_get_cpenable(void); + + +/*---------------------------------------------------------------------- + Interrupts + ----------------------------------------------------------------------*/ + +/* the number of interrupt levels */ +extern const unsigned char Xthal_num_intlevels; +/* the number of interrupts */ +extern const unsigned char Xthal_num_interrupts; + +/* mask for level of interrupts */ +extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS]; +/* mask for level 0 to N interrupts */ +extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS]; + +/* level of each interrupt */ +extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS]; + +/* type per interrupt */ +extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS]; + +/* masks of each type of interrupt */ +extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES]; + +/* interrupt numbers assigned to each timer interrupt */ +extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS]; + +/* INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions: */ +extern unsigned xthal_get_intenable( void ); +extern void xthal_set_intenable( unsigned ); +extern unsigned xthal_get_interrupt( void ); +#define xthal_get_intread xthal_get_interrupt /* backward compatibility */ +extern void xthal_set_intset( unsigned ); +extern void xthal_set_intclear( unsigned ); + + +/*---------------------------------------------------------------------- + Debug + ----------------------------------------------------------------------*/ + +/* Number of instruction and data break registers: */ +extern const int Xthal_num_ibreak; +extern const int Xthal_num_dbreak; + + +/*---------------------------------------------------------------------- + Core Counter + ----------------------------------------------------------------------*/ + +/* counter info */ +extern const unsigned char Xthal_have_ccount; /* set if CCOUNT register present */ +extern const unsigned char Xthal_num_ccompare; /* number of CCOMPAREn registers */ + +/* get CCOUNT register (if not present return 0) */ +extern unsigned xthal_get_ccount(void); + +/* set and get CCOMPAREn registers (if not present, get returns 0) */ +extern void xthal_set_ccompare(int, unsigned); +extern unsigned xthal_get_ccompare(int); + + +/*---------------------------------------------------------------------- + Miscellaneous + ----------------------------------------------------------------------*/ + +extern const unsigned char Xthal_have_prid; +extern const unsigned char Xthal_have_exceptions; +extern const unsigned char Xthal_xea_version; +extern const unsigned char Xthal_have_interrupts; +extern const unsigned char Xthal_have_highlevel_interrupts; +extern const unsigned char Xthal_have_nmi; + +extern unsigned xthal_get_prid( void ); + + +/*---------------------------------------------------------------------- + Virtual interrupt prioritization (DEPRECATED) + ----------------------------------------------------------------------*/ + +/* Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities: */ +extern unsigned xthal_vpri_to_intlevel(unsigned vpri); +extern unsigned xthal_intlevel_to_vpri(unsigned intlevel); + +/* Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints: */ +extern unsigned xthal_int_enable(unsigned); +extern unsigned xthal_int_disable(unsigned); + +/* Set/get virtual priority of an interrupt: */ +extern int xthal_set_int_vpri(int intnum, int vpri); +extern int xthal_get_int_vpri(int intnum); + +/* Set/get interrupt lockout level for exclusive access to virtual priority data structures: */ +extern void xthal_set_vpri_locklevel(unsigned intlevel); +extern unsigned xthal_get_vpri_locklevel(void); + +/* Set/get current virtual interrupt priority: */ +extern unsigned xthal_set_vpri(unsigned vpri); +extern unsigned xthal_get_vpri(void); +extern unsigned xthal_set_vpri_intlevel(unsigned intlevel); +extern unsigned xthal_set_vpri_lock(void); + + +/*---------------------------------------------------------------------- + Generic Interrupt Trampolining Support (DEPRECATED) + ----------------------------------------------------------------------*/ + +typedef void (XtHalVoidFunc)(void); + +/* Bitmask of interrupts currently trampolining down: */ +extern unsigned Xthal_tram_pending; + +/* + * Bitmask of which interrupts currently trampolining down synchronously are + * actually enabled; this bitmask is necessary because INTENABLE cannot hold + * that state (sync-trampolining interrupts must be kept disabled while + * trampolining); in the current implementation, any bit set here is not set + * in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level + * one), its enable bit must be moved from here to INTENABLE: + */ +extern unsigned Xthal_tram_enabled; + +/* Bitmask of interrupts configured for sync trampolining: */ +extern unsigned Xthal_tram_sync; + +/* Trampoline support functions: */ +extern unsigned xthal_tram_pending_to_service( void ); +extern void xthal_tram_done( unsigned serviced_mask ); +extern int xthal_tram_set_sync( int intnum, int sync ); +extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn ); + + +/*---------------------------------------------------------------------- + Internal Memories + ----------------------------------------------------------------------*/ + +extern const unsigned char Xthal_num_instrom; +extern const unsigned char Xthal_num_instram; +extern const unsigned char Xthal_num_datarom; +extern const unsigned char Xthal_num_dataram; +extern const unsigned char Xthal_num_xlmi; + +/* Each of the following arrays contains at least one entry, + * or as many entries as needed if more than one: */ +extern const unsigned int Xthal_instrom_vaddr[]; +extern const unsigned int Xthal_instrom_paddr[]; +extern const unsigned int Xthal_instrom_size []; +extern const unsigned int Xthal_instram_vaddr[]; +extern const unsigned int Xthal_instram_paddr[]; +extern const unsigned int Xthal_instram_size []; +extern const unsigned int Xthal_datarom_vaddr[]; +extern const unsigned int Xthal_datarom_paddr[]; +extern const unsigned int Xthal_datarom_size []; +extern const unsigned int Xthal_dataram_vaddr[]; +extern const unsigned int Xthal_dataram_paddr[]; +extern const unsigned int Xthal_dataram_size []; +extern const unsigned int Xthal_xlmi_vaddr[]; +extern const unsigned int Xthal_xlmi_paddr[]; +extern const unsigned int Xthal_xlmi_size []; + + +/*---------------------------------------------------------------------- + Cache + ----------------------------------------------------------------------*/ + +/* number of cache sets in log2(lines per way) */ +extern const unsigned char Xthal_icache_setwidth; +extern const unsigned char Xthal_dcache_setwidth; +/* cache set associativity (number of ways) */ +extern const unsigned int Xthal_icache_ways; +extern const unsigned int Xthal_dcache_ways; +/* cache features */ +extern const unsigned char Xthal_icache_line_lockable; +extern const unsigned char Xthal_dcache_line_lockable; + +/* cache attribute register control (used by other HAL routines) */ +extern unsigned xthal_get_cacheattr( void ); +extern unsigned xthal_get_icacheattr( void ); +extern unsigned xthal_get_dcacheattr( void ); +extern void xthal_set_cacheattr( unsigned ); +extern void xthal_set_icacheattr( unsigned ); +extern void xthal_set_dcacheattr( unsigned ); +/* set cache attribute (access modes) for a range of memory */ +extern int xthal_set_region_attribute( void *addr, unsigned size, + unsigned cattr, unsigned flags ); +/* Bits of flags parameter to xthal_set_region_attribute(): */ +#define XTHAL_CAFLAG_EXPAND 0x000100 /* only expand allowed access to range, don't reduce it */ +#define XTHAL_CAFLAG_EXACT 0x000200 /* return error if can't apply change to exact range specified */ +#define XTHAL_CAFLAG_NO_PARTIAL 0x000400 /* don't apply change to regions partially covered by range */ +#define XTHAL_CAFLAG_NO_AUTO_WB 0x000800 /* don't writeback data after leaving writeback attribute */ +#define XTHAL_CAFLAG_NO_AUTO_INV 0x001000 /* don't invalidate after disabling cache (entering bypass) */ + +/* enable caches */ +extern void xthal_icache_enable( void ); /* DEPRECATED */ +extern void xthal_dcache_enable( void ); /* DEPRECATED */ +/* disable caches */ +extern void xthal_icache_disable( void ); /* DEPRECATED */ +extern void xthal_dcache_disable( void ); /* DEPRECATED */ + +/* invalidate the caches */ +extern void xthal_icache_all_invalidate( void ); +extern void xthal_dcache_all_invalidate( void ); +/* write dirty data back */ +extern void xthal_dcache_all_writeback( void ); +/* write dirty data back and invalidate */ +extern void xthal_dcache_all_writeback_inv( void ); +/* prefetch and lock specified memory range into cache */ +extern void xthal_icache_region_lock( void *addr, unsigned size ); +extern void xthal_dcache_region_lock( void *addr, unsigned size ); +extern void xthal_icache_line_lock(void *addr); +extern void xthal_dcache_line_lock(void *addr); +/* unlock from cache */ +extern void xthal_icache_all_unlock( void ); +extern void xthal_dcache_all_unlock( void ); +extern void xthal_icache_region_unlock( void *addr, unsigned size ); +extern void xthal_dcache_region_unlock( void *addr, unsigned size ); +extern void xthal_icache_line_unlock(void *addr); +extern void xthal_dcache_line_unlock(void *addr); + + + +/*---------------------------------------------------------------------- + Local Memory ECC/Parity + ----------------------------------------------------------------------*/ + +/* Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx: */ +extern void xthal_memep_inject_error(void *addr, int size, int flags); + + + +/*---------------------------------------------------------------------- + Memory Management Unit + ----------------------------------------------------------------------*/ + +extern const unsigned char Xthal_have_spanning_way; +extern const unsigned char Xthal_have_identity_map; +extern const unsigned char Xthal_have_mimic_cacheattr; +extern const unsigned char Xthal_have_xlt_cacheattr; +extern const unsigned char Xthal_have_cacheattr; +extern const unsigned char Xthal_have_tlbs; + +extern const unsigned char Xthal_mmu_asid_bits; /* 0 .. 8 */ +extern const unsigned char Xthal_mmu_asid_kernel; +extern const unsigned char Xthal_mmu_rings; /* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */ +extern const unsigned char Xthal_mmu_ring_bits; +extern const unsigned char Xthal_mmu_sr_bits; +extern const unsigned char Xthal_mmu_ca_bits; +extern const unsigned int Xthal_mmu_max_pte_page_size; +extern const unsigned int Xthal_mmu_min_pte_page_size; + +extern const unsigned char Xthal_itlb_way_bits; +extern const unsigned char Xthal_itlb_ways; +extern const unsigned char Xthal_itlb_arf_ways; +extern const unsigned char Xthal_dtlb_way_bits; +extern const unsigned char Xthal_dtlb_ways; +extern const unsigned char Xthal_dtlb_arf_ways; + +/* Convert between virtual and physical addresses (through static maps only): */ +/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/ +extern int xthal_static_v2p( unsigned vaddr, unsigned *paddrp ); +extern int xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached ); + + +#ifdef __cplusplus +} +#endif +#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + + + +/**************************************************************************** + EXPERIMENTAL and DEPRECATED Definitions + ****************************************************************************/ + + +#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef INCLUDE_DEPRECATED_HAL_CODE +extern const unsigned char Xthal_have_old_exc_arch; +extern const unsigned char Xthal_have_mmu; +extern const unsigned int Xthal_num_regs; +extern const unsigned char Xthal_num_iroms; +extern const unsigned char Xthal_num_irams; +extern const unsigned char Xthal_num_droms; +extern const unsigned char Xthal_num_drams; +extern const unsigned int Xthal_configid0; +extern const unsigned int Xthal_configid1; +#endif + +#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE +#define XTHAL_24_BIT_BREAK 0x80000000 +#define XTHAL_16_BIT_BREAK 0x40000000 +extern const unsigned short Xthal_ill_inst_16[16]; +#define XTHAL_DEST_REG 0xf0000000 /* Mask for destination register */ +#define XTHAL_DEST_REG_INST 0x08000000 /* Branch address is in register */ +#define XTHAL_DEST_REL_INST 0x04000000 /* Branch address is relative */ +#define XTHAL_RFW_INST 0x00000800 +#define XTHAL_RFUE_INST 0x00000400 +#define XTHAL_RFI_INST 0x00000200 +#define XTHAL_RFE_INST 0x00000100 +#define XTHAL_RET_INST 0x00000080 +#define XTHAL_BREAK_INST 0x00000040 +#define XTHAL_SYSCALL_INST 0x00000020 +#define XTHAL_LOOP_END 0x00000010 /* Not set by xthal_inst_type */ +#define XTHAL_JUMP_INST 0x00000008 /* Call or jump instruction */ +#define XTHAL_BRANCH_INST 0x00000004 /* Branch instruction */ +#define XTHAL_24_BIT_INST 0x00000002 +#define XTHAL_16_BIT_INST 0x00000001 +typedef struct xthal_state { + unsigned pc; + unsigned ar[16]; + unsigned lbeg; + unsigned lend; + unsigned lcount; + unsigned extra_ptr; + unsigned cpregs_ptr[XTHAL_MAX_CPS]; +} XTHAL_STATE; +extern unsigned int xthal_inst_type(void *addr); +extern unsigned int xthal_branch_addr(void *addr); +extern unsigned int xthal_get_npc(XTHAL_STATE *user_state); +#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */ + +#ifdef __cplusplus +} +#endif +#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */ + +#endif /*XTENSA_HAL_H*/ diff --git a/toolchain/inst/xtensa-elf/include/xtensa/xtruntime.h b/toolchain/inst/xtensa-elf/include/xtensa/xtruntime.h new file mode 100644 index 0000000..1c9173b --- /dev/null +++ b/toolchain/inst/xtensa-elf/include/xtensa/xtruntime.h @@ -0,0 +1,169 @@ +/* + * xtruntime.h -- general C definitions for single-threaded run-time + * + * Copyright (c) 2002-2006 by Tensilica Inc. ALL RIGHTS RESERVED. + * These coded instructions, statements, and computer programs are the + * copyrighted works and confidential proprietary information of Tensilica Inc. + * They may not be modified, copied, reproduced, distributed, or disclosed to + * third parties in any manner, medium, or form, in whole or in part, without + * the prior written consent of Tensilica Inc. + */ + +#ifndef XTRUNTIME_H +#define XTRUNTIME_H + +#include +#include + +#ifndef XTSTR +#define _XTSTR(x) # x +#define XTSTR(x) _XTSTR(x) +#endif + +#define _xtos_set_execption_handler _xtos_set_exception_handler /* backward compatibility */ +#define _xtos_set_saved_intenable _xtos_ints_on /* backward compatibility */ +#define _xtos_clear_saved_intenable _xtos_ints_off /* backward compatibility */ + +#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__) + +#ifdef __cplusplus +extern "C" { +#endif + +/*typedef void (_xtos_timerdelta_func)(int);*/ +#ifdef __cplusplus +typedef void (_xtos_handler_func)(...); +#else +typedef void (_xtos_handler_func)(); +#endif +typedef _xtos_handler_func *_xtos_handler; + +/* + * unsigned XTOS_SET_INTLEVEL(int intlevel); + * This macro sets the current interrupt level. + * The 'intlevel' parameter must be a constant. + * This macro returns a 32-bit value that must be passed to + * XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level. + * XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs + * it restores only PS.INTLEVEL rather than the entire PS register + * and thus is slower. + */ +#if !XCHAL_HAVE_INTERRUPTS +# define XTOS_SET_INTLEVEL(intlevel) +# define XTOS_SET_MIN_INTLEVEL(intlevel) +# define XTOS_RESTORE_INTLEVEL(restoreval) +# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) +#elif XCHAL_HAVE_XEA2 +/* In XEA2, we can simply safely set PS.INTLEVEL directly: */ +/* NOTE: these asm macros don't modify memory, but they are marked + * as such to act as memory access barriers to the compiler because + * these macros are sometimes used to delineate critical sections; + * function calls are natural barriers (the compiler does not know + * whether a function modifies memory) unless declared to be inlined. */ +# define XTOS_SET_INTLEVEL(intlevel) ({ unsigned __tmp; \ + __asm__ __volatile__( "rsil %0, " XTSTR(intlevel) "\n" \ + : "=a" (__tmp) : : "memory" ); \ + __tmp;}) +# define XTOS_SET_MIN_INTLEVEL(intlevel) ({ unsigned __tmp, __tmp2, __tmp3; \ + __asm__ __volatile__( "rsr %0, " XTSTR(PS) "\n" /* get old (current) PS.INTLEVEL */ \ + "movi %2, " XTSTR(intlevel) "\n" \ + "extui %1, %0, 0, 4\n" /* keep only INTLEVEL bits of parameter */ \ + "blt %2, %1, 1f\n" \ + "rsil %0, " XTSTR(intlevel) "\n" \ + "1:\n" \ + : "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \ + __tmp;}) +# define XTOS_RESTORE_INTLEVEL(restoreval) do{ unsigned __tmp = (restoreval); \ + __asm__ __volatile__( "wsr %0, " XTSTR(PS) " ; rsync\n" \ + : : "a" (__tmp) : "memory" ); \ + }while(0) +# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_intlevel(restoreval) +#else +/* In XEA1, we have to rely on INTENABLE register virtualization: */ +extern unsigned _xtos_set_vpri( unsigned vpri ); +extern unsigned _xtos_vpri_enabled; /* current virtual priority */ +# define XTOS_SET_INTLEVEL(intlevel) _xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel)) +# define XTOS_SET_MIN_INTLEVEL(intlevel) _xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel)) +# define XTOS_RESTORE_INTLEVEL(restoreval) _xtos_set_vpri(restoreval) +# define XTOS_RESTORE_JUST_INTLEVEL(restoreval) _xtos_set_vpri(restoreval) +#endif + +/* + * The following macros build upon the above. They are generally used + * instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly. + * They all return a value that can be used with XTOS_RESTORE_INTLEVEL() + * or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore + * the effective interrupt level to what it was before the macro was invoked. + * In XEA2, the DISABLE macros are much faster than the MASK macros + * (in all configs, DISABLE sets the effective interrupt level, whereas MASK + * makes ensures the effective interrupt level is at least the level given + * without lowering it; in XEA2 with INTENABLE virtualization, these macros + * affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial + * MASK semantics). + * + * A typical critical section sequence might be: + * unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS; + * ... critical section ... + * XTOS_RESTORE_INTLEVEL(rval); + */ +/* Enable all interrupts (those activated with _xtos_ints_on()): */ +#define XTOS_ENABLE_INTERRUPTS XTOS_SET_INTLEVEL(0) +/* Disable low priority level interrupts (they can interact with the OS): */ +#define XTOS_DISABLE_LOWPRI_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS) +#define XTOS_MASK_LOWPRI_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS) +/* Disable interrupts that can interact with the OS: */ +#define XTOS_DISABLE_EXCM_INTERRUPTS XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL) +#define XTOS_MASK_EXCM_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL) +#if 0 /* XTOS_LOCK_LEVEL is not exported to applications */ +/* Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE: */ +#define XTOS_DISABLE_LOCK_INTERRUPTS XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL) +#define XTOS_MASK_LOCK_INTERRUPTS XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL) +#endif +/* Disable ALL interrupts (not for common use, particularly if one's processor + * configuration has high-level interrupts and one cares about their latency): */ +#define XTOS_DISABLE_ALL_INTERRUPTS XTOS_SET_INTLEVEL(15) + + +extern unsigned int _xtos_ints_off( unsigned int mask ); +extern unsigned int _xtos_ints_on( unsigned int mask ); +extern unsigned _xtos_set_intlevel( int intlevel ); +extern unsigned _xtos_set_min_intlevel( int intlevel ); +extern unsigned _xtos_restore_intlevel( unsigned restoreval ); +extern unsigned _xtos_restore_just_intlevel( unsigned restoreval ); +extern _xtos_handler _xtos_set_interrupt_handler( int n, _xtos_handler f ); +extern _xtos_handler _xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg ); +extern _xtos_handler _xtos_set_exception_handler( int n, _xtos_handler f ); + +extern void _xtos_memep_initrams( void ); +extern void _xtos_memep_enable( int flags ); + +/* Deprecated (but kept because they were documented): */ +extern unsigned int _xtos_read_ints( void ); /* use xthal_get_interrupt() instead */ +extern void _xtos_clear_ints( unsigned int mask ); /* use xthal_set_intclear() instead */ + +#if XCHAL_NUM_CONTEXTS > 1 +extern unsigned _xtos_init_context(int context_num, int stack_size, + _xtos_handler_func *start_func, int arg1); +#endif + +/* Deprecated: */ +#if XCHAL_NUM_TIMERS > 0 +extern void _xtos_timer_0_delta( int cycles ); +#endif +#if XCHAL_NUM_TIMERS > 1 +extern void _xtos_timer_1_delta( int cycles ); +#endif +#if XCHAL_NUM_TIMERS > 2 +extern void _xtos_timer_2_delta( int cycles ); +#endif +#if XCHAL_NUM_TIMERS > 3 +extern void _xtos_timer_3_delta( int cycles ); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */ + +#endif /* XTRUNTIME_H */ -- 2.25.1