From ff7e9700eda14ccf8ebe399d3831ef266e743c2d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 15 Sep 2014 02:44:36 +0200 Subject: [PATCH] arm: cache: Add support for write-allocate D-Cache Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Albert Aribaud Cc: Tom Rini Cc: Wolfgang Denk Cc: Pavel Machek Acked-by: Pavel Machek --- arch/arm/include/asm/system.h | 1 + arch/arm/lib/cache-cp15.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index d51ba668f3..ca2d44faf4 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -185,6 +185,7 @@ enum dcache_option { DCACHE_OFF = 0x12, DCACHE_WRITETHROUGH = 0x1a, DCACHE_WRITEBACK = 0x1e, + DCACHE_WRITEALLOC = 0x16, }; /* Size of an MMU section */ diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 3e62d58542..2155fe8187 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -73,6 +73,8 @@ __weak void dram_bank_mmu_setup(int bank) i++) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) set_section_dcache(i, DCACHE_WRITETHROUGH); +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) + set_section_dcache(i, DCACHE_WRITEALLOC); #else set_section_dcache(i, DCACHE_WRITEBACK); #endif -- 2.25.1