From fefe9d06bd0917739822a4be4c702f1d5d0e0899 Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Fri, 2 Jun 2017 11:19:43 +0200 Subject: [PATCH] rockchip: rk3288: grf: Fix shift for RK3288_TXCLK_DLY_ENA_GMAC_ENABLE RK3288_TXCLK_DLY_ENA_GMAC_ENABLE, in GRF_SOC_CON3, is supposed to be bit 0xe and not 0xf. Otherwise, it is RGMII RX clock delayline enable and introduces random delays and data lose. This commit fixes the issue by replacing RK3288_TXCLK_DLY_ENA_GMAC_ENABLE with the right shift. Signed-off-by: Romain Perier Reviewed-by: Simon Glass --- arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 7d56b8ced0..fbc4a0d80f 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -813,7 +813,7 @@ enum { (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0, RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = - (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, RK3288_CLK_RX_DL_CFG_GMAC_MASK = -- 2.25.1