From f94c44e51e4ffc45d727c6b3d9ead0cb83171f91 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 26 Dec 2017 13:55:52 +0800 Subject: [PATCH] riscv: Add Kconfig to support RISC-V Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu Cc: Padmarao Begari --- MAINTAINERS | 7 +++++++ arch/riscv/Kconfig | 42 ++++++++++++++++++++++++++++++++++++++++++ arch/riscv/Makefile | 11 +++++++++++ arch/riscv/config.mk | 33 +++++++++++++++++++++++++++++++++ 4 files changed, 93 insertions(+) create mode 100644 arch/riscv/Kconfig create mode 100644 arch/riscv/Makefile create mode 100644 arch/riscv/config.mk diff --git a/MAINTAINERS b/MAINTAINERS index 9b4b63b063..754db5553d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -423,6 +423,13 @@ S: Orphaned (Since 2017-01) T: git git://git.denx.de/u-boot-onenand.git F: drivers/mtd/onenand/ +RISC-V +M: Rick Chen +S: Maintained +T: git git://git.denx.de/u-boot-riscv.git +F: arch/riscv/ +F: tools/prelink-riscv.c + SANDBOX M: Simon Glass S: Maintained diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig new file mode 100644 index 0000000000..c50be37c97 --- /dev/null +++ b/arch/riscv/Kconfig @@ -0,0 +1,42 @@ +menu "RISCV architecture" + depends on RISCV + +config SYS_ARCH + default "riscv" + +choice + prompt "Target select" + optional + +config TARGET_NX25_AE250 + bool "Support nx25-ae250" + +endchoice + +source "board/AndesTech/nx25-ae250/Kconfig" + +choice + prompt "CPU selection" + default CPU_RISCV_32 + +config CPU_RISCV_32 + bool "RISCV 32 bit" + select 32BIT + help + Choose this option to build an U-Boot for RISCV32 architecture. + +config CPU_RISCV_64 + bool "RISCV 64 bit" + select 64BIT + help + Choose this option to build an U-Boot for RISCV64 architecture. + +endchoice + +config 32BIT + bool + +config 64BIT + bool + +endmenu diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile new file mode 100644 index 0000000000..09d24db7a9 --- /dev/null +++ b/arch/riscv/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2017 Andes Technology Corporation. +# Rick Chen, Andes Technology Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/riscv/cpu/$(CPU)/start.o + +libs-y += arch/riscv/cpu/$(CPU)/ +libs-y += arch/riscv/lib/ diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk new file mode 100644 index 0000000000..6b681c4286 --- /dev/null +++ b/arch/riscv/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2000-2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (c) 2017 Microsemi Corporation. +# Padmarao Begari, Microsemi Corporation +# +# Copyright (C) 2017 Andes Technology Corporation +# Rick Chen, Andes Technology Corporation +# +# SPDX-License-Identifier: GPL-2.0+ + +ifeq ($(CROSS_COMPILE),) +CROSS_COMPILE := riscv32-unknown-linux-gnu- +endif + +32bit-emul := elf32lriscv +64bit-emul := elf64lriscv + +ifdef CONFIG_32BIT +PLATFORM_LDFLAGS += -m $(32bit-emul) +endif + +ifdef CONFIG_64BIT +PLATFORM_LDFLAGS += -m $(64bit-emul) +endif + +CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \ + -T $(srctree)/examples/standalone/riscv.lds + +PLATFORM_CPPFLAGS += -ffixed-gp -fpic +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -gdwarf-2 +LDFLAGS_u-boot += --gc-sections -static -pie -- 2.25.1