From f88bd7cd0f7c03d959330443be5adabf70351a27 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 17 Feb 2017 11:51:42 +0100 Subject: [PATCH] ar71xx: fix ethernet PLL configuration for QCA956x QCA956x is configured like AR934x, not like the older chips. Should fix ethernet hangs when using the WAN port without SGMII Signed-off-by: Felix Fietkau --- target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c index 07cb12c8e9..790c2d3396 100644 --- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c +++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c @@ -1075,7 +1075,7 @@ void __init ath79_register_eth(unsigned int id) if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII) pdata->set_speed = qca956x_set_speed_sgmii; else - pdata->set_speed = ath79_set_speed_ge0; + pdata->set_speed = ar934x_set_speed_ge0; } else { pdata->reset_bit = QCA955X_RESET_GE1_MAC | QCA955X_RESET_GE1_MDIO; -- 2.25.1