From f79277be3d337906adce6fcc80fe182813e30f8f Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Sun, 20 Mar 2016 17:30:51 +0100 Subject: [PATCH] Add more information about DDR timing values and print them in board info --- u-boot/board/ar7240/common/common.c | 7 +++-- u-boot/cpu/mips/ar7240/qca_dram.c | 41 ++++++++++++++++++++++++++++- u-boot/include/soc/qca_soc_common.h | 5 +++- 3 files changed, 49 insertions(+), 4 deletions(-) diff --git a/u-boot/board/ar7240/common/common.c b/u-boot/board/ar7240/common/common.c index 60f76a3..7b71871 100644 --- a/u-boot/board/ar7240/common/common.c +++ b/u-boot/board/ar7240/common/common.c @@ -122,8 +122,11 @@ void print_board_info(void) /* DDR interface width */ printf("%d-bit ", qca_dram_ddr_width()); - /* CAS latency */ - printf("CL%d\n", qca_dram_cas_lat()); + /* tCL-tRCD-tRP-tRAS latency */ + printf("CL%d-%d-%d-%d\n", qca_dram_cas_lat(), + qca_dram_trcd_lat(), + qca_dram_trp_lat(), + qca_dram_tras_lat()); /* SPI NOR FLASH sizes and types */ printf("%" ALIGN_SIZE "s ", "FLASH:"); diff --git a/u-boot/cpu/mips/ar7240/qca_dram.c b/u-boot/cpu/mips/ar7240/qca_dram.c index 3bca1d3..cc07897 100644 --- a/u-boot/cpu/mips/ar7240/qca_dram.c +++ b/u-boot/cpu/mips/ar7240/qca_dram.c @@ -123,7 +123,7 @@ u32 qca_dram_ddr_width(void) /* * Returns CAS latency, based on setting in DDR_CONFIG register */ -u32 qca_dram_cas_lat(void) +inline u32 qca_dram_cas_lat(void) { #ifndef CONFIG_BOARD_DRAM_CAS_LATENCY u32 reg; @@ -141,6 +141,45 @@ u32 qca_dram_cas_lat(void) #endif } +/* + * Returns tRCD latency + */ +inline u32 qca_dram_trcd_lat(void) +{ + u32 reg; + + reg = (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_TRCD_MASK) + >> QCA_DDR_CFG_TRCD_SHIFT; + + return reg / 2; +} + +/* + * Returns tRP latency + */ +inline u32 qca_dram_trp_lat(void) +{ + u32 reg; + + reg = (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_TRP_MASK) + >> QCA_DDR_CFG_TRP_SHIFT; + + return reg / 2; +} + +/* + * Returns tRAS latency + */ +inline u32 qca_dram_tras_lat(void) +{ + u32 reg; + + reg = (qca_soc_reg_read(QCA_DDR_CFG_REG) & QCA_DDR_CFG_TRAS_MASK) + >> QCA_DDR_CFG_TRAS_SHIFT; + + return reg / 2; +} + /* * =============================================== * DQS delay tap controller tune related functions diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h index 5a1395f..2abf5d5 100644 --- a/u-boot/include/soc/qca_soc_common.h +++ b/u-boot/include/soc/qca_soc_common.h @@ -1593,9 +1593,12 @@ u32 qca_sf_sfdp_info(u32 bank, u32 *flash_size, u32 *sector_size, u8 *erase_c u32 qca_sf_jedec_id(u32 bank); u32 qca_dram_type(void); u32 qca_dram_size(void); -u32 qca_dram_cas_lat(void); u32 qca_dram_ddr_width(void); void qca_dram_init(void); +inline u32 qca_dram_cas_lat(void); +inline u32 qca_dram_trcd_lat(void); +inline u32 qca_dram_trp_lat(void); +inline u32 qca_dram_tras_lat(void); #endif /* !__ASSEMBLY__ */ /* -- 2.25.1