From ed50e35bbea02dc6d2bf38b4c6b39d6ea58a176e Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Mon, 16 Nov 2015 03:15:39 +0100 Subject: [PATCH] Include all files from TP-Link GPL sources needed to make TL-WR820N based on QCA953x compile and work... we will clean this mess later --- u-boot/board/ar7240/ap143/Makefile | 23 + u-boot/board/ar7240/ap143/ap143.c | 185 + u-boot/board/ar7240/ap143/config.mk | 12 + .../board/ar7240/ap143/u-boot-bootstrap.lds | 62 + u-boot/board/ar7240/ap143/u-boot.lds | 43 + u-boot/board/ar7240/common/953x.S | 170 + u-boot/board/ar7240/common/ath_pci.c | 533 ++ u-boot/board/ar7240/common/athr_s27_phy.c | 875 ++++ u-boot/board/ar7240/common/athr_s27_phy.h | 214 + u-boot/board/ar7240/common/init-953x.c | 395 ++ u-boot/board/ar7240/common/qca-eth-953x.c | 706 +++ u-boot/board/ar7240/common/qca-eth-953x.h | 371 ++ u-boot/board/ar7240/common/qca-eth-953x_phy.h | 95 + u-boot/board/ar7240/common/tap-953x.S | 204 + u-boot/include/953x.h | 4525 +++++++++++++++++ u-boot/include/atheros.h | 362 ++ u-boot/include/configs/ap143.h | 201 + u-boot/net/eth.c | 10 +- 18 files changed, 8985 insertions(+), 1 deletion(-) create mode 100644 u-boot/board/ar7240/ap143/Makefile create mode 100644 u-boot/board/ar7240/ap143/ap143.c create mode 100644 u-boot/board/ar7240/ap143/config.mk create mode 100644 u-boot/board/ar7240/ap143/u-boot-bootstrap.lds create mode 100644 u-boot/board/ar7240/ap143/u-boot.lds create mode 100755 u-boot/board/ar7240/common/953x.S create mode 100755 u-boot/board/ar7240/common/ath_pci.c create mode 100755 u-boot/board/ar7240/common/athr_s27_phy.c create mode 100755 u-boot/board/ar7240/common/athr_s27_phy.h create mode 100755 u-boot/board/ar7240/common/init-953x.c create mode 100755 u-boot/board/ar7240/common/qca-eth-953x.c create mode 100755 u-boot/board/ar7240/common/qca-eth-953x.h create mode 100755 u-boot/board/ar7240/common/qca-eth-953x_phy.h create mode 100755 u-boot/board/ar7240/common/tap-953x.S create mode 100755 u-boot/include/953x.h create mode 100755 u-boot/include/atheros.h create mode 100644 u-boot/include/configs/ap143.h diff --git a/u-boot/board/ar7240/ap143/Makefile b/u-boot/board/ar7240/ap143/Makefile new file mode 100644 index 0000000..f606bbf --- /dev/null +++ b/u-boot/board/ar7240/ap143/Makefile @@ -0,0 +1,23 @@ +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/ar7240_flash.o ../common/common.o ../common/qca-eth-953x.o ../common/ath_pci.o ../common/init-953x.o + +ifeq ($(ETH_CONFIG), _s27) +OBJS += ../common/athr_s27_phy.o +endif + +SOBJS = ../common/953x.o ../common/tap-953x.o + +$(LIB): .depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/u-boot/board/ar7240/ap143/ap143.c b/u-boot/board/ar7240/ap143/ap143.c new file mode 100644 index 0000000..43af583 --- /dev/null +++ b/u-boot/board/ar7240/ap143/ap143.c @@ -0,0 +1,185 @@ +#include +#include +#include +#include +#include +#include +#include + +extern int ath_ddr_initial_config(uint32_t refresh); +extern int ath_ddr_find_size(void); + +void led_toggle(void) +{ + return; +} + +void all_led_on(void) +{ + return; +} + +void all_led_off(void) +{ + return; +} + +int reset_button_status(void) +{ + return 0; +} + +int gpio_init(void) +{ + return 0; +} + +void ath_set_tuning_caps(void) +{ + typedef struct { + u_int8_t pad[0x28], + params_for_tuning_caps[2], + featureEnable; + } __attribute__((__packed__)) ar9300_eeprom_t; + + ar9300_eeprom_t *eep; + uint32_t val; + + eep = (ar9300_eeprom_t *)WLANCAL; + + val = XTAL_TCXODET_SET(0x0) | + XTAL_XTAL_CAPINDAC_SET(0x4b) | + XTAL_XTAL_CAPOUTDAC_SET(0x4b) | + XTAL_XTAL_DRVSTR_SET(0x3) | + XTAL_XTAL_SHORTXIN_SET(0x0) | + XTAL_XTAL_LOCALBIAS_SET(0x1) | + XTAL_XTAL_PWDCLKD_SET(0x0) | + XTAL_XTAL_BIAS2X_SET(0x0) | + XTAL_XTAL_LBIAS2X_SET(0x0) | + XTAL_XTAL_OSCON_SET(0x1) | + XTAL_XTAL_PWDCLKIN_SET(0x0) | + XTAL_LOCAL_XTAL_SET(0x0) | + XTAL_PWD_SWREGCLK_SET(0x0) | + XTAL_SPARE_SET(0x0); + + /* checking feature enable bit 6 and caldata is valid */ + if ((eep->featureEnable & 0x40) && (eep->pad[0x0] != 0xff)) { + val &= ~(XTAL_XTAL_CAPINDAC_MASK | XTAL_XTAL_CAPOUTDAC_MASK); + val |= XTAL_XTAL_CAPINDAC_SET(eep->params_for_tuning_caps[0]) | + XTAL_XTAL_CAPOUTDAC_SET(eep->params_for_tuning_caps[0]); + } + + ath_reg_wr(XTAL_ADDRESS, val); + ath_reg_wr(XTAL2_ADDRESS, XTAL2_DCA_BYPASS_SET(0x1) | + XTAL2_FSM_START_L_SET(0x1)); + ath_reg_wr(XTAL3_ADDRESS, XTAL3_EVAL_LENGTH_SET(0x400) | + XTAL3_HARMONIC_NUMBER_SET(0x51)); + +#define __str(x) # x +#define str(x) __str(x) + + //printf("Setting " str(XTAL_ADDRESS) " to 0x%x\n", val); + return; +} + +void ath_usb_initial_config(void) +{ +#define unset(a) (~(a)) + + if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) { + + ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_USB_HOST_RESET_SET(1)); + udelay(1000); + ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_USB_PHY_RESET_SET(1)); + udelay(1000); + + ath_reg_wr(PHY_CTRL5_ADDRESS, PHY_CTRL5_RESET_1); + udelay(1000); + + ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_USB_PHY_PLL_PWD_EXT_SET(1)); + udelay(1000); + ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_USB_PHY_ARESET_SET(1)); + udelay(1000); + + ath_reg_rmw_clear(RST_CLKGAT_EN_ADDRESS, RST_CLKGAT_EN_USB1_SET(1)); + + return; + } + + ath_reg_wr_nf(SWITCH_CLOCK_SPARE_ADDRESS, + ath_reg_rd(SWITCH_CLOCK_SPARE_ADDRESS) | + SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(2)); + udelay(1000); + + ath_reg_rmw_set(RST_RESET_ADDRESS, + RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(1)); + udelay(1000); + ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_ARESET_SET(1)); + udelay(1000); + ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_RESET_SET(1)); + udelay(1000); + ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_HOST_RESET_SET(1)); + udelay(1000); + + ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_USB_PHY_PLL_PWD_EXT_SET(1)); + udelay(10); +} + +void ath_gpio_config(void) +{ + /* disable the CLK_OBS on GPIO_4 and set GPIO4 as input */ +#if 0 + ath_reg_rmw_clear(GPIO_OE_ADDRESS, (1 << 4)); + ath_reg_rmw_clear(GPIO_OUT_FUNCTION1_ADDRESS, GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK); + ath_reg_rmw_set(GPIO_OUT_FUNCTION1_ADDRESS, GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(0x80)); + ath_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 4)); +#endif + +#if 0 + /* Set GPIO 13 as input for LED functionality to be OFF during bootup */ + ath_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 13)); + /* Turn off JUMPST_LED and 5Gz LED during bootup */ + ath_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 15)); +#endif + ath_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 12)); + +} + +int ath_mem_config(void) +{ + unsigned int type, reg32, *tap; + extern uint32_t *ath_ddr_tap_cal(void); + +#if !defined(CONFIG_ATH_EMULATION) + + type = ath_ddr_initial_config(CFG_DDR_REFRESH_VAL); + + tap = ath_ddr_tap_cal(); + //prmsg("tap = 0x%p\n", tap); + + tap = (uint32_t *)0xbd001f10; + //prmsg("Tap (low, high) = (0x%x, 0x%x)\n", tap[0], tap[1]); + + tap = (uint32_t *)TAP_CONTROL_0_ADDRESS; + //prmsg("Tap values = (0x%x, 0x%x, 0x%x, 0x%x)\n", + // tap[0], tap[2], tap[2], tap[3]); + + /* Take WMAC out of reset */ + reg32 = ath_reg_rd(RST_RESET_ADDRESS); + reg32 = reg32 & ~RST_RESET_RTC_RESET_SET(1); + ath_reg_wr_nf(RST_RESET_ADDRESS, reg32); + + ath_usb_initial_config(); + + ath_gpio_config(); +#endif /* !defined(CONFIG_ATH_EMULATION) */ + + //ath_set_tuning_caps(); + + return ath_ddr_find_size(); +} + +long int dram_init() +{ + return ath_mem_config(); +} diff --git a/u-boot/board/ar7240/ap143/config.mk b/u-boot/board/ar7240/ap143/config.mk new file mode 100644 index 0000000..64383b6 --- /dev/null +++ b/u-boot/board/ar7240/ap143/config.mk @@ -0,0 +1,12 @@ +# ROM version +ifdef COMPRESSED_UBOOT + TEXT_BASE = 0x80010000 + BOOTSTRAP_TEXT_BASE = 0x9F000000 +# RAM version +else + ifdef CONFIG_SKIP_LOWLEVEL_INIT + TEXT_BASE = 0x80100000 + else + TEXT_BASE = 0x9F000000 + endif +endif \ No newline at end of file diff --git a/u-boot/board/ar7240/ap143/u-boot-bootstrap.lds b/u-boot/board/ar7240/ap143/u-boot-bootstrap.lds new file mode 100644 index 0000000..4b680e0 --- /dev/null +++ b/u-boot/board/ar7240/ap143/u-boot-bootstrap.lds @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start_bootstrap) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + . = ALIGN(16); + _gp = .; + __got_start_bootstrap = .; + .got : { *(.got) } + __got_end_bootstrap = .; + + + .sdata : { *(.sdata) } + + uboot_end_data_bootstrap = .; + num_got_entries = (__got_end_bootstrap - __got_start_bootstrap) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end_bootstrap = .; +} diff --git a/u-boot/board/ar7240/ap143/u-boot.lds b/u-boot/board/ar7240/ap143/u-boot.lds new file mode 100644 index 0000000..8ccdf20 --- /dev/null +++ b/u-boot/board/ar7240/ap143/u-boot.lds @@ -0,0 +1,43 @@ +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_ARCH(mips) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .sdata : { *(.sdata) } + + . = ALIGN(16); + _gp = .; + __got_start = .; + .got : { *(.got) } + __got_end = .; + + + .sdata : { *(.sdata) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + uboot_end_data = .; + num_got_entries = (__got_end - __got_start) >> 2; + + . = ALIGN(4); + .sbss : { *(.sbss) } + .bss : { *(.bss) } + uboot_end = .; +} diff --git a/u-boot/board/ar7240/common/953x.S b/u-boot/board/ar7240/common/953x.S new file mode 100755 index 0000000..3a2fa43 --- /dev/null +++ b/u-boot/board/ar7240/common/953x.S @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +/* + * Helper macros. + * These Clobber t7, t8 and t9 + */ +#define reg_write(_reg, _val) \ + li t7, KSEG1ADDR(_reg); \ + li t8, _val; \ + sw t8, 0(t7); + +#define reg_rmw_set(_reg, _mask, _val) \ + li t7, KSEG1ADDR(_reg); \ + lw t8, 0(t7); \ + li t9, ~(_mask); \ + and t8, t8, t9; \ + li t9, _val; \ + or t8, t8, t9; \ + sw t8, 0(t7) + +#define cpu_pll_set(_mask, _val) \ + reg_rmw_set(CPU_PLL_CONFIG_ADDRESS, _mask, _val) + +#define ddr_pll_set(_mask, _val) \ + reg_rmw_set(DDR_PLL_CONFIG_ADDRESS, _mask, _val) + +#define cpu_ddr_control_set(_mask, _val) \ + reg_rmw_set(CPU_DDR_CLOCK_CONTROL_ADDRESS, _mask, _val) + + +/****************************************************************************** + * first level initialization: + * + * 0) If clock cntrl reset switch is already set, we're recovering from + * "divider reset"; goto 3. + * 1) Setup divide ratios. + * 2) Reset. + * 3) Setup pll's, wait for lock. + * + *****************************************************************************/ + +.globl lowlevel_init + .type lowlevel_init, @function + .text + .align 4 + +lowlevel_init: + + reg_write(BB_DPLL2_ADDRESS, BB_DPLL2_KI_SET(2) | \ + BB_DPLL2_KD_SET(0x10) | \ + BB_DPLL2_PLL_PWD_SET(1)); + reg_write(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KI_SET(2) | \ + PCIe_DPLL2_KD_SET(0x10) | \ + PCIe_DPLL2_PLL_PWD_SET(1)); + reg_write(DDR_DPLL2_ADDRESS, DDR_DPLL2_KI_SET(2) | \ + DDR_DPLL2_KD_SET(0x10) | \ + DDR_DPLL2_PLL_PWD_SET(1)); + reg_write(CPU_DPLL2_ADDRESS, CPU_DPLL2_KI_SET(2) | \ + CPU_DPLL2_KD_SET(0x10) | \ + CPU_DPLL2_PLL_PWD_SET(1)); + + li t5, CPU_PLL_CONFIG_NINT_VAL + li t6, DDR_PLL_CONFIG_NINT_VAL + li t4, CPU_PLL_DITHER_VAL + li t3, DDR_PLL_DITHER_VAL + +/* + li t7, PLL_CONFIG_VAL_F + lw t8, 0(t7) + li t7, PLL_MAGIC + beq t7, t8, read_from_flash + nop + j pll_bypass_set + nop +read_from_flash: + li t7, PLL_CONFIG_VAL_F + 4 + lw t5, 0(t7) + lw t4, 4(t7) + lw t6, 8(t7) + lw t3, 12(t7) +*/ + +pll_bypass_set: + cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1)); + cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1)); + cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1)); + +init_cpu_pll: + li t7, KSEG1ADDR(CPU_PLL_CONFIG_ADDRESS); + li t8, (CPU_PLL_CONFIG_PLLPWD_SET(1) | \ + CPU_PLL_CONFIG_REF_DIV_VAL | \ + CPU_PLL_CONFIG_RANGE_VAL | \ + CPU_PLL_CONFIG_OUT_DIV_VAL1); + or t8, t8, t5 + sw t8, 0(t7); + +init_ddr_pll: + li t7, KSEG1ADDR(DDR_PLL_CONFIG_ADDRESS); + li t8, (DDR_PLL_CONFIG_PLLPWD_SET(1) | \ + DDR_PLL_CONFIG_REF_DIV_VAL | \ + DDR_PLL_CONFIG_RANGE_VAL | \ + DDR_PLL_CONFIG_OUT_DIV_VAL1); + or t8, t8, t6 + sw t8, 0(t7); + +init_ahb_pll: + reg_write(CPU_DDR_CLOCK_CONTROL_ADDRESS, + CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL | + AHB_CLK_FROM_DDR | + CLK_SRC_CONTROL | + CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV | + CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV | + CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1) | + CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) | + CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1)); + +pll_pwd_unset: + cpu_pll_set(CPU_PLL_CONFIG_PLLPWD_MASK, CPU_PLL_CONFIG_PLLPWD_SET(0)); + ddr_pll_set(DDR_PLL_CONFIG_PLLPWD_MASK, DDR_PLL_CONFIG_PLLPWD_SET(0)); + +outdiv_unset: + cpu_pll_set(CPU_PLL_CONFIG_OUTDIV_MASK, CPU_PLL_CONFIG_OUT_DIV_VAL2); + ddr_pll_set(DDR_PLL_CONFIG_OUTDIV_MASK, DDR_PLL_CONFIG_OUT_DIV_VAL2); + +pll_bypass_unset: + cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0)); + cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0)); + cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0)); + +ddr_pll_dither_unset: + li t7, KSEG1ADDR(DDR_PLL_DITHER_ADDRESS); + sw t3, 0(t7); + +cpu_pll_dither_unset: + li t7, KSEG1ADDR(CPU_PLL_DITHER_ADDRESS); + sw t4, 0(t7); + + lui t7, 47110; + lui t8, 1020; + sw t8, 0xb4(t7); + + jr ra + nop diff --git a/u-boot/board/ar7240/common/ath_pci.c b/u-boot/board/ar7240/common/ath_pci.c new file mode 100755 index 0000000..c29eea0 --- /dev/null +++ b/u-boot/board/ar7240/common/ath_pci.c @@ -0,0 +1,533 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* +** PCI controller "hose" value +*/ + +static struct pci_controller hose; + +static int ath_local_read_config(int where, int size, uint32_t *value); +static int ath_local_write_config(int where, int size, uint32_t value); + +static int +ath_local_read_config(int where, int size, uint32_t *value) +{ + *value = ath_reg_rd(ATH_PCI_CRP + where); + return 0; +} + +static int +ath_local_write_config(int where, int size, uint32_t value) +{ + ath_reg_wr((ATH_PCI_CRP + where),value); + return 0; +} + +static int +ath_pci_read_config(struct pci_controller *hose, + pci_dev_t dev, int where, uint32_t *value) +{ + *value = ath_reg_rd(ATH_PCI_DEV_CFGBASE + where); + return 0; +} + +static int +ath_pci_write_config(struct pci_controller *hose, + pci_dev_t dev, int where, uint32_t value) +{ + ath_reg_wr((ATH_PCI_DEV_CFGBASE + where), value); + return 0; +} + +#ifdef PCIE2_APP_ADDRESS +static int +ath_local_read_config_rc2(int where, int size, uint32_t *value) +{ + *value = ath_reg_rd(0x18250000 + where); + return 0; +} + +static int +ath_local_write_config_rc2(int where, int size, uint32_t value) +{ + ath_reg_wr((0x18250000 + where),value); + return 0; +} + +static int +ath_pci_read_config_rc2(struct pci_controller *hose, + pci_dev_t dev, int where, uint32_t *value) +{ + *value = ath_reg_rd(0xb6000000 + where); + return 0; +} + +static int +ath_pci_write_config_rc2(struct pci_controller *hose, + pci_dev_t dev, int where, uint32_t value) +{ + ath_reg_wr((0xb6000000 + where), value); + return 0; +} +#endif + +/* +** We will use the ART configuration information stored in flash to initialize +** these devices as required. +*/ + +void plat_dev_init(void) +{ + u32 val; + u32 addr; + u32 BaseAddr = 0x10000000; + u32 CalAddr = WLANCAL; + volatile u16 *calData; + + /* + * Copy the device ID from Flash to device config space. + */ + + calData = (u16 *)CalAddr; + +#ifndef CONFIG_PCI_CONFIG_DATA_IN_OTP + if (calData[0] != 0xa55a && calData[0] != 0x5aa5) + { +#ifndef COMPRESSED_UBOOT + prmsg("BOARD IS NOT CALIBRATED!!!\n"); +#endif + return; + } +#else + return; +#endif + /* + ** Need to setup the PCI device to access the internal registers + */ + if ((is_ar7241() || is_ar7242())) + ath_pci_write_config(&hose, NULL, 0x10, 0x1000ffff); + else + ath_pci_write_config(&hose, NULL, 0x10, 0xffff); + + ath_pci_write_config(&hose, NULL, 0x04, 0x6); + +#ifdef PCIE2_APP_ADDRESS + ath_pci_write_config_rc2(&hose, NULL, 0x10, 0xffff); + + ath_pci_write_config_rc2(&hose, NULL, 0x04, 0x6); +#endif + + /* + ** Set pointer to first reg address + */ + + calData += ATH_ART_PCICFG_OFFSET; + + while(*calData != 0xffff) + { + u16 cd; + + cd = *calData++; + addr = BaseAddr + cd; + val = *calData++; + val |= (*calData++) << 16; + + ath_reg_wr_nf(addr,val); + udelay(100); + } + + return; +} + + +/******************************************************************************/ +/*! +** \brief pci host initialization +** +** Sets up the PCI controller on the host. For AR7240 this may not be necessary, +** but this function is required for board support. +** +** We want a 1:1 mapping between PCI and DDR for inbound and outbound. +** The PCI<---AHB decoding works as follows: +** +** 8 registers in the DDR unit provide software configurable 32 bit offsets +** for each of the eight 16MB PCI windows in the 128MB. The offsets will be +** added to any address in the 16MB segment before being sent to the PCI unit. +** +** Essentially for any AHB address generated by the CPU, +** 1. the MSB four bits are stripped off, [31:28], +** 2. Bit 27 is used to decide between the lower 128Mb (PCI) or the rest of +** the AHB space +** 3. Bits 26:24 are used to access one of the 8 window registers and are +** masked off. +** 4. If it is a PCI address, then the WINDOW offset in the WINDOW register +** corresponding to the next 3 bits (bit 26:24) is ADDED to the address, +** to generate the address to PCI unit. +** +** eg. CPU address = 0x100000ff +** window 0 offset = 0x10000000 +** This points to lowermost 16MB window in PCI space. +** So the resulting address would be 0x000000ff+0x10000000 +** = 0x100000ff +** +** eg2. CPU address = 0x120000ff +** WINDOW 2 offset = 0x12000000 +** resulting address would be 0x000000ff+0x12000000 +** = 0x120000ff +** +** There is no translation for inbound access (PCI device as a master) +** +** \return N/A +*/ + +#ifdef COMPRESSED_UBOOT +# define PCI_INIT_RET_TYPE int +# define PCI_INIT_RETURN return 0 +#else +# define PCI_INIT_RET_TYPE void +# define PCI_INIT_RETURN return +#endif + +PCI_INIT_RET_TYPE +pci_init_board (void) +{ + + /** + * We never used pci & pci-e, and sometimes should not initialize with + * it, or fail to startup + * 20141216 + */ + return 0; + +#ifdef CONFIG_ATH_EMULATION + prmsg("--- Skipping %s for emulation\n", __func__); +#else + uint32_t cmd; + + if (is_drqfn() && !is_qca953x()) { + /* + * Dont enable PCIe in DRQFN package as it has some issues + * related to PCIe + */ + PCI_INIT_RETURN; + } + +#if defined(CONFIG_MACH_QCA953x) + if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) { + ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); + + ath_reg_wr(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_RESET_1); + ath_reg_wr(PCIE_PHY_REG_3_ADDRESS, PCIE_PHY_REG_3_RESET_1); + + ath_reg_rmw_set(PCIE_PWR_MGMT_ADDRESS, PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(1)); + + ath_reg_rmw_set(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1)); + + ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); + ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); + + ath_reg_rmw_clear(RST_CLKGAT_EN_ADDRESS, RST_CLKGAT_EN_PCIE_RC_SET(1)); + + PCI_INIT_RETURN; + } else { + /* Honeybee -The PCIe reference clock frequency is being changed + to vary from 99.968MHz to 99.999MHz using SS modulation */ + ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS, + PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) | + PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) | + PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) | + PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff)); + + ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS, + PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84)| + PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17)); + } +#else + +#if defined(CONFIG_MACH_QCA956x) + + ath_reg_rmw_set(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_S_SET(PCIE_PHY_REG_1_S_RESET)); + + ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS, + PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) | + PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) | + PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff)); + + ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS, + PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84) | + PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17)); +#else + // common for rc1 and rc2 + ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS, + PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) | + PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) | + PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x14) | + PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3ff)); + + ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS, + PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x14)); +#endif + +#endif + + ath_reg_wr_nf(PCIE_PLL_CONFIG_ADDRESS, + PCIE_PLL_CONFIG_REFDIV_SET(1) | + PCIE_PLL_CONFIG_BYPASS_SET(1) | + PCIE_PLL_CONFIG_PLLPWD_SET(1)); + udelay(10000); + + ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1)); + udelay(1000); + ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_BYPASS_SET(1)); + udelay(1000); + +#if !defined(CONFIG_MACH_QCA956x) + +#ifdef PCIE2_APP_ADDRESS + if (!(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)) { + pci_rc2_init_board(); + return; + } +#endif + + ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); + udelay(10000); + + ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); + udelay(10000); + +#ifdef PCIE2_APP_ADDRESS + ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); + udelay(10000); +#endif + + ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0); // Put endpoint in reset + udelay(100000); + +#ifdef PCIE2_APP_ADDRESS + ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); + udelay(10000); +#endif + + ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); + udelay(10000); + + ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); + udelay(10000); + + ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) | + PCIE_APP_CFG_BE_SET(0xf) | + PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) | + PCIE_APP_LTSSM_ENABLE_SET(1)); + + cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; + + ath_local_write_config(PCI_COMMAND, 4, cmd); + ath_local_write_config(0x20, 4, 0x1ff01000); + ath_local_write_config(0x24, 4, 0x1ff01000); + + ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4); // Pull endpoint out of reset + udelay(100000); + + /* + * Check if the WLAN PCI-E H/W is present, If the + * WLAN H/W is not present, skip the PCI platform + * initialization code and return + */ + if (((ath_reg_rd(PCIE_RESET_ADDRESS)) & 0x1) == 0x0) { + prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n"); + } +#endif + +#ifdef PCIE2_APP_ADDRESS + pci_rc2_init_board(); +#endif + +#ifndef COMPRESSED_UBOOT + /* + * Now, configure for u-boot tools + */ + + hose.first_busno = 0; + hose.last_busno = 0xff; + + /* System space */ + pci_set_region( &hose.regions[0], + 0x80000000, + 0x00000000, + 32 * 1024 * 1024, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* PCI memory space */ + pci_set_region( &hose.regions[1], + 0x10000000, + 0x10000000, + 128 * 1024 * 1024, + PCI_REGION_MEM); + + hose.region_count = 2; + + pci_register_hose(&hose); + + pci_set_ops( &hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + ath_pci_read_config, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + ath_pci_write_config); +#endif + plat_dev_init(); +#endif /* CONFIG_ATH_EMULATION */ + + PCI_INIT_RETURN; +} + +#ifdef PCIE2_APP_ADDRESS +void +pci_rc2_init_board (void) +{ +#if defined(CONFIG_MACH_QCA956x) + ath_reg_rmw_clear(GPIO_OE_ADDRESS, 0x1); + udelay(10000); + ath_reg_rmw_set(GPIO_OUT_FUNCTION0_ADDRESS, GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(0x73)); + udelay(10000); + ath_reg_rmw_set(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) | + RST_RESET_PCIE_RESET_SET(1)); + + udelay(10000); + ath_reg_rmw_clear(RST_RESET_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) | + RST_RESET_PCIE_RESET_SET(1)); + + udelay(10000); + ath_reg_rmw_set(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) | + RST_RESET_PCIE_RESET_SET(1)); + + udelay(10000); + ath_reg_rmw_clear(RST_RESET2_ADDRESS,RST_RESET_PCIE_PHY_RESET_SET(1) | + RST_RESET_PCIE_RESET_SET(1)); + + udelay(10000); + ath_reg_wr(PCIE2_RESET_ADDRESS,PCIE2_RESET_EP_RESET_L_SET(1)); + udelay(10000); + ath_reg_wr(ATH_PCI_CRP_WRDATA,0x6); + udelay(10000); + ath_reg_wr(PCIE_APP_ADDRESS,PCIE_APP_LTSSM_ENABLE_SET(1) | + PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) | + PCIE_APP_CFG_BE_SET(0xf) | + PCIE_APP_PCIE_BAR_MSN_SET(1)); + udelay(10000); + ath_reg_wr(PCIE_INT_MASK_ADDRESS,PCIE_INT_MASK_CORR_ERR_SET(1) | + PCIE_INT_MASK_NONFATAL_ERR_SET(1) | + PCIE_INT_MASK_FATAL_ERR_SET(1) | + PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_SET(1) | + PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_SET(1) | + PCIE_INT_MASK_INTA_SET(1) | + PCIE_INT_MASK_INTB_SET(1) | + PCIE_INT_MASK_INTC_SET(1) | + PCIE_INT_MASK_INTD_SET(1) | + PCIE_INT_MASK_MSI_SET(1) | + PCIE_INT_MASK_MSI_ERR_SET(1) | + PCIE_INT_MASK_AER_INT_SET(1) | + PCIE_INT_MASK_AER_MSI_SET(1) | + PCIE_INT_MASK_SYS_ERR_SET(1) | + PCIE_INT_MASK_INTAL_SET(1) | + PCIE_INT_MASK_INTBL_SET(1) | + PCIE_INT_MASK_INTCL_SET(1) | + PCIE_INT_MASK_INTDL_SET(1)); + udelay(10000); + ath_local_write_config_rc2(0x70c, 4, 0x1b403200); + udelay(10000); + ath_reg_wr(PCIE_DEBUG_ADDRESS,PCIE_DEBUG_BYTESWAP_SET(1)); + udelay(10000); + + ath_reg_rmw_set(XTAL2_SEC_ADDRESS, XTAL2_SEC_SPARE_SET(0xc)); + udelay(10000); + ath_reg_rmw_clear(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KI_SET(0x3) | + PCIe_DPLL2_KD_SET(0xF)); + udelay(10000); + ath_reg_rmw_set(PCIe_DPLL2_ADDRESS, PCIe_DPLL2_KD_SET(0x4)); + udelay(10000); + +#else + + uint32_t cmd; + + ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_PHY_RESET_SET(1)); + udelay(10000); + + ath_reg_rmw_set(RST_RESET2_ADDRESS, RST_RESET2_PCIE2_RESET_SET(1)); + udelay(10000); + + ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1)); + udelay(10000); + + ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 0); // Put endpoint in reset + udelay(100000); + + ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY2_SET(1)); + udelay(10000); + + ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); + udelay(10000); + + ath_reg_rmw_clear(RST_RESET2_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); + udelay(10000); + + ath_reg_wr_nf(PCIE2_APP_ADDRESS, PCIE2_APP_PCIE2_BAR_MSN_SET(1) | + PCIE2_APP_CFG_BE_SET(0xf) | + PCIE2_APP_SLV_RESP_ERR_MAP_SET(0x3f) | + PCIE2_APP_LTSSM_ENABLE_SET(1)); + + cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | + PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; + + ath_local_write_config_rc2(PCI_COMMAND, 4, cmd); + ath_local_write_config_rc2(0x20, 4, 0x1ff01000); + ath_local_write_config_rc2(0x24, 4, 0x1ff01000); + + ath_reg_wr_nf(PCIE2_RESET_ADDRESS, 4); // Pull endpoint out of reset + udelay(100000); + +#endif + /* + * Check if the WLAN PCI-E H/W is present, If the + * WLAN H/W is not present, skip the PCI platform + * initialization code and return + */ + if (((ath_reg_rd(PCIE2_RESET_ADDRESS)) & 0x1) == 0x0) { + prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n"); + return; + } +} +#endif diff --git a/u-boot/board/ar7240/common/athr_s27_phy.c b/u-boot/board/ar7240/common/athr_s27_phy.c new file mode 100755 index 0000000..11d0a91 --- /dev/null +++ b/u-boot/board/ar7240/common/athr_s27_phy.c @@ -0,0 +1,875 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Manage the atheros ethernet PHY. + * + * All definitions in this file are operating system independent! + */ + +#include +#include +#include +#include + +#include +#include +#include "athr_s27_phy.h" + + +//#include "phy.h" !!!!!!!!!!!!!!!!!!!!!!!!!!!!! +#define ath_gmac_unit2name(_unit) (_unit ? "eth1" : "eth0") + +extern int ath_gmac_miiphy_read(char *devname, uint32_t phaddr, uint8_t reg, uint16_t *data); +extern int ath_gmac_miiphy_write(char *devname, uint32_t phaddr, uint8_t reg, uint16_t data); + +#define phy_reg_read(base, addr, reg) \ + ath_gmac_miiphy_read(ath_gmac_unit2name(base), addr, reg, NULL) + +#define phy_reg_write(base, addr, reg, data) \ + ath_gmac_miiphy_write(ath_gmac_unit2name(base), addr, reg, data) + + + + + + + +/* PHY selections and access functions */ + +typedef enum { + PHY_SRCPORT_INFO, + PHY_PORTINFO_SIZE, +} PHY_CAP_TYPE; + +typedef enum { + PHY_SRCPORT_NONE, + PHY_SRCPORT_VLANTAG, + PHY_SRCPORT_TRAILER, +} PHY_SRCPORT_TYPE; + +#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6) +#define DRV_MSG(x,a,b,c,d,e,f) +#define DRV_PRINT(DBG_SW,X) + +#define ATHR_LAN_PORT_VLAN 1 +#define ATHR_WAN_PORT_VLAN 2 +#define ENET_UNIT_LAN 1 +#define ENET_UNIT_WAN 0 + +#define TRUE 1 +#define FALSE 0 + +#define ATHR_PHY0_ADDR 0x0 +#define ATHR_PHY1_ADDR 0x1 +#define ATHR_PHY2_ADDR 0x2 +#define ATHR_PHY3_ADDR 0x3 +#define ATHR_PHY4_ADDR 0x4 + +#define MODULE_NAME "ATHRS27" + +/* + * Track per-PHY port information. + */ + + +typedef struct { + BOOL isEnetPort; /* normal enet port */ + BOOL isPhyAlive; /* last known state of link */ + int ethUnit; /* MAC associated with this phy port */ + uint32_t phyBase; + uint32_t phyAddr; /* PHY registers associated with this phy port */ + uint32_t VLANTableSetting; /* Value to be written to VLAN table */ +} athrPhyInfo_t; + +/* + * Per-PHY information, indexed by PHY unit number. + */ +static athrPhyInfo_t athrPhyInfo[] = { + + {TRUE, /* port 1 -- LAN port 1 */ + FALSE, + ENET_UNIT_LAN, + 0, + ATHR_PHY0_ADDR, + ATHR_LAN_PORT_VLAN + }, + + {TRUE, /* port 2 -- LAN port 2 */ + FALSE, + ENET_UNIT_LAN, + 0, + ATHR_PHY1_ADDR, + ATHR_LAN_PORT_VLAN + }, + + {TRUE, /* port 3 -- LAN port 3 */ + FALSE, + ENET_UNIT_LAN, + 0, + ATHR_PHY2_ADDR, + ATHR_LAN_PORT_VLAN + }, + + + {TRUE, /* port 4 -- LAN port 4 */ + FALSE, + ENET_UNIT_LAN, + 0, + ATHR_PHY3_ADDR, + ATHR_LAN_PORT_VLAN /* Send to all ports */ + }, + + {TRUE, /* port 5 -- WAN Port 5 */ + FALSE, + ENET_UNIT_WAN, + 0, + ATHR_PHY4_ADDR, + ATHR_LAN_PORT_VLAN /* Send to all ports */ + }, + + {FALSE, /* port 0 -- cpu port 0 */ + TRUE, + ENET_UNIT_LAN, + 0, + 0x00, + ATHR_LAN_PORT_VLAN + }, + +}; + + +#define ATHR_GLOBALREGBASE 0 + +#define ATHR_PHY_MAX 5 + +/* Range of valid PHY IDs is [MIN..MAX] */ +#define ATHR_ID_MIN 0 +#define ATHR_ID_MAX (ATHR_PHY_MAX-1) + + +/* Convenience macros to access myPhyInfo */ +#define ATHR_IS_ENET_PORT(phyUnit) (athrPhyInfo[phyUnit].isEnetPort) +#define ATHR_IS_PHY_ALIVE(phyUnit) (athrPhyInfo[phyUnit].isPhyAlive) +#define ATHR_ETHUNIT(phyUnit) (athrPhyInfo[phyUnit].ethUnit) +#define ATHR_PHYBASE(phyUnit) (athrPhyInfo[phyUnit].phyBase) +#define ATHR_PHYADDR(phyUnit) (athrPhyInfo[phyUnit].phyAddr) +#define ATHR_VLAN_TABLE_SETTING(phyUnit) (athrPhyInfo[phyUnit].VLANTableSetting) + + +#define ATHR_IS_ETHUNIT(phyUnit, ethUnit) \ + (ATHR_IS_ENET_PORT(phyUnit) && \ + ATHR_ETHUNIT(phyUnit) == (ethUnit)) + +#define ATHR_IS_WAN_PORT(phyUnit) (!(ATHR_ETHUNIT(phyUnit)==ENET_UNIT_LAN)) + +/* Forward references */ +BOOL athrs27_phy_is_link_alive(int phyUnit); +uint32_t athrs27_reg_read(uint32_t reg_addr); +void athrs27_reg_write(uint32_t reg_addr, uint32_t reg_val); +unsigned int s27_rd_phy(unsigned int phy_addr, unsigned int reg_addr); +void s27_wr_phy(unsigned int phy_addr, unsigned int reg_addr, unsigned int write_data); + + +void athrs27_powersave_off(int phy_addr) +{ + s27_wr_phy(phy_addr,ATHR_DEBUG_PORT_ADDRESS,0x29); + s27_wr_phy(phy_addr,ATHR_DEBUG_PORT_DATA,0x36c0); + +} +void athrs27_sleep_off(int phy_addr) +{ + s27_wr_phy(phy_addr,ATHR_DEBUG_PORT_ADDRESS,0xb); + s27_wr_phy(phy_addr,ATHR_DEBUG_PORT_DATA,0x3c00); +} + +void athrs27_force_100M(int phyAddr,int duplex) +{ + /* + * Force MDI and MDX to alternate ports + * Phy 0,2 and 4 -- MDI + * Phy 1 and 3 -- MDX + */ + + if(phyAddr%2) { + s27_wr_phy(phyAddr,ATHR_PHY_FUNC_CONTROL,0x820); + } + else { + s27_wr_phy(phyAddr,ATHR_PHY_FUNC_CONTROL,0x800); + } + + s27_wr_phy(phyAddr,0x1d,0x29); + s27_wr_phy(phyAddr,0x1e,0x0); + s27_wr_phy(phyAddr,0x10,0xc60); + s27_wr_phy(phyAddr,ATHR_PHY_CONTROL,(0xa000|(duplex << 8))); +} + +void athrs27_force_10M(int phyAddr,int duplex) +{ + + athrs27_powersave_off(phyAddr); + athrs27_sleep_off(phyAddr); + + s27_wr_phy(phyAddr,ATHR_PHY_CONTROL,(0x8000 |(duplex << 8))); +} + +int athrs27_reg_init(void) +{ +#if S27_PHY_DEBUG + uint32_t rd_val; +#endif + + /* if using header for register configuration, we have to */ + /* configure s27 register after frame transmission is enabled */ + athrs27_reg_rmw(0x8,(1<<28)); /* Set WAN port is connected to GE0 */ + +#if defined(S27_FORCE_100M) + athrs27_force_100M(ATHR_PHY4_ADDR,1); +#elif defined(S27_FORCE_10M) + athrs27_force_10M(ATHR_PHY4_ADDR,1); +#else + s27_wr_phy(ATHR_PHY4_ADDR,ATHR_PHY_CONTROL,0x9000); + +#endif +#ifdef S27_PHY_DEBUG + printf(MODULE_NAME":OPERATIONAL_MODE_REG0:%x\n",athrs27_reg_read(OPERATIONAL_MODE_REG0)); + printf(MODULE_NAME":REG 0x4-->:%x\n",athrs27_reg_read(0x4)); + printf(MODULE_NAME":REG 0x2c-->:%x\n",athrs27_reg_read(0x2c)); + printf(MODULE_NAME":REG 0x8-->:%x\n",athrs27_reg_read(0x8)); +#endif + + return 0; +} + +int athrs27_reg_init_lan(void) +{ + int i = 60; +#if S26_PHY_DEBUG + uint32_t rd_val; +#endif + int phyUnit; + uint32_t phyBase = 0; + BOOL foundPhy = FALSE; + uint32_t phyAddr = 0; + + + /* reset switch */ + printf(MODULE_NAME ": resetting s27\n"); + athrs27_reg_write(0x0, athrs27_reg_read(0x0)|0x80000000); + + while(i--) { + sysMsDelay(100); + if(!(athrs27_reg_read(0x0)&0x80000000)) + break; + } + printf(MODULE_NAME ": s27 reset done\n"); + athrs27_reg_write(PORT_STATUS_REGISTER0,0x4e); + + athrs27_reg_rmw(OPERATIONAL_MODE_REG0,(1<<6)); /* Set GMII mode */ + + if (is_emu() || is_wasp()) { + athrs27_reg_rmw(0x2c,((1<<26)| (1<<16) | 0x1)); /* FiX ME: EBU debug */ + } + + for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) { + + foundPhy = TRUE; + phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + +#if defined(S27_FORCE_100M) + athrs27_force_100M(phyAddr,1); +#elif defined(S27_FORCE_10M) + athrs27_force_10M(phyAddr,1); +#else + s27_wr_phy(phyAddr,ATHR_PHY_CONTROL,0x9000); +#endif + +#if S27_PHY_DEBUG + rd_val = s27_rd_phy(phyAddr,ATHR_PHY_FUNC_CONTROL); + printf("S27 ATHR_PHY_FUNC_CONTROL (%d):%x\n",phyAddr,rd_val); + rd_val = s27_rd_phy(phyAddr,ATHR_PHY_ID1); + printf("S27 PHY ID (%d) :%x\n",phyAddr, rd_val); + rd_val = s27_rd_phy(phyAddr,ATHR_PHY_SPEC_STATUS); + printf("S27 PHY CTRL (%d) :%x\n",phyAddr, rd_val); + rd_val = s27_rd_phy(phyAddr,ATHR_PHY_STATUS); + printf("S27 ATHR PHY STATUS (%d) :%x\n",phyAddr, rd_val); +#endif + } + + /* + * status[1:0]=2'h2; - (0x10 - 1000 Mbps , 0x01 - 100Mbps, 0x0 - 10 Mbps) + * status[2]=1'h1; - Tx Mac En + * status[3]=1'h1; - Rx Mac En + * status[4]=1'h1; - Tx Flow Ctrl En + * status[5]=1'h1; - Rx Flow Ctrl En + * status[6]=1'h1; - Duplex Mode + */ + athrs27_reg_write(PORT_STATUS_REGISTER1, 0x200); /* LAN - 1 */ + athrs27_reg_write(PORT_STATUS_REGISTER2, 0x200); /* LAN - 2 */ + athrs27_reg_write(PORT_STATUS_REGISTER3, 0x200); /* LAN - 3 */ + athrs27_reg_write(PORT_STATUS_REGISTER4, 0x200); /* LAN - 4 */ + + if (is_emu()) { + athrs27_reg_write(PORT_STATUS_REGISTER1, 0x4C); /* LAN - 1 */ + athrs27_reg_write(PORT_STATUS_REGISTER2, 0x4c); /* LAN - 2 */ + athrs27_reg_write(PORT_STATUS_REGISTER3, 0x4c); /* LAN - 3 */ + athrs27_reg_write(PORT_STATUS_REGISTER4, 0x4c); /* LAN - 4 */ + } + + /* QM Control */ + athrs27_reg_write(0x38, 0xc000050e); + + /* + * status[11]=1'h0; - CPU Disable + * status[7] = 1'b1; - Learn One Lock + * status[14] = 1'b0; - Learn Enable + */ +#ifdef ATHEROS_HEADER_EN + athrs27_reg_write(PORT_CONTROL_REGISTER0, 0x4804); +#else + /* Atheros Header Disable */ + athrs27_reg_write(PORT_CONTROL_REGISTER0, 0x4004); +#endif + + /* Tag Priority Mapping */ + athrs27_reg_write(0x70, 0xfa50); + + /* Enable ARP packets to CPU port */ + athrs27_reg_write(S27_ARL_TBL_CTRL_REG,(athrs27_reg_read(S27_ARL_TBL_CTRL_REG) | 0x100000)); + + /* Enable Broadcast packets to CPU port */ + athrs27_reg_write(S27_FLD_MASK_REG,(athrs27_reg_read(S27_FLD_MASK_REG) | + S27_ENABLE_CPU_BROADCAST | S27_ENABLE_CPU_BCAST_FWD )); + + return 0; +} + +/****************************************************************************** +* +* athrs27_phy_is_link_alive - test to see if the specified link is alive +* +* RETURNS: +* TRUE --> link is alive +* FALSE --> link is down +*/ +BOOL +athrs27_phy_is_link_alive(int phyUnit) +{ + uint16_t phyHwStatus; + uint32_t phyBase; + uint32_t phyAddr; + + phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_SPEC_STATUS); + + if (phyHwStatus & ATHR_STATUS_LINK_PASS) + return TRUE; + + return FALSE; +} + +/****************************************************************************** +* +* athrs27_phy_setup - reset and setup the PHY associated with +* the specified MAC unit number. +* +* Resets the associated PHY port. +* +* RETURNS: +* TRUE --> associated PHY is alive +* FALSE --> no LINKs on this ethernet unit +*/ +BOOL +athrs27_phy_setup(int ethUnit) +{ + int phyUnit; + uint16_t phyHwStatus; + uint16_t timeout; + int liveLinks = 0; + uint32_t phyBase = 0; + BOOL foundPhy = FALSE; + uint32_t phyAddr = 0; +//#if S27_PHY_DEBUG + uint32_t rd_val = 0; +//#endif + uint32_t ar7240_revid; + + + /* See if there's any configuration data for this enet */ + /* start auto negogiation on each phy */ + for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) { + + foundPhy = TRUE; + phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + + if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) { + continue; + } + if (!is_emu()) { + s27_wr_phy(phyAddr, ATHR_AUTONEG_ADVERT,ATHR_ADVERTISE_ALL); + + s27_wr_phy(phyAddr, ATHR_PHY_CONTROL,ATHR_CTRL_AUTONEGOTIATION_ENABLE + | ATHR_CTRL_SOFTWARE_RESET); + } + else { + printf("############ is emulation ############\n"); + + if(ATHR_ETHUNIT(phyUnit) == ENET_UNIT_WAN) { + s27_wr_phy(phyAddr, ATHR_AUTONEG_ADVERT,ATHR_ADVERTISE_ALL); + s27_wr_phy(phyAddr,0x9, 0x0); //donot advertise 1000Mbps mode + s27_wr_phy(phyAddr, ATHR_PHY_CONTROL,0x0); + s27_wr_phy(phyAddr, ATHR_PHY_CONTROL,ATHR_CTRL_AUTONEGOTIATION_ENABLE + | ATHR_CTRL_SOFTWARE_RESET); + } + else { + + s27_wr_phy(phyAddr, ATHR_AUTONEG_ADVERT,(ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE | + ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL)); + s27_wr_phy(phyAddr,0x9, 0x0); //donot advertise 1000Mbps mode + s27_wr_phy(phyAddr, ATHR_PHY_CONTROL,0x0); + s27_wr_phy(phyAddr, ATHR_PHY_CONTROL,ATHR_CTRL_AUTONEGOTIATION_ENABLE + | ATHR_CTRL_SOFTWARE_RESET); + } + } + rd_val = s27_rd_phy(phyAddr,ATHR_PHY_CONTROL); + printf("%s ATHR_PHY_CONTROL %d :%x\n",__func__,phyAddr,rd_val); + rd_val = s27_rd_phy(phyAddr,ATHR_PHY_SPEC_STATUS); + printf("%s ATHR_PHY_SPEC_STAUS %d :%x\n",__func__,phyAddr,rd_val); + } + if (!foundPhy) { + return FALSE; /* No PHY's configured for this ethUnit */ + } + + /* + * After the phy is reset, it takes a little while before + * it can respond properly. + */ + if (ethUnit == ENET_UNIT_LAN) + sysMsDelay(100); + else + sysMsDelay(300); + + /* + * Wait up to 3 seconds for ALL associated PHYs to finish + * autonegotiation. The only way we get out of here sooner is + * if ALL PHYs are connected AND finish autonegotiation. + */ + for (phyUnit=0; (phyUnit < ATHR_PHY_MAX) /*&& (timeout > 0) */; phyUnit++) { + if (ATHR_ETHUNIT(phyUnit) == ENET_UNIT_WAN) + continue; + + timeout=20; + for (;;) { + phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_CONTROL); + + if (ATHR_RESET_DONE(phyHwStatus)) { + DRV_PRINT(DRV_DEBUG_PHYSETUP, + ("Port %d, Neg Success\n", phyUnit)); + break; + } + if (timeout == 0) { + DRV_PRINT(DRV_DEBUG_PHYSETUP, + ("Port %d, Negogiation timeout\n", phyUnit)); + break; + } + if (--timeout == 0) { + DRV_PRINT(DRV_DEBUG_PHYSETUP, + ("Port %d, Negogiation timeout\n", phyUnit)); + break; + } + + sysMsDelay(150); + } + /* extend the cable length */ + s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_ADDRESS, 0x14); + s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_DATA, 0xf52); + + /* Force Class A setting phys */ + s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_ADDRESS, 4); + s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_DATA, 0xebbb); + s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_ADDRESS, 5); + s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_DATA, 0x2c47); + + /* fine-tune PHYs */ + s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_ADDRESS, 0x3c); + s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_DATA, 0x1c1); + s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_ADDRESS, 0x37); + s27_wr_phy(phyUnit, ATHR_DEBUG_PORT_DATA, 0xd600); + + +#ifdef S27_VER_1_0 + /* turn off power saving */ + s27_wr_phy(phyUnit, 29, 41); + s27_wr_phy(phyUnit, 30, 0); + printf("def_ S27_VER_1_0\n"); +#endif + } + + /* + * All PHYs have had adequate time to autonegotiate. + * Now initialize software status. + * + * It's possible that some ports may take a bit longer + * to autonegotiate; but we can't wait forever. They'll + * get noticed by mv_phyCheckStatusChange during regular + * polling activities. + */ + for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) { + if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) { + continue; + } + + if (athrs27_phy_is_link_alive(phyUnit)) { + liveLinks++; + ATHR_IS_PHY_ALIVE(phyUnit) = TRUE; + } else { + ATHR_IS_PHY_ALIVE(phyUnit) = FALSE; + } + DRV_PRINT(DRV_DEBUG_PHYSETUP, + ("eth%d: Phy Specific Status=%4.4x\n", + ethUnit, + s27_rd_phy(ATHR_PHYADDR(phyUnit),ATHR_PHY_SPEC_STATUS))); + } + + return (liveLinks > 0); +} + +/****************************************************************************** +* +* athrs27_phy_is_fdx - Determines whether the phy ports associated with the +* specified device are FULL or HALF duplex. +* +* RETURNS: +* 1 --> FULL +* 0 --> HALF +*/ +int +athrs27_phy_is_fdx(int ethUnit,int phyUnit) +{ + uint32_t phyBase; + uint32_t phyAddr; + uint16_t phyHwStatus; + int ii = 200; + + if (ethUnit == ENET_UNIT_LAN) + return TRUE; + + for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) { + if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) { + continue; + } + + if (athrs27_phy_is_link_alive(phyUnit)) { + + phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + + do { + phyHwStatus = s27_rd_phy (phyAddr, ATHR_PHY_SPEC_STATUS); + if(phyHwStatus & ATHR_STATUS_RESOVLED) + break; + sysMsDelay(10); + } while(--ii); + if (phyHwStatus & ATHER_STATUS_FULL_DUPLEX) { + return TRUE; + } + } + } + + return FALSE; +} +/****************************************************************************** +* +* athrs27_phy_speed - Determines the speed of phy ports associated with the +* specified device. +* +* RETURNS: +* ATHR_PHY_SPEED_10T, AG7240_PHY_SPEED_100T; +* ATHR_PHY_SPEED_1000T; +*/ + +int +athrs27_phy_speed(int ethUnit,int phyUnit) +{ + uint16_t phyHwStatus; + uint32_t phyBase; + uint32_t phyAddr; + int ii = 200; + int phySpeed; + for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) { + if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) { + continue; + } + + + phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + phySpeed = _10BASET; + + if (athrs27_phy_is_link_alive(phyUnit)) { + + do { + phyHwStatus = s27_rd_phy(phyAddr, + ATHR_PHY_SPEC_STATUS); + if(phyHwStatus & ATHR_STATUS_RESOVLED) + break; + sysMsDelay(10); + }while(--ii); + + phyHwStatus = ((phyHwStatus & ATHER_STATUS_LINK_MASK) >> + ATHER_STATUS_LINK_SHIFT); + + switch(phyHwStatus) { + case 0: + phySpeed = _10BASET; + break; + case 1: + phySpeed = _100BASET; + break; + case 2: + phySpeed = _1000BASET; + break; + default: + printf("Unkown speed read!\n"); + } + } + + phy_reg_write(1,phyAddr, ATHR_DEBUG_PORT_ADDRESS, 0x18); + + if(phySpeed == _100BASET) { + phy_reg_write(1,phyAddr, ATHR_DEBUG_PORT_DATA, 0xba8); + } else { + phy_reg_write(1,phyAddr, ATHR_DEBUG_PORT_DATA, 0x2ea); + } + } + + if (ethUnit == ENET_UNIT_LAN) + phySpeed = _1000BASET; + + return phySpeed; +} + +/***************************************************************************** +* +* athr_phy_is_up -- checks for significant changes in PHY state. +* +* A "significant change" is: +* dropped link (e.g. ethernet cable unplugged) OR +* autonegotiation completed + link (e.g. ethernet cable plugged in) +* +* When a PHY is plugged in, phyLinkGained is called. +* When a PHY is unplugged, phyLinkLost is called. +*/ + +int +athrs27_phy_is_up(int ethUnit) +{ + + uint16_t phyHwStatus, phyHwControl; + athrPhyInfo_t *lastStatus; + int linkCount = 0; + int lostLinks = 0; + int gainedLinks = 0; + uint32_t phyBase; + uint32_t phyAddr; + int phyUnit; + + for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) { + if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) { + continue; + } + + phyBase = ATHR_PHYBASE(phyUnit); + phyAddr = ATHR_PHYADDR(phyUnit); + + lastStatus = &athrPhyInfo[phyUnit]; + if (lastStatus->isPhyAlive) { /* last known link status was ALIVE */ + phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_SPEC_STATUS); + + /* See if we've lost link */ + if (phyHwStatus & ATHR_STATUS_LINK_PASS) { + linkCount++; + } else { + lostLinks++; + DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d down\n", + ethUnit, phyUnit)); + printf("enet%d port%d down\n",ethUnit, phyUnit); + lastStatus->isPhyAlive = FALSE; + } + } else { /* last known link status was DEAD */ + /* Check for reset complete */ + if(is_emu()) + { + phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_STATUS); + if(phyAddr%2) { + s27_wr_phy(phyAddr,ATHR_PHY_FUNC_CONTROL,0x820); + } + else { + s27_wr_phy(phyAddr,ATHR_PHY_FUNC_CONTROL,0x800); + } + + if((phyHwStatus & 0x4)==0) + { + s27_wr_phy(phyAddr,0x9,0x0); + if(phyAddr !=0x4) + s27_wr_phy(phyAddr,0x4,0x41); + s27_wr_phy(phyAddr,0x0,0x9000); + } + } + + phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_CONTROL); + if (!ATHR_RESET_DONE(phyHwStatus)) + continue; + + phyHwControl = s27_rd_phy(phyAddr, ATHR_PHY_CONTROL); + phyHwStatus = s27_rd_phy(phyAddr, ATHR_PHY_STATUS); + + /* Check for AutoNegotiation complete */ + if ((!(phyHwControl & ATHR_CTRL_AUTONEGOTIATION_ENABLE)) + || ATHR_AUTONEG_DONE(phyHwStatus)) { + phyHwStatus = s27_rd_phy(phyAddr, + ATHR_PHY_SPEC_STATUS); + + if (phyHwStatus & ATHR_STATUS_LINK_PASS) { + gainedLinks++; + linkCount++; + printf("enet%d port%d up\n",ethUnit, phyUnit); + DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d up\n", + ethUnit, phyUnit)); + lastStatus->isPhyAlive = TRUE; + } + } + } + } + return (linkCount); +} + +unsigned int athrs27_reg_read(unsigned int s27_addr) +{ + unsigned int addr_temp; + unsigned int s27_rd_csr_low, s27_rd_csr_high, s27_rd_csr; + unsigned int data,unit = 0; + unsigned int phy_address, reg_address; + + addr_temp = s27_addr >>2; + data = addr_temp >> 7; + + phy_address = 0x1f; + reg_address = 0x10; + + if (is_ar7240()) { + unit = 0; + } + else if(is_ar7241() || is_ar7242() || is_wasp() || is_qca953x() || is_qca956x()) { + unit = 1; + } + + phy_reg_write(unit,phy_address, reg_address, data); + + phy_address = (0x17 & ((addr_temp >> 4) | 0x10)); + reg_address = ((addr_temp << 1) & 0x1e); + s27_rd_csr_low = (uint32_t) phy_reg_read(unit,phy_address, reg_address); + + reg_address = reg_address | 0x1; + s27_rd_csr_high = (uint32_t) phy_reg_read(unit,phy_address, reg_address); + s27_rd_csr = (s27_rd_csr_high << 16) | s27_rd_csr_low ; + + return(s27_rd_csr); +} + +void athrs27_reg_write(unsigned int s27_addr, unsigned int s27_write_data) +{ + unsigned int addr_temp; + unsigned int data; + unsigned int phy_address, reg_address,unit = 0; + + addr_temp = (s27_addr ) >>2; + data = addr_temp >> 7; + + phy_address = 0x1f; + reg_address = 0x10; + + if (is_ar7240()) { + unit = 0; + } + else if(is_ar7241() || is_ar7242() || is_wasp() || is_qca953x() || is_qca956x()) { + unit = 1; + } + phy_reg_write(unit,phy_address, reg_address, data); + + phy_address = (0x17 & ((addr_temp >> 4) | 0x10)); + + reg_address = (((addr_temp << 1) & 0x1e) | 0x1); + data = (s27_write_data >> 16) & 0xffff; + phy_reg_write(unit,phy_address, reg_address, data); + + reg_address = ((addr_temp << 1) & 0x1e); + data = s27_write_data & 0xffff; + phy_reg_write(unit,phy_address, reg_address, data); + +} + +void athrs27_reg_rmw(unsigned int s27_addr, unsigned int s27_write_data) +{ + int val = athrs27_reg_read(s27_addr); + athrs27_reg_write(s27_addr,(val | s27_write_data)); +} + +unsigned int s27_rd_phy(unsigned int phy_addr, unsigned int reg_addr) +{ + int unit, val = 0; + + if (is_ar7240()) { + unit = 0; + } else if(is_ar7241() || is_ar7242() || is_wasp() || is_qca953x() || is_qca956x()) { + unit = 1; + } + val = (uint32_t) phy_reg_read(unit, phy_addr, reg_addr); + return val; +} + +void s27_wr_phy(unsigned int phy_addr, unsigned int reg_addr, unsigned int write_data) +{ + int unit; + + if (is_ar7240()) { + unit = 0; + } else if(is_ar7241() || is_ar7242() || is_wasp() || is_qca953x() || is_qca956x()) { + unit = 1; + } + + phy_reg_write(unit, phy_addr, reg_addr, write_data); +} +int athrs27_mdc_check() +{ + int i; + + for (i=0; i<4000; i++) { + if(athrs27_reg_read(0x10c) != 0x18007fff) + return -1; + } + return 0; +} + diff --git a/u-boot/board/ar7240/common/athr_s27_phy.h b/u-boot/board/ar7240/common/athr_s27_phy.h new file mode 100755 index 0000000..623c75e --- /dev/null +++ b/u-boot/board/ar7240/common/athr_s27_phy.h @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ATHRS27_PHY_H +#define _ATHRS27_PHY_H + + +/*****************/ +/* PHY Registers */ +/*****************/ +#define ATHR_PHY_CONTROL 0 +#define ATHR_PHY_STATUS 1 +#define ATHR_PHY_ID1 2 +#define ATHR_PHY_ID2 3 +#define ATHR_AUTONEG_ADVERT 4 +#define ATHR_LINK_PARTNER_ABILITY 5 +#define ATHR_AUTONEG_EXPANSION 6 +#define ATHR_NEXT_PAGE_TRANSMIT 7 +#define ATHR_LINK_PARTNER_NEXT_PAGE 8 +#define ATHR_1000BASET_CONTROL 9 +#define ATHR_1000BASET_STATUS 10 +#define ATHR_PHY_FUNC_CONTROL 16 +#define ATHR_PHY_SPEC_STATUS 17 +#define ATHR_DEBUG_PORT_ADDRESS 29 +#define ATHR_DEBUG_PORT_DATA 30 +#define ATHR_PHY_INTR_ENABLE 0x12 +#define ATHR_PHY_INTR_STATUS 0x13 + +/* ATHR_PHY_CONTROL fields */ +#define ATHR_CTRL_SOFTWARE_RESET 0x8000 +#define ATHR_CTRL_SPEED_LSB 0x2000 +#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000 +#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200 +#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100 +#define ATHR_CTRL_SPEED_MSB 0x0040 + +#define ATHR_RESET_DONE(phy_control) \ + (((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0) + +/* Phy status fields */ +#define ATHR_STATUS_AUTO_NEG_DONE 0x0020 + +#define ATHR_AUTONEG_DONE(ip_phy_status) \ + (((ip_phy_status) & \ + (ATHR_STATUS_AUTO_NEG_DONE)) == \ + (ATHR_STATUS_AUTO_NEG_DONE)) + +/* Link Partner ability */ +#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100 +#define ATHR_LINK_100BASETX 0x0080 +#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040 +#define ATHR_LINK_10BASETX 0x0020 + +/* Advertisement register. */ +#define ATHR_ADVERTISE_NEXT_PAGE 0x8000 +#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800 +#define ATHR_ADVERTISE_PAUSE 0x0400 +#define ATHR_ADVERTISE_100FULL 0x0100 +#define ATHR_ADVERTISE_100HALF 0x0080 +#define ATHR_ADVERTISE_10FULL 0x0040 +#define ATHR_ADVERTISE_10HALF 0x0020 + +#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE | \ + ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \ + ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL) + +/* 1000BASET_CONTROL */ +#define ATHR_ADVERTISE_1000FULL 0x0200 +#define ATHR_ADVERTISE_1000HALF 0x0100 + +/* Phy Specific status fields */ +#define ATHER_STATUS_LINK_MASK 0xC000 +#define ATHER_STATUS_LINK_SHIFT 14 +#define ATHER_STATUS_FULL_DUPLEX 0x2000 +#define ATHR_STATUS_LINK_PASS 0x0400 +#define ATHR_LATCH_LINK_PASS 0x0004 +#define ATHR_STATUS_RESOVLED 0x0800 + +/*phy debug port register */ +#define ATHER_DEBUG_SERDES_REG 5 + +/* Serdes debug fields */ +#define ATHER_SERDES_BEACON 0x0100 + +#define OPERATIONAL_MODE_REG0 0x4 + +/* S27 CSR Registers */ + +#define PORT_STATUS_REGISTER0 0x0100 +#define PORT_STATUS_REGISTER1 0x0200 +#define PORT_STATUS_REGISTER2 0x0300 +#define PORT_STATUS_REGISTER3 0x0400 +#define PORT_STATUS_REGISTER4 0x0500 +#define PORT_STATUS_REGISTER5 0x0600 + +#define RATE_LIMIT_REGISTER0 0x010C +#define RATE_LIMIT_REGISTER1 0x020C +#define RATE_LIMIT_REGISTER2 0x030C +#define RATE_LIMIT_REGISTER3 0x040C +#define RATE_LIMIT_REGISTER4 0x050C +#define RATE_LIMIT_REGISTER5 0x060C + +#define PORT_CONTROL_REGISTER0 0x0104 +#define PORT_CONTROL_REGISTER1 0x0204 +#define PORT_CONTROL_REGISTER2 0x0304 +#define PORT_CONTROL_REGISTER3 0x0404 +#define PORT_CONTROL_REGISTER4 0x0504 +#define PORT_CONTROL_REGISTER5 0x0604 + +#define CPU_PORT_REGISTER 0x0078 +#define MDIO_CTRL_REGISTER 0x0098 + +#define S27_ARL_TBL_FUNC_REG0 0x0050 +#define S27_ARL_TBL_FUNC_REG1 0x0054 +#define S27_ARL_TBL_FUNC_REG2 0x0058 +#define S27_FLD_MASK_REG 0x002c +#define S27_ARL_TBL_CTRL_REG 0x005c +#define S27_GLOBAL_INTR_REG 0x10 +#define S27_GLOBAL_INTR_MASK_REG 0x14 + + +#define S27_ENABLE_CPU_BROADCAST (1 << 26) +#define S27_ENABLE_CPU_BCAST_FWD (1 << 25) + +#define PHY_LINK_CHANGE_REG 0x4 +#define PHY_LINK_UP 0x400 +#define PHY_LINK_DOWN 0x800 +#define PHY_LINK_DUPLEX_CHANGE 0x2000 +#define PHY_LINK_SPEED_CHANGE 0x4000 +#define PHY_LINK_INTRS (PHY_LINK_UP | PHY_LINK_DOWN | PHY_LINK_DUPLEX_CHANGE | PHY_LINK_SPEED_CHANGE) + +/* SWITCH QOS REGISTERS */ + +#define ATHR_QOS_PORT_0 0x110 /* CPU PORT */ +#define ATHR_QOS_PORT_1 0x210 +#define ATHR_QOS_PORT_2 0x310 +#define ATHR_QOS_PORT_3 0x410 +#define ATHR_QOS_PORT_4 0x510 + +#define ATHR_ENABLE_TOS (1 << 16) + +#define ATHR_QOS_MODE_REGISTER 0x030 +#define ATHR_QOS_FIXED_PRIORITY ((0 << 31) | (0 << 28)) +#define ATHR_QOS_WEIGHTED ((1 << 31) | (0 << 28)) /* Fixed weight 8,4,2,1 */ +#define ATHR_QOS_MIXED ((1 << 31) | (1 << 28)) /* Q3 for managment; Q2,Q1,Q0 - 4,2,1 */ + +#ifndef BOOL +#define BOOL int +#endif + +#define sysMsDelay(_x) udelay((_x) * 1000) +#define mdelay(_x) sysMsDelay(_x) + +#undef S27_VER_1_0 + +/* + * Atheros header defines + */ +#ifndef _ATH_HEADER_CONF +#define _ATH_HEADER_CONF + +typedef enum { + NORMAL_PACKET, + RESERVED0, + MIB_1ST, + RESERVED1, + RESERVED2, + READ_WRITE_REG, + READ_WRITE_REG_ACK, + RESERVED3 +} AT_HEADER_TYPE; + +typedef struct { + uint16_t reserved0 :2; + uint16_t priority :2; + uint16_t type :4; + uint16_t broadcast :1; + uint16_t from_cpu :1; + uint16_t reserved1 :2; + uint16_t port_num :4; +}at_header_t; + +#define ATHR_HEADER_LEN 2 + +#endif // _ATH_HEADER_CONF + +typedef enum { + PORT_EG_UNMODIFIED = 0, /**< egress transmit packets unmodified */ + PORT_EG_UNTAGGED, /**< egress transmit packets without vlan tag */ + PORT_EG_TAGGED, /**< egress transmit packets with vlan tag */ +} port_1q_egmode_t; + +extern void set_packet_inspection_flag(int flag); + +#endif diff --git a/u-boot/board/ar7240/common/init-953x.c b/u-boot/board/ar7240/common/init-953x.c new file mode 100755 index 0000000..30fbb67 --- /dev/null +++ b/u-boot/board/ar7240/common/init-953x.c @@ -0,0 +1,395 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include + + +#define ATH_MAX_DDR_SIZE (256 * 1024 * 1024) +#define ATH_DDR_SIZE_INCR (4 * 1024 * 1024) + +int +ath_ddr_find_size(void) +{ + uint8_t *p = (uint8_t *)KSEG1, pat = 0x77; + int i; + +#define max_i (ATH_MAX_DDR_SIZE / ATH_DDR_SIZE_INCR) + + *p = pat; + + /* + * DDR wraps around. Write a pattern to 0x0000_0000. Write an + * address pattern at 4M, 8M, 16M etc. and check when + * 0x0000_0000 gets overwritten. + */ + for(i = 1; (i < max_i); i++) { + *(p + i * ATH_DDR_SIZE_INCR) = (uint8_t)(i); + if (*p != pat) { + break; + } + } + + return ((i < max_i) ? (i * ATH_DDR_SIZE_INCR) : ATH_MAX_DDR_SIZE); +} + +inline int +ath_ram_type(uint32_t bs) +{ + if (RST_BOOTSTRAP_DDR_SELECT_GET(bs)) { + return ATH_MEM_DDR1; + } else { + return ATH_MEM_DDR2; + } +} + +#define CFG_DDR2_SCORPION_CAS_LATENCY 4 + +#ifdef CONFIG_TB614 +# define DDR_CONFIG2_SWAP_A26_A27_VAL (0x1) +#else +# define DDR_CONFIG2_SWAP_A26_A27_VAL (0x0) +#endif + +#if CFG_DDR2_SCORPION_CAS_LATENCY == 4 +#define CFG_DDR2_CONFIG_VAL DDR_CONFIG_CAS_LATENCY_MSB_SET(0x1) | \ + DDR_CONFIG_OPEN_PAGE_SET(0x1) | \ + DDR_CONFIG_CAS_LATENCY_SET(0x1) | \ + DDR_CONFIG_TMRD_SET(0xf) | \ + DDR_CONFIG_TRFC_SET(0x15) | \ + DDR_CONFIG_TRRD_SET(0x7) | \ + DDR_CONFIG_TRP_SET(0x9) | \ + DDR_CONFIG_TRCD_SET(0x9) | \ + DDR_CONFIG_TRAS_SET(0x1b) + +#define CFG_DDR2_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \ + DDR_CONFIG2_SWAP_A26_A27_SET(DDR_CONFIG2_SWAP_A26_A27_VAL) | \ + DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0x8) | \ + DDR_CONFIG2_TWTR_SET(0x15) | \ + DDR_CONFIG2_TRTP_SET(0x9) | \ + DDR_CONFIG2_TRTW_SET(0xe) | \ + DDR_CONFIG2_TWR_SET(0x1) | \ + DDR_CONFIG2_CKE_SET(0x1) | \ + DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \ + DDR_CONFIG2_BURST_LENGTH_SET(0x8) + +#define CFG_DDR2_CONFIG3_VAL 0x0000000a +#define CFG_DDR2_EXT_MODE_VAL 0x402 +#define CFG_DDR2_MODE_VAL_INIT 0x143 +#define CFG_DDR2_MODE_VAL 0x43 +#define CFG_DDR2_TAP_VAL 0x10 +#define CFG_DDR2_EN_TWL_VAL 0x0000167d +#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff +#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff + +#elif CFG_DDR2_SCORPION_CAS_LATENCY == 5 + +#define CFG_DDR2_CONFIG_VAL DDR_CONFIG_CAS_LATENCY_MSB_SET(0x1) | \ + DDR_CONFIG_OPEN_PAGE_SET(0x1) | \ + DDR_CONFIG_CAS_LATENCY_SET(0x4) | \ + DDR_CONFIG_TMRD_SET(0xf) | \ + DDR_CONFIG_TRFC_SET(0x15) | \ + DDR_CONFIG_TRRD_SET(0x7) | \ + DDR_CONFIG_TRP_SET(0x9) | \ + DDR_CONFIG_TRCD_SET(0x9) | \ + DDR_CONFIG_TRAS_SET(0x1b) + +#define CFG_DDR2_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \ + DDR_CONFIG2_SWAP_A26_A27_SET(DDR_CONFIG2_SWAP_A26_A27_VAL) | \ + DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0xb) | \ + DDR_CONFIG2_TWTR_SET(0x15) | \ + DDR_CONFIG2_TRTP_SET(0x9) | \ + DDR_CONFIG2_TRTW_SET(0xe) | \ + DDR_CONFIG2_TWR_SET(0x1) | \ + DDR_CONFIG2_CKE_SET(0x1) | \ + DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \ + DDR_CONFIG2_BURST_LENGTH_SET(0x8) + +#define CFG_DDR2_CONFIG3_VAL 0x0000000a +#define CFG_DDR2_EXT_MODE_VAL 0x402 +#define CFG_DDR2_MODE_VAL_INIT 0x153 +#define CFG_DDR2_MODE_VAL 0x53 +#define CFG_DDR2_TAP_VAL 0x10 +#define CFG_DDR2_EN_TWL_VAL 0x00001e7d +#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16 0xffff +#define CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_32 0xff +#endif + +#define CFG_DDR1_CONFIG_VAL DDR_CONFIG_OPEN_PAGE_SET(0x1) | \ + DDR_CONFIG_CAS_LATENCY_SET(0x7) | \ + DDR_CONFIG_TMRD_SET(0x5) | \ + DDR_CONFIG_TRFC_SET(0x7) | \ + DDR_CONFIG_TRRD_SET(0x4) | \ + DDR_CONFIG_TRP_SET(0x6) | \ + DDR_CONFIG_TRCD_SET(0x6) | \ + DDR_CONFIG_TRAS_SET(0x10) + +#define CFG_DDR1_CONFIG2_VAL DDR_CONFIG2_HALF_WIDTH_LOW_SET(0x1) | \ + DDR_CONFIG2_GATE_OPEN_LATENCY_SET(0x6) | \ + DDR_CONFIG2_TWTR_SET(0xe) | \ + DDR_CONFIG2_TRTP_SET(0x8) | \ + DDR_CONFIG2_TRTW_SET(0xe) | \ + DDR_CONFIG2_TWR_SET(0xd) | \ + DDR_CONFIG2_CKE_SET(0x1) | \ + DDR_CONFIG2_CNTL_OE_EN_SET(0x1) | \ + DDR_CONFIG2_BURST_LENGTH_SET(0x8) +#define CFG_DDR1_CONFIG3_VAL 0x0 +#define CFG_DDR1_EXT_MODE_VAL 0x0 +#define CFG_DDR1_MODE_VAL_INIT 0x133 +#define CFG_DDR1_MODE_VAL 0x33 +#define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL_16 0xffff +#define CFG_DDR1_RD_DATA_THIS_CYCLE_VAL_32 0xff +#define CFG_DDR1_TAP_VAL 0x20 + +#define CFG_DDR_CTL_CONFIG DDR_CTL_CONFIG_SRAM_TSEL_SET(0x1) | \ + DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(0x1) | \ + DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(0x1) | \ + DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(0x1) | \ + DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(0x1) | \ + DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(0x1) + +int /* ram type */ +ath_ddr_initial_config(uint32_t refresh) +{ +#if !defined(CONFIG_ATH_EMULATION) + int ddr_config, ddr_config2, ddr_config3, ext_mod, mod_val, + mod_val_init, cycle_val, tap_val, type, ctl_config; + uint32_t *pll = (unsigned *)PLL_CONFIG_VAL_F; + uint32_t bootstrap,revid; + + prmsg("\nsri\n"); + if(((revid=ath_reg_rd(RST_REVISION_ID_ADDRESS))&0xff0)==0x140) + prmsg("Honey Bee 1.%d\n", revid & 0xf); + else + prmsg("Honey Bee 2.%d\n", revid & 0xf); + + bootstrap = ath_reg_rd(RST_BOOTSTRAP_ADDRESS); + + switch(type = ath_ram_type(bootstrap)) { + case ATH_MEM_DDR2: + ddr_config = CFG_DDR2_CONFIG_VAL; + ddr_config2 = CFG_DDR2_CONFIG2_VAL; + ddr_config3 = CFG_DDR2_CONFIG3_VAL; + ext_mod = CFG_DDR2_EXT_MODE_VAL; + mod_val_init = CFG_DDR2_MODE_VAL_INIT; + mod_val = CFG_DDR2_MODE_VAL; + tap_val = CFG_DDR2_TAP_VAL; + + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x10); + udelay(10); + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x20); + udelay(10); + prmsg("%s(%d): (", __func__, __LINE__); + + prmsg("16"); + ctl_config = CFG_DDR_CTL_CONFIG | + CPU_DDR_SYNC_MODE | + DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(0x1) | + DDR_CTL_CONFIG_HALF_WIDTH_SET(0x1); + + cycle_val = CFG_DDR2_RD_DATA_THIS_CYCLE_VAL_16; + + ath_reg_wr_nf(DDR_CTL_CONFIG_ADDRESS, ctl_config); + + prmsg("bit) ddr2 init\n"); + udelay(10); + break; + case ATH_MEM_DDR1: + ddr_config = CFG_DDR1_CONFIG_VAL; + ddr_config2 = CFG_DDR1_CONFIG2_VAL; + ddr_config3 = CFG_DDR1_CONFIG3_VAL; + ext_mod = CFG_DDR1_EXT_MODE_VAL; + mod_val_init = CFG_DDR1_MODE_VAL_INIT; + mod_val = CFG_DDR1_MODE_VAL; + tap_val = CFG_DDR1_TAP_VAL; + + prmsg("%s(%d): (", __func__, __LINE__); + prmsg("16"); + cycle_val = CFG_DDR1_RD_DATA_THIS_CYCLE_VAL_16; + + ctl_config = CFG_DDR_CTL_CONFIG | + CPU_DDR_SYNC_MODE | + DDR_CTL_CONFIG_HALF_WIDTH_SET(0x1); + + ath_reg_wr_nf(DDR_CTL_CONFIG_ADDRESS, ctl_config); + udelay(10); + prmsg("bit) ddr1 init\n"); + + break; + } + + ath_reg_wr_nf(DDR_RD_DATA_THIS_CYCLE_ADDRESS, cycle_val); + udelay(100); + ath_reg_wr_nf(DDR_BURST_ADDRESS, 0x74444444); + udelay(100); + ath_reg_wr_nf(DDR_BURST2_ADDRESS, 0x4); + udelay(100); + ath_reg_wr_nf(DDR_AHB_MASTER_TIMEOUT_MAX_ADDRESS, 0xfffff); + udelay(100); + ath_reg_wr_nf(DDR_CONFIG_ADDRESS, ddr_config); + udelay(100); + ath_reg_wr_nf(DDR_CONFIG2_ADDRESS, ddr_config2); + udelay(100); + ath_reg_wr(DDR_CONFIG_3_ADDRESS, ddr_config3); + udelay(100); + + if (type == ATH_MEM_DDR2) { + ath_reg_wr_nf(DDR2_CONFIG_ADDRESS, CFG_DDR2_EN_TWL_VAL); + udelay(100); + } + + ath_reg_wr_nf(DDR_CONFIG2_ADDRESS, ddr_config2 | 0x80); // CKE Enable + udelay(100); + + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x8); // Precharge + udelay(10); + + if (type == ATH_MEM_DDR2) { + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x10); // EMR2 + udelay(10); + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x20); // EMR3 + udelay(10); + } + + if (type == ATH_MEM_DDR1 || type == ATH_MEM_DDR2) { + ath_reg_wr_nf(DDR_EXTENDED_MODE_REGISTER_ADDRESS, CFG_DDR2_EXT_MODE_VAL); // EMR DLL enable, Reduced Driver Impedance control, Differential DQS disabled + udelay(100); + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x2); // EMR write + udelay(10); + } + + ath_reg_wr_nf(DDR_MODE_REGISTER_ADDRESS, mod_val_init); + udelay(1000); + + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x1); // MR Write + udelay(10); + + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x8); // Precharge + udelay(10); + + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x4); // Auto Refresh + udelay(10); + + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x4); // Auto Refresh + udelay(10); + + // Issue MRS to remove DLL out-of-reset + ath_reg_wr_nf(DDR_MODE_REGISTER_ADDRESS, mod_val); + udelay(100); + + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x1); // MR write + udelay(100); + + if (type == ATH_MEM_DDR2) { + ath_reg_wr_nf(DDR_EXTENDED_MODE_REGISTER_ADDRESS, 0x782); + udelay(100); + + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x2); // EMR write + udelay(100); + + ath_reg_wr_nf(DDR_EXTENDED_MODE_REGISTER_ADDRESS, CFG_DDR2_EXT_MODE_VAL); + udelay(100); + + ath_reg_wr_nf(DDR_CONTROL_ADDRESS, 0x2); // EMR write + udelay(100); + } + + ath_reg_wr_nf(DDR_REFRESH_ADDRESS, refresh); + udelay(100); + + ath_reg_wr(TAP_CONTROL_0_ADDRESS, tap_val); + ath_reg_wr(TAP_CONTROL_1_ADDRESS, tap_val); + + ath_reg_wr(PMU1_ADDRESS, 0x633c8178); + // Set DDR2 Voltage to 1.8 volts + ath_reg_wr(PMU2_ADDRESS, PMU2_SWREGMSB_SET(0x40) | PMU2_PGM_SET(0x1) | PMU2_LDO_TUNE_SET(0x0)); + return type; +#else // !emulation + return 0; +#endif +} + +int +ath_uart_freq(void) +{ + //if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_REF_CLK_MASK) { + // return 40 * 1000 * 1000; + //} else { + return 25 * 1000 * 1000; + //} +} + +void +ath_sys_frequency(uint32_t *cpu, uint32_t *ddr, uint32_t *ahb) +{ +#if !defined(CONFIG_ATH_EMULATION) + uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl; +#endif + uint32_t ref; + static uint32_t ath_cpu_freq, ath_ddr_freq, ath_ahb_freq; + + if (ath_cpu_freq) + goto done; + +#ifdef CONFIG_ATH_EMULATION + ath_cpu_freq = 80000000; + ath_ddr_freq = 80000000; + ath_ahb_freq = 40000000; +#else + prmsg("%s: ", __func__); + + clk_ctrl = ath_reg_rd(ATH_DDR_CLK_CTRL); + + pll = ath_reg_rd(ATH_PLL_CONFIG); + out_div = CPU_PLL_CONFIG_OUTDIV_GET(pll); + ref_div = CPU_PLL_CONFIG_REFDIV_GET(pll); + nint = CPU_PLL_CONFIG_NINT_GET(pll); + frac = CPU_PLL_CONFIG_NFRAC_GET(pll); + pll = ref >> 6; + frac = frac * pll / ref_div; + prmsg("cpu apb "); + ath_cpu_freq = (((nint * (ref / ref_div)) + frac) >> out_div) / + (CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(clk_ctrl) + 1); + + pll = ath_reg_rd(ATH_DDR_PLL_CONFIG); + out_div = DDR_PLL_CONFIG_OUTDIV_GET(pll); + ref_div = DDR_PLL_CONFIG_REFDIV_GET(pll); + nint = DDR_PLL_CONFIG_NINT_GET(pll); + frac = DDR_PLL_CONFIG_NFRAC_GET(pll); + pll = ref >> 10; + frac = frac * pll / ref_div; + prmsg("ddr apb "); + ath_ddr_freq = (((nint * (ref / ref_div)) + frac) >> out_div) / + (CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(clk_ctrl) + 1); + + if (CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) { + ath_ahb_freq = ath_ddr_freq / + (CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(clk_ctrl) + 1); + } else { + ath_ahb_freq = ath_cpu_freq / + (CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(clk_ctrl) + 1); + } +#endif + prmsg("cpu %u ddr %u ahb %u\n", + ath_cpu_freq / 1000000, + ath_ddr_freq / 1000000, + ath_ahb_freq / 1000000); +done: + *cpu = ath_cpu_freq; + *ddr = ath_ddr_freq; + *ahb = ath_ahb_freq; +} diff --git a/u-boot/board/ar7240/common/qca-eth-953x.c b/u-boot/board/ar7240/common/qca-eth-953x.c new file mode 100755 index 0000000..6fb86f1 --- /dev/null +++ b/u-boot/board/ar7240/common/qca-eth-953x.c @@ -0,0 +1,706 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "qca-eth-953x.h" +#include "qca-eth-953x_phy.h" +#define SGMII_LINK_WAR_MAX_TRY 10 + +#if (CONFIG_COMMANDS & CFG_CMD_MII) +#include +#endif +#define ath_gmac_unit2mac(_unit) ath_gmac_macs[(_unit)] +#define ath_gmac_name2mac(name) is_drqfn() ? ath_gmac_unit2mac(1):strcmp(name,"eth0") ? ath_gmac_unit2mac(1) : ath_gmac_unit2mac(0) + +int ath_gmac_miiphy_read(char *devname, uint32_t phaddr, uint8_t reg, uint16_t *data); +int ath_gmac_miiphy_write(char *devname, uint32_t phaddr, uint8_t reg, uint16_t data); +extern void ath_sys_frequency(uint32_t *, uint32_t *, uint32_t *); + +#ifndef CFG_ATH_GMAC_NMACS +#define CFG_ATH_GMAC_NMACS 1 +#endif /* CFG_ATH_GMAC_NMACS */ + +ath_gmac_mac_t *ath_gmac_macs[CFG_ATH_GMAC_NMACS]; + + + +#ifdef CFG_ATHRS27_PHY +#define is_s27() 1 + +#else +#define is_s27() 0 + +#endif +#ifdef CFG_ATHRS27_PHY +extern void athrs27_reg_init(void); +extern void athrs27_reg_init_wan(void); +#endif + +#ifdef CONFIG_VIR_PHY +extern int athr_vir_phy_setup(int unit); +extern int athr_vir_phy_is_up(int unit); +extern int athr_vir_phy_is_fdx(int unit); +extern int athr_vir_phy_speed(int unit); +extern void athr_vir_reg_init(void); +#endif + +static int +ath_gmac_send(struct eth_device *dev, volatile void *packet, int length) +{ + int i; + + ath_gmac_mac_t *mac = (ath_gmac_mac_t *)dev->priv; + + ath_gmac_desc_t *f = mac->fifo_tx[mac->next_tx]; + + f->pkt_size = length; + f->res1 = 0; + f->pkt_start_addr = virt_to_phys(packet); + + ath_gmac_tx_give_to_dma(f); + flush_cache((u32) packet, length); + ath_gmac_reg_wr(mac, ATH_DMA_TX_DESC, virt_to_phys(f)); + ath_gmac_reg_wr(mac, ATH_DMA_TX_CTRL, ATH_TXE); + + for (i = 0; i < MAX_WAIT; i++) { + udelay(10); + if (!ath_gmac_tx_owned_by_dma(f)) + break; + } + if (i == MAX_WAIT) + printf("Tx Timed out\n"); + + f->pkt_start_addr = 0; + f->pkt_size = 0; + + if (++mac->next_tx >= NO_OF_TX_FIFOS) + mac->next_tx = 0; + + return (0); +} + +static int ath_gmac_recv(struct eth_device *dev) +{ + int length; + ath_gmac_desc_t *f; + ath_gmac_mac_t *mac; + volatile int dmaed_pkt=0; + int count = 0; + + mac = (ath_gmac_mac_t *)dev->priv; + + for (;;) { + f = mac->fifo_rx[mac->next_rx]; + if (ath_gmac_rx_owned_by_dma(f)) { + /* check if the current Descriptor is_empty is 1,But the DMAed count is not-zero + then move to desciprot where the packet is available */ + dmaed_pkt = (ath_gmac_reg_rd(mac, 0x194) >> 16); + if (!dmaed_pkt) { + break ; + } else { + if (f->is_empty == 1) { + while (count < NO_OF_RX_FIFOS) { + if (++mac->next_rx >= NO_OF_RX_FIFOS) { + mac->next_rx = 0; + } + f = mac->fifo_rx[mac->next_rx]; + /* + * Break on valid data in the desc by checking + * empty bit. + */ + if (!f->is_empty) { + count = 0; + break; + } + count++; + } + } + } + } + + length = f->pkt_size; + + NetReceive(NetRxPackets[mac->next_rx] , length - 4); + flush_cache((u32) NetRxPackets[mac->next_rx] , PKTSIZE_ALIGN); + + ath_gmac_reg_wr(mac,0x194,1); + ath_gmac_rx_give_to_dma(f); + + if (++mac->next_rx >= NO_OF_RX_FIFOS) + mac->next_rx = 0; + } + + if (!(ath_gmac_reg_rd(mac, ATH_DMA_RX_CTRL))) { + ath_gmac_reg_wr(mac, ATH_DMA_RX_DESC, virt_to_phys(f)); + ath_gmac_reg_wr(mac, ATH_DMA_RX_CTRL, 1); + } + + return (0); +} + +void ath_gmac_mii_setup(ath_gmac_mac_t *mac) +{ + u32 mgmt_cfg_val; + + ath_reg_wr(SWITCH_CLOCK_SPARE_ADDRESS, 0x231); + //ath_reg_wr(SWITCH_CLOCK_SPARE_ADDRESS, 0x520); + if ((mac->mac_unit == 1)) { + printf("Honey Bee ----> MAC 1 S27 PHY *\n"); + ath_reg_wr(ATH_ETH_CFG, ETH_CFG_ETH_RXDV_DELAY_SET(3) | + ETH_CFG_ETH_RXD_DELAY_SET(3)| + ETH_CFG_RGMII_GE0_SET(1)); + + ath_reg_wr(ETH_XMII_ADDRESS, ETH_XMII_TX_INVERT_SET(1) | + ETH_XMII_RX_DELAY_SET(2) | + ETH_XMII_TX_DELAY_SET(1) | + ETH_XMII_GIGE_SET(1)); + mgmt_cfg_val = 2; + udelay(1000); + ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val); + return; + } + + if (is_vir_phy()) { + printf("Honey Bee ---->VIR PHY*\n"); + + ath_reg_wr(ATH_ETH_CFG, ETH_CFG_ETH_RXDV_DELAY_SET(3) | + ETH_CFG_ETH_RXD_DELAY_SET(3)| + ETH_CFG_RGMII_GE0_SET(1)); + ath_reg_wr(ETH_XMII_ADDRESS, ETH_XMII_TX_INVERT_SET(1) | + ETH_XMII_RX_DELAY_SET(2) | + ETH_XMII_TX_DELAY_SET(1) | + ETH_XMII_GIGE_SET(1)); + udelay(1000); + ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val); + + return; + } + if (is_s27()) { + mgmt_cfg_val = 2; + printf("Scorpion ---->S27 PHY*\n"); + ath_reg_wr(ETH_CFG_ADDRESS, ETH_CFG_MII_GE0_SET(1)| + ETH_CFG_MII_GE0_SLAVE_SET(1)); + udelay(1000); + ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31)); + ath_gmac_reg_wr(mac, ATH_MAC_MII_MGMT_CFG, mgmt_cfg_val); + + } + + + + +} + + +static void ath_gmac_hw_start(ath_gmac_mac_t *mac) +{ + + + if(mac->mac_unit) + { + ath_gmac_reg_rmw_set(mac, ATH_MAC_CFG2, (ATH_MAC_CFG2_PAD_CRC_EN | + ATH_MAC_CFG2_LEN_CHECK | ATH_MAC_CFG2_IF_1000)); + } else { + + + ath_gmac_reg_rmw_set(mac, ATH_MAC_CFG2, (ATH_MAC_CFG2_PAD_CRC_EN | + ATH_MAC_CFG2_LEN_CHECK | ATH_MAC_CFG2_IF_10_100)); + } + ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_0, 0x1f00); + + + ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_1, 0x10ffff); + ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_2, 0xAAA0555); + + ath_gmac_reg_rmw_set(mac, ATH_MAC_FIFO_CFG_4, 0x3ffff); + /* + * Setting Drop CRC Errors, Pause Frames,Length Error frames + * and Multi/Broad cast frames. + */ + + ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_5, 0x7eccf); + + ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_3, 0x1f00140); + + printf(": cfg1 %#x cfg2 %#x\n", ath_gmac_reg_rd(mac, ATH_MAC_CFG1), + ath_gmac_reg_rd(mac, ATH_MAC_CFG2)); + + +} + +static int ath_gmac_check_link(ath_gmac_mac_t *mac) +{ + int link, duplex, speed; + + ath_gmac_phy_link(mac->mac_unit, &link); + ath_gmac_phy_duplex(mac->mac_unit, &duplex); + ath_gmac_phy_speed(mac->mac_unit, &speed); + + mac->link = link; + + if(!mac->link) { + printf("%s link down\n",mac->dev->name); + return 0; + } + + switch (speed) + { + case _1000BASET: + ath_gmac_set_mac_if(mac, 1); + ath_gmac_reg_rmw_set(mac, ATH_MAC_FIFO_CFG_5, (1 << 19)); + break; + + case _100BASET: + ath_gmac_set_mac_if(mac, 0); + ath_gmac_set_mac_speed(mac, 1); + ath_gmac_reg_rmw_clear(mac, ATH_MAC_FIFO_CFG_5, (1 << 19)); + break; + + case _10BASET: + ath_gmac_set_mac_if(mac, 0); + ath_gmac_set_mac_speed(mac, 0); + ath_gmac_reg_rmw_clear(mac, ATH_MAC_FIFO_CFG_5, (1 << 19)); + break; + + default: + printf("Invalid speed detected\n"); + return 0; + } + + if (mac->link && (duplex == mac->duplex) && (speed == mac->speed)) + return 1; + + mac->duplex = duplex; + mac->speed = speed; + + printf("dup %d speed %d\n", duplex, speed); + + ath_gmac_set_mac_duplex(mac,duplex); + + return 1; +} + +/* + * For every command we re-setup the ring and start with clean h/w rx state + */ +static int ath_gmac_clean_rx(struct eth_device *dev, bd_t * bd) +{ + + int i; + ath_gmac_desc_t *fr; + ath_gmac_mac_t *mac = (ath_gmac_mac_t*)dev->priv; + + if (!ath_gmac_check_link(mac)) + return 0; + + mac->next_rx = 0; + + ath_gmac_reg_wr(mac, ATH_MAC_FIFO_CFG_0, 0x1f00); + ath_gmac_reg_wr(mac, ATH_MAC_CFG1, (ATH_MAC_CFG1_RX_EN | ATH_MAC_CFG1_TX_EN)); + + for (i = 0; i < NO_OF_RX_FIFOS; i++) { + fr = mac->fifo_rx[i]; + fr->pkt_start_addr = virt_to_phys(NetRxPackets[i]); + flush_cache((u32) NetRxPackets[i], PKTSIZE_ALIGN); + ath_gmac_rx_give_to_dma(fr); + } + + ath_gmac_reg_wr(mac, ATH_DMA_RX_DESC, virt_to_phys(mac->fifo_rx[0])); + ath_gmac_reg_wr(mac, ATH_DMA_RX_CTRL, ATH_RXE); /* rx start */ + udelay(1000 * 1000); + + + return 1; + +} + +static int ath_gmac_alloc_fifo(int ndesc, ath_gmac_desc_t ** fifo) +{ + int i; + u32 size; + uchar *p = NULL; + + size = sizeof(ath_gmac_desc_t) * ndesc; + size += CFG_CACHELINE_SIZE - 1; + + if ((p = malloc(size)) == NULL) { + printf("Cant allocate fifos\n"); + return -1; + } + + p = (uchar *) (((u32) p + CFG_CACHELINE_SIZE - 1) & + ~(CFG_CACHELINE_SIZE - 1)); + p = UNCACHED_SDRAM(p); + + for (i = 0; i < ndesc; i++) + fifo[i] = (ath_gmac_desc_t *) p + i; + + return 0; +} + +static int ath_gmac_setup_fifos(ath_gmac_mac_t *mac) +{ + int i; + + if (ath_gmac_alloc_fifo(NO_OF_TX_FIFOS, mac->fifo_tx)) + return 1; + + for (i = 0; i < NO_OF_TX_FIFOS; i++) { + mac->fifo_tx[i]->next_desc = (i == NO_OF_TX_FIFOS - 1) ? + virt_to_phys(mac->fifo_tx[0]) : virt_to_phys(mac->fifo_tx[i + 1]); + ath_gmac_tx_own(mac->fifo_tx[i]); + } + + if (ath_gmac_alloc_fifo(NO_OF_RX_FIFOS, mac->fifo_rx)) + return 1; + + for (i = 0; i < NO_OF_RX_FIFOS; i++) { + mac->fifo_rx[i]->next_desc = (i == NO_OF_RX_FIFOS - 1) ? + virt_to_phys(mac->fifo_rx[0]) : virt_to_phys(mac->fifo_rx[i + 1]); + } + + return (1); +} + +static void ath_gmac_halt(struct eth_device *dev) +{ + ath_gmac_mac_t *mac = (ath_gmac_mac_t *)dev->priv; + ath_gmac_reg_rmw_clear(mac, ATH_MAC_CFG1,(ATH_MAC_CFG1_RX_EN | ATH_MAC_CFG1_TX_EN)); + ath_gmac_reg_wr(mac,ATH_MAC_FIFO_CFG_0,0x1f1f); + ath_gmac_reg_wr(mac,ATH_DMA_RX_CTRL, 0); + while (ath_gmac_reg_rd(mac, ATH_DMA_RX_CTRL)); +} + +unsigned char * +ath_gmac_mac_addr_loc(void) +{ +#ifdef BOARDCAL + /* + ** BOARDCAL environmental variable has the address of the cal sector + */ + + return ((unsigned char *)BOARDCAL); + +#else + /* MAC address is store in the 2nd 4k of last sector */ + return ((unsigned char *) + (KSEG1ADDR(ATH_SPI_BASE) + (4 * 1024) + + flash_info[0].size - (64 * 1024) /* sector_size */ )); +#endif +} + +static void ath_gmac_get_ethaddr(struct eth_device *dev) +{ + unsigned char *eeprom; + unsigned char *mac = dev->enetaddr; +#ifndef CONFIG_ATH_EMULATION + + eeprom = ath_gmac_mac_addr_loc(); + + if (strcmp(dev->name, "eth0") == 0) { + memcpy(mac, eeprom, 6); + } else if (strcmp(dev->name, "eth1") == 0) { + eeprom += 6; + memcpy(mac, eeprom, 6); + } else { + printf("%s: unknown ethernet device %s\n", __func__, dev->name); + return; + } + /* Use fixed address if the above address is invalid */ + if (mac[0] != 0x00 || (mac[0] == 0xff && mac[5] == 0xff)) +#else + if (1) +#endif + { + mac[0] = 0xba; + mac[1] = 0xbe; + mac[2] = 0xfa; + mac[3] = 0xce; + mac[4] = 0x08; + mac[5] = 0x41; + /*printf("No valid address in Flash. Using fixed address\n");*/ + } else { + printf("Fetching MAC Address from 0x%p\n", __func__, eeprom); + } +} + +void +athr_mgmt_init(void) +{ + +#ifdef CONFIG_MGMT_INIT + uint32_t rddata; + + rddata = ath_reg_rd(GPIO_IN_ENABLE3_ADDRESS)& + ~GPIO_IN_ENABLE3_MII_GE1_MDI_MASK; + rddata |= GPIO_IN_ENABLE3_MII_GE1_MDI_SET(19); + ath_reg_wr(GPIO_IN_ENABLE3_ADDRESS, rddata); + + ath_reg_rmw_clear(GPIO_OE_ADDRESS, (1 << 19)); + + ath_reg_rmw_clear(GPIO_OE_ADDRESS, (1 << 17)); + + + rddata = ath_reg_rd(GPIO_OUT_FUNCTION4_ADDRESS) & + ~ (GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK | + GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK); + + rddata |= GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(0x20) | + GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(0x21); + + ath_reg_wr(GPIO_OUT_FUNCTION4_ADDRESS, rddata); +#endif + printf ("%s ::done\n",__func__); +} + +int ath_gmac_enet_initialize(bd_t * bis) +{ + struct eth_device *dev[CFG_ATH_GMAC_NMACS]; + u32 mask, mac_h, mac_l; + int i; + + printf("%s...\n", __func__); + + /* Switch Analog and digital reset seq */ + mask = ATH_RESET_GE1_PHY | ATH_RESET_GE0_PHY; + ath_reg_rmw_set(RST_RESET_ADDRESS, mask); + + udelay(1000 * 100); + mask = ATH_RESET_GE1_PHY ; + ath_reg_rmw_clear(RST_RESET_ADDRESS, mask); + + udelay(1000 * 100); + mask = ATH_RESET_GE0_PHY ; + ath_reg_rmw_clear(RST_RESET_ADDRESS, mask); + udelay(100); + + + for (i = 0;i < CFG_ATH_GMAC_NMACS;i++) { + + if ((dev[i] = (struct eth_device *) malloc(sizeof (struct eth_device))) == NULL) { + puts("malloc failed\n"); + return 0; + } + + if ((ath_gmac_macs[i] = (ath_gmac_mac_t *) malloc(sizeof (ath_gmac_mac_t))) == NULL) { + puts("malloc failed\n"); + return 0; + } + + memset(ath_gmac_macs[i], 0, sizeof(ath_gmac_macs[i])); + memset(dev[i], 0, sizeof(dev[i])); + + sprintf(dev[i]->name, "eth%d", i); + ath_gmac_get_ethaddr(dev[i]); + + ath_gmac_macs[i]->mac_unit = i; + ath_gmac_macs[i]->mac_base = i ? ATH_GE1_BASE : ATH_GE0_BASE ; + ath_gmac_macs[i]->dev = dev[i]; + + dev[i]->iobase = 0; + dev[i]->init = ath_gmac_clean_rx; + dev[i]->halt = ath_gmac_halt; + dev[i]->send = ath_gmac_send; + dev[i]->recv = ath_gmac_recv; + dev[i]->priv = (void *)ath_gmac_macs[i]; + } + + for (i = 0;i < CFG_ATH_GMAC_NMACS;i++) { + + if(!i) { + mask = (ATH_RESET_GE0_MAC | ATH_RESET_GE1_MAC | ATH_RESET_GE0_MDIO | ATH_RESET_GE1_MDIO); + + + printf("%s: reset mask:%x \n", __func__, mask); + + ath_reg_rmw_set(RST_RESET_ADDRESS, mask); + udelay(1000 * 100); + + mask = mask | ATH_RESET_GE0_MDIO | ATH_RESET_GE1_MDIO; + ath_reg_rmw_clear(RST_RESET_ADDRESS, mask); + udelay(1000 * 100); + + udelay(10 * 1000); + } +#if defined(CONFIG_MGMT_INIT) && defined (CONFIG_ATHR_SWITCH_ONLY_MODE) || defined ATH_MDC_GPIO + if (!i) + athr_mgmt_init(); + + if (ath_gmac_macs[i]->mac_unit == 0) + continue; +#endif + eth_register(dev[i]); +#if(CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register(dev[i]->name, ath_gmac_miiphy_read, ath_gmac_miiphy_write); +#endif + ath_gmac_mii_setup(ath_gmac_macs[i]); + + /* if using header for register configuration, we have to */ + /* configure s26 register after frame transmission is enabled */ + + if (ath_gmac_macs[i]->mac_unit == 0) { /* WAN Phy */ +#ifdef CFG_ATHRS27_PHY + printf("S27 reg init\n"); + athrs27_reg_init(); + mask = ATH_RESET_GE0_MAC; + ath_reg_rmw_clear(RST_RESET_ADDRESS, mask); +#endif + +#ifdef CONFIG_VIR_PHY + printf("VIRPhy reg init \n"); + athr_vir_reg_init(); +#endif + } else { +#ifdef CFG_ATHRS27_PHY + printf("S27 reg init\n"); + athrs27_reg_init_lan(); + mask = ATH_RESET_GE1_MAC; + ath_reg_rmw_clear(RST_RESET_ADDRESS, mask); +#endif + + } + + ath_gmac_reg_rmw_set(ath_gmac_macs[i], ATH_MAC_CFG1, ATH_MAC_CFG1_SOFT_RST + | ATH_MAC_CFG1_RX_RST | ATH_MAC_CFG1_TX_RST); + + + ath_gmac_hw_start(ath_gmac_macs[i]); + ath_gmac_setup_fifos(ath_gmac_macs[i]); + + + + udelay(100 * 1000); + + { + unsigned char *mac = dev[i]->enetaddr; + + printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name, + mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, + mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff); + } + mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]); + mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | + (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0); + + ath_gmac_reg_wr(ath_gmac_macs[i], ATH_GE_MAC_ADDR1, mac_l); + ath_gmac_reg_wr(ath_gmac_macs[i], ATH_GE_MAC_ADDR2, mac_h); + + + ath_gmac_phy_setup(ath_gmac_macs[i]->mac_unit); + printf("%s up\n",dev[i]->name); + } + + + return 1; +} + +//#if (CONFIG_COMMANDS & CFG_CMD_MII) +int +ath_gmac_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t *data) +{ + ath_gmac_mac_t *mac = ath_gmac_name2mac(devname); + uint16_t addr = (phy_addr << ATH_ADDR_SHIFT) | reg, val; + volatile int rddata; + uint16_t ii = 0xFFFF; + + + /* + * Check for previous transactions are complete. Added to avoid + * race condition while running at higher frequencies. + */ + do + { + udelay(5); + rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1; + }while(rddata && --ii); + + if (ii == 0) + printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__); + + + ath_gmac_reg_wr(mac, ATH_MII_MGMT_CMD, 0x0); + ath_gmac_reg_wr(mac, ATH_MII_MGMT_ADDRESS, addr); + ath_gmac_reg_wr(mac, ATH_MII_MGMT_CMD, ATH_MGMT_CMD_READ); + + do + { + udelay(5); + rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1; + }while(rddata && --ii); + + if(ii==0) + printf("Error!!! Leave ath_gmac_miiphy_read without polling correct status!\n"); + + val = ath_gmac_reg_rd(mac, ATH_MII_MGMT_STATUS); + ath_gmac_reg_wr(mac, ATH_MII_MGMT_CMD, 0x0); + + if (data != NULL) + *data = val; + + return val; +} + +int +ath_gmac_miiphy_write(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t data) +{ + ath_gmac_mac_t *mac = ath_gmac_name2mac(devname); + uint16_t addr = (phy_addr << ATH_ADDR_SHIFT) | reg; + volatile int rddata; + uint16_t ii = 0xFFFF; + + + /* + * Check for previous transactions are complete. Added to avoid + * race condition while running at higher frequencies. + */ + do { + udelay(5); + rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1; + } while (rddata && --ii); + + if (ii == 0) + printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__); + + ath_gmac_reg_wr(mac, ATH_MII_MGMT_ADDRESS, addr); + ath_gmac_reg_wr(mac, ATH_MII_MGMT_CTRL, data); + + do { + rddata = ath_gmac_reg_rd(mac, ATH_MII_MGMT_IND) & 0x1; + } while (rddata && --ii); + + if (ii == 0) + printf("Error!!! Leave ath_gmac_miiphy_write without polling correct status!\n"); + + return 0; +} +//#endif /* CONFIG_COMMANDS & CFG_CMD_MII */ diff --git a/u-boot/board/ar7240/common/qca-eth-953x.h b/u-boot/board/ar7240/common/qca-eth-953x.h new file mode 100755 index 0000000..fee0249 --- /dev/null +++ b/u-boot/board/ar7240/common/qca-eth-953x.h @@ -0,0 +1,371 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __QCA_ETH_953X_H +#define __QCA_ETH_953X_H + +#include + +#ifdef ATH_RGMII_CAL +#define rgmii_cal_alg() rgmii_calib(mac); +#else +#define rgmii_cal_alg() +#endif + +/* + * h/w descriptor + */ +typedef struct { + uint32_t pkt_start_addr, + is_empty : 1, + res1 : 10, + ftpp_override : 5, + res2 : 4, + pkt_size : 12, + next_desc; +} ath_gmac_desc_t; + +#define NO_OF_TX_FIFOS 8 +#define NO_OF_RX_FIFOS 8 + +typedef struct { + ath_gmac_desc_t *fifo_tx[NO_OF_TX_FIFOS], + *fifo_rx[NO_OF_RX_FIFOS]; + struct eth_device *dev; + uint32_t next_tx, + next_rx, + link, + duplex, + speed, + mac_unit, + mac_base; +} ath_gmac_mac_t; + +#define ath_gmac_reg_wr(_mac, _x, _y) ath_reg_wr(((_x) + _mac->mac_base), (_y)) +#define ath_gmac_reg_rd(_mac, _x) ath_reg_rd(((_x) + _mac->mac_base)) + +#define ath_gmac_reg_rmw_set(_mac, _x, _y) \ + ath_reg_rmw_set(((_x) + _mac->mac_base ), (_y)) +#define ath_gmac_reg_rmw_clear(_mac, _x, _y) \ + ath_reg_rmw_clear(((_x) + _mac->mac_base), (_y)) + +#ifdef COMPRESSED_UBOOT +#define _1000BASET 1000 +#define _100BASET 100 +#define _10BASET 10 +#endif /* #ifdef COMPRESSED_UBOOT */ + +/* + * spd is _1000BASET, _100BASET etc. defined in include/miiphy.h + */ +#define mii_reg(_mac) (ATH_MII0_CTRL + ((_mac)->mac_unit * 4)) +#define mii_if(_mac) (((_mac)->mac_unit == 0) ? mii0_if : mii1_if) + +#define ath_gmac_set_mii_ctrl_speed(_mac, _spd) do { \ + ath_reg_rmw_clear(mii_reg(_mac), (3 << 4)); \ + ath_reg_rmw_set(mii_reg(_mac), ((_spd) << 4)); \ +} while (0) + +#if defined (CFG_MII0_GMII) +# define ath_gmac_get_mii_if() 0 +#elif defined (CFG_MII0_MII) +# define ath_gmac_get_mii_if() 0 +#elif defined (CFG_MII0_RGMII) +# define ath_gmac_get_mii_if() 0 +#elif defined (CFG_MII0_RMII) +# define ath_gmac_get_mii_if() 0 +#endif + +#define MAX_WAIT 1000 + +/* + * Config/Mac Register definitions + */ +#define ATH_MAC_CFG1 0x00 +#define ATH_MAC_CFG2 0x04 +#define ATH_MAC_IFCTL 0x38 + +/* + * fifo control registers + */ +#define ATH_MAC_FIFO_CFG_0 0x48 +#define ATH_MAC_FIFO_CFG_1 0x4c +#define ATH_MAC_FIFO_CFG_2 0x50 +#define ATH_MAC_FIFO_CFG_3 0x54 +#define ATH_MAC_FIFO_CFG_4 0x58 + +#define ATH_MAC_FIFO_CFG_5 0x5c +#define ATH_BYTE_PER_CLK_EN (1 << 19) + +#define ATH_MAC_FIFO_RAM_0 0x60 +#define ATH_MAC_FIFO_RAM_1 0x64 +#define ATH_MAC_FIFO_RAM_2 0x68 +#define ATH_MAC_FIFO_RAM_3 0x6c +#define ATH_MAC_FIFO_RAM_4 0x70 +#define ATH_MAC_FIFO_RAM_5 0x74 +#define ATH_MAC_FIFO_RAM_6 0x78 +#define ATH_MAC_FIFO_RAM_7 0x7c + +/* + * fields + */ +#define ATH_MAC_CFG1_SOFT_RST (1 << 31) +#define ATH_MAC_CFG1_RX_RST (1 << 19) +#define ATH_MAC_CFG1_TX_RST (1 << 18) +#define ATH_MAC_CFG1_LOOPBACK (1 << 8) +#define ATH_MAC_CFG1_RX_EN (1 << 2) +#define ATH_MAC_CFG1_TX_EN (1 << 0) + +#define ATH_MAC_CFG2_FDX (1 << 0) +#define ATH_MAC_CFG2_PAD_CRC_EN (1 << 2) +#define ATH_MAC_CFG2_LEN_CHECK (1 << 4) +#define ATH_MAC_CFG2_HUGE_FRAME_EN (1 << 5) +#define ATH_MAC_CFG2_IF_1000 (1 << 9) +#define ATH_MAC_CFG2_IF_10_100 (1 << 8) + +#define ATH_MAC_IFCTL_SPEED (1 << 16) + +/* + * DMA (tx/rx) register defines + */ +#define ATH_DMA_TX_CTRL 0x180 +#define ATH_DMA_TX_DESC 0x184 +#define ATH_DMA_TX_STATUS 0x188 +#define ATH_DMA_RX_CTRL 0x18c +#define ATH_DMA_RX_DESC 0x190 +#define ATH_DMA_RX_STATUS 0x194 +#define ATH_DMA_INTR_MASK 0x198 +#define ATH_DMA_INTR 0x19c + +/* + * tx/rx ctrl and status bits + */ +#define ATH_TXE (1 << 0) +#define ATH_TX_STATUS_PKTCNT_SHIFT 16 +#define ATH_TX_STATUS_PKT_SENT 0x1 +#define ATH_TX_STATUS_URN 0x2 +#define ATH_TX_STATUS_BUS_ERROR 0x8 + +#define ATH_RXE (1 << 0) + +#define ATH_RX_STATUS_PKTCNT_MASK 0xff0000 +#define ATH_RX_STATUS_PKT_RCVD (1 << 0) +#define ATH_RX_STATUS_OVF (1 << 2) +#define ATH_RX_STATUS_BUS_ERROR (1 << 3) + +/* + * Int and int mask + */ +#define ATH_INTR_TX (1 << 0) +#define ATH_INTR_TX_URN (1 << 1) +#define ATH_INTR_TX_BUS_ERROR (1 << 3) +#define ATH_INTR_RX (1 << 4) +#define ATH_INTR_RX_OVF (1 << 6) +#define ATH_INTR_RX_BUS_ERROR (1 << 7) + +/* + * MII registers + */ +#define ATH_MAC_MII_MGMT_CFG 0x20 +#define ATH_MGMT_CFG_CLK_DIV_20 0x07 + +#define ATH_MII_MGMT_CMD 0x24 +#define ATH_MGMT_CMD_READ 0x1 + +#define ATH_MII_MGMT_ADDRESS 0x28 +#define ATH_ADDR_SHIFT 8 + +#define ATH_MII_MGMT_CTRL 0x2c +#define ATH_MII_MGMT_STATUS 0x30 + +#define ATH_MII_MGMT_IND 0x34 +#define ATH_MGMT_IND_BUSY (1 << 0) +#define ATH_MGMT_IND_INVALID (1 << 2) + +#define ATH_GE_MAC_ADDR1 0x40 +#define ATH_GE_MAC_ADDR2 0x44 + +/* + * Ethernet config registers + */ +#define ATH_ETH_CFG 0x18070000 +#define ATH_ETH_CFG_RGMII_GE0 (1<<0) +#define ATH_ETH_CFG_MII_GE0 (1<<1) +#define ATH_ETH_CFG_GMII_GE0 (1<<2) +#define ATH_ETH_CFG_RMII_GE0 (1<<10) +#define ATH_ETH_CFG_RMII_HISPD_GE0 (1<<11) +#define ATH_ETH_CFG_RMII_MASTER_MODE (1<<12) +#define ATH_ETH_CFG_MII_GE0_MASTER (1<<3) +#define ATH_ETH_CFG_MII_GE0_SLAVE (1<<4) +#define ATH_ETH_CFG_GE0_ERR_EN (1<<5) +#define ATH_ETH_CFG_SW_ONLY_MODE (1<<6) +#define ATH_ETH_CFG_SW_PHY_SWAP (1<<7) +#define ATH_ETH_CFG_SW_PHY_ADDR_SWAP (1<<8) +#define ATH_ETH_CFG_RXD_DELAY (1 << 14) +#define ATH_ETH_CFG_RDV_DELAY (1 << 16) +#define ATH_ETH_SWITCH_CLK_SPARE 0x18050024 + +#define ETH_CFG_ETH_SPARE_MSB 31 +#define ETH_CFG_ETH_SPARE_LSB 22 +#define ETH_CFG_ETH_SPARE_MASK 0xffc00000 +#define ETH_CFG_ETH_SPARE_GET(x) (((x) & ETH_CFG_ETH_SPARE_MASK) >> ETH_CFG_ETH_SPARE_LSB) +#define ETH_CFG_ETH_SPARE_SET(x) (((x) << ETH_CFG_ETH_SPARE_LSB) & ETH_CFG_ETH_SPARE_MASK) +#define ETH_CFG_ETH_SPARE_RESET 0x0 // 0 +#define ETH_CFG_ETH_TXEN_DELAY_MSB 21 +#define ETH_CFG_ETH_TXEN_DELAY_LSB 20 +#define ETH_CFG_ETH_TXEN_DELAY_MASK 0x00300000 +#define ETH_CFG_ETH_TXEN_DELAY_GET(x) (((x) & ETH_CFG_ETH_TXEN_DELAY_MASK) >> ETH_CFG_ETH_TXEN_DELAY_LSB) +#define ETH_CFG_ETH_TXEN_DELAY_SET(x) (((x) << ETH_CFG_ETH_TXEN_DELAY_LSB) & ETH_CFG_ETH_TXEN_DELAY_MASK) +#define ETH_CFG_ETH_TXEN_DELAY_RESET 0x0 // 0 +#define ETH_CFG_ETH_TXD_DELAY_MSB 19 +#define ETH_CFG_ETH_TXD_DELAY_LSB 18 +#define ETH_CFG_ETH_TXD_DELAY_MASK 0x000c0000 +#define ETH_CFG_ETH_TXD_DELAY_GET(x) (((x) & ETH_CFG_ETH_TXD_DELAY_MASK) >> ETH_CFG_ETH_TXD_DELAY_LSB) +#define ETH_CFG_ETH_TXD_DELAY_SET(x) (((x) << ETH_CFG_ETH_TXD_DELAY_LSB) & ETH_CFG_ETH_TXD_DELAY_MASK) +#define ETH_CFG_ETH_TXD_DELAY_RESET 0x0 // 0 +#define ETH_CFG_ETH_RXDV_DELAY_MSB 17 +#define ETH_CFG_ETH_RXDV_DELAY_LSB 16 +#define ETH_CFG_ETH_RXDV_DELAY_MASK 0x00030000 +#define ETH_CFG_ETH_RXDV_DELAY_GET(x) (((x) & ETH_CFG_ETH_RXDV_DELAY_MASK) >> ETH_CFG_ETH_RXDV_DELAY_LSB) +#define ETH_CFG_ETH_RXDV_DELAY_SET(x) (((x) << ETH_CFG_ETH_RXDV_DELAY_LSB) & ETH_CFG_ETH_RXDV_DELAY_MASK) +#define ETH_CFG_ETH_RXDV_DELAY_RESET 0x0 // 0 +#define ETH_CFG_ETH_RXD_DELAY_MSB 15 +#define ETH_CFG_ETH_RXD_DELAY_LSB 14 +#define ETH_CFG_ETH_RXD_DELAY_MASK 0x0000c000 +#define ETH_CFG_ETH_RXD_DELAY_GET(x) (((x) & ETH_CFG_ETH_RXD_DELAY_MASK) >> ETH_CFG_ETH_RXD_DELAY_LSB) +#define ETH_CFG_ETH_RXD_DELAY_SET(x) (((x) << ETH_CFG_ETH_RXD_DELAY_LSB) & ETH_CFG_ETH_RXD_DELAY_MASK) +#define ETH_CFG_ETH_RXD_DELAY_RESET 0x0 // 0 +#define ETH_CFG_RMII_GE0_MASTER_MSB 12 +#define ETH_CFG_RMII_GE0_MASTER_LSB 12 +#define ETH_CFG_RMII_GE0_MASTER_MASK 0x00001000 +#define ETH_CFG_RMII_GE0_MASTER_GET(x) (((x) & ETH_CFG_RMII_GE0_MASTER_MASK) >> ETH_CFG_RMII_GE0_MASTER_LSB) +#define ETH_CFG_RMII_GE0_MASTER_SET(x) (((x) << ETH_CFG_RMII_GE0_MASTER_LSB) & ETH_CFG_RMII_GE0_MASTER_MASK) +#define ETH_CFG_RMII_GE0_MASTER_RESET 0x1 // 1 +#define ETH_CFG_MII_CNTL_SPEED_MSB 11 +#define ETH_CFG_MII_CNTL_SPEED_LSB 11 +#define ETH_CFG_MII_CNTL_SPEED_MASK 0x00000800 +#define ETH_CFG_MII_CNTL_SPEED_GET(x) (((x) & ETH_CFG_MII_CNTL_SPEED_MASK) >> ETH_CFG_MII_CNTL_SPEED_LSB) +#define ETH_CFG_MII_CNTL_SPEED_SET(x) (((x) << ETH_CFG_MII_CNTL_SPEED_LSB) & ETH_CFG_MII_CNTL_SPEED_MASK) +#define ETH_CFG_MII_CNTL_SPEED_RESET 0x0 // 0 +#define ETH_CFG_RMII_GE0_MSB 10 +#define ETH_CFG_RMII_GE0_LSB 10 +#define ETH_CFG_RMII_GE0_MASK 0x00000400 +#define ETH_CFG_RMII_GE0_GET(x) (((x) & ETH_CFG_RMII_GE0_MASK) >> ETH_CFG_RMII_GE0_LSB) +#define ETH_CFG_RMII_GE0_SET(x) (((x) << ETH_CFG_RMII_GE0_LSB) & ETH_CFG_RMII_GE0_MASK) +#define ETH_CFG_RMII_GE0_RESET 0x0 // 0 +#define ETH_CFG_GE0_SGMII_MSB 6 +#define ETH_CFG_GE0_SGMII_LSB 6 +#define ETH_CFG_GE0_SGMII_MASK 0x00000040 +#define ETH_CFG_GE0_SGMII_GET(x) (((x) & ETH_CFG_GE0_SGMII_MASK) >> ETH_CFG_GE0_SGMII_LSB) +#define ETH_CFG_GE0_SGMII_SET(x) (((x) << ETH_CFG_GE0_SGMII_LSB) & ETH_CFG_GE0_SGMII_MASK) +#define ETH_CFG_GE0_SGMII_RESET 0x0 // 0 +#define ETH_CFG_GE0_ERR_EN_MSB 5 +#define ETH_CFG_GE0_ERR_EN_LSB 5 +#define ETH_CFG_GE0_ERR_EN_MASK 0x00000020 +#define ETH_CFG_GE0_ERR_EN_GET(x) (((x) & ETH_CFG_GE0_ERR_EN_MASK) >> ETH_CFG_GE0_ERR_EN_LSB) +#define ETH_CFG_GE0_ERR_EN_SET(x) (((x) << ETH_CFG_GE0_ERR_EN_LSB) & ETH_CFG_GE0_ERR_EN_MASK) +#define ETH_CFG_GE0_ERR_EN_RESET 0x0 // 0 +#define ETH_CFG_MII_GE0_SLAVE_MSB 4 +#define ETH_CFG_MII_GE0_SLAVE_LSB 4 +#define ETH_CFG_MII_GE0_SLAVE_MASK 0x00000010 +#define ETH_CFG_MII_GE0_SLAVE_GET(x) (((x) & ETH_CFG_MII_GE0_SLAVE_MASK) >> ETH_CFG_MII_GE0_SLAVE_LSB) +#define ETH_CFG_MII_GE0_SLAVE_SET(x) (((x) << ETH_CFG_MII_GE0_SLAVE_LSB) & ETH_CFG_MII_GE0_SLAVE_MASK) +#define ETH_CFG_MII_GE0_SLAVE_RESET 0x0 // 0 +#define ETH_CFG_MII_GE0_MASTER_MSB 3 +#define ETH_CFG_MII_GE0_MASTER_LSB 3 +#define ETH_CFG_MII_GE0_MASTER_MASK 0x00000008 +#define ETH_CFG_MII_GE0_MASTER_GET(x) (((x) & ETH_CFG_MII_GE0_MASTER_MASK) >> ETH_CFG_MII_GE0_MASTER_LSB) +#define ETH_CFG_MII_GE0_MASTER_SET(x) (((x) << ETH_CFG_MII_GE0_MASTER_LSB) & ETH_CFG_MII_GE0_MASTER_MASK) +#define ETH_CFG_MII_GE0_MASTER_RESET 0x0 // 0 +#define ETH_CFG_GMII_GE0_MSB 2 +#define ETH_CFG_GMII_GE0_LSB 2 +#define ETH_CFG_GMII_GE0_MASK 0x00000004 +#define ETH_CFG_GMII_GE0_GET(x) (((x) & ETH_CFG_GMII_GE0_MASK) >> ETH_CFG_GMII_GE0_LSB) +#define ETH_CFG_GMII_GE0_SET(x) (((x) << ETH_CFG_GMII_GE0_LSB) & ETH_CFG_GMII_GE0_MASK) +#define ETH_CFG_GMII_GE0_RESET 0x0 // 0 +#define ETH_CFG_MII_GE0_MSB 1 +#define ETH_CFG_MII_GE0_LSB 1 +#define ETH_CFG_MII_GE0_MASK 0x00000002 +#define ETH_CFG_MII_GE0_GET(x) (((x) & ETH_CFG_MII_GE0_MASK) >> ETH_CFG_MII_GE0_LSB) +#define ETH_CFG_MII_GE0_SET(x) (((x) << ETH_CFG_MII_GE0_LSB) & ETH_CFG_MII_GE0_MASK) +#define ETH_CFG_MII_GE0_RESET 0x0 // 0 +#define ETH_CFG_RGMII_GE0_MSB 0 +#define ETH_CFG_RGMII_GE0_LSB 0 +#define ETH_CFG_RGMII_GE0_MASK 0x00000001 +#define ETH_CFG_RGMII_GE0_GET(x) (((x) & ETH_CFG_RGMII_GE0_MASK) >> ETH_CFG_RGMII_GE0_LSB) +#define ETH_CFG_RGMII_GE0_SET(x) (((x) << ETH_CFG_RGMII_GE0_LSB) & ETH_CFG_RGMII_GE0_MASK) +#define ETH_CFG_RGMII_GE0_RESET 0x0 // 0 +#define ETH_CFG_ADDRESS 0x18070000 + + + + +/* + * ownership of descriptors between DMA and cpu + */ +#define ath_gmac_rx_owned_by_dma(_ds) ((_ds)->is_empty == 1) +#define ath_gmac_rx_give_to_dma(_ds) ((_ds)->is_empty = 1) +#define ath_gmac_tx_owned_by_dma(_ds) ((_ds)->is_empty == 0) +#define ath_gmac_tx_give_to_dma(_ds) ((_ds)->is_empty = 0) +#define ath_gmac_tx_own(_ds) ((_ds)->is_empty = 1) + +/* + * link settings + */ +#define ath_gmac_set_mac_duplex(_mac, _fdx) do { \ + if ((_fdx)) { \ + ath_gmac_reg_rmw_set(_mac, \ + ATH_MAC_CFG2, ATH_MAC_CFG2_FDX);\ + } else { \ + ath_gmac_reg_rmw_clear(_mac, \ + ATH_MAC_CFG2, ATH_MAC_CFG2_FDX);\ + } \ +} while (0) + +#define ath_gmac_set_mac_if(_mac, _isXGMII) do { \ + ath_gmac_reg_rmw_clear(_mac, ATH_MAC_CFG2, \ + ATH_MAC_CFG2_IF_1000 | \ + ATH_MAC_CFG2_IF_10_100); \ + if ((_isXGMII)) { \ + ath_gmac_reg_rmw_set(_mac, ATH_MAC_CFG2, \ + ATH_MAC_CFG2_IF_1000); \ + ath_gmac_reg_rmw_set(_mac, ATH_MAC_FIFO_CFG_5, \ + ATH_BYTE_PER_CLK_EN); \ + } else { \ + ath_gmac_reg_rmw_set(_mac, ATH_MAC_CFG2, \ + ATH_MAC_CFG2_IF_10_100); \ + ath_gmac_reg_rmw_clear(_mac, ATH_MAC_FIFO_CFG_5,\ + ATH_BYTE_PER_CLK_EN); \ + } \ +} while (0) + +#define ath_gmac_set_mac_speed(_mac, _is100) do { \ + if ((_is100)) { \ + ath_gmac_reg_rmw_set(_mac, ATH_MAC_IFCTL, \ + ATH_MAC_IFCTL_SPEED); \ + } else { \ + ath_gmac_reg_rmw_clear(_mac, ATH_MAC_IFCTL, \ + ATH_MAC_IFCTL_SPEED); \ + } \ +} while (0) + +#endif /* __QCA_ETH_953X_H */ diff --git a/u-boot/board/ar7240/common/qca-eth-953x_phy.h b/u-boot/board/ar7240/common/qca-eth-953x_phy.h new file mode 100755 index 0000000..0140a61 --- /dev/null +++ b/u-boot/board/ar7240/common/qca-eth-953x_phy.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _QCA_ETH_953x_PHY_H +#define _QCA_ETH_953x_PHY_H +#include + + +#ifdef CONFIG_ATHR_8033_PHY +extern int athrs_ar8033_reg_init(void *arg); +extern int athrs_ar8033_phy_setup(void *arg); +extern int athrs_ar8033_phy_is_fdx(int ethUnit); +extern int athrs_ar8033_phy_is_link_alive(int phyUnit); +extern int athrs_ar8033_phy_is_up(int ethUnit); +extern int athrs_ar8033_phy_speed(int ethUnit,int phyUnit); +#endif + +#ifdef CFG_ATHRS27_PHY +extern int athrs27_phy_setup(int ethUnit); +extern int athrs27_phy_is_up(int ethUnit); +extern int athrs27_phy_is_fdx(int ethUnit); +extern int athrs27_phy_speed(int ethUnit); +#endif + +#ifdef CONFIG_ATHRS17_PHY +extern int athrs17_phy_setup(int ethUnit); +extern int athrs17_phy_is_up(int ethUnit); +extern int athrs17_phy_is_fdx(int ethUnit); +extern int athrs17_phy_speed(int ethUnit); +#endif + +static inline void ath_gmac_phy_setup(int unit) +{ +#ifdef CFG_ATHRS27_PHY + athrs27_phy_setup(unit); +#endif +#ifdef CONFIG_VIR_PHY + athr_vir_phy_setup(unit); +#endif +} + +static inline void ath_gmac_phy_link(int unit, int *link) +{ + +#ifdef CFG_ATHRS27_PHY + *link = athrs27_phy_is_up(unit); +#endif + +#ifdef CONFIG_VIR_PHY + *link = athr_vir_phy_is_up(unit); +#endif +} + +static inline void ath_gmac_phy_duplex(int unit, int *duplex) +{ +#ifdef CFG_ATHRS27_PHY + *duplex = athrs27_phy_is_fdx(unit); +#endif +#ifdef CONFIG_VIR_PHY + *duplex = athr_vir_phy_is_fdx(unit); +#endif +} + +static inline void ath_gmac_phy_speed(int unit, int *speed) +{ +#ifdef CFG_ATHRS27_PHY + *speed = athrs27_phy_speed(unit); +#endif + +#ifdef CONFIG_VIR_PHY + *speed = athr_vir_phy_speed(unit); +#endif + +} + +#endif /* _QCA_ETH_953x_PHY_H */ diff --git a/u-boot/board/ar7240/common/tap-953x.S b/u-boot/board/ar7240/common/tap-953x.S new file mode 100755 index 0000000..bd4f71b --- /dev/null +++ b/u-boot/board/ar7240/common/tap-953x.S @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +.globl ath_ddr_tap_cal + .type ath_ddr_tap_cal, @function + .text + .align 4 +ath_ddr_tap_cal: + li a0, 0xbd001f00 + sw zero, 0x0(a0) // Place where the tap values are saved and used for SWEEP + sw zero, 0x4(a0) // Place where the number of passing taps are saved. + sw zero, 0x14(a0) // Place where the last pass tap value is stored + li a1, 0xaa55aa55 // Indicates that the First pass tap value is not found + sw a1, 0x10(a0) // Place where the First pass tap value is stored + nop + + li a0, 0xb8060000 // RESET_BASE_ADDRESS + lw a1, 0x1c(a0) // Reading the RST_RESET_ADDRESS + li a2, 0x08000000 // Setting the RST_RESET_RTC_RESET + or a1, a1, a2 + sw a1, 0x1c(a0) + + li a3, 0xffffffff + xor a2, a2, a3 + and a1, a1, a2 + sw a1, 0x1c(a0) // Taking the RTC out of RESET + nop + + li a0, 0xb8107000 // RTC_BASE_ADDRESS + li a1, 0x1 + sw a1, 0x0040(a0) // RTC_SYNC_RESET_ADDRESS + + li a2, 0x2 + +_poll_for_RTC_ON: + lw a1, 0x0044(a0) // RTC_SYNC_STATUS_ADDRESS + and a1, a2, a1 + bne a1, a2, _poll_for_RTC_ON + + +_CHANGE_TAPS: + + li t0, 0xbd001f00 // Read the current value of the TAP for programming + lw t1, 0x0(t0) + li t2, 0x00000000 + or t3, t1, t2 + + + li t0, 0xb8000000 // DDR_BASE_ADDRESS + + sw t3, 0x1c(t0) // TAP_CONTROL_0_ADDRESS + sw t3, 0x20(t0) // TAP_CONTROL_1_ADDRESS + sw t3, 0x24(t0) // TAP_CONTROL_2_ADDRESS + sw t3, 0x28(t0) // TAP_CONTROL_3_ADDRESS + + li t1, 0x00000010 // Running the test 8 times + sw t1, 0x0068(t0) // PERF_COMP_ADDR_1_ADDRESS + + li t1, 0xfa5de83f // 4 Row Address Bits, 4 Column Address Bits, 2 BA bits + sw t1, 0x002c(t0) // PERF_MASK_ADDR_0_ADDRESS + + li t1, 0x0000ffff + sw t1, 0x0070(t0) // PERF_COMP_AHB_GE0_1_ADDRESS + + li t1, 0x0000ffff + sw t1, 0x0040(t0) // PERF_COMP_AHB_GE1_0_ADDRESS + + li t1, 0x0000ffff + sw t1, 0x0078(t0) // PERF_COMP_AHB_GE1_1_ADDRESS + + li t1, 0x0000ffff + sw t1, 0x0034(t0) // PERF_MASK_AHB_GE0_0_ADDRESS + + li t1, 0x0000ffff + sw t1, 0x006c(t0) // PERF_MASK_AHB_GE0_1_ADDRESS + + li t1, 0x0000ffff + sw t1, 0x003c(t0) // PERF_MASK_AHB_GE1_0_ADDRESS + + li t1, 0x0000ffff + sw t1, 0x0074(t0) // PERF_MASK_AHB_GE1_1_ADDRESS + + li t1, 0x0000ffff + sw t1, 0x0038(t0) // PERF_COMP_AHB_GE0_0_ADDRESS + + li t1, 0x00000001 + sw t1, 0x011c(t0) // DDR_BIST_ADDRESS + + li t2, 0x1 +_bist_done_poll: + lw t1, 0x0120(t0) // DDR_BIST_STATUS_ADDRESS + and t1, t1, t2 + bne t1, t2, _bist_done_poll + + lw t1, 0x0120(t0) // DDR_BIST_STATUS_ADDRESS + li t4, 0x000001fe + and t2, t1, t4 + srl t2, t2, 0x1 // no. of Pass Runs + + li t5, 0x00000000 + sw t5, 0x011c(t0) //DDR_BIST_ADDRESS - Stop the DDR BIST test + + li t5, 0x0001fe00 + and t5, t5, t1 + bnez t5, _iterate_tap // This is a redundant compare but nevertheless - Comparing the FAILS + + lw t1, 0x0068(t0) // PERF_COMP_ADDR_1_ADDRESS + li t3, 0x000001fe + and t3, t3, t1 + srl t3, t3, 0x1 // No. of runs in the config register. + + bne t3, t2, _iterate_tap + +pass_tap: + li t0, 0xbd001f00 + lw t1, 0x4(t0) + addiu t1, t1, 0x1 + sw t1, 0x4(t0) + + li t0, 0xbd001f10 + lw t1, 0x0(t0) + li t2, 0xaa55aa55 + beq t1, t2, _first_pass + nop + li t0, 0xbd001f00 + lw t1, 0x0(t0) + li t0, 0xbd001f10 + sw t1, 0x4(t0) + nop + b _iterate_tap + nop + +_first_pass: + li t0, 0xbd001f00 + lw t1, 0x0(t0) + li t0, 0xbd001f10 + sw t1, 0x0(t0) + sw t1, 0x4(t0) + nop + +_iterate_tap: + + li t0, 0xbd001f00 + lw t1, 0x0(t0) + li t2, 0x3f + beq t1, t2, _STOP_TEST + nop + addiu t1, t1, 0x1 + sw t1, 0x0(t0) + nop + b _CHANGE_TAPS + +_STOP_TEST: + li t0, 0xbd001f00 + lw t1, 0x4(t0) + bnez t1, _load_center_tap + nop + li t3, 0x8 // Default Tap to be used + b _load_tap_into_reg + +_load_center_tap: + li t0, 0xbd001f10 + lw t1, 0x0(t0) + lw t2, 0x4(t0) + add t3, t1, t2 + srl t3, t3, 0x1 + li t4, 0x3f + and t3, t3, t4 +_load_tap_into_reg: + li t0, 0xb8000000 + sw t3, 0x1c(t0) // TAP_CONTROL_0_ADDRESS + sw t3, 0x20(t0) // TAP_CONTROL_1_ADDRESS + sw t3, 0x24(t0) // TAP_CONTROL_2_ADDRESS + sw t3, 0x28(t0) // TAP_CONTROL_3_ADDRESS + + jr ra + nop + diff --git a/u-boot/include/953x.h b/u-boot/include/953x.h new file mode 100755 index 0000000..67a8127 --- /dev/null +++ b/u-boot/include/953x.h @@ -0,0 +1,4525 @@ +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _QCA953X_H +#define _QCA953X_H + +#ifndef __ASSEMBLY__ +#include +#include +#include +#include +#endif /* __ASSEMBLY__ */ + +#undef is_qca953x +#undef is_hb + +#define is_qca953x() (1) +#define is_hb() (1) + + +#define CPU_PLL_CONFIG_UPDATING_MSB 31 +#define CPU_PLL_CONFIG_UPDATING_LSB 31 +#define CPU_PLL_CONFIG_UPDATING_MASK 0x80000000 +#define CPU_PLL_CONFIG_UPDATING_GET(x) (((x) & CPU_PLL_CONFIG_UPDATING_MASK) >> CPU_PLL_CONFIG_UPDATING_LSB) +#define CPU_PLL_CONFIG_UPDATING_SET(x) (((x) << CPU_PLL_CONFIG_UPDATING_LSB) & CPU_PLL_CONFIG_UPDATING_MASK) +#define CPU_PLL_CONFIG_UPDATING_RESET 0x1 // 1 +#define CPU_PLL_CONFIG_PLLPWD_MSB 30 +#define CPU_PLL_CONFIG_PLLPWD_LSB 30 +#define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000 +#define CPU_PLL_CONFIG_PLLPWD_GET(x) (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB) +#define CPU_PLL_CONFIG_PLLPWD_SET(x) (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK) +#define CPU_PLL_CONFIG_PLLPWD_RESET 0x1 // 1 +#define CPU_PLL_CONFIG_SPARE_MSB 29 +#define CPU_PLL_CONFIG_SPARE_LSB 22 +#define CPU_PLL_CONFIG_SPARE_MASK 0x3fc00000 +#define CPU_PLL_CONFIG_SPARE_GET(x) (((x) & CPU_PLL_CONFIG_SPARE_MASK) >> CPU_PLL_CONFIG_SPARE_LSB) +#define CPU_PLL_CONFIG_SPARE_SET(x) (((x) << CPU_PLL_CONFIG_SPARE_LSB) & CPU_PLL_CONFIG_SPARE_MASK) +#define CPU_PLL_CONFIG_SPARE_RESET 0x0 // 0 +#define CPU_PLL_CONFIG_OUTDIV_MSB 21 +#define CPU_PLL_CONFIG_OUTDIV_LSB 19 +#define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000 +#define CPU_PLL_CONFIG_OUTDIV_GET(x) (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB) +#define CPU_PLL_CONFIG_OUTDIV_SET(x) (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK) +#define CPU_PLL_CONFIG_OUTDIV_RESET 0x0 // 0 +#define CPU_PLL_CONFIG_RANGE_MSB 18 +#define CPU_PLL_CONFIG_RANGE_LSB 17 +#define CPU_PLL_CONFIG_RANGE_MASK 0x00060000 +#define CPU_PLL_CONFIG_RANGE_GET(x) (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB) +#define CPU_PLL_CONFIG_RANGE_SET(x) (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK) +#define CPU_PLL_CONFIG_RANGE_RESET 0x3 // 3 +#define CPU_PLL_CONFIG_REFDIV_MSB 16 +#define CPU_PLL_CONFIG_REFDIV_LSB 12 +#define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000 +#define CPU_PLL_CONFIG_REFDIV_GET(x) (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB) +#define CPU_PLL_CONFIG_REFDIV_SET(x) (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK) +#define CPU_PLL_CONFIG_REFDIV_RESET 0x2 // 2 +#define CPU_PLL_CONFIG_NINT_MSB 11 +#define CPU_PLL_CONFIG_NINT_LSB 6 +#define CPU_PLL_CONFIG_NINT_MASK 0x00000fc0 +#define CPU_PLL_CONFIG_NINT_GET(x) (((x) & CPU_PLL_CONFIG_NINT_MASK) >> CPU_PLL_CONFIG_NINT_LSB) +#define CPU_PLL_CONFIG_NINT_SET(x) (((x) << CPU_PLL_CONFIG_NINT_LSB) & CPU_PLL_CONFIG_NINT_MASK) +#define CPU_PLL_CONFIG_NINT_RESET 0x14 // 20 +#define CPU_PLL_CONFIG_NFRAC_MSB 5 +#define CPU_PLL_CONFIG_NFRAC_LSB 0 +#define CPU_PLL_CONFIG_NFRAC_MASK 0x0000003f +#define CPU_PLL_CONFIG_NFRAC_GET(x) (((x) & CPU_PLL_CONFIG_NFRAC_MASK) >> CPU_PLL_CONFIG_NFRAC_LSB) +#define CPU_PLL_CONFIG_NFRAC_SET(x) (((x) << CPU_PLL_CONFIG_NFRAC_LSB) & CPU_PLL_CONFIG_NFRAC_MASK) +#define CPU_PLL_CONFIG_NFRAC_RESET 0x10 // 16 +#define CPU_PLL_CONFIG_ADDRESS 0x18050000 +#define DDR_PLL_CONFIG_UPDATING_MSB 31 +#define DDR_PLL_CONFIG_UPDATING_LSB 31 +#define DDR_PLL_CONFIG_UPDATING_MASK 0x80000000 +#define DDR_PLL_CONFIG_UPDATING_GET(x) (((x) & DDR_PLL_CONFIG_UPDATING_MASK) >> DDR_PLL_CONFIG_UPDATING_LSB) +#define DDR_PLL_CONFIG_UPDATING_SET(x) (((x) << DDR_PLL_CONFIG_UPDATING_LSB) & DDR_PLL_CONFIG_UPDATING_MASK) +#define DDR_PLL_CONFIG_UPDATING_RESET 0x1 // 1 +#define DDR_PLL_CONFIG_PLLPWD_MSB 30 +#define DDR_PLL_CONFIG_PLLPWD_LSB 30 +#define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000 +#define DDR_PLL_CONFIG_PLLPWD_GET(x) (((x) & DDR_PLL_CONFIG_PLLPWD_MASK) >> DDR_PLL_CONFIG_PLLPWD_LSB) +#define DDR_PLL_CONFIG_PLLPWD_SET(x) (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK) +#define DDR_PLL_CONFIG_PLLPWD_RESET 0x1 // 1 +#define DDR_PLL_CONFIG_SPARE_MSB 29 +#define DDR_PLL_CONFIG_SPARE_LSB 26 +#define DDR_PLL_CONFIG_SPARE_MASK 0x3c000000 +#define DDR_PLL_CONFIG_SPARE_GET(x) (((x) & DDR_PLL_CONFIG_SPARE_MASK) >> DDR_PLL_CONFIG_SPARE_LSB) +#define DDR_PLL_CONFIG_SPARE_SET(x) (((x) << DDR_PLL_CONFIG_SPARE_LSB) & DDR_PLL_CONFIG_SPARE_MASK) +#define DDR_PLL_CONFIG_SPARE_RESET 0x0 // 0 +#define DDR_PLL_CONFIG_OUTDIV_MSB 25 +#define DDR_PLL_CONFIG_OUTDIV_LSB 23 +#define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000 +#define DDR_PLL_CONFIG_OUTDIV_GET(x) (((x) & DDR_PLL_CONFIG_OUTDIV_MASK) >> DDR_PLL_CONFIG_OUTDIV_LSB) +#define DDR_PLL_CONFIG_OUTDIV_SET(x) (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK) +#define DDR_PLL_CONFIG_OUTDIV_RESET 0x0 // 0 +#define DDR_PLL_CONFIG_RANGE_MSB 22 +#define DDR_PLL_CONFIG_RANGE_LSB 21 +#define DDR_PLL_CONFIG_RANGE_MASK 0x00600000 +#define DDR_PLL_CONFIG_RANGE_GET(x) (((x) & DDR_PLL_CONFIG_RANGE_MASK) >> DDR_PLL_CONFIG_RANGE_LSB) +#define DDR_PLL_CONFIG_RANGE_SET(x) (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK) +#define DDR_PLL_CONFIG_RANGE_RESET 0x3 // 3 +#define DDR_PLL_CONFIG_REFDIV_MSB 20 +#define DDR_PLL_CONFIG_REFDIV_LSB 16 +#define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000 +#define DDR_PLL_CONFIG_REFDIV_GET(x) (((x) & DDR_PLL_CONFIG_REFDIV_MASK) >> DDR_PLL_CONFIG_REFDIV_LSB) +#define DDR_PLL_CONFIG_REFDIV_SET(x) (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK) +#define DDR_PLL_CONFIG_REFDIV_RESET 0x2 // 2 +#define DDR_PLL_CONFIG_NINT_MSB 15 +#define DDR_PLL_CONFIG_NINT_LSB 10 +#define DDR_PLL_CONFIG_NINT_MASK 0x0000fc00 +#define DDR_PLL_CONFIG_NINT_GET(x) (((x) & DDR_PLL_CONFIG_NINT_MASK) >> DDR_PLL_CONFIG_NINT_LSB) +#define DDR_PLL_CONFIG_NINT_SET(x) (((x) << DDR_PLL_CONFIG_NINT_LSB) & DDR_PLL_CONFIG_NINT_MASK) +#define DDR_PLL_CONFIG_NINT_RESET 0x14 // 20 +#define DDR_PLL_CONFIG_NFRAC_MSB 9 +#define DDR_PLL_CONFIG_NFRAC_LSB 0 +#define DDR_PLL_CONFIG_NFRAC_MASK 0x000003ff +#define DDR_PLL_CONFIG_NFRAC_GET(x) (((x) & DDR_PLL_CONFIG_NFRAC_MASK) >> DDR_PLL_CONFIG_NFRAC_LSB) +#define DDR_PLL_CONFIG_NFRAC_SET(x) (((x) << DDR_PLL_CONFIG_NFRAC_LSB) & DDR_PLL_CONFIG_NFRAC_MASK) +#define DDR_PLL_CONFIG_NFRAC_RESET 0x200 // 512 +#define DDR_PLL_CONFIG_ADDRESS 0x18050004 + +#define DDR_CTL_CONFIG_SRAM_TSEL_MSB 31 +#define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30 +#define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000 +#define DDR_CTL_CONFIG_SRAM_TSEL_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) >> DDR_CTL_CONFIG_SRAM_TSEL_LSB) +#define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) +#define DDR_CTL_CONFIG_SRAM_TSEL_RESET 0x1 // 1 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MSB 29 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB 21 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK 0x3fe00000 +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(x) (((x) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) >> DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x) (((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) +#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_RESET 0x0 // 0 +#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MSB 20 +#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB 20 +#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK 0x00100000 +#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) +#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK) +#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_RESET 0x1 // 1 +#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MSB 19 +#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB 19 +#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK 0x00080000 +#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) +#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK) +#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_RESET 0x1 // 1 +#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MSB 18 +#define DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB 18 +#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK 0x00040000 +#define DDR_CTL_CONFIG_USB_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) +#define DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK) +#define DDR_CTL_CONFIG_USB_SRAM_SYNC_RESET 0x1 // 1 +#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MSB 17 +#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB 17 +#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK 0x00020000 +#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) +#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK) +#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_RESET 0x1 // 1 +#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MSB 16 +#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB 16 +#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK 0x00010000 +#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) +#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK) +#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_RESET 0x1 // 1 +#define DDR_CTL_CONFIG_SPARE_MSB 13 +#define DDR_CTL_CONFIG_SPARE_LSB 7 +#define DDR_CTL_CONFIG_SPARE_MASK 0x00003f80 +#define DDR_CTL_CONFIG_SPARE_GET(x) (((x) & DDR_CTL_CONFIG_SPARE_MASK) >> DDR_CTL_CONFIG_SPARE_LSB) +#define DDR_CTL_CONFIG_SPARE_SET(x) (((x) << DDR_CTL_CONFIG_SPARE_LSB) & DDR_CTL_CONFIG_SPARE_MASK) +#define DDR_CTL_CONFIG_SPARE_RESET 0x0 // 0 +#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MSB 6 +#define DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB 6 +#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK 0x00000040 +#define DDR_CTL_CONFIG_PAD_DDR2_SEL_GET(x) (((x) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK) >> DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) +#define DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(x) (((x) << DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK) +#define DDR_CTL_CONFIG_PAD_DDR2_SEL_RESET 0x0 // 0 +#define DDR_CTL_CONFIG_GATE_SRAM_CLK_MSB 4 +#define DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB 4 +#define DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK 0x00000010 +#define DDR_CTL_CONFIG_GATE_SRAM_CLK_GET(x) (((x) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK) >> DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB) +#define DDR_CTL_CONFIG_GATE_SRAM_CLK_SET(x) (((x) << DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK) +#define DDR_CTL_CONFIG_GATE_SRAM_CLK_RESET 0x0 // 0 +#define DDR_CTL_CONFIG_SRAM_REQ_ACK_MSB 3 +#define DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB 3 +#define DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK 0x00000008 +#define DDR_CTL_CONFIG_SRAM_REQ_ACK_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK) >> DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB) +#define DDR_CTL_CONFIG_SRAM_REQ_ACK_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK) +#define DDR_CTL_CONFIG_SRAM_REQ_ACK_RESET 0x0 // 0 +#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MSB 2 +#define DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB 2 +#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK 0x00000004 +#define DDR_CTL_CONFIG_CPU_DDR_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK) >> DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) +#define DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK) +#define DDR_CTL_CONFIG_CPU_DDR_SYNC_RESET 0x0 // 0 +#define DDR_CTL_CONFIG_HALF_WIDTH_MSB 1 +#define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1 +#define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002 +#define DDR_CTL_CONFIG_HALF_WIDTH_GET(x) (((x) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) >> DDR_CTL_CONFIG_HALF_WIDTH_LSB) +#define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) (((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) +#define DDR_CTL_CONFIG_HALF_WIDTH_RESET 0x1 // 1 +#define DDR_CTL_CONFIG_SDRAM_MODE_EN_MSB 0 +#define DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB 0 +#define DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK 0x00000001 +#define DDR_CTL_CONFIG_SDRAM_MODE_EN_GET(x) (((x) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK) >> DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB) +#define DDR_CTL_CONFIG_SDRAM_MODE_EN_SET(x) (((x) << DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK) +#define DDR_CTL_CONFIG_SDRAM_MODE_EN_RESET 0x0 // 0 +#define DDR_CTL_CONFIG_ADDRESS 0x18000108 + +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MSB 31 +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB 31 +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK 0x80000000 +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB) +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK) +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_RESET 0x0 // 0 +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MSB 30 +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB 30 +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK 0x40000000 +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB) +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK) +#define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_RESET 0x0 // 0 +#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MSB 29 +#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB 29 +#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK 0x20000000 +#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_GET(x) (((x) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK) >> DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB) +#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_SET(x) (((x) << DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK) +#define DDR_DEBUG_RD_CNTL_USE_LB_CLK_RESET 0x0 // 0 +#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MSB 28 +#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB 28 +#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK 0x10000000 +#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_GET(x) (((x) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK) >> DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB) +#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_SET(x) (((x) << DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK) +#define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_RESET 0x1 // 1 +#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MSB 27 +#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB 27 +#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK 0x08000000 +#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_GET(x) (((x) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK) >> DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB) +#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_SET(x) (((x) << DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK) +#define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_RESET 0x0 // 0 +#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MSB 16 +#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB 16 +#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK 0x00010000 +#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB) +#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB) & DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK) +#define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_RESET 0x0 // 0 +#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MSB 15 +#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB 15 +#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK 0x00008000 +#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK) >> DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB) +#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB) & DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK) +#define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_RESET 0x0 // 0 +#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MSB 14 +#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB 13 +#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK 0x00006000 +#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB) +#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK) +#define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_RESET 0x0 // 0 +#define DDR_DEBUG_RD_CNTL_GATE_TAP_MSB 12 +#define DDR_DEBUG_RD_CNTL_GATE_TAP_LSB 8 +#define DDR_DEBUG_RD_CNTL_GATE_TAP_MASK 0x00001f00 +#define DDR_DEBUG_RD_CNTL_GATE_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_LSB) +#define DDR_DEBUG_RD_CNTL_GATE_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK) +#define DDR_DEBUG_RD_CNTL_GATE_TAP_RESET 0x1 // 1 +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MSB 6 +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB 5 +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK 0x00000060 +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB) +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK) +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_RESET 0x0 // 0 +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_MSB 4 +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB 0 +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK 0x0000001f +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB) +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK) +#define DDR_DEBUG_RD_CNTL_CK_P_TAP_RESET 0x1 // 1 +#define DDR_DEBUG_RD_CNTL_ADDRESS 0x18000118 + +#define DDR2_CONFIG_DDR2_TWL_MSB 13 +#define DDR2_CONFIG_DDR2_TWL_LSB 10 +#define DDR2_CONFIG_DDR2_TWL_MASK 0x00003c00 +#define DDR2_CONFIG_DDR2_TWL_GET(x) (((x) & DDR2_CONFIG_DDR2_TWL_MASK) >> DDR2_CONFIG_DDR2_TWL_LSB) +#define DDR2_CONFIG_DDR2_TWL_SET(x) (((x) << DDR2_CONFIG_DDR2_TWL_LSB) & DDR2_CONFIG_DDR2_TWL_MASK) +#define DDR2_CONFIG_DDR2_TWL_RESET 0x1 // 1 +#define DDR2_CONFIG_DDR2_ODT_MSB 9 +#define DDR2_CONFIG_DDR2_ODT_LSB 9 +#define DDR2_CONFIG_DDR2_ODT_MASK 0x00000200 +#define DDR2_CONFIG_DDR2_ODT_GET(x) (((x) & DDR2_CONFIG_DDR2_ODT_MASK) >> DDR2_CONFIG_DDR2_ODT_LSB) +#define DDR2_CONFIG_DDR2_ODT_SET(x) (((x) << DDR2_CONFIG_DDR2_ODT_LSB) & DDR2_CONFIG_DDR2_ODT_MASK) +#define DDR2_CONFIG_DDR2_ODT_RESET 0x1 // 1 +#define DDR2_CONFIG_TFAW_MSB 7 +#define DDR2_CONFIG_TFAW_LSB 2 +#define DDR2_CONFIG_TFAW_MASK 0x000000fc +#define DDR2_CONFIG_TFAW_GET(x) (((x) & DDR2_CONFIG_TFAW_MASK) >> DDR2_CONFIG_TFAW_LSB) +#define DDR2_CONFIG_TFAW_SET(x) (((x) << DDR2_CONFIG_TFAW_LSB) & DDR2_CONFIG_TFAW_MASK) +#define DDR2_CONFIG_TFAW_RESET 0x16 // 22 +#define DDR2_CONFIG_ENABLE_DDR2_MSB 0 +#define DDR2_CONFIG_ENABLE_DDR2_LSB 0 +#define DDR2_CONFIG_ENABLE_DDR2_MASK 0x00000001 +#define DDR2_CONFIG_ENABLE_DDR2_GET(x) (((x) & DDR2_CONFIG_ENABLE_DDR2_MASK) >> DDR2_CONFIG_ENABLE_DDR2_LSB) +#define DDR2_CONFIG_ENABLE_DDR2_SET(x) (((x) << DDR2_CONFIG_ENABLE_DDR2_LSB) & DDR2_CONFIG_ENABLE_DDR2_MASK) +#define DDR2_CONFIG_ENABLE_DDR2_RESET 0x0 // 0 +#define DDR2_CONFIG_ADDRESS 0x180000b8 + +#define DDR_CONTROL_EMR3S_MSB 5 +#define DDR_CONTROL_EMR3S_LSB 5 +#define DDR_CONTROL_EMR3S_MASK 0x00000020 +#define DDR_CONTROL_EMR3S_GET(x) (((x) & DDR_CONTROL_EMR3S_MASK) >> DDR_CONTROL_EMR3S_LSB) +#define DDR_CONTROL_EMR3S_SET(x) (((x) << DDR_CONTROL_EMR3S_LSB) & DDR_CONTROL_EMR3S_MASK) +#define DDR_CONTROL_EMR3S_RESET 0x0 // 0 +#define DDR_CONTROL_EMR2S_MSB 4 +#define DDR_CONTROL_EMR2S_LSB 4 +#define DDR_CONTROL_EMR2S_MASK 0x00000010 +#define DDR_CONTROL_EMR2S_GET(x) (((x) & DDR_CONTROL_EMR2S_MASK) >> DDR_CONTROL_EMR2S_LSB) +#define DDR_CONTROL_EMR2S_SET(x) (((x) << DDR_CONTROL_EMR2S_LSB) & DDR_CONTROL_EMR2S_MASK) +#define DDR_CONTROL_EMR2S_RESET 0x0 // 0 +#define DDR_CONTROL_PREA_MSB 3 +#define DDR_CONTROL_PREA_LSB 3 +#define DDR_CONTROL_PREA_MASK 0x00000008 +#define DDR_CONTROL_PREA_GET(x) (((x) & DDR_CONTROL_PREA_MASK) >> DDR_CONTROL_PREA_LSB) +#define DDR_CONTROL_PREA_SET(x) (((x) << DDR_CONTROL_PREA_LSB) & DDR_CONTROL_PREA_MASK) +#define DDR_CONTROL_PREA_RESET 0x0 // 0 +#define DDR_CONTROL_REF_MSB 2 +#define DDR_CONTROL_REF_LSB 2 +#define DDR_CONTROL_REF_MASK 0x00000004 +#define DDR_CONTROL_REF_GET(x) (((x) & DDR_CONTROL_REF_MASK) >> DDR_CONTROL_REF_LSB) +#define DDR_CONTROL_REF_SET(x) (((x) << DDR_CONTROL_REF_LSB) & DDR_CONTROL_REF_MASK) +#define DDR_CONTROL_REF_RESET 0x0 // 0 +#define DDR_CONTROL_EMRS_MSB 1 +#define DDR_CONTROL_EMRS_LSB 1 +#define DDR_CONTROL_EMRS_MASK 0x00000002 +#define DDR_CONTROL_EMRS_GET(x) (((x) & DDR_CONTROL_EMRS_MASK) >> DDR_CONTROL_EMRS_LSB) +#define DDR_CONTROL_EMRS_SET(x) (((x) << DDR_CONTROL_EMRS_LSB) & DDR_CONTROL_EMRS_MASK) +#define DDR_CONTROL_EMRS_RESET 0x0 // 0 +#define DDR_CONTROL_MRS_MSB 0 +#define DDR_CONTROL_MRS_LSB 0 +#define DDR_CONTROL_MRS_MASK 0x00000001 +#define DDR_CONTROL_MRS_GET(x) (((x) & DDR_CONTROL_MRS_MASK) >> DDR_CONTROL_MRS_LSB) +#define DDR_CONTROL_MRS_SET(x) (((x) << DDR_CONTROL_MRS_LSB) & DDR_CONTROL_MRS_MASK) +#define DDR_CONTROL_MRS_RESET 0x0 // 0 +#define DDR_CONTROL_ADDRESS 0x18000010 + +#define DDR_CONFIG_CAS_LATENCY_MSB_MSB 31 +#define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31 +#define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000 +#define DDR_CONFIG_CAS_LATENCY_MSB_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) >> DDR_CONFIG_CAS_LATENCY_MSB_LSB) +#define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) +#define DDR_CONFIG_CAS_LATENCY_MSB_RESET 0x0 // 0 +#define DDR_CONFIG_OPEN_PAGE_MSB 30 +#define DDR_CONFIG_OPEN_PAGE_LSB 30 +#define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000 +#define DDR_CONFIG_OPEN_PAGE_GET(x) (((x) & DDR_CONFIG_OPEN_PAGE_MASK) >> DDR_CONFIG_OPEN_PAGE_LSB) +#define DDR_CONFIG_OPEN_PAGE_SET(x) (((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK) +#define DDR_CONFIG_OPEN_PAGE_RESET 0x1 // 1 +#define DDR_CONFIG_CAS_LATENCY_MSB 29 +#define DDR_CONFIG_CAS_LATENCY_LSB 27 +#define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000 +#define DDR_CONFIG_CAS_LATENCY_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MASK) >> DDR_CONFIG_CAS_LATENCY_LSB) +#define DDR_CONFIG_CAS_LATENCY_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK) +#define DDR_CONFIG_CAS_LATENCY_RESET 0x6 // 6 +#define DDR_CONFIG_TMRD_MSB 26 +#define DDR_CONFIG_TMRD_LSB 23 +#define DDR_CONFIG_TMRD_MASK 0x07800000 +#define DDR_CONFIG_TMRD_GET(x) (((x) & DDR_CONFIG_TMRD_MASK) >> DDR_CONFIG_TMRD_LSB) +#define DDR_CONFIG_TMRD_SET(x) (((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK) +#define DDR_CONFIG_TMRD_RESET 0xf // 15 +#define DDR_CONFIG_TRFC_MSB 22 +#define DDR_CONFIG_TRFC_LSB 17 +#define DDR_CONFIG_TRFC_MASK 0x007e0000 +#define DDR_CONFIG_TRFC_GET(x) (((x) & DDR_CONFIG_TRFC_MASK) >> DDR_CONFIG_TRFC_LSB) +#define DDR_CONFIG_TRFC_SET(x) (((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK) +#define DDR_CONFIG_TRFC_RESET 0x24 // 36 +#define DDR_CONFIG_TRRD_MSB 16 +#define DDR_CONFIG_TRRD_LSB 13 +#define DDR_CONFIG_TRRD_MASK 0x0001e000 +#define DDR_CONFIG_TRRD_GET(x) (((x) & DDR_CONFIG_TRRD_MASK) >> DDR_CONFIG_TRRD_LSB) +#define DDR_CONFIG_TRRD_SET(x) (((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK) +#define DDR_CONFIG_TRRD_RESET 0x4 // 4 +#define DDR_CONFIG_TRP_MSB 12 +#define DDR_CONFIG_TRP_LSB 9 +#define DDR_CONFIG_TRP_MASK 0x00001e00 +#define DDR_CONFIG_TRP_GET(x) (((x) & DDR_CONFIG_TRP_MASK) >> DDR_CONFIG_TRP_LSB) +#define DDR_CONFIG_TRP_SET(x) (((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK) +#define DDR_CONFIG_TRP_RESET 0x6 // 6 +#define DDR_CONFIG_TRCD_MSB 8 +#define DDR_CONFIG_TRCD_LSB 5 +#define DDR_CONFIG_TRCD_MASK 0x000001e0 +#define DDR_CONFIG_TRCD_GET(x) (((x) & DDR_CONFIG_TRCD_MASK) >> DDR_CONFIG_TRCD_LSB) +#define DDR_CONFIG_TRCD_SET(x) (((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK) +#define DDR_CONFIG_TRCD_RESET 0x6 // 6 +#define DDR_CONFIG_TRAS_MSB 4 +#define DDR_CONFIG_TRAS_LSB 0 +#define DDR_CONFIG_TRAS_MASK 0x0000001f +#define DDR_CONFIG_TRAS_GET(x) (((x) & DDR_CONFIG_TRAS_MASK) >> DDR_CONFIG_TRAS_LSB) +#define DDR_CONFIG_TRAS_SET(x) (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK) +#define DDR_CONFIG_TRAS_RESET 0x10 // 16 +#define DDR_CONFIG_ADDRESS 0x18000000 + +#define DDR_CONFIG2_HALF_WIDTH_LOW_MSB 31 +#define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31 +#define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000 +#define DDR_CONFIG2_HALF_WIDTH_LOW_GET(x) (((x) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) >> DDR_CONFIG2_HALF_WIDTH_LOW_LSB) +#define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) (((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) +#define DDR_CONFIG2_HALF_WIDTH_LOW_RESET 0x1 // 1 +#define DDR_CONFIG2_SWAP_A26_A27_MSB 30 +#define DDR_CONFIG2_SWAP_A26_A27_LSB 30 +#define DDR_CONFIG2_SWAP_A26_A27_MASK 0x40000000 +#define DDR_CONFIG2_SWAP_A26_A27_GET(x) (((x) & DDR_CONFIG2_SWAP_A26_A27_MASK) >> DDR_CONFIG2_SWAP_A26_A27_LSB) +#define DDR_CONFIG2_SWAP_A26_A27_SET(x) (((x) << DDR_CONFIG2_SWAP_A26_A27_LSB) & DDR_CONFIG2_SWAP_A26_A27_MASK) +#define DDR_CONFIG2_SWAP_A26_A27_RESET 0x0 // 0 +#define DDR_CONFIG2_GATE_OPEN_LATENCY_MSB 29 +#define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26 +#define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000 +#define DDR_CONFIG2_GATE_OPEN_LATENCY_GET(x) (((x) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) >> DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) +#define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) (((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) +#define DDR_CONFIG2_GATE_OPEN_LATENCY_RESET 0x6 // 6 +#define DDR_CONFIG2_TWTR_MSB 25 +#define DDR_CONFIG2_TWTR_LSB 21 +#define DDR_CONFIG2_TWTR_MASK 0x03e00000 +#define DDR_CONFIG2_TWTR_GET(x) (((x) & DDR_CONFIG2_TWTR_MASK) >> DDR_CONFIG2_TWTR_LSB) +#define DDR_CONFIG2_TWTR_SET(x) (((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK) +#define DDR_CONFIG2_TWTR_RESET 0xe // 14 +#define DDR_CONFIG2_TRTP_MSB 20 +#define DDR_CONFIG2_TRTP_LSB 17 +#define DDR_CONFIG2_TRTP_MASK 0x001e0000 +#define DDR_CONFIG2_TRTP_GET(x) (((x) & DDR_CONFIG2_TRTP_MASK) >> DDR_CONFIG2_TRTP_LSB) +#define DDR_CONFIG2_TRTP_SET(x) (((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK) +#define DDR_CONFIG2_TRTP_RESET 0x8 // 8 +#define DDR_CONFIG2_TRTW_MSB 16 +#define DDR_CONFIG2_TRTW_LSB 12 +#define DDR_CONFIG2_TRTW_MASK 0x0001f000 +#define DDR_CONFIG2_TRTW_GET(x) (((x) & DDR_CONFIG2_TRTW_MASK) >> DDR_CONFIG2_TRTW_LSB) +#define DDR_CONFIG2_TRTW_SET(x) (((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK) +#define DDR_CONFIG2_TRTW_RESET 0x10 // 16 +#define DDR_CONFIG2_TWR_MSB 11 +#define DDR_CONFIG2_TWR_LSB 8 +#define DDR_CONFIG2_TWR_MASK 0x00000f00 +#define DDR_CONFIG2_TWR_GET(x) (((x) & DDR_CONFIG2_TWR_MASK) >> DDR_CONFIG2_TWR_LSB) +#define DDR_CONFIG2_TWR_SET(x) (((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK) +#define DDR_CONFIG2_TWR_RESET 0x6 // 6 +#define DDR_CONFIG2_CKE_MSB 7 +#define DDR_CONFIG2_CKE_LSB 7 +#define DDR_CONFIG2_CKE_MASK 0x00000080 +#define DDR_CONFIG2_CKE_GET(x) (((x) & DDR_CONFIG2_CKE_MASK) >> DDR_CONFIG2_CKE_LSB) +#define DDR_CONFIG2_CKE_SET(x) (((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK) +#define DDR_CONFIG2_CKE_RESET 0x0 // 0 +#define DDR_CONFIG2_PHASE_SELECT_MSB 6 +#define DDR_CONFIG2_PHASE_SELECT_LSB 6 +#define DDR_CONFIG2_PHASE_SELECT_MASK 0x00000040 +#define DDR_CONFIG2_PHASE_SELECT_GET(x) (((x) & DDR_CONFIG2_PHASE_SELECT_MASK) >> DDR_CONFIG2_PHASE_SELECT_LSB) +#define DDR_CONFIG2_PHASE_SELECT_SET(x) (((x) << DDR_CONFIG2_PHASE_SELECT_LSB) & DDR_CONFIG2_PHASE_SELECT_MASK) +#define DDR_CONFIG2_PHASE_SELECT_RESET 0x0 // 0 +#define DDR_CONFIG2_CNTL_OE_EN_MSB 5 +#define DDR_CONFIG2_CNTL_OE_EN_LSB 5 +#define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020 +#define DDR_CONFIG2_CNTL_OE_EN_GET(x) (((x) & DDR_CONFIG2_CNTL_OE_EN_MASK) >> DDR_CONFIG2_CNTL_OE_EN_LSB) +#define DDR_CONFIG2_CNTL_OE_EN_SET(x) (((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK) +#define DDR_CONFIG2_CNTL_OE_EN_RESET 0x1 // 1 +#define DDR_CONFIG2_BURST_TYPE_MSB 4 +#define DDR_CONFIG2_BURST_TYPE_LSB 4 +#define DDR_CONFIG2_BURST_TYPE_MASK 0x00000010 +#define DDR_CONFIG2_BURST_TYPE_GET(x) (((x) & DDR_CONFIG2_BURST_TYPE_MASK) >> DDR_CONFIG2_BURST_TYPE_LSB) +#define DDR_CONFIG2_BURST_TYPE_SET(x) (((x) << DDR_CONFIG2_BURST_TYPE_LSB) & DDR_CONFIG2_BURST_TYPE_MASK) +#define DDR_CONFIG2_BURST_TYPE_RESET 0x0 // 0 +#define DDR_CONFIG2_BURST_LENGTH_MSB 3 +#define DDR_CONFIG2_BURST_LENGTH_LSB 0 +#define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f +#define DDR_CONFIG2_BURST_LENGTH_GET(x) (((x) & DDR_CONFIG2_BURST_LENGTH_MASK) >> DDR_CONFIG2_BURST_LENGTH_LSB) +#define DDR_CONFIG2_BURST_LENGTH_SET(x) (((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK) +#define DDR_CONFIG2_BURST_LENGTH_RESET 0x8 // 8 +#define DDR_CONFIG2_ADDRESS 0x18000004 + +#define DDR_CONFIG_3_SPARE_MSB 31 +#define DDR_CONFIG_3_SPARE_LSB 4 +#define DDR_CONFIG_3_SPARE_MASK 0xfffffff0 +#define DDR_CONFIG_3_SPARE_GET(x) (((x) & DDR_CONFIG_3_SPARE_MASK) >> DDR_CONFIG_3_SPARE_LSB) +#define DDR_CONFIG_3_SPARE_SET(x) (((x) << DDR_CONFIG_3_SPARE_LSB) & DDR_CONFIG_3_SPARE_MASK) +#define DDR_CONFIG_3_SPARE_RESET 0x0 // 0 +#define DDR_CONFIG_3_TWR_MSB_MSB 3 +#define DDR_CONFIG_3_TWR_MSB_LSB 3 +#define DDR_CONFIG_3_TWR_MSB_MASK 0x00000008 +#define DDR_CONFIG_3_TWR_MSB_GET(x) (((x) & DDR_CONFIG_3_TWR_MSB_MASK) >> DDR_CONFIG_3_TWR_MSB_LSB) +#define DDR_CONFIG_3_TWR_MSB_SET(x) (((x) << DDR_CONFIG_3_TWR_MSB_LSB) & DDR_CONFIG_3_TWR_MSB_MASK) +#define DDR_CONFIG_3_TWR_MSB_RESET 0x0 // 0 +#define DDR_CONFIG_3_TRAS_MSB_MSB 2 +#define DDR_CONFIG_3_TRAS_MSB_LSB 2 +#define DDR_CONFIG_3_TRAS_MSB_MASK 0x00000004 +#define DDR_CONFIG_3_TRAS_MSB_GET(x) (((x) & DDR_CONFIG_3_TRAS_MSB_MASK) >> DDR_CONFIG_3_TRAS_MSB_LSB) +#define DDR_CONFIG_3_TRAS_MSB_SET(x) (((x) << DDR_CONFIG_3_TRAS_MSB_LSB) & DDR_CONFIG_3_TRAS_MSB_MASK) +#define DDR_CONFIG_3_TRAS_MSB_RESET 0x0 // 0 +#define DDR_CONFIG_3_TRFC_LSB_MSB 1 +#define DDR_CONFIG_3_TRFC_LSB_LSB 0 +#define DDR_CONFIG_3_TRFC_LSB_MASK 0x00000003 +#define DDR_CONFIG_3_TRFC_LSB_GET(x) (((x) & DDR_CONFIG_3_TRFC_LSB_MASK) >> DDR_CONFIG_3_TRFC_LSB_LSB) +#define DDR_CONFIG_3_TRFC_LSB_SET(x) (((x) << DDR_CONFIG_3_TRFC_LSB_LSB) & DDR_CONFIG_3_TRFC_LSB_MASK) +#define DDR_CONFIG_3_TRFC_LSB_RESET 0x0 // 0 +#define DDR_CONFIG_3_ADDRESS 0x1800015c + +#define DDR_MODE_REGISTER_VALUE_MSB 13 +#define DDR_MODE_REGISTER_VALUE_LSB 0 +#define DDR_MODE_REGISTER_VALUE_MASK 0x00003fff +#define DDR_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_MODE_REGISTER_VALUE_MASK) >> DDR_MODE_REGISTER_VALUE_LSB) +#define DDR_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_MODE_REGISTER_VALUE_LSB) & DDR_MODE_REGISTER_VALUE_MASK) +#define DDR_MODE_REGISTER_VALUE_RESET 0x133 // 307 +#define DDR_MODE_REGISTER_ADDRESS 0x18000008 + +#define DDR_EXTENDED_MODE_REGISTER_VALUE_MSB 13 +#define DDR_EXTENDED_MODE_REGISTER_VALUE_LSB 0 +#define DDR_EXTENDED_MODE_REGISTER_VALUE_MASK 0x00003fff +#define DDR_EXTENDED_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK) >> DDR_EXTENDED_MODE_REGISTER_VALUE_LSB) +#define DDR_EXTENDED_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_EXTENDED_MODE_REGISTER_VALUE_LSB) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK) +#define DDR_EXTENDED_MODE_REGISTER_VALUE_RESET 0x2 // 2 +#define DDR_EXTENDED_MODE_REGISTER_ADDRESS 0x1800000c + +#define DDR_REFRESH_ENABLE_MSB 14 +#define DDR_REFRESH_ENABLE_LSB 14 +#define DDR_REFRESH_ENABLE_MASK 0x00004000 +#define DDR_REFRESH_ENABLE_GET(x) (((x) & DDR_REFRESH_ENABLE_MASK) >> DDR_REFRESH_ENABLE_LSB) +#define DDR_REFRESH_ENABLE_SET(x) (((x) << DDR_REFRESH_ENABLE_LSB) & DDR_REFRESH_ENABLE_MASK) +#define DDR_REFRESH_ENABLE_RESET 0x0 // 0 +#define DDR_REFRESH_PERIOD_MSB 13 +#define DDR_REFRESH_PERIOD_LSB 0 +#define DDR_REFRESH_PERIOD_MASK 0x00003fff +#define DDR_REFRESH_PERIOD_GET(x) (((x) & DDR_REFRESH_PERIOD_MASK) >> DDR_REFRESH_PERIOD_LSB) +#define DDR_REFRESH_PERIOD_SET(x) (((x) << DDR_REFRESH_PERIOD_LSB) & DDR_REFRESH_PERIOD_MASK) +#define DDR_REFRESH_PERIOD_RESET 0x12c // 300 +#define DDR_REFRESH_ADDRESS 0x18000014 + +#define BB_DPLL2_LOCAL_PLL_MSB 31 +#define BB_DPLL2_LOCAL_PLL_LSB 31 +#define BB_DPLL2_LOCAL_PLL_MASK 0x80000000 +#define BB_DPLL2_LOCAL_PLL_GET(x) (((x) & BB_DPLL2_LOCAL_PLL_MASK) >> BB_DPLL2_LOCAL_PLL_LSB) +#define BB_DPLL2_LOCAL_PLL_SET(x) (((x) << BB_DPLL2_LOCAL_PLL_LSB) & BB_DPLL2_LOCAL_PLL_MASK) +#define BB_DPLL2_LOCAL_PLL_RESET 0x0 // 0 +#define BB_DPLL2_KI_MSB 30 +#define BB_DPLL2_KI_LSB 29 +#define BB_DPLL2_KI_MASK 0x60000000 +#define BB_DPLL2_KI_GET(x) (((x) & BB_DPLL2_KI_MASK) >> BB_DPLL2_KI_LSB) +#define BB_DPLL2_KI_SET(x) (((x) << BB_DPLL2_KI_LSB) & BB_DPLL2_KI_MASK) +#define BB_DPLL2_KI_RESET 0x2 // 2 +#define BB_DPLL2_KD_MSB 28 +#define BB_DPLL2_KD_LSB 25 +#define BB_DPLL2_KD_MASK 0x1e000000 +#define BB_DPLL2_KD_GET(x) (((x) & BB_DPLL2_KD_MASK) >> BB_DPLL2_KD_LSB) +#define BB_DPLL2_KD_SET(x) (((x) << BB_DPLL2_KD_LSB) & BB_DPLL2_KD_MASK) +#define BB_DPLL2_KD_RESET 0xa // 10 +#define BB_DPLL2_EN_NEGTRIG_MSB 24 +#define BB_DPLL2_EN_NEGTRIG_LSB 24 +#define BB_DPLL2_EN_NEGTRIG_MASK 0x01000000 +#define BB_DPLL2_EN_NEGTRIG_GET(x) (((x) & BB_DPLL2_EN_NEGTRIG_MASK) >> BB_DPLL2_EN_NEGTRIG_LSB) +#define BB_DPLL2_EN_NEGTRIG_SET(x) (((x) << BB_DPLL2_EN_NEGTRIG_LSB) & BB_DPLL2_EN_NEGTRIG_MASK) +#define BB_DPLL2_EN_NEGTRIG_RESET 0x0 // 0 +#define BB_DPLL2_SEL_1SDM_MSB 23 +#define BB_DPLL2_SEL_1SDM_LSB 23 +#define BB_DPLL2_SEL_1SDM_MASK 0x00800000 +#define BB_DPLL2_SEL_1SDM_GET(x) (((x) & BB_DPLL2_SEL_1SDM_MASK) >> BB_DPLL2_SEL_1SDM_LSB) +#define BB_DPLL2_SEL_1SDM_SET(x) (((x) << BB_DPLL2_SEL_1SDM_LSB) & BB_DPLL2_SEL_1SDM_MASK) +#define BB_DPLL2_SEL_1SDM_RESET 0x0 // 0 +#define BB_DPLL2_PLL_PWD_MSB 22 +#define BB_DPLL2_PLL_PWD_LSB 22 +#define BB_DPLL2_PLL_PWD_MASK 0x00400000 +#define BB_DPLL2_PLL_PWD_GET(x) (((x) & BB_DPLL2_PLL_PWD_MASK) >> BB_DPLL2_PLL_PWD_LSB) +#define BB_DPLL2_PLL_PWD_SET(x) (((x) << BB_DPLL2_PLL_PWD_LSB) & BB_DPLL2_PLL_PWD_MASK) +#define BB_DPLL2_PLL_PWD_RESET 0x1 // 1 +#define BB_DPLL2_OUTDIV_MSB 21 +#define BB_DPLL2_OUTDIV_LSB 19 +#define BB_DPLL2_OUTDIV_MASK 0x00380000 +#define BB_DPLL2_OUTDIV_GET(x) (((x) & BB_DPLL2_OUTDIV_MASK) >> BB_DPLL2_OUTDIV_LSB) +#define BB_DPLL2_OUTDIV_SET(x) (((x) << BB_DPLL2_OUTDIV_LSB) & BB_DPLL2_OUTDIV_MASK) +#define BB_DPLL2_OUTDIV_RESET 0x1 // 1 +#define BB_DPLL2_PHASE_SHIFT_MSB 18 +#define BB_DPLL2_PHASE_SHIFT_LSB 12 +#define BB_DPLL2_PHASE_SHIFT_MASK 0x0007f000 +#define BB_DPLL2_PHASE_SHIFT_GET(x) (((x) & BB_DPLL2_PHASE_SHIFT_MASK) >> BB_DPLL2_PHASE_SHIFT_LSB) +#define BB_DPLL2_PHASE_SHIFT_SET(x) (((x) << BB_DPLL2_PHASE_SHIFT_LSB) & BB_DPLL2_PHASE_SHIFT_MASK) +#define BB_DPLL2_PHASE_SHIFT_RESET 0x0 // 0 +#define BB_DPLL2_TESTIN_MSB 11 +#define BB_DPLL2_TESTIN_LSB 2 +#define BB_DPLL2_TESTIN_MASK 0x00000ffc +#define BB_DPLL2_TESTIN_GET(x) (((x) & BB_DPLL2_TESTIN_MASK) >> BB_DPLL2_TESTIN_LSB) +#define BB_DPLL2_TESTIN_SET(x) (((x) << BB_DPLL2_TESTIN_LSB) & BB_DPLL2_TESTIN_MASK) +#define BB_DPLL2_TESTIN_RESET 0x0 // 0 +#define BB_DPLL2_SEL_COUNT_MSB 1 +#define BB_DPLL2_SEL_COUNT_LSB 1 +#define BB_DPLL2_SEL_COUNT_MASK 0x00000002 +#define BB_DPLL2_SEL_COUNT_GET(x) (((x) & BB_DPLL2_SEL_COUNT_MASK) >> BB_DPLL2_SEL_COUNT_LSB) +#define BB_DPLL2_SEL_COUNT_SET(x) (((x) << BB_DPLL2_SEL_COUNT_LSB) & BB_DPLL2_SEL_COUNT_MASK) +#define BB_DPLL2_SEL_COUNT_RESET 0x0 // 0 +#define BB_DPLL2_RESET_TEST_MSB 0 +#define BB_DPLL2_RESET_TEST_LSB 0 +#define BB_DPLL2_RESET_TEST_MASK 0x00000001 +#define BB_DPLL2_RESET_TEST_GET(x) (((x) & BB_DPLL2_RESET_TEST_MASK) >> BB_DPLL2_RESET_TEST_LSB) +#define BB_DPLL2_RESET_TEST_SET(x) (((x) << BB_DPLL2_RESET_TEST_LSB) & BB_DPLL2_RESET_TEST_MASK) +#define BB_DPLL2_RESET_TEST_RESET 0x0 // 0 +#define BB_DPLL2_ADDRESS 0x18116184 + +#define PCIe_DPLL2_LOCAL_PLL_MSB 31 +#define PCIe_DPLL2_LOCAL_PLL_LSB 31 +#define PCIe_DPLL2_LOCAL_PLL_MASK 0x80000000 +#define PCIe_DPLL2_LOCAL_PLL_GET(x) (((x) & PCIe_DPLL2_LOCAL_PLL_MASK) >> PCIe_DPLL2_LOCAL_PLL_LSB) +#define PCIe_DPLL2_LOCAL_PLL_SET(x) (((x) << PCIe_DPLL2_LOCAL_PLL_LSB) & PCIe_DPLL2_LOCAL_PLL_MASK) +#define PCIe_DPLL2_LOCAL_PLL_RESET 0x0 // 0 +#define PCIe_DPLL2_KI_MSB 30 +#define PCIe_DPLL2_KI_LSB 29 +#define PCIe_DPLL2_KI_MASK 0x60000000 +#define PCIe_DPLL2_KI_GET(x) (((x) & PCIe_DPLL2_KI_MASK) >> PCIe_DPLL2_KI_LSB) +#define PCIe_DPLL2_KI_SET(x) (((x) << PCIe_DPLL2_KI_LSB) & PCIe_DPLL2_KI_MASK) +#define PCIe_DPLL2_KI_RESET 0x2 // 2 +#define PCIe_DPLL2_KD_MSB 28 +#define PCIe_DPLL2_KD_LSB 25 +#define PCIe_DPLL2_KD_MASK 0x1e000000 +#define PCIe_DPLL2_KD_GET(x) (((x) & PCIe_DPLL2_KD_MASK) >> PCIe_DPLL2_KD_LSB) +#define PCIe_DPLL2_KD_SET(x) (((x) << PCIe_DPLL2_KD_LSB) & PCIe_DPLL2_KD_MASK) +#define PCIe_DPLL2_KD_RESET 0xa // 10 +#define PCIe_DPLL2_EN_NEGTRIG_MSB 24 +#define PCIe_DPLL2_EN_NEGTRIG_LSB 24 +#define PCIe_DPLL2_EN_NEGTRIG_MASK 0x01000000 +#define PCIe_DPLL2_EN_NEGTRIG_GET(x) (((x) & PCIe_DPLL2_EN_NEGTRIG_MASK) >> PCIe_DPLL2_EN_NEGTRIG_LSB) +#define PCIe_DPLL2_EN_NEGTRIG_SET(x) (((x) << PCIe_DPLL2_EN_NEGTRIG_LSB) & PCIe_DPLL2_EN_NEGTRIG_MASK) +#define PCIe_DPLL2_EN_NEGTRIG_RESET 0x0 // 0 +#define PCIe_DPLL2_SEL_1SDM_MSB 23 +#define PCIe_DPLL2_SEL_1SDM_LSB 23 +#define PCIe_DPLL2_SEL_1SDM_MASK 0x00800000 +#define PCIe_DPLL2_SEL_1SDM_GET(x) (((x) & PCIe_DPLL2_SEL_1SDM_MASK) >> PCIe_DPLL2_SEL_1SDM_LSB) +#define PCIe_DPLL2_SEL_1SDM_SET(x) (((x) << PCIe_DPLL2_SEL_1SDM_LSB) & PCIe_DPLL2_SEL_1SDM_MASK) +#define PCIe_DPLL2_SEL_1SDM_RESET 0x0 // 0 +#define PCIe_DPLL2_PLL_PWD_MSB 22 +#define PCIe_DPLL2_PLL_PWD_LSB 22 +#define PCIe_DPLL2_PLL_PWD_MASK 0x00400000 +#define PCIe_DPLL2_PLL_PWD_GET(x) (((x) & PCIe_DPLL2_PLL_PWD_MASK) >> PCIe_DPLL2_PLL_PWD_LSB) +#define PCIe_DPLL2_PLL_PWD_SET(x) (((x) << PCIe_DPLL2_PLL_PWD_LSB) & PCIe_DPLL2_PLL_PWD_MASK) +#define PCIe_DPLL2_PLL_PWD_RESET 0x1 // 1 +#define PCIe_DPLL2_OUTDIV_MSB 21 +#define PCIe_DPLL2_OUTDIV_LSB 19 +#define PCIe_DPLL2_OUTDIV_MASK 0x00380000 +#define PCIe_DPLL2_OUTDIV_GET(x) (((x) & PCIe_DPLL2_OUTDIV_MASK) >> PCIe_DPLL2_OUTDIV_LSB) +#define PCIe_DPLL2_OUTDIV_SET(x) (((x) << PCIe_DPLL2_OUTDIV_LSB) & PCIe_DPLL2_OUTDIV_MASK) +#define PCIe_DPLL2_OUTDIV_RESET 0x1 // 1 +#define PCIe_DPLL2_PHASE_SHIFT_MSB 18 +#define PCIe_DPLL2_PHASE_SHIFT_LSB 12 +#define PCIe_DPLL2_PHASE_SHIFT_MASK 0x0007f000 +#define PCIe_DPLL2_PHASE_SHIFT_GET(x) (((x) & PCIe_DPLL2_PHASE_SHIFT_MASK) >> PCIe_DPLL2_PHASE_SHIFT_LSB) +#define PCIe_DPLL2_PHASE_SHIFT_SET(x) (((x) << PCIe_DPLL2_PHASE_SHIFT_LSB) & PCIe_DPLL2_PHASE_SHIFT_MASK) +#define PCIe_DPLL2_PHASE_SHIFT_RESET 0x0 // 0 +#define PCIe_DPLL2_TESTIN_MSB 11 +#define PCIe_DPLL2_TESTIN_LSB 2 +#define PCIe_DPLL2_TESTIN_MASK 0x00000ffc +#define PCIe_DPLL2_TESTIN_GET(x) (((x) & PCIe_DPLL2_TESTIN_MASK) >> PCIe_DPLL2_TESTIN_LSB) +#define PCIe_DPLL2_TESTIN_SET(x) (((x) << PCIe_DPLL2_TESTIN_LSB) & PCIe_DPLL2_TESTIN_MASK) +#define PCIe_DPLL2_TESTIN_RESET 0x0 // 0 +#define PCIe_DPLL2_SEL_COUNT_MSB 1 +#define PCIe_DPLL2_SEL_COUNT_LSB 1 +#define PCIe_DPLL2_SEL_COUNT_MASK 0x00000002 +#define PCIe_DPLL2_SEL_COUNT_GET(x) (((x) & PCIe_DPLL2_SEL_COUNT_MASK) >> PCIe_DPLL2_SEL_COUNT_LSB) +#define PCIe_DPLL2_SEL_COUNT_SET(x) (((x) << PCIe_DPLL2_SEL_COUNT_LSB) & PCIe_DPLL2_SEL_COUNT_MASK) +#define PCIe_DPLL2_SEL_COUNT_RESET 0x0 // 0 +#define PCIe_DPLL2_RESET_TEST_MSB 0 +#define PCIe_DPLL2_RESET_TEST_LSB 0 +#define PCIe_DPLL2_RESET_TEST_MASK 0x00000001 +#define PCIe_DPLL2_RESET_TEST_GET(x) (((x) & PCIe_DPLL2_RESET_TEST_MASK) >> PCIe_DPLL2_RESET_TEST_LSB) +#define PCIe_DPLL2_RESET_TEST_SET(x) (((x) << PCIe_DPLL2_RESET_TEST_LSB) & PCIe_DPLL2_RESET_TEST_MASK) +#define PCIe_DPLL2_RESET_TEST_RESET 0x0 // 0 +#define PCIe_DPLL2_ADDRESS 0x18116c04 + +#define DDR_DPLL2_LOCAL_PLL_MSB 31 +#define DDR_DPLL2_LOCAL_PLL_LSB 31 +#define DDR_DPLL2_LOCAL_PLL_MASK 0x80000000 +#define DDR_DPLL2_LOCAL_PLL_GET(x) (((x) & DDR_DPLL2_LOCAL_PLL_MASK) >> DDR_DPLL2_LOCAL_PLL_LSB) +#define DDR_DPLL2_LOCAL_PLL_SET(x) (((x) << DDR_DPLL2_LOCAL_PLL_LSB) & DDR_DPLL2_LOCAL_PLL_MASK) +#define DDR_DPLL2_LOCAL_PLL_RESET 0x0 // 0 +#define DDR_DPLL2_KI_MSB 30 +#define DDR_DPLL2_KI_LSB 29 +#define DDR_DPLL2_KI_MASK 0x60000000 +#define DDR_DPLL2_KI_GET(x) (((x) & DDR_DPLL2_KI_MASK) >> DDR_DPLL2_KI_LSB) +#define DDR_DPLL2_KI_SET(x) (((x) << DDR_DPLL2_KI_LSB) & DDR_DPLL2_KI_MASK) +#define DDR_DPLL2_KI_RESET 0x2 // 2 +#define DDR_DPLL2_KD_MSB 28 +#define DDR_DPLL2_KD_LSB 25 +#define DDR_DPLL2_KD_MASK 0x1e000000 +#define DDR_DPLL2_KD_GET(x) (((x) & DDR_DPLL2_KD_MASK) >> DDR_DPLL2_KD_LSB) +#define DDR_DPLL2_KD_SET(x) (((x) << DDR_DPLL2_KD_LSB) & DDR_DPLL2_KD_MASK) +#define DDR_DPLL2_KD_RESET 0xa // 10 +#define DDR_DPLL2_EN_NEGTRIG_MSB 24 +#define DDR_DPLL2_EN_NEGTRIG_LSB 24 +#define DDR_DPLL2_EN_NEGTRIG_MASK 0x01000000 +#define DDR_DPLL2_EN_NEGTRIG_GET(x) (((x) & DDR_DPLL2_EN_NEGTRIG_MASK) >> DDR_DPLL2_EN_NEGTRIG_LSB) +#define DDR_DPLL2_EN_NEGTRIG_SET(x) (((x) << DDR_DPLL2_EN_NEGTRIG_LSB) & DDR_DPLL2_EN_NEGTRIG_MASK) +#define DDR_DPLL2_EN_NEGTRIG_RESET 0x0 // 0 +#define DDR_DPLL2_SEL_1SDM_MSB 23 +#define DDR_DPLL2_SEL_1SDM_LSB 23 +#define DDR_DPLL2_SEL_1SDM_MASK 0x00800000 +#define DDR_DPLL2_SEL_1SDM_GET(x) (((x) & DDR_DPLL2_SEL_1SDM_MASK) >> DDR_DPLL2_SEL_1SDM_LSB) +#define DDR_DPLL2_SEL_1SDM_SET(x) (((x) << DDR_DPLL2_SEL_1SDM_LSB) & DDR_DPLL2_SEL_1SDM_MASK) +#define DDR_DPLL2_SEL_1SDM_RESET 0x0 // 0 +#define DDR_DPLL2_PLL_PWD_MSB 22 +#define DDR_DPLL2_PLL_PWD_LSB 22 +#define DDR_DPLL2_PLL_PWD_MASK 0x00400000 +#define DDR_DPLL2_PLL_PWD_GET(x) (((x) & DDR_DPLL2_PLL_PWD_MASK) >> DDR_DPLL2_PLL_PWD_LSB) +#define DDR_DPLL2_PLL_PWD_SET(x) (((x) << DDR_DPLL2_PLL_PWD_LSB) & DDR_DPLL2_PLL_PWD_MASK) +#define DDR_DPLL2_PLL_PWD_RESET 0x1 // 1 +#define DDR_DPLL2_OUTDIV_MSB 21 +#define DDR_DPLL2_OUTDIV_LSB 19 +#define DDR_DPLL2_OUTDIV_MASK 0x00380000 +#define DDR_DPLL2_OUTDIV_GET(x) (((x) & DDR_DPLL2_OUTDIV_MASK) >> DDR_DPLL2_OUTDIV_LSB) +#define DDR_DPLL2_OUTDIV_SET(x) (((x) << DDR_DPLL2_OUTDIV_LSB) & DDR_DPLL2_OUTDIV_MASK) +#define DDR_DPLL2_OUTDIV_RESET 0x1 // 1 +#define DDR_DPLL2_PHASE_SHIFT_MSB 18 +#define DDR_DPLL2_PHASE_SHIFT_LSB 12 +#define DDR_DPLL2_PHASE_SHIFT_MASK 0x0007f000 +#define DDR_DPLL2_PHASE_SHIFT_GET(x) (((x) & DDR_DPLL2_PHASE_SHIFT_MASK) >> DDR_DPLL2_PHASE_SHIFT_LSB) +#define DDR_DPLL2_PHASE_SHIFT_SET(x) (((x) << DDR_DPLL2_PHASE_SHIFT_LSB) & DDR_DPLL2_PHASE_SHIFT_MASK) +#define DDR_DPLL2_PHASE_SHIFT_RESET 0x0 // 0 +#define DDR_DPLL2_TESTIN_MSB 11 +#define DDR_DPLL2_TESTIN_LSB 2 +#define DDR_DPLL2_TESTIN_MASK 0x00000ffc +#define DDR_DPLL2_TESTIN_GET(x) (((x) & DDR_DPLL2_TESTIN_MASK) >> DDR_DPLL2_TESTIN_LSB) +#define DDR_DPLL2_TESTIN_SET(x) (((x) << DDR_DPLL2_TESTIN_LSB) & DDR_DPLL2_TESTIN_MASK) +#define DDR_DPLL2_TESTIN_RESET 0x0 // 0 +#define DDR_DPLL2_SEL_COUNT_MSB 1 +#define DDR_DPLL2_SEL_COUNT_LSB 1 +#define DDR_DPLL2_SEL_COUNT_MASK 0x00000002 +#define DDR_DPLL2_SEL_COUNT_GET(x) (((x) & DDR_DPLL2_SEL_COUNT_MASK) >> DDR_DPLL2_SEL_COUNT_LSB) +#define DDR_DPLL2_SEL_COUNT_SET(x) (((x) << DDR_DPLL2_SEL_COUNT_LSB) & DDR_DPLL2_SEL_COUNT_MASK) +#define DDR_DPLL2_SEL_COUNT_RESET 0x0 // 0 +#define DDR_DPLL2_RESET_TEST_MSB 0 +#define DDR_DPLL2_RESET_TEST_LSB 0 +#define DDR_DPLL2_RESET_TEST_MASK 0x00000001 +#define DDR_DPLL2_RESET_TEST_GET(x) (((x) & DDR_DPLL2_RESET_TEST_MASK) >> DDR_DPLL2_RESET_TEST_LSB) +#define DDR_DPLL2_RESET_TEST_SET(x) (((x) << DDR_DPLL2_RESET_TEST_LSB) & DDR_DPLL2_RESET_TEST_MASK) +#define DDR_DPLL2_RESET_TEST_RESET 0x0 // 0 +#define DDR_DPLL2_ADDRESS 0x18116244 + +#define CPU_DPLL2_LOCAL_PLL_MSB 31 +#define CPU_DPLL2_LOCAL_PLL_LSB 31 +#define CPU_DPLL2_LOCAL_PLL_MASK 0x80000000 +#define CPU_DPLL2_LOCAL_PLL_GET(x) (((x) & CPU_DPLL2_LOCAL_PLL_MASK) >> CPU_DPLL2_LOCAL_PLL_LSB) +#define CPU_DPLL2_LOCAL_PLL_SET(x) (((x) << CPU_DPLL2_LOCAL_PLL_LSB) & CPU_DPLL2_LOCAL_PLL_MASK) +#define CPU_DPLL2_LOCAL_PLL_RESET 0x0 // 0 +#define CPU_DPLL2_KI_MSB 30 +#define CPU_DPLL2_KI_LSB 29 +#define CPU_DPLL2_KI_MASK 0x60000000 +#define CPU_DPLL2_KI_GET(x) (((x) & CPU_DPLL2_KI_MASK) >> CPU_DPLL2_KI_LSB) +#define CPU_DPLL2_KI_SET(x) (((x) << CPU_DPLL2_KI_LSB) & CPU_DPLL2_KI_MASK) +#define CPU_DPLL2_KI_RESET 0x2 // 2 +#define CPU_DPLL2_KD_MSB 28 +#define CPU_DPLL2_KD_LSB 25 +#define CPU_DPLL2_KD_MASK 0x1e000000 +#define CPU_DPLL2_KD_GET(x) (((x) & CPU_DPLL2_KD_MASK) >> CPU_DPLL2_KD_LSB) +#define CPU_DPLL2_KD_SET(x) (((x) << CPU_DPLL2_KD_LSB) & CPU_DPLL2_KD_MASK) +#define CPU_DPLL2_KD_RESET 0xa // 10 +#define CPU_DPLL2_EN_NEGTRIG_MSB 24 +#define CPU_DPLL2_EN_NEGTRIG_LSB 24 +#define CPU_DPLL2_EN_NEGTRIG_MASK 0x01000000 +#define CPU_DPLL2_EN_NEGTRIG_GET(x) (((x) & CPU_DPLL2_EN_NEGTRIG_MASK) >> CPU_DPLL2_EN_NEGTRIG_LSB) +#define CPU_DPLL2_EN_NEGTRIG_SET(x) (((x) << CPU_DPLL2_EN_NEGTRIG_LSB) & CPU_DPLL2_EN_NEGTRIG_MASK) +#define CPU_DPLL2_EN_NEGTRIG_RESET 0x0 // 0 +#define CPU_DPLL2_SEL_1SDM_MSB 23 +#define CPU_DPLL2_SEL_1SDM_LSB 23 +#define CPU_DPLL2_SEL_1SDM_MASK 0x00800000 +#define CPU_DPLL2_SEL_1SDM_GET(x) (((x) & CPU_DPLL2_SEL_1SDM_MASK) >> CPU_DPLL2_SEL_1SDM_LSB) +#define CPU_DPLL2_SEL_1SDM_SET(x) (((x) << CPU_DPLL2_SEL_1SDM_LSB) & CPU_DPLL2_SEL_1SDM_MASK) +#define CPU_DPLL2_SEL_1SDM_RESET 0x0 // 0 +#define CPU_DPLL2_PLL_PWD_MSB 22 +#define CPU_DPLL2_PLL_PWD_LSB 22 +#define CPU_DPLL2_PLL_PWD_MASK 0x00400000 +#define CPU_DPLL2_PLL_PWD_GET(x) (((x) & CPU_DPLL2_PLL_PWD_MASK) >> CPU_DPLL2_PLL_PWD_LSB) +#define CPU_DPLL2_PLL_PWD_SET(x) (((x) << CPU_DPLL2_PLL_PWD_LSB) & CPU_DPLL2_PLL_PWD_MASK) +#define CPU_DPLL2_PLL_PWD_RESET 0x1 // 1 +#define CPU_DPLL2_OUTDIV_MSB 21 +#define CPU_DPLL2_OUTDIV_LSB 19 +#define CPU_DPLL2_OUTDIV_MASK 0x00380000 +#define CPU_DPLL2_OUTDIV_GET(x) (((x) & CPU_DPLL2_OUTDIV_MASK) >> CPU_DPLL2_OUTDIV_LSB) +#define CPU_DPLL2_OUTDIV_SET(x) (((x) << CPU_DPLL2_OUTDIV_LSB) & CPU_DPLL2_OUTDIV_MASK) +#define CPU_DPLL2_OUTDIV_RESET 0x1 // 1 +#define CPU_DPLL2_PHASE_SHIFT_MSB 18 +#define CPU_DPLL2_PHASE_SHIFT_LSB 12 +#define CPU_DPLL2_PHASE_SHIFT_MASK 0x0007f000 +#define CPU_DPLL2_PHASE_SHIFT_GET(x) (((x) & CPU_DPLL2_PHASE_SHIFT_MASK) >> CPU_DPLL2_PHASE_SHIFT_LSB) +#define CPU_DPLL2_PHASE_SHIFT_SET(x) (((x) << CPU_DPLL2_PHASE_SHIFT_LSB) & CPU_DPLL2_PHASE_SHIFT_MASK) +#define CPU_DPLL2_PHASE_SHIFT_RESET 0x0 // 0 +#define CPU_DPLL2_TESTIN_MSB 11 +#define CPU_DPLL2_TESTIN_LSB 2 +#define CPU_DPLL2_TESTIN_MASK 0x00000ffc +#define CPU_DPLL2_TESTIN_GET(x) (((x) & CPU_DPLL2_TESTIN_MASK) >> CPU_DPLL2_TESTIN_LSB) +#define CPU_DPLL2_TESTIN_SET(x) (((x) << CPU_DPLL2_TESTIN_LSB) & CPU_DPLL2_TESTIN_MASK) +#define CPU_DPLL2_TESTIN_RESET 0x0 // 0 +#define CPU_DPLL2_SEL_COUNT_MSB 1 +#define CPU_DPLL2_SEL_COUNT_LSB 1 +#define CPU_DPLL2_SEL_COUNT_MASK 0x00000002 +#define CPU_DPLL2_SEL_COUNT_GET(x) (((x) & CPU_DPLL2_SEL_COUNT_MASK) >> CPU_DPLL2_SEL_COUNT_LSB) +#define CPU_DPLL2_SEL_COUNT_SET(x) (((x) << CPU_DPLL2_SEL_COUNT_LSB) & CPU_DPLL2_SEL_COUNT_MASK) +#define CPU_DPLL2_SEL_COUNT_RESET 0x0 // 0 +#define CPU_DPLL2_RESET_TEST_MSB 0 +#define CPU_DPLL2_RESET_TEST_LSB 0 +#define CPU_DPLL2_RESET_TEST_MASK 0x00000001 +#define CPU_DPLL2_RESET_TEST_GET(x) (((x) & CPU_DPLL2_RESET_TEST_MASK) >> CPU_DPLL2_RESET_TEST_LSB) +#define CPU_DPLL2_RESET_TEST_SET(x) (((x) << CPU_DPLL2_RESET_TEST_LSB) & CPU_DPLL2_RESET_TEST_MASK) +#define CPU_DPLL2_RESET_TEST_RESET 0x0 // 0 +#define CPU_DPLL2_ADDRESS 0x181161c4 + +#define DDR_RD_DATA_THIS_CYCLE_ADDRESS 0x18000018 + +#define TAP_CONTROL_0_ADDRESS 0x1800001c +#define TAP_CONTROL_1_ADDRESS 0x18000020 +#define TAP_CONTROL_2_ADDRESS 0x18000024 +#define TAP_CONTROL_3_ADDRESS 0x18000028 + +#define DDR_BURST_CPU_PRIORITY_MSB 31 +#define DDR_BURST_CPU_PRIORITY_LSB 31 +#define DDR_BURST_CPU_PRIORITY_MASK 0x80000000 +#define DDR_BURST_CPU_PRIORITY_GET(x) (((x) & DDR_BURST_CPU_PRIORITY_MASK) >> DDR_BURST_CPU_PRIORITY_LSB) +#define DDR_BURST_CPU_PRIORITY_SET(x) (((x) << DDR_BURST_CPU_PRIORITY_LSB) & DDR_BURST_CPU_PRIORITY_MASK) +#define DDR_BURST_CPU_PRIORITY_RESET 0x0 // 0 +#define DDR_BURST_CPU_PRIORITY_BE_MSB 30 +#define DDR_BURST_CPU_PRIORITY_BE_LSB 30 +#define DDR_BURST_CPU_PRIORITY_BE_MASK 0x40000000 +#define DDR_BURST_CPU_PRIORITY_BE_GET(x) (((x) & DDR_BURST_CPU_PRIORITY_BE_MASK) >> DDR_BURST_CPU_PRIORITY_BE_LSB) +#define DDR_BURST_CPU_PRIORITY_BE_SET(x) (((x) << DDR_BURST_CPU_PRIORITY_BE_LSB) & DDR_BURST_CPU_PRIORITY_BE_MASK) +#define DDR_BURST_CPU_PRIORITY_BE_RESET 0x1 // 1 +#define DDR_BURST_ENABLE_RWP_MASK_MSB 29 +#define DDR_BURST_ENABLE_RWP_MASK_LSB 28 +#define DDR_BURST_ENABLE_RWP_MASK_MASK 0x30000000 +#define DDR_BURST_ENABLE_RWP_MASK_GET(x) (((x) & DDR_BURST_ENABLE_RWP_MASK_MASK) >> DDR_BURST_ENABLE_RWP_MASK_LSB) +#define DDR_BURST_ENABLE_RWP_MASK_SET(x) (((x) << DDR_BURST_ENABLE_RWP_MASK_LSB) & DDR_BURST_ENABLE_RWP_MASK_MASK) +#define DDR_BURST_ENABLE_RWP_MASK_RESET 0x3 // 3 +#define DDR_BURST_MAX_WRITE_BURST_MSB 27 +#define DDR_BURST_MAX_WRITE_BURST_LSB 24 +#define DDR_BURST_MAX_WRITE_BURST_MASK 0x0f000000 +#define DDR_BURST_MAX_WRITE_BURST_GET(x) (((x) & DDR_BURST_MAX_WRITE_BURST_MASK) >> DDR_BURST_MAX_WRITE_BURST_LSB) +#define DDR_BURST_MAX_WRITE_BURST_SET(x) (((x) << DDR_BURST_MAX_WRITE_BURST_LSB) & DDR_BURST_MAX_WRITE_BURST_MASK) +#define DDR_BURST_MAX_WRITE_BURST_RESET 0x4 // 4 +#define DDR_BURST_MAX_READ_BURST_MSB 23 +#define DDR_BURST_MAX_READ_BURST_LSB 20 +#define DDR_BURST_MAX_READ_BURST_MASK 0x00f00000 +#define DDR_BURST_MAX_READ_BURST_GET(x) (((x) & DDR_BURST_MAX_READ_BURST_MASK) >> DDR_BURST_MAX_READ_BURST_LSB) +#define DDR_BURST_MAX_READ_BURST_SET(x) (((x) << DDR_BURST_MAX_READ_BURST_LSB) & DDR_BURST_MAX_READ_BURST_MASK) +#define DDR_BURST_MAX_READ_BURST_RESET 0x4 // 4 +#define DDR_BURST_CPU_MAX_BL_MSB 19 +#define DDR_BURST_CPU_MAX_BL_LSB 16 +#define DDR_BURST_CPU_MAX_BL_MASK 0x000f0000 +#define DDR_BURST_CPU_MAX_BL_GET(x) (((x) & DDR_BURST_CPU_MAX_BL_MASK) >> DDR_BURST_CPU_MAX_BL_LSB) +#define DDR_BURST_CPU_MAX_BL_SET(x) (((x) << DDR_BURST_CPU_MAX_BL_LSB) & DDR_BURST_CPU_MAX_BL_MASK) +#define DDR_BURST_CPU_MAX_BL_RESET 0x3 // 3 +#define DDR_BURST_USB_MAX_BL_MSB 15 +#define DDR_BURST_USB_MAX_BL_LSB 12 +#define DDR_BURST_USB_MAX_BL_MASK 0x0000f000 +#define DDR_BURST_USB_MAX_BL_GET(x) (((x) & DDR_BURST_USB_MAX_BL_MASK) >> DDR_BURST_USB_MAX_BL_LSB) +#define DDR_BURST_USB_MAX_BL_SET(x) (((x) << DDR_BURST_USB_MAX_BL_LSB) & DDR_BURST_USB_MAX_BL_MASK) +#define DDR_BURST_USB_MAX_BL_RESET 0x4 // 4 +#define DDR_BURST_PCIE_MAX_BL_MSB 11 +#define DDR_BURST_PCIE_MAX_BL_LSB 8 +#define DDR_BURST_PCIE_MAX_BL_MASK 0x00000f00 +#define DDR_BURST_PCIE_MAX_BL_GET(x) (((x) & DDR_BURST_PCIE_MAX_BL_MASK) >> DDR_BURST_PCIE_MAX_BL_LSB) +#define DDR_BURST_PCIE_MAX_BL_SET(x) (((x) << DDR_BURST_PCIE_MAX_BL_LSB) & DDR_BURST_PCIE_MAX_BL_MASK) +#define DDR_BURST_PCIE_MAX_BL_RESET 0x3 // 3 +#define DDR_BURST_GE1_MAX_BL_MSB 7 +#define DDR_BURST_GE1_MAX_BL_LSB 4 +#define DDR_BURST_GE1_MAX_BL_MASK 0x000000f0 +#define DDR_BURST_GE1_MAX_BL_GET(x) (((x) & DDR_BURST_GE1_MAX_BL_MASK) >> DDR_BURST_GE1_MAX_BL_LSB) +#define DDR_BURST_GE1_MAX_BL_SET(x) (((x) << DDR_BURST_GE1_MAX_BL_LSB) & DDR_BURST_GE1_MAX_BL_MASK) +#define DDR_BURST_GE1_MAX_BL_RESET 0x3 // 3 +#define DDR_BURST_GE0_MAX_BL_MSB 3 +#define DDR_BURST_GE0_MAX_BL_LSB 0 +#define DDR_BURST_GE0_MAX_BL_MASK 0x0000000f +#define DDR_BURST_GE0_MAX_BL_GET(x) (((x) & DDR_BURST_GE0_MAX_BL_MASK) >> DDR_BURST_GE0_MAX_BL_LSB) +#define DDR_BURST_GE0_MAX_BL_SET(x) (((x) << DDR_BURST_GE0_MAX_BL_LSB) & DDR_BURST_GE0_MAX_BL_MASK) +#define DDR_BURST_GE0_MAX_BL_RESET 0x3 // 3 +#define DDR_BURST_ADDRESS 0x180000c4 + +#define DDR_BURST2_WMAC_MAX_BL_MSB 3 +#define DDR_BURST2_WMAC_MAX_BL_LSB 0 +#define DDR_BURST2_WMAC_MAX_BL_MASK 0x0000000f +#define DDR_BURST2_WMAC_MAX_BL_GET(x) (((x) & DDR_BURST2_WMAC_MAX_BL_MASK) >> DDR_BURST2_WMAC_MAX_BL_LSB) +#define DDR_BURST2_WMAC_MAX_BL_SET(x) (((x) << DDR_BURST2_WMAC_MAX_BL_LSB) & DDR_BURST2_WMAC_MAX_BL_MASK) +#define DDR_BURST2_WMAC_MAX_BL_RESET 0x3 // 3 +#define DDR_BURST2_ADDRESS 0x180000c8 + +#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MSB 19 +#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB 0 +#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK 0x000fffff +#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_GET(x) (((x) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK) >> DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB) +#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_SET(x) (((x) << DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK) +#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_RESET 0x8000 // 32768 +#define DDR_AHB_MASTER_TIMEOUT_MAX_ADDRESS 0x180000cc + +#define PMU1_ADDRESS 0x18116c40 + +#define PMU2_SWREGMSB_MSB 31 +#define PMU2_SWREGMSB_LSB 22 +#define PMU2_SWREGMSB_MASK 0xffc00000 +#define PMU2_SWREGMSB_GET(x) (((x) & PMU2_SWREGMSB_MASK) >> PMU2_SWREGMSB_LSB) +#define PMU2_SWREGMSB_SET(x) (((x) << PMU2_SWREGMSB_LSB) & PMU2_SWREGMSB_MASK) +#define PMU2_SWREGMSB_RESET 0x0 // 0 +#define PMU2_PGM_MSB 21 +#define PMU2_PGM_LSB 21 +#define PMU2_PGM_MASK 0x00200000 +#define PMU2_PGM_GET(x) (((x) & PMU2_PGM_MASK) >> PMU2_PGM_LSB) +#define PMU2_PGM_SET(x) (((x) << PMU2_PGM_LSB) & PMU2_PGM_MASK) +#define PMU2_PGM_RESET 0x0 // 0 +#define PMU2_LDO_TUNE_MSB 20 +#define PMU2_LDO_TUNE_LSB 19 +#define PMU2_LDO_TUNE_MASK 0x00180000 +#define PMU2_LDO_TUNE_GET(x) (((x) & PMU2_LDO_TUNE_MASK) >> PMU2_LDO_TUNE_LSB) +#define PMU2_LDO_TUNE_SET(x) (((x) << PMU2_LDO_TUNE_LSB) & PMU2_LDO_TUNE_MASK) +#define PMU2_LDO_TUNE_RESET 0x0 // 0 +#define PMU2_PWDLDO_DDR_MSB 18 +#define PMU2_PWDLDO_DDR_LSB 18 +#define PMU2_PWDLDO_DDR_MASK 0x00040000 +#define PMU2_PWDLDO_DDR_GET(x) (((x) & PMU2_PWDLDO_DDR_MASK) >> PMU2_PWDLDO_DDR_LSB) +#define PMU2_PWDLDO_DDR_SET(x) (((x) << PMU2_PWDLDO_DDR_LSB) & PMU2_PWDLDO_DDR_MASK) +#define PMU2_PWDLDO_DDR_RESET 0x0 // 0 +#define PMU2_LPOPWD_MSB 17 +#define PMU2_LPOPWD_LSB 17 +#define PMU2_LPOPWD_MASK 0x00020000 +#define PMU2_LPOPWD_GET(x) (((x) & PMU2_LPOPWD_MASK) >> PMU2_LPOPWD_LSB) +#define PMU2_LPOPWD_SET(x) (((x) << PMU2_LPOPWD_LSB) & PMU2_LPOPWD_MASK) +#define PMU2_LPOPWD_RESET 0x0 // 0 +#define PMU2_SPARE_MSB 16 +#define PMU2_SPARE_LSB 0 +#define PMU2_SPARE_MASK 0x0001ffff +#define PMU2_SPARE_GET(x) (((x) & PMU2_SPARE_MASK) >> PMU2_SPARE_LSB) +#define PMU2_SPARE_SET(x) (((x) << PMU2_SPARE_LSB) & PMU2_SPARE_MASK) +#define PMU2_SPARE_RESET 0x0 // 0 +#define PMU2_ADDRESS 0x18116c44 + +#define PHY_CTRL0_LOOPBACK_ERR_CNT_MSB 31 +#define PHY_CTRL0_LOOPBACK_ERR_CNT_LSB 24 +#define PHY_CTRL0_LOOPBACK_ERR_CNT_MASK 0xff000000 +#define PHY_CTRL0_LOOPBACK_ERR_CNT_GET(x) (((x) & PHY_CTRL0_LOOPBACK_ERR_CNT_MASK) >> PHY_CTRL0_LOOPBACK_ERR_CNT_LSB) +#define PHY_CTRL0_LOOPBACK_ERR_CNT_SET(x) (((x) << PHY_CTRL0_LOOPBACK_ERR_CNT_LSB) & PHY_CTRL0_LOOPBACK_ERR_CNT_MASK) +#define PHY_CTRL0_LOOPBACK_ERR_CNT_RESET 0x0 // 0 +#define PHY_CTRL0_DIG_LOOPBACK_EN_MSB 23 +#define PHY_CTRL0_DIG_LOOPBACK_EN_LSB 23 +#define PHY_CTRL0_DIG_LOOPBACK_EN_MASK 0x00800000 +#define PHY_CTRL0_DIG_LOOPBACK_EN_GET(x) (((x) & PHY_CTRL0_DIG_LOOPBACK_EN_MASK) >> PHY_CTRL0_DIG_LOOPBACK_EN_LSB) +#define PHY_CTRL0_DIG_LOOPBACK_EN_SET(x) (((x) << PHY_CTRL0_DIG_LOOPBACK_EN_LSB) & PHY_CTRL0_DIG_LOOPBACK_EN_MASK) +#define PHY_CTRL0_DIG_LOOPBACK_EN_RESET 0x0 // 0 +#define PHY_CTRL0_ANA_LOOPBACK_EN_MSB 22 +#define PHY_CTRL0_ANA_LOOPBACK_EN_LSB 22 +#define PHY_CTRL0_ANA_LOOPBACK_EN_MASK 0x00400000 +#define PHY_CTRL0_ANA_LOOPBACK_EN_GET(x) (((x) & PHY_CTRL0_ANA_LOOPBACK_EN_MASK) >> PHY_CTRL0_ANA_LOOPBACK_EN_LSB) +#define PHY_CTRL0_ANA_LOOPBACK_EN_SET(x) (((x) << PHY_CTRL0_ANA_LOOPBACK_EN_LSB) & PHY_CTRL0_ANA_LOOPBACK_EN_MASK) +#define PHY_CTRL0_ANA_LOOPBACK_EN_RESET 0x0 // 0 +#define PHY_CTRL0_TX_PATTERN_EN_MSB 21 +#define PHY_CTRL0_TX_PATTERN_EN_LSB 21 +#define PHY_CTRL0_TX_PATTERN_EN_MASK 0x00200000 +#define PHY_CTRL0_TX_PATTERN_EN_GET(x) (((x) & PHY_CTRL0_TX_PATTERN_EN_MASK) >> PHY_CTRL0_TX_PATTERN_EN_LSB) +#define PHY_CTRL0_TX_PATTERN_EN_SET(x) (((x) << PHY_CTRL0_TX_PATTERN_EN_LSB) & PHY_CTRL0_TX_PATTERN_EN_MASK) +#define PHY_CTRL0_TX_PATTERN_EN_RESET 0x0 // 0 +#define PHY_CTRL0_RX_PATTERN_EN_MSB 20 +#define PHY_CTRL0_RX_PATTERN_EN_LSB 20 +#define PHY_CTRL0_RX_PATTERN_EN_MASK 0x00100000 +#define PHY_CTRL0_RX_PATTERN_EN_GET(x) (((x) & PHY_CTRL0_RX_PATTERN_EN_MASK) >> PHY_CTRL0_RX_PATTERN_EN_LSB) +#define PHY_CTRL0_RX_PATTERN_EN_SET(x) (((x) << PHY_CTRL0_RX_PATTERN_EN_LSB) & PHY_CTRL0_RX_PATTERN_EN_MASK) +#define PHY_CTRL0_RX_PATTERN_EN_RESET 0x0 // 0 +#define PHY_CTRL0_TEST_SPEED_SELECT_MSB 19 +#define PHY_CTRL0_TEST_SPEED_SELECT_LSB 19 +#define PHY_CTRL0_TEST_SPEED_SELECT_MASK 0x00080000 +#define PHY_CTRL0_TEST_SPEED_SELECT_GET(x) (((x) & PHY_CTRL0_TEST_SPEED_SELECT_MASK) >> PHY_CTRL0_TEST_SPEED_SELECT_LSB) +#define PHY_CTRL0_TEST_SPEED_SELECT_SET(x) (((x) << PHY_CTRL0_TEST_SPEED_SELECT_LSB) & PHY_CTRL0_TEST_SPEED_SELECT_MASK) +#define PHY_CTRL0_TEST_SPEED_SELECT_RESET 0x0 // 0 +#define PHY_CTRL0_PLL_OVERIDE_MSB 18 +#define PHY_CTRL0_PLL_OVERIDE_LSB 18 +#define PHY_CTRL0_PLL_OVERIDE_MASK 0x00040000 +#define PHY_CTRL0_PLL_OVERIDE_GET(x) (((x) & PHY_CTRL0_PLL_OVERIDE_MASK) >> PHY_CTRL0_PLL_OVERIDE_LSB) +#define PHY_CTRL0_PLL_OVERIDE_SET(x) (((x) << PHY_CTRL0_PLL_OVERIDE_LSB) & PHY_CTRL0_PLL_OVERIDE_MASK) +#define PHY_CTRL0_PLL_OVERIDE_RESET 0x0 // 0 +#define PHY_CTRL0_PLL_MOD_MSB 17 +#define PHY_CTRL0_PLL_MOD_LSB 15 +#define PHY_CTRL0_PLL_MOD_MASK 0x00038000 +#define PHY_CTRL0_PLL_MOD_GET(x) (((x) & PHY_CTRL0_PLL_MOD_MASK) >> PHY_CTRL0_PLL_MOD_LSB) +#define PHY_CTRL0_PLL_MOD_SET(x) (((x) << PHY_CTRL0_PLL_MOD_LSB) & PHY_CTRL0_PLL_MOD_MASK) +#define PHY_CTRL0_PLL_MOD_RESET 0x0 // 0 +#define PHY_CTRL0_PLL_DIV_MSB 14 +#define PHY_CTRL0_PLL_DIV_LSB 6 +#define PHY_CTRL0_PLL_DIV_MASK 0x00007fc0 +#define PHY_CTRL0_PLL_DIV_GET(x) (((x) & PHY_CTRL0_PLL_DIV_MASK) >> PHY_CTRL0_PLL_DIV_LSB) +#define PHY_CTRL0_PLL_DIV_SET(x) (((x) << PHY_CTRL0_PLL_DIV_LSB) & PHY_CTRL0_PLL_DIV_MASK) +#define PHY_CTRL0_PLL_DIV_RESET 0x0 // 0 +#define PHY_CTRL0_PLL_RS_MSB 5 +#define PHY_CTRL0_PLL_RS_LSB 3 +#define PHY_CTRL0_PLL_RS_MASK 0x00000038 +#define PHY_CTRL0_PLL_RS_GET(x) (((x) & PHY_CTRL0_PLL_RS_MASK) >> PHY_CTRL0_PLL_RS_LSB) +#define PHY_CTRL0_PLL_RS_SET(x) (((x) << PHY_CTRL0_PLL_RS_LSB) & PHY_CTRL0_PLL_RS_MASK) +#define PHY_CTRL0_PLL_RS_RESET 0x2 // 2 +#define PHY_CTRL0_PLL_ICP_MSB 2 +#define PHY_CTRL0_PLL_ICP_LSB 0 +#define PHY_CTRL0_PLL_ICP_MASK 0x00000007 +#define PHY_CTRL0_PLL_ICP_GET(x) (((x) & PHY_CTRL0_PLL_ICP_MASK) >> PHY_CTRL0_PLL_ICP_LSB) +#define PHY_CTRL0_PLL_ICP_SET(x) (((x) << PHY_CTRL0_PLL_ICP_LSB) & PHY_CTRL0_PLL_ICP_MASK) +#define PHY_CTRL0_PLL_ICP_RESET 0x5 // 5 +#define PHY_CTRL0_ADDRESS 0x18116c80 +#define PHY_CTRL0_OFFSET 0x0000 +// SW modifiable bits +#define PHY_CTRL0_SW_MASK 0xffffffff +// bits defined at reset +#define PHY_CTRL0_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PHY_CTRL0_RESET 0x00000015 + +#define PHY_CTRL1_PLL_OBS_MODE_N_MSB 31 +#define PHY_CTRL1_PLL_OBS_MODE_N_LSB 31 +#define PHY_CTRL1_PLL_OBS_MODE_N_MASK 0x80000000 +#define PHY_CTRL1_PLL_OBS_MODE_N_GET(x) (((x) & PHY_CTRL1_PLL_OBS_MODE_N_MASK) >> PHY_CTRL1_PLL_OBS_MODE_N_LSB) +#define PHY_CTRL1_PLL_OBS_MODE_N_SET(x) (((x) << PHY_CTRL1_PLL_OBS_MODE_N_LSB) & PHY_CTRL1_PLL_OBS_MODE_N_MASK) +#define PHY_CTRL1_PLL_OBS_MODE_N_RESET 0x1 // 1 +#define PHY_CTRL1_DISABLE_CLK_GATING_MSB 27 +#define PHY_CTRL1_DISABLE_CLK_GATING_LSB 27 +#define PHY_CTRL1_DISABLE_CLK_GATING_MASK 0x08000000 +#define PHY_CTRL1_DISABLE_CLK_GATING_GET(x) (((x) & PHY_CTRL1_DISABLE_CLK_GATING_MASK) >> PHY_CTRL1_DISABLE_CLK_GATING_LSB) +#define PHY_CTRL1_DISABLE_CLK_GATING_SET(x) (((x) << PHY_CTRL1_DISABLE_CLK_GATING_LSB) & PHY_CTRL1_DISABLE_CLK_GATING_MASK) +#define PHY_CTRL1_DISABLE_CLK_GATING_RESET 0x0 // 0 +#define PHY_CTRL1_ENABLE_REFCLK_GATE_MSB 26 +#define PHY_CTRL1_ENABLE_REFCLK_GATE_LSB 26 +#define PHY_CTRL1_ENABLE_REFCLK_GATE_MASK 0x04000000 +#define PHY_CTRL1_ENABLE_REFCLK_GATE_GET(x) (((x) & PHY_CTRL1_ENABLE_REFCLK_GATE_MASK) >> PHY_CTRL1_ENABLE_REFCLK_GATE_LSB) +#define PHY_CTRL1_ENABLE_REFCLK_GATE_SET(x) (((x) << PHY_CTRL1_ENABLE_REFCLK_GATE_LSB) & PHY_CTRL1_ENABLE_REFCLK_GATE_MASK) +#define PHY_CTRL1_ENABLE_REFCLK_GATE_RESET 0x1 // 1 +#define PHY_CTRL1_CLKOBS_SEL_MSB 25 +#define PHY_CTRL1_CLKOBS_SEL_LSB 23 +#define PHY_CTRL1_CLKOBS_SEL_MASK 0x03800000 +#define PHY_CTRL1_CLKOBS_SEL_GET(x) (((x) & PHY_CTRL1_CLKOBS_SEL_MASK) >> PHY_CTRL1_CLKOBS_SEL_LSB) +#define PHY_CTRL1_CLKOBS_SEL_SET(x) (((x) << PHY_CTRL1_CLKOBS_SEL_LSB) & PHY_CTRL1_CLKOBS_SEL_MASK) +#define PHY_CTRL1_CLKOBS_SEL_RESET 0x0 // 0 +#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MSB 22 +#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB 21 +#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK 0x00600000 +#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_GET(x) (((x) & PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK) >> PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB) +#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_SET(x) (((x) << PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB) & PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK) +#define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_RESET 0x3 // 3 +#define PHY_CTRL1_USE_PLL_LOCKDETECT_MSB 20 +#define PHY_CTRL1_USE_PLL_LOCKDETECT_LSB 20 +#define PHY_CTRL1_USE_PLL_LOCKDETECT_MASK 0x00100000 +#define PHY_CTRL1_USE_PLL_LOCKDETECT_GET(x) (((x) & PHY_CTRL1_USE_PLL_LOCKDETECT_MASK) >> PHY_CTRL1_USE_PLL_LOCKDETECT_LSB) +#define PHY_CTRL1_USE_PLL_LOCKDETECT_SET(x) (((x) << PHY_CTRL1_USE_PLL_LOCKDETECT_LSB) & PHY_CTRL1_USE_PLL_LOCKDETECT_MASK) +#define PHY_CTRL1_USE_PLL_LOCKDETECT_RESET 0x0 // 0 +#define PHY_CTRL1_TX_PATTERN_SEL_MSB 19 +#define PHY_CTRL1_TX_PATTERN_SEL_LSB 18 +#define PHY_CTRL1_TX_PATTERN_SEL_MASK 0x000c0000 +#define PHY_CTRL1_TX_PATTERN_SEL_GET(x) (((x) & PHY_CTRL1_TX_PATTERN_SEL_MASK) >> PHY_CTRL1_TX_PATTERN_SEL_LSB) +#define PHY_CTRL1_TX_PATTERN_SEL_SET(x) (((x) << PHY_CTRL1_TX_PATTERN_SEL_LSB) & PHY_CTRL1_TX_PATTERN_SEL_MASK) +#define PHY_CTRL1_TX_PATTERN_SEL_RESET 0x0 // 0 +#define PHY_CTRL1_FORCE_SUSPEND_MSB 13 +#define PHY_CTRL1_FORCE_SUSPEND_LSB 13 +#define PHY_CTRL1_FORCE_SUSPEND_MASK 0x00002000 +#define PHY_CTRL1_FORCE_SUSPEND_GET(x) (((x) & PHY_CTRL1_FORCE_SUSPEND_MASK) >> PHY_CTRL1_FORCE_SUSPEND_LSB) +#define PHY_CTRL1_FORCE_SUSPEND_SET(x) (((x) << PHY_CTRL1_FORCE_SUSPEND_LSB) & PHY_CTRL1_FORCE_SUSPEND_MASK) +#define PHY_CTRL1_FORCE_SUSPEND_RESET 0x0 // 0 +#define PHY_CTRL1_NO_PLL_PWD_MSB 12 +#define PHY_CTRL1_NO_PLL_PWD_LSB 12 +#define PHY_CTRL1_NO_PLL_PWD_MASK 0x00001000 +#define PHY_CTRL1_NO_PLL_PWD_GET(x) (((x) & PHY_CTRL1_NO_PLL_PWD_MASK) >> PHY_CTRL1_NO_PLL_PWD_LSB) +#define PHY_CTRL1_NO_PLL_PWD_SET(x) (((x) << PHY_CTRL1_NO_PLL_PWD_LSB) & PHY_CTRL1_NO_PLL_PWD_MASK) +#define PHY_CTRL1_NO_PLL_PWD_RESET 0x0 // 0 +#define PHY_CTRL1_RX_RSVD_MSB 11 +#define PHY_CTRL1_RX_RSVD_LSB 9 +#define PHY_CTRL1_RX_RSVD_MASK 0x00000e00 +#define PHY_CTRL1_RX_RSVD_GET(x) (((x) & PHY_CTRL1_RX_RSVD_MASK) >> PHY_CTRL1_RX_RSVD_LSB) +#define PHY_CTRL1_RX_RSVD_SET(x) (((x) << PHY_CTRL1_RX_RSVD_LSB) & PHY_CTRL1_RX_RSVD_MASK) +#define PHY_CTRL1_RX_RSVD_RESET 0x0 // 0 +#define PHY_CTRL1_RX_SELVREF0P25_MSB 8 +#define PHY_CTRL1_RX_SELVREF0P25_LSB 8 +#define PHY_CTRL1_RX_SELVREF0P25_MASK 0x00000100 +#define PHY_CTRL1_RX_SELVREF0P25_GET(x) (((x) & PHY_CTRL1_RX_SELVREF0P25_MASK) >> PHY_CTRL1_RX_SELVREF0P25_LSB) +#define PHY_CTRL1_RX_SELVREF0P25_SET(x) (((x) << PHY_CTRL1_RX_SELVREF0P25_LSB) & PHY_CTRL1_RX_SELVREF0P25_MASK) +#define PHY_CTRL1_RX_SELVREF0P25_RESET 0x0 // 0 +#define PHY_CTRL1_RX_SELVREF0P6_MSB 7 +#define PHY_CTRL1_RX_SELVREF0P6_LSB 7 +#define PHY_CTRL1_RX_SELVREF0P6_MASK 0x00000080 +#define PHY_CTRL1_RX_SELVREF0P6_GET(x) (((x) & PHY_CTRL1_RX_SELVREF0P6_MASK) >> PHY_CTRL1_RX_SELVREF0P6_LSB) +#define PHY_CTRL1_RX_SELVREF0P6_SET(x) (((x) << PHY_CTRL1_RX_SELVREF0P6_LSB) & PHY_CTRL1_RX_SELVREF0P6_MASK) +#define PHY_CTRL1_RX_SELVREF0P6_RESET 0x1 // 1 +#define PHY_CTRL1_RX_SELIR_100M_MSB 6 +#define PHY_CTRL1_RX_SELIR_100M_LSB 5 +#define PHY_CTRL1_RX_SELIR_100M_MASK 0x00000060 +#define PHY_CTRL1_RX_SELIR_100M_GET(x) (((x) & PHY_CTRL1_RX_SELIR_100M_MASK) >> PHY_CTRL1_RX_SELIR_100M_LSB) +#define PHY_CTRL1_RX_SELIR_100M_SET(x) (((x) << PHY_CTRL1_RX_SELIR_100M_LSB) & PHY_CTRL1_RX_SELIR_100M_MASK) +#define PHY_CTRL1_RX_SELIR_100M_RESET 0x0 // 0 +#define PHY_CTRL1_RX_LOWR_PDET_MSB 4 +#define PHY_CTRL1_RX_LOWR_PDET_LSB 4 +#define PHY_CTRL1_RX_LOWR_PDET_MASK 0x00000010 +#define PHY_CTRL1_RX_LOWR_PDET_GET(x) (((x) & PHY_CTRL1_RX_LOWR_PDET_MASK) >> PHY_CTRL1_RX_LOWR_PDET_LSB) +#define PHY_CTRL1_RX_LOWR_PDET_SET(x) (((x) << PHY_CTRL1_RX_LOWR_PDET_LSB) & PHY_CTRL1_RX_LOWR_PDET_MASK) +#define PHY_CTRL1_RX_LOWR_PDET_RESET 0x1 // 1 +#define PHY_CTRL1_RX_BYPASSEQ_MSB 3 +#define PHY_CTRL1_RX_BYPASSEQ_LSB 3 +#define PHY_CTRL1_RX_BYPASSEQ_MASK 0x00000008 +#define PHY_CTRL1_RX_BYPASSEQ_GET(x) (((x) & PHY_CTRL1_RX_BYPASSEQ_MASK) >> PHY_CTRL1_RX_BYPASSEQ_LSB) +#define PHY_CTRL1_RX_BYPASSEQ_SET(x) (((x) << PHY_CTRL1_RX_BYPASSEQ_LSB) & PHY_CTRL1_RX_BYPASSEQ_MASK) +#define PHY_CTRL1_RX_BYPASSEQ_RESET 0x0 // 0 +#define PHY_CTRL1_RX_FORCERXON_MSB 2 +#define PHY_CTRL1_RX_FORCERXON_LSB 2 +#define PHY_CTRL1_RX_FORCERXON_MASK 0x00000004 +#define PHY_CTRL1_RX_FORCERXON_GET(x) (((x) & PHY_CTRL1_RX_FORCERXON_MASK) >> PHY_CTRL1_RX_FORCERXON_LSB) +#define PHY_CTRL1_RX_FORCERXON_SET(x) (((x) << PHY_CTRL1_RX_FORCERXON_LSB) & PHY_CTRL1_RX_FORCERXON_MASK) +#define PHY_CTRL1_RX_FORCERXON_RESET 0x1 // 1 +#define PHY_CTRL1_RX_FILBW_SEL_MSB 1 +#define PHY_CTRL1_RX_FILBW_SEL_LSB 0 +#define PHY_CTRL1_RX_FILBW_SEL_MASK 0x00000003 +#define PHY_CTRL1_RX_FILBW_SEL_GET(x) (((x) & PHY_CTRL1_RX_FILBW_SEL_MASK) >> PHY_CTRL1_RX_FILBW_SEL_LSB) +#define PHY_CTRL1_RX_FILBW_SEL_SET(x) (((x) << PHY_CTRL1_RX_FILBW_SEL_LSB) & PHY_CTRL1_RX_FILBW_SEL_MASK) +#define PHY_CTRL1_RX_FILBW_SEL_RESET 0x1 // 1 +#define PHY_CTRL1_ADDRESS 0x18116c84 +#define PHY_CTRL1_OFFSET 0x0004 +// SW modifiable bits +#define PHY_CTRL1_SW_MASK 0x8ffc3fff +// bits defined at reset +#define PHY_CTRL1_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PHY_CTRL1_RESET 0x84600095 + +#define PHY_CTRL2_PWD_EXTBIAS_MSB 31 +#define PHY_CTRL2_PWD_EXTBIAS_LSB 31 +#define PHY_CTRL2_PWD_EXTBIAS_MASK 0x80000000 +#define PHY_CTRL2_PWD_EXTBIAS_GET(x) (((x) & PHY_CTRL2_PWD_EXTBIAS_MASK) >> PHY_CTRL2_PWD_EXTBIAS_LSB) +#define PHY_CTRL2_PWD_EXTBIAS_SET(x) (((x) << PHY_CTRL2_PWD_EXTBIAS_LSB) & PHY_CTRL2_PWD_EXTBIAS_MASK) +#define PHY_CTRL2_PWD_EXTBIAS_RESET 0x0 // 0 +#define PHY_CTRL2_TX_RSVD_MSB 30 +#define PHY_CTRL2_TX_RSVD_LSB 27 +#define PHY_CTRL2_TX_RSVD_MASK 0x78000000 +#define PHY_CTRL2_TX_RSVD_GET(x) (((x) & PHY_CTRL2_TX_RSVD_MASK) >> PHY_CTRL2_TX_RSVD_LSB) +#define PHY_CTRL2_TX_RSVD_SET(x) (((x) << PHY_CTRL2_TX_RSVD_LSB) & PHY_CTRL2_TX_RSVD_MASK) +#define PHY_CTRL2_TX_RSVD_RESET 0x0 // 0 +#define PHY_CTRL2_TX_LCKDET_OVR_MSB 26 +#define PHY_CTRL2_TX_LCKDET_OVR_LSB 26 +#define PHY_CTRL2_TX_LCKDET_OVR_MASK 0x04000000 +#define PHY_CTRL2_TX_LCKDET_OVR_GET(x) (((x) & PHY_CTRL2_TX_LCKDET_OVR_MASK) >> PHY_CTRL2_TX_LCKDET_OVR_LSB) +#define PHY_CTRL2_TX_LCKDET_OVR_SET(x) (((x) << PHY_CTRL2_TX_LCKDET_OVR_LSB) & PHY_CTRL2_TX_LCKDET_OVR_MASK) +#define PHY_CTRL2_TX_LCKDET_OVR_RESET 0x0 // 0 +#define PHY_CTRL2_TX_MAN_CAL_MSB 25 +#define PHY_CTRL2_TX_MAN_CAL_LSB 22 +#define PHY_CTRL2_TX_MAN_CAL_MASK 0x03c00000 +#define PHY_CTRL2_TX_MAN_CAL_GET(x) (((x) & PHY_CTRL2_TX_MAN_CAL_MASK) >> PHY_CTRL2_TX_MAN_CAL_LSB) +#define PHY_CTRL2_TX_MAN_CAL_SET(x) (((x) << PHY_CTRL2_TX_MAN_CAL_LSB) & PHY_CTRL2_TX_MAN_CAL_MASK) +#define PHY_CTRL2_TX_MAN_CAL_RESET 0x3 // 3 +#define PHY_CTRL2_TX_CAL_SEL_MSB 21 +#define PHY_CTRL2_TX_CAL_SEL_LSB 21 +#define PHY_CTRL2_TX_CAL_SEL_MASK 0x00200000 +#define PHY_CTRL2_TX_CAL_SEL_GET(x) (((x) & PHY_CTRL2_TX_CAL_SEL_MASK) >> PHY_CTRL2_TX_CAL_SEL_LSB) +#define PHY_CTRL2_TX_CAL_SEL_SET(x) (((x) << PHY_CTRL2_TX_CAL_SEL_LSB) & PHY_CTRL2_TX_CAL_SEL_MASK) +#define PHY_CTRL2_TX_CAL_SEL_RESET 0x1 // 1 +#define PHY_CTRL2_TX_CAL_EN_MSB 20 +#define PHY_CTRL2_TX_CAL_EN_LSB 20 +#define PHY_CTRL2_TX_CAL_EN_MASK 0x00100000 +#define PHY_CTRL2_TX_CAL_EN_GET(x) (((x) & PHY_CTRL2_TX_CAL_EN_MASK) >> PHY_CTRL2_TX_CAL_EN_LSB) +#define PHY_CTRL2_TX_CAL_EN_SET(x) (((x) << PHY_CTRL2_TX_CAL_EN_LSB) & PHY_CTRL2_TX_CAL_EN_MASK) +#define PHY_CTRL2_TX_CAL_EN_RESET 0x1 // 1 +#define PHY_CTRL2_PWD_ISP_MSB 13 +#define PHY_CTRL2_PWD_ISP_LSB 8 +#define PHY_CTRL2_PWD_ISP_MASK 0x00003f00 +#define PHY_CTRL2_PWD_ISP_GET(x) (((x) & PHY_CTRL2_PWD_ISP_MASK) >> PHY_CTRL2_PWD_ISP_LSB) +#define PHY_CTRL2_PWD_ISP_SET(x) (((x) << PHY_CTRL2_PWD_ISP_LSB) & PHY_CTRL2_PWD_ISP_MASK) +#define PHY_CTRL2_PWD_ISP_RESET 0x1b // 27 +#define PHY_CTRL2_PWD_IPLL_MSB 7 +#define PHY_CTRL2_PWD_IPLL_LSB 2 +#define PHY_CTRL2_PWD_IPLL_MASK 0x000000fc +#define PHY_CTRL2_PWD_IPLL_GET(x) (((x) & PHY_CTRL2_PWD_IPLL_MASK) >> PHY_CTRL2_PWD_IPLL_LSB) +#define PHY_CTRL2_PWD_IPLL_SET(x) (((x) << PHY_CTRL2_PWD_IPLL_LSB) & PHY_CTRL2_PWD_IPLL_MASK) +#define PHY_CTRL2_PWD_IPLL_RESET 0x1b // 27 +#define PHY_CTRL2_HSRXPHASE_PS_EN_MSB 1 +#define PHY_CTRL2_HSRXPHASE_PS_EN_LSB 1 +#define PHY_CTRL2_HSRXPHASE_PS_EN_MASK 0x00000002 +#define PHY_CTRL2_HSRXPHASE_PS_EN_GET(x) (((x) & PHY_CTRL2_HSRXPHASE_PS_EN_MASK) >> PHY_CTRL2_HSRXPHASE_PS_EN_LSB) +#define PHY_CTRL2_HSRXPHASE_PS_EN_SET(x) (((x) << PHY_CTRL2_HSRXPHASE_PS_EN_LSB) & PHY_CTRL2_HSRXPHASE_PS_EN_MASK) +#define PHY_CTRL2_HSRXPHASE_PS_EN_RESET 0x0 // 0 +#define PHY_CTRL2_HSTXBIAS_PS_EN_MSB 0 +#define PHY_CTRL2_HSTXBIAS_PS_EN_LSB 0 +#define PHY_CTRL2_HSTXBIAS_PS_EN_MASK 0x00000001 +#define PHY_CTRL2_HSTXBIAS_PS_EN_GET(x) (((x) & PHY_CTRL2_HSTXBIAS_PS_EN_MASK) >> PHY_CTRL2_HSTXBIAS_PS_EN_LSB) +#define PHY_CTRL2_HSTXBIAS_PS_EN_SET(x) (((x) << PHY_CTRL2_HSTXBIAS_PS_EN_LSB) & PHY_CTRL2_HSTXBIAS_PS_EN_MASK) +#define PHY_CTRL2_HSTXBIAS_PS_EN_RESET 0x0 // 0 +#define PHY_CTRL2_ADDRESS 0x18116c88 +#define PHY_CTRL2_OFFSET 0x0008 +// SW modifiable bits +#define PHY_CTRL2_SW_MASK 0xfff03fff +// bits defined at reset +#define PHY_CTRL2_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PHY_CTRL2_RESET 0x00f01b6c + +#define PHY_CTRL3_SPARE_BITS_MSB 31 +#define PHY_CTRL3_SPARE_BITS_LSB 27 +#define PHY_CTRL3_SPARE_BITS_MASK 0xf8000000 +#define PHY_CTRL3_SPARE_BITS_GET(x) (((x) & PHY_CTRL3_SPARE_BITS_MASK) >> PHY_CTRL3_SPARE_BITS_LSB) +#define PHY_CTRL3_SPARE_BITS_SET(x) (((x) << PHY_CTRL3_SPARE_BITS_LSB) & PHY_CTRL3_SPARE_BITS_MASK) +#define PHY_CTRL3_SPARE_BITS_RESET 0x0 // 0 +#define PHY_CTRL3_SUS_RES_FIX_DIS_MSB 26 +#define PHY_CTRL3_SUS_RES_FIX_DIS_LSB 26 +#define PHY_CTRL3_SUS_RES_FIX_DIS_MASK 0x04000000 +#define PHY_CTRL3_SUS_RES_FIX_DIS_GET(x) (((x) & PHY_CTRL3_SUS_RES_FIX_DIS_MASK) >> PHY_CTRL3_SUS_RES_FIX_DIS_LSB) +#define PHY_CTRL3_SUS_RES_FIX_DIS_SET(x) (((x) << PHY_CTRL3_SUS_RES_FIX_DIS_LSB) & PHY_CTRL3_SUS_RES_FIX_DIS_MASK) +#define PHY_CTRL3_SUS_RES_FIX_DIS_RESET 0x0 // 0 +#define PHY_CTRL3_TX_STARTCAL_MSB 25 +#define PHY_CTRL3_TX_STARTCAL_LSB 25 +#define PHY_CTRL3_TX_STARTCAL_MASK 0x02000000 +#define PHY_CTRL3_TX_STARTCAL_GET(x) (((x) & PHY_CTRL3_TX_STARTCAL_MASK) >> PHY_CTRL3_TX_STARTCAL_LSB) +#define PHY_CTRL3_TX_STARTCAL_SET(x) (((x) << PHY_CTRL3_TX_STARTCAL_LSB) & PHY_CTRL3_TX_STARTCAL_MASK) +#define PHY_CTRL3_TX_STARTCAL_RESET 0x0 // 0 +#define PHY_CTRL3_TX_SELTEST_MSB 24 +#define PHY_CTRL3_TX_SELTEST_LSB 22 +#define PHY_CTRL3_TX_SELTEST_MASK 0x01c00000 +#define PHY_CTRL3_TX_SELTEST_GET(x) (((x) & PHY_CTRL3_TX_SELTEST_MASK) >> PHY_CTRL3_TX_SELTEST_LSB) +#define PHY_CTRL3_TX_SELTEST_SET(x) (((x) << PHY_CTRL3_TX_SELTEST_LSB) & PHY_CTRL3_TX_SELTEST_MASK) +#define PHY_CTRL3_TX_SELTEST_RESET 0x0 // 0 +#define PHY_CTRL3_TX_DISABLE_SHORT_DET_MSB 21 +#define PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB 21 +#define PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK 0x00200000 +#define PHY_CTRL3_TX_DISABLE_SHORT_DET_GET(x) (((x) & PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK) >> PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB) +#define PHY_CTRL3_TX_DISABLE_SHORT_DET_SET(x) (((x) << PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB) & PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK) +#define PHY_CTRL3_TX_DISABLE_SHORT_DET_RESET 0x0 // 0 +#define PHY_CTRL3_PWD_ITX_MSB 18 +#define PHY_CTRL3_PWD_ITX_LSB 0 +#define PHY_CTRL3_PWD_ITX_MASK 0x0007ffff +#define PHY_CTRL3_PWD_ITX_GET(x) (((x) & PHY_CTRL3_PWD_ITX_MASK) >> PHY_CTRL3_PWD_ITX_LSB) +#define PHY_CTRL3_PWD_ITX_SET(x) (((x) << PHY_CTRL3_PWD_ITX_LSB) & PHY_CTRL3_PWD_ITX_MASK) +#define PHY_CTRL3_PWD_ITX_RESET 0x14765 // 83813 +#define PHY_CTRL3_ADDRESS 0x18116c8c +#define PHY_CTRL3_OFFSET 0x000c +// SW modifiable bits +#define PHY_CTRL3_SW_MASK 0xffe7ffff +// bits defined at reset +#define PHY_CTRL3_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PHY_CTRL3_RESET 0x00014765 + +#define PHY_CTRL4_PPRBS_ERR_CNT_MSB 31 +#define PHY_CTRL4_PPRBS_ERR_CNT_LSB 24 +#define PHY_CTRL4_PPRBS_ERR_CNT_MASK 0xff000000 +#define PHY_CTRL4_PPRBS_ERR_CNT_GET(x) (((x) & PHY_CTRL4_PPRBS_ERR_CNT_MASK) >> PHY_CTRL4_PPRBS_ERR_CNT_LSB) +#define PHY_CTRL4_PPRBS_ERR_CNT_SET(x) (((x) << PHY_CTRL4_PPRBS_ERR_CNT_LSB) & PHY_CTRL4_PPRBS_ERR_CNT_MASK) +#define PHY_CTRL4_PPRBS_ERR_CNT_RESET 0x0 // 0 +#define PHY_CTRL4_LS_PRBS_EN_MSB 21 +#define PHY_CTRL4_LS_PRBS_EN_LSB 21 +#define PHY_CTRL4_LS_PRBS_EN_MASK 0x00200000 +#define PHY_CTRL4_LS_PRBS_EN_GET(x) (((x) & PHY_CTRL4_LS_PRBS_EN_MASK) >> PHY_CTRL4_LS_PRBS_EN_LSB) +#define PHY_CTRL4_LS_PRBS_EN_SET(x) (((x) << PHY_CTRL4_LS_PRBS_EN_LSB) & PHY_CTRL4_LS_PRBS_EN_MASK) +#define PHY_CTRL4_LS_PRBS_EN_RESET 0x0 // 0 +#define PHY_CTRL4_PPRBS_TERM_SEL_MSB 20 +#define PHY_CTRL4_PPRBS_TERM_SEL_LSB 20 +#define PHY_CTRL4_PPRBS_TERM_SEL_MASK 0x00100000 +#define PHY_CTRL4_PPRBS_TERM_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_TERM_SEL_MASK) >> PHY_CTRL4_PPRBS_TERM_SEL_LSB) +#define PHY_CTRL4_PPRBS_TERM_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_TERM_SEL_LSB) & PHY_CTRL4_PPRBS_TERM_SEL_MASK) +#define PHY_CTRL4_PPRBS_TERM_SEL_RESET 0x0 // 0 +#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_MSB 19 +#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB 19 +#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK 0x00080000 +#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK) >> PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB) +#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB) & PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK) +#define PHY_CTRL4_PPRBS_DIG_LPBK_EN_RESET 0x0 // 0 +#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_MSB 18 +#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB 18 +#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK 0x00040000 +#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK) >> PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB) +#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB) & PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK) +#define PHY_CTRL4_PPRBS_ANA_LPBK_EN_RESET 0x0 // 0 +#define PHY_CTRL4_PPRBS_PAT_SEL_MSB 17 +#define PHY_CTRL4_PPRBS_PAT_SEL_LSB 16 +#define PHY_CTRL4_PPRBS_PAT_SEL_MASK 0x00030000 +#define PHY_CTRL4_PPRBS_PAT_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_PAT_SEL_MASK) >> PHY_CTRL4_PPRBS_PAT_SEL_LSB) +#define PHY_CTRL4_PPRBS_PAT_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_PAT_SEL_LSB) & PHY_CTRL4_PPRBS_PAT_SEL_MASK) +#define PHY_CTRL4_PPRBS_PAT_SEL_RESET 0x0 // 0 +#define PHY_CTRL4_PPRBS_TX_EN_MSB 15 +#define PHY_CTRL4_PPRBS_TX_EN_LSB 15 +#define PHY_CTRL4_PPRBS_TX_EN_MASK 0x00008000 +#define PHY_CTRL4_PPRBS_TX_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_TX_EN_MASK) >> PHY_CTRL4_PPRBS_TX_EN_LSB) +#define PHY_CTRL4_PPRBS_TX_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_TX_EN_LSB) & PHY_CTRL4_PPRBS_TX_EN_MASK) +#define PHY_CTRL4_PPRBS_TX_EN_RESET 0x0 // 0 +#define PHY_CTRL4_PPRBS_RX_EN_MSB 14 +#define PHY_CTRL4_PPRBS_RX_EN_LSB 14 +#define PHY_CTRL4_PPRBS_RX_EN_MASK 0x00004000 +#define PHY_CTRL4_PPRBS_RX_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_RX_EN_MASK) >> PHY_CTRL4_PPRBS_RX_EN_LSB) +#define PHY_CTRL4_PPRBS_RX_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_RX_EN_LSB) & PHY_CTRL4_PPRBS_RX_EN_MASK) +#define PHY_CTRL4_PPRBS_RX_EN_RESET 0x0 // 0 +#define PHY_CTRL4_PPRBS_SPEED_SEL_MSB 13 +#define PHY_CTRL4_PPRBS_SPEED_SEL_LSB 13 +#define PHY_CTRL4_PPRBS_SPEED_SEL_MASK 0x00002000 +#define PHY_CTRL4_PPRBS_SPEED_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_SPEED_SEL_MASK) >> PHY_CTRL4_PPRBS_SPEED_SEL_LSB) +#define PHY_CTRL4_PPRBS_SPEED_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_SPEED_SEL_LSB) & PHY_CTRL4_PPRBS_SPEED_SEL_MASK) +#define PHY_CTRL4_PPRBS_SPEED_SEL_RESET 0x0 // 0 +#define PHY_CTRL4_PPRBS_RX_INV_MSB 12 +#define PHY_CTRL4_PPRBS_RX_INV_LSB 12 +#define PHY_CTRL4_PPRBS_RX_INV_MASK 0x00001000 +#define PHY_CTRL4_PPRBS_RX_INV_GET(x) (((x) & PHY_CTRL4_PPRBS_RX_INV_MASK) >> PHY_CTRL4_PPRBS_RX_INV_LSB) +#define PHY_CTRL4_PPRBS_RX_INV_SET(x) (((x) << PHY_CTRL4_PPRBS_RX_INV_LSB) & PHY_CTRL4_PPRBS_RX_INV_MASK) +#define PHY_CTRL4_PPRBS_RX_INV_RESET 0x0 // 0 +#define PHY_CTRL4_PWD_IRX_MSB 11 +#define PHY_CTRL4_PWD_IRX_LSB 0 +#define PHY_CTRL4_PWD_IRX_MASK 0x00000fff +#define PHY_CTRL4_PWD_IRX_GET(x) (((x) & PHY_CTRL4_PWD_IRX_MASK) >> PHY_CTRL4_PWD_IRX_LSB) +#define PHY_CTRL4_PWD_IRX_SET(x) (((x) << PHY_CTRL4_PWD_IRX_LSB) & PHY_CTRL4_PWD_IRX_MASK) +#define PHY_CTRL4_PWD_IRX_RESET 0x6dd // 1757 +#define PHY_CTRL4_ADDRESS 0x18116c90 +#define PHY_CTRL4_OFFSET 0x0010 +// SW modifiable bits +#define PHY_CTRL4_SW_MASK 0xff3fffff +// bits defined at reset +#define PHY_CTRL4_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PHY_CTRL4_RESET 0x000006dd + +#define PHY_CTRL5_SPARE_BITS_MSB 31 +#define PHY_CTRL5_SPARE_BITS_LSB 30 +#define PHY_CTRL5_SPARE_BITS_MASK 0xc0000000 +#define PHY_CTRL5_SPARE_BITS_GET(x) (((x) & PHY_CTRL5_SPARE_BITS_MASK) >> PHY_CTRL5_SPARE_BITS_LSB) +#define PHY_CTRL5_SPARE_BITS_SET(x) (((x) << PHY_CTRL5_SPARE_BITS_LSB) & PHY_CTRL5_SPARE_BITS_MASK) +#define PHY_CTRL5_SPARE_BITS_RESET 0x0 // 0 +#define PHY_CTRL5_HOST_RES_FIX_EN_MSB 29 +#define PHY_CTRL5_HOST_RES_FIX_EN_LSB 29 +#define PHY_CTRL5_HOST_RES_FIX_EN_MASK 0x20000000 +#define PHY_CTRL5_HOST_RES_FIX_EN_GET(x) (((x) & PHY_CTRL5_HOST_RES_FIX_EN_MASK) >> PHY_CTRL5_HOST_RES_FIX_EN_LSB) +#define PHY_CTRL5_HOST_RES_FIX_EN_SET(x) (((x) << PHY_CTRL5_HOST_RES_FIX_EN_LSB) & PHY_CTRL5_HOST_RES_FIX_EN_MASK) +#define PHY_CTRL5_HOST_RES_FIX_EN_RESET 0x1 // 1 +#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MSB 28 +#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB 26 +#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK 0x1c000000 +#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK) >> PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB) +#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB) & PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK) +#define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_RESET 0x6 // 6 +#define PHY_CTRL5_HOST_DISCON_DETECT_ON_MSB 25 +#define PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB 25 +#define PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK 0x02000000 +#define PHY_CTRL5_HOST_DISCON_DETECT_ON_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK) >> PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB) +#define PHY_CTRL5_HOST_DISCON_DETECT_ON_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB) & PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK) +#define PHY_CTRL5_HOST_DISCON_DETECT_ON_RESET 0x1 // 1 +#define PHY_CTRL5_HOST_DISCON_FIX_ON_MSB 24 +#define PHY_CTRL5_HOST_DISCON_FIX_ON_LSB 24 +#define PHY_CTRL5_HOST_DISCON_FIX_ON_MASK 0x01000000 +#define PHY_CTRL5_HOST_DISCON_FIX_ON_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_FIX_ON_MASK) >> PHY_CTRL5_HOST_DISCON_FIX_ON_LSB) +#define PHY_CTRL5_HOST_DISCON_FIX_ON_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_FIX_ON_LSB) & PHY_CTRL5_HOST_DISCON_FIX_ON_MASK) +#define PHY_CTRL5_HOST_DISCON_FIX_ON_RESET 0x1 // 1 +#define PHY_CTRL5_DM_PULLDOWN_MSB 23 +#define PHY_CTRL5_DM_PULLDOWN_LSB 23 +#define PHY_CTRL5_DM_PULLDOWN_MASK 0x00800000 +#define PHY_CTRL5_DM_PULLDOWN_GET(x) (((x) & PHY_CTRL5_DM_PULLDOWN_MASK) >> PHY_CTRL5_DM_PULLDOWN_LSB) +#define PHY_CTRL5_DM_PULLDOWN_SET(x) (((x) << PHY_CTRL5_DM_PULLDOWN_LSB) & PHY_CTRL5_DM_PULLDOWN_MASK) +#define PHY_CTRL5_DM_PULLDOWN_RESET 0x0 // 0 +#define PHY_CTRL5_DP_PULLDOWN_MSB 22 +#define PHY_CTRL5_DP_PULLDOWN_LSB 22 +#define PHY_CTRL5_DP_PULLDOWN_MASK 0x00400000 +#define PHY_CTRL5_DP_PULLDOWN_GET(x) (((x) & PHY_CTRL5_DP_PULLDOWN_MASK) >> PHY_CTRL5_DP_PULLDOWN_LSB) +#define PHY_CTRL5_DP_PULLDOWN_SET(x) (((x) << PHY_CTRL5_DP_PULLDOWN_LSB) & PHY_CTRL5_DP_PULLDOWN_MASK) +#define PHY_CTRL5_DP_PULLDOWN_RESET 0x0 // 0 +#define PHY_CTRL5_SUSPEND_N_MSB 21 +#define PHY_CTRL5_SUSPEND_N_LSB 21 +#define PHY_CTRL5_SUSPEND_N_MASK 0x00200000 +#define PHY_CTRL5_SUSPEND_N_GET(x) (((x) & PHY_CTRL5_SUSPEND_N_MASK) >> PHY_CTRL5_SUSPEND_N_LSB) +#define PHY_CTRL5_SUSPEND_N_SET(x) (((x) << PHY_CTRL5_SUSPEND_N_LSB) & PHY_CTRL5_SUSPEND_N_MASK) +#define PHY_CTRL5_SUSPEND_N_RESET 0x1 // 1 +#define PHY_CTRL5_TERM_SEL_MSB 20 +#define PHY_CTRL5_TERM_SEL_LSB 20 +#define PHY_CTRL5_TERM_SEL_MASK 0x00100000 +#define PHY_CTRL5_TERM_SEL_GET(x) (((x) & PHY_CTRL5_TERM_SEL_MASK) >> PHY_CTRL5_TERM_SEL_LSB) +#define PHY_CTRL5_TERM_SEL_SET(x) (((x) << PHY_CTRL5_TERM_SEL_LSB) & PHY_CTRL5_TERM_SEL_MASK) +#define PHY_CTRL5_TERM_SEL_RESET 0x0 // 0 +#define PHY_CTRL5_XCVR_SEL_MSB 19 +#define PHY_CTRL5_XCVR_SEL_LSB 18 +#define PHY_CTRL5_XCVR_SEL_MASK 0x000c0000 +#define PHY_CTRL5_XCVR_SEL_GET(x) (((x) & PHY_CTRL5_XCVR_SEL_MASK) >> PHY_CTRL5_XCVR_SEL_LSB) +#define PHY_CTRL5_XCVR_SEL_SET(x) (((x) << PHY_CTRL5_XCVR_SEL_LSB) & PHY_CTRL5_XCVR_SEL_MASK) +#define PHY_CTRL5_XCVR_SEL_RESET 0x0 // 0 +#define PHY_CTRL5_TEST_JK_OVERRIDE_MSB 17 +#define PHY_CTRL5_TEST_JK_OVERRIDE_LSB 17 +#define PHY_CTRL5_TEST_JK_OVERRIDE_MASK 0x00020000 +#define PHY_CTRL5_TEST_JK_OVERRIDE_GET(x) (((x) & PHY_CTRL5_TEST_JK_OVERRIDE_MASK) >> PHY_CTRL5_TEST_JK_OVERRIDE_LSB) +#define PHY_CTRL5_TEST_JK_OVERRIDE_SET(x) (((x) << PHY_CTRL5_TEST_JK_OVERRIDE_LSB) & PHY_CTRL5_TEST_JK_OVERRIDE_MASK) +#define PHY_CTRL5_TEST_JK_OVERRIDE_RESET 0x0 // 0 +#define PHY_CTRL5_FORCE_TEST_SE0_NAK_MSB 16 +#define PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB 16 +#define PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK 0x00010000 +#define PHY_CTRL5_FORCE_TEST_SE0_NAK_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK) >> PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB) +#define PHY_CTRL5_FORCE_TEST_SE0_NAK_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB) & PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK) +#define PHY_CTRL5_FORCE_TEST_SE0_NAK_RESET 0x0 // 0 +#define PHY_CTRL5_FORCE_TEST_K_MSB 15 +#define PHY_CTRL5_FORCE_TEST_K_LSB 15 +#define PHY_CTRL5_FORCE_TEST_K_MASK 0x00008000 +#define PHY_CTRL5_FORCE_TEST_K_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_K_MASK) >> PHY_CTRL5_FORCE_TEST_K_LSB) +#define PHY_CTRL5_FORCE_TEST_K_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_K_LSB) & PHY_CTRL5_FORCE_TEST_K_MASK) +#define PHY_CTRL5_FORCE_TEST_K_RESET 0x0 // 0 +#define PHY_CTRL5_FORCE_TEST_J_MSB 14 +#define PHY_CTRL5_FORCE_TEST_J_LSB 14 +#define PHY_CTRL5_FORCE_TEST_J_MASK 0x00004000 +#define PHY_CTRL5_FORCE_TEST_J_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_J_MASK) >> PHY_CTRL5_FORCE_TEST_J_LSB) +#define PHY_CTRL5_FORCE_TEST_J_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_J_LSB) & PHY_CTRL5_FORCE_TEST_J_MASK) +#define PHY_CTRL5_FORCE_TEST_J_RESET 0x0 // 0 +#define PHY_CTRL5_FORCE_IDDQ_MSB 13 +#define PHY_CTRL5_FORCE_IDDQ_LSB 13 +#define PHY_CTRL5_FORCE_IDDQ_MASK 0x00002000 +#define PHY_CTRL5_FORCE_IDDQ_GET(x) (((x) & PHY_CTRL5_FORCE_IDDQ_MASK) >> PHY_CTRL5_FORCE_IDDQ_LSB) +#define PHY_CTRL5_FORCE_IDDQ_SET(x) (((x) << PHY_CTRL5_FORCE_IDDQ_LSB) & PHY_CTRL5_FORCE_IDDQ_MASK) +#define PHY_CTRL5_FORCE_IDDQ_RESET 0x0 // 0 +#define PHY_CTRL5_EB_WATERMARK_MSB 12 +#define PHY_CTRL5_EB_WATERMARK_LSB 7 +#define PHY_CTRL5_EB_WATERMARK_MASK 0x00001f80 +#define PHY_CTRL5_EB_WATERMARK_GET(x) (((x) & PHY_CTRL5_EB_WATERMARK_MASK) >> PHY_CTRL5_EB_WATERMARK_LSB) +#define PHY_CTRL5_EB_WATERMARK_SET(x) (((x) << PHY_CTRL5_EB_WATERMARK_LSB) & PHY_CTRL5_EB_WATERMARK_MASK) +#define PHY_CTRL5_EB_WATERMARK_RESET 0x14 // 20 +#define PHY_CTRL5_TX_BIAS_DELAY_MSB 6 +#define PHY_CTRL5_TX_BIAS_DELAY_LSB 0 +#define PHY_CTRL5_TX_BIAS_DELAY_MASK 0x0000007f +#define PHY_CTRL5_TX_BIAS_DELAY_GET(x) (((x) & PHY_CTRL5_TX_BIAS_DELAY_MASK) >> PHY_CTRL5_TX_BIAS_DELAY_LSB) +#define PHY_CTRL5_TX_BIAS_DELAY_SET(x) (((x) << PHY_CTRL5_TX_BIAS_DELAY_LSB) & PHY_CTRL5_TX_BIAS_DELAY_MASK) +#define PHY_CTRL5_TX_BIAS_DELAY_RESET 0x32 // 50 +#define PHY_CTRL5_ADDRESS 0x18116c94 +#define PHY_CTRL5_OFFSET 0x0014 +// SW modifiable bits +#define PHY_CTRL5_SW_MASK 0xffffffff +// bits defined at reset +#define PHY_CTRL5_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PHY_CTRL5_RESET 0x3b200a32 +#define PHY_CTRL5_RESET_1 0x3b202a58 + +#define PHY_CTRL6_SPARE_BITS_MSB 31 +#define PHY_CTRL6_SPARE_BITS_LSB 9 +#define PHY_CTRL6_SPARE_BITS_MASK 0xfffffe00 +#define PHY_CTRL6_SPARE_BITS_GET(x) (((x) & PHY_CTRL6_SPARE_BITS_MASK) >> PHY_CTRL6_SPARE_BITS_LSB) +#define PHY_CTRL6_SPARE_BITS_SET(x) (((x) << PHY_CTRL6_SPARE_BITS_LSB) & PHY_CTRL6_SPARE_BITS_MASK) +#define PHY_CTRL6_SPARE_BITS_RESET 0x0 // 0 +#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_MSB 8 +#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB 8 +#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK 0x00000100 +#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_GET(x) (((x) & PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK) >> PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB) +#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_SET(x) (((x) << PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB) & PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK) +#define PHY_CTRL6_DIS_SETUP_RETRY_FIX_RESET 0x0 // 0 +#define PHY_CTRL6_XCVR_SEL_MSB 7 +#define PHY_CTRL6_XCVR_SEL_LSB 6 +#define PHY_CTRL6_XCVR_SEL_MASK 0x000000c0 +#define PHY_CTRL6_XCVR_SEL_GET(x) (((x) & PHY_CTRL6_XCVR_SEL_MASK) >> PHY_CTRL6_XCVR_SEL_LSB) +#define PHY_CTRL6_XCVR_SEL_SET(x) (((x) << PHY_CTRL6_XCVR_SEL_LSB) & PHY_CTRL6_XCVR_SEL_MASK) +#define PHY_CTRL6_XCVR_SEL_RESET 0x0 // 0 +#define PHY_CTRL6_XCVRSEL_OVERRIDE_MSB 5 +#define PHY_CTRL6_XCVRSEL_OVERRIDE_LSB 5 +#define PHY_CTRL6_XCVRSEL_OVERRIDE_MASK 0x00000020 +#define PHY_CTRL6_XCVRSEL_OVERRIDE_GET(x) (((x) & PHY_CTRL6_XCVRSEL_OVERRIDE_MASK) >> PHY_CTRL6_XCVRSEL_OVERRIDE_LSB) +#define PHY_CTRL6_XCVRSEL_OVERRIDE_SET(x) (((x) << PHY_CTRL6_XCVRSEL_OVERRIDE_LSB) & PHY_CTRL6_XCVRSEL_OVERRIDE_MASK) +#define PHY_CTRL6_XCVRSEL_OVERRIDE_RESET 0x0 // 0 +#define PHY_CTRL6_IDDIG_MSB 4 +#define PHY_CTRL6_IDDIG_LSB 4 +#define PHY_CTRL6_IDDIG_MASK 0x00000010 +#define PHY_CTRL6_IDDIG_GET(x) (((x) & PHY_CTRL6_IDDIG_MASK) >> PHY_CTRL6_IDDIG_LSB) +#define PHY_CTRL6_IDDIG_SET(x) (((x) << PHY_CTRL6_IDDIG_LSB) & PHY_CTRL6_IDDIG_MASK) +#define PHY_CTRL6_IDDIG_RESET 0x0 // 0 +#define PHY_CTRL6_SESSEND_MSB 3 +#define PHY_CTRL6_SESSEND_LSB 3 +#define PHY_CTRL6_SESSEND_MASK 0x00000008 +#define PHY_CTRL6_SESSEND_GET(x) (((x) & PHY_CTRL6_SESSEND_MASK) >> PHY_CTRL6_SESSEND_LSB) +#define PHY_CTRL6_SESSEND_SET(x) (((x) << PHY_CTRL6_SESSEND_LSB) & PHY_CTRL6_SESSEND_MASK) +#define PHY_CTRL6_SESSEND_RESET 0x0 // 0 +#define PHY_CTRL6_VBUSVALID_MSB 2 +#define PHY_CTRL6_VBUSVALID_LSB 2 +#define PHY_CTRL6_VBUSVALID_MASK 0x00000004 +#define PHY_CTRL6_VBUSVALID_GET(x) (((x) & PHY_CTRL6_VBUSVALID_MASK) >> PHY_CTRL6_VBUSVALID_LSB) +#define PHY_CTRL6_VBUSVALID_SET(x) (((x) << PHY_CTRL6_VBUSVALID_LSB) & PHY_CTRL6_VBUSVALID_MASK) +#define PHY_CTRL6_VBUSVALID_RESET 0x1 // 1 +#define PHY_CTRL6_BVALID_MSB 1 +#define PHY_CTRL6_BVALID_LSB 1 +#define PHY_CTRL6_BVALID_MASK 0x00000002 +#define PHY_CTRL6_BVALID_GET(x) (((x) & PHY_CTRL6_BVALID_MASK) >> PHY_CTRL6_BVALID_LSB) +#define PHY_CTRL6_BVALID_SET(x) (((x) << PHY_CTRL6_BVALID_LSB) & PHY_CTRL6_BVALID_MASK) +#define PHY_CTRL6_BVALID_RESET 0x1 // 1 +#define PHY_CTRL6_AVALID_MSB 0 +#define PHY_CTRL6_AVALID_LSB 0 +#define PHY_CTRL6_AVALID_MASK 0x00000001 +#define PHY_CTRL6_AVALID_GET(x) (((x) & PHY_CTRL6_AVALID_MASK) >> PHY_CTRL6_AVALID_LSB) +#define PHY_CTRL6_AVALID_SET(x) (((x) << PHY_CTRL6_AVALID_LSB) & PHY_CTRL6_AVALID_MASK) +#define PHY_CTRL6_AVALID_RESET 0x1 // 1 +#define PHY_CTRL6_ADDRESS 0x18116c98 +#define PHY_CTRL6_OFFSET 0x0018 +// SW modifiable bits +#define PHY_CTRL6_SW_MASK 0xffffffff +// bits defined at reset +#define PHY_CTRL6_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PHY_CTRL6_RESET 0x00000007 + +#define PHY_STATUS_TX_CAL_MSB 3 +#define PHY_STATUS_TX_CAL_LSB 0 +#define PHY_STATUS_TX_CAL_MASK 0x0000000f +#define PHY_STATUS_TX_CAL_GET(x) (((x) & PHY_STATUS_TX_CAL_MASK) >> PHY_STATUS_TX_CAL_LSB) +#define PHY_STATUS_TX_CAL_SET(x) (((x) << PHY_STATUS_TX_CAL_LSB) & PHY_STATUS_TX_CAL_MASK) +#define PHY_STATUS_TX_CAL_RESET 0x0 // 0 +#define PHY_STATUS_ADDRESS 0x18116c9c +#define PHY_STATUS_OFFSET 0x001c +// SW modifiable bits +#define PHY_STATUS_SW_MASK 0x0000000f +// bits defined at reset +#define PHY_STATUS_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PHY_STATUS_RESET 0x00000000 + +#define PHY_CTRL7_PPRBS_ERROR_RATE_MSB 31 +#define PHY_CTRL7_PPRBS_ERROR_RATE_LSB 11 +#define PHY_CTRL7_PPRBS_ERROR_RATE_MASK 0xfffff800 +#define PHY_CTRL7_PPRBS_ERROR_RATE_GET(x) (((x) & PHY_CTRL7_PPRBS_ERROR_RATE_MASK) >> PHY_CTRL7_PPRBS_ERROR_RATE_LSB) +#define PHY_CTRL7_PPRBS_ERROR_RATE_SET(x) (((x) << PHY_CTRL7_PPRBS_ERROR_RATE_LSB) & PHY_CTRL7_PPRBS_ERROR_RATE_MASK) +#define PHY_CTRL7_PPRBS_ERROR_RATE_RESET 0xa000 // 40960 +#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MSB 10 +#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB 1 +#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK 0x000007fe +#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_GET(x) (((x) & PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK) >> PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB) +#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_SET(x) (((x) << PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB) & PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK) +#define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_RESET 0x0 // 0 +#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_MSB 0 +#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB 0 +#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK 0x00000001 +#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_GET(x) (((x) & PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK) >> PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB) +#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_SET(x) (((x) << PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB) & PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK) +#define PHY_CTRL7_PPRBS_TRIGGER_ERROR_RESET 0x0 // 0 +#define PHY_CTRL7_ADDRESS 0x18116ca0 +#define PHY_CTRL7_OFFSET 0x0020 +// SW modifiable bits +#define PHY_CTRL7_SW_MASK 0xffffffff +// bits defined at reset +#define PHY_CTRL7_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PHY_CTRL7_RESET 0x05000000 + +#define PHY_CTRL8_USBPLL_PWD_MSB 7 +#define PHY_CTRL8_USBPLL_PWD_LSB 7 +#define PHY_CTRL8_USBPLL_PWD_MASK 0x00000080 +#define PHY_CTRL8_USBPLL_PWD_GET(x) (((x) & PHY_CTRL8_USBPLL_PWD_MASK) >> PHY_CTRL8_USBPLL_PWD_LSB) +#define PHY_CTRL8_USBPLL_PWD_SET(x) (((x) << PHY_CTRL8_USBPLL_PWD_LSB) & PHY_CTRL8_USBPLL_PWD_MASK) +#define PHY_CTRL8_USBPLL_PWD_RESET 0x0 // 0 +#define PHY_CTRL8_TX_FASTRISE_MSB 6 +#define PHY_CTRL8_TX_FASTRISE_LSB 4 +#define PHY_CTRL8_TX_FASTRISE_MASK 0x00000070 +#define PHY_CTRL8_TX_FASTRISE_GET(x) (((x) & PHY_CTRL8_TX_FASTRISE_MASK) >> PHY_CTRL8_TX_FASTRISE_LSB) +#define PHY_CTRL8_TX_FASTRISE_SET(x) (((x) << PHY_CTRL8_TX_FASTRISE_LSB) & PHY_CTRL8_TX_FASTRISE_MASK) +#define PHY_CTRL8_TX_FASTRISE_RESET 0x5 // 5 +#define PHY_CTRL8_TX_ENPRE_MSB 3 +#define PHY_CTRL8_TX_ENPRE_LSB 2 +#define PHY_CTRL8_TX_ENPRE_MASK 0x0000000c +#define PHY_CTRL8_TX_ENPRE_GET(x) (((x) & PHY_CTRL8_TX_ENPRE_MASK) >> PHY_CTRL8_TX_ENPRE_LSB) +#define PHY_CTRL8_TX_ENPRE_SET(x) (((x) << PHY_CTRL8_TX_ENPRE_LSB) & PHY_CTRL8_TX_ENPRE_MASK) +#define PHY_CTRL8_TX_ENPRE_RESET 0x0 // 0 +#define PHY_CTRL8_RX_SQ_HYST_EN_MSB 1 +#define PHY_CTRL8_RX_SQ_HYST_EN_LSB 1 +#define PHY_CTRL8_RX_SQ_HYST_EN_MASK 0x00000002 +#define PHY_CTRL8_RX_SQ_HYST_EN_GET(x) (((x) & PHY_CTRL8_RX_SQ_HYST_EN_MASK) >> PHY_CTRL8_RX_SQ_HYST_EN_LSB) +#define PHY_CTRL8_RX_SQ_HYST_EN_SET(x) (((x) << PHY_CTRL8_RX_SQ_HYST_EN_LSB) & PHY_CTRL8_RX_SQ_HYST_EN_MASK) +#define PHY_CTRL8_RX_SQ_HYST_EN_RESET 0x0 // 0 +#define PHY_CTRL8_RX_SKIP2_MSB 0 +#define PHY_CTRL8_RX_SKIP2_LSB 0 +#define PHY_CTRL8_RX_SKIP2_MASK 0x00000001 +#define PHY_CTRL8_RX_SKIP2_GET(x) (((x) & PHY_CTRL8_RX_SKIP2_MASK) >> PHY_CTRL8_RX_SKIP2_LSB) +#define PHY_CTRL8_RX_SKIP2_SET(x) (((x) << PHY_CTRL8_RX_SKIP2_LSB) & PHY_CTRL8_RX_SKIP2_MASK) +#define PHY_CTRL8_RX_SKIP2_RESET 0x0 // 0 +#define PHY_CTRL8_ADDRESS 0x18116ca4 +#define PHY_CTRL8_OFFSET 0x0024 +// SW modifiable bits +#define PHY_CTRL8_SW_MASK 0x000000ff +// bits defined at reset +#define PHY_CTRL8_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PHY_CTRL8_RESET 0x00000050 +#define CPU_DDR_CLOCK_CONTROL_SPARE_MSB 31 +#define CPU_DDR_CLOCK_CONTROL_SPARE_LSB 25 +#define CPU_DDR_CLOCK_CONTROL_SPARE_MASK 0xfe000000 +#define CPU_DDR_CLOCK_CONTROL_SPARE_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) >> CPU_DDR_CLOCK_CONTROL_SPARE_LSB) +#define CPU_DDR_CLOCK_CONTROL_SPARE_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_SPARE_LSB) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) +#define CPU_DDR_CLOCK_CONTROL_SPARE_RESET 0x0 // 0 +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MSB 24 +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24 +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000 +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) +#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET 0x1 // 1 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB 23 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB 23 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK 0x00800000 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET 0x0 // 0 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB 22 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB 22 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK 0x00400000 +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) +#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET 0x0 // 0 +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MSB 21 +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB 21 +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK 0x00200000 +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB) +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK) +#define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_RESET 0x1 // 1 +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MSB 20 +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB 20 +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK 0x00100000 +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB) +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK) +#define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_RESET 0x1 // 1 +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB 19 +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15 +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000 +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) +#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET 0x0 // 0 +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB 14 +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10 +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00 +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET 0x0 // 0 +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB 9 +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5 +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0 +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET 0x0 // 0 +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB 4 +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4 +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010 +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) +#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET 0x1 // 1 +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB 3 +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3 +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008 +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) +#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET 0x1 // 1 +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB 2 +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2 +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004 +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) +#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET 0x1 // 1 +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB 1 +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB 1 +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK 0x00000002 +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) +#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET 0x0 // 0 +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB 0 +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB 0 +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK 0x00000001 +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) +#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET 0x0 // 0 +#define CPU_DDR_CLOCK_CONTROL_ADDRESS 0x18050008 + +#define PCIE_PLL_CONFIG_UPDATING_MSB 31 +#define PCIE_PLL_CONFIG_UPDATING_LSB 31 +#define PCIE_PLL_CONFIG_UPDATING_MASK 0x80000000 +#define PCIE_PLL_CONFIG_UPDATING_GET(x) (((x) & PCIE_PLL_CONFIG_UPDATING_MASK) >> PCIE_PLL_CONFIG_UPDATING_LSB) +#define PCIE_PLL_CONFIG_UPDATING_SET(x) (((x) << PCIE_PLL_CONFIG_UPDATING_LSB) & PCIE_PLL_CONFIG_UPDATING_MASK) +#define PCIE_PLL_CONFIG_UPDATING_RESET 0x0 // 0 +#define PCIE_PLL_CONFIG_PLLPWD_MSB 30 +#define PCIE_PLL_CONFIG_PLLPWD_LSB 30 +#define PCIE_PLL_CONFIG_PLLPWD_MASK 0x40000000 +#define PCIE_PLL_CONFIG_PLLPWD_GET(x) (((x) & PCIE_PLL_CONFIG_PLLPWD_MASK) >> PCIE_PLL_CONFIG_PLLPWD_LSB) +#define PCIE_PLL_CONFIG_PLLPWD_SET(x) (((x) << PCIE_PLL_CONFIG_PLLPWD_LSB) & PCIE_PLL_CONFIG_PLLPWD_MASK) +#define PCIE_PLL_CONFIG_PLLPWD_RESET 0x1 // 1 +#define PCIE_PLL_CONFIG_BYPASS_MSB 16 +#define PCIE_PLL_CONFIG_BYPASS_LSB 16 +#define PCIE_PLL_CONFIG_BYPASS_MASK 0x00010000 +#define PCIE_PLL_CONFIG_BYPASS_GET(x) (((x) & PCIE_PLL_CONFIG_BYPASS_MASK) >> PCIE_PLL_CONFIG_BYPASS_LSB) +#define PCIE_PLL_CONFIG_BYPASS_SET(x) (((x) << PCIE_PLL_CONFIG_BYPASS_LSB) & PCIE_PLL_CONFIG_BYPASS_MASK) +#define PCIE_PLL_CONFIG_BYPASS_RESET 0x1 // 1 +#define PCIE_PLL_CONFIG_REFDIV_MSB 14 +#define PCIE_PLL_CONFIG_REFDIV_LSB 10 +#define PCIE_PLL_CONFIG_REFDIV_MASK 0x00007c00 +#define PCIE_PLL_CONFIG_REFDIV_GET(x) (((x) & PCIE_PLL_CONFIG_REFDIV_MASK) >> PCIE_PLL_CONFIG_REFDIV_LSB) +#define PCIE_PLL_CONFIG_REFDIV_SET(x) (((x) << PCIE_PLL_CONFIG_REFDIV_LSB) & PCIE_PLL_CONFIG_REFDIV_MASK) +#define PCIE_PLL_CONFIG_REFDIV_RESET 0x1 // 1 +#define PCIE_PLL_CONFIG_ADDRESS 0x18050010 + +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MSB 31 +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB 31 +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK 0x80000000 +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) >> PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) +#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_RESET 0x1 // 1 +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MSB 30 +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB 30 +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK 0x40000000 +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) >> PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) +#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_RESET 0x1 // 1 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MSB 20 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB 15 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK 0x001f8000 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_RESET 0x13 // 19 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MSB 14 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB 1 +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK 0x00007ffe +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) +#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_RESET 0x3fff // 16383 +#define PCIE_PLL_DITHER_DIV_MAX_ADDRESS 0x18050014 + +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MSB 20 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB 15 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK 0x001f8000 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_RESET 0x13 // 19 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MSB 14 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB 1 +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK 0x00007ffe +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) +#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_RESET 0x399d // 14749 +#define PCIE_PLL_DITHER_DIV_MIN_ADDRESS 0x18050018 + +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MSB 31 +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB 28 +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK 0xf0000000 +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) >> PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) +#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_RESET 0x0 // 0 +#define PCIE_PLL_DITHER_STEP_STEP_INT_MSB 24 +#define PCIE_PLL_DITHER_STEP_STEP_INT_LSB 15 +#define PCIE_PLL_DITHER_STEP_STEP_INT_MASK 0x01ff8000 +#define PCIE_PLL_DITHER_STEP_STEP_INT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) >> PCIE_PLL_DITHER_STEP_STEP_INT_LSB) +#define PCIE_PLL_DITHER_STEP_STEP_INT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_INT_LSB) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) +#define PCIE_PLL_DITHER_STEP_STEP_INT_RESET 0x0 // 0 +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MSB 14 +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB 1 +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK 0x00007ffe +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) >> PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) +#define PCIE_PLL_DITHER_STEP_STEP_FRAC_RESET 0xa // 10 +#define PCIE_PLL_DITHER_STEP_ADDRESS 0x1805001c + + + +// 32'h180f0008 (PCIE_PWR_MGMT) +#define PCIE_PWR_MGMT_PME_INT_MSB 8 +#define PCIE_PWR_MGMT_PME_INT_LSB 8 +#define PCIE_PWR_MGMT_PME_INT_MASK 0x00000100 +#define PCIE_PWR_MGMT_PME_INT_GET(x) (((x) & PCIE_PWR_MGMT_PME_INT_MASK) >> PCIE_PWR_MGMT_PME_INT_LSB) +#define PCIE_PWR_MGMT_PME_INT_SET(x) (((x) << PCIE_PWR_MGMT_PME_INT_LSB) & PCIE_PWR_MGMT_PME_INT_MASK) +#define PCIE_PWR_MGMT_PME_INT_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MSB 7 +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB 7 +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK 0x00000080 +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_GET(x) (((x) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) >> PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(x) (((x) << PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MSB 6 +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB 6 +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK 0x00000040 +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) >> PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_RADM_PM_PME_MSB 5 +#define PCIE_PWR_MGMT_RADM_PM_PME_LSB 5 +#define PCIE_PWR_MGMT_RADM_PM_PME_MASK 0x00000020 +#define PCIE_PWR_MGMT_RADM_PM_PME_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) >> PCIE_PWR_MGMT_RADM_PM_PME_LSB) +#define PCIE_PWR_MGMT_RADM_PM_PME_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_PME_LSB) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) +#define PCIE_PWR_MGMT_RADM_PM_PME_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_AUX_PM_EN_MSB 4 +#define PCIE_PWR_MGMT_AUX_PM_EN_LSB 4 +#define PCIE_PWR_MGMT_AUX_PM_EN_MASK 0x00000010 +#define PCIE_PWR_MGMT_AUX_PM_EN_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) >> PCIE_PWR_MGMT_AUX_PM_EN_LSB) +#define PCIE_PWR_MGMT_AUX_PM_EN_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PM_EN_LSB) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) +#define PCIE_PWR_MGMT_AUX_PM_EN_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_READY_ENTR_L23_MSB 3 +#define PCIE_PWR_MGMT_READY_ENTR_L23_LSB 3 +#define PCIE_PWR_MGMT_READY_ENTR_L23_MASK 0x00000008 +#define PCIE_PWR_MGMT_READY_ENTR_L23_GET(x) (((x) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) >> PCIE_PWR_MGMT_READY_ENTR_L23_LSB) +#define PCIE_PWR_MGMT_READY_ENTR_L23_SET(x) (((x) << PCIE_PWR_MGMT_READY_ENTR_L23_LSB) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) +#define PCIE_PWR_MGMT_READY_ENTR_L23_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_REQ_EXIT_L1_MSB 2 +#define PCIE_PWR_MGMT_REQ_EXIT_L1_LSB 2 +#define PCIE_PWR_MGMT_REQ_EXIT_L1_MASK 0x00000004 +#define PCIE_PWR_MGMT_REQ_EXIT_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) >> PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) +#define PCIE_PWR_MGMT_REQ_EXIT_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) +#define PCIE_PWR_MGMT_REQ_EXIT_L1_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MSB 1 +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB 1 +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK 0x00000002 +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) >> PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_AUX_PWR_DET_MSB 0 +#define PCIE_PWR_MGMT_AUX_PWR_DET_LSB 0 +#define PCIE_PWR_MGMT_AUX_PWR_DET_MASK 0x00000001 +#define PCIE_PWR_MGMT_AUX_PWR_DET_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) >> PCIE_PWR_MGMT_AUX_PWR_DET_LSB) +#define PCIE_PWR_MGMT_AUX_PWR_DET_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PWR_DET_LSB) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) +#define PCIE_PWR_MGMT_AUX_PWR_DET_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_ADDRESS 0x180f0008 +#define PCIE_PWR_MGMT_OFFSET 0x0008 +// SW modifiable bits +#define PCIE_PWR_MGMT_SW_MASK 0x000001ff +// bits defined at reset +#define PCIE_PWR_MGMT_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PCIE_PWR_MGMT_RESET 0x00000000 + + +// 32'h180600c0 (RST_CLKGAT_EN) +#define RST_CLKGAT_EN_SPARE_MSB 31 +#define RST_CLKGAT_EN_SPARE_LSB 12 +#define RST_CLKGAT_EN_SPARE_MASK 0xfffff000 +#define RST_CLKGAT_EN_SPARE_GET(x) (((x) & RST_CLKGAT_EN_SPARE_MASK) >> RST_CLKGAT_EN_SPARE_LSB) +#define RST_CLKGAT_EN_SPARE_SET(x) (((x) << RST_CLKGAT_EN_SPARE_LSB) & RST_CLKGAT_EN_SPARE_MASK) +#define RST_CLKGAT_EN_SPARE_RESET 0x0 // 0 +#define RST_CLKGAT_EN_WMAC_MSB 9 +#define RST_CLKGAT_EN_WMAC_LSB 9 +#define RST_CLKGAT_EN_WMAC_MASK 0x00000200 +#define RST_CLKGAT_EN_WMAC_GET(x) (((x) & RST_CLKGAT_EN_WMAC_MASK) >> RST_CLKGAT_EN_WMAC_LSB) +#define RST_CLKGAT_EN_WMAC_SET(x) (((x) << RST_CLKGAT_EN_WMAC_LSB) & RST_CLKGAT_EN_WMAC_MASK) +#define RST_CLKGAT_EN_WMAC_RESET 0x1 // 1 +#define RST_CLKGAT_EN_USB1_MSB 7 +#define RST_CLKGAT_EN_USB1_LSB 7 +#define RST_CLKGAT_EN_USB1_MASK 0x00000080 +#define RST_CLKGAT_EN_USB1_GET(x) (((x) & RST_CLKGAT_EN_USB1_MASK) >> RST_CLKGAT_EN_USB1_LSB) +#define RST_CLKGAT_EN_USB1_SET(x) (((x) << RST_CLKGAT_EN_USB1_LSB) & RST_CLKGAT_EN_USB1_MASK) +#define RST_CLKGAT_EN_USB1_RESET 0x1 // 1 +#define RST_CLKGAT_EN_GE1_MSB 6 +#define RST_CLKGAT_EN_GE1_LSB 6 +#define RST_CLKGAT_EN_GE1_MASK 0x00000040 +#define RST_CLKGAT_EN_GE1_GET(x) (((x) & RST_CLKGAT_EN_GE1_MASK) >> RST_CLKGAT_EN_GE1_LSB) +#define RST_CLKGAT_EN_GE1_SET(x) (((x) << RST_CLKGAT_EN_GE1_LSB) & RST_CLKGAT_EN_GE1_MASK) +#define RST_CLKGAT_EN_GE1_RESET 0x1 // 1 +#define RST_CLKGAT_EN_GE0_MSB 5 +#define RST_CLKGAT_EN_GE0_LSB 5 +#define RST_CLKGAT_EN_GE0_MASK 0x00000020 +#define RST_CLKGAT_EN_GE0_GET(x) (((x) & RST_CLKGAT_EN_GE0_MASK) >> RST_CLKGAT_EN_GE0_LSB) +#define RST_CLKGAT_EN_GE0_SET(x) (((x) << RST_CLKGAT_EN_GE0_LSB) & RST_CLKGAT_EN_GE0_MASK) +#define RST_CLKGAT_EN_GE0_RESET 0x1 // 1 +#define RST_CLKGAT_EN_PCIE_RC_MSB 1 +#define RST_CLKGAT_EN_PCIE_RC_LSB 1 +#define RST_CLKGAT_EN_PCIE_RC_MASK 0x00000002 +#define RST_CLKGAT_EN_PCIE_RC_GET(x) (((x) & RST_CLKGAT_EN_PCIE_RC_MASK) >> RST_CLKGAT_EN_PCIE_RC_LSB) +#define RST_CLKGAT_EN_PCIE_RC_SET(x) (((x) << RST_CLKGAT_EN_PCIE_RC_LSB) & RST_CLKGAT_EN_PCIE_RC_MASK) +#define RST_CLKGAT_EN_PCIE_RC_RESET 0x1 // 1 +#define RST_CLKGAT_EN_ADDRESS 0x180600c0 +#define RST_CLKGAT_EN_OFFSET 0x00c0 +// SW modifiable bits +#define RST_CLKGAT_EN_SW_MASK 0xfffff2e2 +// bits defined at reset +#define RST_CLKGAT_EN_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define RST_CLKGAT_EN_RESET 0x000002e2 + + + +#define PCIE_PHY_REG_1_ADDRESS 0x18116cc0 +#define PCIE_PHY_REG_3_ADDRESS 0x18116cc8 + + + + + +#define LDO_POWER_CONTROL_PKG_SEL_MSB 5 +#define LDO_POWER_CONTROL_PKG_SEL_LSB 5 +#define LDO_POWER_CONTROL_PKG_SEL_MASK 0x00000020 +#define LDO_POWER_CONTROL_PKG_SEL_GET(x) (((x) & LDO_POWER_CONTROL_PKG_SEL_MASK) >> LDO_POWER_CONTROL_PKG_SEL_LSB) +#define LDO_POWER_CONTROL_PKG_SEL_SET(x) (((x) << LDO_POWER_CONTROL_PKG_SEL_LSB) & LDO_POWER_CONTROL_PKG_SEL_MASK) +#define LDO_POWER_CONTROL_PKG_SEL_RESET 0x0 // 0 +#define LDO_POWER_CONTROL_PWDLDO_CPU_MSB 4 +#define LDO_POWER_CONTROL_PWDLDO_CPU_LSB 4 +#define LDO_POWER_CONTROL_PWDLDO_CPU_MASK 0x00000010 +#define LDO_POWER_CONTROL_PWDLDO_CPU_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) >> LDO_POWER_CONTROL_PWDLDO_CPU_LSB) +#define LDO_POWER_CONTROL_PWDLDO_CPU_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_CPU_LSB) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) +#define LDO_POWER_CONTROL_PWDLDO_CPU_RESET 0x0 // 0 +#define LDO_POWER_CONTROL_PWDLDO_DDR_MSB 3 +#define LDO_POWER_CONTROL_PWDLDO_DDR_LSB 3 +#define LDO_POWER_CONTROL_PWDLDO_DDR_MASK 0x00000008 +#define LDO_POWER_CONTROL_PWDLDO_DDR_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) >> LDO_POWER_CONTROL_PWDLDO_DDR_LSB) +#define LDO_POWER_CONTROL_PWDLDO_DDR_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_DDR_LSB) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) +#define LDO_POWER_CONTROL_PWDLDO_DDR_RESET 0x0 // 0 +#define LDO_POWER_CONTROL_CPU_REFSEL_MSB 2 +#define LDO_POWER_CONTROL_CPU_REFSEL_LSB 1 +#define LDO_POWER_CONTROL_CPU_REFSEL_MASK 0x00000006 +#define LDO_POWER_CONTROL_CPU_REFSEL_GET(x) (((x) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) >> LDO_POWER_CONTROL_CPU_REFSEL_LSB) +#define LDO_POWER_CONTROL_CPU_REFSEL_SET(x) (((x) << LDO_POWER_CONTROL_CPU_REFSEL_LSB) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) +#define LDO_POWER_CONTROL_CPU_REFSEL_RESET 0x3 // 3 +#define LDO_POWER_CONTROL_SELECT_DDR1_MSB 0 +#define LDO_POWER_CONTROL_SELECT_DDR1_LSB 0 +#define LDO_POWER_CONTROL_SELECT_DDR1_MASK 0x00000001 +#define LDO_POWER_CONTROL_SELECT_DDR1_GET(x) (((x) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) >> LDO_POWER_CONTROL_SELECT_DDR1_LSB) +#define LDO_POWER_CONTROL_SELECT_DDR1_SET(x) (((x) << LDO_POWER_CONTROL_SELECT_DDR1_LSB) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) +#define LDO_POWER_CONTROL_SELECT_DDR1_RESET 0x0 // 0 +#define LDO_POWER_CONTROL_ADDRESS 0x18050020 + +#define SWITCH_CLOCK_SPARE_SPARE_MSB 31 +#define SWITCH_CLOCK_SPARE_SPARE_LSB 12 +#define SWITCH_CLOCK_SPARE_SPARE_MASK 0xfffff000 +#define SWITCH_CLOCK_SPARE_SPARE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB) +#define SWITCH_CLOCK_SPARE_SPARE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK) +#define SWITCH_CLOCK_SPARE_SPARE_RESET 0x0 // 0 +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB 11 +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB 8 +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0x00000f00 +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) +#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET 0x5 // 5 +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB 7 +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB 7 +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK 0x00000080 +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) +#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET 0x0 // 0 +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MSB 6 +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB 6 +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK 0x00000040 +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB) +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK) +#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_RESET 0x0 // 0 +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MSB 5 +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB 5 +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK 0x00000020 +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_GET(x) (((x) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) >> SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_SET(x) (((x) << SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) +#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_RESET 0x1 // 1 +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MSB 4 +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB 4 +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK 0x00000010 +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_GET(x) (((x) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) >> SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_SET(x) (((x) << SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) +#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_RESET 0x1 // 1 +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MSB 3 +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB 3 +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK 0x00000008 +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_GET(x) (((x) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) >> SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_SET(x) (((x) << SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) +#define SWITCH_CLOCK_SPARE_EEE_ENABLE_RESET 0x0 // 0 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MSB 2 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB 2 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK 0x00000004 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB) +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK) +#define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_RESET 0x0 // 0 +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MSB 1 +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB 1 +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK 0x00000002 +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) >> SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) +#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_RESET 0x0 // 0 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MSB 0 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB 0 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK 0x00000001 +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) +#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_RESET 0x1 // 1 +#define SWITCH_CLOCK_SPARE_ADDRESS 0x18050024 + +#define CURRENT_PCIE_PLL_DITHER_INT_MSB 20 +#define CURRENT_PCIE_PLL_DITHER_INT_LSB 15 +#define CURRENT_PCIE_PLL_DITHER_INT_MASK 0x001f8000 +#define CURRENT_PCIE_PLL_DITHER_INT_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_INT_MASK) >> CURRENT_PCIE_PLL_DITHER_INT_LSB) +#define CURRENT_PCIE_PLL_DITHER_INT_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_INT_LSB) & CURRENT_PCIE_PLL_DITHER_INT_MASK) +#define CURRENT_PCIE_PLL_DITHER_INT_RESET 0x1 // 1 +#define CURRENT_PCIE_PLL_DITHER_FRAC_MSB 13 +#define CURRENT_PCIE_PLL_DITHER_FRAC_LSB 0 +#define CURRENT_PCIE_PLL_DITHER_FRAC_MASK 0x00003fff +#define CURRENT_PCIE_PLL_DITHER_FRAC_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) >> CURRENT_PCIE_PLL_DITHER_FRAC_LSB) +#define CURRENT_PCIE_PLL_DITHER_FRAC_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_FRAC_LSB) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) +#define CURRENT_PCIE_PLL_DITHER_FRAC_RESET 0x0 // 0 +#define CURRENT_PCIE_PLL_DITHER_ADDRESS 0x18050028 + +#define ETH_XMII_TX_INVERT_MSB 31 +#define ETH_XMII_TX_INVERT_LSB 31 +#define ETH_XMII_TX_INVERT_MASK 0x80000000 +#define ETH_XMII_TX_INVERT_GET(x) (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB) +#define ETH_XMII_TX_INVERT_SET(x) (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK) +#define ETH_XMII_TX_INVERT_RESET 0x0 // 0 +#define ETH_XMII_GIGE_QUAD_MSB 30 +#define ETH_XMII_GIGE_QUAD_LSB 30 +#define ETH_XMII_GIGE_QUAD_MASK 0x40000000 +#define ETH_XMII_GIGE_QUAD_GET(x) (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB) +#define ETH_XMII_GIGE_QUAD_SET(x) (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK) +#define ETH_XMII_GIGE_QUAD_RESET 0x0 // 0 +#define ETH_XMII_RX_DELAY_MSB 29 +#define ETH_XMII_RX_DELAY_LSB 28 +#define ETH_XMII_RX_DELAY_MASK 0x30000000 +#define ETH_XMII_RX_DELAY_GET(x) (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB) +#define ETH_XMII_RX_DELAY_SET(x) (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK) +#define ETH_XMII_RX_DELAY_RESET 0x0 // 0 +#define ETH_XMII_TX_DELAY_MSB 27 +#define ETH_XMII_TX_DELAY_LSB 26 +#define ETH_XMII_TX_DELAY_MASK 0x0c000000 +#define ETH_XMII_TX_DELAY_GET(x) (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB) +#define ETH_XMII_TX_DELAY_SET(x) (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK) +#define ETH_XMII_TX_DELAY_RESET 0x0 // 0 +#define ETH_XMII_GIGE_MSB 25 +#define ETH_XMII_GIGE_LSB 25 +#define ETH_XMII_GIGE_MASK 0x02000000 +#define ETH_XMII_GIGE_GET(x) (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB) +#define ETH_XMII_GIGE_SET(x) (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK) +#define ETH_XMII_GIGE_RESET 0x0 // 0 +#define ETH_XMII_OFFSET_PHASE_MSB 24 +#define ETH_XMII_OFFSET_PHASE_LSB 24 +#define ETH_XMII_OFFSET_PHASE_MASK 0x01000000 +#define ETH_XMII_OFFSET_PHASE_GET(x) (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB) +#define ETH_XMII_OFFSET_PHASE_SET(x) (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK) +#define ETH_XMII_OFFSET_PHASE_RESET 0x0 // 0 +#define ETH_XMII_OFFSET_COUNT_MSB 23 +#define ETH_XMII_OFFSET_COUNT_LSB 16 +#define ETH_XMII_OFFSET_COUNT_MASK 0x00ff0000 +#define ETH_XMII_OFFSET_COUNT_GET(x) (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB) +#define ETH_XMII_OFFSET_COUNT_SET(x) (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK) +#define ETH_XMII_OFFSET_COUNT_RESET 0x0 // 0 +#define ETH_XMII_PHASE1_COUNT_MSB 15 +#define ETH_XMII_PHASE1_COUNT_LSB 8 +#define ETH_XMII_PHASE1_COUNT_MASK 0x0000ff00 +#define ETH_XMII_PHASE1_COUNT_GET(x) (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB) +#define ETH_XMII_PHASE1_COUNT_SET(x) (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK) +#define ETH_XMII_PHASE1_COUNT_RESET 0x1 // 1 +#define ETH_XMII_PHASE0_COUNT_MSB 7 +#define ETH_XMII_PHASE0_COUNT_LSB 0 +#define ETH_XMII_PHASE0_COUNT_MASK 0x000000ff +#define ETH_XMII_PHASE0_COUNT_GET(x) (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB) +#define ETH_XMII_PHASE0_COUNT_SET(x) (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK) +#define ETH_XMII_PHASE0_COUNT_RESET 0x1 // 1 +#define ETH_XMII_ADDRESS 0x1805002c + +#define BB_PLL_CONFIG_UPDATING_MSB 31 +#define BB_PLL_CONFIG_UPDATING_LSB 31 +#define BB_PLL_CONFIG_UPDATING_MASK 0x80000000 +#define BB_PLL_CONFIG_UPDATING_GET(x) (((x) & BB_PLL_CONFIG_UPDATING_MASK) >> BB_PLL_CONFIG_UPDATING_LSB) +#define BB_PLL_CONFIG_UPDATING_SET(x) (((x) << BB_PLL_CONFIG_UPDATING_LSB) & BB_PLL_CONFIG_UPDATING_MASK) +#define BB_PLL_CONFIG_UPDATING_RESET 0x1 // 1 +#define BB_PLL_CONFIG_PLLPWD_MSB 30 +#define BB_PLL_CONFIG_PLLPWD_LSB 30 +#define BB_PLL_CONFIG_PLLPWD_MASK 0x40000000 +#define BB_PLL_CONFIG_PLLPWD_GET(x) (((x) & BB_PLL_CONFIG_PLLPWD_MASK) >> BB_PLL_CONFIG_PLLPWD_LSB) +#define BB_PLL_CONFIG_PLLPWD_SET(x) (((x) << BB_PLL_CONFIG_PLLPWD_LSB) & BB_PLL_CONFIG_PLLPWD_MASK) +#define BB_PLL_CONFIG_PLLPWD_RESET 0x1 // 1 +#define BB_PLL_CONFIG_SPARE_MSB 29 +#define BB_PLL_CONFIG_SPARE_LSB 29 +#define BB_PLL_CONFIG_SPARE_MASK 0x20000000 +#define BB_PLL_CONFIG_SPARE_GET(x) (((x) & BB_PLL_CONFIG_SPARE_MASK) >> BB_PLL_CONFIG_SPARE_LSB) +#define BB_PLL_CONFIG_SPARE_SET(x) (((x) << BB_PLL_CONFIG_SPARE_LSB) & BB_PLL_CONFIG_SPARE_MASK) +#define BB_PLL_CONFIG_SPARE_RESET 0x0 // 0 +#define BB_PLL_CONFIG_REFDIV_MSB 28 +#define BB_PLL_CONFIG_REFDIV_LSB 24 +#define BB_PLL_CONFIG_REFDIV_MASK 0x1f000000 +#define BB_PLL_CONFIG_REFDIV_GET(x) (((x) & BB_PLL_CONFIG_REFDIV_MASK) >> BB_PLL_CONFIG_REFDIV_LSB) +#define BB_PLL_CONFIG_REFDIV_SET(x) (((x) << BB_PLL_CONFIG_REFDIV_LSB) & BB_PLL_CONFIG_REFDIV_MASK) +#define BB_PLL_CONFIG_REFDIV_RESET 0x1 // 1 +#define BB_PLL_CONFIG_NINT_MSB 21 +#define BB_PLL_CONFIG_NINT_LSB 16 +#define BB_PLL_CONFIG_NINT_MASK 0x003f0000 +#define BB_PLL_CONFIG_NINT_GET(x) (((x) & BB_PLL_CONFIG_NINT_MASK) >> BB_PLL_CONFIG_NINT_LSB) +#define BB_PLL_CONFIG_NINT_SET(x) (((x) << BB_PLL_CONFIG_NINT_LSB) & BB_PLL_CONFIG_NINT_MASK) +#define BB_PLL_CONFIG_NINT_RESET 0x2 // 2 +#define BB_PLL_CONFIG_NFRAC_MSB 13 +#define BB_PLL_CONFIG_NFRAC_LSB 0 +#define BB_PLL_CONFIG_NFRAC_MASK 0x00003fff +#define BB_PLL_CONFIG_NFRAC_GET(x) (((x) & BB_PLL_CONFIG_NFRAC_MASK) >> BB_PLL_CONFIG_NFRAC_LSB) +#define BB_PLL_CONFIG_NFRAC_SET(x) (((x) << BB_PLL_CONFIG_NFRAC_LSB) & BB_PLL_CONFIG_NFRAC_MASK) +#define BB_PLL_CONFIG_NFRAC_RESET 0xccc // 3276 +#define BB_PLL_CONFIG_ADDRESS 0x18050040 + +#define DDR_PLL_DITHER_DITHER_EN_MSB 31 +#define DDR_PLL_DITHER_DITHER_EN_LSB 31 +#define DDR_PLL_DITHER_DITHER_EN_MASK 0x80000000 +#define DDR_PLL_DITHER_DITHER_EN_GET(x) (((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB) +#define DDR_PLL_DITHER_DITHER_EN_SET(x) (((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK) +#define DDR_PLL_DITHER_DITHER_EN_RESET 0x0 // 0 +#define DDR_PLL_DITHER_UPDATE_COUNT_MSB 30 +#define DDR_PLL_DITHER_UPDATE_COUNT_LSB 27 +#define DDR_PLL_DITHER_UPDATE_COUNT_MASK 0x78000000 +#define DDR_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER_UPDATE_COUNT_LSB) +#define DDR_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) +#define DDR_PLL_DITHER_UPDATE_COUNT_RESET 0xf // 15 +#define DDR_PLL_DITHER_NFRAC_STEP_MSB 26 +#define DDR_PLL_DITHER_NFRAC_STEP_LSB 20 +#define DDR_PLL_DITHER_NFRAC_STEP_MASK 0x07f00000 +#define DDR_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> DDR_PLL_DITHER_NFRAC_STEP_LSB) +#define DDR_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) & DDR_PLL_DITHER_NFRAC_STEP_MASK) +#define DDR_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1 +#define DDR_PLL_DITHER_NFRAC_MIN_MSB 19 +#define DDR_PLL_DITHER_NFRAC_MIN_LSB 10 +#define DDR_PLL_DITHER_NFRAC_MIN_MASK 0x000ffc00 +#define DDR_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MIN_MASK) >> DDR_PLL_DITHER_NFRAC_MIN_LSB) +#define DDR_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MIN_LSB) & DDR_PLL_DITHER_NFRAC_MIN_MASK) +#define DDR_PLL_DITHER_NFRAC_MIN_RESET 0x19 // 25 +#define DDR_PLL_DITHER_NFRAC_MAX_MSB 9 +#define DDR_PLL_DITHER_NFRAC_MAX_LSB 0 +#define DDR_PLL_DITHER_NFRAC_MAX_MASK 0x000003ff +#define DDR_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MAX_MASK) >> DDR_PLL_DITHER_NFRAC_MAX_LSB) +#define DDR_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MAX_LSB) & DDR_PLL_DITHER_NFRAC_MAX_MASK) +#define DDR_PLL_DITHER_NFRAC_MAX_RESET 0x3e8 // 1000 +#define DDR_PLL_DITHER_ADDRESS 0x18050044 + +#define CPU_PLL_DITHER_DITHER_EN_MSB 31 +#define CPU_PLL_DITHER_DITHER_EN_LSB 31 +#define CPU_PLL_DITHER_DITHER_EN_MASK 0x80000000 +#define CPU_PLL_DITHER_DITHER_EN_GET(x) (((x) & CPU_PLL_DITHER_DITHER_EN_MASK) >> CPU_PLL_DITHER_DITHER_EN_LSB) +#define CPU_PLL_DITHER_DITHER_EN_SET(x) (((x) << CPU_PLL_DITHER_DITHER_EN_LSB) & CPU_PLL_DITHER_DITHER_EN_MASK) +#define CPU_PLL_DITHER_DITHER_EN_RESET 0x0 // 0 +#define CPU_PLL_DITHER_UPDATE_COUNT_MSB 23 +#define CPU_PLL_DITHER_UPDATE_COUNT_LSB 18 +#define CPU_PLL_DITHER_UPDATE_COUNT_MASK 0x00fc0000 +#define CPU_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) >> CPU_PLL_DITHER_UPDATE_COUNT_LSB) +#define CPU_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) +#define CPU_PLL_DITHER_UPDATE_COUNT_RESET 0x14 // 20 +#define CPU_PLL_DITHER_NFRAC_STEP_MSB 17 +#define CPU_PLL_DITHER_NFRAC_STEP_LSB 12 +#define CPU_PLL_DITHER_NFRAC_STEP_MASK 0x0003f000 +#define CPU_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_STEP_MASK) >> CPU_PLL_DITHER_NFRAC_STEP_LSB) +#define CPU_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) & CPU_PLL_DITHER_NFRAC_STEP_MASK) +#define CPU_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1 +#define CPU_PLL_DITHER_NFRAC_MIN_MSB 11 +#define CPU_PLL_DITHER_NFRAC_MIN_LSB 6 +#define CPU_PLL_DITHER_NFRAC_MIN_MASK 0x00000fc0 +#define CPU_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MIN_MASK) >> CPU_PLL_DITHER_NFRAC_MIN_LSB) +#define CPU_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MIN_LSB) & CPU_PLL_DITHER_NFRAC_MIN_MASK) +#define CPU_PLL_DITHER_NFRAC_MIN_RESET 0x3 // 3 +#define CPU_PLL_DITHER_NFRAC_MAX_MSB 5 +#define CPU_PLL_DITHER_NFRAC_MAX_LSB 0 +#define CPU_PLL_DITHER_NFRAC_MAX_MASK 0x0000003f +#define CPU_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MAX_MASK) >> CPU_PLL_DITHER_NFRAC_MAX_LSB) +#define CPU_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MAX_LSB) & CPU_PLL_DITHER_NFRAC_MAX_MASK) +#define CPU_PLL_DITHER_NFRAC_MAX_RESET 0x3c // 60 +#define CPU_PLL_DITHER_ADDRESS 0x18050048 + +#define RST_RESET_USB_EXT_PWR_SEQ_MSB 29 +#define RST_RESET_USB_EXT_PWR_SEQ_LSB 29 +#define RST_RESET_USB_EXT_PWR_SEQ_MASK 0x20000000 +#define RST_RESET_USB_EXT_PWR_SEQ_GET(x) (((x) & RST_RESET_USB_EXT_PWR_SEQ_MASK) >> RST_RESET_USB_EXT_PWR_SEQ_LSB) +#define RST_RESET_USB_EXT_PWR_SEQ_SET(x) (((x) << RST_RESET_USB_EXT_PWR_SEQ_LSB) & RST_RESET_USB_EXT_PWR_SEQ_MASK) +#define RST_RESET_USB_EXT_PWR_SEQ_RESET 0x1 // 1 +#define RST_RESET_EXTERNAL_RESET_MSB 28 +#define RST_RESET_EXTERNAL_RESET_LSB 28 +#define RST_RESET_EXTERNAL_RESET_MASK 0x10000000 +#define RST_RESET_EXTERNAL_RESET_GET(x) (((x) & RST_RESET_EXTERNAL_RESET_MASK) >> RST_RESET_EXTERNAL_RESET_LSB) +#define RST_RESET_EXTERNAL_RESET_SET(x) (((x) << RST_RESET_EXTERNAL_RESET_LSB) & RST_RESET_EXTERNAL_RESET_MASK) +#define RST_RESET_EXTERNAL_RESET_RESET 0x0 // 0 +#define RST_RESET_RTC_RESET_MSB 27 +#define RST_RESET_RTC_RESET_LSB 27 +#define RST_RESET_RTC_RESET_MASK 0x08000000 +#define RST_RESET_RTC_RESET_GET(x) (((x) & RST_RESET_RTC_RESET_MASK) >> RST_RESET_RTC_RESET_LSB) +#define RST_RESET_RTC_RESET_SET(x) (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK) +#define RST_RESET_RTC_RESET_RESET 0x1 // 1 +#define RST_RESET_FULL_CHIP_RESET_MSB 24 +#define RST_RESET_FULL_CHIP_RESET_LSB 24 +#define RST_RESET_FULL_CHIP_RESET_MASK 0x01000000 +#define RST_RESET_FULL_CHIP_RESET_GET(x) (((x) & RST_RESET_FULL_CHIP_RESET_MASK) >> RST_RESET_FULL_CHIP_RESET_LSB) +#define RST_RESET_FULL_CHIP_RESET_SET(x) (((x) << RST_RESET_FULL_CHIP_RESET_LSB) & RST_RESET_FULL_CHIP_RESET_MASK) +#define RST_RESET_FULL_CHIP_RESET_RESET 0x0 // 0 +#define RST_RESET_GE1_MDIO_RESET_MSB 23 +#define RST_RESET_GE1_MDIO_RESET_LSB 23 +#define RST_RESET_GE1_MDIO_RESET_MASK 0x00800000 +#define RST_RESET_GE1_MDIO_RESET_GET(x) (((x) & RST_RESET_GE1_MDIO_RESET_MASK) >> RST_RESET_GE1_MDIO_RESET_LSB) +#define RST_RESET_GE1_MDIO_RESET_SET(x) (((x) << RST_RESET_GE1_MDIO_RESET_LSB) & RST_RESET_GE1_MDIO_RESET_MASK) +#define RST_RESET_GE1_MDIO_RESET_RESET 0x1 // 1 +#define RST_RESET_GE0_MDIO_RESET_MSB 22 +#define RST_RESET_GE0_MDIO_RESET_LSB 22 +#define RST_RESET_GE0_MDIO_RESET_MASK 0x00400000 +#define RST_RESET_GE0_MDIO_RESET_GET(x) (((x) & RST_RESET_GE0_MDIO_RESET_MASK) >> RST_RESET_GE0_MDIO_RESET_LSB) +#define RST_RESET_GE0_MDIO_RESET_SET(x) (((x) << RST_RESET_GE0_MDIO_RESET_LSB) & RST_RESET_GE0_MDIO_RESET_MASK) +#define RST_RESET_GE0_MDIO_RESET_RESET 0x1 // 1 +#define RST_RESET_CPU_NMI_MSB 21 +#define RST_RESET_CPU_NMI_LSB 21 +#define RST_RESET_CPU_NMI_MASK 0x00200000 +#define RST_RESET_CPU_NMI_GET(x) (((x) & RST_RESET_CPU_NMI_MASK) >> RST_RESET_CPU_NMI_LSB) +#define RST_RESET_CPU_NMI_SET(x) (((x) << RST_RESET_CPU_NMI_LSB) & RST_RESET_CPU_NMI_MASK) +#define RST_RESET_CPU_NMI_RESET 0x0 // 0 +#define RST_RESET_CPU_COLD_RESET_MSB 20 +#define RST_RESET_CPU_COLD_RESET_LSB 20 +#define RST_RESET_CPU_COLD_RESET_MASK 0x00100000 +#define RST_RESET_CPU_COLD_RESET_GET(x) (((x) & RST_RESET_CPU_COLD_RESET_MASK) >> RST_RESET_CPU_COLD_RESET_LSB) +#define RST_RESET_CPU_COLD_RESET_SET(x) (((x) << RST_RESET_CPU_COLD_RESET_LSB) & RST_RESET_CPU_COLD_RESET_MASK) +#define RST_RESET_CPU_COLD_RESET_RESET 0x0 // 0 +#define RST_RESET_DDR_RESET_MSB 16 +#define RST_RESET_DDR_RESET_LSB 16 +#define RST_RESET_DDR_RESET_MASK 0x00010000 +#define RST_RESET_DDR_RESET_GET(x) (((x) & RST_RESET_DDR_RESET_MASK) >> RST_RESET_DDR_RESET_LSB) +#define RST_RESET_DDR_RESET_SET(x) (((x) << RST_RESET_DDR_RESET_LSB) & RST_RESET_DDR_RESET_MASK) +#define RST_RESET_DDR_RESET_RESET 0x0 // 0 +#define RST_RESET_USB_PHY_PLL_PWD_EXT_MSB 15 +#define RST_RESET_USB_PHY_PLL_PWD_EXT_LSB 15 +#define RST_RESET_USB_PHY_PLL_PWD_EXT_MASK 0x00008000 +#define RST_RESET_USB_PHY_PLL_PWD_EXT_GET(x) (((x) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) >> RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) +#define RST_RESET_USB_PHY_PLL_PWD_EXT_SET(x) (((x) << RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) +#define RST_RESET_USB_PHY_PLL_PWD_EXT_RESET 0x0 // 0 +#define RST_RESET_GE1_MAC_RESET_MSB 13 +#define RST_RESET_GE1_MAC_RESET_LSB 13 +#define RST_RESET_GE1_MAC_RESET_MASK 0x00002000 +#define RST_RESET_GE1_MAC_RESET_GET(x) (((x) & RST_RESET_GE1_MAC_RESET_MASK) >> RST_RESET_GE1_MAC_RESET_LSB) +#define RST_RESET_GE1_MAC_RESET_SET(x) (((x) << RST_RESET_GE1_MAC_RESET_LSB) & RST_RESET_GE1_MAC_RESET_MASK) +#define RST_RESET_GE1_MAC_RESET_RESET 0x1 // 1 +#define RST_RESET_ETH_SWITCH_ARESET_MSB 12 +#define RST_RESET_ETH_SWITCH_ARESET_LSB 12 +#define RST_RESET_ETH_SWITCH_ARESET_MASK 0x00001000 +#define RST_RESET_ETH_SWITCH_ARESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_ARESET_MASK) >> RST_RESET_ETH_SWITCH_ARESET_LSB) +#define RST_RESET_ETH_SWITCH_ARESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_ARESET_LSB) & RST_RESET_ETH_SWITCH_ARESET_MASK) +#define RST_RESET_ETH_SWITCH_ARESET_RESET 0x1 // 1 +#define RST_RESET_USB_PHY_ARESET_MSB 11 +#define RST_RESET_USB_PHY_ARESET_LSB 11 +#define RST_RESET_USB_PHY_ARESET_MASK 0x00000800 +#define RST_RESET_USB_PHY_ARESET_GET(x) (((x) & RST_RESET_USB_PHY_ARESET_MASK) >> RST_RESET_USB_PHY_ARESET_LSB) +#define RST_RESET_USB_PHY_ARESET_SET(x) (((x) << RST_RESET_USB_PHY_ARESET_LSB) & RST_RESET_USB_PHY_ARESET_MASK) +#define RST_RESET_USB_PHY_ARESET_RESET 0x1 // 1 +#define RST_RESET_GE0_MAC_RESET_MSB 9 +#define RST_RESET_GE0_MAC_RESET_LSB 9 +#define RST_RESET_GE0_MAC_RESET_MASK 0x00000200 +#define RST_RESET_GE0_MAC_RESET_GET(x) (((x) & RST_RESET_GE0_MAC_RESET_MASK) >> RST_RESET_GE0_MAC_RESET_LSB) +#define RST_RESET_GE0_MAC_RESET_SET(x) (((x) << RST_RESET_GE0_MAC_RESET_LSB) & RST_RESET_GE0_MAC_RESET_MASK) +#define RST_RESET_GE0_MAC_RESET_RESET 0x1 // 1 +#define RST_RESET_ETH_SWITCH_RESET_MSB 8 +#define RST_RESET_ETH_SWITCH_RESET_LSB 8 +#define RST_RESET_ETH_SWITCH_RESET_MASK 0x00000100 +#define RST_RESET_ETH_SWITCH_RESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_RESET_MASK) >> RST_RESET_ETH_SWITCH_RESET_LSB) +#define RST_RESET_ETH_SWITCH_RESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_RESET_LSB) & RST_RESET_ETH_SWITCH_RESET_MASK) +#define RST_RESET_ETH_SWITCH_RESET_RESET 0x1 // 1 +#define RST_RESET_PCIE_PHY_RESET_MSB 7 +#define RST_RESET_PCIE_PHY_RESET_LSB 7 +#define RST_RESET_PCIE_PHY_RESET_MASK 0x00000080 +#define RST_RESET_PCIE_PHY_RESET_GET(x) (((x) & RST_RESET_PCIE_PHY_RESET_MASK) >> RST_RESET_PCIE_PHY_RESET_LSB) +#define RST_RESET_PCIE_PHY_RESET_SET(x) (((x) << RST_RESET_PCIE_PHY_RESET_LSB) & RST_RESET_PCIE_PHY_RESET_MASK) +#define RST_RESET_PCIE_PHY_RESET_RESET 0x1 // 1 +#define RST_RESET_PCIE_RESET_MSB 6 +#define RST_RESET_PCIE_RESET_LSB 6 +#define RST_RESET_PCIE_RESET_MASK 0x00000040 +#define RST_RESET_PCIE_RESET_GET(x) (((x) & RST_RESET_PCIE_RESET_MASK) >> RST_RESET_PCIE_RESET_LSB) +#define RST_RESET_PCIE_RESET_SET(x) (((x) << RST_RESET_PCIE_RESET_LSB) & RST_RESET_PCIE_RESET_MASK) +#define RST_RESET_PCIE_RESET_RESET 0x1 // 1 +#define RST_RESET_USB_HOST_RESET_MSB 5 +#define RST_RESET_USB_HOST_RESET_LSB 5 +#define RST_RESET_USB_HOST_RESET_MASK 0x00000020 +#define RST_RESET_USB_HOST_RESET_GET(x) (((x) & RST_RESET_USB_HOST_RESET_MASK) >> RST_RESET_USB_HOST_RESET_LSB) +#define RST_RESET_USB_HOST_RESET_SET(x) (((x) << RST_RESET_USB_HOST_RESET_LSB) & RST_RESET_USB_HOST_RESET_MASK) +#define RST_RESET_USB_HOST_RESET_RESET 0x1 // 1 +#define RST_RESET_USB_PHY_RESET_MSB 4 +#define RST_RESET_USB_PHY_RESET_LSB 4 +#define RST_RESET_USB_PHY_RESET_MASK 0x00000010 +#define RST_RESET_USB_PHY_RESET_GET(x) (((x) & RST_RESET_USB_PHY_RESET_MASK) >> RST_RESET_USB_PHY_RESET_LSB) +#define RST_RESET_USB_PHY_RESET_SET(x) (((x) << RST_RESET_USB_PHY_RESET_LSB) & RST_RESET_USB_PHY_RESET_MASK) +#define RST_RESET_USB_PHY_RESET_RESET 0x1 // 1 +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MSB 3 +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB 3 +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK 0x00000008 +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_GET(x) (((x) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) >> RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(x) (((x) << RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) +#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_RESET 0x0 // 0 +#define RST_RESET_ADDRESS 0x1806001c + + +#define RST_MISC2_SPARE_MSB 31 +#define RST_MISC2_SPARE_LSB 26 +#define RST_MISC2_SPARE_MASK 0xfc000000 +#define RST_MISC2_SPARE_GET(x) (((x) & RST_MISC2_SPARE_MASK) >> RST_MISC2_SPARE_LSB) +#define RST_MISC2_SPARE_SET(x) (((x) << RST_MISC2_SPARE_LSB) & RST_MISC2_SPARE_MASK) +#define RST_MISC2_SPARE_RESET 0x0 // 0 +#define RST_MISC2_PCIE_CLKOBS1_SEL_MSB 19 +#define RST_MISC2_PCIE_CLKOBS1_SEL_LSB 19 +#define RST_MISC2_PCIE_CLKOBS1_SEL_MASK 0x00080000 +#define RST_MISC2_PCIE_CLKOBS1_SEL_GET(x) (((x) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK) >> RST_MISC2_PCIE_CLKOBS1_SEL_LSB) +#define RST_MISC2_PCIE_CLKOBS1_SEL_SET(x) (((x) << RST_MISC2_PCIE_CLKOBS1_SEL_LSB) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK) +#define RST_MISC2_PCIE_CLKOBS1_SEL_RESET 0x0 // 0 +#define RST_MISC2_EXT_HOST_WASP_RST_EN_MSB 18 +#define RST_MISC2_EXT_HOST_WASP_RST_EN_LSB 18 +#define RST_MISC2_EXT_HOST_WASP_RST_EN_MASK 0x00040000 +#define RST_MISC2_EXT_HOST_WASP_RST_EN_GET(x) (((x) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) >> RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) +#define RST_MISC2_EXT_HOST_WASP_RST_EN_SET(x) (((x) << RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) +#define RST_MISC2_EXT_HOST_WASP_RST_EN_RESET 0x0 // 0 +#define RST_MISC2_PERSTN_RCPHY_MSB 13 +#define RST_MISC2_PERSTN_RCPHY_LSB 13 +#define RST_MISC2_PERSTN_RCPHY_MASK 0x00002000 +#define RST_MISC2_PERSTN_RCPHY_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY_MASK) >> RST_MISC2_PERSTN_RCPHY_LSB) +#define RST_MISC2_PERSTN_RCPHY_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY_LSB) & RST_MISC2_PERSTN_RCPHY_MASK) +#define RST_MISC2_PERSTN_RCPHY_RESET 0x1 // 1 +#define RST_MISC2_RESERVED_MSB 3 +#define RST_MISC2_RESERVED_LSB 1 +#define RST_MISC2_RESERVED_MASK 0x0000000e +#define RST_MISC2_RESERVED_GET(x) (((x) & RST_MISC2_RESERVED_MASK) >> RST_MISC2_RESERVED_LSB) +#define RST_MISC2_RESERVED_SET(x) (((x) << RST_MISC2_RESERVED_LSB) & RST_MISC2_RESERVED_MASK) +#define RST_MISC2_RESERVED_RESET 0x0 // 0 +#define RST_MISC2_ADDRESS 0x180600bc + +#define PCIE_APP_CFG_TYPE_MSB 21 +#define PCIE_APP_CFG_TYPE_LSB 20 +#define PCIE_APP_CFG_TYPE_MASK 0x00300000 +#define PCIE_APP_CFG_TYPE_GET(x) (((x) & PCIE_APP_CFG_TYPE_MASK) >> PCIE_APP_CFG_TYPE_LSB) +#define PCIE_APP_CFG_TYPE_SET(x) (((x) << PCIE_APP_CFG_TYPE_LSB) & PCIE_APP_CFG_TYPE_MASK) +#define PCIE_APP_CFG_TYPE_RESET 0x0 // 0 +#define PCIE_APP_PCIE_BAR_MSN_MSB 19 +#define PCIE_APP_PCIE_BAR_MSN_LSB 16 +#define PCIE_APP_PCIE_BAR_MSN_MASK 0x000f0000 +#define PCIE_APP_PCIE_BAR_MSN_GET(x) (((x) & PCIE_APP_PCIE_BAR_MSN_MASK) >> PCIE_APP_PCIE_BAR_MSN_LSB) +#define PCIE_APP_PCIE_BAR_MSN_SET(x) (((x) << PCIE_APP_PCIE_BAR_MSN_LSB) & PCIE_APP_PCIE_BAR_MSN_MASK) +#define PCIE_APP_PCIE_BAR_MSN_RESET 0x1 // 1 +#define PCIE_APP_CFG_BE_MSB 15 +#define PCIE_APP_CFG_BE_LSB 12 +#define PCIE_APP_CFG_BE_MASK 0x0000f000 +#define PCIE_APP_CFG_BE_GET(x) (((x) & PCIE_APP_CFG_BE_MASK) >> PCIE_APP_CFG_BE_LSB) +#define PCIE_APP_CFG_BE_SET(x) (((x) << PCIE_APP_CFG_BE_LSB) & PCIE_APP_CFG_BE_MASK) +#define PCIE_APP_CFG_BE_RESET 0xf // 15 +#define PCIE_APP_SLV_RESP_ERR_MAP_MSB 11 +#define PCIE_APP_SLV_RESP_ERR_MAP_LSB 6 +#define PCIE_APP_SLV_RESP_ERR_MAP_MASK 0x00000fc0 +#define PCIE_APP_SLV_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_SLV_RESP_ERR_MAP_MASK) >> PCIE_APP_SLV_RESP_ERR_MAP_LSB) +#define PCIE_APP_SLV_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_SLV_RESP_ERR_MAP_LSB) & PCIE_APP_SLV_RESP_ERR_MAP_MASK) +#define PCIE_APP_SLV_RESP_ERR_MAP_RESET 0x3f // 63 +#define PCIE_APP_MSTR_RESP_ERR_MAP_MSB 5 +#define PCIE_APP_MSTR_RESP_ERR_MAP_LSB 4 +#define PCIE_APP_MSTR_RESP_ERR_MAP_MASK 0x00000030 +#define PCIE_APP_MSTR_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK) >> PCIE_APP_MSTR_RESP_ERR_MAP_LSB) +#define PCIE_APP_MSTR_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_MSTR_RESP_ERR_MAP_LSB) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK) +#define PCIE_APP_MSTR_RESP_ERR_MAP_RESET 0x0 // 0 +#define PCIE_APP_INIT_RST_MSB 3 +#define PCIE_APP_INIT_RST_LSB 3 +#define PCIE_APP_INIT_RST_MASK 0x00000008 +#define PCIE_APP_INIT_RST_GET(x) (((x) & PCIE_APP_INIT_RST_MASK) >> PCIE_APP_INIT_RST_LSB) +#define PCIE_APP_INIT_RST_SET(x) (((x) << PCIE_APP_INIT_RST_LSB) & PCIE_APP_INIT_RST_MASK) +#define PCIE_APP_INIT_RST_RESET 0x0 // 0 +#define PCIE_APP_PM_XMT_TURNOFF_MSB 2 +#define PCIE_APP_PM_XMT_TURNOFF_LSB 2 +#define PCIE_APP_PM_XMT_TURNOFF_MASK 0x00000004 +#define PCIE_APP_PM_XMT_TURNOFF_GET(x) (((x) & PCIE_APP_PM_XMT_TURNOFF_MASK) >> PCIE_APP_PM_XMT_TURNOFF_LSB) +#define PCIE_APP_PM_XMT_TURNOFF_SET(x) (((x) << PCIE_APP_PM_XMT_TURNOFF_LSB) & PCIE_APP_PM_XMT_TURNOFF_MASK) +#define PCIE_APP_PM_XMT_TURNOFF_RESET 0x0 // 0 +#define PCIE_APP_UNLOCK_MSG_MSB 1 +#define PCIE_APP_UNLOCK_MSG_LSB 1 +#define PCIE_APP_UNLOCK_MSG_MASK 0x00000002 +#define PCIE_APP_UNLOCK_MSG_GET(x) (((x) & PCIE_APP_UNLOCK_MSG_MASK) >> PCIE_APP_UNLOCK_MSG_LSB) +#define PCIE_APP_UNLOCK_MSG_SET(x) (((x) << PCIE_APP_UNLOCK_MSG_LSB) & PCIE_APP_UNLOCK_MSG_MASK) +#define PCIE_APP_UNLOCK_MSG_RESET 0x0 // 0 +#define PCIE_APP_LTSSM_ENABLE_MSB 0 +#define PCIE_APP_LTSSM_ENABLE_LSB 0 +#define PCIE_APP_LTSSM_ENABLE_MASK 0x00000001 +#define PCIE_APP_LTSSM_ENABLE_GET(x) (((x) & PCIE_APP_LTSSM_ENABLE_MASK) >> PCIE_APP_LTSSM_ENABLE_LSB) +#define PCIE_APP_LTSSM_ENABLE_SET(x) (((x) << PCIE_APP_LTSSM_ENABLE_LSB) & PCIE_APP_LTSSM_ENABLE_MASK) +#define PCIE_APP_LTSSM_ENABLE_RESET 0x0 // 0 +#define PCIE_APP_ADDRESS 0x180f0000 + +#define PCIE_PWR_MGMT_PME_INT_MSB 8 +#define PCIE_PWR_MGMT_PME_INT_LSB 8 +#define PCIE_PWR_MGMT_PME_INT_MASK 0x00000100 +#define PCIE_PWR_MGMT_PME_INT_GET(x) (((x) & PCIE_PWR_MGMT_PME_INT_MASK) >> PCIE_PWR_MGMT_PME_INT_LSB) +#define PCIE_PWR_MGMT_PME_INT_SET(x) (((x) << PCIE_PWR_MGMT_PME_INT_LSB) & PCIE_PWR_MGMT_PME_INT_MASK) +#define PCIE_PWR_MGMT_PME_INT_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MSB 7 +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB 7 +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK 0x00000080 +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_GET(x) (((x) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) >> PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(x) (((x) << PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) +#define PCIE_PWR_MGMT_ASSERT_CLKREQN_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MSB 6 +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB 6 +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK 0x00000040 +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) >> PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) +#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_RADM_PM_PME_MSB 5 +#define PCIE_PWR_MGMT_RADM_PM_PME_LSB 5 +#define PCIE_PWR_MGMT_RADM_PM_PME_MASK 0x00000020 +#define PCIE_PWR_MGMT_RADM_PM_PME_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) >> PCIE_PWR_MGMT_RADM_PM_PME_LSB) +#define PCIE_PWR_MGMT_RADM_PM_PME_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_PME_LSB) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) +#define PCIE_PWR_MGMT_RADM_PM_PME_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_AUX_PM_EN_MSB 4 +#define PCIE_PWR_MGMT_AUX_PM_EN_LSB 4 +#define PCIE_PWR_MGMT_AUX_PM_EN_MASK 0x00000010 +#define PCIE_PWR_MGMT_AUX_PM_EN_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) >> PCIE_PWR_MGMT_AUX_PM_EN_LSB) +#define PCIE_PWR_MGMT_AUX_PM_EN_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PM_EN_LSB) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) +#define PCIE_PWR_MGMT_AUX_PM_EN_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_READY_ENTR_L23_MSB 3 +#define PCIE_PWR_MGMT_READY_ENTR_L23_LSB 3 +#define PCIE_PWR_MGMT_READY_ENTR_L23_MASK 0x00000008 +#define PCIE_PWR_MGMT_READY_ENTR_L23_GET(x) (((x) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) >> PCIE_PWR_MGMT_READY_ENTR_L23_LSB) +#define PCIE_PWR_MGMT_READY_ENTR_L23_SET(x) (((x) << PCIE_PWR_MGMT_READY_ENTR_L23_LSB) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) +#define PCIE_PWR_MGMT_READY_ENTR_L23_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_REQ_EXIT_L1_MSB 2 +#define PCIE_PWR_MGMT_REQ_EXIT_L1_LSB 2 +#define PCIE_PWR_MGMT_REQ_EXIT_L1_MASK 0x00000004 +#define PCIE_PWR_MGMT_REQ_EXIT_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) >> PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) +#define PCIE_PWR_MGMT_REQ_EXIT_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) +#define PCIE_PWR_MGMT_REQ_EXIT_L1_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MSB 1 +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB 1 +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK 0x00000002 +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) >> PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) +#define PCIE_PWR_MGMT_REQ_ENTRY_L1_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_AUX_PWR_DET_MSB 0 +#define PCIE_PWR_MGMT_AUX_PWR_DET_LSB 0 +#define PCIE_PWR_MGMT_AUX_PWR_DET_MASK 0x00000001 +#define PCIE_PWR_MGMT_AUX_PWR_DET_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) >> PCIE_PWR_MGMT_AUX_PWR_DET_LSB) +#define PCIE_PWR_MGMT_AUX_PWR_DET_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PWR_DET_LSB) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) +#define PCIE_PWR_MGMT_AUX_PWR_DET_RESET 0x0 // 0 +#define PCIE_PWR_MGMT_ADDRESS 0x180f0008 +#define PCIE_PWR_MGMT_OFFSET 0x0008 +// SW modifiable bits +#define PCIE_PWR_MGMT_SW_MASK 0x000001ff +// bits defined at reset +#define PCIE_PWR_MGMT_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PCIE_PWR_MGMT_RESET 0x00000000 + +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MSB 31 +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB 31 +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK 0x80000000 +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK) >> PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB) +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK) +#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MSB 30 +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB 29 +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK 0x60000000 +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK) >> PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB) +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK) +#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_PERSTDELAY_MSB 28 +#define PCIE_PHY_REG_1_PERSTDELAY_LSB 27 +#define PCIE_PHY_REG_1_PERSTDELAY_MASK 0x18000000 +#define PCIE_PHY_REG_1_PERSTDELAY_GET(x) (((x) & PCIE_PHY_REG_1_PERSTDELAY_MASK) >> PCIE_PHY_REG_1_PERSTDELAY_LSB) +#define PCIE_PHY_REG_1_PERSTDELAY_SET(x) (((x) << PCIE_PHY_REG_1_PERSTDELAY_LSB) & PCIE_PHY_REG_1_PERSTDELAY_MASK) +#define PCIE_PHY_REG_1_PERSTDELAY_RESET 0x2 // 2 +#define PCIE_PHY_REG_1_CLKOBSSEL_MSB 26 +#define PCIE_PHY_REG_1_CLKOBSSEL_LSB 25 +#define PCIE_PHY_REG_1_CLKOBSSEL_MASK 0x06000000 +#define PCIE_PHY_REG_1_CLKOBSSEL_GET(x) (((x) & PCIE_PHY_REG_1_CLKOBSSEL_MASK) >> PCIE_PHY_REG_1_CLKOBSSEL_LSB) +#define PCIE_PHY_REG_1_CLKOBSSEL_SET(x) (((x) << PCIE_PHY_REG_1_CLKOBSSEL_LSB) & PCIE_PHY_REG_1_CLKOBSSEL_MASK) +#define PCIE_PHY_REG_1_CLKOBSSEL_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_DATAOBSEN_MSB 24 +#define PCIE_PHY_REG_1_DATAOBSEN_LSB 24 +#define PCIE_PHY_REG_1_DATAOBSEN_MASK 0x01000000 +#define PCIE_PHY_REG_1_DATAOBSEN_GET(x) (((x) & PCIE_PHY_REG_1_DATAOBSEN_MASK) >> PCIE_PHY_REG_1_DATAOBSEN_LSB) +#define PCIE_PHY_REG_1_DATAOBSEN_SET(x) (((x) << PCIE_PHY_REG_1_DATAOBSEN_LSB) & PCIE_PHY_REG_1_DATAOBSEN_MASK) +#define PCIE_PHY_REG_1_DATAOBSEN_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_FUNCTESTEN_MSB 23 +#define PCIE_PHY_REG_1_FUNCTESTEN_LSB 23 +#define PCIE_PHY_REG_1_FUNCTESTEN_MASK 0x00800000 +#define PCIE_PHY_REG_1_FUNCTESTEN_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTEN_MASK) >> PCIE_PHY_REG_1_FUNCTESTEN_LSB) +#define PCIE_PHY_REG_1_FUNCTESTEN_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTEN_LSB) & PCIE_PHY_REG_1_FUNCTESTEN_MASK) +#define PCIE_PHY_REG_1_FUNCTESTEN_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_DISABLE_MSB 22 +#define PCIE_PHY_REG_1_SERDES_DISABLE_LSB 22 +#define PCIE_PHY_REG_1_SERDES_DISABLE_MASK 0x00400000 +#define PCIE_PHY_REG_1_SERDES_DISABLE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK) >> PCIE_PHY_REG_1_SERDES_DISABLE_LSB) +#define PCIE_PHY_REG_1_SERDES_DISABLE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DISABLE_LSB) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK) +#define PCIE_PHY_REG_1_SERDES_DISABLE_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_RXCLKINV_MSB 21 +#define PCIE_PHY_REG_1_RXCLKINV_LSB 21 +#define PCIE_PHY_REG_1_RXCLKINV_MASK 0x00200000 +#define PCIE_PHY_REG_1_RXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_RXCLKINV_MASK) >> PCIE_PHY_REG_1_RXCLKINV_LSB) +#define PCIE_PHY_REG_1_RXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_RXCLKINV_LSB) & PCIE_PHY_REG_1_RXCLKINV_MASK) +#define PCIE_PHY_REG_1_RXCLKINV_RESET 0x1 // 1 +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MSB 20 +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB 20 +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK 0x00100000 +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB) +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK) +#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MSB 19 +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB 19 +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK 0x00080000 +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB) +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK) +#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_ENABLECLKREQ_MSB 18 +#define PCIE_PHY_REG_1_ENABLECLKREQ_LSB 18 +#define PCIE_PHY_REG_1_ENABLECLKREQ_MASK 0x00040000 +#define PCIE_PHY_REG_1_ENABLECLKREQ_GET(x) (((x) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK) >> PCIE_PHY_REG_1_ENABLECLKREQ_LSB) +#define PCIE_PHY_REG_1_ENABLECLKREQ_SET(x) (((x) << PCIE_PHY_REG_1_ENABLECLKREQ_LSB) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK) +#define PCIE_PHY_REG_1_ENABLECLKREQ_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_FORCELOOPBACK_MSB 17 +#define PCIE_PHY_REG_1_FORCELOOPBACK_LSB 17 +#define PCIE_PHY_REG_1_FORCELOOPBACK_MASK 0x00020000 +#define PCIE_PHY_REG_1_FORCELOOPBACK_GET(x) (((x) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK) >> PCIE_PHY_REG_1_FORCELOOPBACK_LSB) +#define PCIE_PHY_REG_1_FORCELOOPBACK_SET(x) (((x) << PCIE_PHY_REG_1_FORCELOOPBACK_LSB) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK) +#define PCIE_PHY_REG_1_FORCELOOPBACK_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SEL_CLK_MSB 16 +#define PCIE_PHY_REG_1_SEL_CLK_LSB 15 +#define PCIE_PHY_REG_1_SEL_CLK_MASK 0x00018000 +#define PCIE_PHY_REG_1_SEL_CLK_GET(x) (((x) & PCIE_PHY_REG_1_SEL_CLK_MASK) >> PCIE_PHY_REG_1_SEL_CLK_LSB) +#define PCIE_PHY_REG_1_SEL_CLK_SET(x) (((x) << PCIE_PHY_REG_1_SEL_CLK_LSB) & PCIE_PHY_REG_1_SEL_CLK_MASK) +#define PCIE_PHY_REG_1_SEL_CLK_RESET 0x2 // 2 +#define PCIE_PHY_REG_1_SERDES_RX_EQ_MSB 14 +#define PCIE_PHY_REG_1_SERDES_RX_EQ_LSB 14 +#define PCIE_PHY_REG_1_SERDES_RX_EQ_MASK 0x00004000 +#define PCIE_PHY_REG_1_SERDES_RX_EQ_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK) >> PCIE_PHY_REG_1_SERDES_RX_EQ_LSB) +#define PCIE_PHY_REG_1_SERDES_RX_EQ_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_RX_EQ_LSB) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK) +#define PCIE_PHY_REG_1_SERDES_RX_EQ_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MSB 13 +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB 13 +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK 0x00002000 +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK) >> PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB) +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK) +#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_RESET 0x1 // 1 +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MSB 12 +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB 12 +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK 0x00001000 +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) >> PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) +#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MSB 11 +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB 11 +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK 0x00000800 +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK) >> PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB) +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK) +#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_CDR_BW_MSB 10 +#define PCIE_PHY_REG_1_SERDES_CDR_BW_LSB 9 +#define PCIE_PHY_REG_1_SERDES_CDR_BW_MASK 0x00000600 +#define PCIE_PHY_REG_1_SERDES_CDR_BW_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK) >> PCIE_PHY_REG_1_SERDES_CDR_BW_LSB) +#define PCIE_PHY_REG_1_SERDES_CDR_BW_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_CDR_BW_LSB) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK) +#define PCIE_PHY_REG_1_SERDES_CDR_BW_RESET 0x3 // 3 +#define PCIE_PHY_REG_1_SERDES_TH_LOS_MSB 8 +#define PCIE_PHY_REG_1_SERDES_TH_LOS_LSB 7 +#define PCIE_PHY_REG_1_SERDES_TH_LOS_MASK 0x00000180 +#define PCIE_PHY_REG_1_SERDES_TH_LOS_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK) >> PCIE_PHY_REG_1_SERDES_TH_LOS_LSB) +#define PCIE_PHY_REG_1_SERDES_TH_LOS_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TH_LOS_LSB) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK) +#define PCIE_PHY_REG_1_SERDES_TH_LOS_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MSB 6 +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB 6 +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK 0x00000040 +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK) >> PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB) +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK) +#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_RESET 0x1 // 1 +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_MSB 5 +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB 5 +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK 0x00000020 +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK) >> PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB) +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK) +#define PCIE_PHY_REG_1_SERDES_HALFTXDR_RESET 0x0 // 0 +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_MSB 4 +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB 4 +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK 0x00000010 +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK) >> PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB) +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK) +#define PCIE_PHY_REG_1_SERDES_SEL_HSP_RESET 0x1 // 1 +#define PCIE_PHY_REG_1_S_MSB 3 +#define PCIE_PHY_REG_1_S_LSB 0 +#define PCIE_PHY_REG_1_S_MASK 0x0000000f +#define PCIE_PHY_REG_1_S_GET(x) (((x) & PCIE_PHY_REG_1_S_MASK) >> PCIE_PHY_REG_1_S_LSB) +#define PCIE_PHY_REG_1_S_SET(x) (((x) << PCIE_PHY_REG_1_S_LSB) & PCIE_PHY_REG_1_S_MASK) +#define PCIE_PHY_REG_1_S_RESET 0xe // 14 +#define PCIE_PHY_REG_1_ADDRESS 0x18116cc0 +#define PCIE_PHY_REG_1_OFFSET 0x0000 +// SW modifiable bits +#define PCIE_PHY_REG_1_SW_MASK 0xffffffff +// bits defined at reset +#define PCIE_PHY_REG_1_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PCIE_PHY_REG_1_RESET 0x1021265e +#define PCIE_PHY_REG_1_RESET_1 0x0061060e + +// 32'h18116cc4 (PCIE_PHY_REG_2) +#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MSB 31 +#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB 24 +#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK 0xff000000 +#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK) >> PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB) +#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB) & PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK) +#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_RESET 0x0 // 0 +#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MSB 23 +#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB 23 +#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK 0x00800000 +#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_GET(x) (((x) & PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK) >> PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB) +#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_SET(x) (((x) << PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB) & PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK) +#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_RESET 0x0 // 0 +#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MSB 22 +#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB 22 +#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK 0x00400000 +#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_GET(x) (((x) & PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK) >> PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB) +#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_SET(x) (((x) << PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB) & PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK) +#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_RESET 0x0 // 0 +#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_MSB 21 +#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB 21 +#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK 0x00200000 +#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK) >> PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB) +#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB) & PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK) +#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_RESET 0x0 // 0 +#define PCIE_PHY_REG_2_PRBS_START_MSB 20 +#define PCIE_PHY_REG_2_PRBS_START_LSB 20 +#define PCIE_PHY_REG_2_PRBS_START_MASK 0x00100000 +#define PCIE_PHY_REG_2_PRBS_START_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_START_MASK) >> PCIE_PHY_REG_2_PRBS_START_LSB) +#define PCIE_PHY_REG_2_PRBS_START_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_START_LSB) & PCIE_PHY_REG_2_PRBS_START_MASK) +#define PCIE_PHY_REG_2_PRBS_START_RESET 0x0 // 0 +#define PCIE_PHY_REG_2_PRBS_TS_NUM_MSB 19 +#define PCIE_PHY_REG_2_PRBS_TS_NUM_LSB 13 +#define PCIE_PHY_REG_2_PRBS_TS_NUM_MASK 0x000fe000 +#define PCIE_PHY_REG_2_PRBS_TS_NUM_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_TS_NUM_MASK) >> PCIE_PHY_REG_2_PRBS_TS_NUM_LSB) +#define PCIE_PHY_REG_2_PRBS_TS_NUM_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_TS_NUM_LSB) & PCIE_PHY_REG_2_PRBS_TS_NUM_MASK) +#define PCIE_PHY_REG_2_PRBS_TS_NUM_RESET 0x40 // 64 +#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_MSB 12 +#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB 12 +#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK 0x00001000 +#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK) >> PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB) +#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB) & PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK) +#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_RESET 0x0 // 0 +#define PCIE_PHY_REG_2_TXDETRXOVREN_MSB 11 +#define PCIE_PHY_REG_2_TXDETRXOVREN_LSB 11 +#define PCIE_PHY_REG_2_TXDETRXOVREN_MASK 0x00000800 +#define PCIE_PHY_REG_2_TXDETRXOVREN_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXOVREN_MASK) >> PCIE_PHY_REG_2_TXDETRXOVREN_LSB) +#define PCIE_PHY_REG_2_TXDETRXOVREN_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXOVREN_LSB) & PCIE_PHY_REG_2_TXDETRXOVREN_MASK) +#define PCIE_PHY_REG_2_TXDETRXOVREN_RESET 0x0 // 0 +#define PCIE_PHY_REG_2_DATAOBSPRBSERR_MSB 10 +#define PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB 10 +#define PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK 0x00000400 +#define PCIE_PHY_REG_2_DATAOBSPRBSERR_GET(x) (((x) & PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK) >> PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB) +#define PCIE_PHY_REG_2_DATAOBSPRBSERR_SET(x) (((x) << PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB) & PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK) +#define PCIE_PHY_REG_2_DATAOBSPRBSERR_RESET 0x0 // 0 +#define PCIE_PHY_REG_2_CDRREADYTIMER_MSB 9 +#define PCIE_PHY_REG_2_CDRREADYTIMER_LSB 6 +#define PCIE_PHY_REG_2_CDRREADYTIMER_MASK 0x000003c0 +#define PCIE_PHY_REG_2_CDRREADYTIMER_GET(x) (((x) & PCIE_PHY_REG_2_CDRREADYTIMER_MASK) >> PCIE_PHY_REG_2_CDRREADYTIMER_LSB) +#define PCIE_PHY_REG_2_CDRREADYTIMER_SET(x) (((x) << PCIE_PHY_REG_2_CDRREADYTIMER_LSB) & PCIE_PHY_REG_2_CDRREADYTIMER_MASK) +#define PCIE_PHY_REG_2_CDRREADYTIMER_RESET 0x7 // 7 +#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MSB 5 +#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB 1 +#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK 0x0000003e +#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK) >> PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB) +#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB) & PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK) +#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_RESET 0xc // 12 +#define PCIE_PHY_REG_2_FORCEDETECT_MSB 0 +#define PCIE_PHY_REG_2_FORCEDETECT_LSB 0 +#define PCIE_PHY_REG_2_FORCEDETECT_MASK 0x00000001 +#define PCIE_PHY_REG_2_FORCEDETECT_GET(x) (((x) & PCIE_PHY_REG_2_FORCEDETECT_MASK) >> PCIE_PHY_REG_2_FORCEDETECT_LSB) +#define PCIE_PHY_REG_2_FORCEDETECT_SET(x) (((x) << PCIE_PHY_REG_2_FORCEDETECT_LSB) & PCIE_PHY_REG_2_FORCEDETECT_MASK) +#define PCIE_PHY_REG_2_FORCEDETECT_RESET 0x0 // 0 +#define PCIE_PHY_REG_2_ADDRESS 0x18116cc4 +#define PCIE_PHY_REG_2_OFFSET 0x0004 +// SW modifiable bits +#define PCIE_PHY_REG_2_SW_MASK 0xffffffff +// bits defined at reset +#define PCIE_PHY_REG_2_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PCIE_PHY_REG_2_RESET 0x000801d8 + +#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MSB 31 +#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB 28 +#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK 0xf0000000 +#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_GET(x) (((x) & PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK) >> PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB) +#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_SET(x) (((x) << PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB) & PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK) +#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_RESET 0x0 // 0 +#define PCIE_PHY_REG_3_SPARE_MSB 27 +#define PCIE_PHY_REG_3_SPARE_LSB 11 +#define PCIE_PHY_REG_3_SPARE_MASK 0x0ffff800 +#define PCIE_PHY_REG_3_SPARE_GET(x) (((x) & PCIE_PHY_REG_3_SPARE_MASK) >> PCIE_PHY_REG_3_SPARE_LSB) +#define PCIE_PHY_REG_3_SPARE_SET(x) (((x) << PCIE_PHY_REG_3_SPARE_LSB) & PCIE_PHY_REG_3_SPARE_MASK) +#define PCIE_PHY_REG_3_SPARE_RESET 0xa0b // 2571 +#define PCIE_PHY_REG_3_SEL_CLK100_MSB 10 +#define PCIE_PHY_REG_3_SEL_CLK100_LSB 10 +#define PCIE_PHY_REG_3_SEL_CLK100_MASK 0x00000400 +#define PCIE_PHY_REG_3_SEL_CLK100_GET(x) (((x) & PCIE_PHY_REG_3_SEL_CLK100_MASK) >> PCIE_PHY_REG_3_SEL_CLK100_LSB) +#define PCIE_PHY_REG_3_SEL_CLK100_SET(x) (((x) << PCIE_PHY_REG_3_SEL_CLK100_LSB) & PCIE_PHY_REG_3_SEL_CLK100_MASK) +#define PCIE_PHY_REG_3_SEL_CLK100_RESET 0x0 // 0 +#define PCIE_PHY_REG_3_EN_BEACONGEN_MSB 9 +#define PCIE_PHY_REG_3_EN_BEACONGEN_LSB 9 +#define PCIE_PHY_REG_3_EN_BEACONGEN_MASK 0x00000200 +#define PCIE_PHY_REG_3_EN_BEACONGEN_GET(x) (((x) & PCIE_PHY_REG_3_EN_BEACONGEN_MASK) >> PCIE_PHY_REG_3_EN_BEACONGEN_LSB) +#define PCIE_PHY_REG_3_EN_BEACONGEN_SET(x) (((x) << PCIE_PHY_REG_3_EN_BEACONGEN_LSB) & PCIE_PHY_REG_3_EN_BEACONGEN_MASK) +#define PCIE_PHY_REG_3_EN_BEACONGEN_RESET 0x0 // 0 +#define PCIE_PHY_REG_3_TXELECIDLE_MSB 8 +#define PCIE_PHY_REG_3_TXELECIDLE_LSB 8 +#define PCIE_PHY_REG_3_TXELECIDLE_MASK 0x00000100 +#define PCIE_PHY_REG_3_TXELECIDLE_GET(x) (((x) & PCIE_PHY_REG_3_TXELECIDLE_MASK) >> PCIE_PHY_REG_3_TXELECIDLE_LSB) +#define PCIE_PHY_REG_3_TXELECIDLE_SET(x) (((x) << PCIE_PHY_REG_3_TXELECIDLE_LSB) & PCIE_PHY_REG_3_TXELECIDLE_MASK) +#define PCIE_PHY_REG_3_TXELECIDLE_RESET 0x0 // 0 +#define PCIE_PHY_REG_3_SEL_CLK_MSB 7 +#define PCIE_PHY_REG_3_SEL_CLK_LSB 6 +#define PCIE_PHY_REG_3_SEL_CLK_MASK 0x000000c0 +#define PCIE_PHY_REG_3_SEL_CLK_GET(x) (((x) & PCIE_PHY_REG_3_SEL_CLK_MASK) >> PCIE_PHY_REG_3_SEL_CLK_LSB) +#define PCIE_PHY_REG_3_SEL_CLK_SET(x) (((x) << PCIE_PHY_REG_3_SEL_CLK_LSB) & PCIE_PHY_REG_3_SEL_CLK_MASK) +#define PCIE_PHY_REG_3_SEL_CLK_RESET 0x0 // 0 +#define PCIE_PHY_REG_3_RX_DET_REQ_MSB 5 +#define PCIE_PHY_REG_3_RX_DET_REQ_LSB 5 +#define PCIE_PHY_REG_3_RX_DET_REQ_MASK 0x00000020 +#define PCIE_PHY_REG_3_RX_DET_REQ_GET(x) (((x) & PCIE_PHY_REG_3_RX_DET_REQ_MASK) >> PCIE_PHY_REG_3_RX_DET_REQ_LSB) +#define PCIE_PHY_REG_3_RX_DET_REQ_SET(x) (((x) << PCIE_PHY_REG_3_RX_DET_REQ_LSB) & PCIE_PHY_REG_3_RX_DET_REQ_MASK) +#define PCIE_PHY_REG_3_RX_DET_REQ_RESET 0x0 // 0 +#define PCIE_PHY_REG_3_MODE_OCLK_IN_MSB 4 +#define PCIE_PHY_REG_3_MODE_OCLK_IN_LSB 4 +#define PCIE_PHY_REG_3_MODE_OCLK_IN_MASK 0x00000010 +#define PCIE_PHY_REG_3_MODE_OCLK_IN_GET(x) (((x) & PCIE_PHY_REG_3_MODE_OCLK_IN_MASK) >> PCIE_PHY_REG_3_MODE_OCLK_IN_LSB) +#define PCIE_PHY_REG_3_MODE_OCLK_IN_SET(x) (((x) << PCIE_PHY_REG_3_MODE_OCLK_IN_LSB) & PCIE_PHY_REG_3_MODE_OCLK_IN_MASK) +#define PCIE_PHY_REG_3_MODE_OCLK_IN_RESET 0x0 // 0 +#define PCIE_PHY_REG_3_EN_PLL_MSB 3 +#define PCIE_PHY_REG_3_EN_PLL_LSB 3 +#define PCIE_PHY_REG_3_EN_PLL_MASK 0x00000008 +#define PCIE_PHY_REG_3_EN_PLL_GET(x) (((x) & PCIE_PHY_REG_3_EN_PLL_MASK) >> PCIE_PHY_REG_3_EN_PLL_LSB) +#define PCIE_PHY_REG_3_EN_PLL_SET(x) (((x) << PCIE_PHY_REG_3_EN_PLL_LSB) & PCIE_PHY_REG_3_EN_PLL_MASK) +#define PCIE_PHY_REG_3_EN_PLL_RESET 0x1 // 1 +#define PCIE_PHY_REG_3_EN_LCKDT_MSB 2 +#define PCIE_PHY_REG_3_EN_LCKDT_LSB 2 +#define PCIE_PHY_REG_3_EN_LCKDT_MASK 0x00000004 +#define PCIE_PHY_REG_3_EN_LCKDT_GET(x) (((x) & PCIE_PHY_REG_3_EN_LCKDT_MASK) >> PCIE_PHY_REG_3_EN_LCKDT_LSB) +#define PCIE_PHY_REG_3_EN_LCKDT_SET(x) (((x) << PCIE_PHY_REG_3_EN_LCKDT_LSB) & PCIE_PHY_REG_3_EN_LCKDT_MASK) +#define PCIE_PHY_REG_3_EN_LCKDT_RESET 0x1 // 1 +#define PCIE_PHY_REG_3_EN_BUFS_RX_MSB 1 +#define PCIE_PHY_REG_3_EN_BUFS_RX_LSB 1 +#define PCIE_PHY_REG_3_EN_BUFS_RX_MASK 0x00000002 +#define PCIE_PHY_REG_3_EN_BUFS_RX_GET(x) (((x) & PCIE_PHY_REG_3_EN_BUFS_RX_MASK) >> PCIE_PHY_REG_3_EN_BUFS_RX_LSB) +#define PCIE_PHY_REG_3_EN_BUFS_RX_SET(x) (((x) << PCIE_PHY_REG_3_EN_BUFS_RX_LSB) & PCIE_PHY_REG_3_EN_BUFS_RX_MASK) +#define PCIE_PHY_REG_3_EN_BUFS_RX_RESET 0x0 // 0 +#define PCIE_PHY_REG_3_EN_MSB 0 +#define PCIE_PHY_REG_3_EN_LSB 0 +#define PCIE_PHY_REG_3_EN_MASK 0x00000001 +#define PCIE_PHY_REG_3_EN_GET(x) (((x) & PCIE_PHY_REG_3_EN_MASK) >> PCIE_PHY_REG_3_EN_LSB) +#define PCIE_PHY_REG_3_EN_SET(x) (((x) << PCIE_PHY_REG_3_EN_LSB) & PCIE_PHY_REG_3_EN_MASK) +#define PCIE_PHY_REG_3_EN_RESET 0x0 // 0 +#define PCIE_PHY_REG_3_ADDRESS 0x18116cc8 +#define PCIE_PHY_REG_3_OFFSET 0x0008 +// SW modifiable bits +#define PCIE_PHY_REG_3_SW_MASK 0xffffffff +// bits defined at reset +#define PCIE_PHY_REG_3_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PCIE_PHY_REG_3_RESET 0x0050580c +#define PCIE_PHY_REG_3_RESET_1 0x00505900 + +#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_MSB 31 +#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB 11 +#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK 0xfffff800 +#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK) >> PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB) +#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB) & PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK) +#define PCIE_PHY_REG_4_PRBS_ERROR_RATE_RESET 0xa000 // 40960 +#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MSB 10 +#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB 1 +#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK 0x000007fe +#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK) >> PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB) +#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB) & PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK) +#define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_RESET 0x0 // 0 +#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MSB 0 +#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB 0 +#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK 0x00000001 +#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK) >> PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB) +#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB) & PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK) +#define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_RESET 0x0 // 0 +#define PCIE_PHY_REG_4_ADDRESS 0x18116ccc +#define PCIE_PHY_REG_4_OFFSET 0x000c +// SW modifiable bits +#define PCIE_PHY_REG_4_SW_MASK 0xffffffff +// bits defined at reset +#define PCIE_PHY_REG_4_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define PCIE_PHY_REG_4_RESET 0x05000000 + +#define XTAL_TCXODET_MSB 31 +#define XTAL_TCXODET_LSB 31 +#define XTAL_TCXODET_MASK 0x80000000 +#define XTAL_TCXODET_GET(x) (((x) & XTAL_TCXODET_MASK) >> XTAL_TCXODET_LSB) +#define XTAL_TCXODET_SET(x) (((x) << XTAL_TCXODET_LSB) & XTAL_TCXODET_MASK) +#define XTAL_TCXODET_RESET 0x0 // 0 +#define XTAL_XTAL_CAPINDAC_MSB 30 +#define XTAL_XTAL_CAPINDAC_LSB 24 +#define XTAL_XTAL_CAPINDAC_MASK 0x7f000000 +#define XTAL_XTAL_CAPINDAC_GET(x) (((x) & XTAL_XTAL_CAPINDAC_MASK) >> XTAL_XTAL_CAPINDAC_LSB) +#define XTAL_XTAL_CAPINDAC_SET(x) (((x) << XTAL_XTAL_CAPINDAC_LSB) & XTAL_XTAL_CAPINDAC_MASK) +#define XTAL_XTAL_CAPINDAC_RESET 0x4b // 75 +#define XTAL_XTAL_CAPOUTDAC_MSB 23 +#define XTAL_XTAL_CAPOUTDAC_LSB 17 +#define XTAL_XTAL_CAPOUTDAC_MASK 0x00fe0000 +#define XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & XTAL_XTAL_CAPOUTDAC_MASK) >> XTAL_XTAL_CAPOUTDAC_LSB) +#define XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << XTAL_XTAL_CAPOUTDAC_LSB) & XTAL_XTAL_CAPOUTDAC_MASK) +#define XTAL_XTAL_CAPOUTDAC_RESET 0x4b // 75 +#define XTAL_XTAL_DRVSTR_MSB 16 +#define XTAL_XTAL_DRVSTR_LSB 15 +#define XTAL_XTAL_DRVSTR_MASK 0x00018000 +#define XTAL_XTAL_DRVSTR_GET(x) (((x) & XTAL_XTAL_DRVSTR_MASK) >> XTAL_XTAL_DRVSTR_LSB) +#define XTAL_XTAL_DRVSTR_SET(x) (((x) << XTAL_XTAL_DRVSTR_LSB) & XTAL_XTAL_DRVSTR_MASK) +#define XTAL_XTAL_DRVSTR_RESET 0x0 // 0 +#define XTAL_XTAL_SHORTXIN_MSB 14 +#define XTAL_XTAL_SHORTXIN_LSB 14 +#define XTAL_XTAL_SHORTXIN_MASK 0x00004000 +#define XTAL_XTAL_SHORTXIN_GET(x) (((x) & XTAL_XTAL_SHORTXIN_MASK) >> XTAL_XTAL_SHORTXIN_LSB) +#define XTAL_XTAL_SHORTXIN_SET(x) (((x) << XTAL_XTAL_SHORTXIN_LSB) & XTAL_XTAL_SHORTXIN_MASK) +#define XTAL_XTAL_SHORTXIN_RESET 0x0 // 0 +#define XTAL_XTAL_LOCALBIAS_MSB 13 +#define XTAL_XTAL_LOCALBIAS_LSB 13 +#define XTAL_XTAL_LOCALBIAS_MASK 0x00002000 +#define XTAL_XTAL_LOCALBIAS_GET(x) (((x) & XTAL_XTAL_LOCALBIAS_MASK) >> XTAL_XTAL_LOCALBIAS_LSB) +#define XTAL_XTAL_LOCALBIAS_SET(x) (((x) << XTAL_XTAL_LOCALBIAS_LSB) & XTAL_XTAL_LOCALBIAS_MASK) +#define XTAL_XTAL_LOCALBIAS_RESET 0x1 // 1 +#define XTAL_XTAL_PWDCLKD_MSB 12 +#define XTAL_XTAL_PWDCLKD_LSB 12 +#define XTAL_XTAL_PWDCLKD_MASK 0x00001000 +#define XTAL_XTAL_PWDCLKD_GET(x) (((x) & XTAL_XTAL_PWDCLKD_MASK) >> XTAL_XTAL_PWDCLKD_LSB) +#define XTAL_XTAL_PWDCLKD_SET(x) (((x) << XTAL_XTAL_PWDCLKD_LSB) & XTAL_XTAL_PWDCLKD_MASK) +#define XTAL_XTAL_PWDCLKD_RESET 0x0 // 0 +#define XTAL_XTAL_BIAS2X_MSB 11 +#define XTAL_XTAL_BIAS2X_LSB 11 +#define XTAL_XTAL_BIAS2X_MASK 0x00000800 +#define XTAL_XTAL_BIAS2X_GET(x) (((x) & XTAL_XTAL_BIAS2X_MASK) >> XTAL_XTAL_BIAS2X_LSB) +#define XTAL_XTAL_BIAS2X_SET(x) (((x) << XTAL_XTAL_BIAS2X_LSB) & XTAL_XTAL_BIAS2X_MASK) +#define XTAL_XTAL_BIAS2X_RESET 0x0 // 0 +#define XTAL_XTAL_LBIAS2X_MSB 10 +#define XTAL_XTAL_LBIAS2X_LSB 10 +#define XTAL_XTAL_LBIAS2X_MASK 0x00000400 +#define XTAL_XTAL_LBIAS2X_GET(x) (((x) & XTAL_XTAL_LBIAS2X_MASK) >> XTAL_XTAL_LBIAS2X_LSB) +#define XTAL_XTAL_LBIAS2X_SET(x) (((x) << XTAL_XTAL_LBIAS2X_LSB) & XTAL_XTAL_LBIAS2X_MASK) +#define XTAL_XTAL_LBIAS2X_RESET 0x0 // 0 +#define XTAL_XTAL_SELVREG_MSB 9 +#define XTAL_XTAL_SELVREG_LSB 9 +#define XTAL_XTAL_SELVREG_MASK 0x00000200 +#define XTAL_XTAL_SELVREG_GET(x) (((x) & XTAL_XTAL_SELVREG_MASK) >> XTAL_XTAL_SELVREG_LSB) +#define XTAL_XTAL_SELVREG_SET(x) (((x) << XTAL_XTAL_SELVREG_LSB) & XTAL_XTAL_SELVREG_MASK) +#define XTAL_XTAL_SELVREG_RESET 0x0 // 0 +#define XTAL_XTAL_OSCON_MSB 8 +#define XTAL_XTAL_OSCON_LSB 8 +#define XTAL_XTAL_OSCON_MASK 0x00000100 +#define XTAL_XTAL_OSCON_GET(x) (((x) & XTAL_XTAL_OSCON_MASK) >> XTAL_XTAL_OSCON_LSB) +#define XTAL_XTAL_OSCON_SET(x) (((x) << XTAL_XTAL_OSCON_LSB) & XTAL_XTAL_OSCON_MASK) +#define XTAL_XTAL_OSCON_RESET 0x1 // 1 +#define XTAL_XTAL_PWDCLKIN_MSB 7 +#define XTAL_XTAL_PWDCLKIN_LSB 7 +#define XTAL_XTAL_PWDCLKIN_MASK 0x00000080 +#define XTAL_XTAL_PWDCLKIN_GET(x) (((x) & XTAL_XTAL_PWDCLKIN_MASK) >> XTAL_XTAL_PWDCLKIN_LSB) +#define XTAL_XTAL_PWDCLKIN_SET(x) (((x) << XTAL_XTAL_PWDCLKIN_LSB) & XTAL_XTAL_PWDCLKIN_MASK) +#define XTAL_XTAL_PWDCLKIN_RESET 0x0 // 0 +#define XTAL_LOCAL_XTAL_MSB 6 +#define XTAL_LOCAL_XTAL_LSB 6 +#define XTAL_LOCAL_XTAL_MASK 0x00000040 +#define XTAL_LOCAL_XTAL_GET(x) (((x) & XTAL_LOCAL_XTAL_MASK) >> XTAL_LOCAL_XTAL_LSB) +#define XTAL_LOCAL_XTAL_SET(x) (((x) << XTAL_LOCAL_XTAL_LSB) & XTAL_LOCAL_XTAL_MASK) +#define XTAL_LOCAL_XTAL_RESET 0x0 // 0 +#define XTAL_PWD_SWREGCLK_MSB 5 +#define XTAL_PWD_SWREGCLK_LSB 5 +#define XTAL_PWD_SWREGCLK_MASK 0x00000020 +#define XTAL_PWD_SWREGCLK_GET(x) (((x) & XTAL_PWD_SWREGCLK_MASK) >> XTAL_PWD_SWREGCLK_LSB) +#define XTAL_PWD_SWREGCLK_SET(x) (((x) << XTAL_PWD_SWREGCLK_LSB) & XTAL_PWD_SWREGCLK_MASK) +#define XTAL_PWD_SWREGCLK_RESET 0x0 // 0 +#define XTAL_LOCAL_EXT_CLK_OUT_EN_MSB 4 +#define XTAL_LOCAL_EXT_CLK_OUT_EN_LSB 4 +#define XTAL_LOCAL_EXT_CLK_OUT_EN_MASK 0x00000010 +#define XTAL_LOCAL_EXT_CLK_OUT_EN_GET(x) (((x) & XTAL_LOCAL_EXT_CLK_OUT_EN_MASK) >> XTAL_LOCAL_EXT_CLK_OUT_EN_LSB) +#define XTAL_LOCAL_EXT_CLK_OUT_EN_SET(x) (((x) << XTAL_LOCAL_EXT_CLK_OUT_EN_LSB) & XTAL_LOCAL_EXT_CLK_OUT_EN_MASK) +#define XTAL_LOCAL_EXT_CLK_OUT_EN_RESET 0x0 // 0 +#define XTAL_EXT_CLK_OUT_EN_MSB 3 +#define XTAL_EXT_CLK_OUT_EN_LSB 3 +#define XTAL_EXT_CLK_OUT_EN_MASK 0x00000008 +#define XTAL_EXT_CLK_OUT_EN_GET(x) (((x) & XTAL_EXT_CLK_OUT_EN_MASK) >> XTAL_EXT_CLK_OUT_EN_LSB) +#define XTAL_EXT_CLK_OUT_EN_SET(x) (((x) << XTAL_EXT_CLK_OUT_EN_LSB) & XTAL_EXT_CLK_OUT_EN_MASK) +#define XTAL_EXT_CLK_OUT_EN_RESET 0x0 // 0 +#define XTAL_XTAL_SVREG_MSB 2 +#define XTAL_XTAL_SVREG_LSB 2 +#define XTAL_XTAL_SVREG_MASK 0x00000004 +#define XTAL_XTAL_SVREG_GET(x) (((x) & XTAL_XTAL_SVREG_MASK) >> XTAL_XTAL_SVREG_LSB) +#define XTAL_XTAL_SVREG_SET(x) (((x) << XTAL_XTAL_SVREG_LSB) & XTAL_XTAL_SVREG_MASK) +#define XTAL_XTAL_SVREG_RESET 0x0 // 0 +#define XTAL_RBK_UDSEL_MSB 1 +#define XTAL_RBK_UDSEL_LSB 1 +#define XTAL_RBK_UDSEL_MASK 0x00000002 +#define XTAL_RBK_UDSEL_GET(x) (((x) & XTAL_RBK_UDSEL_MASK) >> XTAL_RBK_UDSEL_LSB) +#define XTAL_RBK_UDSEL_SET(x) (((x) << XTAL_RBK_UDSEL_LSB) & XTAL_RBK_UDSEL_MASK) +#define XTAL_RBK_UDSEL_RESET 0x0 // 0 +#define XTAL_SPARE_MSB 0 +#define XTAL_SPARE_LSB 0 +#define XTAL_SPARE_MASK 0x00000001 +#define XTAL_SPARE_GET(x) (((x) & XTAL_SPARE_MASK) >> XTAL_SPARE_LSB) +#define XTAL_SPARE_SET(x) (((x) << XTAL_SPARE_LSB) & XTAL_SPARE_MASK) +#define XTAL_SPARE_RESET 0x0 // 0 +#define XTAL_ADDRESS 0x181162c0 + +#define XTAL2_TDC_COUNT_MSB 31 +#define XTAL2_TDC_COUNT_LSB 26 +#define XTAL2_TDC_COUNT_MASK 0xfc000000 +#define XTAL2_TDC_COUNT_GET(x) (((x) & XTAL2_TDC_COUNT_MASK) >> XTAL2_TDC_COUNT_LSB) +#define XTAL2_TDC_COUNT_SET(x) (((x) << XTAL2_TDC_COUNT_LSB) & XTAL2_TDC_COUNT_MASK) +#define XTAL2_TDC_COUNT_RESET 0x0 // 0 +#define XTAL2_TDC_PH_COUNT_MSB 25 +#define XTAL2_TDC_PH_COUNT_LSB 21 +#define XTAL2_TDC_PH_COUNT_MASK 0x03e00000 +#define XTAL2_TDC_PH_COUNT_GET(x) (((x) & XTAL2_TDC_PH_COUNT_MASK) >> XTAL2_TDC_PH_COUNT_LSB) +#define XTAL2_TDC_PH_COUNT_SET(x) (((x) << XTAL2_TDC_PH_COUNT_LSB) & XTAL2_TDC_PH_COUNT_MASK) +#define XTAL2_TDC_PH_COUNT_RESET 0x0 // 0 +#define XTAL2_DUTY_UP_MSB 20 +#define XTAL2_DUTY_UP_LSB 16 +#define XTAL2_DUTY_UP_MASK 0x001f0000 +#define XTAL2_DUTY_UP_GET(x) (((x) & XTAL2_DUTY_UP_MASK) >> XTAL2_DUTY_UP_LSB) +#define XTAL2_DUTY_UP_SET(x) (((x) << XTAL2_DUTY_UP_LSB) & XTAL2_DUTY_UP_MASK) +#define XTAL2_DUTY_UP_RESET 0x0 // 0 +#define XTAL2_DUTY_DN_MSB 15 +#define XTAL2_DUTY_DN_LSB 11 +#define XTAL2_DUTY_DN_MASK 0x0000f800 +#define XTAL2_DUTY_DN_GET(x) (((x) & XTAL2_DUTY_DN_MASK) >> XTAL2_DUTY_DN_LSB) +#define XTAL2_DUTY_DN_SET(x) (((x) << XTAL2_DUTY_DN_LSB) & XTAL2_DUTY_DN_MASK) +#define XTAL2_DUTY_DN_RESET 0x0 // 0 +#define XTAL2_DCA_BYPASS_MSB 10 +#define XTAL2_DCA_BYPASS_LSB 10 +#define XTAL2_DCA_BYPASS_MASK 0x00000400 +#define XTAL2_DCA_BYPASS_GET(x) (((x) & XTAL2_DCA_BYPASS_MASK) >> XTAL2_DCA_BYPASS_LSB) +#define XTAL2_DCA_BYPASS_SET(x) (((x) << XTAL2_DCA_BYPASS_LSB) & XTAL2_DCA_BYPASS_MASK) +#define XTAL2_DCA_BYPASS_RESET 0x1 // 1 +#define XTAL2_DCA_SWCAL_MSB 9 +#define XTAL2_DCA_SWCAL_LSB 9 +#define XTAL2_DCA_SWCAL_MASK 0x00000200 +#define XTAL2_DCA_SWCAL_GET(x) (((x) & XTAL2_DCA_SWCAL_MASK) >> XTAL2_DCA_SWCAL_LSB) +#define XTAL2_DCA_SWCAL_SET(x) (((x) << XTAL2_DCA_SWCAL_LSB) & XTAL2_DCA_SWCAL_MASK) +#define XTAL2_DCA_SWCAL_RESET 0x0 // 0 +#define XTAL2_FSM_UD_HOLD_MSB 8 +#define XTAL2_FSM_UD_HOLD_LSB 8 +#define XTAL2_FSM_UD_HOLD_MASK 0x00000100 +#define XTAL2_FSM_UD_HOLD_GET(x) (((x) & XTAL2_FSM_UD_HOLD_MASK) >> XTAL2_FSM_UD_HOLD_LSB) +#define XTAL2_FSM_UD_HOLD_SET(x) (((x) << XTAL2_FSM_UD_HOLD_LSB) & XTAL2_FSM_UD_HOLD_MASK) +#define XTAL2_FSM_UD_HOLD_RESET 0x0 // 0 +#define XTAL2_FSM_START_L_MSB 7 +#define XTAL2_FSM_START_L_LSB 7 +#define XTAL2_FSM_START_L_MASK 0x00000080 +#define XTAL2_FSM_START_L_GET(x) (((x) & XTAL2_FSM_START_L_MASK) >> XTAL2_FSM_START_L_LSB) +#define XTAL2_FSM_START_L_SET(x) (((x) << XTAL2_FSM_START_L_LSB) & XTAL2_FSM_START_L_MASK) +#define XTAL2_FSM_START_L_RESET 0x1 // 1 +#define XTAL2_FSM_DN_READBACK_MSB 6 +#define XTAL2_FSM_DN_READBACK_LSB 2 +#define XTAL2_FSM_DN_READBACK_MASK 0x0000007c +#define XTAL2_FSM_DN_READBACK_GET(x) (((x) & XTAL2_FSM_DN_READBACK_MASK) >> XTAL2_FSM_DN_READBACK_LSB) +#define XTAL2_FSM_DN_READBACK_SET(x) (((x) << XTAL2_FSM_DN_READBACK_LSB) & XTAL2_FSM_DN_READBACK_MASK) +#define XTAL2_FSM_DN_READBACK_RESET 0x0 // 0 +#define XTAL2_TDC_SAT_FLAG_MSB 1 +#define XTAL2_TDC_SAT_FLAG_LSB 1 +#define XTAL2_TDC_SAT_FLAG_MASK 0x00000002 +#define XTAL2_TDC_SAT_FLAG_GET(x) (((x) & XTAL2_TDC_SAT_FLAG_MASK) >> XTAL2_TDC_SAT_FLAG_LSB) +#define XTAL2_TDC_SAT_FLAG_SET(x) (((x) << XTAL2_TDC_SAT_FLAG_LSB) & XTAL2_TDC_SAT_FLAG_MASK) +#define XTAL2_TDC_SAT_FLAG_RESET 0x0 // 0 +#define XTAL2_FSM_READY_MSB 0 +#define XTAL2_FSM_READY_LSB 0 +#define XTAL2_FSM_READY_MASK 0x00000001 +#define XTAL2_FSM_READY_GET(x) (((x) & XTAL2_FSM_READY_MASK) >> XTAL2_FSM_READY_LSB) +#define XTAL2_FSM_READY_SET(x) (((x) << XTAL2_FSM_READY_LSB) & XTAL2_FSM_READY_MASK) +#define XTAL2_FSM_READY_RESET 0x0 // 0 +#define XTAL2_ADDRESS 0x181162c4 + +#define XTAL3_FSM_UP_READBACK_MSB 31 +#define XTAL3_FSM_UP_READBACK_LSB 27 +#define XTAL3_FSM_UP_READBACK_MASK 0xf8000000 +#define XTAL3_FSM_UP_READBACK_GET(x) (((x) & XTAL3_FSM_UP_READBACK_MASK) >> XTAL3_FSM_UP_READBACK_LSB) +#define XTAL3_FSM_UP_READBACK_SET(x) (((x) << XTAL3_FSM_UP_READBACK_LSB) & XTAL3_FSM_UP_READBACK_MASK) +#define XTAL3_FSM_UP_READBACK_RESET 0x0 // 0 +#define XTAL3_EVAL_LENGTH_MSB 26 +#define XTAL3_EVAL_LENGTH_LSB 16 +#define XTAL3_EVAL_LENGTH_MASK 0x07ff0000 +#define XTAL3_EVAL_LENGTH_GET(x) (((x) & XTAL3_EVAL_LENGTH_MASK) >> XTAL3_EVAL_LENGTH_LSB) +#define XTAL3_EVAL_LENGTH_SET(x) (((x) << XTAL3_EVAL_LENGTH_LSB) & XTAL3_EVAL_LENGTH_MASK) +#define XTAL3_EVAL_LENGTH_RESET 0x400 // 1024 +#define XTAL3_TDC_ERROR_FLAG_MSB 15 +#define XTAL3_TDC_ERROR_FLAG_LSB 15 +#define XTAL3_TDC_ERROR_FLAG_MASK 0x00008000 +#define XTAL3_TDC_ERROR_FLAG_GET(x) (((x) & XTAL3_TDC_ERROR_FLAG_MASK) >> XTAL3_TDC_ERROR_FLAG_LSB) +#define XTAL3_TDC_ERROR_FLAG_SET(x) (((x) << XTAL3_TDC_ERROR_FLAG_LSB) & XTAL3_TDC_ERROR_FLAG_MASK) +#define XTAL3_TDC_ERROR_FLAG_RESET 0x0 // 0 +#define XTAL3_HARMONIC_NUMBER_MSB 14 +#define XTAL3_HARMONIC_NUMBER_LSB 2 +#define XTAL3_HARMONIC_NUMBER_MASK 0x00007ffc +#define XTAL3_HARMONIC_NUMBER_GET(x) (((x) & XTAL3_HARMONIC_NUMBER_MASK) >> XTAL3_HARMONIC_NUMBER_LSB) +#define XTAL3_HARMONIC_NUMBER_SET(x) (((x) << XTAL3_HARMONIC_NUMBER_LSB) & XTAL3_HARMONIC_NUMBER_MASK) +#define XTAL3_HARMONIC_NUMBER_RESET 0x51 // 81 +#define XTAL3_SPARE_MSB 1 +#define XTAL3_SPARE_LSB 0 +#define XTAL3_SPARE_MASK 0x00000003 +#define XTAL3_SPARE_GET(x) (((x) & XTAL3_SPARE_MASK) >> XTAL3_SPARE_LSB) +#define XTAL3_SPARE_SET(x) (((x) << XTAL3_SPARE_LSB) & XTAL3_SPARE_MASK) +#define XTAL3_SPARE_RESET 0x0 // 0 +#define XTAL3_ADDRESS 0x181162c8 + +#define RST_REVISION_ID_ADDRESS 0x18060090 +#define is_drqfn() (!(ath_reg_rd(RST_REVISION_ID_ADDRESS) & 0x1000)) + +#define RST_BOOTSTRAP_RES4_MSB 15 +#define RST_BOOTSTRAP_RES4_LSB 13 +#define RST_BOOTSTRAP_RES4_MASK 0x0000e000 +#define RST_BOOTSTRAP_RES4_GET(x) (((x) & RST_BOOTSTRAP_RES4_MASK) >> RST_BOOTSTRAP_RES4_LSB) +#define RST_BOOTSTRAP_RES4_SET(x) (((x) << RST_BOOTSTRAP_RES4_LSB) & RST_BOOTSTRAP_RES4_MASK) +#define RST_BOOTSTRAP_RES4_RESET 0x0 // 0 +#define RST_BOOTSTRAP_SW_OPTION2_MSB 12 +#define RST_BOOTSTRAP_SW_OPTION2_LSB 12 +#define RST_BOOTSTRAP_SW_OPTION2_MASK 0x00001000 +#define RST_BOOTSTRAP_SW_OPTION2_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION2_MASK) >> RST_BOOTSTRAP_SW_OPTION2_LSB) +#define RST_BOOTSTRAP_SW_OPTION2_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION2_LSB) & RST_BOOTSTRAP_SW_OPTION2_MASK) +#define RST_BOOTSTRAP_SW_OPTION2_RESET 0x0 // 0 +#define RST_BOOTSTRAP_SW_OPTION1_MSB 11 +#define RST_BOOTSTRAP_SW_OPTION1_LSB 11 +#define RST_BOOTSTRAP_SW_OPTION1_MASK 0x00000800 +#define RST_BOOTSTRAP_SW_OPTION1_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION1_MASK) >> RST_BOOTSTRAP_SW_OPTION1_LSB) +#define RST_BOOTSTRAP_SW_OPTION1_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION1_LSB) & RST_BOOTSTRAP_SW_OPTION1_MASK) +#define RST_BOOTSTRAP_SW_OPTION1_RESET 0x0 // 0 +#define RST_BOOTSTRAP_TESTROM_ENABLE_MSB 10 +#define RST_BOOTSTRAP_TESTROM_ENABLE_LSB 10 +#define RST_BOOTSTRAP_TESTROM_ENABLE_MASK 0x00000400 +#define RST_BOOTSTRAP_TESTROM_ENABLE_GET(x) (((x) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) >> RST_BOOTSTRAP_TESTROM_ENABLE_LSB) +#define RST_BOOTSTRAP_TESTROM_ENABLE_SET(x) (((x) << RST_BOOTSTRAP_TESTROM_ENABLE_LSB) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) +#define RST_BOOTSTRAP_TESTROM_ENABLE_RESET 0x0 // 0 +#define RST_BOOTSTRAP_RES3_MSB 9 +#define RST_BOOTSTRAP_RES3_LSB 9 +#define RST_BOOTSTRAP_RES3_MASK 0x00000200 +#define RST_BOOTSTRAP_RES3_GET(x) (((x) & RST_BOOTSTRAP_RES3_MASK) >> RST_BOOTSTRAP_RES3_LSB) +#define RST_BOOTSTRAP_RES3_SET(x) (((x) << RST_BOOTSTRAP_RES3_LSB) & RST_BOOTSTRAP_RES3_MASK) +#define RST_BOOTSTRAP_RES3_RESET 0x0 // 0 +#define RST_BOOTSTRAP_SRIF_ENABLE_MSB 8 +#define RST_BOOTSTRAP_SRIF_ENABLE_LSB 8 +#define RST_BOOTSTRAP_SRIF_ENABLE_MASK 0x00000100 +#define RST_BOOTSTRAP_SRIF_ENABLE_GET(x) (((x) & RST_BOOTSTRAP_SRIF_ENABLE_MASK) >> RST_BOOTSTRAP_SRIF_ENABLE_LSB) +#define RST_BOOTSTRAP_SRIF_ENABLE_SET(x) (((x) << RST_BOOTSTRAP_SRIF_ENABLE_LSB) & RST_BOOTSTRAP_SRIF_ENABLE_MASK) +#define RST_BOOTSTRAP_SRIF_ENABLE_RESET 0x0 // 0 +#define RST_BOOTSTRAP_USB_MODE_MSB 7 +#define RST_BOOTSTRAP_USB_MODE_LSB 7 +#define RST_BOOTSTRAP_USB_MODE_MASK 0x00000080 +#define RST_BOOTSTRAP_USB_MODE_GET(x) (((x) & RST_BOOTSTRAP_USB_MODE_MASK) >> RST_BOOTSTRAP_USB_MODE_LSB) +#define RST_BOOTSTRAP_USB_MODE_SET(x) (((x) << RST_BOOTSTRAP_USB_MODE_LSB) & RST_BOOTSTRAP_USB_MODE_MASK) +#define RST_BOOTSTRAP_USB_MODE_RESET 0x0 // 0 +#define RST_BOOTSTRAP_RES2_MSB 6 +#define RST_BOOTSTRAP_RES2_LSB 6 +#define RST_BOOTSTRAP_RES2_MASK 0x00000040 +#define RST_BOOTSTRAP_RES2_GET(x) (((x) & RST_BOOTSTRAP_RES2_MASK) >> RST_BOOTSTRAP_RES2_LSB) +#define RST_BOOTSTRAP_RES2_SET(x) (((x) << RST_BOOTSTRAP_RES2_LSB) & RST_BOOTSTRAP_RES2_MASK) +#define RST_BOOTSTRAP_RES2_RESET 0x0 // 0 +#define RST_BOOTSTRAP_EJTAG_MODE_MSB 5 +#define RST_BOOTSTRAP_EJTAG_MODE_LSB 5 +#define RST_BOOTSTRAP_EJTAG_MODE_MASK 0x00000020 +#define RST_BOOTSTRAP_EJTAG_MODE_GET(x) (((x) & RST_BOOTSTRAP_EJTAG_MODE_MASK) >> RST_BOOTSTRAP_EJTAG_MODE_LSB) +#define RST_BOOTSTRAP_EJTAG_MODE_SET(x) (((x) << RST_BOOTSTRAP_EJTAG_MODE_LSB) & RST_BOOTSTRAP_EJTAG_MODE_MASK) +#define RST_BOOTSTRAP_EJTAG_MODE_RESET 0x0 // 0 +#define RST_BOOTSTRAP_REF_CLK_MSB 4 +#define RST_BOOTSTRAP_REF_CLK_LSB 4 +#define RST_BOOTSTRAP_REF_CLK_MASK 0x00000010 +#define RST_BOOTSTRAP_REF_CLK_GET(x) (((x) & RST_BOOTSTRAP_REF_CLK_MASK) >> RST_BOOTSTRAP_REF_CLK_LSB) +#define RST_BOOTSTRAP_REF_CLK_SET(x) (((x) << RST_BOOTSTRAP_REF_CLK_LSB) & RST_BOOTSTRAP_REF_CLK_MASK) +#define RST_BOOTSTRAP_REF_CLK_RESET 0x0 // 0 +#define RST_BOOTSTRAP_RES1_MSB 3 +#define RST_BOOTSTRAP_RES1_LSB 3 +#define RST_BOOTSTRAP_RES1_MASK 0x00000008 +#define RST_BOOTSTRAP_RES1_GET(x) (((x) & RST_BOOTSTRAP_RES1_MASK) >> RST_BOOTSTRAP_RES1_LSB) +#define RST_BOOTSTRAP_RES1_SET(x) (((x) << RST_BOOTSTRAP_RES1_LSB) & RST_BOOTSTRAP_RES1_MASK) +#define RST_BOOTSTRAP_RES1_RESET 0x0 // 0 +#define RST_BOOTSTRAP_RES0_MSB 2 +#define RST_BOOTSTRAP_RES0_LSB 2 +#define RST_BOOTSTRAP_RES0_MASK 0x00000004 +#define RST_BOOTSTRAP_RES0_GET(x) (((x) & RST_BOOTSTRAP_RES0_MASK) >> RST_BOOTSTRAP_RES0_LSB) +#define RST_BOOTSTRAP_RES0_SET(x) (((x) << RST_BOOTSTRAP_RES0_LSB) & RST_BOOTSTRAP_RES0_MASK) +#define RST_BOOTSTRAP_RES0_RESET 0x0 // 0 +#define RST_BOOTSTRAP_SDRAM_SELECT_MSB 1 +#define RST_BOOTSTRAP_SDRAM_SELECT_LSB 1 +#define RST_BOOTSTRAP_SDRAM_SELECT_MASK 0x00000002 +#define RST_BOOTSTRAP_SDRAM_SELECT_GET(x) (((x) & RST_BOOTSTRAP_SDRAM_SELECT_MASK) >> RST_BOOTSTRAP_SDRAM_SELECT_LSB) +#define RST_BOOTSTRAP_SDRAM_SELECT_SET(x) (((x) << RST_BOOTSTRAP_SDRAM_SELECT_LSB) & RST_BOOTSTRAP_SDRAM_SELECT_MASK) +#define RST_BOOTSTRAP_SDRAM_SELECT_RESET 0x0 // 0 +#define RST_BOOTSTRAP_DDR_SELECT_MSB 0 +#define RST_BOOTSTRAP_DDR_SELECT_LSB 0 +#define RST_BOOTSTRAP_DDR_SELECT_MASK 0x00000001 +#define RST_BOOTSTRAP_DDR_SELECT_GET(x) (((x) & RST_BOOTSTRAP_DDR_SELECT_MASK) >> RST_BOOTSTRAP_DDR_SELECT_LSB) +#define RST_BOOTSTRAP_DDR_SELECT_SET(x) (((x) << RST_BOOTSTRAP_DDR_SELECT_LSB) & RST_BOOTSTRAP_DDR_SELECT_MASK) +#define RST_BOOTSTRAP_DDR_SELECT_RESET 0x0 // 0 +#define RST_BOOTSTRAP_ADDRESS 0x180600b0 + +#define RST_CLKGAT_EN_SPARE_MSB 31 +#define RST_CLKGAT_EN_SPARE_LSB 12 +#define RST_CLKGAT_EN_SPARE_MASK 0xfffff000 +#define RST_CLKGAT_EN_SPARE_GET(x) (((x) & RST_CLKGAT_EN_SPARE_MASK) >> RST_CLKGAT_EN_SPARE_LSB) +#define RST_CLKGAT_EN_SPARE_SET(x) (((x) << RST_CLKGAT_EN_SPARE_LSB) & RST_CLKGAT_EN_SPARE_MASK) +#define RST_CLKGAT_EN_SPARE_RESET 0x0 // 0 +#define RST_CLKGAT_EN_WMAC_MSB 9 +#define RST_CLKGAT_EN_WMAC_LSB 9 +#define RST_CLKGAT_EN_WMAC_MASK 0x00000200 +#define RST_CLKGAT_EN_WMAC_GET(x) (((x) & RST_CLKGAT_EN_WMAC_MASK) >> RST_CLKGAT_EN_WMAC_LSB) +#define RST_CLKGAT_EN_WMAC_SET(x) (((x) << RST_CLKGAT_EN_WMAC_LSB) & RST_CLKGAT_EN_WMAC_MASK) +#define RST_CLKGAT_EN_WMAC_RESET 0x1 // 1 +#define RST_CLKGAT_EN_USB1_MSB 7 +#define RST_CLKGAT_EN_USB1_LSB 7 +#define RST_CLKGAT_EN_USB1_MASK 0x00000080 +#define RST_CLKGAT_EN_USB1_GET(x) (((x) & RST_CLKGAT_EN_USB1_MASK) >> RST_CLKGAT_EN_USB1_LSB) +#define RST_CLKGAT_EN_USB1_SET(x) (((x) << RST_CLKGAT_EN_USB1_LSB) & RST_CLKGAT_EN_USB1_MASK) +#define RST_CLKGAT_EN_USB1_RESET 0x1 // 1 +#define RST_CLKGAT_EN_GE1_MSB 6 +#define RST_CLKGAT_EN_GE1_LSB 6 +#define RST_CLKGAT_EN_GE1_MASK 0x00000040 +#define RST_CLKGAT_EN_GE1_GET(x) (((x) & RST_CLKGAT_EN_GE1_MASK) >> RST_CLKGAT_EN_GE1_LSB) +#define RST_CLKGAT_EN_GE1_SET(x) (((x) << RST_CLKGAT_EN_GE1_LSB) & RST_CLKGAT_EN_GE1_MASK) +#define RST_CLKGAT_EN_GE1_RESET 0x1 // 1 +#define RST_CLKGAT_EN_GE0_MSB 5 +#define RST_CLKGAT_EN_GE0_LSB 5 +#define RST_CLKGAT_EN_GE0_MASK 0x00000020 +#define RST_CLKGAT_EN_GE0_GET(x) (((x) & RST_CLKGAT_EN_GE0_MASK) >> RST_CLKGAT_EN_GE0_LSB) +#define RST_CLKGAT_EN_GE0_SET(x) (((x) << RST_CLKGAT_EN_GE0_LSB) & RST_CLKGAT_EN_GE0_MASK) +#define RST_CLKGAT_EN_GE0_RESET 0x1 // 1 +#define RST_CLKGAT_EN_PCIE_RC_MSB 1 +#define RST_CLKGAT_EN_PCIE_RC_LSB 1 +#define RST_CLKGAT_EN_PCIE_RC_MASK 0x00000002 +#define RST_CLKGAT_EN_PCIE_RC_GET(x) (((x) & RST_CLKGAT_EN_PCIE_RC_MASK) >> RST_CLKGAT_EN_PCIE_RC_LSB) +#define RST_CLKGAT_EN_PCIE_RC_SET(x) (((x) << RST_CLKGAT_EN_PCIE_RC_LSB) & RST_CLKGAT_EN_PCIE_RC_MASK) +#define RST_CLKGAT_EN_PCIE_RC_RESET 0x1 // 1 +#define RST_CLKGAT_EN_ADDRESS 0x180600c0 +#define RST_CLKGAT_EN_OFFSET 0x00c0 +// SW modifiable bits +#define RST_CLKGAT_EN_SW_MASK 0xfffff2e2 +// bits defined at reset +#define RST_CLKGAT_EN_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define RST_CLKGAT_EN_RESET 0x000002e2 + +#define GPIO_OE_ADDRESS 0x18040000 +#define GPIO_IN_ADDRESS 0x18040004/* by huangwenzhong, 03Sep13 */ +#define GPIO_OUT_ADDRESS 0x18040008 +#define GPIO_SPARE_ADDRESS 0x18040070 + + +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MSB 31 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB 24 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK 0xff000000 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB) +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK) +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MSB 23 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB 16 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK 0x00ff0000 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB) +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK) +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MSB 15 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB 8 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK 0x0000ff00 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB) +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK) +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MSB 7 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB 0 +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK 0x000000ff +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB) +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK) +#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION0_ADDRESS 0x1804002c + +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MSB 31 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB 24 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK 0xff000000 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_RESET 0xc // 12 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MSB 23 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB 16 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK 0x00ff0000 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_RESET 0x8 // 8 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MSB 15 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB 8 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK 0x0000ff00 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_RESET 0x9 // 9 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MSB 7 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB 0 +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK 0x000000ff +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) +#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x5d // 93 +#define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030 + +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MSB 31 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB 24 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK 0xff000000 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB) +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK) +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MSB 23 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB 16 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK 0x00ff0000 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB) +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK) +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MSB 15 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB 8 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK 0x0000ff00 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB) +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK) +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MSB 7 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB 0 +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK 0x000000ff +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB) +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK) +#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION2_ADDRESS 0x18040034 + +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MSB 31 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB 24 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK 0xff000000 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB) +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK) +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MSB 23 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB 16 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK 0x00ff0000 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB) +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK) +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MSB 15 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB 8 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK 0x0000ff00 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB) +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK) +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MSB 7 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB 0 +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK 0x000000ff +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB) +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK) +#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION3_ADDRESS 0x18040038 + +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MSB 15 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_RESET 0x1 // 1 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MSB 7 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB 0 +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK 0x000000ff +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB) +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK) +#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_RESET 0x0 // 0 +#define GPIO_OUT_FUNCTION4_ADDRESS 0x1804003c + +#define GPIO_IN_ENABLE0_UART_SIN_MSB 15 +#define GPIO_IN_ENABLE0_UART_SIN_LSB 8 +#define GPIO_IN_ENABLE0_UART_SIN_MASK 0x0000ff00 +#define GPIO_IN_ENABLE0_UART_SIN_GET(x) (((x) & GPIO_IN_ENABLE0_UART_SIN_MASK) >> GPIO_IN_ENABLE0_UART_SIN_LSB) +#define GPIO_IN_ENABLE0_UART_SIN_SET(x) (((x) << GPIO_IN_ENABLE0_UART_SIN_LSB) & GPIO_IN_ENABLE0_UART_SIN_MASK) +#define GPIO_IN_ENABLE0_UART_SIN_RESET 0x80 // 128 +#define GPIO_IN_ENABLE0_SPI_DATA_IN_MSB 7 +#define GPIO_IN_ENABLE0_SPI_DATA_IN_LSB 0 +#define GPIO_IN_ENABLE0_SPI_DATA_IN_MASK 0x000000ff +#define GPIO_IN_ENABLE0_SPI_DATA_IN_GET(x) (((x) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK) >> GPIO_IN_ENABLE0_SPI_DATA_IN_LSB) +#define GPIO_IN_ENABLE0_SPI_DATA_IN_SET(x) (((x) << GPIO_IN_ENABLE0_SPI_DATA_IN_LSB) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK) +#define GPIO_IN_ENABLE0_SPI_DATA_IN_RESET 0x8 // 8 +#define GPIO_IN_ENABLE0_ADDRESS 0x18040044 + +#define GPIO_IN_ENABLE1_RES_MSB 31 +#define GPIO_IN_ENABLE1_RES_LSB 0 +#define GPIO_IN_ENABLE1_RES_MASK 0xffffffff +#define GPIO_IN_ENABLE1_RES_GET(x) (((x) & GPIO_IN_ENABLE1_RES_MASK) >> GPIO_IN_ENABLE1_RES_LSB) +#define GPIO_IN_ENABLE1_RES_SET(x) (((x) << GPIO_IN_ENABLE1_RES_LSB) & GPIO_IN_ENABLE1_RES_MASK) +#define GPIO_IN_ENABLE1_RES_RESET 0x0 // 0 +#define GPIO_IN_ENABLE1_ADDRESS 0x18040048 + +#define GPIO_IN_ENABLE2_RES_MSB 31 +#define GPIO_IN_ENABLE2_RES_LSB 0 +#define GPIO_IN_ENABLE2_RES_MASK 0xffffffff +#define GPIO_IN_ENABLE2_RES_GET(x) (((x) & GPIO_IN_ENABLE2_RES_MASK) >> GPIO_IN_ENABLE2_RES_LSB) +#define GPIO_IN_ENABLE2_RES_SET(x) (((x) << GPIO_IN_ENABLE2_RES_LSB) & GPIO_IN_ENABLE2_RES_MASK) +#define GPIO_IN_ENABLE2_RES_RESET 0x0 // 0 +#define GPIO_IN_ENABLE2_ADDRESS 0x1804004c + +#define GPIO_IN_ENABLE3_RES_MSB 31 +#define GPIO_IN_ENABLE3_RES_LSB 0 +#define GPIO_IN_ENABLE3_RES_MASK 0xffffffff +#define GPIO_IN_ENABLE3_RES_GET(x) (((x) & GPIO_IN_ENABLE3_RES_MASK) >> GPIO_IN_ENABLE3_RES_LSB) +#define GPIO_IN_ENABLE3_RES_SET(x) (((x) << GPIO_IN_ENABLE3_RES_LSB) & GPIO_IN_ENABLE3_RES_MASK) +#define GPIO_IN_ENABLE3_RES_RESET 0x0 // 0 +#define GPIO_IN_ENABLE3_ADDRESS 0x18040050 + +#define GPIO_IN_ENABLE4_RES_MSB 31 +#define GPIO_IN_ENABLE4_RES_LSB 0 +#define GPIO_IN_ENABLE4_RES_MASK 0xffffffff +#define GPIO_IN_ENABLE4_RES_GET(x) (((x) & GPIO_IN_ENABLE4_RES_MASK) >> GPIO_IN_ENABLE4_RES_LSB) +#define GPIO_IN_ENABLE4_RES_SET(x) (((x) << GPIO_IN_ENABLE4_RES_LSB) & GPIO_IN_ENABLE4_RES_MASK) +#define GPIO_IN_ENABLE4_RES_RESET 0x0 // 0 +#define GPIO_IN_ENABLE4_ADDRESS 0x18040054 + +#define GPIO_IN_ENABLE5_WMAC_IN3_MSB 31 +#define GPIO_IN_ENABLE5_WMAC_IN3_LSB 24 +#define GPIO_IN_ENABLE5_WMAC_IN3_MASK 0xff000000 +#define GPIO_IN_ENABLE5_WMAC_IN3_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN3_MASK) >> GPIO_IN_ENABLE5_WMAC_IN3_LSB) +#define GPIO_IN_ENABLE5_WMAC_IN3_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN3_LSB) & GPIO_IN_ENABLE5_WMAC_IN3_MASK) +#define GPIO_IN_ENABLE5_WMAC_IN3_RESET 0x80 // 128 +#define GPIO_IN_ENABLE5_WMAC_IN2_MSB 23 +#define GPIO_IN_ENABLE5_WMAC_IN2_LSB 16 +#define GPIO_IN_ENABLE5_WMAC_IN2_MASK 0x00ff0000 +#define GPIO_IN_ENABLE5_WMAC_IN2_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN2_MASK) >> GPIO_IN_ENABLE5_WMAC_IN2_LSB) +#define GPIO_IN_ENABLE5_WMAC_IN2_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN2_LSB) & GPIO_IN_ENABLE5_WMAC_IN2_MASK) +#define GPIO_IN_ENABLE5_WMAC_IN2_RESET 0x80 // 128 +#define GPIO_IN_ENABLE5_WMAC_IN1_MSB 15 +#define GPIO_IN_ENABLE5_WMAC_IN1_LSB 8 +#define GPIO_IN_ENABLE5_WMAC_IN1_MASK 0x0000ff00 +#define GPIO_IN_ENABLE5_WMAC_IN1_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN1_MASK) >> GPIO_IN_ENABLE5_WMAC_IN1_LSB) +#define GPIO_IN_ENABLE5_WMAC_IN1_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN1_LSB) & GPIO_IN_ENABLE5_WMAC_IN1_MASK) +#define GPIO_IN_ENABLE5_WMAC_IN1_RESET 0x80 // 128 +#define GPIO_IN_ENABLE5_WMAC_IN0_MSB 7 +#define GPIO_IN_ENABLE5_WMAC_IN0_LSB 0 +#define GPIO_IN_ENABLE5_WMAC_IN0_MASK 0x000000ff +#define GPIO_IN_ENABLE5_WMAC_IN0_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN0_MASK) >> GPIO_IN_ENABLE5_WMAC_IN0_LSB) +#define GPIO_IN_ENABLE5_WMAC_IN0_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN0_LSB) & GPIO_IN_ENABLE5_WMAC_IN0_MASK) +#define GPIO_IN_ENABLE5_WMAC_IN0_RESET 0x80 // 128 +#define GPIO_IN_ENABLE5_ADDRESS 0x18040058 + +#define GPIO_IN_ENABLE6_WMAC_IN7_MSB 31 +#define GPIO_IN_ENABLE6_WMAC_IN7_LSB 24 +#define GPIO_IN_ENABLE6_WMAC_IN7_MASK 0xff000000 +#define GPIO_IN_ENABLE6_WMAC_IN7_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN7_MASK) >> GPIO_IN_ENABLE6_WMAC_IN7_LSB) +#define GPIO_IN_ENABLE6_WMAC_IN7_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN7_LSB) & GPIO_IN_ENABLE6_WMAC_IN7_MASK) +#define GPIO_IN_ENABLE6_WMAC_IN7_RESET 0x80 // 128 +#define GPIO_IN_ENABLE6_WMAC_IN6_MSB 23 +#define GPIO_IN_ENABLE6_WMAC_IN6_LSB 16 +#define GPIO_IN_ENABLE6_WMAC_IN6_MASK 0x00ff0000 +#define GPIO_IN_ENABLE6_WMAC_IN6_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN6_MASK) >> GPIO_IN_ENABLE6_WMAC_IN6_LSB) +#define GPIO_IN_ENABLE6_WMAC_IN6_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN6_LSB) & GPIO_IN_ENABLE6_WMAC_IN6_MASK) +#define GPIO_IN_ENABLE6_WMAC_IN6_RESET 0x80 // 128 +#define GPIO_IN_ENABLE6_WMAC_IN5_MSB 15 +#define GPIO_IN_ENABLE6_WMAC_IN5_LSB 8 +#define GPIO_IN_ENABLE6_WMAC_IN5_MASK 0x0000ff00 +#define GPIO_IN_ENABLE6_WMAC_IN5_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN5_MASK) >> GPIO_IN_ENABLE6_WMAC_IN5_LSB) +#define GPIO_IN_ENABLE6_WMAC_IN5_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN5_LSB) & GPIO_IN_ENABLE6_WMAC_IN5_MASK) +#define GPIO_IN_ENABLE6_WMAC_IN5_RESET 0x80 // 128 +#define GPIO_IN_ENABLE6_WMAC_IN4_MSB 7 +#define GPIO_IN_ENABLE6_WMAC_IN4_LSB 0 +#define GPIO_IN_ENABLE6_WMAC_IN4_MASK 0x000000ff +#define GPIO_IN_ENABLE6_WMAC_IN4_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN4_MASK) >> GPIO_IN_ENABLE6_WMAC_IN4_LSB) +#define GPIO_IN_ENABLE6_WMAC_IN4_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN4_LSB) & GPIO_IN_ENABLE6_WMAC_IN4_MASK) +#define GPIO_IN_ENABLE6_WMAC_IN4_RESET 0x80 // 128 +#define GPIO_IN_ENABLE6_ADDRESS 0x1804005c + +#define GPIO_IN_ENABLE7_WMAC_IN11_MSB 31 +#define GPIO_IN_ENABLE7_WMAC_IN11_LSB 24 +#define GPIO_IN_ENABLE7_WMAC_IN11_MASK 0xff000000 +#define GPIO_IN_ENABLE7_WMAC_IN11_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN11_MASK) >> GPIO_IN_ENABLE7_WMAC_IN11_LSB) +#define GPIO_IN_ENABLE7_WMAC_IN11_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN11_LSB) & GPIO_IN_ENABLE7_WMAC_IN11_MASK) +#define GPIO_IN_ENABLE7_WMAC_IN11_RESET 0x80 // 128 +#define GPIO_IN_ENABLE7_WMAC_IN10_MSB 23 +#define GPIO_IN_ENABLE7_WMAC_IN10_LSB 16 +#define GPIO_IN_ENABLE7_WMAC_IN10_MASK 0x00ff0000 +#define GPIO_IN_ENABLE7_WMAC_IN10_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN10_MASK) >> GPIO_IN_ENABLE7_WMAC_IN10_LSB) +#define GPIO_IN_ENABLE7_WMAC_IN10_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN10_LSB) & GPIO_IN_ENABLE7_WMAC_IN10_MASK) +#define GPIO_IN_ENABLE7_WMAC_IN10_RESET 0x80 // 128 +#define GPIO_IN_ENABLE7_WMAC_IN9_MSB 15 +#define GPIO_IN_ENABLE7_WMAC_IN9_LSB 8 +#define GPIO_IN_ENABLE7_WMAC_IN9_MASK 0x0000ff00 +#define GPIO_IN_ENABLE7_WMAC_IN9_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN9_MASK) >> GPIO_IN_ENABLE7_WMAC_IN9_LSB) +#define GPIO_IN_ENABLE7_WMAC_IN9_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN9_LSB) & GPIO_IN_ENABLE7_WMAC_IN9_MASK) +#define GPIO_IN_ENABLE7_WMAC_IN9_RESET 0x80 // 128 +#define GPIO_IN_ENABLE7_WMAC_IN8_MSB 7 +#define GPIO_IN_ENABLE7_WMAC_IN8_LSB 0 +#define GPIO_IN_ENABLE7_WMAC_IN8_MASK 0x000000ff +#define GPIO_IN_ENABLE7_WMAC_IN8_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN8_MASK) >> GPIO_IN_ENABLE7_WMAC_IN8_LSB) +#define GPIO_IN_ENABLE7_WMAC_IN8_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN8_LSB) & GPIO_IN_ENABLE7_WMAC_IN8_MASK) +#define GPIO_IN_ENABLE7_WMAC_IN8_RESET 0x80 // 128 +#define GPIO_IN_ENABLE7_ADDRESS 0x18040060 + +#define GPIO_IN_ENABLE8_SRIF_SRESET_MSB 31 +#define GPIO_IN_ENABLE8_SRIF_SRESET_LSB 24 +#define GPIO_IN_ENABLE8_SRIF_SRESET_MASK 0xff000000 +#define GPIO_IN_ENABLE8_SRIF_SRESET_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SRESET_MASK) >> GPIO_IN_ENABLE8_SRIF_SRESET_LSB) +#define GPIO_IN_ENABLE8_SRIF_SRESET_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SRESET_LSB) & GPIO_IN_ENABLE8_SRIF_SRESET_MASK) +#define GPIO_IN_ENABLE8_SRIF_SRESET_RESET 0x80 // 128 +#define GPIO_IN_ENABLE8_SRIF_SIN_MSB 23 +#define GPIO_IN_ENABLE8_SRIF_SIN_LSB 16 +#define GPIO_IN_ENABLE8_SRIF_SIN_MASK 0x00ff0000 +#define GPIO_IN_ENABLE8_SRIF_SIN_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SIN_MASK) >> GPIO_IN_ENABLE8_SRIF_SIN_LSB) +#define GPIO_IN_ENABLE8_SRIF_SIN_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SIN_LSB) & GPIO_IN_ENABLE8_SRIF_SIN_MASK) +#define GPIO_IN_ENABLE8_SRIF_SIN_RESET 0x80 // 128 +#define GPIO_IN_ENABLE8_SRIF_SOT_MSB 15 +#define GPIO_IN_ENABLE8_SRIF_SOT_LSB 8 +#define GPIO_IN_ENABLE8_SRIF_SOT_MASK 0x0000ff00 +#define GPIO_IN_ENABLE8_SRIF_SOT_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SOT_MASK) >> GPIO_IN_ENABLE8_SRIF_SOT_LSB) +#define GPIO_IN_ENABLE8_SRIF_SOT_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SOT_LSB) & GPIO_IN_ENABLE8_SRIF_SOT_MASK) +#define GPIO_IN_ENABLE8_SRIF_SOT_RESET 0x80 // 128 +#define GPIO_IN_ENABLE8_SRIF_SCLK_MSB 7 +#define GPIO_IN_ENABLE8_SRIF_SCLK_LSB 0 +#define GPIO_IN_ENABLE8_SRIF_SCLK_MASK 0x000000ff +#define GPIO_IN_ENABLE8_SRIF_SCLK_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SCLK_MASK) >> GPIO_IN_ENABLE8_SRIF_SCLK_LSB) +#define GPIO_IN_ENABLE8_SRIF_SCLK_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SCLK_LSB) & GPIO_IN_ENABLE8_SRIF_SCLK_MASK) +#define GPIO_IN_ENABLE8_SRIF_SCLK_RESET 0x80 // 128 +#define GPIO_IN_ENABLE8_ADDRESS 0x18040064 + +#define GPIO_IN_ENABLE9_RES_MSB 31 +#define GPIO_IN_ENABLE9_RES_LSB 0 +#define GPIO_IN_ENABLE9_RES_MASK 0xffffffff +#define GPIO_IN_ENABLE9_RES_GET(x) (((x) & GPIO_IN_ENABLE9_RES_MASK) >> GPIO_IN_ENABLE9_RES_LSB) +#define GPIO_IN_ENABLE9_RES_SET(x) (((x) << GPIO_IN_ENABLE9_RES_LSB) & GPIO_IN_ENABLE9_RES_MASK) +#define GPIO_IN_ENABLE9_RES_RESET 0x0 // 0 +#define GPIO_IN_ENABLE9_ADDRESS 0x18040068 + +#define GPIO_FUNCTION_EXT_MDIO_SEL_MSB 11 +#define GPIO_FUNCTION_EXT_MDIO_SEL_LSB 11 +#define GPIO_FUNCTION_EXT_MDIO_SEL_MASK 0x00000800 +#define GPIO_FUNCTION_EXT_MDIO_SEL_GET(x) (((x) & GPIO_FUNCTION_EXT_MDIO_SEL_MASK) >> GPIO_FUNCTION_EXT_MDIO_SEL_LSB) +#define GPIO_FUNCTION_EXT_MDIO_SEL_SET(x) (((x) << GPIO_FUNCTION_EXT_MDIO_SEL_LSB) & GPIO_FUNCTION_EXT_MDIO_SEL_MASK) +#define GPIO_FUNCTION_EXT_MDIO_SEL_RESET 0x0 // 0 +#define GPIO_FUNCTION_CLK_OBS6_ENABLE_MSB 8 +#define GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB 8 +#define GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK 0x00000100 +#define GPIO_FUNCTION_CLK_OBS6_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB) +#define GPIO_FUNCTION_CLK_OBS6_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK) +#define GPIO_FUNCTION_CLK_OBS6_ENABLE_RESET 0x0 // 0 +#define GPIO_FUNCTION_CLK_OBS5_ENABLE_MSB 7 +#define GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB 7 +#define GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK 0x00000080 +#define GPIO_FUNCTION_CLK_OBS5_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB) +#define GPIO_FUNCTION_CLK_OBS5_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK) +#define GPIO_FUNCTION_CLK_OBS5_ENABLE_RESET 0x0 // 0 +#define GPIO_FUNCTION_CLK_OBS4_ENABLE_MSB 6 +#define GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB 6 +#define GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK 0x00000040 +#define GPIO_FUNCTION_CLK_OBS4_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB) +#define GPIO_FUNCTION_CLK_OBS4_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK) +#define GPIO_FUNCTION_CLK_OBS4_ENABLE_RESET 0x0 // 0 +#define GPIO_FUNCTION_CLK_OBS3_ENABLE_MSB 5 +#define GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB 5 +#define GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK 0x00000020 +#define GPIO_FUNCTION_CLK_OBS3_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB) +#define GPIO_FUNCTION_CLK_OBS3_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK) +#define GPIO_FUNCTION_CLK_OBS3_ENABLE_RESET 0x1 // 1 +#define GPIO_FUNCTION_CLK_OBS2_ENABLE_MSB 4 +#define GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB 4 +#define GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK 0x00000010 +#define GPIO_FUNCTION_CLK_OBS2_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB) +#define GPIO_FUNCTION_CLK_OBS2_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK) +#define GPIO_FUNCTION_CLK_OBS2_ENABLE_RESET 0x0 // 0 +#define GPIO_FUNCTION_CLK_OBS1_ENABLE_MSB 3 +#define GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB 3 +#define GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK 0x00000008 +#define GPIO_FUNCTION_CLK_OBS1_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB) +#define GPIO_FUNCTION_CLK_OBS1_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK) +#define GPIO_FUNCTION_CLK_OBS1_ENABLE_RESET 0x0 // 0 +#define GPIO_FUNCTION_CLK_OBS0_ENABLE_MSB 2 +#define GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB 2 +#define GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK 0x00000004 +#define GPIO_FUNCTION_CLK_OBS0_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB) +#define GPIO_FUNCTION_CLK_OBS0_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK) +#define GPIO_FUNCTION_CLK_OBS0_ENABLE_RESET 0x0 // 0 +#define GPIO_FUNCTION_DISABLE_JTAG_MSB 1 +#define GPIO_FUNCTION_DISABLE_JTAG_LSB 1 +#define GPIO_FUNCTION_DISABLE_JTAG_MASK 0x00000002 +#define GPIO_FUNCTION_DISABLE_JTAG_GET(x) (((x) & GPIO_FUNCTION_DISABLE_JTAG_MASK) >> GPIO_FUNCTION_DISABLE_JTAG_LSB) +#define GPIO_FUNCTION_DISABLE_JTAG_SET(x) (((x) << GPIO_FUNCTION_DISABLE_JTAG_LSB) & GPIO_FUNCTION_DISABLE_JTAG_MASK) +#define GPIO_FUNCTION_DISABLE_JTAG_RESET 0x0 // 0 +#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MSB 0 +#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB 0 +#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK 0x00000001 +#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_GET(x) (((x) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK) >> GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB) +#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_SET(x) (((x) << GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK) +#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_RESET 0x0 // 0 +#define GPIO_FUNCTION_ADDRESS 0x1804006c + +#define PCIE_RESET_EP_RESET_L_MSB 2 +#define PCIE_RESET_EP_RESET_L_LSB 2 +#define PCIE_RESET_EP_RESET_L_MASK 0x00000004 +#define PCIE_RESET_EP_RESET_L_GET(x) (((x) & PCIE_RESET_EP_RESET_L_MASK) >> PCIE_RESET_EP_RESET_L_LSB) +#define PCIE_RESET_EP_RESET_L_SET(x) (((x) << PCIE_RESET_EP_RESET_L_LSB) & PCIE_RESET_EP_RESET_L_MASK) +#define PCIE_RESET_EP_RESET_L_RESET 0x0 // 0 +#define PCIE_RESET_LINK_REQ_RESET_MSB 1 +#define PCIE_RESET_LINK_REQ_RESET_LSB 1 +#define PCIE_RESET_LINK_REQ_RESET_MASK 0x00000002 +#define PCIE_RESET_LINK_REQ_RESET_GET(x) (((x) & PCIE_RESET_LINK_REQ_RESET_MASK) >> PCIE_RESET_LINK_REQ_RESET_LSB) +#define PCIE_RESET_LINK_REQ_RESET_SET(x) (((x) << PCIE_RESET_LINK_REQ_RESET_LSB) & PCIE_RESET_LINK_REQ_RESET_MASK) +#define PCIE_RESET_LINK_REQ_RESET_RESET 0x0 // 0 +#define PCIE_RESET_LINK_UP_MSB 0 +#define PCIE_RESET_LINK_UP_LSB 0 +#define PCIE_RESET_LINK_UP_MASK 0x00000001 +#define PCIE_RESET_LINK_UP_GET(x) (((x) & PCIE_RESET_LINK_UP_MASK) >> PCIE_RESET_LINK_UP_LSB) +#define PCIE_RESET_LINK_UP_SET(x) (((x) << PCIE_RESET_LINK_UP_LSB) & PCIE_RESET_LINK_UP_MASK) +#define PCIE_RESET_LINK_UP_RESET 0x0 // 0 +#define PCIE_RESET_ADDRESS 0x180f0018 + +#define ETH_CFG_ETH_SPARE_MSB 31 +#define ETH_CFG_ETH_SPARE_LSB 22 +#define ETH_CFG_ETH_SPARE_MASK 0xffc00000 +#define ETH_CFG_ETH_SPARE_GET(x) (((x) & ETH_CFG_ETH_SPARE_MASK) >> ETH_CFG_ETH_SPARE_LSB) +#define ETH_CFG_ETH_SPARE_SET(x) (((x) << ETH_CFG_ETH_SPARE_LSB) & ETH_CFG_ETH_SPARE_MASK) +#define ETH_CFG_ETH_SPARE_RESET 0x0 // 0 +#define ETH_CFG_SW_ACC_MSB_FIRST_MSB 13 +#define ETH_CFG_SW_ACC_MSB_FIRST_LSB 13 +#define ETH_CFG_SW_ACC_MSB_FIRST_MASK 0x00002000 +#define ETH_CFG_SW_ACC_MSB_FIRST_GET(x) (((x) & ETH_CFG_SW_ACC_MSB_FIRST_MASK) >> ETH_CFG_SW_ACC_MSB_FIRST_LSB) +#define ETH_CFG_SW_ACC_MSB_FIRST_SET(x) (((x) << ETH_CFG_SW_ACC_MSB_FIRST_LSB) & ETH_CFG_SW_ACC_MSB_FIRST_MASK) +#define ETH_CFG_SW_ACC_MSB_FIRST_RESET 0x1 // 1 +#define ETH_CFG_SW_APB_ACCESS_MSB 9 +#define ETH_CFG_SW_APB_ACCESS_LSB 9 +#define ETH_CFG_SW_APB_ACCESS_MASK 0x00000200 +#define ETH_CFG_SW_APB_ACCESS_GET(x) (((x) & ETH_CFG_SW_APB_ACCESS_MASK) >> ETH_CFG_SW_APB_ACCESS_LSB) +#define ETH_CFG_SW_APB_ACCESS_SET(x) (((x) << ETH_CFG_SW_APB_ACCESS_LSB) & ETH_CFG_SW_APB_ACCESS_MASK) +#define ETH_CFG_SW_APB_ACCESS_RESET 0x0 // 0 +#define ETH_CFG_SW_PHY_ADDR_SWAP_MSB 8 +#define ETH_CFG_SW_PHY_ADDR_SWAP_LSB 8 +#define ETH_CFG_SW_PHY_ADDR_SWAP_MASK 0x00000100 +#define ETH_CFG_SW_PHY_ADDR_SWAP_GET(x) (((x) & ETH_CFG_SW_PHY_ADDR_SWAP_MASK) >> ETH_CFG_SW_PHY_ADDR_SWAP_LSB) +#define ETH_CFG_SW_PHY_ADDR_SWAP_SET(x) (((x) << ETH_CFG_SW_PHY_ADDR_SWAP_LSB) & ETH_CFG_SW_PHY_ADDR_SWAP_MASK) +#define ETH_CFG_SW_PHY_ADDR_SWAP_RESET 0x0 // 0 +#define ETH_CFG_SW_PHY_SWAP_MSB 7 +#define ETH_CFG_SW_PHY_SWAP_LSB 7 +#define ETH_CFG_SW_PHY_SWAP_MASK 0x00000080 +#define ETH_CFG_SW_PHY_SWAP_GET(x) (((x) & ETH_CFG_SW_PHY_SWAP_MASK) >> ETH_CFG_SW_PHY_SWAP_LSB) +#define ETH_CFG_SW_PHY_SWAP_SET(x) (((x) << ETH_CFG_SW_PHY_SWAP_LSB) & ETH_CFG_SW_PHY_SWAP_MASK) +#define ETH_CFG_SW_PHY_SWAP_RESET 0x0 // 0 +#define ETH_CFG_SW_ONLY_MODE_MSB 6 +#define ETH_CFG_SW_ONLY_MODE_LSB 6 +#define ETH_CFG_SW_ONLY_MODE_MASK 0x00000040 +#define ETH_CFG_SW_ONLY_MODE_GET(x) (((x) & ETH_CFG_SW_ONLY_MODE_MASK) >> ETH_CFG_SW_ONLY_MODE_LSB) +#define ETH_CFG_SW_ONLY_MODE_SET(x) (((x) << ETH_CFG_SW_ONLY_MODE_LSB) & ETH_CFG_SW_ONLY_MODE_MASK) +#define ETH_CFG_SW_ONLY_MODE_RESET 0x0 // 0 +#define ETH_CFG_ADDRESS 0x18070000 + +#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ + +#define CONFIG_BOOTDELAY 1 /* autoboot after 4 seconds */ + +/* Only interrupt boot if special string is typed */ +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n" +#undef CONFIG_AUTOBOOT_DELAY_STR +#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ +#define CONFIG_AUTOBOOT_STOP_STR2 "tpl" /* esd special for esd access*/ + +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {115200} + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_ROOTFS_RD + +#define CONFIG_BOOTARGS_RD "console=ttyS0,115200 root=01:00 rd_start=0x802d0000 rd_size=5242880 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),4096k(rootfs),2048k(uImage)" + +/* XXX - putting rootfs in last partition results in jffs errors */ +#define CONFIG_BOOTARGS_FL "console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),5120k(rootfs),2048k(uImage)" + +#ifdef CONFIG_ROOTFS_FLASH +#define CONFIG_BOOTARGS CONFIG_BOOTARGS_FL +#else +#define CONFIG_BOOTARGS "" +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "ap143-2.0> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 512 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args*/ + +#define CFG_MALLOC_LEN (128*1024) + +#define CFG_BOOTPARAMS_LEN (128*1024) + +#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ +//#define CFG_SDRAM_BASE 0xa0000000 /* Cached addr */ + +//#define CFG_LOAD_ADDR 0x81000000 /* default load address */ +//#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CFG_MEMTEST_START 0x80100000 +#undef CFG_MEMTEST_START +#define CFG_MEMTEST_START 0x80200000 +#define CFG_MEMTEST_END 0x83800000 + +/*------------------------------------------------------------------------ + * * * JFFS2 + */ +#define CFG_JFFS_CUSTOM_PART /* board defined part */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=ath-nor0" + +#define CONFIG_MEMSIZE_IN_BYTES + +#define CFG_RX_ETH_BUFFER 16 + + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_ICACHE_SIZE 65536 +#define CFG_CACHELINE_SIZE 32 + +/* + * Address map + */ +#define ATH_PCI_MEM_BASE 0x10000000 /* 128M */ +#define ATH_APB_BASE 0x18000000 /* 384M */ +#define ATH_GE0_BASE 0x19000000 /* 16M */ +#define ATH_GE1_BASE 0x1a000000 /* 16M */ +#define ATH_USB_OHCI_BASE 0x1b000000 +#define ATH_USB_EHCI_BASE 0x1b000000 +#define ATH_USB_EHCI_BASE_1 0x1b000000 +#define ATH_USB_EHCI_BASE_2 0x1b400000 +#define ATH_SPI_BASE 0x1f000000 + +/* + * Added the PCI LCL RESET register from u-boot + * ath_soc.h so that we can query the PCI LCL RESET + * register for the presence of WLAN H/W. + */ +#define ATH_PCI_LCL_BASE (ATH_APB_BASE+0x000f0000) +#define ATH_PCI_LCL_APP (ATH_PCI_LCL_BASE+0x00) +#define ATH_PCI_LCL_RESET (ATH_PCI_LCL_BASE+0x18) + +/* + * APB block + */ +#define ATH_DDR_CTL_BASE ATH_APB_BASE+0x00000000 +#define ATH_CPU_BASE ATH_APB_BASE+0x00010000 +#define ATH_UART_BASE ATH_APB_BASE+0x00020000 +#define ATH_USB_CONFIG_BASE ATH_APB_BASE+0x00030000 +#define ATH_GPIO_BASE ATH_APB_BASE+0x00040000 +#define ATH_PLL_BASE ATH_APB_BASE+0x00050000 +#define ATH_RESET_BASE ATH_APB_BASE+0x00060000 +#define ATH_DMA_BASE ATH_APB_BASE+0x000A0000 +#define ATH_SLIC_BASE ATH_APB_BASE+0x000A9000 +#define ATH_STEREO_BASE ATH_APB_BASE+0x000B0000 +#define ATH_PCI_CTLR_BASE ATH_APB_BASE+0x000F0000 +#define ATH_OTP_BASE ATH_APB_BASE+0x00130000 +//#define ATH_NAND_FLASH_BASE 0x1b800000u + + +/* + * DDR Config values + */ +#define ATH_DDR_CONFIG_16BIT (1 << 31) +#define ATH_DDR_CONFIG_PAGE_OPEN (1 << 30) +#define ATH_DDR_CONFIG_CAS_LAT_SHIFT 27 +#define ATH_DDR_CONFIG_TMRD_SHIFT 23 +#define ATH_DDR_CONFIG_TRFC_SHIFT 17 +#define ATH_DDR_CONFIG_TRRD_SHIFT 13 +#define ATH_DDR_CONFIG_TRP_SHIFT 9 +#define ATH_DDR_CONFIG_TRCD_SHIFT 5 +#define ATH_DDR_CONFIG_TRAS_SHIFT 0 + +#define ATH_DDR_CONFIG2_BL2 (2 << 0) +#define ATH_DDR_CONFIG2_BL4 (4 << 0) +#define ATH_DDR_CONFIG2_BL8 (8 << 0) + +#define ATH_DDR_CONFIG2_BT_IL (1 << 4) +#define ATH_DDR_CONFIG2_CNTL_OE_EN (1 << 5) +#define ATH_DDR_CONFIG2_PHASE_SEL (1 << 6) +#define ATH_DDR_CONFIG2_DRAM_CKE (1 << 7) +#define ATH_DDR_CONFIG2_TWR_SHIFT 8 +#define ATH_DDR_CONFIG2_TRTW_SHIFT 12 +#define ATH_DDR_CONFIG2_TRTP_SHIFT 17 +#define ATH_DDR_CONFIG2_TWTR_SHIFT 21 +#define ATH_DDR_CONFIG2_HALF_WIDTH_L (1 << 31) + +#define ATH_DDR_TAP_DEFAULT 0x18 + +/* + * DDR block, gmac flushing + */ +#define ATH_DDR_GE0_FLUSH ATH_DDR_CTL_BASE+0x9c +#define ATH_DDR_GE1_FLUSH ATH_DDR_CTL_BASE+0xa0 +#define ATH_DDR_USB_FLUSH ATH_DDR_CTL_BASE+0xa4 +#define ATH_DDR_PCIE_FLUSH ATH_DDR_CTL_BASE+0x88 + +#define ATH_EEPROM_GE0_MAC_ADDR 0xbfff1000 +#define ATH_EEPROM_GE1_MAC_ADDR 0xbfff1006 + +/* + * PLL block/CPU + */ + +#define ATH_PLL_CONFIG ATH_PLL_BASE+0x0 +#define ATH_DDR_CLK_CTRL ATH_PLL_BASE+0x8 + + +#define PLL_DIV_SHIFT 0 +#define PLL_DIV_MASK 0x3ff +#define REF_DIV_SHIFT 10 +#define REF_DIV_MASK 0xf +#define AHB_DIV_SHIFT 19 +#define AHB_DIV_MASK 0x1 +#define DDR_DIV_SHIFT 22 +#define DDR_DIV_MASK 0x1 +#define ATH_DDR_PLL_CONFIG ATH_PLL_BASE+0x4 +#define ATH_ETH_XMII_CONFIG ATH_PLL_BASE+0x2c +#define ATH_AUDIO_PLL_CONFIG ATH_PLL_BASE+0x30 + +#define ATH_ETH_INT0_CLK ATH_PLL_BASE+0x14 +#define ATH_ETH_INT1_CLK ATH_PLL_BASE+0x18 + + +/* + * USB block + */ +#define ATH_USB_FLADJ_VAL ATH_USB_CONFIG_BASE +#define ATH_USB_CONFIG ATH_USB_CONFIG_BASE+0x4 +#define ATH_USB_WINDOW 0x10000 +#define ATH_USB_MODE ATH_USB_EHCI_BASE+0x1a8 + +/* + * PCI block + */ +#define ATH_PCI_WINDOW 0x8000000 /* 128MB */ +#define ATH_PCI_WINDOW0_OFFSET ATH_DDR_CTL_BASE+0x7c +#define ATH_PCI_WINDOW1_OFFSET ATH_DDR_CTL_BASE+0x80 +#define ATH_PCI_WINDOW2_OFFSET ATH_DDR_CTL_BASE+0x84 +#define ATH_PCI_WINDOW3_OFFSET ATH_DDR_CTL_BASE+0x88 +#define ATH_PCI_WINDOW4_OFFSET ATH_DDR_CTL_BASE+0x8c +#define ATH_PCI_WINDOW5_OFFSET ATH_DDR_CTL_BASE+0x90 +#define ATH_PCI_WINDOW6_OFFSET ATH_DDR_CTL_BASE+0x94 +#define ATH_PCI_WINDOW7_OFFSET ATH_DDR_CTL_BASE+0x98 + +#define ATH_PCI_WINDOW0_VAL 0x10000000 +#define ATH_PCI_WINDOW1_VAL 0x11000000 +#define ATH_PCI_WINDOW2_VAL 0x12000000 +#define ATH_PCI_WINDOW3_VAL 0x13000000 +#define ATH_PCI_WINDOW4_VAL 0x14000000 +#define ATH_PCI_WINDOW5_VAL 0x15000000 +#define ATH_PCI_WINDOW6_VAL 0x16000000 +#define ATH_PCI_WINDOW7_VAL 0x07000000 + +#define ath_write_pci_window(_no) \ + ath_reg_wr(ATH_PCI_WINDOW##_no##_OFFSET, ATH_PCI_WINDOW##_no##_VAL); + +/* + * CRP. To access the host controller config and status registers + */ +#define ATH_PCI_CRP 0x180c0000 +#define ATH_PCI_DEV_CFGBASE 0x14000000 +#define ATH_PCI_CRP_AD_CBE ATH_PCI_CRP +#define ATH_PCI_CRP_WRDATA ATH_PCI_CRP+0x4 +#define ATH_PCI_CRP_RDDATA ATH_PCI_CRP+0x8 +#define ATH_PCI_ERROR ATH_PCI_CRP+0x1c +#define ATH_PCI_ERROR_ADDRESS ATH_PCI_CRP+0x20 +#define ATH_PCI_AHB_ERROR ATH_PCI_CRP+0x24 +#define ATH_PCI_AHB_ERROR_ADDRESS ATH_PCI_CRP+0x28 + +#define ATH_CRP_CMD_WRITE 0x00010000 +#define ATH_CRP_CMD_READ 0x00000000 + +/* + * PCI CFG. To generate config cycles + */ +#define ATH_PCI_CFG_AD ATH_PCI_CRP+0xc +#define ATH_PCI_CFG_CBE ATH_PCI_CRP+0x10 +#define ATH_PCI_CFG_WRDATA ATH_PCI_CRP+0x14 +#define ATH_PCI_CFG_RDDATA ATH_PCI_CRP+0x18 +#define ATH_CFG_CMD_READ 0x0000000a +#define ATH_CFG_CMD_WRITE 0x0000000b + +#define ATH_PCI_IDSEL_ADLINE_START 17 + +#define ATH_SPI_FS (ATH_SPI_BASE+0x00) +#define ATH_SPI_READ (ATH_SPI_BASE+0x00) +#define ATH_SPI_CLOCK (ATH_SPI_BASE+0x04) +#define ATH_SPI_WRITE (ATH_SPI_BASE+0x08) +#define ATH_SPI_RD_STATUS (ATH_SPI_BASE+0x0c) +#define ATH_SPI_SHIFT_DO (ATH_SPI_BASE+0x10) +#define ATH_SPI_SHIFT_CNT (ATH_SPI_BASE+0x14) +#define ATH_SPI_SHIFT_DI (ATH_SPI_BASE+0x18) +#define ATH_SPI_D0_HIGH (1<<0) /* Pin spi_do */ +#define ATH_SPI_CLK_HIGH (1<<8) /* Pin spi_clk */ + +#define ATH_SPI_CS_ENABLE_0 (6<<16) /* Pin gpio/cs0 (active low) */ +#define ATH_SPI_CS_ENABLE_1 (5<<16) /* Pin gpio/cs1 (active low) */ +#define ATH_SPI_CS_ENABLE_2 (3<<16) /* Pin gpio/cs2 (active low) */ +#define ATH_SPI_CS_DIS 0x70000 +#define ATH_SPI_CE_LOW 0x60000 +#define ATH_SPI_CE_HIGH 0x60100 + +#define ATH_SPI_SECTOR_SIZE (1024*64) +#define ATH_SPI_PAGE_SIZE 256 + +#define ATH_RESET_GE0_MAC RST_RESET_GE0_MAC_RESET_SET(1) +#define ATH_RESET_GE0_PHY RST_RESET_ETH_SWITCH_RESET_SET(1) +#define ATH_RESET_GE1_MAC RST_RESET_GE1_MAC_RESET_SET(1) +#define ATH_RESET_GE1_PHY RST_RESET_ETH_SWITCH_ARESET_SET(1) +#define ATH_RESET_GE0_MDIO RST_RESET_GE0_MDIO_RESET_SET(1) +#define ATH_RESET_GE1_MDIO RST_RESET_GE1_MDIO_RESET_SET(1) + +/* + * SOC + */ +#define ATH_SPI_CMD_WRITE_SR 0x01 +#define ATH_SPI_CMD_WREN 0x06 +#define ATH_SPI_CMD_RD_STATUS 0x05 +#define ATH_SPI_CMD_FAST_READ 0x0b +#define ATH_SPI_CMD_PAGE_PROG 0x02 +#define ATH_SPI_CMD_SECTOR_ERASE 0xd8 +#define ATH_SPI_CMD_CHIP_ERASE 0xc7 +#define ATH_SPI_CMD_RDID 0x9f + +#if defined(CFG_ATH_EMULATION) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(2) // 80 MHz +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(1) // 40 MHz + +#elif (CFG_PLL_FREQ == CFG_PLL_550_400_200) + +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(22) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(16) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) +#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_720_600_200) + +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) +#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_720_600_300) + +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) +#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_400_400_200) + +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(16) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(16) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) +#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_720_680_240) + +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(17) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) +#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_720_600_240) + +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) +#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_560_450_220) + +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(14) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(11) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0x100) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) +#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_680_680_226) + +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(1) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(17) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(17) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) +#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_550_600_200) + +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(22) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(24) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) +#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_600_600_200) + +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(1) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(24) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + +#elif (CFG_PLL_FREQ == CFG_PLL_650_400_200) + +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(26) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(0xf) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(1) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x2FB) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0x27B) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) +#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) + + +#elif (CFG_PLL_FREQ == CFG_PLL_650_600_200) +#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) + +#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(26) +#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) +#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) +#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ + CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ + CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ + CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(0x17) +#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) +#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) +#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(1) | \ + DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ae) | \ + DDR_PLL_DITHER_NFRAC_MIN_SET(0x385) | \ + DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ + DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) + +#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) +#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) +#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) +#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) +#else + # error "CFG_PLL_FREQ not set" +#endif // CFG_PLL_FREQ + +#define CPU_CLK_FROM_DDR_PLL CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(0) +#define CPU_CLK_FROM_CPU_PLL CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) + +#define DDR_CLK_FROM_DDR_PLL CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) +#define DDR_CLK_FROM_CPU_PLL CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(0) + +#if CPU_DDR_SYNC_MODE + +# define both_from_cpu 0 +# define both_from_ddr 1 + +# if both_from_ddr +# define CLK_SRC_CONTROL (CPU_CLK_FROM_DDR_PLL | DDR_CLK_FROM_DDR_PLL) +# define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) +# elif both_from_cpu +# define CLK_SRC_CONTROL (CPU_CLK_FROM_CPU_PLL | DDR_CLK_FROM_CPU_PLL) +# define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) +# else +# error "Invalid sync mode settings" +# endif +#else +# define CLK_SRC_CONTROL (CPU_CLK_FROM_CPU_PLL | DDR_CLK_FROM_DDR_PLL) +#endif + + + +#define __nint_to_mhz(n, ref) ((n) * (ref) * 1000000) +#define __cpu_hz_40(pll) (__nint_to_mhz(CPU_PLL_CONFIG_NINT_GET(pll), 40)) +#define __cpu_hz_25(pll) (__nint_to_mhz(CPU_PLL_CONFIG_NINT_GET(pll), 25)) + +/* Since the count is incremented every other tick, divide by 2 */ +#define CFG_HZ (__cpu_hz_40(CPU_PLL_CONFIG_NINT_VAL) / 2) + +/* SGMII DEFINES */ + +// 32'h18070034 (SGMII_CONFIG) +#define SGMII_CONFIG_BERT_ENABLE_MSB 14 +#define SGMII_CONFIG_BERT_ENABLE_LSB 14 +#define SGMII_CONFIG_BERT_ENABLE_MASK 0x00004000 +#define SGMII_CONFIG_BERT_ENABLE_GET(x) (((x) & SGMII_CONFIG_BERT_ENABLE_MASK) >> SGMII_CONFIG_BERT_ENABLE_LSB) +#define SGMII_CONFIG_BERT_ENABLE_SET(x) (((x) << SGMII_CONFIG_BERT_ENABLE_LSB) & SGMII_CONFIG_BERT_ENABLE_MASK) +#define SGMII_CONFIG_BERT_ENABLE_RESET 0x0 // 0 +#define SGMII_CONFIG_PRBS_ENABLE_MSB 13 +#define SGMII_CONFIG_PRBS_ENABLE_LSB 13 +#define SGMII_CONFIG_PRBS_ENABLE_MASK 0x00002000 +#define SGMII_CONFIG_PRBS_ENABLE_GET(x) (((x) & SGMII_CONFIG_PRBS_ENABLE_MASK) >> SGMII_CONFIG_PRBS_ENABLE_LSB) +#define SGMII_CONFIG_PRBS_ENABLE_SET(x) (((x) << SGMII_CONFIG_PRBS_ENABLE_LSB) & SGMII_CONFIG_PRBS_ENABLE_MASK) +#define SGMII_CONFIG_PRBS_ENABLE_RESET 0x0 // 0 +#define SGMII_CONFIG_MDIO_COMPLETE_MSB 12 +#define SGMII_CONFIG_MDIO_COMPLETE_LSB 12 +#define SGMII_CONFIG_MDIO_COMPLETE_MASK 0x00001000 +#define SGMII_CONFIG_MDIO_COMPLETE_GET(x) (((x) & SGMII_CONFIG_MDIO_COMPLETE_MASK) >> SGMII_CONFIG_MDIO_COMPLETE_LSB) +#define SGMII_CONFIG_MDIO_COMPLETE_SET(x) (((x) << SGMII_CONFIG_MDIO_COMPLETE_LSB) & SGMII_CONFIG_MDIO_COMPLETE_MASK) +#define SGMII_CONFIG_MDIO_COMPLETE_RESET 0x0 // 0 +#define SGMII_CONFIG_MDIO_PULSE_MSB 11 +#define SGMII_CONFIG_MDIO_PULSE_LSB 11 +#define SGMII_CONFIG_MDIO_PULSE_MASK 0x00000800 +#define SGMII_CONFIG_MDIO_PULSE_GET(x) (((x) & SGMII_CONFIG_MDIO_PULSE_MASK) >> SGMII_CONFIG_MDIO_PULSE_LSB) +#define SGMII_CONFIG_MDIO_PULSE_SET(x) (((x) << SGMII_CONFIG_MDIO_PULSE_LSB) & SGMII_CONFIG_MDIO_PULSE_MASK) +#define SGMII_CONFIG_MDIO_PULSE_RESET 0x0 // 0 +#define SGMII_CONFIG_MDIO_ENABLE_MSB 10 +#define SGMII_CONFIG_MDIO_ENABLE_LSB 10 +#define SGMII_CONFIG_MDIO_ENABLE_MASK 0x00000400 +#define SGMII_CONFIG_MDIO_ENABLE_GET(x) (((x) & SGMII_CONFIG_MDIO_ENABLE_MASK) >> SGMII_CONFIG_MDIO_ENABLE_LSB) +#define SGMII_CONFIG_MDIO_ENABLE_SET(x) (((x) << SGMII_CONFIG_MDIO_ENABLE_LSB) & SGMII_CONFIG_MDIO_ENABLE_MASK) +#define SGMII_CONFIG_MDIO_ENABLE_RESET 0x0 // 0 +#define SGMII_CONFIG_NEXT_PAGE_LOADED_MSB 9 +#define SGMII_CONFIG_NEXT_PAGE_LOADED_LSB 9 +#define SGMII_CONFIG_NEXT_PAGE_LOADED_MASK 0x00000200 +#define SGMII_CONFIG_NEXT_PAGE_LOADED_GET(x) (((x) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK) >> SGMII_CONFIG_NEXT_PAGE_LOADED_LSB) +#define SGMII_CONFIG_NEXT_PAGE_LOADED_SET(x) (((x) << SGMII_CONFIG_NEXT_PAGE_LOADED_LSB) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK) +#define SGMII_CONFIG_NEXT_PAGE_LOADED_RESET 0x0 // 0 +#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MSB 8 +#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB 8 +#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK 0x00000100 +#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_GET(x) (((x) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK) >> SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB) +#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_SET(x) (((x) << SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK) +#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_RESET 0x0 // 0 +#define SGMII_CONFIG_SPEED_MSB 7 +#define SGMII_CONFIG_SPEED_LSB 6 +#define SGMII_CONFIG_SPEED_MASK 0x000000c0 +#define SGMII_CONFIG_SPEED_GET(x) (((x) & SGMII_CONFIG_SPEED_MASK) >> SGMII_CONFIG_SPEED_LSB) +#define SGMII_CONFIG_SPEED_SET(x) (((x) << SGMII_CONFIG_SPEED_LSB) & SGMII_CONFIG_SPEED_MASK) +#define SGMII_CONFIG_SPEED_RESET 0x0 // 0 +#define SGMII_CONFIG_FORCE_SPEED_MSB 5 +#define SGMII_CONFIG_FORCE_SPEED_LSB 5 +#define SGMII_CONFIG_FORCE_SPEED_MASK 0x00000020 +#define SGMII_CONFIG_FORCE_SPEED_GET(x) (((x) & SGMII_CONFIG_FORCE_SPEED_MASK) >> SGMII_CONFIG_FORCE_SPEED_LSB) +#define SGMII_CONFIG_FORCE_SPEED_SET(x) (((x) << SGMII_CONFIG_FORCE_SPEED_LSB) & SGMII_CONFIG_FORCE_SPEED_MASK) +#define SGMII_CONFIG_FORCE_SPEED_RESET 0x0 // 0 +#define SGMII_CONFIG_MR_REG4_CHANGED_MSB 4 +#define SGMII_CONFIG_MR_REG4_CHANGED_LSB 4 +#define SGMII_CONFIG_MR_REG4_CHANGED_MASK 0x00000010 +#define SGMII_CONFIG_MR_REG4_CHANGED_GET(x) (((x) & SGMII_CONFIG_MR_REG4_CHANGED_MASK) >> SGMII_CONFIG_MR_REG4_CHANGED_LSB) +#define SGMII_CONFIG_MR_REG4_CHANGED_SET(x) (((x) << SGMII_CONFIG_MR_REG4_CHANGED_LSB) & SGMII_CONFIG_MR_REG4_CHANGED_MASK) +#define SGMII_CONFIG_MR_REG4_CHANGED_RESET 0x0 // 0 +#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MSB 3 +#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB 3 +#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK 0x00000008 +#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_GET(x) (((x) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK) >> SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB) +#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_SET(x) (((x) << SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK) +#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_RESET 0x0 // 0 +#define SGMII_CONFIG_MODE_CTRL_MSB 2 +#define SGMII_CONFIG_MODE_CTRL_LSB 0 +#define SGMII_CONFIG_MODE_CTRL_MASK 0x00000007 +#define SGMII_CONFIG_MODE_CTRL_GET(x) (((x) & SGMII_CONFIG_MODE_CTRL_MASK) >> SGMII_CONFIG_MODE_CTRL_LSB) +#define SGMII_CONFIG_MODE_CTRL_SET(x) (((x) << SGMII_CONFIG_MODE_CTRL_LSB) & SGMII_CONFIG_MODE_CTRL_MASK) +#define SGMII_CONFIG_MODE_CTRL_RESET 0x0 // 0 +#define SGMII_CONFIG_ADDRESS 0x18070034 + + + +// 32'h1807001c (MR_AN_CONTROL) +#define MR_AN_CONTROL_PHY_RESET_MSB 15 +#define MR_AN_CONTROL_PHY_RESET_LSB 15 +#define MR_AN_CONTROL_PHY_RESET_MASK 0x00008000 +#define MR_AN_CONTROL_PHY_RESET_GET(x) (((x) & MR_AN_CONTROL_PHY_RESET_MASK) >> MR_AN_CONTROL_PHY_RESET_LSB) +#define MR_AN_CONTROL_PHY_RESET_SET(x) (((x) << MR_AN_CONTROL_PHY_RESET_LSB) & MR_AN_CONTROL_PHY_RESET_MASK) +#define MR_AN_CONTROL_PHY_RESET_RESET 0x0 // 0 +#define MR_AN_CONTROL_LOOPBACK_MSB 14 +#define MR_AN_CONTROL_LOOPBACK_LSB 14 +#define MR_AN_CONTROL_LOOPBACK_MASK 0x00004000 +#define MR_AN_CONTROL_LOOPBACK_GET(x) (((x) & MR_AN_CONTROL_LOOPBACK_MASK) >> MR_AN_CONTROL_LOOPBACK_LSB) +#define MR_AN_CONTROL_LOOPBACK_SET(x) (((x) << MR_AN_CONTROL_LOOPBACK_LSB) & MR_AN_CONTROL_LOOPBACK_MASK) +#define MR_AN_CONTROL_LOOPBACK_RESET 0x0 // 0 +#define MR_AN_CONTROL_SPEED_SEL0_MSB 13 +#define MR_AN_CONTROL_SPEED_SEL0_LSB 13 +#define MR_AN_CONTROL_SPEED_SEL0_MASK 0x00002000 +#define MR_AN_CONTROL_SPEED_SEL0_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL0_MASK) >> MR_AN_CONTROL_SPEED_SEL0_LSB) +#define MR_AN_CONTROL_SPEED_SEL0_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL0_LSB) & MR_AN_CONTROL_SPEED_SEL0_MASK) +#define MR_AN_CONTROL_SPEED_SEL0_RESET 0x0 // 0 +#define MR_AN_CONTROL_AN_ENABLE_MSB 12 +#define MR_AN_CONTROL_AN_ENABLE_LSB 12 +#define MR_AN_CONTROL_AN_ENABLE_MASK 0x00001000 +#define MR_AN_CONTROL_AN_ENABLE_GET(x) (((x) & MR_AN_CONTROL_AN_ENABLE_MASK) >> MR_AN_CONTROL_AN_ENABLE_LSB) +#define MR_AN_CONTROL_AN_ENABLE_SET(x) (((x) << MR_AN_CONTROL_AN_ENABLE_LSB) & MR_AN_CONTROL_AN_ENABLE_MASK) +#define MR_AN_CONTROL_AN_ENABLE_RESET 0x1 // 1 +#define MR_AN_CONTROL_POWER_DOWN_MSB 11 +#define MR_AN_CONTROL_POWER_DOWN_LSB 11 +#define MR_AN_CONTROL_POWER_DOWN_MASK 0x00000800 +#define MR_AN_CONTROL_POWER_DOWN_GET(x) (((x) & MR_AN_CONTROL_POWER_DOWN_MASK) >> MR_AN_CONTROL_POWER_DOWN_LSB) +#define MR_AN_CONTROL_POWER_DOWN_SET(x) (((x) << MR_AN_CONTROL_POWER_DOWN_LSB) & MR_AN_CONTROL_POWER_DOWN_MASK) +#define MR_AN_CONTROL_POWER_DOWN_RESET 0x0 // 0 +#define MR_AN_CONTROL_RESTART_AN_MSB 9 +#define MR_AN_CONTROL_RESTART_AN_LSB 9 +#define MR_AN_CONTROL_RESTART_AN_MASK 0x00000200 +#define MR_AN_CONTROL_RESTART_AN_GET(x) (((x) & MR_AN_CONTROL_RESTART_AN_MASK) >> MR_AN_CONTROL_RESTART_AN_LSB) +#define MR_AN_CONTROL_RESTART_AN_SET(x) (((x) << MR_AN_CONTROL_RESTART_AN_LSB) & MR_AN_CONTROL_RESTART_AN_MASK) +#define MR_AN_CONTROL_RESTART_AN_RESET 0x0 // 0 +#define MR_AN_CONTROL_DUPLEX_MODE_MSB 8 +#define MR_AN_CONTROL_DUPLEX_MODE_LSB 8 +#define MR_AN_CONTROL_DUPLEX_MODE_MASK 0x00000100 +#define MR_AN_CONTROL_DUPLEX_MODE_GET(x) (((x) & MR_AN_CONTROL_DUPLEX_MODE_MASK) >> MR_AN_CONTROL_DUPLEX_MODE_LSB) +#define MR_AN_CONTROL_DUPLEX_MODE_SET(x) (((x) << MR_AN_CONTROL_DUPLEX_MODE_LSB) & MR_AN_CONTROL_DUPLEX_MODE_MASK) +#define MR_AN_CONTROL_DUPLEX_MODE_RESET 0x1 // 1 +#define MR_AN_CONTROL_SPEED_SEL1_MSB 6 +#define MR_AN_CONTROL_SPEED_SEL1_LSB 6 +#define MR_AN_CONTROL_SPEED_SEL1_MASK 0x00000040 +#define MR_AN_CONTROL_SPEED_SEL1_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL1_MASK) >> MR_AN_CONTROL_SPEED_SEL1_LSB) +#define MR_AN_CONTROL_SPEED_SEL1_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL1_LSB) & MR_AN_CONTROL_SPEED_SEL1_MASK) +#define MR_AN_CONTROL_SPEED_SEL1_RESET 0x1 // 1 +#define MR_AN_CONTROL_ADDRESS 0x1807001c + + + + + +// 32'h18070014 (SGMII_RESET) +#define SGMII_RESET_HW_RX_125M_N_MSB 4 +#define SGMII_RESET_HW_RX_125M_N_LSB 4 +#define SGMII_RESET_HW_RX_125M_N_MASK 0x00000010 +#define SGMII_RESET_HW_RX_125M_N_GET(x) (((x) & SGMII_RESET_HW_RX_125M_N_MASK) >> SGMII_RESET_HW_RX_125M_N_LSB) +#define SGMII_RESET_HW_RX_125M_N_SET(x) (((x) << SGMII_RESET_HW_RX_125M_N_LSB) & SGMII_RESET_HW_RX_125M_N_MASK) +#define SGMII_RESET_HW_RX_125M_N_RESET 0x0 // 0 +#define SGMII_RESET_TX_125M_N_MSB 3 +#define SGMII_RESET_TX_125M_N_LSB 3 +#define SGMII_RESET_TX_125M_N_MASK 0x00000008 +#define SGMII_RESET_TX_125M_N_GET(x) (((x) & SGMII_RESET_TX_125M_N_MASK) >> SGMII_RESET_TX_125M_N_LSB) +#define SGMII_RESET_TX_125M_N_SET(x) (((x) << SGMII_RESET_TX_125M_N_LSB) & SGMII_RESET_TX_125M_N_MASK) +#define SGMII_RESET_TX_125M_N_RESET 0x0 // 0 +#define SGMII_RESET_RX_125M_N_MSB 2 +#define SGMII_RESET_RX_125M_N_LSB 2 +#define SGMII_RESET_RX_125M_N_MASK 0x00000004 +#define SGMII_RESET_RX_125M_N_GET(x) (((x) & SGMII_RESET_RX_125M_N_MASK) >> SGMII_RESET_RX_125M_N_LSB) +#define SGMII_RESET_RX_125M_N_SET(x) (((x) << SGMII_RESET_RX_125M_N_LSB) & SGMII_RESET_RX_125M_N_MASK) +#define SGMII_RESET_RX_125M_N_RESET 0x0 // 0 +#define SGMII_RESET_TX_CLK_N_MSB 1 +#define SGMII_RESET_TX_CLK_N_LSB 1 +#define SGMII_RESET_TX_CLK_N_MASK 0x00000002 +#define SGMII_RESET_TX_CLK_N_GET(x) (((x) & SGMII_RESET_TX_CLK_N_MASK) >> SGMII_RESET_TX_CLK_N_LSB) +#define SGMII_RESET_TX_CLK_N_SET(x) (((x) << SGMII_RESET_TX_CLK_N_LSB) & SGMII_RESET_TX_CLK_N_MASK) +#define SGMII_RESET_TX_CLK_N_RESET 0x0 // 0 +#define SGMII_RESET_RX_CLK_N_MSB 0 +#define SGMII_RESET_RX_CLK_N_LSB 0 +#define SGMII_RESET_RX_CLK_N_MASK 0x00000001 +#define SGMII_RESET_RX_CLK_N_GET(x) (((x) & SGMII_RESET_RX_CLK_N_MASK) >> SGMII_RESET_RX_CLK_N_LSB) +#define SGMII_RESET_RX_CLK_N_SET(x) (((x) << SGMII_RESET_RX_CLK_N_LSB) & SGMII_RESET_RX_CLK_N_MASK) +#define SGMII_RESET_RX_CLK_N_RESET 0x0 // 0 +#define SGMII_RESET_ADDRESS 0x18070014 + + + +// 32'h18070038 (SGMII_MAC_RX_CONFIG) +#define SGMII_MAC_RX_CONFIG_LINK_MSB 15 +#define SGMII_MAC_RX_CONFIG_LINK_LSB 15 +#define SGMII_MAC_RX_CONFIG_LINK_MASK 0x00008000 +#define SGMII_MAC_RX_CONFIG_LINK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_LINK_MASK) >> SGMII_MAC_RX_CONFIG_LINK_LSB) +#define SGMII_MAC_RX_CONFIG_LINK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_LINK_LSB) & SGMII_MAC_RX_CONFIG_LINK_MASK) +#define SGMII_MAC_RX_CONFIG_LINK_RESET 0x0 // 0 +#define SGMII_MAC_RX_CONFIG_ACK_MSB 14 +#define SGMII_MAC_RX_CONFIG_ACK_LSB 14 +#define SGMII_MAC_RX_CONFIG_ACK_MASK 0x00004000 +#define SGMII_MAC_RX_CONFIG_ACK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ACK_MASK) >> SGMII_MAC_RX_CONFIG_ACK_LSB) +#define SGMII_MAC_RX_CONFIG_ACK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ACK_LSB) & SGMII_MAC_RX_CONFIG_ACK_MASK) +#define SGMII_MAC_RX_CONFIG_ACK_RESET 0x0 // 0 +#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MSB 12 +#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB 12 +#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK 0x00001000 +#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK) >> SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB) +#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK) +#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_RESET 0x0 // 0 +#define SGMII_MAC_RX_CONFIG_SPEED_MODE_MSB 11 +#define SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB 10 +#define SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK 0x00000c00 +#define SGMII_MAC_RX_CONFIG_SPEED_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK) >> SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB) +#define SGMII_MAC_RX_CONFIG_SPEED_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK) +#define SGMII_MAC_RX_CONFIG_SPEED_MODE_RESET 0x0 // 0 +#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MSB 8 +#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB 8 +#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK 0x00000100 +#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB) +#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK) +#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_RESET 0x0 // 0 +#define SGMII_MAC_RX_CONFIG_PAUSE_MSB 7 +#define SGMII_MAC_RX_CONFIG_PAUSE_LSB 7 +#define SGMII_MAC_RX_CONFIG_PAUSE_MASK 0x00000080 +#define SGMII_MAC_RX_CONFIG_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_PAUSE_LSB) +#define SGMII_MAC_RX_CONFIG_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_PAUSE_MASK) +#define SGMII_MAC_RX_CONFIG_PAUSE_RESET 0x0 // 0 +#define SGMII_MAC_RX_CONFIG_RES0_MSB 0 +#define SGMII_MAC_RX_CONFIG_RES0_LSB 0 +#define SGMII_MAC_RX_CONFIG_RES0_MASK 0x00000001 +#define SGMII_MAC_RX_CONFIG_RES0_GET(x) (((x) & SGMII_MAC_RX_CONFIG_RES0_MASK) >> SGMII_MAC_RX_CONFIG_RES0_LSB) +#define SGMII_MAC_RX_CONFIG_RES0_SET(x) (((x) << SGMII_MAC_RX_CONFIG_RES0_LSB) & SGMII_MAC_RX_CONFIG_RES0_MASK) +#define SGMII_MAC_RX_CONFIG_RES0_RESET 0x1 // 1 +#define SGMII_MAC_RX_CONFIG_ADDRESS 0x18070038 + +// 32'h18070058 (SGMII_DEBUG) +#define SGMII_DEBUG_ARB_STATE_MSB 27 +#define SGMII_DEBUG_ARB_STATE_LSB 24 +#define SGMII_DEBUG_ARB_STATE_MASK 0x0f000000 +#define SGMII_DEBUG_ARB_STATE_GET(x) (((x) & SGMII_DEBUG_ARB_STATE_MASK) >> SGMII_DEBUG_ARB_STATE_LSB) +#define SGMII_DEBUG_ARB_STATE_SET(x) (((x) << SGMII_DEBUG_ARB_STATE_LSB) & SGMII_DEBUG_ARB_STATE_MASK) +#define SGMII_DEBUG_ARB_STATE_RESET 0x0 // 0 +#define SGMII_DEBUG_RX_SYNC_STATE_MSB 23 +#define SGMII_DEBUG_RX_SYNC_STATE_LSB 16 +#define SGMII_DEBUG_RX_SYNC_STATE_MASK 0x00ff0000 +#define SGMII_DEBUG_RX_SYNC_STATE_GET(x) (((x) & SGMII_DEBUG_RX_SYNC_STATE_MASK) >> SGMII_DEBUG_RX_SYNC_STATE_LSB) +#define SGMII_DEBUG_RX_SYNC_STATE_SET(x) (((x) << SGMII_DEBUG_RX_SYNC_STATE_LSB) & SGMII_DEBUG_RX_SYNC_STATE_MASK) +#define SGMII_DEBUG_RX_SYNC_STATE_RESET 0x0 // 0 +#define SGMII_DEBUG_RX_STATE_MSB 15 +#define SGMII_DEBUG_RX_STATE_LSB 8 +#define SGMII_DEBUG_RX_STATE_MASK 0x0000ff00 +#define SGMII_DEBUG_RX_STATE_GET(x) (((x) & SGMII_DEBUG_RX_STATE_MASK) >> SGMII_DEBUG_RX_STATE_LSB) +#define SGMII_DEBUG_RX_STATE_SET(x) (((x) << SGMII_DEBUG_RX_STATE_LSB) & SGMII_DEBUG_RX_STATE_MASK) +#define SGMII_DEBUG_RX_STATE_RESET 0x0 // 0 +#define SGMII_DEBUG_TX_STATE_MSB 7 +#define SGMII_DEBUG_TX_STATE_LSB 0 +#define SGMII_DEBUG_TX_STATE_MASK 0x000000ff +#define SGMII_DEBUG_TX_STATE_GET(x) (((x) & SGMII_DEBUG_TX_STATE_MASK) >> SGMII_DEBUG_TX_STATE_LSB) +#define SGMII_DEBUG_TX_STATE_SET(x) (((x) << SGMII_DEBUG_TX_STATE_LSB) & SGMII_DEBUG_TX_STATE_MASK) +#define SGMII_DEBUG_TX_STATE_RESET 0x0 // 0 +#define SGMII_DEBUG_ADDRESS 0x18070058 +#define SGMII_DEBUG_OFFSET 0x0058 + + + +// 32'h18070060 (SGMII_INTERRUPT_MASK) +#define SGMII_INTERRUPT_MASK_MASK_MSB 7 +#define SGMII_INTERRUPT_MASK_MASK_LSB 0 +#define SGMII_INTERRUPT_MASK_MASK_MASK 0x000000ff +#define SGMII_INTERRUPT_MASK_MASK_GET(x) (((x) & SGMII_INTERRUPT_MASK_MASK_MASK) >> SGMII_INTERRUPT_MASK_MASK_LSB) +#define SGMII_INTERRUPT_MASK_MASK_SET(x) (((x) << SGMII_INTERRUPT_MASK_MASK_LSB) & SGMII_INTERRUPT_MASK_MASK_MASK) +#define SGMII_INTERRUPT_MASK_MASK_RESET 0x0 // 0 +#define SGMII_INTERRUPT_MASK_ADDRESS 0x18070060 + + + + +// 32'h1807005c (SGMII_INTERRUPT) +#define SGMII_INTERRUPT_INTR_MSB 7 +#define SGMII_INTERRUPT_INTR_LSB 0 +#define SGMII_INTERRUPT_INTR_MASK 0x000000ff +#define SGMII_INTERRUPT_INTR_GET(x) (((x) & SGMII_INTERRUPT_INTR_MASK) >> SGMII_INTERRUPT_INTR_LSB) +#define SGMII_INTERRUPT_INTR_SET(x) (((x) << SGMII_INTERRUPT_INTR_LSB) & SGMII_INTERRUPT_INTR_MASK) +#define SGMII_INTERRUPT_INTR_RESET 0x0 // 0 +#define SGMII_INTERRUPT_ADDRESS 0x1807005c +#define SGMII_INTERRUPT_OFFSET 0x005c +// SW modifiable bits +#define SGMII_INTERRUPT_SW_MASK 0x000000ff +// bits defined at reset +#define SGMII_INTERRUPT_RSTMASK 0xffffffff +// reset value (ignore bits undefined at reset) +#define SGMII_INTERRUPT_RESET 0x00000000 + +// 32'h18070060 (SGMII_INTERRUPT_MASK) +#define SGMII_INTERRUPT_MASK_MASK_MSB 7 +#define SGMII_INTERRUPT_MASK_MASK_LSB 0 +#define SGMII_INTERRUPT_MASK_MASK_MASK 0x000000ff +#define SGMII_INTERRUPT_MASK_MASK_GET(x) (((x) & SGMII_INTERRUPT_MASK_MASK_MASK) >> SGMII_INTERRUPT_MASK_MASK_LSB) +#define SGMII_INTERRUPT_MASK_MASK_SET(x) (((x) << SGMII_INTERRUPT_MASK_MASK_LSB) & SGMII_INTERRUPT_MASK_MASK_MASK) +#define SGMII_INTERRUPT_MASK_MASK_RESET 0x0 // 0 +#define SGMII_INTERRUPT_MASK_ADDRESS 0x18070060 + + +#define SGMII_LINK_FAIL (1 << 0) +#define SGMII_DUPLEX_ERR (1 << 1) +#define SGMII_MR_AN_COMPLETE (1 << 2) +#define SGMII_LINK_MAC_CHANGE (1 << 3) +#define SGMII_DUPLEX_MODE_CHANGE (1 << 4) +#define SGMII_SPEED_MODE_MAC_CHANGE (1 << 5) +#define SGMII_RX_QUIET_CHANGE (1 << 6) +#define SGMII_RX_MDIO_COMP_CHANGE (1 << 7) + +#define SGMII_INTR SGMII_LINK_FAIL | \ + SGMII_LINK_MAC_CHANGE | \ + SGMII_DUPLEX_MODE_CHANGE | \ + SGMII_SPEED_MODE_MAC_CHANGE + + +// 32'h18050048 (ETH_SGMII) +#define ETH_SGMII_TX_INVERT_MSB 31 +#define ETH_SGMII_TX_INVERT_LSB 31 +#define ETH_SGMII_TX_INVERT_MASK 0x80000000 +#define ETH_SGMII_TX_INVERT_GET(x) (((x) & ETH_SGMII_TX_INVERT_MASK) >> ETH_SGMII_TX_INVERT_LSB) +#define ETH_SGMII_TX_INVERT_SET(x) (((x) << ETH_SGMII_TX_INVERT_LSB) & ETH_SGMII_TX_INVERT_MASK) +#define ETH_SGMII_TX_INVERT_RESET 0x0 // 0 +#define ETH_SGMII_GIGE_QUAD_MSB 30 +#define ETH_SGMII_GIGE_QUAD_LSB 30 +#define ETH_SGMII_GIGE_QUAD_MASK 0x40000000 +#define ETH_SGMII_GIGE_QUAD_GET(x) (((x) & ETH_SGMII_GIGE_QUAD_MASK) >> ETH_SGMII_GIGE_QUAD_LSB) +#define ETH_SGMII_GIGE_QUAD_SET(x) (((x) << ETH_SGMII_GIGE_QUAD_LSB) & ETH_SGMII_GIGE_QUAD_MASK) +#define ETH_SGMII_GIGE_QUAD_RESET 0x0 // 0 +#define ETH_SGMII_RX_DELAY_MSB 29 +#define ETH_SGMII_RX_DELAY_LSB 28 +#define ETH_SGMII_RX_DELAY_MASK 0x30000000 +#define ETH_SGMII_RX_DELAY_GET(x) (((x) & ETH_SGMII_RX_DELAY_MASK) >> ETH_SGMII_RX_DELAY_LSB) +#define ETH_SGMII_RX_DELAY_SET(x) (((x) << ETH_SGMII_RX_DELAY_LSB) & ETH_SGMII_RX_DELAY_MASK) +#define ETH_SGMII_RX_DELAY_RESET 0x0 // 0 +#define ETH_SGMII_TX_DELAY_MSB 27 +#define ETH_SGMII_TX_DELAY_LSB 26 +#define ETH_SGMII_TX_DELAY_MASK 0x0c000000 +#define ETH_SGMII_TX_DELAY_GET(x) (((x) & ETH_SGMII_TX_DELAY_MASK) >> ETH_SGMII_TX_DELAY_LSB) +#define ETH_SGMII_TX_DELAY_SET(x) (((x) << ETH_SGMII_TX_DELAY_LSB) & ETH_SGMII_TX_DELAY_MASK) +#define ETH_SGMII_TX_DELAY_RESET 0x0 // 0 +#define ETH_SGMII_CLK_SEL_MSB 25 +#define ETH_SGMII_CLK_SEL_LSB 25 +#define ETH_SGMII_CLK_SEL_MASK 0x02000000 +#define ETH_SGMII_CLK_SEL_GET(x) (((x) & ETH_SGMII_CLK_SEL_MASK) >> ETH_SGMII_CLK_SEL_LSB) +#define ETH_SGMII_CLK_SEL_SET(x) (((x) << ETH_SGMII_CLK_SEL_LSB) & ETH_SGMII_CLK_SEL_MASK) +#define ETH_SGMII_CLK_SEL_RESET 0x1 // 1 +#define ETH_SGMII_GIGE_MSB 24 +#define ETH_SGMII_GIGE_LSB 24 +#define ETH_SGMII_GIGE_MASK 0x01000000 +#define ETH_SGMII_GIGE_GET(x) (((x) & ETH_SGMII_GIGE_MASK) >> ETH_SGMII_GIGE_LSB) +#define ETH_SGMII_GIGE_SET(x) (((x) << ETH_SGMII_GIGE_LSB) & ETH_SGMII_GIGE_MASK) +#define ETH_SGMII_GIGE_RESET 0x1 // 1 +#define ETH_SGMII_PHASE1_COUNT_MSB 15 +#define ETH_SGMII_PHASE1_COUNT_LSB 8 +#define ETH_SGMII_PHASE1_COUNT_MASK 0x0000ff00 +#define ETH_SGMII_PHASE1_COUNT_GET(x) (((x) & ETH_SGMII_PHASE1_COUNT_MASK) >> ETH_SGMII_PHASE1_COUNT_LSB) +#define ETH_SGMII_PHASE1_COUNT_SET(x) (((x) << ETH_SGMII_PHASE1_COUNT_LSB) & ETH_SGMII_PHASE1_COUNT_MASK) +#define ETH_SGMII_PHASE1_COUNT_RESET 0x1 // 1 +#define ETH_SGMII_PHASE0_COUNT_MSB 7 +#define ETH_SGMII_PHASE0_COUNT_LSB 0 +#define ETH_SGMII_PHASE0_COUNT_MASK 0x000000ff +#define ETH_SGMII_PHASE0_COUNT_GET(x) (((x) & ETH_SGMII_PHASE0_COUNT_MASK) >> ETH_SGMII_PHASE0_COUNT_LSB) +#define ETH_SGMII_PHASE0_COUNT_SET(x) (((x) << ETH_SGMII_PHASE0_COUNT_LSB) & ETH_SGMII_PHASE0_COUNT_MASK) +#define ETH_SGMII_PHASE0_COUNT_RESET 0x1 // 1 +#define ETH_SGMII_ADDRESS 0x18050048 + +#endif /* _QCA953X_H */ diff --git a/u-boot/include/atheros.h b/u-boot/include/atheros.h new file mode 100755 index 0000000..e4af1e0 --- /dev/null +++ b/u-boot/include/atheros.h @@ -0,0 +1,362 @@ +/* + * vim: tabstop=8 : noexpandtab + */ + +/* + * Copyright (c) 2013 Qualcomm Atheros, Inc. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _ATHEROS_H +#define _ATHEROS_H + +/* + * Set everything to zero. The corresponding header will + * undef and re-define the appropriate ones + */ +#define is_ar7100() (0) + + +#define is_ar7240() (0) +#define is_ar7241() (0) +#define is_ar7242() (0) + +#define is_ar9330() (0) +#define is_ar933x() (0) +#define is_hornet() (0) + +#define is_ar934x() (0) +#define is_wasp() (0) + +#define is_qca955x() (0) +#define is_sco() (0) + +#define is_qca953x() (0) +#define is_hb() (0) + +#define is_qca956x() (0) + +#define ATH_CONSOLE_BAUD 115200 + +#define AR7240_REV_1_2 0xc2 + +#ifdef CONFIG_ATH_EMULATION +#define is_emu() (1) +#else +#define is_emu() (0) +#endif + +#ifdef CONFIG_F1E_PHY +#define is_f1e() 1 +#else +#define is_f1e() 0 +#endif +#ifdef CONFIG_F2E_PHY +#define is_f2e() 1 +#else +#define is_f2e() 0 +#endif +#ifdef CONFIG_ATHRS16_PHY +#define is_s16() 1 +#else +#define is_s16() 0 +#endif + +#ifdef CONFIG_ATHRS17_PHY +#define is_s17() 1 +#else +#define is_s17() 0 +#endif + +#ifdef CONFIG_ATHR_8033_PHY +#define is_ar8033() 1 +#else +#define is_ar8033() 0 +#endif + +#ifdef CONFIG_VIR_PHY +#define is_vir_phy() 1 +#else +#define is_vir_phy() 0 +#endif + +#ifdef CFG_ATHRS27_PHY +#define is_s27() 1 +#else +#define is_s27() 0 +#endif + +#define ath_arch_init_irq() /* nothing */ + +#ifndef __ASSEMBLY__ + +int ath_uart_freq(void); + +typedef unsigned int ath_reg_t; + +#ifdef COMPRESSED_UBOOT +# define prmsg(...) +#else +# define prmsg printf +#endif + +#endif /* __ASSEMBLY__ */ + +#define ath_reg_rd(_phys) (*(volatile ath_reg_t *)KSEG1ADDR(_phys)) + +#define ath_reg_wr_nf(_phys, _val) \ + ((*(volatile ath_reg_t *)KSEG1ADDR(_phys)) = (_val)) + +#define ath_reg_wr(_phys, _val) do { \ + ath_reg_wr_nf(_phys, _val); \ + ath_reg_rd(_phys); \ +} while(0) + +#define ath_reg_rmw_set(_reg, _mask) do { \ + ath_reg_wr((_reg), (ath_reg_rd((_reg)) | (_mask))); \ + ath_reg_rd((_reg)); \ +} while(0) + +#define ath_reg_rmw_clear(_reg, _mask) do { \ + ath_reg_wr((_reg), (ath_reg_rd((_reg)) & ~(_mask))); \ + ath_reg_rd((_reg)); \ +} while(0) + +#define ath_uart_rd(y) ath_reg_rd((ATH_UART_BASE+y)) +#define ath_uart_wr(x, z) ath_reg_wr((ATH_UART_BASE+x), z) + +#define REG_OFFSET 4 + +#define OFS_RCV_BUFFER (0 * REG_OFFSET) +#define OFS_TRANS_HOLD (0 * REG_OFFSET) +#define OFS_SEND_BUFFER (0 * REG_OFFSET) +#define OFS_INTR_ENABLE (1 * REG_OFFSET) +#define OFS_INTR_ID (2 * REG_OFFSET) +#define OFS_DATA_FORMAT (3 * REG_OFFSET) +#define OFS_LINE_CONTROL (3 * REG_OFFSET) +#define OFS_MODEM_CONTROL (4 * REG_OFFSET) +#define OFS_RS232_OUTPUT (4 * REG_OFFSET) +#define OFS_LINE_STATUS (5 * REG_OFFSET) +#define OFS_MODEM_STATUS (6 * REG_OFFSET) +#define OFS_RS232_INPUT (6 * REG_OFFSET) +#define OFS_SCRATCH_PAD (7 * REG_OFFSET) + +#define OFS_DIVISOR_LSB (0 * REG_OFFSET) +#define OFS_DIVISOR_MSB (1 * REG_OFFSET) + +/* + * PLL Config for different CPU/DDR/AHB frequencies + */ +#define CFG_PLL_720_600_200 0x01 +#define CFG_PLL_720_680_240 0x02 +#define CFG_PLL_720_600_240 0x03 +#define CFG_PLL_680_680_226 0x04 +#define CFG_PLL_720_600_300 0x05 +#define CFG_PLL_400_400_200 0x06 +#define CFG_PLL_560_450_220 0x07 +#define CFG_PLL_550_400_200 0x08 +#define CFG_PLL_550_600_200 0x09 +#define CFG_PLL_600_600_200 0x0a +#define CFG_PLL_750_400_250 0x0b +#define CFG_PLL_800_400_266 0x0c +#define CFG_PLL_750_667_250 0x0d +#define CFG_PLL_800_600_266 0x0e +#define CFG_PLL_800_667_266 0x0f +#define CFG_PLL_810_700_270 0x10 +#define CFG_PLL_810_666_270 0x11 +#define CFG_PLL_775_650_258 0x12 +#define CFG_PLL_650_400_200 0x13 +#define CFG_PLL_650_600_200 0x14 + +#define UBOOT_SIZE (256 * 1024) +#define PLL_FLASH_ADDR (CFG_FLASH_BASE + UBOOT_SIZE) +#define PLL_CONFIG_VAL_F (PLL_FLASH_ADDR + CFG_FLASH_SECTOR_SIZE - 0x20) +#define PLL_MAGIC 0xaabbccdd +#define SRIF_PLL_CONFIG_VAL_F (PLL_CONFIG_VAL_F - 12) +#define SRIF_PLL_MAGIC 0x73726966 /* srif */ + +#include + +#if defined(CONFIG_MACH_AR724x) +# include <724x.h> +#elif defined(CONFIG_MACH_AR933x) +# include <933x.h> +#elif defined(CONFIG_MACH_AR934x) +# include <934x.h> +#elif defined(CONFIG_MACH_QCA955x) +# include <955x.h> +#elif defined(CONFIG_MACH_QCA953x) +# include <953x.h> +#elif defined(CONFIG_MACH_QCA956x) +# include <956x.h> +#else +# error "Building U-Boot for unknown device" +#endif + +#ifndef __ASSEMBLY__ + +#define ATH_MEM_SDRAM 1 +#define ATH_MEM_DDR1 2 +#define ATH_MEM_DDR2 3 +/* + * GPIO Access & Control + */ +void ath_gpio_init(void); +void ath_gpio_down(void); +void ath_gpio_up(void); + +void ath_gpio_irq_init(int); +/* + * GPIO Helper Functions + */ +void ath_gpio_enable_slic(void); + +/* enable UART block, takes away GPIO 10 and 9 */ +void ath_gpio_enable_uart(void); + +/* enable STEREO block, takes away GPIO 11,8,7, and 6 */ +void ath_gpio_enable_stereo(void); + +/* allow CS0/CS1 to be controlled via SPI register, takes away GPIO0/GPIO1 */ +void ath_gpio_enable_spi_cs1_cs0(void); + +/* allow GPIO0/GPIO1 to be used as SCL/SDA for software based i2c */ +void ath_gpio_enable_i2c_on_gpio_0_1(void); + +/* + * GPIO General Functions + */ +void ath_gpio_drive_low(unsigned int mask); +void ath_gpio_drive_high(unsigned int mask); + +unsigned int ath_gpio_float_high_test(unsigned int mask); + +/* Functions to access SPI through software. Example: + * + * ath_spi_down(); ---------------------- disable others from accessing SPI bus taking semaphore + * ath_spi_enable_soft_access(); -------- disable HW control of SPI + * + * + * + * + * + * + * + * ath_spi_disable_soft_acess(); ------- enable HW control of SPI bus + * ath_spi_up(); ----------------------- enable others to access SPI bus releasing semaphore + */ +void ath_spi_init(void); +void ath_spi_down(void); +void ath_spi_up(void); + +static inline void +ath_spi_enable_soft_access(void) +{ + ath_reg_wr_nf(ATH_SPI_FS, 1); +} + +static inline void +ath_spi_disable_soft_access(void) +{ + ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_DIS); + ath_reg_wr_nf(ATH_SPI_FS, 0); +} + +void ath_spi_raw_output_u8(unsigned char val); +void ath_spi_raw_output_u32(unsigned int val); +unsigned int ath_spi_raw_input_u8(void); +unsigned int ath_spi_raw_input_u32(void); + +void ath_spi_flash_read_page(unsigned int addr, unsigned char *data, int len); +void ath_spi_flash_write_page(unsigned int addr, unsigned char *data, int len); +void ath_spi_flash_sector_erase(unsigned int addr); + +/* + * Allow access to cs0-2 when GPIO Function enables cs0-2 through SPI register. + */ +static inline void +ath_spi_enable_cs0(void) +{ + unsigned int cs; + ath_spi_down(); + ath_spi_enable_soft_access(); + cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS; + ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_0 | cs); +} + +static inline void +ath_spi_enable_cs1(void) +{ + unsigned int cs; +#if defined(CONFIG_MACH_AR934x) || \ + defined(CONFIG_MACH_QCA955x) + ath_spi_down(); + ath_spi_init(); + ath_spi_enable_soft_access(); + cs = ath_reg_rd(ATH_SPI_WRITE) & ATH_SPI_CS_DIS; + ath_reg_wr_nf(ATH_SPI_WRITE, cs | ATH_SPI_CLK_HIGH); + cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS; + ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs | ATH_SPI_CLK_HIGH); + ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs); +#else + ath_spi_down(); + ath_spi_enable_soft_access(); + cs = ath_reg_rd(ATH_SPI_WRITE) & ~ATH_SPI_CS_DIS; + ath_reg_wr_nf(ATH_SPI_WRITE, ATH_SPI_CS_ENABLE_1 | cs); +#endif +} + +static inline void +ath_spi_disable_cs(void) +{ + unsigned int cs = ath_reg_rd(ATH_SPI_WRITE) | ATH_SPI_CS_DIS; + ath_reg_wr_nf(ATH_SPI_WRITE, cs); + ath_spi_disable_soft_access(); + ath_spi_up(); +} + +/* + * Example usage to access BOOT flash + */ +static inline void +ath_spi_flash_cs0_sector_erase(unsigned int addr) +{ + ath_spi_enable_cs0(); + ath_spi_flash_sector_erase(addr); + ath_spi_disable_cs(); +} + +static inline void +ath_spi_flash_cs0_write_page(unsigned int addr, unsigned char *data, int len) +{ + ath_spi_enable_cs0(); + ath_spi_flash_write_page(addr, data, len); + ath_spi_disable_cs(); +} + +#endif /* __ASSEMBLY__ */ + + +#endif /* _ATHEROS_H */ diff --git a/u-boot/include/configs/ap143.h b/u-boot/include/configs/ap143.h new file mode 100644 index 0000000..5ab7625 --- /dev/null +++ b/u-boot/include/configs/ap143.h @@ -0,0 +1,201 @@ +/* + * This file contains the configuration parameters for the DB12x (AR9344) board. + */ + +#ifndef _AP143_CONFIG_H +#define _AP143_CONFIG_H + +#include +#include + +/* + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash +#define CFG_FLASH_SECTOR_SIZE 64 * 1024 +/* + * We boot from this flash + */ +#define CFG_FLASH_BASE 0x9F000000 +#ifdef COMPRESSED_UBOOT + #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE + #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE +#endif + +/* + * The following #defines are needed to get flash environment right + */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +/* + * Default bootargs + */ +#undef CONFIG_BOOTARGS +#if defined(CONFIG_FOR_TPLINK_WR820N_CH) +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)" +#endif + +/* + * Other env default values + */ +#undef CONFIG_BOOTFILE +#define CONFIG_BOOTFILE "firmware.bin" + +#undef CONFIG_LOADADDR +#define CONFIG_LOADADDR 0x80800000 + +#define CFG_LOAD_ADDR 0x9F020000 +#define UPDATE_SCRIPT_FW_ADDR "0x9F020000" +#define CONFIG_BOOTCOMMAND "bootm 0x9F020000" + + +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.2 + +#undef CFG_PLL_FREQ +#undef CFG_HZ + +// CPU-RAM-AHB frequency setting +//#define CFG_PLL_FREQ CFG_PLL_650_400_200 +//#define CFG_PLL_FREQ 0x13 +#define CFG_HZ_FALLBACK (650000000LU/2) + +#define CFG_HZ bd->bi_cfg_hz +#define AR7240_SPI_CONTROL 0x43 +#define AR7240_SPI_CONTROL_DEFAULT AR7240_SPI_CONTROL +/* + * MIPS32 24K Processor Core Family Software User's Manual + * + * 6.2.9 Count Register (CP0 Register 9, Select 0) + * The Count register acts as a timer, incrementing at a constant + * rate, whether or not an instruction is executed, retired, or + * any forward progress is made through the pipeline. The counter + * increments every other clock, if the DC bit in the Cause register + * is 0. + * + * Since the count is incremented every other tick, divide by 2 + * XXX derive this from CFG_PLL_FREQ + */ + + + +/* + * Address and size of Primary Environment Sector + */ +#define CFG_ENV_IS_IN_FLASH 1 +#undef CFG_ENV_IS_NOWHERE + +#define CFG_ENV_ADDR 0x9F01EC00 +#define CFG_ENV_SIZE 0x1000 +#define CFG_ENV_SECT_SIZE 0x10000 + +/* + * Available commands + */ +#define CONFIG_COMMANDS (CFG_CMD_MEMORY | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_FLASH | \ + CFG_CMD_NET | \ + CFG_CMD_RUN | \ + CFG_CMD_DATE | \ + CFG_CMD_SNTP | \ + CFG_CMD_ECHO | \ + CFG_CMD_BOOTD | \ + CFG_CMD_ITEST | \ + CFG_CMD_ENV | \ + CFG_CMD_LOADB) + +// Enable NetConsole and custom NetConsole port +#define CONFIG_NETCONSOLE +#define CONFIG_NETCONSOLE_PORT 6666 + + + + + + + +/*modify from 0x4138 to 0x40c3, ddr refresh interval: 12uS to 7.8uS. by wkp + from Li Guanwen, 30Dec14. */ +//#define CFG_DDR_REFRESH_VAL 0x40c3 (??????????????????) +#define CFG_DDR_REFRESH_VAL 0x4138 + + + + + + +/* + * Web Failsafe configuration + */ +#define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR +#define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE + +// Firmware partition offset +#define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000 + +// U-Boot partition size +#define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (CONFIG_MAX_UBOOT_SIZE_KB * 1024) + +// TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB +#define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x1EC00" +#define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "0x20000" + +// ART partition size +#define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024) + +// max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES) +// TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART) +#define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024) + +// progress state info +#define WEBFAILSAFE_PROGRESS_START 0 +#define WEBFAILSAFE_PROGRESS_TIMEOUT 1 +#define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2 +#define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3 +#define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4 + +// update type +#define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0 +#define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1 +#define WEBFAILSAFE_UPGRADE_TYPE_ART 2 + +/*-----------------------------------------------------------------------*/ + +/* + * Additional environment variables for simple upgrades + */ +//#define CONFIG_EXTRA_ENV_SETTINGS SILENT_ENV_VARIABLE + +/* + * Cache lock for stack + */ +#define CFG_INIT_SP_OFFSET 0x1000 +#define CONFIG_INIT_SRAM_SP_OFFSET 0xbd001800 + +/* For Merlin, both PCI, PCI-E interfaces are valid */ +#define ATH_ART_PCICFG_OFFSET 12 +/* use eth1(LAN) as the net interface */ +#define CONFIG_AG7240_SPEPHY +#define CONFIG_NET_MULTI +#define CONFIG_PCI 1 +#define WLANCAL 0x9fff1000 +#define BOARDCAL 0x9fff0000 +#define CFG_MII0_RMII 1 +#define CFG_BOOTM_LEN (16 << 20) /* 16 MB */ + +#undef DEBUG + +/* MAC address, model and PIN number offsets in FLASH */ +#define OFFSET_MAC_DATA_BLOCK 0x010000 +#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 +#define OFFSET_MAC_ADDRESS 0x00FC00 +#define OFFSET_ROUTER_MODEL 0x00FD00 +#define OFFSET_PIN_NUMBER 0x00FE00 + +#include + +#endif /* __AP143_CONFIG_H */ diff --git a/u-boot/net/eth.c b/u-boot/net/eth.c index 93b14a1..a33a911 100644 --- a/u-boot/net/eth.c +++ b/u-boot/net/eth.c @@ -27,7 +27,11 @@ #include #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) -extern int ag7240_enet_initialize(bd_t * bis); +#if defined(CONFIG_ATHEROS) + extern int ath_gmac_enet_initialize(bd_t * bis); +#else + extern int ag7240_enet_initialize(bd_t * bis); +#endif /* static struct eth_device *eth_devices, *eth_current; @@ -120,7 +124,11 @@ int eth_initialize(bd_t *bis){ #endif // ag7240 initialization +#if defined(CONFIG_ATHEROS) + ath_gmac_enet_initialize(bis); +#else ag7240_enet_initialize(bis); +#endif if(!eth_devices){ puts("## Error: no ethernet found\n"); -- 2.25.1