From eb5394120643922626f18e5fe7b0b3dc0ed43b9a Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 8 Oct 2012 07:44:25 +0000 Subject: [PATCH] powerpc/mpc85xx: software workaround for DDR erratum A-004468 Boot space translation utilizes the pre-translation address to select the DDR controller target. However, the post-translation address will be presented to the selected DDR controller. It is possible that the pre- translation address selects one DDR controller but the post-translation address exists in a different DDR controller when using certain DDR controller interleaving modes. The device may fail to boot under these circumstances. Note that a DDR MSE error will not be detected since DDR controller bounds registers are programmed to be the same when configured for DDR controller interleaving. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 + arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- arch/powerpc/cpu/mpc85xx/mp.c | 96 ++++++++++++++++++++--- arch/powerpc/cpu/mpc86xx/fdt.c | 2 +- arch/powerpc/cpu/mpc86xx/mp.c | 9 ++- arch/powerpc/cpu/mpc8xxx/ddr/util.c | 10 +++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + arch/powerpc/include/asm/mp.h | 2 +- arch/powerpc/lib/board.c | 4 +- 9 files changed, 111 insertions(+), 18 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index bc7e5e36e2..ce5924bc13 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -76,6 +76,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) puts("Work-around for Erratum ESDHC111 enabled\n"); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A004468 + puts("Work-around for Erratum A004468 enabled\n"); +#endif #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) puts("Work-around for Erratum ESDHC135 enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index d54527aa47..8221481359 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -48,7 +48,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) { int off; ulong spin_tbl_addr = get_spin_phys_addr(); - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); u32 id = get_my_id(); const char *enable_method; diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index ffc2a9ad65..39adf8e887 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -27,9 +27,11 @@ #include #include #include +#include #include "mp.h" DECLARE_GLOBAL_DATA_PTR; +u32 fsl_ddr_get_intl3r(void); u32 get_my_id() { @@ -191,13 +193,68 @@ int cpu_release(int nr, int argc, char * const argv[]) return 0; } -u32 determine_mp_bootpg(void) +u32 determine_mp_bootpg(unsigned int *pagesize) { + u32 bootpg; +#ifdef CONFIG_SYS_FSL_ERRATUM_A004468 + u32 svr = get_svr(); + u32 granule_size, check; + struct law_entry e; +#endif + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ if ((u64)gd->ram_size > 0xfffff000) - return (0xfffff000); + bootpg = 0xfffff000; + else + bootpg = gd->ram_size - 4096; + if (pagesize) + *pagesize = 4096; + +#ifdef CONFIG_SYS_FSL_ERRATUM_A004468 +/* + * Erratum A004468 has two parts. The 3-way interleaving applies to T4240, + * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But + * the way boot page chosen in u-boot avoids hitting this erratum. So only + * thw workaround for 3-way interleaving is needed. + * + * To make sure boot page translation works with 3-Way DDR interleaving + * enforce a check for the following constrains + * 8K granule size requires BRSIZE=8K and + * bootpg >> log2(BRSIZE) %3 == 1 + * 4K and 1K granule size requires BRSIZE=4K and + * bootpg >> log2(BRSIZE) %3 == 0 + */ + if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) { + e = find_law(bootpg); + switch (e.trgt_id) { + case LAW_TRGT_IF_DDR_INTLV_123: + granule_size = fsl_ddr_get_intl3r() & 0x1f; + if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) { + if (pagesize) + *pagesize = 8192; + bootpg &= 0xffffe000; /* align to 8KB */ + check = bootpg >> 13; + while ((check % 3) != 1) + check--; + bootpg = check << 13; + debug("Boot page (8K) at 0x%08x\n", bootpg); + break; + } else { + bootpg &= 0xfffff000; /* align to 4KB */ + check = bootpg >> 12; + while ((check % 3) != 0) + check--; + bootpg = check << 12; + debug("Boot page (4K) at 0x%08x\n", bootpg); + } + break; + default: + break; + } + } +#endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */ - return (gd->ram_size - 4096); + return bootpg; } ulong get_spin_phys_addr(void) @@ -219,9 +276,9 @@ ulong get_spin_virt_addr(void) } #ifdef CONFIG_FSL_CORENET -static void plat_mp_up(unsigned long bootpg) +static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) { - u32 cpu_up_mask, whoami; + u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K; u32 *table = (u32 *)get_spin_virt_addr(); volatile ccsr_gur_t *gur; volatile ccsr_local_t *ccm; @@ -241,7 +298,11 @@ static void plat_mp_up(unsigned long bootpg) out_be32(&ccm->bstrl, bootpg); e = find_law(bootpg); - out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K); + /* pagesize is only 4K or 8K */ + if (pagesize == 8192) + brsize = LAW_SIZE_8K; + out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize); + debug("BRSIZE is 0x%x\n", brsize); /* readback to sync write */ in_be32(&ccm->bstrar); @@ -294,7 +355,7 @@ static void plat_mp_up(unsigned long bootpg) #endif } #else -static void plat_mp_up(unsigned long bootpg) +static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) { u32 up, cpu_up_mask, whoami; u32 *table = (u32 *)get_spin_virt_addr(); @@ -374,7 +435,7 @@ static void plat_mp_up(unsigned long bootpg) void cpu_mp_lmb_reserve(struct lmb *lmb) { - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); lmb_reserve(lmb, bootpg, 4096); } @@ -383,8 +444,23 @@ void setup_mp(void) { extern ulong __secondary_start_page; extern ulong __bootpg_addr; + ulong fixup = (ulong)&__secondary_start_page; - u32 bootpg = determine_mp_bootpg(); + u32 bootpg, bootpg_map, pagesize; + + bootpg = determine_mp_bootpg(&pagesize); + + /* + * pagesize is only 4K or 8K + * we only use the last 4K of boot page + * bootpg_map saves the address for the boot page + * 8K is used for the workaround of 3-way DDR interleaving + */ + + bootpg_map = bootpg; + + if (pagesize == 8192) + bootpg += 4096; /* use 2nd half */ /* Some OSes expect secondary cores to be held in reset */ if (hold_cores_in_reset(0)) @@ -407,7 +483,7 @@ void setup_mp(void) memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096); - plat_mp_up(bootpg); + plat_mp_up(bootpg_map, pagesize); } else { puts("WARNING: No reset page TLB. " "Skipping secondary core setup\n"); diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 61f5110b7d..2f955fe930 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -20,7 +20,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_MP int off; - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c index 30c99ebc56..de705f0ae8 100644 --- a/arch/powerpc/cpu/mpc86xx/mp.c +++ b/arch/powerpc/cpu/mpc86xx/mp.c @@ -90,8 +90,11 @@ int cpu_release(int nr, int argc, char * const argv[]) return 1; } -u32 determine_mp_bootpg(void) +u32 determine_mp_bootpg(unsigned int *pagesize) { + if (pagesize) + *pagesize = 4096; + /* if we have 4G or more of memory, put the boot page at 4Gb-1M */ if ((u64)gd->ram_size > 0xfffff000) return (0xfff00000); @@ -101,7 +104,7 @@ u32 determine_mp_bootpg(void) void cpu_mp_lmb_reserve(struct lmb *lmb) { - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); /* tell u-boot we stole a page */ lmb_reserve(lmb, bootpg, 4096); @@ -115,7 +118,7 @@ void setup_mp(void) { extern ulong __secondary_start_page; ulong fixup = (ulong)&__secondary_start_page; - u32 bootpg = determine_mp_bootpg(); + u32 bootpg = determine_mp_bootpg(NULL); u32 bootpg_va; if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) { diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index afc5fae497..940ffff773 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -121,6 +121,16 @@ void fsl_ddr_set_intl3r(const unsigned int granule_size) #endif } +u32 fsl_ddr_get_intl3r(void) +{ + u32 val = 0; +#ifdef CONFIG_E6500 + u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); + val = *mcintl3r; +#endif + return val; +} + void board_add_ram_info(int use_default) { #if defined(CONFIG_MPC83xx) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index ba13ddf951..ecb156619d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -511,6 +511,7 @@ #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #elif defined(CONFIG_PPC_B4860) diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h index fe490bac05..9188ede3f5 100644 --- a/arch/powerpc/include/asm/mp.h +++ b/arch/powerpc/include/asm/mp.h @@ -25,7 +25,7 @@ void setup_mp(void); void cpu_mp_lmb_reserve(struct lmb *lmb); -u32 determine_mp_bootpg(void); +u32 determine_mp_bootpg(unsigned int *pagesize); int is_core_disabled(int nr); #ifdef CONFIG_E6500 diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index b860141efd..ebf400851a 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -440,8 +440,8 @@ void board_init_f(ulong bootflag) * We need to make sure the location we intend to put secondary core * boot code is reserved and not used by any part of u-boot */ - if (addr > determine_mp_bootpg()) { - addr = determine_mp_bootpg(); + if (addr > determine_mp_bootpg(NULL)) { + addr = determine_mp_bootpg(NULL); debug("Reserving MP boot page to %08lx\n", addr); } #endif -- 2.25.1