From d9eaae3bae99cf79fd1453f4980b2624a6be9501 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 20 Dec 2018 08:40:25 +0100 Subject: [PATCH] travis: Wire Xilinx Versal Virt platform Test Xilinx Versal Virt platform running on the v3.1.0 Qemu. Signed-off-by: Michal Simek --- .travis.yml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/.travis.yml b/.travis.yml index 59e615abb2..49a7fa94f3 100644 --- a/.travis.yml +++ b/.travis.yml @@ -463,6 +463,13 @@ matrix: QEMU_TARGET="arm-softmmu" TEST_PY_ID="--id qemu" BUILDMAN="^zynq_zc702$" + - name: "test/py xilinx_versal_virt" + env: + - TEST_PY_BD="xilinx_versal_virt" + TEST_PY_TEST_SPEC="not sleep" + QEMU_TARGET="aarch64-softmmu" + TEST_PY_ID="--id qemu" + BUILDMAN="^xilinx_versal_virt$" - name: "test/py xtfpga" env: - TEST_PY_BD="xtfpga" -- 2.25.1