From d9ba54f77392aba655793fa527111d4d49c06eb7 Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Sun, 20 Mar 2016 17:00:21 +0100 Subject: [PATCH] Restore workaround for AR9331 hang at boot issue It looks that we really need it, so restore workaround from original Atheros (Q)SDK. In future we should try to find better way to deal with this problem. --- u-boot/cpu/mips/ar7240/ar933x_pll_init.S | 51 ++++++++++++++++++------ u-boot/cpu/mips/ar7240/qca_gpio_init.S | 37 +++++++++++++++++ u-boot/include/soc/qca_soc_common.h | 21 ++++++---- 3 files changed, 90 insertions(+), 19 deletions(-) diff --git a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S index 1e409c1..1bf0e6b 100644 --- a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S +++ b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S @@ -61,28 +61,58 @@ set_xtal_40mhz: li reg_ref_clk_val, 40 /* - * Several WLAN module resets as in broken Atheros SDK code - * TODO: do we really need this? + * Several WLAN module resets as in Atheros (Q)SDK */ wlan_rst_init: - li reg_loop_counter, 10 + li t8, QCA_RST_RST_REG + + /* 2x WLAN resets */ + lw t9, 0(t8) + or t9, t9, QCA_RST_RESET_WLAN_RST_MASK + sw t9, 0(t8) + nop + nop + lw t9, 0(t8) + and t9, t9, ~QCA_RST_RESET_WLAN_RST_MASK + sw t9, 0(t8) + nop + nop + + lw t9, 0(t8) + or t9, t9, QCA_RST_RESET_WLAN_RST_MASK + sw t9, 0(t8) + nop + nop + lw t9, 0(t8) + and t9, t9, ~QCA_RST_RESET_WLAN_RST_MASK + sw t9, 0(t8) + nop + nop wlan_rst: li t8, QCA_RST_RST_REG + lw t9, 0(t8) or t9, t9, QCA_RST_RESET_WLAN_RST_MASK sw t9, 0(t8) nop nop - lw t9, 0(t8) and t9, t9, ~QCA_RST_RESET_WLAN_RST_MASK sw t9, 0(t8) nop nop + li reg_loop_counter, 30 + +eep_busy: + beq zero, reg_loop_counter, wlan_rst + nop addi reg_loop_counter, reg_loop_counter, -1 - bnez reg_loop_counter, wlan_rst + li t8, QCA_RST_BOOTSTRAP_REG + lw t9, 0(t8) + and t9, t9, QCA_RST_BOOTSTRAP_EEPBUSY_MASK + bnez t9, eep_busy nop /* @@ -266,14 +296,11 @@ xtal_is_40mhz_recovery: /* * Load target value into CPU_CLOCK_CONTROL register, but for now keep bypass * enabled (by default, after reset, it should be bypassed, do it just in case) - * and AHB_POST_DIV equal to 4 */ cpu_clock_control: li t8, QCA_PLL_CPU_CLK_CTRL_REG move t9, reg_cpu_clk_ctrl or t9, t9, QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK - and t9, t9, ~QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK - or t9, t9, (3 << QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT) sw t9, 0(t8) /* @@ -311,10 +338,10 @@ cpu_pll_wait: /* Disable bypassing all clocks, use target AHB_POST_DIV value */ pll_bypass_disable: - li t8, QCA_PLL_CPU_CLK_CTRL_REG - move t9, reg_cpu_clk_ctrl - and t9, t9, ~QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK - sw t9, 0(t8) + li t8, QCA_PLL_CPU_CLK_CTRL_REG + lw t9, 0(t8) + and t9, t9, ~QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK + sw t9, 0(t8) /* Setup SPI (clock and other settings) */ spi_setup: diff --git a/u-boot/cpu/mips/ar7240/qca_gpio_init.S b/u-boot/cpu/mips/ar7240/qca_gpio_init.S index 9f48aec..433c2e4 100644 --- a/u-boot/cpu/mips/ar7240/qca_gpio_init.S +++ b/u-boot/cpu/mips/ar7240/qca_gpio_init.S @@ -435,6 +435,42 @@ lowlevel_gpio_init: #endif #endif + /* + * Workaround for hang issue, + * from original Atheros (Q)SDK: + * + * "Hornet 1.1 currently need a reset + * once we boot to let the resetb has + * enough time to stable, so that + * trigger reset at 1st boot". + * + * Read one 4 byte value from SRAM base address and compare it with + * known magic number (0x12345678 here), if it's the same, it means + * that this is not first boot and we can continue. Otherwise, make + * full chip reset (it's not power reset, SRAM data will survive). + * + * We need it here as it's first custom asm code executed in start{_bootstrap).S + * + * TODO: FIXME! + */ +first_boot: + li t8, 0xBD000000 + lw t9, 0(t8) + li t7, 0x12345678 + sw t7, 0(t8) + bne t9, t7, full_reset + nop + + b gpio_setup + nop + +full_reset: + li t8, QCA_RST_RST_REG + lw t9, 0(t8) + or t9, t9, QCA_RST_RESET_FULL_CHIP_RST_MASK + sw t9, 0(t8) + nop + /* * GPIO configuration, using GPIO_FUNCTION_1 register: * 1. Disable JTAG by default @@ -442,6 +478,7 @@ lowlevel_gpio_init: * 3. Disable HSUART RTS/CTS on GPIO11/12 if needed * 4. Disable selected Ethernet switch LEDs if needed */ +gpio_setup: li t8, QCA_GPIO_FUNC_1_REG lw t9, 0(t8) #if defined(CONFIG_SKIP_LOWLEVEL_INIT) || \ diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h index 1f0a24e..fc4f14a 100644 --- a/u-boot/include/soc/qca_soc_common.h +++ b/u-boot/include/soc/qca_soc_common.h @@ -1276,17 +1276,22 @@ #define QCA_RST_BOOTSTRAP_REF_CLK_40M_VAL 0x1 #if (SOC_TYPE & QCA_AR933X_SOC) + #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT 3 + #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK (1 << QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT) + #define QCA_RST_BOOTSTRAP_EEPBUSY_SHIFT 4 + #define QCA_RST_BOOTSTRAP_EEPBUSY_MASK (1 << QCA_RST_BOOTSTRAP_EEPBUSY_SHIFT) #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 12 #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2) - #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 0 - #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1 - #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 2 #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT 16 #define QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK (1 << QCA_RST_BOOTSTRAP_JTAG_APB_SEL_SHIFT) #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT 17 #define QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_MASK (1 << QCA_RST_BOOTSTRAP_MDIO_SLAVE_EN_SHIFT) #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT 18 #define QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_MASK (1 << QCA_RST_BOOTSTRAP_MDIO_GPIO_EN_SHIFT) + + #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 0 + #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1 + #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 2 #else #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 0 @@ -1297,16 +1302,18 @@ #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK (1 << QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT) #endif - #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 3 - #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1 - #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 0 - #define QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT 2 #define QCA_RST_BOOTSTRAP_BOOT_SEL_MASK (1 << QCA_RST_BOOTSTRAP_BOOT_SEL_SHIFT) #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT 3 #define QCA_RST_BOOTSTRAP_DDR_WIDTH_32_MASK (1 << QCA_RST_BOOTSTRAP_DDR_WIDTH_32_SHIFT) #define QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT 5 #define QCA_RST_BOOTSTRAP_JTAG_MODE_MASK (1 << QCA_RST_BOOTSTRAP_JTAG_MODE_SHIFT) + #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT 7 + #define QCA_RST_BOOTSTRAP_USB_MODE_DEV_MASK (1 << QCA_RST_BOOTSTRAP_USB_MODE_DEV_SHIFT) + + #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 3 + #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1 + #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 0 #endif /* RST_RESET */ -- 2.25.1