From c60a854286c1ae3a4c336b5d6e31e6fc006a9b8c Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Tue, 19 Nov 2013 12:35:33 +0100 Subject: [PATCH] Simpler settings for PLL registers on AR9331 --- u-boot/board/ar7240/ap121/hornet_pll_init.S | 584 ++++++++++---------- u-boot/include/configs/ap121.h | 261 ++++----- 2 files changed, 397 insertions(+), 448 deletions(-) diff --git a/u-boot/board/ar7240/ap121/hornet_pll_init.S b/u-boot/board/ar7240/ap121/hornet_pll_init.S index 0158625..7b13bc3 100755 --- a/u-boot/board/ar7240/ap121/hornet_pll_init.S +++ b/u-boot/board/ar7240/ap121/hornet_pll_init.S @@ -9,6 +9,13 @@ .text .align 4 +#define CLEAR_BIT(val, bit) ((val) & ~(1 << (bit))) +#define SET_BIT(val, bit) ((val) | (1 << (bit))) + +#define CLEAR_PLL_POWER_DOWN(reg_val) CLEAR_BIT(reg_val, 30) +#define SET_AHB_DIV_TO_4(reg_val) SET_BIT(SET_BIT(reg_val, 15), 16) +#define CLEAR_PLL_BYPASS(reg_val) CLEAR_BIT(reg_val, 2) + /* * Helper macros. * These Clobber t7, t8 and t9 @@ -23,252 +30,258 @@ hornet_pll_init: #if 1 -/* These three wlan reset will avoid original issue, -so full chip reset isn't needed here. */ - set_reg(0xb806001c, 0x00c06b30) - nop - set_reg(0xb806001c, 0x00c06330) - nop - set_reg(0xb806001c, 0x00c06b30) - nop - set_reg(0xb806001c, 0x00c06330) - nop +/* These three wlan reset will avoid original issue, so full chip reset isn't needed here. */ + set_reg(0xb806001c, 0x00c06b30) + nop + set_reg(0xb806001c, 0x00c06330) + nop + set_reg(0xb806001c, 0x00c06b30) + nop + set_reg(0xb806001c, 0x00c06330) + nop + reset_wlan: - set_reg(0xb806001c, 0x00c06b30) - nop - set_reg(0xb806001c, 0x00c06330) - nop + set_reg(0xb806001c, 0x00c06b30) + nop + set_reg(0xb806001c, 0x00c06330) + nop + li t5, 0x20 - li t5, 0x20 check_val: - beq zero, t5, reset_wlan - addi t5, t5, -1 - li t6, 0xb80600ac - lw t7, 0(t6) - li t8, 0x10 - and t7, t7, t8 - bne zero, t7, check_val - - set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110e) - nop + beq zero, t5, reset_wlan + addi t5, t5, -1 + li t6, 0xb80600ac + lw t7, 0(t6) + li t8, 0x10 + and t7, t7, t8 + bne zero, t7, check_val + set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110e) + nop #else /* clear wlan reset bit in RESET_Register 0x1c */ - set_reg(AR7240_RESET, 0x00c06b30) - nop - set_reg(AR7240_RESET, 0x00c06330) - nop + set_reg(AR7240_RESET, 0x00c06b30) + nop + set_reg(AR7240_RESET, 0x00c06330) + nop /* cleck bootstrap status, wait for bit4 on, then clear bit16 */ wait_loop0: - li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS) - lw t7, 0(t6) - li t8, 0x10 - and t7, t7, t8 - bne zero, t7, wait_loop0 - nop - set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110e) - nop -#endif - + li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS) + lw t7, 0(t6) + li t8, 0x10 + and t7, t7, t8 + bne zero, t7, wait_loop0 + nop + set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110e) + nop +#endif + /* RTC reset */ - set_reg(0x1810704c, 0x00000003) - nop - nop - set_reg(0x18107040, 0x00000000) - nop - nop - set_reg(0x18107040, 0x00000001) - nop + set_reg(0x1810704c, 0x00000003) + nop + nop + set_reg(0x18107040, 0x00000000) + nop + nop + set_reg(0x18107040, 0x00000001) + nop + wait_loop1: - li t6, KSEG1ADDR(0x18107044) - lw t7, 0(t6) - li t8, 0x2 - and t7, t7, t8 - bne t8, t7, wait_loop1 - nop - - /* AHB/APH reset */ - set_reg(0x18104000, 0x00000003) - nop - set_reg(0x18104000, 0x00000000) - nop - - /* MAC reset */ - set_reg(0x18107000, 0x0000000F) - nop - set_reg(0x18107000, 0x00000000) - nop + li t6, KSEG1ADDR(0x18107044) + lw t7, 0(t6) + li t8, 0x2 + and t7, t7, t8 + bne t8, t7, wait_loop1 + nop + +/* AHB/APH reset */ +/* + * TODO: something is wrong here! + * 0x18104000 is "Reset the Host Interface (HOST_INTF_RESET_CONTROL)" and bits 0:7 are RESERVED! + */ + set_reg(0x18104000, 0x00000003) + nop + set_reg(0x18104000, 0x00000000) + nop + +/* MAC reset */ +/* + * TODO: same here - something is wrong here! + * "RTC registers occupy the offset range 0x18107000–0x18107FFC in the AR9331 address space." + */ + set_reg(0x18107000, 0x0000000F) + nop + set_reg(0x18107000, 0x00000000) + nop #if 1 /* fetch pmu1.refv and ctrl2.tx from OTP */ - li t1, KSEG1ADDR(0x18114014) - lw t2, 0(t1) + li t1, KSEG1ADDR(0x18114014) + lw t2, 0(t1) + otp_loop0: - li t3, KSEG1ADDR(0x18115f18) - lw t4, 0(t3) - nop - li t5, 0x7 - and t4, t4, t5 - li t5, 0x4 - bne t4, t5, otp_loop0 - nop - - li t6, KSEG1ADDR(0x18115f1c) - lw t7, 0(t6) - nop - li t8, 0x80000080 - and t9, t7, t8 - beq t8, t9, fetch_otp + li t3, KSEG1ADDR(0x18115f18) + lw t4, 0(t3) + nop + li t5, 0x7 + and t4, t4, t5 + li t5, 0x4 + bne t4, t5, otp_loop0 + nop + li t6, KSEG1ADDR(0x18115f1c) + lw t7, 0(t6) + nop + li t8, 0x80000080 + and t9, t7, t8 + beq t8, t9, fetch_otp + otp_loop0_end: + li t1, KSEG1ADDR(0x18114004) + lw t2, 0(t1) - li t1, KSEG1ADDR(0x18114004) - lw t2, 0(t1) otp_loop1: - li t3, KSEG1ADDR(0x18115f18) - lw t4, 0(t3) - nop - li t5, 0x7 - and t4, t4, t5 - li t5, 0x4 - bne t4, t5, otp_loop1 - nop - - li t6, KSEG1ADDR(0x18115f1c) - lw t7, 0(t6) - nop - li t8, 0x80000080 - and t9, t7, t8 + li t3, KSEG1ADDR(0x18115f18) + lw t4, 0(t3) + nop + li t5, 0x7 + and t4, t4, t5 + li t5, 0x4 + bne t4, t5, otp_loop1 + nop + li t6, KSEG1ADDR(0x18115f1c) + lw t7, 0(t6) + nop + li t8, 0x80000080 + and t9, t7, t8 + default_pmu: - li t5, 0x80 /* default 0x031c4386 */ - bne t8, t9, otp_end -otp_loop1_end: + li t5, 0x80 /* default 0x031c4386 */ + bne t8, t9, otp_end +otp_loop1_end: fetch_otp: - srl t8, t7, 0x18 - li t1, 0xf - and t2, t1 , t7 /* USB */ - and t5, t1 , t8 /* PMU */ + srl t8, t7, 0x18 + li t1, 0xf + and t2, t1 , t7 /* USB */ + and t5, t1 , t8 /* PMU */ check_pmu: - li t0, 0x4 /* PMU range should be 0x4~0xa */ - bgt t0, t5, default_pmu - nop - li t0, 0xa /* PMU range should be 0x4~0xa */ - blt t0, t5, default_pmu - nop - li t0, 0x4 - sll t5, t5, t0 + li t0, 0x4 /* PMU range should be 0x4~0xa */ + bgt t0, t5, default_pmu + nop + li t0, 0xa /* PMU range should be 0x4~0xa */ + blt t0, t5, default_pmu + nop + li t0, 0x4 + sll t5, t5, t0 otp_end: #endif #if 1 /* Program PMU */ #define PMU_TEST_NO 1000 - li t6, KSEG1ADDR(0x18116c40) - li t9, 0xbd000010 - li t0, 0 - li t1, 0 - li t2, 0 - - li t3, PMU_TEST_NO - sw t3, 12(t9) + li t6, KSEG1ADDR(0x18116c40) + li t9, 0xbd000010 + li t0, 0 + li t1, 0 + li t2, 0 + li t3, PMU_TEST_NO + sw t3, 12(t9) + pmu_loop0: - beq zero, t3, pmu_loop0_end - nop - addi t3, t3, -1 - - li t7, 0x10180000 /* ldo_tune 0x3 */ - nop - sw t7, 4(t6) - nop - lw t8, 4(t6) - nop - beq t8, t7, pmu_loop0_end - nop - - addiu t0, t0, 1 - b pmu_loop0 - nop -pmu_loop0_end: - - li t3, PMU_TEST_NO + beq zero, t3, pmu_loop0_end + nop + addi t3, t3, -1 + li t7, 0x10180000 /* ldo_tune 0x3 */ + nop + sw t7, 4(t6) + nop + lw t8, 4(t6) + nop + beq t8, t7, pmu_loop0_end + nop + addiu t0, t0, 1 + b pmu_loop0 + nop + +pmu_loop0_end: + li t3, PMU_TEST_NO + pmu_loop1: - beq zero, t3, pmu_loop1_end - nop - addi t3, t3, -1 - - //li t7, 0x031c4326 /* 1.100V */ - //li t7, 0x031c4336 /* 1.125V */ - //li t7, 0x031c4346 /* 1.150V */ - //li t7, 0x031c4356 /* 1.175V */ - //li t7, 0x031c4366 /* 1.200V */ - //li t7, 0x031c4376 /* 1.225V */ - li t7, 0x031c4386 /* 1.250V (DEFAULT) */ - //li t7, 0x031c4396 /* 1.275V */ - //li t7, 0x031c43a6 /* 1.300V */ - nop + beq zero, t3, pmu_loop1_end + nop + addi t3, t3, -1 + //li t7, 0x031c4326 /* 1.100V */ + //li t7, 0x031c4336 /* 1.125V */ + //li t7, 0x031c4346 /* 1.150V */ + //li t7, 0x031c4356 /* 1.175V */ + //li t7, 0x031c4366 /* 1.200V */ + //li t7, 0x031c4376 /* 1.225V */ + li t7, 0x031c4386 /* 1.250V (DEFAULT) */ + //li t7, 0x031c4396 /* 1.275V */ + //li t7, 0x031c43a6 /* 1.300V */ + nop + #if 1 /* from OTP */ - li t8, 0xffffff0f - and t7, t7, t8 - or t7, t7, t5 + li t8, 0xffffff0f + and t7, t7, t8 + or t7, t7, t5 #endif - sw t7, 0(t6) - nop - lw t8, 0(t6) - nop - beq t8, t7, pmu_loop1_end - nop - - addiu t1, t1, 1 - b pmu_loop1 - nop -pmu_loop1_end: - - li t3, PMU_TEST_NO -pmu_loop2: - beq zero, t3, pmu_loop2_end - nop - addi t3, t3, -1 - - li t7, 0x10380000 /* ldo_tune 0x3 */ - nop - sw t7, 4(t6) - nop - lw t8, 4(t6) - nop - beq t8, t7, pmu_loop2_end - nop - - addiu t2, t2, 1 - b pmu_loop2 - nop -pmu_loop2_end: - - sw t0, 0(t9) - nop - sw t1, 4(t9) - nop - sw t2, 8(t9) - nop + sw t7, 0(t6) + nop + lw t8, 0(t6) + nop + beq t8, t7, pmu_loop1_end + nop + addiu t1, t1, 1 + b pmu_loop1 + nop + +pmu_loop1_end: + li t3, PMU_TEST_NO + +pmu_loop2: + beq zero, t3, pmu_loop2_end + nop + addi t3, t3, -1 + li t7, 0x10380000 /* ldo_tune 0x3 */ + nop + sw t7, 4(t6) + nop + lw t8, 4(t6) + nop + beq t8, t7, pmu_loop2_end + nop + addiu t2, t2, 1 + b pmu_loop2 + nop + +pmu_loop2_end: + sw t0, 0(t9) + nop + sw t1, 4(t9) + nop + sw t2, 8(t9) + nop #endif #if 1 /* Program ki, kd */ - /* Program ki/kd */ +/* Program ki/kd */ #if CONFIG_40MHZ_XTAL_SUPPORT - set_reg(0x18116244, 0x19e82f01) + set_reg(0x18116244, 0x19e82f01) #else - set_reg(0x18116244, 0x18e82f01) + set_reg(0x18116244, 0x18e82f01) #endif - nop + nop - /* Program phase shift */ - li t6, KSEG1ADDR(0x18116248) - lw t7, 0(t6) - li t8, 0xc07fffff - and t7, t7, t8 - li t8, 0x800000 - or t7, t7, t8 - sw t7, 0(t6) - nop +/* Program phase shift */ + li t6, KSEG1ADDR(0x18116248) + lw t7, 0(t6) + li t8, 0xc07fffff + and t7, t7, t8 + li t8, 0x800000 + or t7, t7, t8 + sw t7, 0(t6) + nop #endif /* max AHB Master wait time out ... */ @@ -276,12 +289,13 @@ pmu_loop2_end: // nop /* set PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */ - set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL1) +/* in some cases, the SoC doesn't start with higher clock on AHB */ + set_reg(AR7240_CPU_CLOCK_CONTROL, SET_AHB_DIV_TO_4(CPU_CLK_CONTROL_VAL)) nop /* set SETTLE_TIME in CPU PLL */ - set_reg(AR7240_USB_PLL_CONFIG, CPU_PLL_SETTLE_TIME_VAL) - nop + set_reg(AR7240_USB_PLL_CONFIG, CPU_PLL_SETTLE_TIME_VAL) + nop /* read GPIO_SET register */ li t0, KSEG1ADDR(AR7240_GPIO_IN) @@ -292,26 +306,26 @@ pmu_loop2_end: pll_unlock_handler: /* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */ - set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL1) - j wait_loop2 - nop + set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL) + j wait_loop2 + nop pll_default_unlock_handler: /* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */ - set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL1_DEFAULT) - nop + set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL_DEFAULT) + nop wait_loop2: - li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) - lw t7, 0(t6) - li t8, 0x80000000 - and t7, t7, t8 - bne zero, t7, wait_loop2 - nop + li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) + lw t7, 0(t6) + li t8, 0x80000000 + and t7, t7, t8 + bne zero, t7, wait_loop2 + nop /* put frac bit19:10 configuration */ - set_reg(AR7240_PCIE_PLL_CONFIG, CPU_PLL_DITHER_FRAC_VAL) - nop + set_reg(AR7240_PCIE_PLL_CONFIG, CPU_PLL_DITHER_FRAC_VAL) + nop /* read GPIO_SET register */ li t0, KSEG1ADDR(AR7240_GPIO_IN) @@ -322,79 +336,85 @@ wait_loop2: pll_lock_handler: /* clear PLL power down bit in CPU PLLl configuration */ - set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL2) - j wait_loop3 - nop + set_reg(AR7240_CPU_PLL_CONFIG, CLEAR_PLL_POWER_DOWN(CPU_PLL_CONFIG_VAL)) + j wait_loop3 + nop pll_default_lock_handler: /* clear PLL power down bit in CPU PLLl configuration */ - set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL2_DEFAULT) - nop + set_reg(AR7240_CPU_PLL_CONFIG, CLEAR_PLL_POWER_DOWN(CPU_PLL_CONFIG_VAL_DEFAULT)) + nop wait_loop3: - li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) - lw t7, 0(t6) - li t8, 0x80000000 - and t7, t7, t8 - bne zero, t7, wait_loop3 - nop + li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) + lw t7, 0(t6) + li t8, 0x80000000 + and t7, t7, t8 + bne zero, t7, wait_loop3 + nop /* confirm DDR PLL lock */ - li t3, 100 - li t4, 0 + li t3, 100 + li t4, 0 + start_meas0: - addi t4, t4, 1 - bgt t4, t3, pll_unlock_handler - nop - li t5, 5 + addi t4, t4, 1 + bgt t4, t3, pll_unlock_handler + nop + li t5, 5 + start_meas: - li t6, KSEG1ADDR(0x18116248) - lw t7, 0(t6) - li t8, 0xbfffffff - and t7, t7, t8 - sw t7, 0(t6) - nop + li t6, KSEG1ADDR(0x18116248) + lw t7, 0(t6) + li t8, 0xbfffffff + and t7, t7, t8 + sw t7, 0(t6) + nop /* delay */ - li t9, 10 -delayloop0: - subu t9, t9, 1 - bne t9, zero, delayloop0 - nop + li t9, 10 - li t8, 0x40000000 - or t7, t7, t8 - sw t7, 0(t6) - nop +delayloop0: + subu t9, t9, 1 + bne t9, zero, delayloop0 + nop + li t8, 0x40000000 + or t7, t7, t8 + sw t7, 0(t6) + nop meas_done_statue: - li t6, KSEG1ADDR(0x1811624c) - lw t7, 0(t6) - li t8, 0x8 - and t7, t7, t8 - beq zero, t7, meas_done_statue - nop - + li t6, KSEG1ADDR(0x1811624c) + lw t7, 0(t6) + li t8, 0x8 + and t7, t7, t8 + beq zero, t7, meas_done_statue + nop + meas_result: - li t6, KSEG1ADDR(0x18116248) - lw t7, 0(t6) - li t8, 0x007ffff8 - and t7, t7, t8 - srl t7, t7, 3 - li t8, 0x4000 - bgt t7, t8, start_meas0 - nop - addi t5, t5, -1 - bne zero, t5, start_meas - nop - -/* clear PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */ - set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL2) - nop + li t6, KSEG1ADDR(0x18116248) + lw t7, 0(t6) + li t8, 0x007ffff8 + and t7, t7, t8 + srl t7, t7, 3 + li t8, 0x4000 + bgt t7, t8, start_meas0 + nop + addi t5, t5, -1 + bne zero, t5, start_meas + nop + +/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */ + set_reg(AR7240_CPU_CLOCK_CONTROL, CLEAR_PLL_BYPASS(CPU_CLK_CONTROL_VAL)) + nop /* Sync mode , Set Bit 8 of DDR Tap Conrtol 3 register */ - set_reg(AR7240_DDR_TAP_CONTROL3, 0x10105); - nop +/* + * TODO: something is wrong here? + * There is no AR7240_DDR_TAP_CONTROL3 in AR9331 datasheet! + */ + //set_reg(AR7240_DDR_TAP_CONTROL3, 0x10105); + //nop - jr ra - nop + jr ra + nop diff --git a/u-boot/include/configs/ap121.h b/u-boot/include/configs/ap121.h index 476737a..2ff6cbc 100755 --- a/u-boot/include/configs/ap121.h +++ b/u-boot/include/configs/ap121.h @@ -88,28 +88,13 @@ #undef CFG_PLL_FREQ #undef CFG_HZ -#undef CPU_PLL_CONFIG_VAL1 -#undef CPU_CLK_CONTROL_VAL2 +#undef CPU_PLL_CONFIG_VAL +#undef CPU_CLK_CONTROL_VAL // CPU-RAM-AHB frequency setting #define CFG_PLL_FREQ CFG_PLL_400_400_200 //#define CFG_PLL_FREQ CFG_PLL_525_525_262 // only for test! -/* - * MIPS32 24K Processor Core Family Software User's Manual - * - * 6.2.9 Count Register (CP0 Register 9, Select 0) - * The Count register acts as a timer, incrementing at a constant - * rate, whether or not an instruction is executed, retired, or - * any forward progress is made through the pipeline. The counter - * increments every other clock, if the DC bit in the Cause register - * is 0. - * - * Since the count is incremented every other tick, divide by 2 - * XXX derive this from CFG_PLL_FREQ - */ - - /* * CPU_PLL_DITHER_FRAC_VAL * @@ -127,7 +112,7 @@ * * Value written into CPU Phase Lock Loop Configuration Register 2 (CPU_PLL_CONFIG2) * - * bits 0..11 SETTLE_TIME => 580 (0x352) + * bits 0..11 SETTLE_TIME => 850 (0x352) * */ #if CONFIG_40MHZ_XTAL_SUPPORT @@ -137,11 +122,12 @@ #endif /* - * CPU_CLK_CONTROL_VAL1 - * CPU_CLK_CONTROL_VAL2 + * CPU_CLK_CONTROL_VAL + * + * In CPU_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL) + * After PLL configuration we nedd to clear this bit * * Values written into CPU Clock Control Register CLOCK_CONTROL - * with PLL bypass disabled * * bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test purposes. Software must enable the CPU PLL for normal operation and then set this bit to 0) * bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1) @@ -151,18 +137,17 @@ */ /* - * CPU_PLL_CONFIG_VAL1 - * CPU_PLL_CONFIG_VAL2 + * CPU_PLL_CONFIG_VAL * - * In CPU_PLL_CONFIG_VAL1 bit 30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) - * In CPU_PLL_CONFIG_VAL2 bit 30 is unset + * In CPU_PLL_CONFIG_VAL bit 30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL) + * After PLL configuration we need to clear this bit * * Values written into CPU Phase Lock Loop Configuration (CPU_PLL_CONFIG) * * bits 10..15 (6bit) DIV_INT (The integer part of the DIV to CPU PLL) => 32 (0x20) - * bits 16..20 (5bit) REFDIV (Reference clock divider) => 1 (0x1) [doesn't start at valuse different than 1 (maybe need to change other dividers?)] + * bits 16..20 (5bit) REFDIV (Reference clock divider) => 1 (0x1) [doesn't start at values different than 1 (maybe need to change other dividers?)] * bits 21 (1bit) RANGE (Determine the VCO frequency range of the CPU PLL) => 0 (0x0) [doesn't have impact on clock values] - * bits 23..25 (3bit) OUTDIV (Define the ratio betwee VCO output and PLL output => 1 (0x1) + * bits 23..25 (3bit) OUTDIV (Define the ratio between VCO output and PLL output => 1 (0x1) * VCOOUT * (1/2^OUTDIV) = PLLOUT) */ @@ -188,55 +173,47 @@ * */ +/* + * CPU_PLL_CONFIG and CPU_CLK_CONTROL registers values generator + */ +#define MAKE_CPU_PLL_CONFIG_VAL(divint, refdiv, outdiv) (0x40000000 | ((0x3F & divint) << 10) | ((0x1F & refdiv) << 16) | ((0x7 & outdiv) << 23)) +#define MAKE_CPU_CLK_CONTROL_VAL(cpudiv, ddrdiv, ahbdiv) (0x4 | ((0x3 & (cpudiv - 1)) << 5) | ((0x3 & (ddrdiv - 1)) << 10) | ((0x3 & (ahbdiv - 1)) << 15)) + /* * Default values (400/400/200 MHz) for O/C recovery mode */ // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 -#define CPU_CLK_CONTROL_VAL1_DEFAULT 0x00018004 -#define CPU_CLK_CONTROL_VAL2_DEFAULT 0x00008000 +#define CPU_CLK_CONTROL_VAL_DEFAULT MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2) #if CONFIG_40MHZ_XTAL_SUPPORT - // DIV_INT = 20 (40 MHz * 20/2 = 400 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1_DEFAULT 0x40815000 - #define CPU_PLL_CONFIG_VAL2_DEFAULT 0x00815000 + // DIV_INT = 20 (40 MHz * 20/2 = 400 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL_DEFAULT MAKE_CPU_PLL_CONFIG_VAL(20, 1, 1) #else - // DIV_INT = 32 (25 MHz * 32/2 = 400 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1_DEFAULT 0x40818000 - #define CPU_PLL_CONFIG_VAL2_DEFAULT 0x00818000 + // DIV_INT = 32 (25 MHz * 32/2 = 400 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL_DEFAULT MAKE_CPU_PLL_CONFIG_VAL(32, 1, 1) #endif // CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz) -#define AR7240_SPI_CONTROL_DEFAULT 0x42 +#define AR7240_SPI_CONTROL_DEFAULT 0x42 #if (CFG_PLL_FREQ == CFG_PLL_400_400_200) - #define CFG_HZ (400000000LU/2) + #define CFG_HZ (400000000LU/2) // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 - #define CPU_CLK_CONTROL_VAL1 0x00018004 - #define CPU_CLK_CONTROL_VAL2 0x00008000 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2) #if CONFIG_40MHZ_XTAL_SUPPORT - // DIV_INT = 20 (40 MHz * 20/2 = 400 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x40815000 - #define CPU_PLL_CONFIG_VAL2 0x00815000 + // DIV_INT = 20 (40 MHz * 20/2 = 400 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x40815000 #else - // DIV_INT = 32 (25 MHz * 32/2 = 400 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x40818000 - #define CPU_PLL_CONFIG_VAL2 0x00818000 + // DIV_INT = 32 (25 MHz * 32/2 = 400 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x40818000 #endif // CLOCK_DIVIDER = 2 (SPI clock = 200 / 6 ~ 33 MHz) @@ -244,54 +221,42 @@ #elif (CFG_PLL_FREQ == CFG_PLL_412_412_206) - #define CFG_HZ (412500000LU/2) + #define CFG_HZ (412500000LU/2) // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 - #define CPU_CLK_CONTROL_VAL1 0x00018004 - #define CPU_CLK_CONTROL_VAL2 0x00008000 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2) - // DIV_INT = 33 (25 MHz * 33/2 = 412,5 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x40818400 - #define CPU_PLL_CONFIG_VAL2 0x00818400 + // DIV_INT = 33 (25 MHz * 33/2 = 412,5 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x40818400 // CLOCK_DIVIDER = 2 (SPI clock = 206,25 / 6 ~ 34,4 MHz) #define AR7240_SPI_CONTROL 0x42 #elif (CFG_PLL_FREQ == CFG_PLL_425_425_212) - #define CFG_HZ (425000000LU/2) + #define CFG_HZ (425000000LU/2) // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 - #define CPU_CLK_CONTROL_VAL1 0x00018004 - #define CPU_CLK_CONTROL_VAL2 0x00008000 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2) - // DIV_INT = 34 (25 MHz * 34/2 = 425 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x40818800 - #define CPU_PLL_CONFIG_VAL2 0x00818800 + // DIV_INT = 34 (25 MHz * 34/2 = 425 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x40818800 // CLOCK_DIVIDER = 2 (SPI clock = 212,5 / 6 ~ 35,4 MHz) #define AR7240_SPI_CONTROL 0x42 #elif (CFG_PLL_FREQ == CFG_PLL_437_437_218) - #define CFG_HZ (437500000LU/2) + #define CFG_HZ (437500000LU/2) // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 - #define CPU_CLK_CONTROL_VAL1 0x00018004 - #define CPU_CLK_CONTROL_VAL2 0x00008000 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2) - // DIV_INT = 35 (25 MHz * 35/2 = 437,5 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x40818C00 - #define CPU_PLL_CONFIG_VAL2 0x00818C00 + // DIV_INT = 35 (25 MHz * 35/2 = 437,5 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x40818C00 // CLOCK_DIVIDER = 2 (SPI clock = 218,75 / 6 ~ 36,5 MHz) #define AR7240_SPI_CONTROL 0x42 @@ -299,72 +264,56 @@ #elif (CFG_PLL_FREQ == CFG_PLL_450_450_225) - #define CFG_HZ (450000000LU/2) + #define CFG_HZ (450000000LU/2) // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 - #define CPU_CLK_CONTROL_VAL1 0x00018004 - #define CPU_CLK_CONTROL_VAL2 0x00008000 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2) - // DIV_INT = 36 (25 MHz * 36/2 = 450 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x40819000 - #define CPU_PLL_CONFIG_VAL2 0x00819000 + // DIV_INT = 36 (25 MHz * 36/2 = 450 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x40819000 // CLOCK_DIVIDER = 3 (SPI clock = 225 / 6 ~ 37,5 MHz) #define AR7240_SPI_CONTROL 0x42 #elif (CFG_PLL_FREQ == CFG_PLL_462_462_231) - #define CFG_HZ (462500000LU/2) + #define CFG_HZ (462500000LU/2) // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 - #define CPU_CLK_CONTROL_VAL1 0x00018004 - #define CPU_CLK_CONTROL_VAL2 0x00008000 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2) - // DIV_INT = 37 (25 MHz * 37/2 = 462,5 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x40819400 - #define CPU_PLL_CONFIG_VAL2 0x00819400 + // DIV_INT = 37 (25 MHz * 37/2 = 462,5 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x40819400 // CLOCK_DIVIDER = 3 (SPI clock = 231,25 / 6 ~ 38,5 MHz) #define AR7240_SPI_CONTROL 0x42 #elif (CFG_PLL_FREQ == CFG_PLL_475_475_237) - #define CFG_HZ (475000000LU/2) + #define CFG_HZ (475000000LU/2) // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 - #define CPU_CLK_CONTROL_VAL1 0x00018004 - #define CPU_CLK_CONTROL_VAL2 0x00008000 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2) - // DIV_INT = 38 (25 MHz * 38/2 = 475 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x40819800 - #define CPU_PLL_CONFIG_VAL2 0x00819800 + // DIV_INT = 38 (25 MHz * 38/2 = 475 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x40819800 // CLOCK_DIVIDER = 3 (SPI clock = 237,5 / 6 ~ 39,6 MHz) #define AR7240_SPI_CONTROL 0x42 #elif (CFG_PLL_FREQ == CFG_PLL_487_487_243) - #define CFG_HZ (487500000LU/2) + #define CFG_HZ (487500000LU/2) // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 - #define CPU_CLK_CONTROL_VAL1 0x00018004 - #define CPU_CLK_CONTROL_VAL2 0x00008000 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2) - // DIV_INT = 39 (25 MHz * 39/2 = 487,5 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x40819C00 - #define CPU_PLL_CONFIG_VAL2 0x00819C00 + // DIV_INT = 39 (25 MHz * 39/2 = 487,5 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x40819C00 // CLOCK_DIVIDER = 3 (SPI clock = 243,75 / 8 ~ 30,5 MHz) #define AR7240_SPI_CONTROL 0x43 @@ -372,90 +321,70 @@ #elif (CFG_PLL_FREQ == CFG_PLL_500_500_250) - #define CFG_HZ (500000000LU/2) + #define CFG_HZ (500000000LU/2) // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 - #define CPU_CLK_CONTROL_VAL1 0x00018004 - #define CPU_CLK_CONTROL_VAL2 0x00008000 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2) - // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x4081A000 - #define CPU_PLL_CONFIG_VAL2 0x0081A000 + // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x4081A000 // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31,3 MHz) #define AR7240_SPI_CONTROL 0x43 #elif (CFG_PLL_FREQ == CFG_PLL_500_250_250) - #define CFG_HZ (500000000LU/2) + #define CFG_HZ (500000000LU/2) // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 2 - #define CPU_CLK_CONTROL_VAL1 0x00018404 - #define CPU_CLK_CONTROL_VAL2 0x00008400 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 2, 2) - // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x4081A000 - #define CPU_PLL_CONFIG_VAL2 0x0081A000 + // DIV_INT = 40 (25 MHz * 40/2 = 500 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x4081A000 // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31,3 MHz) #define AR7240_SPI_CONTROL 0x43 #elif (CFG_PLL_FREQ == CFG_PLL_562_281_140) - #define CFG_HZ (562500000LU/2) + #define CFG_HZ (562500000LU/2) // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4 - #define CPU_CLK_CONTROL_VAL1 0x00018404 - #define CPU_CLK_CONTROL_VAL2 0x00018400 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 2, 4) - // DIV_INT = 45 (25 MHz * 45/2 = 562,5 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x4081B400 - #define CPU_PLL_CONFIG_VAL2 0x0081B400 + // DIV_INT = 45 (25 MHz * 45/2 = 562,5 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x4081B400 // CLOCK_DIVIDER = 1 (SPI clock = 140,625 / 4 ~ 35,2 MHz) #define AR7240_SPI_CONTROL 0x41 #elif (CFG_PLL_FREQ == CFG_PLL_525_262_131) - #define CFG_HZ (525000000LU/2) + #define CFG_HZ (525000000LU/2) // CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 4 - #define CPU_CLK_CONTROL_VAL1 0x00018404 - #define CPU_CLK_CONTROL_VAL2 0x00018400 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 2, 4) - // DIV_INT = 42 (25 MHz * 42/2 = 525 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x4081A800 - #define CPU_PLL_CONFIG_VAL2 0x0081A800 + // DIV_INT = 42 (25 MHz * 42/2 = 525 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x4081A800 // CLOCK_DIVIDER = 1 (SPI clock = 131 / 4 ~ 32,8 MHz) #define AR7240_SPI_CONTROL 0x41 #elif (CFG_PLL_FREQ == CFG_PLL_525_525_262) - #define CFG_HZ (525000000LU/2) + #define CFG_HZ (525000000LU/2) // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2 - #define CPU_CLK_CONTROL_VAL1 0x00008004 - #define CPU_CLK_CONTROL_VAL2 0x00008000 - - // DIV_INT = 42 (25 MHz * 42/2 = 525 MHz) - // REFDIV = 1 - // RANGE = 0 - // OUTDIV = 1 - #define CPU_PLL_CONFIG_VAL1 0x4081A800 - #define CPU_PLL_CONFIG_VAL2 0x0081A800 + #define CPU_CLK_CONTROL_VAL MAKE_CPU_CLK_CONTROL_VAL(1, 1, 2) + + // DIV_INT = 42 (25 MHz * 42/2 = 525 MHz) + // REFDIV = 1, OUTDIV = 1 + #define CPU_PLL_CONFIG_VAL 0x4081A800 // CLOCK_DIVIDER = 1 (SPI clock = 131 / 4 ~ 32,8 MHz) #define AR7240_SPI_CONTROL 0x41 -- 2.25.1