From bfdfbf85bb71b28e9547aa2e61812ea0d10560f4 Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Sun, 20 Mar 2016 17:12:32 +0100 Subject: [PATCH] Be consistent with register names in common QC/A header --- u-boot/cpu/mips/ar7240/ar933x_pll_init.S | 4 ++-- u-boot/cpu/mips/ar7240/qca95xx_pll_init.S | 2 +- u-boot/cpu/mips/ar7240/qca_common.c | 4 ++-- u-boot/cpu/mips/ar7240/qca_gpio_init.S | 2 +- u-boot/include/soc/qca_soc_common.h | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S index 1bf0e6b..442f957 100644 --- a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S +++ b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S @@ -64,7 +64,7 @@ set_xtal_40mhz: * Several WLAN module resets as in Atheros (Q)SDK */ wlan_rst_init: - li t8, QCA_RST_RST_REG + li t8, QCA_RST_RESET_REG /* 2x WLAN resets */ lw t9, 0(t8) @@ -90,7 +90,7 @@ wlan_rst_init: nop wlan_rst: - li t8, QCA_RST_RST_REG + li t8, QCA_RST_RESET_REG lw t9, 0(t8) or t9, t9, QCA_RST_RESET_WLAN_RST_MASK diff --git a/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S b/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S index 31a66f1..5ecfa69 100755 --- a/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S +++ b/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S @@ -76,7 +76,7 @@ ahb_max_timeout: * TODO: do we need to reset RTC at all? */ rtc_reset: - li t8, QCA_RST_RST_REG + li t8, QCA_RST_RESET_REG lw t9, 0(t8) or t9, t9, QCA_RST_RESET_RTC_RST_MASK sw t9, 0(t8) diff --git a/u-boot/cpu/mips/ar7240/qca_common.c b/u-boot/cpu/mips/ar7240/qca_common.c index 6d50f80..6c87659 100644 --- a/u-boot/cpu/mips/ar7240/qca_common.c +++ b/u-boot/cpu/mips/ar7240/qca_common.c @@ -1,7 +1,7 @@ /* * Qualcomm/Atheros WiSoCs common/helper functions * - * Copyright (C) 2015 Piotr Dymacz + * Copyright (C) 2016 Piotr Dymacz * * SPDX-License-Identifier: GPL-2.0 */ @@ -28,7 +28,7 @@ void qca_full_chip_reset(void) volatile u32 i = 1; do { - qca_soc_reg_write(QCA_RST_RST_REG, + qca_soc_reg_write(QCA_RST_RESET_REG, QCA_RST_RESET_FULL_CHIP_RST_MASK | QCA_RST_RESET_DDR_RST_MASK); } while (i); diff --git a/u-boot/cpu/mips/ar7240/qca_gpio_init.S b/u-boot/cpu/mips/ar7240/qca_gpio_init.S index 433c2e4..9009928 100644 --- a/u-boot/cpu/mips/ar7240/qca_gpio_init.S +++ b/u-boot/cpu/mips/ar7240/qca_gpio_init.S @@ -465,7 +465,7 @@ first_boot: nop full_reset: - li t8, QCA_RST_RST_REG + li t8, QCA_RST_RESET_REG lw t9, 0(t8) or t9, t9, QCA_RST_RESET_FULL_CHIP_RST_MASK sw t9, 0(t8) diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h index 53879d1..5a1395f 100644 --- a/u-boot/include/soc/qca_soc_common.h +++ b/u-boot/include/soc/qca_soc_common.h @@ -1246,7 +1246,7 @@ #define QCA_RST_MISC_INTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x10 #define QCA_RST_MISC_INTERRUPT_MASK_REG QCA_RST_BASE_REG + 0x14 #define QCA_RST_GLOBALINTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x18 -#define QCA_RST_RST_REG QCA_RST_BASE_REG + 0x1C +#define QCA_RST_RESET_REG QCA_RST_BASE_REG + 0x1C #define QCA_RST_REVISION_ID_REG QCA_RST_BASE_REG + 0x90 #define QCA_RST_GENERAL_TIMER2_REG QCA_RST_BASE_REG + 0x94 #define QCA_RST_GENERAL_TIMER2_RELOAD_REG QCA_RST_BASE_REG + 0x98 -- 2.25.1