From b8cdbfde70de8874fa58288bf3cc2a01bd16477e Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Tue, 22 Mar 2016 01:22:41 +0100 Subject: [PATCH] Remove old and not needed anymore code from old QC/A headers --- u-boot/include/953x.h | 458 ---------------- u-boot/include/ar7240_soc.h | 50 -- u-boot/include/ar934x_soc.h | 1003 ----------------------------------- 3 files changed, 1511 deletions(-) diff --git a/u-boot/include/953x.h b/u-boot/include/953x.h index 67a8127..76df430 100755 --- a/u-boot/include/953x.h +++ b/u-boot/include/953x.h @@ -3486,78 +3486,6 @@ #define ETH_CFG_SW_ONLY_MODE_RESET 0x0 // 0 #define ETH_CFG_ADDRESS 0x18070000 -#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ - -#define CONFIG_BOOTDELAY 1 /* autoboot after 4 seconds */ - -/* Only interrupt boot if special string is typed */ -#define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n" -#undef CONFIG_AUTOBOOT_DELAY_STR -#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ -#define CONFIG_AUTOBOOT_STOP_STR2 "tpl" /* esd special for esd access*/ - -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE {115200} - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_ROOTFS_RD - -#define CONFIG_BOOTARGS_RD "console=ttyS0,115200 root=01:00 rd_start=0x802d0000 rd_size=5242880 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),4096k(rootfs),2048k(uImage)" - -/* XXX - putting rootfs in last partition results in jffs errors */ -#define CONFIG_BOOTARGS_FL "console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),5120k(rootfs),2048k(uImage)" - -#ifdef CONFIG_ROOTFS_FLASH -#define CONFIG_BOOTARGS CONFIG_BOOTARGS_FL -#else -#define CONFIG_BOOTARGS "" -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "ap143-2.0> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 512 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args*/ - -#define CFG_MALLOC_LEN (128*1024) - -#define CFG_BOOTPARAMS_LEN (128*1024) - -#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ -//#define CFG_SDRAM_BASE 0xa0000000 /* Cached addr */ - -//#define CFG_LOAD_ADDR 0x81000000 /* default load address */ -//#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ - -#define CFG_MEMTEST_START 0x80100000 -#undef CFG_MEMTEST_START -#define CFG_MEMTEST_START 0x80200000 -#define CFG_MEMTEST_END 0x83800000 - -/*------------------------------------------------------------------------ - * * * JFFS2 - */ -#define CFG_JFFS_CUSTOM_PART /* board defined part */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=ath-nor0" - -#define CONFIG_MEMSIZE_IN_BYTES - -#define CFG_RX_ETH_BUFFER 16 - - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_ICACHE_SIZE 65536 -#define CFG_CACHELINE_SIZE 32 - /* * Address map */ @@ -3763,384 +3691,6 @@ #define ATH_SPI_CMD_CHIP_ERASE 0xc7 #define ATH_SPI_CMD_RDID 0x9f -#if defined(CFG_ATH_EMULATION) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(2) // 80 MHz -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(1) // 40 MHz - -#elif (CFG_PLL_FREQ == CFG_PLL_550_400_200) - -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(22) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(16) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) -#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_720_600_200) - -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) -#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_720_600_300) - -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) -#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_400_400_200) - -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(16) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(16) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) -#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_720_680_240) - -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(17) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) -#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_720_600_240) - -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) -#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_560_450_220) - -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(14) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(11) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0x100) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) -#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_680_680_226) - -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(1) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(17) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(17) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) -#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_550_600_200) - -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(22) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(24) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) -#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_600_200) - -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(1) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(24) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_650_400_200) - -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(26) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(0xf) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(1) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x2FB) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0x27B) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) -#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - - -#elif (CFG_PLL_FREQ == CFG_PLL_650_600_200) -#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) - -#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(26) -#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) -#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) -#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ - CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ - CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ - CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(0x17) -#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) -#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) -#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(1) | \ - DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ae) | \ - DDR_PLL_DITHER_NFRAC_MIN_SET(0x385) | \ - DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ - DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) - -#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) -#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) -#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) -#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) -#else - # error "CFG_PLL_FREQ not set" -#endif // CFG_PLL_FREQ - #define CPU_CLK_FROM_DDR_PLL CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(0) #define CPU_CLK_FROM_CPU_PLL CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) @@ -4166,14 +3716,6 @@ #endif - -#define __nint_to_mhz(n, ref) ((n) * (ref) * 1000000) -#define __cpu_hz_40(pll) (__nint_to_mhz(CPU_PLL_CONFIG_NINT_GET(pll), 40)) -#define __cpu_hz_25(pll) (__nint_to_mhz(CPU_PLL_CONFIG_NINT_GET(pll), 25)) - -/* Since the count is incremented every other tick, divide by 2 */ -#define CFG_HZ (__cpu_hz_40(CPU_PLL_CONFIG_NINT_VAL) / 2) - /* SGMII DEFINES */ // 32'h18070034 (SGMII_CONFIG) diff --git a/u-boot/include/ar7240_soc.h b/u-boot/include/ar7240_soc.h index 4810f39..8524d89 100644 --- a/u-boot/include/ar7240_soc.h +++ b/u-boot/include/ar7240_soc.h @@ -407,56 +407,6 @@ #define WASP_REF_CLK_25 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */ #define WASP_RAM_TYPE(a) ((a) & 0x3) -#define CFG_934X_SDRAM_CONFIG_VAL 0x7fbe8cd0 -#define CFG_934X_SDRAM_MODE_VAL_INIT 0x133 -#define CFG_934X_SDRAM_MODE_VAL 0x33 -#define CFG_934X_SDRAM_CONFIG2_VAL 0x959f66a8 -#define CFG_934X_SDRAM_TAP_VAL 0x1f1f - -#define CFG_934X_DDR1_CONFIG_VAL 0x7fd48cd0 // 0xc7d48cd0 -#define CFG_934X_DDR1_MODE_VAL_INIT 0x133 -#define CFG_934X_DDR1_EXT_MODE_VAL 0x0 -#define CFG_934X_DDR1_MODE_VAL 0x33 -#define CFG_934X_DDR1_CONFIG2_VAL 0x99d0e6a8 // 0x9dd0e6a8 - -#if (CFG_PLL_FREQ == CFG_PLL_500_500_250) -#define CFG_934X_DDR2_CONFIG_VAL 0xcfbc8cd0 -#define CFG_934X_DDR2_MODE_VAL_INIT 0x143 -#define CFG_934X_DDR2_EXT_MODE_VAL 0x402 -#define CFG_934X_DDR2_MODE_VAL 0x43 -#define CFG_934X_DDR2_CONFIG2_VAL 0xa5d0e6a8 -#define CFG_934X_DDR2_EN_TWL_VAL 0x1659 -#define CFG_934X_DDR2_TAP_VAL 0 -#elif (CFG_PLL_FREQ == CFG_PLL_650_600_300) || \ - (CFG_PLL_FREQ == CFG_PLL_600_600_300) || \ - (CFG_PLL_FREQ == CFG_PLL_600_550_275) || \ - (CFG_PLL_FREQ == CFG_PLL_600_575_287) - -#define CFG_934X_DDR2_CONFIG_VAL 0xcfd48cd0 -#define CFG_934X_DDR2_MODE_VAL_INIT 0x143 -#define CFG_934X_DDR2_EXT_MODE_VAL 0x402 -#define CFG_934X_DDR2_MODE_VAL 0x43 -#define CFG_934X_DDR2_CONFIG2_VAL 0xa1d0e6a8 -#define CFG_934X_DDR2_EN_TWL_VAL 0x1659 -#define CFG_934X_DDR2_TAP_VAL 0x5 -#else -/* -* Date: 2011-030-24 -* Name: Charles Teng -* Reason: patch from LSDK-9.2.0.312 -*/ -#define CFG_934X_DDR2_CONFIG_VAL 0xc7d48cd0 -#define CFG_934X_DDR2_MODE_VAL_INIT 0x133 -#define CFG_934X_DDR2_EXT_MODE_VAL_INIT 0x382 -#define CFG_934X_DDR2_EXT_MODE_VAL 0x402 -#define CFG_934X_DDR2_MODE_VAL 0x33 -#define CFG_934X_DDR2_CONFIG2_VAL 0x9dd0e6a8 -#define CFG_934X_DDR2_EN_TWL_VAL 0xe59 -#define CFG_934X_DDR2_TAP_VAL 0x10012 -#endif - -#define CFG_934X_DDR1_TAP_VAL 0x14 - #define AR7240_REV_ID_AR7130 0xa0 #define AR7240_REV_ID_AR7141 0xa1 #define AR7240_REV_ID_AR7161 0xa2 diff --git a/u-boot/include/ar934x_soc.h b/u-boot/include/ar934x_soc.h index 1d05bf3..c077384 100644 --- a/u-boot/include/ar934x_soc.h +++ b/u-boot/include/ar934x_soc.h @@ -1800,1007 +1800,4 @@ #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x14 // 20 #define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030 - -#if (CFG_PLL_FREQ == CFG_PLL_400_400_200) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(32) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(20) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) - #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_400_200_200) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(32) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(20) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(2) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(2) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(15) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_1_2G_400_200) - - #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(48) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1) - - #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(32) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_500_1G_250) - - #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(48) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(1) - - #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(40) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_550_1_1G_275) - - #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(44) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_400_200) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) - #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_332_166) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(26) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_332_200) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(26) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_266_133) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_266_200) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(16) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_566_550_275) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(22) - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(13) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) - - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40) - #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) - #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(768) | DDR_PLL_DITHER_NFRAC_MAX_SET(768) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_566_525_262) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(13) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) - - #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40) - #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) - #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(128) | DDR_PLL_DITHER_NFRAC_MAX_SET(128) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_566_500_250) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) - - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40) - #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) - #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(512) | DDR_PLL_DITHER_NFRAC_MAX_SET(512) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_566_475_237) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - /* - * Date: 2011-030-24 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.312 - */ - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(19) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(11) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) - - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(41) | CPU_PLL_DITHER_NFRAC_MAX_SET(41) - #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) - #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(1023) - /* - * Date: 2011-030-24 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.312 - */ - #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(895) | DDR_PLL_DITHER_NFRAC_MAX_SET(1023) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_566_450_225) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(36) - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(22) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) - - #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40) - #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) - #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(512) | DDR_PLL_DITHER_NFRAC_MAX_SET(512) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_566_400_200) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(16) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(10) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) - - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(40) | CPU_PLL_DITHER_NFRAC_MAX_SET(40) - #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(9) | CPU_PLL_DITHER_NFRAC_MAX_SET(9) - #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_560_480_240) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(22) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(14) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(19) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(20) - - #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(25) | CPU_PLL_DITHER_NFRAC_MAX_SET(25) - #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(204) | DDR_PLL_DITHER_NFRAC_MAX_SET(204) - #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_650_600_300) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(26) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_600_300) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_550_275) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(22) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_650_325) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(26) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_525_262) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(21) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_575_287) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(23) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(14) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_450_200) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(18) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_533_400_200) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(21) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(13) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) - - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) - #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(20) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_533_500_250) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(21) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(13) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_350_175) - - #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(28) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_300_150) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(24) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(15) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_400_300) - - #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(32) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_500_400_200) - - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(20) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(12) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - /* - * Date: 2011-030-21 - * Name: Charles Teng - * Reason: patch from LSDK-9.2.0.303 - * WASP 1.1 support - */ - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(20) - - #define CPU_PLL_NFRAC_25 CPU_PLL_DITHER_NFRAC_MIN_SET(0) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) - #define CPU_PLL_NFRAC_40 CPU_PLL_DITHER_NFRAC_MIN_SET(32) | CPU_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_25 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - #define DDR_PLL_NFRAC_40 DDR_PLL_DITHER_NFRAC_MIN_SET(0) | DDR_PLL_DITHER_NFRAC_MAX_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_700_400_200) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(28) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(17) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(3) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(32) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(1) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_600_500_250) - - #define CPU_PLL_CONFIG_NINT_VAL_25 CPU_PLL_CONFIG_NINT_SET(24) - #define CPU_PLL_CONFIG_NINT_VAL_40 CPU_PLL_CONFIG_NINT_SET(15) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL_25 DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_NINT_VAL_40 DDR_PLL_CONFIG_NINT_SET(12) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#elif (CFG_PLL_FREQ == CFG_PLL_500_500_250) - - #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(20) - #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) - #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(1) - #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) - - #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(20) - #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) - #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(1) - #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) - - #define CPU_PLL_NFRAC_MIN_SET CPU_PLL_DITHER_NFRAC_MIN_SET(0) - - #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) - #define CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) - #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) - #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) - -#endif - #endif /* _AR934X_SOC_H */ -- 2.25.1