From a8f0d97a4d36034b8fb7dc9a22a6f09232acf2e2 Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Thu, 10 Mar 2016 23:25:01 +0100 Subject: [PATCH] Move DDR_RD_DATA_THIS_CYCLE reg setup in new AR933x dram init code before timing setup --- u-boot/cpu/mips/ar7240/ar933x_dram.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/u-boot/cpu/mips/ar7240/ar933x_dram.c b/u-boot/cpu/mips/ar7240/ar933x_dram.c index 7d0ecbd..05fbc3e 100644 --- a/u-boot/cpu/mips/ar7240/ar933x_dram.c +++ b/u-boot/cpu/mips/ar7240/ar933x_dram.c @@ -153,6 +153,9 @@ void qca_dram_init(void) { u32 mem_type = qca_dram_type(); + /* AR933x supports only 16-bit memory */ + qca_soc_reg_write(QCA_DDR_RD_DATA_THIS_CYCLE_REG, 0xFF); + /* DDR timings (if not defined, use values from old SDK code) */ #ifdef CONFIG_QCA_DDR_CFG_REG_VAL qca_soc_reg_write(QCA_DDR_CFG_REG, CONFIG_QCA_DDR_CFG_REG_VAL); @@ -178,9 +181,6 @@ void qca_dram_init(void) _qca_ddr_cfg2_reg_val(0, 1, 0, 1, 6, 14, 8, 14, 7, 1)); #endif - /* AR933x supports only 16-bit memory */ - qca_soc_reg_write(QCA_DDR_RD_DATA_THIS_CYCLE_REG, 0xFF); - if (mem_type == RAM_MEMORY_TYPE_SDR) { /* Enable SDR */ qca_soc_reg_write(QCA_SDR_CFG_REG, 1); -- 2.25.1