From a7c66ad2e52b49a7cf5efb9665dd0527db96ea29 Mon Sep 17 00:00:00 2001 From: Marian Balakowicz Date: Tue, 14 Mar 2006 16:01:25 +0100 Subject: [PATCH] Correct shift offsets in icache_status and dcache_status for MPC83xx. --- CHANGELOG | 2 ++ cpu/mpc83xx/start.S | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 77f1a254d2..e40ba053e9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Correct shift offsets in icache_status and dcache_status for MPC83xx. + * Add support for DS1374 RTC chip. * Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 46c748f790..324f6c36fe 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -796,7 +796,7 @@ icache_disable: .globl icache_status icache_status: mfspr r3, HID0 - rlwinm r3, r3, HID0_ICE_SHIFT, 31, 31 + rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 blr .globl dcache_enable @@ -828,7 +828,7 @@ dcache_disable: .globl dcache_status dcache_status: mfspr r3, HID0 - rlwinm r3, r3, HID0_DCE_SHIFT, 31, 31 + rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 blr .globl get_pvr -- 2.25.1