From a3f88293ddd13facd734769c1664d35ab4ed681f Mon Sep 17 00:00:00 2001
From: Ben Gardiner <bengardiner@nanometrics.ca>
Date: Thu, 14 Oct 2010 17:26:22 -0400
Subject: [PATCH] da850evm: setup the NAND flash timings

The default NAND flash timings are very conservative. This patch assigns the
timings reccomended in the recent linux kernel patch [1] from Sekhar Nori. The
speedup, as reported in that patch, is 5.3x for reads.

[1] http://www.spinics.net/lists/arm-kernel/msg100278.html

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
CC: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
---
 board/davinci/da8xxevm/da850evm.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index f84adb9b62..0eb9e29ea3 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -24,6 +24,7 @@
 #include <common.h>
 #include <i2c.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
 #include <asm/io.h>
 #include "../common/misc.h"
 #include "common.h"
@@ -98,6 +99,23 @@ int board_init(void)
 	irq_init();
 #endif
 
+
+#ifdef CONFIG_NAND_DAVINCI
+	/*
+	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
+	 * Linux kernel @ 25MHz EMIFA
+	 */
+	writel((DAVINCI_ABCR_WSETUP(0) |
+		DAVINCI_ABCR_WSTROBE(0) |
+		DAVINCI_ABCR_WHOLD(0) |
+		DAVINCI_ABCR_RSETUP(0) |
+		DAVINCI_ABCR_RSTROBE(1) |
+		DAVINCI_ABCR_RHOLD(0) |
+		DAVINCI_ABCR_TA(0) |
+		DAVINCI_ABCR_ASIZE_8BIT),
+	       &davinci_emif_regs->ab2cr); /* CS3 */
+#endif
+
 	/* arch number of the board */
 	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
 
-- 
2.25.1