From 9c71bcdc81b5d5a7acafb4e2b860e3ce68db6108 Mon Sep 17 00:00:00 2001
From: Peter Griffin <peter.griffin@linaro.org>
Date: Thu, 10 Sep 2015 21:55:17 +0100
Subject: [PATCH] ARM: hikey: hi6220: Migrate over to DM_SERIAL and use UART3
 by default.

Use DM for the pl01x serial driver on hikey. Also allow UART0 or
UART3 to be chosen via Kconfig.

By default we now output to UART3 as the latest version of ATF outputs
to this UART. Also UART3 comes out on the LS connector, as opposed to
UART0 which goes to a unpopulated header.

As part of this change we also enable CONFIG_BOARD_EARLY_INIT_F and
call the pinmux configuration code for the UART. Before we were
relying on ATF having already configured the pin configuration.

NB: Upstream Linux kernel doesn't yet support UART3, so serial console
will still be output on UART0 when booting a upstream kernel.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/Kconfig              |  2 +-
 board/hisilicon/hikey/Kconfig |  7 ++++++
 board/hisilicon/hikey/hikey.c | 43 +++++++++++++++++++++++++++++++++++
 configs/hikey_defconfig       |  1 +
 include/configs/hikey.h       | 11 ++++-----
 5 files changed, 56 insertions(+), 8 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5a8d4b2052..0b07e08db6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -604,6 +604,7 @@ config TARGET_HIKEY
 	select ARM64
 	select DM
 	select DM_GPIO
+	select DM_SERIAL
 	  help
 	  Support for HiKey 96boards platform. It features a HI6220
 	  SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
@@ -612,7 +613,6 @@ config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
 	select SUPPORT_SPL
-
 config TARGET_LS1021ATWR
 	bool "Support ls1021atwr"
 	select CPU_V7
diff --git a/board/hisilicon/hikey/Kconfig b/board/hisilicon/hikey/Kconfig
index f7f1055e17..9171502a19 100644
--- a/board/hisilicon/hikey/Kconfig
+++ b/board/hisilicon/hikey/Kconfig
@@ -12,4 +12,11 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "hikey"
 
+config CONS_INDEX
+	int "UART used for console"
+	range 1 4
+	default 4
+	help
+	  The hi6220 SoC has 5 UARTs. For example to use UART0 enter 1 here.
+
 endif
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index 9948747217..c4ae40bfb4 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -6,6 +6,7 @@
  */
 #include <common.h>
 #include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
 #include <errno.h>
 #include <malloc.h>
 #include <netdev.h>
@@ -69,6 +70,48 @@ U_BOOT_DEVICES(hi6220_gpios) = {
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static const struct pl01x_serial_platdata serial_platdata = {
+#if CONFIG_CONS_INDEX == 1
+	.base = HI6220_UART0_BASE,
+#elif CONFIG_CONS_INDEX == 4
+	.base = HI6220_UART3_BASE,
+#else
+#error "Unsuported console index value."
+#endif
+	.type = TYPE_PL011,
+	.clock = 19200000
+};
+
+U_BOOT_DEVICE(hikey_seriala) = {
+	.name = "serial_pl01x",
+	.platdata = &serial_platdata,
+};
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_uart_init(void)
+{
+	switch (CONFIG_CONS_INDEX) {
+	case 1:
+		hi6220_pinmux_config(PERIPH_ID_UART0);
+		break;
+	case 4:
+		hi6220_pinmux_config(PERIPH_ID_UART3);
+		break;
+	default:
+		debug("%s: Unsupported UART selected\n", __func__);
+		return -1;
+	}
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	board_uart_init();
+	return 0;
+}
+#endif
+
 struct peri_sc_periph_regs *peri_sc =
 	(struct peri_sc_periph_regs *)HI6220_PERI_BASE;
 
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index 64a5929e9e..70aa7085fd 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -1,2 +1,3 @@
 CONFIG_ARM=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 # CONFIG_CMD_IMLS is not set
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index ae8187ad1c..b7c22e8c48 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -31,6 +31,8 @@
 /* Flat Device Tree Definitions */
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_BOARD_EARLY_INIT_F
+
 /* Physical Memory Map */
 
 /* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */
@@ -59,13 +61,8 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_8M)
 
-/* PL011 Serial Configuration */
-#define CONFIG_PL011_SERIAL
-
-#define CONFIG_PL011_CLOCK		19200000
-#define CONFIG_PL01x_PORTS		{(void *)0xF8015000}
-#define CONFIG_CONS_INDEX		0
-
+/* Serial port PL010/PL011 through the device model */
+#define CONFIG_PL01X_SERIAL
 #define CONFIG_BAUDRATE			115200
 
 #define CONFIG_CMD_USB
-- 
2.25.1