From 8e9e62c946e295ca8e0b81d07b6b1cc884a70bc1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 4 Apr 2016 17:28:16 +0200 Subject: [PATCH] ddr: altera: Fix scc_mgr_set() argument order The code should be setting registers to zero, not one register to value. Swap the order of arguments to correct the behavior. The behavior is now in-line with code generated by Quartus 15.1 . Signed-off-by: Marek Vasut Cc: Dinh Nguyen Cc: Chin Liang See --- drivers/ddr/altera/sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index bf74b4e651..3859e66a00 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -279,7 +279,7 @@ static void scc_mgr_initialize(void) for (i = 0; i < 16; i++) { debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n", __func__, __LINE__, i); - scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i); + scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0); } } -- 2.25.1