From 880e46f2d33c382a1acb449e277cf4f535b5c62a Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Fri, 17 Jul 2015 00:45:11 +0200
Subject: [PATCH] ddr: altera: Rework initialize_tracking()

Clean the function up by getting rid of all the insane XOR-leftshift
combos when assembling register values. While at it, remove all the
ad-hoc variables necessary for this XOR-leftshift voodoo. Finally,
get rid of the iterative division implementation of two constants
and replace it with a DIV_ROUND_UP() macro :-)

Signed-off-by: Marek Vasut <marex@denx.de>
---
 drivers/ddr/altera/sequencer.c | 88 ++++++++++++++--------------------
 1 file changed, 35 insertions(+), 53 deletions(-)

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 28e32ff575..aceb6a06e1 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3612,65 +3612,47 @@ static void initialize_hps_phy(void)
 	writel(reg, &sdr_ctrl->phy_ctrl2);
 }
 
+/**
+ * initialize_tracking() - Initialize tracking
+ *
+ * Initialize the register file with usable initial data.
+ */
 static void initialize_tracking(void)
 {
-	uint32_t concatenated_longidle = 0x0;
-	uint32_t concatenated_delays = 0x0;
-	uint32_t concatenated_rw_addr = 0x0;
-	uint32_t concatenated_refresh = 0x0;
-	uint32_t trk_sample_count = 7500;
-	uint32_t dtaps_per_ptap;
-	uint32_t tmp_delay;
+	/*
+	 * Initialize the register file with the correct data.
+	 * Compute usable version of value in case we skip full
+	 * computation later.
+	 */
+	writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
+	       &sdr_reg_file->dtaps_per_ptap);
+
+	/* trk_sample_count */
+	writel(7500, &sdr_reg_file->trk_sample_count);
+
+	/* longidle outer loop [15:0] */
+	writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
 
 	/*
-	 * compute usable version of value in case we skip full
-	 * computation later
+	 * longidle sample count [31:24]
+	 * trfc, worst case of 933Mhz 4Gb [23:16]
+	 * trcd, worst case [15:8]
+	 * vfifo wait [7:0]
 	 */
-	dtaps_per_ptap = 0;
-	tmp_delay = 0;
-	while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
-		dtaps_per_ptap++;
-		tmp_delay += IO_DELAY_PER_DCHAIN_TAP;
-	}
-	dtaps_per_ptap--;
-
-	concatenated_longidle = concatenated_longidle ^ 10;
-		/*longidle outer loop */
-	concatenated_longidle = concatenated_longidle << 16;
-	concatenated_longidle = concatenated_longidle ^ 100;
-		/*longidle sample count */
-	concatenated_delays = concatenated_delays ^ 243;
-		/* trfc, worst case of 933Mhz 4Gb */
-	concatenated_delays = concatenated_delays << 8;
-	concatenated_delays = concatenated_delays ^ 14;
-		/* trcd, worst case */
-	concatenated_delays = concatenated_delays << 8;
-	concatenated_delays = concatenated_delays ^ 10;
-		/* vfifo wait */
-	concatenated_delays = concatenated_delays << 8;
-	concatenated_delays = concatenated_delays ^ 4;
-		/* mux delay */
-
-	concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_IDLE;
-	concatenated_rw_addr = concatenated_rw_addr << 8;
-	concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_ACTIVATE_1;
-	concatenated_rw_addr = concatenated_rw_addr << 8;
-	concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_SGLE_READ;
-	concatenated_rw_addr = concatenated_rw_addr << 8;
-	concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_PRECHARGE_ALL;
-
-	concatenated_refresh = concatenated_refresh ^ RW_MGR_REFRESH_ALL;
-	concatenated_refresh = concatenated_refresh << 24;
-	concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
+	writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
+	       &sdr_reg_file->delays);
 
-	/* Initialize the register file with the correct data */
-	writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
-	writel(trk_sample_count, &sdr_reg_file->trk_sample_count);
-	writel(concatenated_longidle, &sdr_reg_file->trk_longidle);
-	writel(concatenated_delays, &sdr_reg_file->delays);
-	writel(concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr);
-	writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, &sdr_reg_file->trk_read_dqs_width);
-	writel(concatenated_refresh, &sdr_reg_file->trk_rfsh);
+	/* mux delay */
+	writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
+	       (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
+	       &sdr_reg_file->trk_rw_mgr_addr);
+
+	writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
+	       &sdr_reg_file->trk_read_dqs_width);
+
+	/* trefi [7:0] */
+	writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
+	       &sdr_reg_file->trk_rfsh);
 }
 
 int sdram_calibration_full(void)
-- 
2.25.1