From 864915561b3273a4f8894804146d6739e8e49ab2 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 10 Aug 2018 02:39:37 -0700 Subject: [PATCH] x86: coreboot: Add default TSC frequency in the device tree It was observed sometimes U-Boot as the coreboot payload fails to boot on QEMU. This is because TSC calibration fails with no valid frequency. This adds default TSC frequency in the device tree. Signed-off-by: Bin Meng Reviewed-by: Christian Gmeiner --- arch/x86/dts/coreboot.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts index a94f781833..e212f3dc7d 100644 --- a/arch/x86/dts/coreboot.dts +++ b/arch/x86/dts/coreboot.dts @@ -30,6 +30,10 @@ stdout-path = "/serial"; }; + tsc-timer { + clock-frequency = <1000000000>; + }; + pci { compatible = "pci-x86"; u-boot,dm-pre-reloc; -- 2.25.1