From 82719ce57519130236db355778ff0233be7d75b7 Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Tue, 22 Mar 2016 00:53:34 +0100 Subject: [PATCH] Add SWITCH_CLOCK_CONTROL register definition in common QC/A header --- u-boot/include/soc/qca_soc_common.h | 38 ++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h index 2abf5d5..64290b0 100644 --- a/u-boot/include/soc/qca_soc_common.h +++ b/u-boot/include/soc/qca_soc_common.h @@ -945,7 +945,7 @@ #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x14 #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x18 #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x1C - #define QCA_PLL_SWITCH_CLK_SPARE_REG QCA_PLL_BASE_REG + 0x20 + #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x20 #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x24 #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x28 #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x2C @@ -1125,6 +1125,42 @@ #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT 24 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT) +/* SWITCH_CLOCK_CONTROL */ +#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT 0 +#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT) +#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT 1 +#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT) +#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT 2 +#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT) +#define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT 3 +#define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT) +#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT 4 +#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT) +#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT 5 +#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT) + +#if (SOC_TYPE & QCA_AR934X_SOC) |\ + (SOC_TYPE & QCA_QCA953X_SOC) + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT 6 + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT) +#else + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT 6 + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT 12 + #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT 13 + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT 14 + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT 15 + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT) +#endif + +#define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT 7 +#define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT) +#define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT 8 +#define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_MASK BITS(QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT, 4) + /* DDR_PLL_DITHER register (DDR PLL dither parameter) */ #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT 0 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT, 10) -- 2.25.1