From 7a9fe56452dd544ec5884af784bfd7f1c3bbc45a Mon Sep 17 00:00:00 2001 From: Imre Kaloz Date: Tue, 7 Apr 2015 21:29:26 +0000 Subject: [PATCH] generic/3.18: upgrade to 3.18.11 Signed-off-by: Imre Kaloz SVN-Revision: 45303 --- include/kernel-version.mk | 4 +- .../668-fix-ipv6-throw-routes.patch | 31 ------- ...td-nand-pxa3xx-Fix-PIO-FIFO-draining.patch | 92 ------------------- 3 files changed, 2 insertions(+), 125 deletions(-) delete mode 100644 target/linux/generic/patches-3.18/668-fix-ipv6-throw-routes.patch delete mode 100644 target/linux/mvebu/patches-3.18/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch diff --git a/include/kernel-version.mk b/include/kernel-version.mk index 8c3d371766..522c2f3a2c 100644 --- a/include/kernel-version.mk +++ b/include/kernel-version.mk @@ -6,14 +6,14 @@ LINUX_VERSION-3.8 = .13 LINUX_VERSION-3.10 = .58 LINUX_VERSION-3.13 = .7 LINUX_VERSION-3.14 = .35 -LINUX_VERSION-3.18 = .10 +LINUX_VERSION-3.18 = .11 LINUX_VERSION-4.0 = -rc6 LINUX_KERNEL_MD5SUM-3.8.13 = 2af19d06cd47ec459519159cdd10542d LINUX_KERNEL_MD5SUM-3.10.58 = 3ff3478b6351143cef22d4b81cf48b01 LINUX_KERNEL_MD5SUM-3.13.7 = 370adced5e5c1cb1d0d621c2dae2723f LINUX_KERNEL_MD5SUM-3.14.35 = e5e92c40d14bc8ae9a8701db4e1cbb27 -LINUX_KERNEL_MD5SUM-3.18.10 = 1e8ad8a122e332e429d4c786ece4582e +LINUX_KERNEL_MD5SUM-3.18.11 = 2def91951c9cedf7896efb864e0c090c LINUX_KERNEL_MD5SUM-4.0-rc6 = bec0aeeacab2852d9a17ccbfa7e280f8 ifdef KERNEL_PATCHVER diff --git a/target/linux/generic/patches-3.18/668-fix-ipv6-throw-routes.patch b/target/linux/generic/patches-3.18/668-fix-ipv6-throw-routes.patch deleted file mode 100644 index 283ffce911..0000000000 --- a/target/linux/generic/patches-3.18/668-fix-ipv6-throw-routes.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 9cd600244515bd4540898411ab781a97f0cc387f Mon Sep 17 00:00:00 2001 -From: Steven Barth -Date: Thu, 19 Mar 2015 11:54:50 +0100 -Subject: [PATCH] ipv6: fix backtracking for throw routes - -for throw routes to trigger evaluation of other policy rules -EAGAIN needs to be propagated up to fib_rules_lookup -similar to how its done for IPv4 - -A simple testcase for verification is: - -ip -6 rule add lookup 33333 priority 33333 -ip -6 route add throw 2001:db8::1 -ip -6 route add 2001:db8::1 via fe80::1 dev wlan0 table 33333 -ip route get 2001:db8::1 - -Signed-off-by: Steven Barth ---- - net/ipv6/fib6_rules.c | 1 + - 1 file changed, 1 insertion(+) - ---- a/net/ipv6/fib6_rules.c -+++ b/net/ipv6/fib6_rules.c -@@ -104,6 +104,7 @@ static int fib6_rule_action(struct fib_r - goto again; - flp6->saddr = saddr; - } -+ err = rt->dst.error; - goto out; - } - again: diff --git a/target/linux/mvebu/patches-3.18/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch b/target/linux/mvebu/patches-3.18/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch deleted file mode 100644 index a841f5eadd..0000000000 --- a/target/linux/mvebu/patches-3.18/019-mtd-nand-pxa3xx-Fix-PIO-FIFO-draining.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 11aa9df4de06cc257327d783c5cb615989e87286 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Fri, 23 Jan 2015 15:18:27 +0100 -Subject: [PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining - -The NDDB register holds the data that are needed by the read and write -commands. - -However, during a read PIO access, the datasheet specifies that after each 32 -bits read in that register, when BCH is enabled, we have to make sure that the -RDDREQ bit is set in the NDSR register. - -This fixes an issue that was seen on the Armada 385, and presumably other mvebu -SoCs, when a read on a newly erased page would end up in the driver reporting a -timeout from the NAND. - -Cc: # v3.14 -Signed-off-by: Maxime Ripard ---- - drivers/mtd/nand/pxa3xx_nand.c | 45 ++++++++++++++++++++++++++++++++++++------ - 1 file changed, 39 insertions(+), 6 deletions(-) - ---- a/drivers/mtd/nand/pxa3xx_nand.c -+++ b/drivers/mtd/nand/pxa3xx_nand.c -@@ -23,6 +23,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -480,6 +481,38 @@ static void disable_int(struct pxa3xx_na - nand_writel(info, NDCR, ndcr | int_mask); - } - -+static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) -+{ -+ u32 *dst = (u32 *)data; -+ -+ if (info->ecc_bch) { -+ while (len--) { -+ u32 timeout; -+ -+ *dst++ = nand_readl(info, NDDB); -+ -+ /* -+ * According to the datasheet, when reading -+ * from NDDB with BCH enabled, after each 32 -+ * bits reads, we have to make sure that the -+ * NDSR.RDDREQ bit is set -+ */ -+ timeout = jiffies + msecs_to_jiffies(5); -+ while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) { -+ if (!time_before(jiffies, timeout)) { -+ dev_err(&info->pdev->dev, -+ "Timeout on RDDREQ while draining the FIFO\n"); -+ return; -+ } -+ -+ cpu_relax(); -+ } -+ } -+ } else { -+ __raw_readsl(info->mmio_base + NDDB, data, len); -+ } -+} -+ - static void handle_data_pio(struct pxa3xx_nand_info *info) - { - unsigned int do_bytes = min(info->data_size, info->chunk_size); -@@ -496,14 +529,14 @@ static void handle_data_pio(struct pxa3x - DIV_ROUND_UP(info->oob_size, 4)); - break; - case STATE_PIO_READING: -- __raw_readsl(info->mmio_base + NDDB, -- info->data_buff + info->data_buff_pos, -- DIV_ROUND_UP(do_bytes, 4)); -+ drain_fifo(info, -+ info->data_buff + info->data_buff_pos, -+ DIV_ROUND_UP(do_bytes, 4)); - - if (info->oob_size > 0) -- __raw_readsl(info->mmio_base + NDDB, -- info->oob_buff + info->oob_buff_pos, -- DIV_ROUND_UP(info->oob_size, 4)); -+ drain_fifo(info, -+ info->oob_buff + info->oob_buff_pos, -+ DIV_ROUND_UP(info->oob_size, 4)); - break; - default: - dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__, -- 2.25.1