From 7a78f148d6a7298e4fface680dc7eacd877b1aba Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Wed, 31 Jan 2007 15:54:29 -0600 Subject: [PATCH] mpc83xx: Add support for the MPC8349E-mITX-GP Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX. Bonus features include support for low-boot (BMS bit in HRCW is 0) for the ITX and a README for the ITX and the ITX-GP. Signed-off-by: Timur Tabi --- MAINTAINERS | 1 + MAKEALL | 4 +- Makefile | 15 +- board/mpc8349itx/config.mk | 6 +- board/mpc8349itx/mpc8349itx.c | 22 +- doc/README.mpc8349itx | 187 ++++++++++++++ include/configs/MPC8349ITX.h | 459 +++++++++++++--------------------- include/mpc83xx.h | 41 +++ 8 files changed, 447 insertions(+), 288 deletions(-) create mode 100644 doc/README.mpc8349itx diff --git a/MAINTAINERS b/MAINTAINERS index 1d0a8dfdb3..183fb10d96 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -350,6 +350,7 @@ John Zhan Timur Tabi MPC8349E-mITX MPC8349 + MPC8349E-mITX-GP MPC8349 Kim Phillips diff --git a/MAKEALL b/MAKEALL index f259e681ce..816210e44a 100755 --- a/MAKEALL +++ b/MAKEALL @@ -132,8 +132,8 @@ LIST_8260=" \ ######################################################################### LIST_83xx=" \ - MPC832XEMDS MPC8349EMDS MPC8349ITX MPC8360EMDS \ - sbc8349 TQM834x \ + MPC832XEMDS MPC8349EMDS MPC8349ITX MPC8349ITXGP \ + MPC8360EMDS sbc8349 TQM834x \ " diff --git a/Makefile b/Makefile index 3e4afcc2a6..47008ee9c7 100644 --- a/Makefile +++ b/Makefile @@ -1642,8 +1642,19 @@ MPC832XEMDS_SLAVE_config: unconfig MPC8349EMDS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds -MPC8349ITX_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349itx +MPC8349ITX_config \ +MPC8349ITX_LOWBOOT_config \ +MPC8349ITXGP_config: unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/mpc8349itx + @echo "#define CONFIG_$(subst _LOWBOOT,,$(@:_config=))" >> $(obj)include/config.h + @if [ "$(findstring GP,$@)" ] ; then \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + fi + @if [ "$(findstring LOWBOOT,$@)" ] ; then \ + echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \ + fi + @$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx MPC8360EMDS_config \ MPC8360EMDS_HOST_33_config \ diff --git a/board/mpc8349itx/config.mk b/board/mpc8349itx/config.mk index 2e113118bd..1901fdc2ce 100644 --- a/board/mpc8349itx/config.mk +++ b/board/mpc8349itx/config.mk @@ -21,10 +21,14 @@ # # -# MPC8349ITX +# MPC8349E-mITX and MPC8349E-mITX-GP # +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE TEXT_BASE = 0xFEF00000 +endif ifneq ($(OBJTREE),$(SRCTREE)) # We are building u-boot in a separate directory, use generated diff --git a/board/mpc8349itx/mpc8349itx.c b/board/mpc8349itx/mpc8349itx.c index 72c47f4e62..2b3ded1762 100644 --- a/board/mpc8349itx/mpc8349itx.c +++ b/board/mpc8349itx/mpc8349itx.c @@ -168,7 +168,11 @@ long int initdram(int board_type) int checkboard(void) { +#ifdef CONFIG_MPC8349ITX puts("Board: Freescale MPC8349E-mITX\n"); +#else + puts("Board: Freescale MPC8349E-mITX-GP\n"); +#endif return 0; } @@ -181,6 +185,7 @@ int checkboard(void) */ int misc_init_f(void) { +#ifdef CONFIG_VSC7385 volatile u32 *vsc7385_cpuctrl; /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up @@ -200,6 +205,7 @@ int misc_init_f(void) vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0); *vsc7385_cpuctrl |= 0x0c; +#endif #ifdef CONFIG_COMPACT_FLASH /* UPM Table Configuration Code */ @@ -269,9 +275,19 @@ int misc_init_r(void) #ifdef CFG_I2C_EEPROM_ADDR static u8 eeprom_data[] = /* HRCW data */ { - 0xaa, 0x55, 0xaa, - 0x7c, 0x02, 0x40, 0x05, 0x04, 0x00, 0x00, - 0x7c, 0x02, 0x41, 0xb4, 0x60, 0xa0, 0x00, + 0xAA, 0x55, 0xAA, /* Preamble */ + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x40, /* RCWL ADDR=0x0_0900 */ + (CFG_HRCW_LOW >> 24) & 0xFF, + (CFG_HRCW_LOW >> 16) & 0xFF, + (CFG_HRCW_LOW >> 8) & 0xFF, + CFG_HRCW_LOW & 0xFF, + 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */ + 0x02, 0x41, /* RCWH ADDR=0x0_0904 */ + (CFG_HRCW_HIGH >> 24) & 0xFF, + (CFG_HRCW_HIGH >> 16) & 0xFF, + (CFG_HRCW_HIGH >> 8) & 0xFF, + CFG_HRCW_HIGH & 0xFF }; u8 data[sizeof(eeprom_data)]; diff --git a/doc/README.mpc8349itx b/doc/README.mpc8349itx new file mode 100644 index 0000000000..4ae03ae055 --- /dev/null +++ b/doc/README.mpc8349itx @@ -0,0 +1,187 @@ +Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards +--------------------------------------------------- + +1. Board Description + + The MPC8349E-mITX and MPC8349E-mITX-GP are reference boards featuring + the Freescale MPC8349E processor in a Mini-ITX form factor. + + The MPC8349E-mITX-GP is an MPC8349E-mITX with the following differences: + + A) One 8MB on-board flash EEPROM chip, instead of two. + B) No SATA controller + C) No Compact Flash slot + D) No Mini-PCI slot + E) No Vitesse 7385 5-port Ethernet switch + F) No 4-port USB Type-A interface + +2. Board Switches and Jumpers + +2.0 Descriptions for all of the board jumpers can be found in the User + Guide. Of particular interest to U-Boot developers is jumper J22: + + Pos. Name Default Description + ----------------------------------------------------------------------- + A LGPL0 ON (0) HRCW source, bit 0 + B LGPL1 ON (0) HRCW source, bit 1 + C LGPL3 ON (0) HRCW source, bit 2 + D LGPL5 OFF (1) PCI_SYNC_OUT frequency + E BOOT1 ON (0) Flash EEPROM boot device + F PCI_M66EN ON (0) PCI 66MHz enable + G I2C-WP ON (0) I2C EEPROM write protection + H F_WP OFF (1) Flash EEPROM write protection + + Jumper J22.E is only for the ITX, and it decides the configuration + of the flash chips. If J22.E is ON (i.e. jumpered), then flash chip + U4 is located at address FE000000 and flash chip U7 is at FE800000. + If J22.E is OFF, then U7 is at FE000000 and U4 is at FE800000. + + For U-Boot development, J22.E can be used to switch back-and-forth + between two U-Boot images. + +3. Memory Map + +3.1. The memory map should look pretty much like this: + + 0x0000_0000 - 0x0FFF_FFFF DDR SDRAM (256 MB) + 0x8000_0000 - 0x9FFF_FFFF PCI1 memory space (512 MB) + 0xA000_0000 - 0xBFFF_FFFF PCI2 memory space (512 MB) + 0xE000_0000 - 0xEFFF_FFFF IMMR (1 MB) + 0xE200_0000 - 0xE2FF_FFFF PCI1 I/O space (16 MB) + 0xE300_0000 - 0xE3FF_FFFF PCI2 I/O space (16 MB) + 0xF000_0000 - 0xF000_FFFF Compact Flash (ITX only) + 0xF001_0000 - 0xF001_FFFF Local bus expansion slot + 0xF800_0000 - 0xF801_FFFF Vitesse 7385 Parallel Interface (ITX only) + 0xFE00_0000 - 0xFE7F_FFFF First 8MB bank of Flash memory + 0xFE80_0000 - 0xFEFF_FFFF Second 8MB bank of Flash memory (ITX only) + +3.2 Flash EEPROM layout. + + On the ITX, jumper J22.E is used to determine which flash chips are + at which address. When J22.E is switched, addresses from FE000000 + to FE7FFFFF are swapped with addresses from FE800000 to FEFFFFFF. + + On the ITX, at the normal boot address (aka HIGHBOOT): + + FE00_0000 HRCW + FE70_0000 Alternative U-Boot image + FE80_0000 Alternative HRCW + FEF0_0000 U-Boot image + FEFF_FFFF End of flash + + On the ITX, at the low boot address (LOWBOOT) + + FE00_0000 HRCW and U-Boot image + FE04_0000 U-Boot environment variables + FE80_0000 Alternative HRCW and U-Boot image + FEFF_FFFF End of flash + + On the ITX-GP, the only option is LOWBOOT and there is only one chip + + FE00_0000 HRCW and U-Boot image + FE04_0000 U-Boot environment variables + F7FF_FFFF End of flash + +4. Definitions + +4.1 Explanation of NEW definitions in: + + include/configs/MPC8349ITX.h + + CONFIG_MPC83XX MPC83xx family + CONFIG_MPC8349 MPC8349 specific + CONFIG_MPC8349ITX MPC8349E-mITX + CONFIG_MPC8349ITXGP MPC8349E-mITX-GP + +5. Compilation + + Assuming you're using BASH shell: + + export CROSS_COMPILE=your-cross-compile-prefix + cd u-boot + make distclean + + make MPC8349ITX_config + or: + make MPC8349ITXGP_config + or: + make MPC8349ITX_LOWBOOT_config + + make + +6. Downloading and Flashing Images + +6.1 Download via tftp: + + tftp $loadaddr + + where "" is the path and filename, on the TFTP server, of + the U-Boot image. + +6.1 Reflash U-Boot Image using U-Boot + + setenv uboot + run tftpflash + + where "" is the path and filename, on the TFTP server, of + the U-Boot image. + +6.2 Using the HRCW to switch between two different U-Boot images on the ITX + + Because the ITX has 16MB of flash, it is possible to keep two U-Boot + images in flash, and use the HRCW to specify which one is to be used + when the board boots. This trick is especially effective with a + hardware debugger that can override the HRCW, such as the BDI-2000. + + When the BMS bit in the HRCW is 0, the ITX will boot the U-Boot image + at address FE000000. When the BMS bit is 1, the ITX will boot the + image at address FEF00000. + + Therefore, just put a U-Boot image at both FE000000 and FEF00000 and + change the BMS bit whenever you want to boot the other image. + + Step-by-step instructions: + + 1) Build an ITX image to be loaded at FEF00000 + + make distclean + make MPC8349ITX_config + make + + 2) Take the u-boot.bin image and flash it at FEF00000. + + tftp $loadaddr u-boot.bin + protect off all + erase FEF00000 +$filesize + cp.b $loadaddr FEF00000 $filesize + + 3) Build an ITX image to be loaded at FE000000 + + make distclean + make MPC8349ITX_LOWBOOT_config + make + + 4) Take the u-boot.bin image and flash it at FE000000. + + tftp $loadaddr u-boot.bin + protect off FE000000 +$filesize + erase FE000000 +$filesize + cp.b $loadaddr FE000000 $filesize + + The HRCW in flash is currently set to boot the image at FE000000. + + If you have a hardware debugger, configure it to set the HRCW to + B460A000 04040000 if you want to boot the image at FEF00000, or set + it to B060A000 04040000 if you want to boot the image at FE000000. + + To change the HRCW in flash to boot the image at FEF00000, use these + U-Boot commands: + + cp.b FE000000 1000 10000 ; copy 1st flash sector to 1000 + mw.b 1020 b4 8 ; modify BMS bit + protect off FE000000 +10000 + erase FE000000 +10000 + cp.b 1000 FE000000 10000 + +7. Notes + 1) The console baudrate for MPC8349EITX is 115200bps. diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index cbdbb2921d..37bbfb336d 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -21,7 +21,7 @@ */ /* - MPC8349E-mITX board configuration file + MPC8349E-mITX and MPC8349E-mITX-GP board configuration file Memory map: @@ -31,11 +31,11 @@ 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) - 0xF000_0000-0xF000_FFFF Compact Flash + 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) 0xF001_0000-0xF001_FFFF Local bus expansion slot - 0xF800_0000-0xF801_FFFF GBE L2 Switch VSC7385 - 0xFF00_0000-0xFF7F_FFFF Alternative bank of Flash memory (8MB) - 0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB) + 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) + 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory + 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) I2C address list: Align. Board @@ -56,7 +56,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#undef DEBUG +#if (TEXT_BASE == 0xFE000000) +#define CFG_LOWBOOT +#endif /* * High Level Configuration Options @@ -64,14 +66,26 @@ #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ #define CONFIG_MPC8349 /* MPC8349 specific */ -#define CONFIG_PCI +#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ + + +/* On-board devices */ +#ifdef CONFIG_MPC8349ITX #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ -#define CONFIG_RTC_DS1337 +#define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */ +#endif -/* I2C */ +#define CONFIG_PCI +#define CONFIG_RTC_DS1337 #define CONFIG_HARD_I2C +#define CONFIG_TSEC_ENET /* TSEC Ethernet support */ +/* + * Device configurations + */ + +/* I2C */ #ifdef CONFIG_HARD_I2C #define CONFIG_MISC_INIT_F @@ -111,59 +125,40 @@ #endif -#define CONFIG_TSEC_ENET /* tsec ethernet support */ -#define CONFIG_ENV_OVERWRITE +/* Compact Flash */ +#ifdef CONFIG_COMPACT_FLASH -#define PCI_66M -#ifdef PCI_66M -#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ -#else -#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ -#endif +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 1 -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef PCI_66M -#define CONFIG_SYS_CLK_FREQ 66666666 -#else -#define CONFIG_SYS_CLK_FREQ 33333333 -#endif -#endif +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR CFG_CF_BASE +#define CFG_ATA_DATA_OFFSET 0x0000 +#define CFG_ATA_REG_OFFSET 0 +#define CFG_ATA_ALT_OFFSET 0x0200 +#define CFG_ATA_STRIDE 2 -#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ +#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00003000 /* memtest region */ -#define CFG_MEMTEST_END 0x07100000 /* only has 128M */ +#define CONFIG_DOS_PARTITION -/* - * DDR Setup - */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#endif /* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. + * DDR Setup */ -#undef CONFIG_DDR_32BIT - -#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CFG_SDRAM_BASE CFG_DDR_BASE -#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE -#undef CONFIG_DDR_2T_TIMING +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE #define CFG_83XX_DDR_USES_CS0 +#define CFG_MEMTEST_START 0x1000 /* memtest region */ +#define CFG_MEMTEST_END 0x2000 -#ifndef CONFIG_SPD_EEPROM -/* - * Manually set up DDR parameters - */ +#ifdef CONFIG_HARD_I2C +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#endif + +#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ #define CFG_DDR_SIZE 256 /* Mb */ #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) @@ -171,46 +166,65 @@ #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ #endif -/* FLASH on the Local Bus */ +/* + *Flash on the Local Bus + */ + #define CFG_FLASH_CFI /* use the Common Flash Interface */ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ #define CFG_FLASH_EMPTY_INFO +#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +/* The ITX has two flash chips, but the ITX-GP has only one. To support both +boards, we say we have two, but don't display a message if we find only one. */ +#define CFG_FLASH_QUIET_TEST +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} +#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ +#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ + +/* + * BRx, ORx, LBLAWBARx, and LBLAWARx + */ + +/* Flash */ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) -#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16Mb window bytes */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE +#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) -/* VSC7385 on the Local Bus */ -#define CFG_VSC7385_BASE 0xF8000000 /* start of VSC7385 */ +/* Vitesse 7385 */ -#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) -#define CFG_OR1_PRELIM (0xFFFE0000 /* 128KB */ | \ - OR_GPCM_CSNT | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_SETA | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#ifdef CONFIG_VSC7385 -#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE /* Access window base at VSC7385 base */ -#define CFG_LBLAWAR1_PRELIM 0x80000010 /* Access window size 128K */ +#define CFG_VSC7385_BASE 0xF8000000 -#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 135 /* sectors per device */ +#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) +#define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ + OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} +#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE +#define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) -#undef CFG_FLASH_CHECKSUM -#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#endif -#define CFG_LED_BASE 0xF9000000 /* start of LED and Board ID */ +/* LED */ + +#define CFG_LED_BASE 0xF9000000 #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) -#define CFG_OR2_PRELIM (0xFFE00000 /* 2MB */ | \ - OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | \ - OR_GPCM_SCY_9 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ + OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) + +/* Compact Flash */ #ifdef CONFIG_COMPACT_FLASH @@ -219,32 +233,16 @@ #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) -#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */ -#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */ - -#undef CONFIG_IDE_RESET -#undef CONFIG_IDE_PREINIT - -#define CFG_IDE_MAXBUS 1 -#define CFG_IDE_MAXDEVICE 1 - -#define CFG_ATA_IDE0_OFFSET 0x0000 -#define CFG_ATA_BASE_ADDR CFG_CF_BASE -#define CFG_ATA_DATA_OFFSET 0x0000 -#define CFG_ATA_REG_OFFSET 0 -#define CFG_ATA_ALT_OFFSET 0x0200 -#define CFG_ATA_STRIDE 2 - -#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ +#define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE +#define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) #endif -#define CONFIG_DOS_PARTITION - -#define CFG_MID_FLASH_JUMP 0x7F000000 +/* + * U-Boot memory configuration + */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ - #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else @@ -253,10 +251,10 @@ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK -#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ -#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -272,97 +270,9 @@ #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) #define CFG_LBC_LBCR 0x00000000 -#undef CFG_LB_SDRAM /* if board has SRDAM on local bus */ - -#ifdef CFG_LB_SDRAM -/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CFG_LBLAWBAR2_PRELIM 0xF0000000 -#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ - -#define CFG_BR2_PRELIM (CFG_LBC_SDRAM_BASE | BR_PS_32 | BR_MS_SDRAM | BR_V) -#define CFG_OR2_PRELIM (0xFC000000 /* 64 MB */ | \ - OR_SDRAM_XAM | \ - ((9 - 7) << OR_SDRAM_COLS_SHIFT) | \ - ((13 - 9) << OR_SDRAM_ROWS_SHIFT) | \ - OR_SDRAM_EAD) - #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ -/* - * LSDMR masks - */ -#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) -#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) -#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) -#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ - | CFG_LBC_LSDMR_BSMA1516 \ - | CFG_LBC_LSDMR_RFCR8 \ - | CFG_LBC_LSDMR_PRETOACT6 \ - | CFG_LBC_LSDMR_ACTTORW3 \ - | CFG_LBC_LSDMR_BL8 \ - | CFG_LBC_LSDMR_WRC3 \ - | CFG_LBC_LSDMR_CL3 \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_PCHALL) -#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_ARFRSH) -#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_MRW) -#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ - | CFG_LBC_LSDMR_OP_NORMAL) -#endif - /* * Serial Port */ @@ -374,20 +284,16 @@ #define CFG_NS16550_CLK get_bus_freq(0) #define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_BAUDRATE 115200 #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) -/* Use the HUSH parser */ -#define CFG_HUSH_PARSER -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " -#endif - /* pass open firmware flat tree */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_FLAT_TREE +#define CONFIG_OF_BOARD_SETUP /* maximum size of the flat tree (8K) */ #define OF_FLAT_TREE_MAX_SIZE 8192 @@ -397,6 +303,9 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" +/* + * PCI + */ #ifdef CONFIG_PCI #define CONFIG_MPC83XX_PCI2 @@ -447,14 +356,18 @@ #endif +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#endif + /* TSEC */ #ifdef CONFIG_TSEC_ENET -#ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI -#endif - #define CONFIG_MII #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ @@ -468,6 +381,7 @@ #endif #ifdef CONFIG_MPC83XX_TSEC2 +#define CONFIG_HAS_ETH1 #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" #define CFG_TSEC2_OFFSET 0x25000 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ @@ -479,14 +393,15 @@ #endif - /* * Environment */ +#define CONFIG_ENV_OVERWRITE + #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE)) #define CFG_ENV_SIZE 0x2000 #else #define CFG_NO_FLASH /* Flash is not usable now */ @@ -533,16 +448,23 @@ /* Watchdog */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#ifdef CONFIG_WATCHDOG -#define CFG_WATCHDOG_VALUE 0xFFFFFFC3 -#endif /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + #define CFG_LOAD_ADDR 0x2000000 /* default load address */ -#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#ifdef CONFIG_MPC8349ITX +#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ +#endif #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -562,15 +484,15 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ +/* + * Cache Configuration + */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ #endif -#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - #define CFG_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ HRCWL_DDR_TO_SCB_CLK_1X1 |\ @@ -578,12 +500,12 @@ HRCWL_VCO_1X2 |\ HRCWL_CORE_TO_CSB_2X1) -#ifdef PCI_64BIT +#ifdef CFG_LOWBOOT #define CFG_HRCW_HIGH (\ HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ + HRCWH_32_BIT_PCI |\ HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ HRCWH_FROM_0X00000100 |\ HRCWH_BOOTSEQ_DISABLE |\ @@ -596,7 +518,7 @@ HRCWH_PCI_HOST |\ HRCWH_32_BIT_PCI |\ HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ HRCWH_FROM_0XFFF00100 |\ HRCWH_BOOTSEQ_DISABLE |\ @@ -606,30 +528,32 @@ HRCWH_TSEC2M_IN_GMII ) #endif -/* System performance */ +/* + * System performance + */ #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ -#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count */ -/* System IO Config */ +/* + * System IO Config + */ #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) -#define CFG_HID0_INIT 0x000000000 - -#define CFG_HID0_FINAL CFG_HID0_INIT +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE -/* DDR @ 0x00000000 */ +/* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -/* PCI @ 0x80000000 */ +/* PCI */ #ifdef CONFIG_PCI #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) @@ -706,97 +630,72 @@ #endif #ifdef CONFIG_MPC83XX_TSEC2 -#define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif -#if 1 -#define CONFIG_IPADDR 10.82.19.159 -#define CONFIG_SERVERIP 10.82.48.106 -#define CONFIG_GATEWAYIP 10.82.19.254 -#define CONFIG_NETMASK 255.255.252.0 -#define CONFIG_NETDEV eth0 - -#define CONFIG_HOSTNAME mpc8349emitx -#define CONFIG_ROOTPATH /nfsroot0/u/timur/itx-ltib/rootfs -#define CONFIG_BOOTFILE timur/uImage - -#define CONFIG_UBOOTPATH timur/u-boot.bin -#else #define CONFIG_IPADDR 192.168.1.253 #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.252.0 #define CONFIG_NETDEV eth0 +#ifdef CONFIG_MPC8349ITX #define CONFIG_HOSTNAME mpc8349emitx -#define CONFIG_ROOTPATH /nfsroot/rootfs -#define CONFIG_BOOTFILE uImage - -#define CONFIG_UBOOTPATH u-boot.bin +#else +#define CONFIG_HOSTNAME mpc8349emitxgp #endif -#define CONFIG_UBOOTSTART fe700000 -#define CONFIG_UBOOTEND fe77ffff - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_BAUDRATE 115200 +/* Default path and filenames */ +#define CONFIG_ROOTPATH /nfsroot/rootfs +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTDELAY 6 +#ifdef CONFIG_MPC8349ITX +#define CONFIG_FDTFILE mpc8349emitx.dtb #else -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ +#define CONFIG_FDTFILE mpc8349emitxgp.dtb #endif +#define CONFIG_BOOTDELAY 0 + #define XMK_STR(x) #x #define MK_STR(x) XMK_STR(x) #define CONFIG_BOOTARGS \ "root=/dev/nfs rw" \ " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ - " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ + " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ " console=ttyS0," MK_STR(CONFIG_BAUDRATE) #define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ - "tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize; " \ - "cmp.b $loadaddr " MK_STR(CONFIG_UBOOTSTART) " $filesize\0" \ - "tftpupdate=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \ - "protect off FEF00000 FEF7FFFF; " \ - "erase FEF00000 FEF7FFFF; " \ - "cp.b $loadaddr FEF00000 $filesize; " \ - "protect on FEF00000 FEF7FFFF; " \ - "cmp.b $loadaddr FEF00000 $filesize\0" \ - "tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \ - "copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \ - "cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "fdtaddr=400000\0" \ - "fdtfile=mpc8349emitx.dtb\0" \ - "" + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" #define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" + "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ + " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - + "setenv bootargs root=/dev/ram rw" \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #undef MK_STR #undef XMK_STR diff --git a/include/mpc83xx.h b/include/mpc83xx.h index c1c6ad1e71..1b62f81293 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -825,6 +825,47 @@ #define OR_SDRAM_EAD 0x00000001 #define OR_SDRAM_EAD_SHIFT 0 +#define OR_AM_32KB 0xFFFF8000 +#define OR_AM_64KB 0xFFFF0000 +#define OR_AM_128KB 0xFFFE0000 +#define OR_AM_256KB 0xFFFC0000 +#define OR_AM_512KB 0xFFF80000 +#define OR_AM_1MB 0xFFF00000 +#define OR_AM_2MB 0xFFE00000 +#define OR_AM_4MB 0xFFC00000 +#define OR_AM_8MB 0xFF800000 +#define OR_AM_16MB 0xFF000000 +#define OR_AM_32MB 0xFE000000 +#define OR_AM_64MB 0xFC000000 +#define OR_AM_128MB 0xF8000000 +#define OR_AM_256MB 0xF0000000 +#define OR_AM_512MB 0xE0000000 +#define OR_AM_1GB 0xC0000000 +#define OR_AM_2GB 0x80000000 +#define OR_AM_4GB 0x00000000 + +#define LBLAWAR_EN 0x80000000 +#define LBLAWAR_4KB 0x0000000B +#define LBLAWAR_8KB 0x0000000C +#define LBLAWAR_16KB 0x0000000D +#define LBLAWAR_32KB 0x0000000E +#define LBLAWAR_64KB 0x0000000F +#define LBLAWAR_128KB 0x00000010 +#define LBLAWAR_256KB 0x00000011 +#define LBLAWAR_512KB 0x00000012 +#define LBLAWAR_1MB 0x00000013 +#define LBLAWAR_2MB 0x00000014 +#define LBLAWAR_4MB 0x00000015 +#define LBLAWAR_8MB 0x00000016 +#define LBLAWAR_16MB 0x00000017 +#define LBLAWAR_32MB 0x00000018 +#define LBLAWAR_64MB 0x00000019 +#define LBLAWAR_128MB 0x0000001A +#define LBLAWAR_256MB 0x0000001B +#define LBLAWAR_512MB 0x0000001C +#define LBLAWAR_1GB 0x0000001D +#define LBLAWAR_2GB 0x0000001E + /* LBCR - Local Bus Configuration Register */ #define LBCR_LDIS 0x80000000 -- 2.25.1