From 7577cb19fc229ebd2a20e1cb8a94a2b423d4f0cf Mon Sep 17 00:00:00 2001 From: Mario Six Date: Mon, 21 Jan 2019 09:17:41 +0100 Subject: [PATCH] mpc8315erdb: Merge BR/OR settings The mpc8315erdb has the option of either configuring the eLBC (enhanced local system bus) such that * NOR flash is the first memory bank, and NAND flash is the second memory bank, or * NAND flash is the first memory bank, and NOR flash is the second memory bank, by using CONFIG_SYS_NOR_{BR,OR}_PRELIM and CONFIG_SYS_NAND_{BR,OR}_PRELIM for defining CONFIG_SYS_{BR,OR}{0,1}_PRELIM. After Kconfig migration, replacing some lines in the defconfig will have the same effect. Hence, we will not create distinct ve8313_{NOR,NAND} configs for such a small change. Instead, fix the current default (NOR first, NAND second), and unroll the CONFIG_SYS_NAND_{BR,OR}_PRELIM options. This will ease the Kconfig migration. Signed-off-by: Mario Six --- include/configs/MPC8315ERDB.h | 40 +++++++++++++++++------------------ 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index b8506321af..a2b5b07ea9 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -191,20 +191,6 @@ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) -#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ #define CONFIG_SYS_MAX_FLASH_SECT 135 @@ -236,13 +222,26 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ | BR_DECC_CHK_GEN /* Use HW ECC */ \ | BR_PS_8 /* 8 bit port */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM \ - (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ +#define CONFIG_SYS_OR1_PRELIM \ + (OR_AM_32KB \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -251,10 +250,9 @@ | OR_FCM_EHTR) /* 0xFFFF8396 */ -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM +/* Still needed for spl_minimal.c */ +#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM +#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) -- 2.25.1