From 70a0e2e34171994005208e75aaa2277ee1d8ae6c Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Mon, 29 Aug 2016 00:26:03 +0200 Subject: [PATCH] Cleanup board configs - move common defines into separate header file - remove old ar7240.h config - clean up mess --- u-boot/Makefile | 5 +- u-boot/board/ar7240/common/qca-eth-953x.c | 3 + u-boot/common/cmd_custom.c | 4 +- u-boot/httpd/httpd.c | 8 +- u-boot/include/configs/ap121.h | 650 +++++++--------------- u-boot/include/configs/ap143.h | 369 ++++-------- u-boot/include/configs/ar7240.h | 48 -- u-boot/include/configs/db12x.h | 270 +++------ u-boot/include/configs/qca9k_common.h | 139 +++++ u-boot/include/soc/qca_soc_common.h | 11 + u-boot/net/httpd.c | 24 +- 11 files changed, 557 insertions(+), 974 deletions(-) delete mode 100644 u-boot/include/configs/ar7240.h create mode 100644 u-boot/include/configs/qca9k_common.h diff --git a/u-boot/Makefile b/u-boot/Makefile index 67844c0..616bf34 100644 --- a/u-boot/Makefile +++ b/u-boot/Makefile @@ -344,15 +344,14 @@ unconfig: config_common: @ >include/config.h @$(call include_add,soc/soc_list.h) - @$(call define_add,CONFIG_BOOTDELAY,1) - @$(call define_add,CONFIG_SILENT_CONSOLE,1) - @$(call define_add,CFG_CONSOLE_INFO_QUIET,1) @$(call define_add,CONFIG_MAX_BUTTON_PRESSING,10) @$(call define_add,CONFIG_DELAY_TO_AUTORUN_HTTPD,3) @$(call define_add,CONFIG_DELAY_TO_AUTORUN_CONSOLE,5) @$(call define_add,CONFIG_DELAY_TO_AUTORUN_NETCONSOLE,7) ar933x_common: unconfig config_common + @$(call define_add,CFG_AG7240_NMACS,2) + @$(call define_add,CFG_ATHRS26_PHY,1) @$(call define_add,CONFIG_MACH_HORNET,1) ar934x_common: unconfig config_common diff --git a/u-boot/board/ar7240/common/qca-eth-953x.c b/u-boot/board/ar7240/common/qca-eth-953x.c index fd4fcb8..cd52540 100644 --- a/u-boot/board/ar7240/common/qca-eth-953x.c +++ b/u-boot/board/ar7240/common/qca-eth-953x.c @@ -403,6 +403,9 @@ static void ath_gmac_halt(struct eth_device *dev) while (ath_gmac_reg_rd(mac, ATH_DMA_RX_CTRL)); } +/* FIXME! */ +#define BOARDCAL 0x9FFF0000 + unsigned char * ath_gmac_mac_addr_loc(void) { diff --git a/u-boot/common/cmd_custom.c b/u-boot/common/cmd_custom.c index 4e49479..3e50032 100644 --- a/u-boot/common/cmd_custom.c +++ b/u-boot/common/cmd_custom.c @@ -83,7 +83,7 @@ int do_set_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ } // backup block with MAC address from flash in RAM - data_pointer = (unsigned char *)WEBFAILSAFE_UPLOAD_RAM_ADDRESS; + data_pointer = (unsigned char *)CONFIG_LOADADDR; if(!data_pointer){ puts("## Error: couldn't allocate RAM for data block backup!\n"); @@ -104,7 +104,7 @@ int do_set_mac(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]){ "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX", CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK, OFFSET_MAC_DATA_BLOCK_LENGTH, - WEBFAILSAFE_UPLOAD_RAM_ADDRESS, + CONFIG_LOADADDR, CFG_FLASH_BASE + OFFSET_MAC_DATA_BLOCK, OFFSET_MAC_DATA_BLOCK_LENGTH); diff --git a/u-boot/httpd/httpd.c b/u-boot/httpd/httpd.c index 082a646..767cf17 100644 --- a/u-boot/httpd/httpd.c +++ b/u-boot/httpd/httpd.c @@ -193,7 +193,7 @@ static int httpd_findandstore_firstchunk(void){ // has correct size (for every type of upgrade) // U-Boot - if((webfailsafe_upgrade_type == WEBFAILSAFE_UPGRADE_TYPE_UBOOT) && (hs->upload_total > WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES)){ + if((webfailsafe_upgrade_type == WEBFAILSAFE_UPGRADE_TYPE_UBOOT) && (hs->upload_total > (CONFIG_MAX_UBOOT_SIZE_KB * 1024))){ printf("## Error: file too big!\n"); webfailsafe_upload_failed = 1; @@ -455,7 +455,7 @@ void httpd_appcall(void){ * find beginning of the data in first packet */ - webfailsafe_data_pointer = (u8_t *)WEBFAILSAFE_UPLOAD_RAM_ADDRESS; + webfailsafe_data_pointer = (u8_t *)CONFIG_LOADADDR; if(!webfailsafe_data_pointer){ printf("## Error: couldn't allocate RAM for data!\n"); @@ -463,10 +463,10 @@ void httpd_appcall(void){ uip_abort(); return; } else { - printf("Data will be downloaded at 0x%X in RAM\n", WEBFAILSAFE_UPLOAD_RAM_ADDRESS); + printf("Data will be downloaded at 0x%X in RAM\n", CONFIG_LOADADDR); } - memset((void *)webfailsafe_data_pointer, 0xFF, WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES); + memset((void *)webfailsafe_data_pointer, 0xFF, (CONFIG_MAX_UBOOT_SIZE_KB * 1024)); if(httpd_findandstore_firstchunk()){ data_start_found = 1; diff --git a/u-boot/include/configs/ap121.h b/u-boot/include/configs/ap121.h index 0a40da9..ef45c0c 100644 --- a/u-boot/include/configs/ap121.h +++ b/u-boot/include/configs/ap121.h @@ -9,25 +9,60 @@ * SPDX-License-Identifier: GPL-2.0 */ -#ifndef __AP121_CONFIG_H -#define __AP121_CONFIG_H +#ifndef _AP121_H +#define _AP121_H -#include #include +#include #include /* + * ================== * GPIO configuration + * ================== */ -#if defined(CONFIG_FOR_TPLINK_WR703N_V1) ||\ - defined(CONFIG_FOR_TPLINK_WR710N_V1) +#if defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) - #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO27 - #define CONFIG_QCA_GPIO_MASK_OUT GPIO8 |\ - CONFIG_QCA_GPIO_MASK_LED_ACT_L + #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO13 | GPIO14 + #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO0 + #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L |\ + CONFIG_QCA_GPIO_MASK_LED_ACT_H #define CONFIG_QCA_GPIO_MASK_IN GPIO11 - #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\ - CONFIG_QCA_GPIO_MASK_LED_ACT_L + #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L + #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H + +#elif defined(CONFIG_FOR_DLINK_DIR505_A1) + + #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO26 | GPIO27 + #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L + #define CONFIG_QCA_GPIO_MASK_IN GPIO11 + #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L + +#elif defined(CONFIG_FOR_DRAGINO_V2) ||\ + defined(CONFIG_FOR_MESH_POTATO_V2) + + #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO28 + #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13 | GPIO17 + #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L |\ + CONFIG_QCA_GPIO_MASK_LED_ACT_H + #define CONFIG_QCA_GPIO_MASK_IN GPIO11 + #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L + #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H + +#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV) + + #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13 | GPIO15 | GPIO17 |\ + GPIO27 + #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L + #define CONFIG_QCA_GPIO_MASK_IN GPIO11 + #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L + +#elif defined(CONFIG_FOR_GL_INET) + + #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO13 + #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_H + #define CONFIG_QCA_GPIO_MASK_IN GPIO11 + #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H #elif defined(CONFIG_FOR_TPLINK_MR10U_V1) @@ -38,15 +73,6 @@ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO18 |\ CONFIG_QCA_GPIO_MASK_LED_ACT_L -#elif defined(CONFIG_FOR_TPLINK_WR720N_V3) - - #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO27 - #define CONFIG_QCA_GPIO_MASK_OUT GPIO8 |\ - CONFIG_QCA_GPIO_MASK_LED_ACT_L - #define CONFIG_QCA_GPIO_MASK_IN GPIO11 | GPIO18 | GPIO20 - #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\ - CONFIG_QCA_GPIO_MASK_LED_ACT_L - #elif defined(CONFIG_FOR_TPLINK_MR13U_V1) #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO27 @@ -56,20 +82,6 @@ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO18 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H -#elif defined(CONFIG_FOR_DLINK_DIR505_A1) - - #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO26 | GPIO27 - #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L - #define CONFIG_QCA_GPIO_MASK_IN GPIO11 - #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L - -#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) - - #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO27 - #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L - #define CONFIG_QCA_GPIO_MASK_IN GPIO11 - #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L - #elif defined(CONFIG_FOR_TPLINK_MR3020_V1) #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 @@ -92,17 +104,6 @@ CONFIG_QCA_GPIO_MASK_LED_ACT_L #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H -#elif defined(CONFIG_FOR_TPLINK_WR740N_V4) - - #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO1 | GPIO13 |\ - GPIO14 | GPIO15 | GPIO16 - #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO17 | GPIO27 - #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L |\ - CONFIG_QCA_GPIO_MASK_LED_ACT_H - #define CONFIG_QCA_GPIO_MASK_IN GPIO11 | GPIO26 - #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L - #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H - #elif defined(CONFIG_FOR_TPLINK_MR3220_V2) #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO1 | GPIO13 |\ @@ -117,218 +118,130 @@ CONFIG_QCA_GPIO_MASK_LED_ACT_L #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H -#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV) +#elif defined(CONFIG_FOR_TPLINK_WR703N_V1) ||\ + defined(CONFIG_FOR_TPLINK_WR710N_V1) - #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13 | GPIO15 | GPIO17 |\ - GPIO27 - #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L + #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO27 + #define CONFIG_QCA_GPIO_MASK_OUT GPIO8 |\ + CONFIG_QCA_GPIO_MASK_LED_ACT_L #define CONFIG_QCA_GPIO_MASK_IN GPIO11 - #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L + #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\ + CONFIG_QCA_GPIO_MASK_LED_ACT_L -#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) +#elif defined(CONFIG_FOR_TPLINK_WR720N_V3) - #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO13 | GPIO14 - #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO0 - #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L |\ - CONFIG_QCA_GPIO_MASK_LED_ACT_H - #define CONFIG_QCA_GPIO_MASK_IN GPIO11 - #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L - #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H + #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO27 + #define CONFIG_QCA_GPIO_MASK_OUT GPIO8 |\ + CONFIG_QCA_GPIO_MASK_LED_ACT_L + #define CONFIG_QCA_GPIO_MASK_IN GPIO11 | GPIO18 | GPIO20 + #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO8 |\ + CONFIG_QCA_GPIO_MASK_LED_ACT_L -#elif defined(CONFIG_FOR_DRAGINO_V2) ||\ - defined(CONFIG_FOR_MESH_POTATO_V2) +#elif defined(CONFIG_FOR_TPLINK_WR740N_V4) - #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO28 - #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13 | GPIO17 + #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO1 | GPIO13 |\ + GPIO14 | GPIO15 | GPIO16 + #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO17 | GPIO27 #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L |\ CONFIG_QCA_GPIO_MASK_LED_ACT_H - #define CONFIG_QCA_GPIO_MASK_IN GPIO11 + #define CONFIG_QCA_GPIO_MASK_IN GPIO11 | GPIO26 #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H -#elif defined(CONFIG_FOR_GL_INET) +#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) - #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO13 - #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_H + #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO27 + #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L #define CONFIG_QCA_GPIO_MASK_IN GPIO11 - #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H - -#endif - -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash + #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L -/* - * We boot from this flash - */ -#define CFG_FLASH_BASE 0x9F000000 -#ifdef COMPRESSED_UBOOT - #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE - #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE #endif /* - * The following #defines are needed to get flash environment right - */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) - -/* + * ================ * Default bootargs + * ================ */ -#undef CONFIG_BOOTARGS - -#if defined(CONFIG_FOR_TPLINK_WR703N_V1) || \ - defined(CONFIG_FOR_TPLINK_WR720N_V3) || \ - defined(CONFIG_FOR_TPLINK_MR3020_V1) || \ - defined(CONFIG_FOR_TPLINK_MR3040_V1V2) || \ - defined(CONFIG_FOR_TPLINK_MR10U_V1) || \ - defined(CONFIG_FOR_TPLINK_WR740N_V4) || \ - defined(CONFIG_FOR_TPLINK_MR3220_V2) || \ - defined(CONFIG_FOR_TPLINK_MR13U_V1) || \ - defined(CONFIG_FOR_GL_INET) - - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(ART)" +#if defined(CONFIG_FOR_GL_INET) ||\ + defined(CONFIG_FOR_TPLINK_MR10U_V1) ||\ + defined(CONFIG_FOR_TPLINK_MR13U_V1) ||\ + defined(CONFIG_FOR_TPLINK_MR3020_V1) ||\ + defined(CONFIG_FOR_TPLINK_MR3040_V1V2) ||\ + defined(CONFIG_FOR_TPLINK_MR3220_V2) ||\ + defined(CONFIG_FOR_TPLINK_WR703N_V1) ||\ + defined(CONFIG_FOR_TPLINK_WR720N_V3) ||\ + defined(CONFIG_FOR_TPLINK_WR740N_V4) + + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)" #elif defined(CONFIG_FOR_TPLINK_WR710N_V1) - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(ART)" + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(art)" #elif defined(CONFIG_FOR_DLINK_DIR505_A1) - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:06 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:64k(u-boot),64k(ART),64k(mac),64k(nvram),256k(language),1024k(uImage),6656k(rootfs)" + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:06 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=ar7240-nor0:64k(u-boot),64k(ART),64k(mac),64k(nvram),256k(language),1024k(uImage),6656k(rootfs)" #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV) - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(ART)" + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=ar7240-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)" #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:128k(u-boot),64k(u-boot-env),16128k(firmware),64k(ART)" + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=ar7240-nor0:128k(u-boot),64k(u-boot-env),16128k(firmware),64k(art)" #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(ART)" + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),16000k(firmware),64k(art)" -#elif defined(CONFIG_FOR_DRAGINO_V2) || \ +#elif defined(CONFIG_FOR_DRAGINO_V2) ||\ defined(CONFIG_FOR_MESH_POTATO_V2) - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ar7240-nor0:192k(u-boot),64k(u-boot-env),16064k(firmware),64k(ART)" + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=ar7240-nor0:192k(u-boot),64k(u-boot-env),16064k(firmware),64k(art)" #endif /* - * Other env default values + * ============================= + * Load address and boot command + * ============================= */ -#undef CONFIG_BOOTFILE -#define CONFIG_BOOTFILE "firmware.bin" - -#undef CONFIG_LOADADDR -#define CONFIG_LOADADDR 0x80800000 - #if defined(CONFIG_FOR_DLINK_DIR505_A1) - #define CFG_LOAD_ADDR 0x9F080000 - #define UPDATE_SCRIPT_FW_ADDR "0x9F080000" + #define CFG_LOAD_ADDR 0x9F080000 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) - #define CFG_LOAD_ADDR 0x9F050000 - #define UPDATE_SCRIPT_FW_ADDR "0x9F050000" -#elif defined(CONFIG_FOR_DRAGINO_V2) || \ - defined(CONFIG_FOR_MESH_POTATO_V2) - #define CFG_LOAD_ADDR 0x9F040000 - #define UPDATE_SCRIPT_FW_ADDR "0x9F040000" -#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) - #define CFG_LOAD_ADDR 0x9F030000 - #define UPDATE_SCRIPT_FW_ADDR "0x9F030000" -#else - #define CFG_LOAD_ADDR 0x9F020000 - #define UPDATE_SCRIPT_FW_ADDR "0x9F020000" -#endif - -#if defined(CONFIG_FOR_DLINK_DIR505_A1) - #define CONFIG_BOOTCOMMAND "bootm 0x9F080000" -#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) - #define CONFIG_BOOTCOMMAND "bootm 0x9F050000" -#elif defined(CONFIG_FOR_DRAGINO_V2) || \ + #define CFG_LOAD_ADDR 0x9F050000 +#elif defined(CONFIG_FOR_DRAGINO_V2) ||\ defined(CONFIG_FOR_MESH_POTATO_V2) - #define CONFIG_BOOTCOMMAND "bootm 0x9F040000" + #define CFG_LOAD_ADDR 0x9F040000 #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) - #define CONFIG_BOOTCOMMAND "bootm 0x9F030000" + #define CFG_LOAD_ADDR 0x9F030000 #else - #define CONFIG_BOOTCOMMAND "bootm 0x9F020000" + #define CFG_LOAD_ADDR 0x9F020000 #endif -/* - * Dragino 2 uses different IP addresses - */ -#if defined(CONFIG_FOR_DRAGINO_V2) - #define CONFIG_IPADDR 192.168.255.1 - #define CONFIG_SERVERIP 192.168.255.2 -#else - #define CONFIG_IPADDR 192.168.1.1 - #define CONFIG_SERVERIP 192.168.1.2 -#endif +#define CONFIG_BOOTCOMMAND "bootm " MK_STR(CFG_LOAD_ADDR) /* - * Dragino 2 uses different prompt + * ========================= + * Environment configuration + * ========================= */ -#if defined(CONFIG_FOR_DRAGINO_V2) || \ +#if defined(CONFIG_FOR_DRAGINO_V2) ||\ defined(CONFIG_FOR_MESH_POTATO_V2) - #if defined(CFG_PROMPT) - #undef CFG_PROMPT - #endif - #define CFG_PROMPT "dr_boot> " -#endif - -#if defined(CONFIG_FOR_BLACK_SWIFT_BOARD) - #if defined(CFG_PROMPT) - #undef CFG_PROMPT - #endif - #define CFG_PROMPT "BSB> " -#endif - -/* - * PLL/Clocks configuration - */ -#ifdef CFG_HZ - #undef CFG_HZ -#endif -#define CFG_HZ bd->bi_cfg_hz - -#define CONFIG_QCA_PLL QCA_PLL_PRESET_400_400_200 - - -/* - * For PLL/clocks recovery use reset button by default - */ -#ifdef CONFIG_GPIO_RESET_BTN - #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN CONFIG_GPIO_RESET_BTN -#endif - -#ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW - #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW 1 -#endif - -/* - * Cache lock for stack - */ -#define CFG_INIT_SP_OFFSET 0x1000 - -/* - * Address and size of Primary Environment Sector - */ -#if !defined(CONFIG_FOR_DLINK_DIR505_A1) - #define CFG_ENV_IS_IN_FLASH 1 - #undef CFG_ENV_IS_NOWHERE -#else - #undef CFG_ENV_IS_IN_FLASH - #define CFG_ENV_IS_NOWHERE 1 -#endif - -#if defined(CONFIG_FOR_DRAGINO_V2) || \ - defined(CONFIG_FOR_MESH_POTATO_V2) #define CFG_ENV_ADDR 0x9F030000 #define CFG_ENV_SIZE 0x8000 #define CFG_ENV_SECT_SIZE 0x10000 @@ -347,282 +260,151 @@ #endif /* - * Available commands + * =========================== + * List of available baudrates + * =========================== */ -#if defined(CONFIG_FOR_DLINK_DIR505_A1) - - #define CONFIG_CMD_MEMORY - #define CONFIG_CMD_PING - #define CONFIG_CMD_FLASH - #define CONFIG_CMD_NET - #define CONFIG_CMD_RUN - #define CONFIG_CMD_DATE - #define CONFIG_CMD_ECHO - #define CONFIG_CMD_BOOTD - #define CONFIG_CMD_ITEST - #define CONFIG_CMD_IMI +#define CFG_BAUDRATE_TABLE \ + { 600, 1200, 2400, 4800, 9600, 14400, \ + 19200, 28800, 38400, 56000, 57600, 115200, \ + 128000, 153600, 230400, 250000, 256000, 460800, \ + 576000, 921600, 1000000, 1152000, 1500000, 2000000 } +/* + * ================================================== + * MAC address/es, model and WPS pin offsets in FLASH + * ================================================== + */ +#if defined(CONFIG_FOR_DRAGINO_V2) ||\ + defined(CONFIG_FOR_MESH_POTATO_V2) ||\ + defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) + #define OFFSET_MAC_DATA_BLOCK 0xFF0000 + #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 + #define OFFSET_MAC_ADDRESS 0x000000 + #define OFFSET_MAC_ADDRESS2 0x000006 +#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV) + #define OFFSET_MAC_DATA_BLOCK 0x010000 + #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 + #define OFFSET_MAC_ADDRESS 0x00FC00 +#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) + #define OFFSET_MAC_DATA_BLOCK 0xFF0000 + #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 + #define OFFSET_MAC_ADDRESS 0x000000 +#elif defined(CONFIG_FOR_DLINK_DIR505_A1) + /* + * DIR-505 has two MAC addresses inside dedicated MAC partition + * They are stored in plain text... + * TODO: read/write MAC stored as plain text + * #define OFFSET_MAC_DATA_BLOCK 0x02000 + * #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 + * #define OFFSET_MAC_ADDRESS 0x000004 + * #define OFFSET_MAC_ADDRESS2 0x000016 + */ #else - - #define CONFIG_CMD_MEMORY - #define CONFIG_CMD_DHCP - #define CONFIG_CMD_PING - #define CONFIG_CMD_FLASH - #define CONFIG_CMD_NET - #define CONFIG_CMD_RUN - #define CONFIG_CMD_DATE - #define CONFIG_CMD_SNTP - #define CONFIG_CMD_ECHO - #define CONFIG_CMD_BOOTD - #define CONFIG_CMD_ITEST - #define CONFIG_CMD_IMI - #define CONFIG_CMD_ENV - #define CONFIG_CMD_LOADB - #define CONFIG_CMD_BUTTON - #define CONFIG_CMD_SLEEP - + #define OFFSET_MAC_DATA_BLOCK 0x010000 + #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 + #define OFFSET_MAC_ADDRESS 0x00FC00 #endif -// Enable NetConsole and custom NetConsole port -#define CONFIG_NETCONSOLE -#define CONFIG_NETCONSOLE_PORT 6666 - -#define CONFIG_NET_MULTI +#if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) &&\ + !defined(CONFIG_FOR_DLINK_DIR505_A1) &&\ + !defined(CONFIG_FOR_GS_OOLITE_V1_DEV) &&\ + !defined(CONFIG_FOR_DRAGINO_V2) &&\ + !defined(CONFIG_FOR_MESH_POTATO_V2) &&\ + !defined(CONFIG_FOR_GL_INET) &&\ + !defined(CONFIG_FOR_BLACK_SWIFT_BOARD) + #define OFFSET_ROUTER_MODEL 0xFD00 +#endif -/* choose eth1 first for tftpboot interface added by ZJin, 110328 */ -#define CONFIG_AG7240_SPEPHY +#if defined(CONFIG_FOR_TPLINK_MR3020_V1) ||\ + defined(CONFIG_FOR_TPLINK_WR740N_V4) ||\ + defined(CONFIG_FOR_TPLINK_MR3220_V2) ||\ + defined(CONFIG_FOR_TPLINK_WR710N_V1) + #define OFFSET_PIN_NUMBER 0xFE00 +#endif /* - * Web Failsafe configuration + * ========================= + * Custom changes per device + * ========================= */ -#define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR -// U-Boot partition size and offset -#define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE -#define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (CONFIG_MAX_UBOOT_SIZE_KB * 1024) +/* Dragino 2 uses different IP addresses */ +#if defined(CONFIG_FOR_DRAGINO_V2) + #undef CONFIG_IPADDR + #define CONFIG_IPADDR 192.168.255.1 -#if defined(CONFIG_FOR_DLINK_DIR505_A1) - #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x10000" - #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES -#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) - #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x40000" - #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES -#elif defined(CONFIG_FOR_DRAGINO_V2) || \ - defined(CONFIG_FOR_MESH_POTATO_V2) - #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x30000" - #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES -#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) - #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x20000" - #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES -#else - // TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB - #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x1EC00" - #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "0x20000" + #undef CONFIG_SERVERIP + #define CONFIG_SERVERIP 192.168.255.2 #endif -// Firmware partition offset -#if defined(CONFIG_FOR_DLINK_DIR505_A1) - #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x80000 -#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) - #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x50000 -#elif defined(CONFIG_FOR_DRAGINO_V2) || \ - defined(CONFIG_FOR_MESH_POTATO_V2) - #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x40000 +/* Dragino 2 and Black Swift boards use different prompts */ +#if defined(CONFIG_FOR_DRAGINO_V2) ||\ + defined(CONFIG_FOR_MESH_POTATO_V2) + #undef CFG_PROMPT + #define CFG_PROMPT "dr_boot> " #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) - #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x30000 -#else - #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000 + #undef CFG_PROMPT + #define CFG_PROMPT "BSB> " #endif -// ART partition size and offset +/* + * =========================== + * HTTP recovery configuration + * =========================== + */ +#define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_LOAD_ADDR + #if defined(CONFIG_FOR_DLINK_DIR505_A1) - #define WEBFAILSAFE_UPLOAD_ART_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x10000 + #define WEBFAILSAFE_UPLOAD_ART_ADDRESS (CFG_FLASH_BASE + 0x10000) #endif -#define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024) - -// max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES) +/* Firmware size limit */ #if defined(CONFIG_FOR_DLINK_DIR505_A1) - // D-Link DIR-505: 64k(U-Boot),64k(ART),64k(MAC),64k(NVRAM),256k(Language) #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (512 * 1024) #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) - // Carambola 2: 256k(U-Boot),64k(U-Boot env),64k(ART) #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (384 * 1024) -#elif defined(CONFIG_FOR_DRAGINO_V2) || \ +#elif defined(CONFIG_FOR_DRAGINO_V2) ||\ defined(CONFIG_FOR_MESH_POTATO_V2) - // Dragino 2: 192k(U-Boot),64k(U-Boot env),64k(ART) #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (320 * 1024) #elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV) - // GS-Oolite v1: 128k(U-Boot + MAC),64k(ART) #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024) #elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) - // Black Swift board: 128k(U-Boot),64k(U-Boot env),64k(ART) #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (256 * 1024) #else - // TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART) #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024) #endif -// progress state info -#define WEBFAILSAFE_PROGRESS_START 0 -#define WEBFAILSAFE_PROGRESS_TIMEOUT 1 -#define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2 -#define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3 -#define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4 - -// update type -#define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0 -#define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1 -#define WEBFAILSAFE_UPGRADE_TYPE_ART 2 - -/*-----------------------------------------------------------------------*/ /* - * Additional environment variables for simple upgrades + * ======================== + * PLL/Clocks configuration + * ======================== */ -#define CONFIG_EXTRA_ENV_SETTINGS "uboot_addr=0x9F000000\0" \ - "uboot_name=uboot.bin\0" \ - "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \ - "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \ - "uboot_upg=" \ - "if ping $serverip; then " \ - "mw.b $loadaddr 0xFF $uboot_backup_size && " \ - "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \ - "tftp $loadaddr $uboot_name && " \ - "if itest.l $filesize <= $uboot_size; then " \ - "erase $uboot_addr +$uboot_backup_size && " \ - "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \ - "echo OK!; " \ - "else " \ - "echo ERROR! Wrong file size!; " \ - "fi; " \ - "else " \ - "echo ERROR! Server not reachable!; " \ - "fi\0" \ - "firmware_addr=" UPDATE_SCRIPT_FW_ADDR "\0" \ - "firmware_name=firmware.bin\0" \ - "firmware_upg=" \ - "if ping $serverip; then " \ - "tftp $loadaddr $firmware_name && " \ - "erase $firmware_addr +$filesize && " \ - "cp.b $loadaddr $firmware_addr $filesize && " \ - "echo OK!; " \ - "else " \ - "echo ERROR! Server not reachable!; " \ - "fi\0" - -#define CFG_ATHRS26_PHY 1 -#define CFG_AG7240_NMACS 2 -#define CFG_MII0_RMII 1 -#define CFG_BOOTM_LEN (16 << 20) /* 16 MB */ - -#undef DEBUG - -/* MAC address, model and PIN number offsets in FLASH */ -#if defined(CONFIG_FOR_DLINK_DIR505_A1) - // DIR-505 has two MAC addresses inside dedicated MAC partition - // They are stored in plain text... TODO: read/write MAC stored as plain text - //#define OFFSET_MAC_DATA_BLOCK 0x020000 - //#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 - //#define OFFSET_MAC_ADDRESS 0x000004 - //#define OFFSET_MAC_ADDRESS2 0x000016 -#elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) || \ - defined(CONFIG_FOR_DRAGINO_V2) || \ - defined(CONFIG_FOR_MESH_POTATO_V2) - // Carambola 2 and Dragino 2 have two MAC addresses at the beginning of ART partition - #define OFFSET_MAC_DATA_BLOCK 0xFF0000 - #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 - #define OFFSET_MAC_ADDRESS 0x000000 - #define OFFSET_MAC_ADDRESS2 0x000006 -#elif defined(CONFIG_FOR_GS_OOLITE_V1_DEV) - // GS-OOlite has only one MAC, inside second block - // It's some kind of TP-Link clone - #define OFFSET_MAC_DATA_BLOCK 0x010000 - #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 - #define OFFSET_MAC_ADDRESS 0x00FC00 -#elif defined(CONFIG_FOR_BLACK_SWIFT_BOARD) - // Black Swift board has only one MAC address at the beginning of ART partition - #define OFFSET_MAC_DATA_BLOCK 0xFF0000 - #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 - #define OFFSET_MAC_ADDRESS 0x000000 -#else - #define OFFSET_MAC_DATA_BLOCK 0x010000 - #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 - #define OFFSET_MAC_ADDRESS 0x00FC00 -#endif - -#if !defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) && \ - !defined(CONFIG_FOR_DLINK_DIR505_A1) && \ - !defined(CONFIG_FOR_GS_OOLITE_V1_DEV) && \ - !defined(CONFIG_FOR_DRAGINO_V2) && \ - !defined(CONFIG_FOR_MESH_POTATO_V2) && \ - !defined(CONFIG_FOR_GL_INET) && \ - !defined(CONFIG_FOR_BLACK_SWIFT_BOARD) -#define OFFSET_ROUTER_MODEL 0x00FD00 -#endif - -#if defined(CONFIG_FOR_TPLINK_MR3020_V1) || \ - defined(CONFIG_FOR_TPLINK_WR740N_V4) || \ - defined(CONFIG_FOR_TPLINK_MR3220_V2) || \ - defined(CONFIG_FOR_TPLINK_WR710N_V1) - #define OFFSET_PIN_NUMBER 0x00FE00 -#endif +#define CONFIG_QCA_PLL QCA_PLL_PRESET_400_400_200 -/* - * PLL and clocks configurations from FLASH - */ -#if defined(CONFIG_FOR_DLINK_DIR505_A1) || \ +#if defined(CONFIG_FOR_DLINK_DIR505_A1) ||\ defined(CONFIG_FOR_BLACK_SWIFT_BOARD) - /* - * For DIR505 A1: - * We will store PLL and CLOCK registers - * configuration at the end of MAC data - * partition (3rd 64 KiB block) - * ---- - * For Black Swift board: - * We will store PLL and CLOCK registers - * configuration at the end of environment - * sector (64 KB, environment uses only part!) - */ - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00020000 - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000 + + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x20000 + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000 #elif defined(CONFIG_FOR_8DEVICES_CARAMBOLA2) - /* - * We will store PLL and CLOCK registers - * configuration at the end of environment - * sector (64 KB, environment uses only half!) - */ - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00040000 - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000 -#elif defined(CONFIG_FOR_DRAGINO_V2) || \ + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x40000 + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000 + +#elif defined(CONFIG_FOR_DRAGINO_V2) ||\ defined(CONFIG_FOR_MESH_POTATO_V2) - /* - * We will store PLL and CLOCK registers - * configuration at the end of environment - * sector (64 KB, environment uses only half!) - */ - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00030000 - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000 + + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x30000 + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000 #else - /* - * All TP-Link routers have a lot of unused space - * in FLASH, in second 64 KiB block. - * We will store there PLL and CLOCK - * registers configuration. - */ - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00010000 - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000 -#endif + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x10000 + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000 -#if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET) - /* Use last 32 bytes */ - #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET (CFG_FLASH_BASE + \ - CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \ - 0x0000FFE0) #endif -#endif /* __AP121_CONFIG_H */ +#endif /* _AP121_H */ diff --git a/u-boot/include/configs/ap143.h b/u-boot/include/configs/ap143.h index 29bdbbb..411bb71 100644 --- a/u-boot/include/configs/ap143.h +++ b/u-boot/include/configs/ap143.h @@ -9,14 +9,17 @@ * SPDX-License-Identifier: GPL-2.0 */ -#ifndef _AP143_CONFIG_H -#define _AP143_CONFIG_H +#ifndef _AP143_H +#define _AP143_H #include +#include #include /* + * ================== * GPIO configuration + * ================== */ #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\ defined(CONFIG_FOR_TPLINK_WR802N) @@ -55,139 +58,62 @@ #endif /* - * Miscellaneous configurable options + * ================ + * Default bootargs + * ================ */ -#ifndef CONFIG_BOOTDELAY - #define CONFIG_BOOTDELAY 1 -#endif +#if defined(CONFIG_FOR_TPLINK_WR820N_CN) -#define CFG_LONGHELP - -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 600, 1200, 2400, 4800, 9600, 14400, \ - 19200, 28800, 38400, 56000, 57600, 115200 } - -#define CFG_ALT_MEMTEST -#define CFG_HUSH_PARSER -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size, was: def + 16 */ -#define CFG_MAXARGS 16 /* max number of command */ -#define CFG_MALLOC_LEN 512*1024 /* def: 128*1024 */ -#define CFG_BOOTPARAMS_LEN 512*1024 /* def: 128 */ -#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ -#define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x200000) /* RAM test start = CFG_SDRAM_BASE + 2 MB */ -#define CFG_MEMTEST_END (CFG_SDRAM_BASE + bd->bi_memsize - 0x200001) /* RAM test end = CFG_SDRAM_BASE + RAM size - 2 MB - 1 Byte */ -#define CFG_RX_ETH_BUFFER 16 - -#define CFG_DCACHE_SIZE 32768 -#define CFG_ICACHE_SIZE 65536 -#define CFG_CACHELINE_SIZE 32 + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(art)" -/* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash -#define CFG_FLASH_SECTOR_SIZE 64 * 1024 +#elif defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\ + defined(CONFIG_FOR_TPLINK_WR802N) -/* - * We boot from this flash - */ -#define CFG_FLASH_BASE 0x9F000000 -#ifdef COMPRESSED_UBOOT - #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE - #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE -#endif + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)" -/* - * The following #defines are needed to get flash environment right - */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) - -/* - * Default bootargs - */ -#undef CONFIG_BOOTARGS -#if defined(CONFIG_FOR_TPLINK_WR820N_CN) - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)" -#elif defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\ - defined(CONFIG_FOR_TPLINK_WR802N) - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)" #elif defined(CONFIG_FOR_WALLYS_DR531) - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k" -#elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) - #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),14528k(rootfs),1472k(kernel),64k(ART),16000k(firmware)" -#endif -/* - * Other env default values - */ -#undef CONFIG_BOOTFILE -#define CONFIG_BOOTFILE "firmware.bin" - -#undef CONFIG_LOADADDR -#define CONFIG_LOADADDR 0x80800000 + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=jffs2 init=/sbin/init "\ + "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k" -#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\ - defined(CONFIG_FOR_TPLINK_WR802N) ||\ - defined(CONFIG_FOR_TPLINK_WR841N_V9) - #define CFG_LOAD_ADDR 0x9F020000 - #define UPDATE_SCRIPT_FW_ADDR "0x9F020000" - #define CONFIG_BOOTCOMMAND "bootm 0x9F020000" -#elif defined(CONFIG_FOR_WALLYS_DR531) - #define CFG_LOAD_ADDR 0x9F050000 - #define UPDATE_SCRIPT_FW_ADDR "0x9F050000" - #define CONFIG_BOOTCOMMAND "bootm 0x9F050000" #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) - #define CFG_LOAD_ADDR 0x9FE80000 - #define UPDATE_SCRIPT_FW_ADDR "0x9F050000" - #define CONFIG_BOOTCOMMAND "bootm 0x9FE80000" -#endif -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.2 + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),14528k(rootfs),1472k(kernel),64k(art),16000k(firmware)" -/* - * PLL/Clocks configuration - */ -#ifdef CFG_HZ - #undef CFG_HZ -#endif -#define CFG_HZ bd->bi_cfg_hz - -#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\ - defined(CONFIG_FOR_TPLINK_WR802N) ||\ - defined(CONFIG_FOR_TPLINK_WR841N_V9) - #define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200 -#elif defined(CONFIG_FOR_WALLYS_DR531) ||\ - defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) - #define CONFIG_QCA_PLL QCA_PLL_PRESET_650_400_200 #endif /* - * For PLL/clocks recovery use reset button by default + * ============================= + * Load address and boot command + * ============================= */ -#ifdef CONFIG_GPIO_RESET_BTN - #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN CONFIG_GPIO_RESET_BTN +#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\ + defined(CONFIG_FOR_TPLINK_WR802N) ||\ + defined(CONFIG_FOR_TPLINK_WR841N_V9) + #define CFG_LOAD_ADDR 0x9F020000 +#elif defined(CONFIG_FOR_WALLYS_DR531) + #define CFG_LOAD_ADDR 0x9F050000 +#elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) + #define CFG_LOAD_ADDR 0x9FE80000 #endif -#ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW - #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW 1 -#endif +#define CONFIG_BOOTCOMMAND "bootm " MK_STR(CFG_LOAD_ADDR) /* - * Address and size of Primary Environment Sector + * ========================= + * Environment configuration + * ========================= */ -#define CFG_ENV_IS_IN_FLASH 1 -#undef CFG_ENV_IS_NOWHERE - #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\ - defined(CONFIG_FOR_TPLINK_WR802N) ||\ - defined(CONFIG_FOR_TPLINK_WR841N_V9) + defined(CONFIG_FOR_TPLINK_WR802N) ||\ + defined(CONFIG_FOR_TPLINK_WR841N_V9) #define CFG_ENV_ADDR 0x9F01EC00 #define CFG_ENV_SIZE 0x1000 #define CFG_ENV_SECT_SIZE 0x10000 @@ -202,183 +128,98 @@ #endif /* - * Available commands + * =========================== + * List of available baudrates + * =========================== */ -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_NET -#define CONFIG_CMD_RUN -#define CONFIG_CMD_DATE -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_ITEST -#define CONFIG_CMD_IMI -#define CONFIG_CMD_ENV -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_BUTTON -#define CONFIG_CMD_SLEEP - -// Enable NetConsole and custom NetConsole port -#define CONFIG_NETCONSOLE -#define CONFIG_NETCONSOLE_PORT 6666 +#define CFG_BAUDRATE_TABLE \ + { 600, 1200, 2400, 4800, 9600, 14400, \ + 19200, 28800, 38400, 56000, 57600, 115200 } /* - * Web Failsafe configuration + * ================================================== + * MAC address/es, model and WPS pin offsets in FLASH + * ================================================== */ -#define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR -#define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE - -// Firmware partition offset #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\ - defined(CONFIG_FOR_TPLINK_WR802N) ||\ - defined(CONFIG_FOR_TPLINK_WR841N_V9) - #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000 -#elif defined(CONFIG_FOR_WALLYS_DR531) ||\ - defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) - #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x50000 -#endif - -// U-Boot partition size -#define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (CONFIG_MAX_UBOOT_SIZE_KB * 1024) - -// TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB -#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\ - defined(CONFIG_FOR_TPLINK_WR802N) ||\ - defined(CONFIG_FOR_TPLINK_WR841N_V9) - #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x1EC00" - #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "0x20000" + defined(CONFIG_FOR_TPLINK_WR802N) ||\ + defined(CONFIG_FOR_TPLINK_WR841N_V9) + #define OFFSET_MAC_DATA_BLOCK 0x010000 + #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 + #define OFFSET_MAC_ADDRESS 0x00FC00 + #define OFFSET_ROUTER_MODEL 0x00FD00 + #define OFFSET_PIN_NUMBER 0x00FE00 #elif defined(CONFIG_FOR_WALLYS_DR531) - #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x30000" - #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES + #define OFFSET_MAC_DATA_BLOCK 0x030000 + #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 + #define OFFSET_MAC_ADDRESS 0x00F810 #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) - #define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x40000" - #define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES + #define OFFSET_MAC_DATA_BLOCK 0xFF0000 + #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 + #define OFFSET_MAC_ADDRESS 0x000000 #endif -// ART partition size -#define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024) +/* + * =========================== + * HTTP recovery configuration + * =========================== + */ +#if defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) + #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_FLASH_BASE + 0x50000 +#else + #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_LOAD_ADDR +#endif -// max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES) -// TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART) +/* Firmware size limit */ #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\ - defined(CONFIG_FOR_TPLINK_WR802N) ||\ - defined(CONFIG_FOR_TPLINK_WR841N_V9) + defined(CONFIG_FOR_TPLINK_WR802N) ||\ + defined(CONFIG_FOR_TPLINK_WR841N_V9) #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024) #elif defined(CONFIG_FOR_WALLYS_DR531) ||\ - defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) - // Wallys DR531: 192k(U-Boot),64k(U-Boot env),64k(partition-table),64k(ART) - // Zbtlink ZBT-WE1526: 256k(U-Boot),64k(U-Boot env),64k(ART) + defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (384 * 1024) #endif -// progress state info -#define WEBFAILSAFE_PROGRESS_START 0 -#define WEBFAILSAFE_PROGRESS_TIMEOUT 1 -#define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2 -#define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3 -#define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4 - -// update type -#define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0 -#define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1 -#define WEBFAILSAFE_UPGRADE_TYPE_ART 2 - -/*-----------------------------------------------------------------------*/ - /* - * Additional environment variables for simple upgrades - */ -#define CONFIG_EXTRA_ENV_SETTINGS "uboot_addr=0x9F000000\0" \ - "uboot_name=uboot.bin\0" \ - "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \ - "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \ - "uboot_upg=" \ - "if ping $serverip; then " \ - "mw.b $loadaddr 0xFF $uboot_backup_size && " \ - "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \ - "tftp $loadaddr $uboot_name && " \ - "if itest.l $filesize <= $uboot_size; then " \ - "erase $uboot_addr +$uboot_backup_size && " \ - "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \ - "echo OK!; " \ - "else " \ - "echo ERROR! Wrong file size!; " \ - "fi; " \ - "else " \ - "echo ERROR! Server not reachable!; " \ - "fi\0" -/* - * Cache lock for stack + * ======================== + * PLL/Clocks configuration + * ======================== */ -#define CFG_INIT_SP_OFFSET 0x1000 -#define CONFIG_INIT_SRAM_SP_OFFSET 0xbd001800 - -/* use eth1(LAN) as the net interface */ -#define CONFIG_AG7240_SPEPHY -#define CONFIG_NET_MULTI - #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\ - defined(CONFIG_FOR_TPLINK_WR802N) ||\ - defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\ - defined(CONFIG_FOR_WALLYS_DR531) ||\ - defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) - #define BOARDCAL 0x9fff0000 + defined(CONFIG_FOR_TPLINK_WR802N) ||\ + defined(CONFIG_FOR_TPLINK_WR841N_V9) + #define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200 +#elif defined(CONFIG_FOR_WALLYS_DR531) ||\ + defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) + #define CONFIG_QCA_PLL QCA_PLL_PRESET_650_400_200 #endif -#define CFG_MII0_RMII 1 -#define CFG_BOOTM_LEN (16 << 20) /* 16 MB */ - -#undef DEBUG -/* MAC address, model and PIN number offsets in FLASH */ #if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\ - defined(CONFIG_FOR_TPLINK_WR802N) ||\ - defined(CONFIG_FOR_TPLINK_WR841N_V9) - #define OFFSET_MAC_DATA_BLOCK 0x010000 - #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 - #define OFFSET_MAC_ADDRESS 0x00FC00 - #define OFFSET_ROUTER_MODEL 0x00FD00 - #define OFFSET_PIN_NUMBER 0x00FE00 + defined(CONFIG_FOR_TPLINK_WR802N) ||\ + defined(CONFIG_FOR_TPLINK_WR841N_V9) + + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x10000 + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000 + #elif defined(CONFIG_FOR_WALLYS_DR531) - #define OFFSET_MAC_DATA_BLOCK 0x030000 - #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 - #define OFFSET_MAC_ADDRESS 0x00F810 + + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x30000 + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000 + #elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) - #define OFFSET_MAC_DATA_BLOCK 0xFF0000 - #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 - #define OFFSET_MAC_ADDRESS 0x000000 + + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x40000 + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000 + #endif /* - * PLL and clocks configurations from FLASH + * =================== + * Other configuration + * =================== */ -#if defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\ - defined(CONFIG_FOR_TPLINK_WR802N) ||\ - defined(CONFIG_FOR_TPLINK_WR841N_V9) - /* - * All TP-Link routers have a lot of unused space - * in FLASH, in second 64 KiB block. - * We will store there PLL and CLOCK - * registers configuration. - */ - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00010000 - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000 -#elif defined(CONFIG_FOR_WALLYS_DR531) - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00030000 - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000 -#elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526) - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00040000 - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000 -#endif - -#if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET) - /* Use last 32 bytes */ - #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET (CFG_FLASH_BASE + \ - CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \ - 0x0000FFE0) -#endif +/* Cache lock for stack */ +#define CONFIG_INIT_SRAM_SP_OFFSET 0xbd001800 -#endif /* __AP143_CONFIG_H */ +#endif /* _AP143_H */ diff --git a/u-boot/include/configs/ar7240.h b/u-boot/include/configs/ar7240.h deleted file mode 100644 index 6911bc6..0000000 --- a/u-boot/include/configs/ar7240.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file contains the configuration parameters for the dbau1x00 board. - */ - -#ifndef __AR7240_CONFIG_H -#define __AR7240_CONFIG_H - -#ifndef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 1 /* autoboot after x seconds */ -#endif - -#define CONFIG_MENUPROMPT "Hit any key to stop autobooting: %2d " -#define CONFIG_AUTOBOOT_PROMPT "Autobooting in:\t%d s (type 'tpl' to run U-Boot console)\n\n" -#define CONFIG_AUTOBOOT_STOP_STR "tpl" -#undef CONFIG_AUTOBOOT_DELAY_STR -#define DEBUG_BOOTKEYS 0 -#define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE { 600, 1200, 2400, 4800, 9600, 14400, \ - 19200, 28800, 38400, 56000, 57600, 115200, \ - 128000, 153600, 230400, 250000, 256000, 460800, \ - 576000, 921600, 1000000, 1152000, 1500000, 2000000 } - -/* - * Miscellaneous configurable options - */ -#define CFG_ALT_MEMTEST -#define CFG_HUSH_PARSER -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ -#define CFG_PROMPT_HUSH_PS2 "> " -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size, was: def + 16 */ -#define CFG_MAXARGS 16 /* max number of command */ -#define CFG_MALLOC_LEN 512*1024 /* def: 128*1024 */ -#define CFG_BOOTPARAMS_LEN 512*1024 /* def: 128 */ -#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ -#define CFG_MEMTEST_START (CFG_SDRAM_BASE + 0x200000) /* RAM test start = CFG_SDRAM_BASE + 2 MB */ -#define CFG_MEMTEST_END (CFG_SDRAM_BASE + bd->bi_memsize - 0x200001) /* RAM test end = CFG_SDRAM_BASE + RAM size - 2 MB - 1 Byte */ -#define CFG_RX_ETH_BUFFER 16 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 -#define CFG_ICACHE_SIZE 65536 -#define CFG_CACHELINE_SIZE 32 - -#endif /* __AR7240_CONFIG_H */ diff --git a/u-boot/include/configs/db12x.h b/u-boot/include/configs/db12x.h index a0c51c9..f342def 100644 --- a/u-boot/include/configs/db12x.h +++ b/u-boot/include/configs/db12x.h @@ -9,15 +9,17 @@ * SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DB12X_CONFIG_H -#define __DB12X_CONFIG_H +#ifndef _DB12X_H +#define _DB12X_H -#include #include +#include #include /* + * ================== * GPIO configuration + * ================== */ #if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) @@ -71,243 +73,97 @@ #endif /* - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash -/* - * We boot from this flash - */ -#define CFG_FLASH_BASE 0x9F000000 -#ifdef COMPRESSED_UBOOT - #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE - #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE -#endif - -/* - * The following #defines are needed to get flash environment right - */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (192 << 10) - -/* + * ================ * Default bootargs + * ================ */ -#undef CONFIG_BOOTARGS -#if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) || defined (CONFIG_FOR_TPLINK_WDR3500_V1) -#define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)" -#else -#define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)" -#endif - -/* - * Other env default values - */ -#undef CONFIG_BOOTFILE -#define CONFIG_BOOTFILE "firmware.bin" +#if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) ||\ + defined(CONFIG_FOR_TPLINK_WDR3500_V1) -#undef CONFIG_LOADADDR -#define CONFIG_LOADADDR 0x80800000 - -#define CFG_LOAD_ADDR 0x9F020000 -#define UPDATE_SCRIPT_FW_ADDR "0x9F020000" -#define CONFIG_BOOTCOMMAND "bootm 0x9F020000" - - -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.2 - -/* - * PLL/Clocks configuration - */ -#ifdef CFG_HZ - #undef CFG_HZ -#endif -#define CFG_HZ bd->bi_cfg_hz - -/* For now, use some safe clocks for all AR934x */ -#define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200 + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(art)" +#else -/* - * For PLL/clocks recovery use reset button by default - */ -#ifdef CONFIG_GPIO_RESET_BTN - #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN CONFIG_GPIO_RESET_BTN -#endif + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\ + "rootfstype=squashfs init=/sbin/init "\ + "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)" -#ifdef CONFIG_GPIO_RESET_BTN_ACTIVE_LOW - #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW 1 #endif /* - * MIPS32 24K Processor Core Family Software User's Manual - * - * 6.2.9 Count Register (CP0 Register 9, Select 0) - * The Count register acts as a timer, incrementing at a constant - * rate, whether or not an instruction is executed, retired, or - * any forward progress is made through the pipeline. The counter - * increments every other clock, if the DC bit in the Cause register - * is 0. - * - * Since the count is incremented every other tick, divide by 2 - * XXX derive this from CFG_PLL_FREQ + * ============================= + * Load address and boot command + * ============================= */ +#define CFG_LOAD_ADDR 0x9F020000 +#define CONFIG_BOOTCOMMAND "bootm " MK_STR(CFG_LOAD_ADDR) /* - * Cache lock for stack + * ========================= + * Environment configuration + * ========================= */ -#define CFG_INIT_SP_OFFSET 0x1000 -#define CONFIG_INIT_SRAM_SP_OFFSET 0xbd007000 - -/* - * Address and size of Primary Environment Sector - */ -#define CFG_ENV_IS_IN_FLASH 1 -#undef CFG_ENV_IS_NOWHERE - #define CFG_ENV_ADDR 0x9F01EC00 #define CFG_ENV_SIZE 0x1000 #define CFG_ENV_SECT_SIZE 0x10000 /* - * Available commands + * =========================== + * List of available baudrates + * =========================== */ -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_FLASH -#define CONFIG_CMD_NET -#define CONFIG_CMD_RUN -#define CONFIG_CMD_DATE -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_ITEST -#define CONFIG_CMD_IMI -#define CONFIG_CMD_ENV -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_BUTTON -#define CONFIG_CMD_SLEEP - -// Enable NetConsole and custom NetConsole port -#define CONFIG_NETCONSOLE -#define CONFIG_NETCONSOLE_PORT 6666 - -#define CONFIG_NET_MULTI - -#ifdef CFG_ATHRS27_PHY - /* use eth1(LAN) as the net interface */ - #define CONFIG_AG7240_SPEPHY -#endif +#define CFG_BAUDRATE_TABLE \ + { 600, 1200, 2400, 4800, 9600, 14400, \ + 19200, 28800, 38400, 56000, 57600, 115200 } /* - * Web Failsafe configuration + * ================================================== + * MAC address/es, model and WPS pin offsets in FLASH + * ================================================== */ -#define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR -#define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE - -// Firmware partition offset -#define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000 - -// U-Boot partition size -#define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (CONFIG_MAX_UBOOT_SIZE_KB * 1024) - -// TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB -#define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x1EC00" -#define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "0x20000" +#define OFFSET_MAC_DATA_BLOCK 0x010000 +#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 +#define OFFSET_MAC_ADDRESS 0x00FC00 +#define OFFSET_ROUTER_MODEL 0x00FD00 +#define OFFSET_PIN_NUMBER 0x00FE00 -// ART partition size -#define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024) +/* + * =========================== + * HTTP recovery configuration + * =========================== + */ +#define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_LOAD_ADDR -// max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES) -// TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART) +/* Firmware size limit */ #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024) -// progress state info -#define WEBFAILSAFE_PROGRESS_START 0 -#define WEBFAILSAFE_PROGRESS_TIMEOUT 1 -#define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2 -#define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3 -#define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4 - -// update type -#define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0 -#define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1 -#define WEBFAILSAFE_UPGRADE_TYPE_ART 2 - -/*-----------------------------------------------------------------------*/ - /* - * Additional environment variables for simple upgrades + * ======================== + * PLL/Clocks configuration + * ======================== */ -#define CONFIG_EXTRA_ENV_SETTINGS "uboot_addr=0x9F000000\0" \ - "uboot_name=uboot.bin\0" \ - "uboot_size=" UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "\0" \ - "uboot_backup_size=" UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "\0" \ - "uboot_upg=" \ - "if ping $serverip; then " \ - "mw.b $loadaddr 0xFF $uboot_backup_size && " \ - "cp.b $uboot_addr $loadaddr $uboot_backup_size && " \ - "tftp $loadaddr $uboot_name && " \ - "if itest.l $filesize <= $uboot_size; then " \ - "erase $uboot_addr +$uboot_backup_size && " \ - "cp.b $loadaddr $uboot_addr $uboot_backup_size && " \ - "echo OK!; " \ - "else " \ - "echo ERROR! Wrong file size!; " \ - "fi; " \ - "else " \ - "echo ERROR! Server not reachable!; " \ - "fi\0" \ - "firmware_addr=" UPDATE_SCRIPT_FW_ADDR "\0" \ - "firmware_name=firmware.bin\0" \ - "firmware_upg=" \ - "if ping $serverip; then " \ - "tftp $loadaddr $firmware_name && " \ - "erase $firmware_addr +$filesize && " \ - "cp.b $loadaddr $firmware_addr $filesize && " \ - "echo OK!; " \ - "else " \ - "echo ERROR! Server not reachable!; " \ - "fi\0" +#define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200 -#define CFG_MII0_RMII 1 -#define CFG_BOOTM_LEN (16 << 20) /* 16 MB */ +#if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) ||\ + defined(CONFIG_FOR_TPLINK_WDR3500_V1) ||\ + defined(CONFIG_FOR_TPLINK_MR3420_V2) ||\ + defined(CONFIG_FOR_TPLINK_WR841N_V8) ||\ + defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2) -#undef DEBUG + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x10000 + #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000 -/* MAC address, model and PIN number offsets in FLASH */ -#define OFFSET_MAC_DATA_BLOCK 0x010000 -#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000 -#define OFFSET_MAC_ADDRESS 0x00FC00 -#define OFFSET_ROUTER_MODEL 0x00FD00 -#define OFFSET_PIN_NUMBER 0x00FE00 +#endif /* - * PLL and clocks configurations from FLASH + * =================== + * Other configuration + * =================== */ -#if defined(CONFIG_FOR_TPLINK_WDR3600_WDR43X0_V1) || \ - defined(CONFIG_FOR_TPLINK_WDR3500_V1) || \ - defined(CONFIG_FOR_TPLINK_MR3420_V2) || \ - defined(CONFIG_FOR_TPLINK_WR841N_V8) || \ - defined(CONFIG_FOR_TPLINK_WA830RE_V2_WA801ND_V2) - /* - * All TP-Link routers have a lot of unused space - * in FLASH, in second 64 KiB block. - * We will store there PLL and CLOCK - * registers configuration. - */ - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x00010000 - #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x00010000 - -#endif -#if defined(CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET) - /* Use last 32 bytes */ - #define CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET (CFG_FLASH_BASE + \ - CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET + \ - 0x0000FFE0) -#endif +/* Cache lock for stack */ +#define CONFIG_INIT_SRAM_SP_OFFSET 0xbd007000 -#endif /* __DB12X_CONFIG_H */ +#endif /* _DB12X_H */ diff --git a/u-boot/include/configs/qca9k_common.h b/u-boot/include/configs/qca9k_common.h new file mode 100644 index 0000000..986c52a --- /dev/null +++ b/u-boot/include/configs/qca9k_common.h @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2016 Piotr Dymacz + * + * This file contains some of the common configs/defines + * for boards based on Qualcomm/Atheros QCA9xxx WiSoCs + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __QCA9K_COMMON_H +#define __QCA9K_COMMON_H + +/* No debug */ +#if defined(DEBUG) + #undef DEBUG +#endif + +/* Wait only 1 second by default */ +#if !defined(CONFIG_BOOTDELAY) + #define CONFIG_BOOTDELAY 1 +#endif + +#if !defined(CONFIG_MENUPROMPT) + #define CONFIG_MENUPROMPT "Hit any key to stop booting: %2d " +#endif + +/* Allow to disable console output, don't display console info */ +#define CONFIG_SILENT_CONSOLE 1 +#define CFG_CONSOLE_INFO_QUIET 1 + +/* Use 115200 as default baudrate */ +#if !defined(CONFIG_BAUDRATE) + #define CONFIG_BAUDRATE 115200 +#endif + +/* CLI parser, prompt */ +#define CFG_HUSH_PARSER 1 +#define CFG_LONGHELP 1 +#define CFG_PROMPT "u-boot> " +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_CBSIZE 1024 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 +#define CFG_MALLOC_LEN (512 * 1024) +#define CFG_BOOTPARAMS_LEN (512 * 1024) + +/* RAM memory start address */ +#define CFG_SDRAM_BASE 0x80000000 + +/* Ethernet related */ +#define CONFIG_NET_MULTI 1 +#define CFG_MII0_RMII 1 +#define CFG_RX_ETH_BUFFER 16 + +/* Memory test */ +#define CFG_ALT_MEMTEST 1 +#define CFG_MEMTEST_START (CFG_SDRAM_BASE + (2 * 1024 * 1024)) +#define CFG_MEMTEST_END (CFG_SDRAM_BASE + bd->bi_memsize \ + - (4 * 1024 * 1024) - 1) + +/* FLASH */ +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 4096 +#define CFG_FLASH_BASE 0x9F000000 + +#if defined(COMPRESSED_UBOOT) + #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE + #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE +#endif + +/* Boot related */ +#define CFG_BOOTM_LEN (16 << 20) + +/* The following #defines are needed to get flash environment right */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) + +/* Default device and server IPs, net console */ +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.2 +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NETCONSOLE_PORT 6666 + +/* Other environment variables */ +#define CONFIG_BOOTFILE "firmware.bin" +#define CONFIG_LOADADDR 0x80800000 + +/* This is needed for time calculation */ +#define CFG_HZ (bd->bi_cfg_hz) + +/* Cache */ +#define CFG_INIT_SP_OFFSET 0x1000 +#define CFG_CACHELINE_SIZE 32 +#define CFG_DCACHE_SIZE (32 * 1024) +#define CFG_ICACHE_SIZE (64 * 1024) + +/* Environment related */ +#define CFG_ENV_IS_IN_FLASH 1 +#undef CFG_ENV_IS_NOWHERE + +/* Available commands */ +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_NET +#define CONFIG_CMD_RUN +#define CONFIG_CMD_DATE +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_ITEST +#define CONFIG_CMD_IMI +#define CONFIG_CMD_ENV +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_BUTTON +#define CONFIG_CMD_SLEEP + +/* For HTTP based recovery */ +/* TODO: move it to httpd related header */ +#define WEBFAILSAFE_PROGRESS_START 0 +#define WEBFAILSAFE_PROGRESS_TIMEOUT 1 +#define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2 +#define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3 +#define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4 + +#define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0 +#define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1 +#define WEBFAILSAFE_UPGRADE_TYPE_ART 2 + +#define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024) + +/* Some helper macros */ +/* TODO: move them out from here */ +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#endif /* __QCA9K_COMMON_H */ diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h index fe40c4b..a6e8d4e 100644 --- a/u-boot/include/soc/qca_soc_common.h +++ b/u-boot/include/soc/qca_soc_common.h @@ -1946,6 +1946,17 @@ 0x0000FFE0) #endif +/* + * For PLL/clocks recovery use reset button by default + */ +#if defined(CONFIG_GPIO_RESET_BTN) + #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN CONFIG_GPIO_RESET_BTN +#endif + +#if defined(CONFIG_GPIO_RESET_BTN_ACTIVE_LOW) + #define CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW 1 +#endif + /* * Functions */ diff --git a/u-boot/net/httpd.c b/u-boot/net/httpd.c index c4b7e4f..ca174ca 100644 --- a/u-boot/net/httpd.c +++ b/u-boot/net/httpd.c @@ -58,13 +58,13 @@ int do_http_upgrade(const ulong size, const int upgrade_type){ if(size % info->sector_size != 0){ printf("Backup: copying %d bytes of data from FLASH at address 0x%X to RAM at address 0x%X...\n", backup_size - size, - WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + size, - WEBFAILSAFE_UPLOAD_RAM_ADDRESS + size); + CFG_FLASH_BASE + size, + CONFIG_LOADADDR + size); sprintf(buf, "cp.b 0x%lX 0x%lX 0x%lX", - WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + size, - WEBFAILSAFE_UPLOAD_RAM_ADDRESS + size, + CFG_FLASH_BASE + size, + CONFIG_LOADADDR + size, backup_size - size); if(!run_command(buf, 0)){ @@ -76,10 +76,10 @@ int do_http_upgrade(const ulong size, const int upgrade_type){ printf("\n\n****************************\n* U-BOOT UPGRADING *\n* DO NOT POWER OFF DEVICE! *\n****************************\n\n"); sprintf(buf, "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX", - WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS, + CFG_FLASH_BASE, backup_size, - WEBFAILSAFE_UPLOAD_RAM_ADDRESS, - WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS, + CONFIG_LOADADDR, + CFG_FLASH_BASE, backup_size); } else if(upgrade_type == WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE){ @@ -89,7 +89,7 @@ int do_http_upgrade(const ulong size, const int upgrade_type){ "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX", WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS, size, - WEBFAILSAFE_UPLOAD_RAM_ADDRESS, + CONFIG_LOADADDR, WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS, size); @@ -103,16 +103,16 @@ int do_http_upgrade(const ulong size, const int upgrade_type){ "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX", WEBFAILSAFE_UPLOAD_ART_ADDRESS, WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES, - WEBFAILSAFE_UPLOAD_RAM_ADDRESS, + CONFIG_LOADADDR, WEBFAILSAFE_UPLOAD_ART_ADDRESS, WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES); #else sprintf(buf, "erase 0x%lX +0x%lX; cp.b 0x%lX 0x%lX 0x%lX", - WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + (info->size - WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES), + CFG_FLASH_BASE + (info->size - WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES), WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES, - WEBFAILSAFE_UPLOAD_RAM_ADDRESS, - WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + (info->size - WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES), + CONFIG_LOADADDR, + CFG_FLASH_BASE + (info->size - WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES), WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES); #endif -- 2.25.1