From 6a2ccd64c3adc87687fe0f232e8775274ac1ae21 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 1 Jan 2018 22:51:45 -0200 Subject: [PATCH] mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULL i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to access it. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan Reviewed-by: Stefano Babic --- arch/arm/mach-imx/mx6/ddr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index 52a9a25904..39dbd2f607 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -908,7 +908,7 @@ void mx6sdl_dram_iocfg(unsigned width, #define MR(val, ba, cmd, cs1) \ ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba) #define MMDC1(entry, value) do { \ - if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) \ + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \ mmdc1->entry = value; \ } while (0) @@ -1215,7 +1215,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, u16 mem_speed = ddr3_cfg->mem_speed; mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; - if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR; /* Limit mem_speed for MX6D/MX6Q */ -- 2.25.1