From 5f2c16dab20281f427c1138f33cefeb2e9785b7e Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 18 Jul 2019 00:34:03 -0700 Subject: [PATCH] doc: arch: Convert README.mips to reST Convert plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng Reviewed-by: Heinrich Schuchardt --- doc/arch/index.rst | 2 ++ doc/{README.mips => arch/mips.rst} | 28 ++++++++++------------------ 2 files changed, 12 insertions(+), 18 deletions(-) rename doc/{README.mips => arch/mips.rst} (74%) diff --git a/doc/arch/index.rst b/doc/arch/index.rst index a03ee6b752..1aeb7a1327 100644 --- a/doc/arch/index.rst +++ b/doc/arch/index.rst @@ -5,3 +5,5 @@ Architecture-specific doc .. toctree:: :maxdepth: 2 + + mips diff --git a/doc/README.mips b/doc/arch/mips.rst similarity index 74% rename from doc/README.mips rename to doc/arch/mips.rst index b28f6285cc..b8166087dd 100644 --- a/doc/README.mips +++ b/doc/arch/mips.rst @@ -1,17 +1,16 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +MIPS +==== Notes for the MIPS architecture port of U-Boot Toolchains ---------- - http://www.denx.de/wiki/DULG/ELDK - ELDK < DULG < DENX - - http://www.emdebian.org/crosstools.html - Embedded Debian -- Cross-development toolchains - - http://buildroot.uclibc.org/ - Buildroot + * `ELDK < DULG < DENX `_ + * `Embedded Debian -- Cross-development toolchains `_ + * `Buildroot `_ Known Issues ------------ @@ -24,9 +23,9 @@ Known Issues re-initializes the cache. The more common uImage 'bootm' command does not suffer this problem. - [workaround] To avoid this cache incoherency, - 1) insert flush_cache(all) before calling dcache_disable(), or - 2) fix dcache_disable() to do both flushing and disabling cache. + [workaround] To avoid this cache incoherency: + - insert flush_cache(all) before calling dcache_disable(), or + - fix dcache_disable() to do both flushing and disabling cache. * Note that Linux users need to kill dcache_disable() in do_bootelf_exec() or override do_bootelf_exec() not to disable I-/D-caches, because most @@ -36,19 +35,12 @@ TODOs ----- * Probe CPU types, I-/D-cache and TLB size etc. automatically - * Secondary cache support missing - * Initialize TLB entries redardless of their use - * R2000/R3000 class parts are not supported - * Limited testing across different MIPS variants - * Due to cache initialization issues, the DRAM on board must be initialized in board specific assembler language before the cache init code is run -- that is, initialize the DRAM in lowlevel_init(). - * centralize/share more CPU code of MIPS32, MIPS64 and XBurst - * support Qemu Malta -- 2.25.1