From 52e727c8eb449db8b8dcb38201cbe034c8fa3c04 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sun, 30 Apr 2017 21:57:07 +0200 Subject: [PATCH] net: pch_gbe: CPU accessible addresses are virtual Use the virt_to_bus & bus_to_virt functions rather than phys_to_bus & bus_to_phys, since the addresses accessed by the CPU will be virtual rather than physical. On MIPS physical & virtual addresses differ as we use virtual addresses in kseg0, and attempting to use physical addresses directly caused problems as they're in the user segment which would be mapped via the uninitialised TLB. Signed-off-by: Paul Burton Signed-off-by: Daniel Schwierzeck Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Simon Glass Acked-by: Joe Hershberger --- drivers/net/pch_gbe.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index 7d15616356..14323512b0 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -117,15 +117,15 @@ static void pch_gbe_rx_descs_init(struct udevice *dev) memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM); for (i = 0; i < PCH_GBE_DESC_NUM; i++) - rx_desc[i].buffer_addr = dm_pci_phys_to_mem(priv->dev, + rx_desc[i].buffer_addr = dm_pci_virt_to_mem(priv->dev, priv->rx_buff[i]); - writel(dm_pci_phys_to_mem(priv->dev, (ulong)rx_desc), + writel(dm_pci_virt_to_mem(priv->dev, rx_desc), &mac_regs->rx_dsc_base); writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1), &mac_regs->rx_dsc_size); - writel(dm_pci_phys_to_mem(priv->dev, (ulong)(rx_desc + 1)), + writel(dm_pci_virt_to_mem(priv->dev, rx_desc + 1), &mac_regs->rx_dsc_sw_p); } @@ -137,11 +137,11 @@ static void pch_gbe_tx_descs_init(struct udevice *dev) memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM); - writel(dm_pci_phys_to_mem(priv->dev, (ulong)tx_desc), + writel(dm_pci_virt_to_mem(priv->dev, tx_desc), &mac_regs->tx_dsc_base); writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1), &mac_regs->tx_dsc_size); - writel(dm_pci_phys_to_mem(priv->dev, (ulong)(tx_desc + 1)), + writel(dm_pci_virt_to_mem(priv->dev, tx_desc + 1), &mac_regs->tx_dsc_sw_p); } @@ -251,7 +251,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length) if (length < 64) frame_ctrl |= PCH_GBE_TXD_CTRL_APAD; - tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (ulong)packet); + tx_desc->buffer_addr = dm_pci_virt_to_mem(priv->dev, packet); tx_desc->length = length; tx_desc->tx_words_eob = length + 3; tx_desc->tx_frame_ctrl = frame_ctrl; @@ -262,7 +262,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length) if (++priv->tx_idx >= PCH_GBE_DESC_NUM) priv->tx_idx = 0; - writel(dm_pci_phys_to_mem(priv->dev, (ulong)(tx_head + priv->tx_idx)), + writel(dm_pci_virt_to_mem(priv->dev, tx_head + priv->tx_idx), &mac_regs->tx_dsc_sw_p); start = get_timer(0); @@ -283,7 +283,8 @@ static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp) struct pch_gbe_priv *priv = dev_get_priv(dev); struct pch_gbe_regs *mac_regs = priv->mac_regs; struct pch_gbe_rx_desc *rx_desc; - ulong hw_desc, buffer_addr, length; + ulong hw_desc, length; + void *buffer; rx_desc = &priv->rx_desc[priv->rx_idx]; @@ -291,12 +292,12 @@ static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp) hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld); /* Just return if not receiving any packet */ - if ((ulong)rx_desc == hw_desc) + if (virt_to_phys(rx_desc) == hw_desc) return -EAGAIN; - buffer_addr = dm_pci_mem_to_phys(priv->dev, rx_desc->buffer_addr); - *packetp = (uchar *)buffer_addr; length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN; + buffer = dm_pci_mem_to_virt(priv->dev, rx_desc->buffer_addr, length, 0); + *packetp = (uchar *)buffer; return length; } @@ -315,7 +316,7 @@ static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length) if (++rx_swp >= PCH_GBE_DESC_NUM) rx_swp = 0; - writel(dm_pci_phys_to_mem(priv->dev, (ulong)(rx_head + rx_swp)), + writel(dm_pci_virt_to_mem(priv->dev, rx_head + rx_swp), &mac_regs->rx_dsc_sw_p); return 0; -- 2.25.1