From 4f9a2157a5c0489946d5163f7baa87466998f6f7 Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Sun, 12 Jun 2016 16:17:12 +0200 Subject: [PATCH] Rework PLL/clock related registers/bit fields in common QCA header --- u-boot/include/soc/qca_soc_common.h | 443 +++++++++++++++++++--------- 1 file changed, 309 insertions(+), 134 deletions(-) diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h index c3164c2..ea98815 100644 --- a/u-boot/include/soc/qca_soc_common.h +++ b/u-boot/include/soc/qca_soc_common.h @@ -924,62 +924,83 @@ /* * PLL control registers */ -#define QCA_PLL_CPU_PLL_CFG_REG QCA_PLL_BASE_REG + 0x00 +#define QCA_PLL_CPU_PLL_CFG_REG QCA_PLL_BASE_REG + 0x00 #if (SOC_TYPE & QCA_AR933X_SOC) - #define QCA_PLL_CPU_PLL_CFG2_REG QCA_PLL_BASE_REG + 0x04 - #define QCA_PLL_CPU_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08 - #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG QCA_PLL_BASE_REG + 0x10 - #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x14 - #define QCA_PLL_ETHSW_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24 - #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C - #define QCA_PLL_USB_SUSPEND_REG QCA_PLL_BASE_REG + 0x40 - #define QCA_PLL_WLAN_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x44 + #define QCA_PLL_CPU_PLL_CFG2_REG QCA_PLL_BASE_REG + 0x04 + #define QCA_PLL_CPU_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08 + #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG QCA_PLL_BASE_REG + 0x10 + #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x14 + #define QCA_PLL_ETHSW_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24 + #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C + #define QCA_PLL_USB_SUSPEND_REG QCA_PLL_BASE_REG + 0x40 + #define QCA_PLL_WLAN_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x44 #else - #define QCA_PLL_DDR_PLL_CFG_REG QCA_PLL_BASE_REG + 0x04 - #define QCA_PLL_CPU_DDR_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08 - - #if (SOC_TYPE & QCA_QCA955X_SOC) - #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x0C - #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x10 - #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x14 - #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x18 - #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x1C - #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x20 - #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x24 - #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x28 - #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x2C - #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x30 - #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x34 - #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x38 - #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x40 - #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44 - #define QCA_PLL_ETH_SGMII_CTRL_REG QCA_PLL_BASE_REG + 0x48 - #define QCA_PLL_ETH_SGMII_SERDES_REG QCA_PLL_BASE_REG + 0x4C - #define QCA_PLL_SLIC_PWM_DIV_REG QCA_PLL_BASE_REG + 0x50 - #else - #define QCA_PLL_CPU_SYNC_REG QCA_PLL_BASE_REG + 0x0C - #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x10 - #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x14 - #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x18 - #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x1C - #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x20 - #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24 - - #if (SOC_TYPE & QCA_AR9344_SOC) - #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28 + #if (SOC_TYPE & QCA_QCA956X_SOC) + #define QCA_PLL_CPU_PLL_CFG1_REG QCA_PLL_BASE_REG + 0x04 + #define QCA_PLL_DDR_PLL_CFG_REG QCA_PLL_BASE_REG + 0x08 + #define QCA_PLL_DDR_PLL_CFG1_REG QCA_PLL_BASE_REG + 0x0C + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x10 + #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x14 + #define QCA_PLL_PCIE_PLL_DITHER_MAX_REG QCA_PLL_BASE_REG + 0x18 + #define QCA_PLL_PCIE_PLL_DITHER_MIN_REG QCA_PLL_BASE_REG + 0x1C + #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x20 + #define QCA_PLL_LDO_PWR_CTRL_REG QCA_PLL_BASE_REG + 0x24 + #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x28 + #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x2C + #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x30 + #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x34 + #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x38 + #define QCA_PLL_DDR_PLL_DITHER2_REG QCA_PLL_BASE_REG + 0x3C + #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x40 + #define QCA_PLL_CPU_PLL_DITHER2_REG QCA_PLL_BASE_REG + 0x44 + #define QCA_PLL_ETH_SGMII_CTRL_REG QCA_PLL_BASE_REG + 0x48 + #define QCA_PLL_ETH_SGMII_SERDES_REG QCA_PLL_BASE_REG + 0x4C #else - #define QCA_PLL_CURR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28 - #endif - - #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C - #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x30 - #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x34 - #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x38 - #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x3C - #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x40 - #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44 - #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x48 + #define QCA_PLL_DDR_PLL_CFG_REG QCA_PLL_BASE_REG + 0x04 + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08 + + #if (SOC_TYPE & QCA_QCA955X_SOC) + #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x0C + #define QCA_PLL_PCIE_PLL_DITHER_MAX_REG QCA_PLL_BASE_REG + 0x10 + #define QCA_PLL_PCIE_PLL_DITHER_MIN_REG QCA_PLL_BASE_REG + 0x14 + #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x18 + #define QCA_PLL_LDO_PWR_CTRL_REG QCA_PLL_BASE_REG + 0x1C + #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x20 + #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x24 + #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x28 + #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x2C + #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x30 + #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x34 + #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x38 + #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x3C + #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x40 + #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44 + #define QCA_PLL_ETH_SGMII_CTRL_REG QCA_PLL_BASE_REG + 0x48 + #define QCA_PLL_ETH_SGMII_SERDES_REG QCA_PLL_BASE_REG + 0x4C + #define QCA_PLL_SLIC_PWM_DIV_REG QCA_PLL_BASE_REG + 0x50 + #else + #define QCA_PLL_CPU_SYNC_REG QCA_PLL_BASE_REG + 0x0C + #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x10 + #define QCA_PLL_PCIE_PLL_DITHER_MAX_REG QCA_PLL_BASE_REG + 0x14 + #define QCA_PLL_PCIE_PLL_DITHER_MIN_REG QCA_PLL_BASE_REG + 0x18 + #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x1C + #define QCA_PLL_LDO_PWR_CTRL_REG QCA_PLL_BASE_REG + 0x20 + #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24 + #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28 + #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C + + #if (SOC_TYPE & QCA_AR934X_SOC) + #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x30 + #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x34 + #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x38 + #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x3C + #endif + + #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x40 + #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44 + #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x48 + #endif #endif #endif @@ -1000,10 +1021,15 @@ #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 23 #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3) #else - #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0 - #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 6) - #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 6 - #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6) + #if (SOC_TYPE & QCA_AR934X_SOC) |\ + (SOC_TYPE & QCA_QCA953X_SOC) |\ + (SOC_TYPE & QCA_QCA955X_SOC) + #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0 + #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 6) + #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 6 + #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6) + #endif + #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 12 #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5) #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 17 @@ -1017,6 +1043,14 @@ #define QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT 31 #define QCA_PLL_CPU_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT) +/* CPU_PLL_CONFIG1 register (QCA956x only) */ +#define QCA_PLL_CPU_PLL_CFG1_NFRAC_L_SHIFT 0 +#define QCA_PLL_CPU_PLL_CFG1_NFRAC_L_MASK BITS(QCA_PLL_CPU_PLL_CFG1_NFRAC_L_SHIFT, 5) +#define QCA_PLL_CPU_PLL_CFG1_NFRAC_H_SHIFT 5 +#define QCA_PLL_CPU_PLL_CFG1_NFRAC_H_MASK BITS(QCA_PLL_CPU_PLL_CFG1_NFRAC_H_SHIFT, 13) +#define QCA_PLL_CPU_PLL_CFG1_NINT_SHIFT 18 +#define QCA_PLL_CPU_PLL_CFG1_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG1_NINT_SHIFT, 9) + /* CPU_PLL_CONFIG2 register (CPU phase lock loop configuration, AR933x only) */ #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT 0 #define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_MASK BITS(QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT, 12) @@ -1084,10 +1118,15 @@ #define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_MASK BIT(QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT) /* DDR_PLL_CONFIG register (DDR PLL configuration) */ -#define QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT 0 -#define QCA_PLL_DDR_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT, 10) -#define QCA_PLL_DDR_PLL_CFG_NINT_SHIFT 10 -#define QCA_PLL_DDR_PLL_CFG_NINT_MASK BITS(QCA_PLL_DDR_PLL_CFG_NINT_SHIFT, 6) +#if (SOC_TYPE & QCA_AR934X_SOC) |\ + (SOC_TYPE & QCA_QCA953X_SOC) |\ + (SOC_TYPE & QCA_QCA955X_SOC) + #define QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT 0 + #define QCA_PLL_DDR_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT, 10) + #define QCA_PLL_DDR_PLL_CFG_NINT_SHIFT 10 + #define QCA_PLL_DDR_PLL_CFG_NINT_MASK BITS(QCA_PLL_DDR_PLL_CFG_NINT_SHIFT, 6) +#endif + #define QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT 16 #define QCA_PLL_DDR_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT, 5) #define QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT 21 @@ -1099,6 +1138,14 @@ #define QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT 31 #define QCA_PLL_DDR_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT) +/* DDR_PLL_CONFIG1 register (QCA956x only) */ +#define QCA_PLL_DDR_PLL_CFG1_NFRAC_L_SHIFT 0 +#define QCA_PLL_DDR_PLL_CFG1_NFRAC_L_MASK BITS(QCA_PLL_DDR_PLL_CFG1_NFRAC_L_SHIFT, 5) +#define QCA_PLL_DDR_PLL_CFG1_NFRAC_H_SHIFT 5 +#define QCA_PLL_DDR_PLL_CFG1_NFRAC_H_MASK BITS(QCA_PLL_DDR_PLL_CFG1_NFRAC_H_SHIFT, 13) +#define QCA_PLL_DDR_PLL_CFG1_NINT_SHIFT 18 +#define QCA_PLL_DDR_PLL_CFG1_NINT_MASK BITS(QCA_PLL_DDR_PLL_CFG1_NINT_SHIFT, 9) + /* CPU_DDR_CLOCK_CONTROL register (CPU DDR clock control) */ #define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT 1 #define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT) @@ -1114,10 +1161,20 @@ #define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT, 5) #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT, 5) -#define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT 20 -#define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT) -#define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT 21 -#define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT) + +#if (SOC_TYPE & QCA_QCA955X_SOC) |\ + (SOC_TYPE & QCA_QCA956X_SOC) + #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_DDRPLL_SHIFT 20 + #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_DDRPLL_SHIFT) + #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_CPUPLL_SHIFT 21 + #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_CPUPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_CPUPLL_SHIFT) +#else + #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT 20 + #define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT) + #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT 21 + #define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT) +#endif + #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT 22 #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT) #define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT 23 @@ -1125,47 +1182,105 @@ #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT 24 #define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK BIT(QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT) -/* SWITCH_CLOCK_CONTROL */ -#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT 0 -#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT) -#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT 1 -#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT) -#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT 2 -#define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT) -#define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT 3 -#define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT) -#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT 4 -#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT) -#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT 5 -#define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT) +/* PCIE_PLL_CONFIG register (PCIE RC phase lock loop configuration) */ +#define QCA_PLL_PCIE_PLL_CFG_REFDIV_SHIFT 10 +#define QCA_PLL_PCIE_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_PCIE_PLL_CFG_REFDIV_SHIFT, 5) +#define QCA_PLL_PCIE_PLL_CFG_BYPASS_SHIFT 16 +#define QCA_PLL_PCIE_PLL_CFG_BYPASS_MASK BIT(QCA_PLL_PCIE_PLL_CFG_BYPASS_SHIFT) +#define QCA_PLL_PCIE_PLL_CFG_PLLPWD_SHIFT 30 +#define QCA_PLL_PCIE_PLL_CFG_PLLPWD_MASK BIT(QCA_PLL_PCIE_PLL_CFG_PLLPWD_SHIFT) +#define QCA_PLL_PCIE_PLL_CFG_UPDATING_SHIFT 31 +#define QCA_PLL_PCIE_PLL_CFG_UPDATING_MASK BIT(QCA_PLL_PCIE_PLL_CFG_UPDATING_SHIFT) + +/* PCIE_PLL_DITHER_DIV_MAX (PCIE PLL dither parameter) */ +#define QCA_PLL_PCIE_PLL_DITHER_MAX_NFRAC_MAX_SHIFT 1 +#define QCA_PLL_PCIE_PLL_DITHER_MAX_NFRAC_MAX_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_MAX_NFRAC_MAX_SHIFT, 14) +#define QCA_PLL_PCIE_PLL_DITHER_MAX_NINT_MAX_SHIFT 15 +#define QCA_PLL_PCIE_PLL_DITHER_MAX_NINT_MAX_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_MAX_NINT_MAX_SHIFT, 6) +#define QCA_PLL_PCIE_PLL_DITHER_MAX_USE_MAX_SHIFT 30 +#define QCA_PLL_PCIE_PLL_DITHER_MAX_USE_MAX_MASK BIT(QCA_PLL_PCIE_PLL_DITHER_MAX_USE_MAX_SHIFT) +#define QCA_PLL_PCIE_PLL_DITHER_MAX_DITHER_EN_SHIFT 31 +#define QCA_PLL_PCIE_PLL_DITHER_MAX_DITHER_EN_MASK BIT(QCA_PLL_PCIE_PLL_DITHER_MAX_DITHER_EN_SHIFT) + +/* PCIE_PLL_DITHER_DIV_MIN (PCIE PLL dither parameter) */ +#define QCA_PLL_PCIE_PLL_DITHER_MIN_NFRAC_MIN_SHIFT 1 +#define QCA_PLL_PCIE_PLL_DITHER_MIN_NFRAC_MIN_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_MIN_NFRAC_MIN_SHIFT, 14) +#define QCA_PLL_PCIE_PLL_DITHER_MIN_NINT_MIN_SHIFT 15 +#define QCA_PLL_PCIE_PLL_DITHER_MIN_NINT_MIN_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_MIN_NINT_MIN_SHIFT, 6) + +/* PCIE_PLL_DITHER_STEP (PCIE PLL dither parameter) */ +#define QCA_PLL_PCIE_PLL_DITHER_STEP_NFRAC_STEP_SHIFT 1 +#define QCA_PLL_PCIE_PLL_DITHER_STEP_NFRAC_STEP_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_STEP_NFRAC_STEP_SHIFT, 14) +#define QCA_PLL_PCIE_PLL_DITHER_STEP_NINT_STEP_SHIFT 15 +#define QCA_PLL_PCIE_PLL_DITHER_STEP_NINT_STEP_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_STEP_NINT_STEP_SHIFT, 10) +#define QCA_PLL_PCIE_PLL_DITHER_STEP_UPDATE_CNT_SHIFT 28 +#define QCA_PLL_PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK BITS(QCA_PLL_PCIE_PLL_DITHER_STEP_UPDATE_CNT_SHIFT, 4) +/* SWITCH_CLOCK_CONTROL */ #if (SOC_TYPE & QCA_AR934X_SOC) |\ (SOC_TYPE & QCA_QCA953X_SOC) - #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT 6 - #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT 0 + #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT 1 + #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT 2 + #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_OFF_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT 3 + #define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT 4 + #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT 5 + #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT 6 + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL_SHIFT) #else - #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT 6 - #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT) - #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT 12 - #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT) - #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT 13 - #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT) - #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT 14 - #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT) - #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT 15 - #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_I2C_CLK_SEL_SHIFT 5 + #define QCA_PLL_SWITCH_CLK_CTRL_I2C_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_I2C_CLK_SEL_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT 6 + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_1_SHIFT) + + #if (SOC_TYPE & QCA_QCA955X_SOC) + #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT 12 + #define QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_NAND_CLK_SEL_SHIFT) + #elif (SOC_TYPE & QCA_QCA956X_SOC) + #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT 12 + #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_PLL_EN_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT 19 + #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_CLK_SEL_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT 16 + #define QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_SWITCH_TEST_MODE_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT 17 + #define QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_EEE_EN_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT 18 + #define QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_ETH_PHY_125MHZ_DIS_SHIFT) + #endif + + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT 13 + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL0_2_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT 14 + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_1_SHIFT) + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT 15 + #define QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL1_2_SHIFT) #endif -#define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT 7 -#define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT) -#define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT 8 -#define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_MASK BITS(QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT, 4) +#define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT 7 +#define QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_MASK BIT(QCA_PLL_SWITCH_CLK_CTRL_HSUART_CLK_SEL_SHIFT) +#define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT 8 +#define QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_MASK BITS(QCA_PLL_SWITCH_CLK_CTRL_USB_CLK_SEL_SHIFT, 4) /* DDR_PLL_DITHER register (DDR PLL dither parameter) */ -#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT 0 -#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT, 10) -#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT 10 -#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 10) +#if (SOC_TYPE & QCA_QCA956X_SOC) + #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_L_SHIFT 0 + #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_L_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_L_SHIFT, 5) + #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_H_SHIFT 5 + #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_H_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_H_SHIFT, 13) +#else + #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT 0 + #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT, 10) + #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT 10 + #define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 10) +#endif + #define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_SHIFT 20 #define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 7) #define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT 27 @@ -1173,6 +1288,12 @@ #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT 31 #define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT) +/* DDR_PLL_DITHER2 register (QCA956x only) */ +#define QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_L_SHIFT 0 +#define QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_L_MASK BITS(QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_L_SHIFT, 5) +#define QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_H_SHIFT 5 +#define QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_H_MASK BITS(QCA_PLL_DDR_PLL_DITHER2_NFRAC_MAX_H_SHIFT, 13) + #if (SOC_TYPE & QCA_AR933X_SOC) /* PLL_DITHER_FRAC register (CPU PLL dither FRAC) */ #define QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT 0 @@ -1185,52 +1306,95 @@ /* PLL_DITHER register (CPU PLL dither) */ #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 0 #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 14) - #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31 - #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT) #else /* CPU_PLL_DITHER register (CPU PLL dither parameter) */ - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT 0 - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 6) - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT 6 - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6) - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 12 - #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6) - #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 18 - #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6) - #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31 - #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT) + #if (SOC_TYPE & QCA_QCA956X_SOC) + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_L_SHIFT 0 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_L_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_L_SHIFT, 5) + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_H_SHIFT 5 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_H_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_H_SHIFT, 13) + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 18 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6) + #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 24 + #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6) + #else + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT 0 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 6) + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT 6 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6) + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 12 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6) + #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 18 + #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6) + #endif #endif +#define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31 +#define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK BIT(QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT) + +/* CPU_PLL_DITHER2 register (QCA956x only) */ +#define QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_L_SHIFT 0 +#define QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_L_MASK BITS(QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_L_SHIFT, 5) +#define QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_H_SHIFT 5 +#define QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_H_MASK BITS(QCA_PLL_CPU_PLL_DITHER2_NFRAC_MAX_H_SHIFT, 13) + /* * PLL SRIF registers (not available in AR933x) */ -#define QCA_PLL_SRIF_CPU_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x1C0 -#define QCA_PLL_SRIF_CPU_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x1C4 -#define QCA_PLL_SRIF_CPU_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x1C8 -#define QCA_PLL_SRIF_AUD_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x200 -#define QCA_PLL_SRIF_AUD_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x204 -#define QCA_PLL_SRIF_AUD_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x208 -#define QCA_PLL_SRIF_DDR_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x240 -#define QCA_PLL_SRIF_DDR_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x244 -#define QCA_PLL_SRIF_DDR_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x248 -#define QCA_PLL_SRIF_PCIE_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0xC00 -#define QCA_PLL_SRIF_PCIE_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0xC04 -#define QCA_PLL_SRIF_PCIE_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0xC08 +#define QCA_PLL_SRIF_BB_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0x180 +#define QCA_PLL_SRIF_AUD_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0x200 + +#if (SOC_TYPE & QCA_QCA955X_SOC) |\ + (SOC_TYPE & QCA_QCA956X_SOC) + #define QCA_PLL_SRIF_CPU_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0xF00 + #define QCA_PLL_SRIF_DDR_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0xEC0 + #define QCA_PLL_SRIF_PCIE_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0xC80 +#else + #define QCA_PLL_SRIF_CPU_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0x1C0 + #define QCA_PLL_SRIF_DDR_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0x240 + #define QCA_PLL_SRIF_PCIE_DPLL_BASE_REG QCA_PLL_SRIF_BASE_REG + 0xC00 +#endif + +#define QCA_PLL_SRIF_BB_DPLL1_REG QCA_PLL_SRIF_BB_DPLL_BASE_REG + 0x0 +#define QCA_PLL_SRIF_BB_DPLL2_REG QCA_PLL_SRIF_BB_DPLL_BASE_REG + 0x4 +#define QCA_PLL_SRIF_BB_DPLL3_REG QCA_PLL_SRIF_BB_DPLL_BASE_REG + 0x8 +#define QCA_PLL_SRIF_BB_DPLL4_REG QCA_PLL_SRIF_BB_DPLL_BASE_REG + 0xC + +#define QCA_PLL_SRIF_CPU_DPLL1_REG QCA_PLL_SRIF_CPU_DPLL_BASE_REG + 0x0 +#define QCA_PLL_SRIF_CPU_DPLL2_REG QCA_PLL_SRIF_CPU_DPLL_BASE_REG + 0x4 +#define QCA_PLL_SRIF_CPU_DPLL3_REG QCA_PLL_SRIF_CPU_DPLL_BASE_REG + 0x8 +#define QCA_PLL_SRIF_CPU_DPLL4_REG QCA_PLL_SRIF_CPU_DPLL_BASE_REG + 0xC + +#define QCA_PLL_SRIF_AUD_DPLL1_REG QCA_PLL_SRIF_AUD_DPLL_BASE_REG + 0x0 +#define QCA_PLL_SRIF_AUD_DPLL2_REG QCA_PLL_SRIF_AUD_DPLL_BASE_REG + 0x4 +#define QCA_PLL_SRIF_AUD_DPLL3_REG QCA_PLL_SRIF_AUD_DPLL_BASE_REG + 0x8 +#define QCA_PLL_SRIF_AUD_DPLL4_REG QCA_PLL_SRIF_AUD_DPLL_BASE_REG + 0xC + +#define QCA_PLL_SRIF_DDR_DPLL1_REG QCA_PLL_SRIF_DDR_DPLL_BASE_REG + 0x0 +#define QCA_PLL_SRIF_DDR_DPLL2_REG QCA_PLL_SRIF_DDR_DPLL_BASE_REG + 0x4 +#define QCA_PLL_SRIF_DDR_DPLL3_REG QCA_PLL_SRIF_DDR_DPLL_BASE_REG + 0x8 +#define QCA_PLL_SRIF_DDR_DPLL4_REG QCA_PLL_SRIF_DDR_DPLL_BASE_REG + 0xC + +#define QCA_PLL_SRIF_PCIE_DPLL1_REG QCA_PLL_SRIF_PCIE_DPLL_BASE_REG + 0x0 +#define QCA_PLL_SRIF_PCIE_DPLL2_REG QCA_PLL_SRIF_PCIE_DPLL_BASE_REG + 0x4 +#define QCA_PLL_SRIF_PCIE_DPLL3_REG QCA_PLL_SRIF_PCIE_DPLL_BASE_REG + 0x8 +#define QCA_PLL_SRIF_PCIE_DPLL4_REG QCA_PLL_SRIF_PCIE_DPLL_BASE_REG + 0xC /* * PLL SRIF registers BIT fields (not available in AR933x) */ -/* DPLL1 (common for CPU, AUD, DDR and PCIE) */ -#define QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT 0 -#define QCA_PLL_SRIF_DPLL1_NFRAC_MASK BITS(QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT, 18) -#define QCA_PLL_SRIF_DPLL1_NINT_SHIFT 18 -#define QCA_PLL_SRIF_DPLL1_NINT_MASK BITS(QCA_PLL_SRIF_DPLL1_NINT_SHIFT, 9) -#define QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT 27 -#define QCA_PLL_SRIF_DPLL1_REFDIV_MASK BITS(QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT, 5) - -/* DPLL2 (common for CPU, AUD, DDR and PCIE) */ -#if (SOC_TYPE & QCA_QCA953X_SOC) +/* DPLL1 (common for BB, CPU, AUD, DDR and PCIE) */ +#define QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT 0 +#define QCA_PLL_SRIF_DPLL1_NFRAC_MASK BITS(QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT, 18) +#define QCA_PLL_SRIF_DPLL1_NINT_SHIFT 18 +#define QCA_PLL_SRIF_DPLL1_NINT_MASK BITS(QCA_PLL_SRIF_DPLL1_NINT_SHIFT, 9) +#define QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT 27 +#define QCA_PLL_SRIF_DPLL1_REFDIV_MASK BITS(QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT, 5) + +/* DPLL2 (common for BB, CPU, AUD, DDR and PCIE) */ +#if (SOC_TYPE & QCA_QCA953X_SOC) |\ + (SOC_TYPE & QCA_QCA956X_SOC) #define QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT 0 #define QCA_PLL_SRIF_DPLL2_RST_TEST_MASK BIT(QCA_PLL_SRIF_DPLL2_RST_TEST_SHIFT) #define QCA_PLL_SRIF_DPLL2_SEL_CNT_SHIFT 1 @@ -1254,10 +1418,18 @@ #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 31 #define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK BIT(QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT) #else + #define QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT 0 + #define QCA_PLL_SRIF_DPLL2_TEST_IN_MASK BITS(QCA_PLL_SRIF_DPLL2_TEST_IN_SHIFT, 7) + #define QCA_PLL_SRIF_DPLL2_DELTA_SHIFT 7 + #define QCA_PLL_SRIF_DPLL2_DELTA_MASK BITS(QCA_PLL_SRIF_DPLL2_DELTA_SHIFT, 6) #define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 13 #define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2) #define QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT 16 #define QCA_PLL_SRIF_DPLL2_PLLPWD_MASK BIT(QCA_PLL_SRIF_DPLL2_PLLPWD_SHIFT) + #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT 17 + #define QCA_PLL_SRIF_DPLL2_SEL_1SDM_MASK BIT(QCA_PLL_SRIF_DPLL2_SEL_1SDM_SHIFT) + #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT 18 + #define QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_MASK BIT(QCA_PLL_SRIF_DPLL2_NEGTRIG_EN_SHIFT) #define QCA_PLL_SRIF_DPLL2_KD_SHIFT 19 #define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7) #define QCA_PLL_SRIF_DPLL2_KI_SHIFT 26 @@ -1268,9 +1440,12 @@ #define QCA_PLL_SRIF_DPLL2_RANGE_MASK BIT(QCA_PLL_SRIF_DPLL2_RANGE_SHIFT) #endif -/* DPLL3 (common for CPU, AUD, DDR and PCIE) */ -#define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT 23 -#define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_MASK BITS(QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT, 7) +/* DPLL3 (common for BB, CPU, AUD, DDR and PCIE) */ +/* DPLL4 (common for BB, CPU, AUD, DDR and PCIE) */ + +/* + * TODO: check and confirm DPLL3/4 register structure + */ /* * Reset control registers -- 2.25.1