From 3933fdd5001cc72cb1ea8bb92bbe536b8b601504 Mon Sep 17 00:00:00 2001 From: Rich Felker Date: Mon, 14 Apr 2014 23:41:49 -0400 Subject: [PATCH] use dmb barrier instruction for atomics on arm v7 aside from potentially offering better performance, this change is needed since the old coprocessor-based approach to barriers is deprecated in arm v7, and some compilers/assemblers issue errors when using the deprecated instruction for v7 targets. --- arch/arm/atomic.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/atomic.h b/arch/arm/atomic.h index 50ad9478..d8f64843 100644 --- a/arch/arm/atomic.h +++ b/arch/arm/atomic.h @@ -25,17 +25,24 @@ static inline int a_ctz_64(uint64_t x) #if __ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__ \ || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ \ || __ARM_ARCH >= 7 + +#if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7 +#define MEM_BARRIER "dmb ish" +#else +#define MEM_BARRIER "mcr p15,0,r0,c7,c10,5" +#endif + static inline int __k_cas(int t, int s, volatile int *p) { int ret; __asm__( - " mcr p15,0,r0,c7,c10,5\n" + " " MEM_BARRIER "\n" "1: ldrex %0,%3\n" " subs %0,%0,%1\n" " strexeq %0,%2,%3\n" " teqeq %0,#1\n" " beq 1b\n" - " mcr p15,0,r0,c7,c10,5\n" + " " MEM_BARRIER "\n" : "=&r"(ret) : "r"(t), "r"(s), "Q"(*p) : "memory", "cc" ); -- 2.25.1