From 2e15e082e0aa7ff0f14f831d4c9e498b94c909c5 Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Sun, 21 Feb 2016 10:29:34 +0100 Subject: [PATCH] Introduce new low level init code for AR934x/QCA95xx and AR933x New code is simpler, more universal and supports: - clock configuration stored in FLASH - non-fractional PLL/clocks configuration - recovery mode (sets safe clocks when recovery button is pressed) This was tested on many different QC/A WiSoCs and platforms, including new QCA95xx chips. Code for AR933x still needs some additional work. The original code from Atheros SDK is very buggy and includes lot of (still) unknown parts, like "pmu setup", "meas", etc. It seems that most of that is related with radio configuration. --- u-boot/cpu/mips/ar7240/Makefile | 6 +- u-boot/cpu/mips/ar7240/ar933x_pll_init.S | 718 ++++------ u-boot/cpu/mips/ar7240/ar934x_pll_init.S | 290 ---- u-boot/cpu/mips/ar7240/qca95xx_pll_init.S | 471 +++++++ u-boot/include/soc/ar933x_pll_init.h | 200 +++ u-boot/include/soc/qca95xx_pll_init.h | 1460 +++++++++++++++++++++ u-boot/include/soc/qca_pll_list.h | 139 ++ 7 files changed, 2541 insertions(+), 743 deletions(-) delete mode 100644 u-boot/cpu/mips/ar7240/ar934x_pll_init.S create mode 100755 u-boot/cpu/mips/ar7240/qca95xx_pll_init.S create mode 100644 u-boot/include/soc/ar933x_pll_init.h create mode 100644 u-boot/include/soc/qca95xx_pll_init.h create mode 100644 u-boot/include/soc/qca_pll_list.h diff --git a/u-boot/cpu/mips/ar7240/Makefile b/u-boot/cpu/mips/ar7240/Makefile index f009f25..7f21c65 100644 --- a/u-boot/cpu/mips/ar7240/Makefile +++ b/u-boot/cpu/mips/ar7240/Makefile @@ -23,7 +23,11 @@ endif ifeq ($(BOARD), db12x) OBJS += ag934x.o - SOBJS += ar934x_pll_init.o + SOBJS += qca95xx_pll_init.o +endif + +ifeq ($(BOARD), ap143) + SOBJS += qca95xx_pll_init.o endif all: .depend $(START) $(LIB) diff --git a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S index 21f77a6..b12e71f 100644 --- a/u-boot/cpu/mips/ar7240/ar933x_pll_init.S +++ b/u-boot/cpu/mips/ar7240/ar933x_pll_init.S @@ -1,531 +1,345 @@ +/* + * PLL and clocks configurations for + * Qualcomm/Atheros AR933x WiSoC + * + * Copyright (C) 2016 Piotr Dymacz + * Copyright (C) 2008-2010 Atheros Communications Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include #include -#include +#include +#include #include #include #include -#include - - .globl lowlevel_init - .type lowlevel_init, @function - .text - .align 4 - -#define CLEAR_BIT(val, bit) ((val) & ~(1 << (bit))) -#define SET_BIT(val, bit) ((val) | (1 << (bit))) - -#define CLEAR_PLL_POWER_DOWN(reg_val) CLEAR_BIT(reg_val, 30) -#define SET_PLL_POWER_DOWN(reg_val) SET_BIT(reg_val, 30) -#define SET_AHB_DIV_TO_4(reg_val) SET_BIT(SET_BIT(reg_val, 15), 16) -#define CLEAR_PLL_BYPASS(reg_val) CLEAR_BIT(reg_val, 2) -#define SET_PLL_BYPASS(reg_val) SET_BIT(reg_val, 2) -/* - * Helper macros. - * These Clobber t7, t8 and t9 - * or t8, t8, t9; - */ -#define set_reg(_reg, _val) \ - li t7, KSEG1ADDR(_reg); \ - lw t8, 0(t7); \ - li t9, _val; \ - sw t9, 0(t7); - -/* if reset button is active low -> use bne (branch on not equal) */ -#ifdef GPIO_RST_BUTTON_IS_ACTIVE_LOW - #define recovery_jump(_branch) \ - bne t1, (1 << GPIO_RST_BUTTON_BIT), _branch; -#else - #define recovery_jump(_branch) \ - beq t1, (1 << GPIO_RST_BUTTON_BIT), _branch; +#define reg_oc_recovery t0 +#define reg_spi_ctrl_cfg t1 +#define reg_ref_clk_val t2 +#define reg_cpu_pll_cfg t3 +#define reg_cpu_clk_ctrl t4 +#define reg_cpu_pll_dit t5 +#define reg_loop_counter t6 + +/* Sanity check for O/C recovery button number */ +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN + #if (CONFIG_QCA_GPIO_OC_RECOVERY_BTN >= QCA_GPIO_COUNT) + #error "O/C recovery button number is not correct!" + #endif + + #define CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN \ + (1 << CONFIG_QCA_GPIO_OC_RECOVERY_BTN) #endif +.globl lowlevel_init +.type lowlevel_init, @function +.align 4 +.text +.ent lowlevel_init + lowlevel_init: -#if 1 -/* These three wlan reset will avoid original issue, - * so full chip reset isn't needed here. - * - * WLAN_RESET in RST_RESET (AR7240_RESET) register - * 0x00C06B30 -> BIT(11) is set - * 0x00C06330 -> BIT(11) is not set +/* + * Get reference clock (XTAL) type, based on BOOTSTRAP register + * and save its value in one register for later use */ - set_reg(AR7240_RESET, 0x00C06B30) - nop - set_reg(AR7240_RESET, 0x00C06330) - nop - set_reg(AR7240_RESET, 0x00C06B30) - nop - set_reg(AR7240_RESET, 0x00C06330) + li reg_ref_clk_val, 25 + li t8, QCA_RST_BOOTSTRAP_REG + lw t9, 0(t8) + li t8, QCA_RST_BOOTSTRAP_REF_CLK_MASK + and t9, t9, t8 + bgtz t9, set_xtal_40mhz nop -reset_wlan: - set_reg(AR7240_RESET, 0x00C06B30) + b wlan_rst_init nop - set_reg(AR7240_RESET, 0x00C06330) - nop - li t5, 0x20 - -check_val: - beq zero, t5, reset_wlan - addi t5, t5, -1 - li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS) - lw t7, 0(t6) - li t8, 0x10 - and t7, t7, t8 - bne zero, t7, check_val - set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110E) - nop -#else -/* clear wlan reset bit in RESET_Register 0x1c */ - set_reg(AR7240_RESET, 0x00C06B30) - nop - set_reg(AR7240_RESET, 0x00C06330) - nop - -/* cleck bootstrap status, wait for bit4 on, then clear bit16 */ -wait_loop0: - li t6, KSEG1ADDR(HORNET_BOOTSTRAP_STATUS) - lw t7, 0(t6) - li t8, 0x10 - and t7, t7, t8 - bne zero, t7, wait_loop0 - nop - set_reg(HORNET_BOOTSTRAP_STATUS, 0x0002110E) - nop -#endif -/* RTC reset */ -/* 0x1810704C -> RTC_FORCE_WAKE (RTC Force Wake) */ - set_reg(0x1810704C, 0x00000003) - nop - nop -/* 0x18107040 -> RTC_RESET (RTC Reset and Force Sleep and Force Wakeup) */ - set_reg(0x18107040, 0x00000000) - nop - nop - set_reg(0x18107040, 0x00000001) - nop - -wait_loop1: -/* 0x18107044 -> RTC_STATUS (RTC Sleep Status) */ - li t6, KSEG1ADDR(0x18107044) - lw t7, 0(t6) - li t8, 0x2 - and t7, t7, t8 - bne t8, t7, wait_loop1 - nop +set_xtal_40mhz: + li reg_ref_clk_val, 40 /* - * AHB/APH reset - * TODO: 0x18104000 is "Reset the Host Interface (HOST_INTF_RESET_CONTROL)" and bits 0:7 are RESERVED! + * Several WLAN module resets as in broken Atheros SDK code + * TODO: do we really need this? */ -/* - set_reg(0x18104000, 0x00000003) - nop - set_reg(0x18104000, 0x00000000) - nop -*/ -/* - * MAC reset (TODO: ?? AR9344 has 0x18107000 register -> AR9344_RTC_BASE) - */ -/* - set_reg(0x18107000, 0x0000000F) - nop - set_reg(0x18107000, 0x00000000) - nop -*/ +wlan_rst_init: + li reg_loop_counter, 10 -#if 1 /* fetch pmu1.refv and ctrl2.tx from OTP */ - li t1, KSEG1ADDR(0x18114014) - lw t2, 0(t1) - -otp_loop0: - li t3, KSEG1ADDR(0x18115F18) - lw t4, 0(t3) - nop - li t5, 0x7 - and t4, t4, t5 - li t5, 0x4 - bne t4, t5, otp_loop0 +wlan_rst: + li t8, QCA_RST_RST_REG + lw t9, 0(t8) + or t9, t9, QCA_RST_RESET_WLAN_RST_MASK + sw t9, 0(t8) nop - li t6, KSEG1ADDR(0x18115F1C) - lw t7, 0(t6) nop - li t8, 0x80000080 - and t9, t7, t8 - beq t8, t9, fetch_otp -otp_loop0_end: - li t1, KSEG1ADDR(0x18114004) - lw t2, 0(t1) - -otp_loop1: - li t3, KSEG1ADDR(0x18115F18) - lw t4, 0(t3) - nop - li t5, 0x7 - and t4, t4, t5 - li t5, 0x4 - bne t4, t5, otp_loop1 + lw t9, 0(t8) + and t9, t9, ~QCA_RST_RESET_WLAN_RST_MASK + sw t9, 0(t8) nop - li t6, KSEG1ADDR(0x18115F1C) - lw t7, 0(t6) nop - li t8, 0x80000080 - and t9, t7, t8 - -default_pmu: - li t5, 0x80 /* default 0x031c4386 */ - bne t8, t9, otp_end - -fetch_otp: - srl t8, t7, 0x18 - li t1, 0xf - and t2, t1, t7 /* USB */ - and t5, t1, t8 /* PMU */ - -check_pmu: - li t0, 0x4 /* PMU range should be 0x4~0xa */ - bgt t0, t5, default_pmu - nop - li t0, 0xa /* PMU range should be 0x4~0xa */ - blt t0, t5, default_pmu - nop - li t0, 0x4 - sll t5, t5, t0 - -otp_end: -#endif -#if 1 /* Program PMU */ -#define PMU_TEST_NO 1000 - li t6, KSEG1ADDR(0x18116C40) - li t9, 0xbd000010 - li t0, 0 - li t1, 0 - li t2, 0 - li t3, PMU_TEST_NO - sw t3, 12(t9) - -pmu_loop0: - beq zero, t3, pmu_loop0_end - nop - addi t3, t3, -1 - li t7, 0x10180000 /* ldo_tune 0x3 */ - nop - sw t7, 4(t6) - nop - lw t8, 4(t6) - nop - beq t8, t7, pmu_loop0_end - nop - addiu t0, t0, 1 - b pmu_loop0 - nop - -pmu_loop0_end: - li t3, PMU_TEST_NO - -pmu_loop1: - beq zero, t3, pmu_loop1_end - nop - addi t3, t3, -1 - //li t7, 0x031c4326 /* 1.100V */ - //li t7, 0x031c4336 /* 1.125V */ - //li t7, 0x031c4346 /* 1.150V */ - //li t7, 0x031c4356 /* 1.175V */ - //li t7, 0x031c4366 /* 1.200V */ - //li t7, 0x031c4376 /* 1.225V */ - li t7, 0x031c4386 /* 1.250V (DEFAULT) */ - //li t7, 0x031c4396 /* 1.275V */ - //li t7, 0x031c43a6 /* 1.300V */ - nop - -#if 1 /* from OTP */ - li t8, 0xFFFFFF0F - and t7, t7, t8 - or t7, t7, t5 -#endif - sw t7, 0(t6) - nop - lw t8, 0(t6) - nop - beq t8, t7, pmu_loop1_end - nop - addiu t1, t1, 1 - b pmu_loop1 - nop - -pmu_loop1_end: - li t3, PMU_TEST_NO - -pmu_loop2: - beq zero, t3, pmu_loop2_end - nop - addi t3, t3, -1 - li t7, 0x10380000 /* ldo_tune 0x3 */ - nop - sw t7, 4(t6) - nop - lw t8, 4(t6) - nop - beq t8, t7, pmu_loop2_end - nop - addiu t2, t2, 1 - b pmu_loop2 - nop - -pmu_loop2_end: - sw t0, 0(t9) - nop - sw t1, 4(t9) - nop - sw t2, 8(t9) - nop -#endif - -#if 1 /* Program ki, kd */ -// TODO: ?? -/* Program ki/kd */ -#if CONFIG_40MHZ_XTAL_SUPPORT - set_reg(0x18116244, 0x19e82f01) -#else - set_reg(0x18116244, 0x18e82f01) -#endif - nop - -/* Program phase shift */ - li t6, KSEG1ADDR(0x18116248) - lw t7, 0(t6) - li t8, 0xc07fffff - and t7, t7, t8 - li t8, 0x800000 - or t7, t7, t8 - sw t7, 0(t6) - nop -#endif - -/* max AHB Master wait time out ... */ - set_reg(0x1800009C, 0xfffff) + addi reg_loop_counter, reg_loop_counter, -1 + bnez reg_loop_counter, wlan_rst nop /* - * O/C recovery mode + * From datasheet: + * For normal operation mode, SW should select + * the APB interface before register access * - * If RESET BUTTON is pressed and hold during power on - * we will use default PLL and clocks configuration (400/400/200) - * - * Using t0 and t1 (t1 indicates if recovery mode was turned on) + * Register: BOOTSTRAP, bit: 17 (JTAG=1, APB=0) + * Should be set by default, but it's not... */ -pll_clock_control_oc_recovery: - li t0, KSEG1ADDR(AR7240_GPIO_IN) - lw t1, 0(t0) - and t1, t1, (1 << GPIO_RST_BUTTON_BIT) - recovery_jump(pll_clock_control_default) - nop +sel_apb_for_mac: + li t8, QCA_RST_BOOTSTRAP_REG + lw t9, 0(t8) + and t9, t9, ~QCA_RST_BOOTSTRAP_JTAG_APB_SEL_MASK + sw t9, 0(t8) + +/* AHB max master timeout */ +ahb_max_timeout: + li t8, QCA_AHB_MASTER_TOUT_MAX_REG + lw t9, 0(t8) + or t9, t9, 0xFFFFF + sw t9, 0(t8) -#if defined(PLL_IN_FLASH_MAGIC_OFFSET) /* - * PLL and CLOCK configuration from FLASH - * - * Using t0, t2 and t3 (t2 stores magic value from flash) + * Reset RTC + * TODO: do we need to reset RTC at all? */ -pll_clock_control_flash: - li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address - lw t2, 0(t0) // load PLL_IN_FLASH_MAGIC value from FLASH - bne t2, PLL_IN_FLASH_MAGIC, pll_clock_control // jump if we don't have PLL_MAGIC value in FLASH +rtc_reset: + li t8, QCA_RTC_SYNC_FORCE_WAKE_REG + li t9, (QCA_RTC_SYNC_FORCE_WAKE_EN_MASK |\ + QCA_RTC_SYNC_FORCE_WAKE_MACINTR_MASK) + sw t9, 0(t8) nop - lw t3, 8(t0) // load CLOCK_CONTROL register value from FLASH - or t3, t3, 0x18004 // set BYPASS bit and make AHB_POST_DIV = 4 - li t0, KSEG1ADDR(AR7240_CPU_CLOCK_CONTROL) // load CLOCK_CONTROL register address - sw t3, 0(t0) // store value in CLOCK_CONTROL register - j pll_settle_time // jump to pll_settle_time nop -#endif -pll_clock_control: -/* set PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */ -/* in some cases, the SoC doesn't start with higher clock on AHB */ - set_reg(AR7240_CPU_CLOCK_CONTROL, SET_AHB_DIV_TO_4(SET_PLL_BYPASS(CPU_CLK_CONTROL_VAL))) - j pll_settle_time + li t8, QCA_RTC_SYNC_RST_REG + li t9, 0x0 + sw t9, 0(t8) nop - -pll_clock_control_default: -/* set PLL bypass(Bit 2), CPU_POST_DIV, DDR_POST_DIV, AHB_POST_DIV in CPU clock control */ -/* in some cases, the SoC doesn't start with higher clock on AHB */ - set_reg(AR7240_CPU_CLOCK_CONTROL, SET_AHB_DIV_TO_4(SET_PLL_BYPASS(CPU_CLK_CONTROL_VAL_DEFAULT))) nop -pll_settle_time: -/* set SETTLE_TIME in CPU PLL */ - set_reg(AR7240_USB_PLL_CONFIG, CPU_PLL_SETTLE_TIME_VAL) + li t9, QCA_RTC_SYNC_RST_RESET_MASK + sw t9, 0(t8) nop -pll_unlock_handler_oc_recovery: - recovery_jump(pll_unlock_handler_default) - nop + li t8, QCA_RTC_SYNC_STATUS_REG -#if defined(PLL_IN_FLASH_MAGIC_OFFSET) -pll_unlock_handler_flash: - bne t2, PLL_IN_FLASH_MAGIC, pll_unlock_handler // jump if we don't have PLL_MAGIC value in FLASH +rtc_wait_on: + lw t9, 0(t8) + and t9, t9, QCA_RTC_SYNC_STATUS_ON_MASK + beqz t9, rtc_wait_on nop - li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address - lw t3, 4(t0) // load CPU_PLL_CONFIG register value from FLASH - or t3, t3, 0x40000000 // set CPU_PLLPWD bit (power down for CPU PLL) - li t0, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) // load CPU_PLL_CONFIG register address - sw t3, 0(t0) // store value in CPU_PLL_CONFIG register - j wait_loop2 // jump to wait_loop2 - nop -#endif -pll_unlock_handler: -/* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */ - set_reg(AR7240_CPU_PLL_CONFIG, SET_PLL_POWER_DOWN(CPU_PLL_CONFIG_VAL)) - j wait_loop2 - nop - -pll_unlock_handler_default: -/* set nint, frac, refdiv, outdiv, range in CPU PLL configuration resiter */ - set_reg(AR7240_CPU_PLL_CONFIG, SET_PLL_POWER_DOWN(CPU_PLL_CONFIG_VAL_DEFAULT)) - nop +/* + * O/C recovery mode (start with safe PLL/clocks configuration): + * 1. Check if defined recovery button is pressed + * 2. Indicate recovery mode in predefined register + * 3. If in recovery mode, do not use PLL configuration from FLASH, + * because it is probably the reason why user is using recovery mode + */ +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN +is_oc_recovery_btn_pressed: + li reg_oc_recovery, 0 + li t8, QCA_GPIO_IN_REG + lw t9, 0(t8) + and t9, t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN -wait_loop2: - li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) - lw t7, 0(t6) - li t8, 0x80000000 - and t7, t7, t8 - bne zero, t7, wait_loop2 + #ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW + bne t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN, in_oc_recovery_mode nop - -/* put frac bit19:10 configuration */ -/* TODO: do we need this? */ - set_reg(AR7240_PCIE_PLL_CONFIG, CPU_PLL_DITHER_FRAC_VAL) - nop - -pll_lock_handler_oc_recovery: - recovery_jump(pll_lock_handler_default) + #else + beq t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN, in_oc_recovery_mode nop + #endif -#if defined(PLL_IN_FLASH_MAGIC_OFFSET) -pll_lock_handler_flash: - bne t2, PLL_IN_FLASH_MAGIC, pll_lock_handler // jump if we don't have PLL_MAGIC value in FLASH + #ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET + b is_pll_cfg_in_flash + #else + b xtal_type_check + #endif nop - li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address - lw t3, 4(t0) // load CPU_PLL_CONFIG register value from FLASH - li t0, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) // load CPU_PLL_CONFIG register address - sw t3, 0(t0) // store value in CPU_PLL_CONFIG register - j wait_loop3 // jump to wait_loop3 - nop -#endif -pll_lock_handler: -/* clear PLL power down bit in CPU PLL configuration */ - set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL) - j wait_loop3 +in_oc_recovery_mode: + li reg_oc_recovery, 1 + b xtal_type_check nop +#endif /* CONFIG_QCA_GPIO_OC_RECOVERY_BTN */ -pll_lock_handler_default: -/* clear PLL power down bit in CPU PLL configuration */ - set_reg(AR7240_CPU_PLL_CONFIG, CPU_PLL_CONFIG_VAL_DEFAULT) +/* + * Check if PLL configuration is stored in FLASH: + * 1. Get 32-bit value from defined offset in FLASH + * 2. Compare it with predefined magic value + * 3. If values are not equal, continue default PLL/clocks configuration + * 4. If values are equal it means we should have target PLL/clocks register + * values stored in FLASH, just after magic value, in the following order: + * - SPI_CONTROL (offset 4) + * - CPU_PLL_CONFIG (offset 8) + * - CPU_CLOCK_CONTROL (offset 12) + * - CPU_PLL_DITHER_FRAC (offset 16) + * 5. After loading target values from FLASH, + * jump directly to PLL/clocks configuration + */ +#ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET +is_pll_cfg_in_flash: + li t8, CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET + lw t9, 0(t8) + bne t9, QCA_PLL_IN_FLASH_MAGIC, xtal_type_check nop -wait_loop3: -/* wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */ - li t6, KSEG1ADDR(AR7240_CPU_PLL_CONFIG) - lw t7, 0(t6) - li t8, 0x80000000 - and t7, t7, t8 - bne zero, t7, wait_loop3 +pll_cfg_in_flash: + lw reg_spi_ctrl_cfg, 4(t8) + lw reg_cpu_pll_cfg, 8(t8) + lw reg_cpu_clk_ctrl, 12(t8) + lw reg_cpu_pll_dit, 16(t8) + b cpu_clock_control nop +#endif /* CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET */ -/* confirm DDR PLL lock */ - li t3, 100 - li t4, 0 - -start_meas0: - addi t4, t4, 1 - bgt t4, t3, pll_unlock_handler_oc_recovery - nop - li t5, 5 - -start_meas: - li t6, KSEG1ADDR(0x18116248) - lw t7, 0(t6) - li t8, 0xBFFFFFFF - and t7, t7, t8 - sw t7, 0(t6) +/* + * Check XTAL type, configure PLL settle time and include dedicated + * PLL/clocks values, predefined in header file, based on selected + * preset configuration + */ +xtal_type_check: + beq reg_ref_clk_val, 40, xtal_is_40mhz nop -/* delay */ - li t9, 10 +xtal_is_25mhz: + li t8, QCA_PLL_CPU_PLL_CFG2_REG + li t9, QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL25 + sw t9, 0(t8) -delayloop0: - subu t9, t9, 1 - bne t9, zero, delayloop0 - nop - li t8, 0x40000000 - or t7, t7, t8 - sw t7, 0(t6) +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN + beq reg_oc_recovery, 1, xtal_is_25mhz_recovery nop +#endif -meas_done_statue: - li t6, KSEG1ADDR(0x1811624C) - lw t7, 0(t6) - li t8, 0x8 - and t7, t7, t8 - beq zero, t7, meas_done_statue + li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL + li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 + li reg_cpu_clk_ctrl, QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 + li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 + b cpu_clock_control nop -meas_result: - li t6, KSEG1ADDR(0x18116248) - lw t7, 0(t6) - li t8, 0x007FFFF8 - and t7, t7, t8 - srl t7, t7, 3 - li t8, 0x4000 - bgt t7, t8, start_meas0 - nop - addi t5, t5, -1 - bne zero, t5, start_meas +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN +xtal_is_25mhz_recovery: + li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL_SAFE + li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25 + li reg_cpu_clk_ctrl, QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL25 + li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL25 + b cpu_clock_control nop +#endif -pll_clear_bypass_oc_recovery: - recovery_jump(pll_clear_bypass_default) - nop +xtal_is_40mhz: + li t8, QCA_PLL_CPU_PLL_CFG2_REG + li t9, QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL40 + sw t9, 0(t8) -#if defined(PLL_IN_FLASH_MAGIC_OFFSET) -pll_clear_bypass_flash: - bne t2, PLL_IN_FLASH_MAGIC, pll_clear_bypass // jump if we don't have PLL_MAGIC value in FLASH - nop - li t0, (CFG_FLASH_BASE + PLL_IN_FLASH_DATA_BLOCK_OFFSET + PLL_IN_FLASH_MAGIC_OFFSET) // load PLL_IN_FLASH_MAGIC address - lw t3, 8(t0) // load CLOCK_CONTROL register value from FLASH - li t0, KSEG1ADDR(AR7240_CPU_CLOCK_CONTROL) // load CLOCK_CONTROL register address - sw t3, 0(t0) // store value in CLOCK_CONTROL register - j end // jump to end +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN + beq reg_oc_recovery, 1, xtal_is_40mhz_recovery nop #endif -pll_clear_bypass: -/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */ - set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL) - j end - nop + li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL + li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 + li reg_cpu_clk_ctrl, QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 + li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 -pll_clear_bypass_default: -/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */ - set_reg(AR7240_CPU_CLOCK_CONTROL, CPU_CLK_CONTROL_VAL_DEFAULT) +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN + b cpu_clock_control nop -/* Sync mode, Set Bit 8 of DDR Tap Conrtol 3 register */ +xtal_is_40mhz_recovery: + li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL_SAFE + li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40 + li reg_cpu_clk_ctrl, QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL40 + li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL40 +#endif + /* - * TODO: something is wrong here? - * There is no AR7240_DDR_TAP_CONTROL3 in AR9331 datasheet! + * Load target value into CPU_CLOCK_CONTROL register, but for now keep bypass + * enabled (by default, after reset, it should be bypassed, do it just in case) */ +cpu_clock_control: + li t8, QCA_PLL_CPU_CLK_CTRL_REG + move t9, reg_cpu_clk_ctrl + or t9, t9, QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK + sw t9, 0(t8) + /* - set_reg(AR7240_DDR_TAP_CONTROL3, 0x10105); + * Load target value into CPU_PLL_CONFIG register, but for now keep PLL down + * (by default, after reset, it should be powered down, do it just in case) + */ +cpu_pll_config: + li t8, QCA_PLL_CPU_PLL_CFG_REG + move t9, reg_cpu_pll_cfg + or t9, t9, QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK + sw t9, 0(t8) + +/* Load target NFRAC_MIN value into PLL_DITHER_FRAC register */ +cpu_pll_dither: + li t8, QCA_PLL_CPU_PLL_DITHER_FRAC_REG + lw t9, 0(t8) + and t9, t9, ~QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK + or t9, t9, reg_cpu_pll_dit + sw t9, 0(t8) + +/* Enable CPU PLL and wait for update complete */ +cpu_pll_enable: + li t8, QCA_PLL_CPU_PLL_CFG_REG + lw t9, 0(t8) + and t9, t9, ~QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK + sw t9, 0(t8) + nop + +/* Wait for CPU PLL update complete */ +cpu_pll_wait: + lw t9, 0(t8) + and t9, t9, QCA_PLL_CPU_PLL_CFG_UPDATING_MASK + bgtz t9, cpu_pll_wait + nop + +/* Disable bypassing all clocks */ +pll_bypass_disable: + li t8, QCA_PLL_CPU_CLK_CTRL_REG + lw t9, 0(t8) + and t9, t9, ~QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK + sw t9, 0(t8) + +/* Setup SPI (clock and other settings) */ +spi_setup: + li t8, QCA_SPI_CTRL_REG + sw reg_spi_ctrl_cfg, 0(t8) + and reg_spi_ctrl_cfg, reg_spi_ctrl_cfg, QCA_SPI_CTRL_REMAP_DIS_MASK + beqz reg_spi_ctrl_cfg, end nop -*/ + +/* + * This is a small hack, needed after setting REMAP_DISABLE bit + * in SPI_CONTROL_ADDR register. + * + * Before that, SPI FLASH is mapped to 0x1FC00000, but just after + * setting REMAP_DISABLE bit, aliasing is disabled and SPI FLASH + * is mapped to 0x1F00000, so that the whole 16 MB address space + * could be used. + * + * That means, we need to "fix" return address, stored previously + * in $ra register, subtracting a value 0x00C00000 from it. + * + * Without that, jump would end up somewhere far away on FLASH... + */ + li t8, 0x00C00000 + subu ra, ra, t8 end: jr ra nop + +.end lowlevel_init diff --git a/u-boot/cpu/mips/ar7240/ar934x_pll_init.S b/u-boot/cpu/mips/ar7240/ar934x_pll_init.S deleted file mode 100644 index f2a1d02..0000000 --- a/u-boot/cpu/mips/ar7240/ar934x_pll_init.S +++ /dev/null @@ -1,290 +0,0 @@ -#include -#include -#include -#include -#include -#include - -/* - * Helper macros. - * These Clobber t7, t8 and t9 - */ -#define cpu_ddr_control_set(_mask, _val) set_val(AR934X_CPU_DDR_CLOCK_CONTROL, _mask, _val) - -#define set_val(_reg, _mask, _val) \ - li t7, KSEG1ADDR(_reg); \ - lw t8, 0(t7); \ - li t9, ~_mask; \ - and t8, t8, t9; \ - li t9, _val; \ - or t8, t8, t9; \ - sw t8, 0(t7) - -#define set_bb_pll(reg, val) \ - li t7, KSEG1ADDR(reg); \ - li t8, val; \ - sw t8, 0(t7); - -#define set_srif_pll(reg, val) \ - li t7, KSEG1ADDR(reg); \ - li t8, val; \ - sw t8, 0(t7); - -#define set_srif_pll_reg(reg, _r) \ - li t7, KSEG1ADDR(reg); \ - sw _r, 0(t7); - -#define inc_loop_count(loc) \ - li t9, loc; \ - lw t7, 0(t9); \ - addi t7, t7, 1; \ - sw t7, 0(t9); - -#define clear_loop_count(loc) \ - li t9, loc; \ - sw zero, 0(t9); - -/****************************************************************************** - * first level initialization: - * - * 0) If clock cntrl reset switch is already set, we're recovering from - * "divider reset"; goto 3. - * 1) Setup divide ratios. - * 2) Reset. - * 3) Setup pll's, wait for lock. - * - *****************************************************************************/ - -.globl lowlevel_init - .type lowlevel_init, @function - .text - .align 4 - -lowlevel_init: - set_bb_pll(DPLL2_ADDRESS_c4, 0x13210f00); // 0x181161c4 (AR934X_SRIF_CPU_DPLL2_REG) - set_bb_pll(DPLL3_ADDRESS_c8, 0x03000000); // 0x181161c8 (AR934X_SRIF_CPU_DPLL3_REG) - set_bb_pll(DPLL2_ADDRESS_44, 0x13210f00); // 0x18116244 (AR934X_SRIF_DDR_DPLL2_REG) - set_bb_pll(DPLL3_ADDRESS_48, 0x03000000); // 0x18116248 (AR934X_SRIF_DDR_DPLL3_REG) - set_bb_pll(DPLL3_ADDRESS_88, 0x03000000); // 0x18116188 (??) - -ref_recognition: - li t5, KSEG1ADDR(WASP_BOOTSTRAP_REG); - li t6, WASP_REF_CLK_25 - lw t7, 0(t5); - and t6, t7, t6 - beq zero, t6, setup_ref25_val - nop - -setup_ref40_val: - li t5, CPU_PLL_CONFIG_NINT_VAL_40 - li t6, DDR_PLL_CONFIG_NINT_VAL_40 - li t7, CPU_PLL_NFRAC_40 - li t9, DDR_PLL_NFRAC_40 - b 1f - nop - -setup_ref25_val: - li t5, CPU_PLL_CONFIG_NINT_VAL_25 - li t6, DDR_PLL_CONFIG_NINT_VAL_25 - li t7, CPU_PLL_NFRAC_25 - li t9, DDR_PLL_NFRAC_25 - -1: - li t4, (CPU_PLL_DITHER_DITHER_EN_SET(0) | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf)); - or t4, t4, t7 - - li t8, (CPU_PLL_CONFIG_REF_DIV_VAL | CPU_PLL_CONFIG_RANGE_VAL | CPU_PLL_CONFIG_OUT_DIV_VAL2); - or t5, t5, t8 - - li t8, (DDR_PLL_CONFIG_REF_DIV_VAL | DDR_PLL_CONFIG_RANGE_VAL | DDR_PLL_CONFIG_OUT_DIV_VAL2); - or t6, t6, t8 - - li t3, (DDR_PLL_DITHER_DITHER_EN_SET(0) | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf)); - or t3, t3, t9 - -pll_bypass_set: - cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1)); - cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1)); - cpu_ddr_control_set(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1)); - -init_cpu_pll: - li t7, KSEG1ADDR(AR934X_CPU_PLL_CONFIG); - li t8, CPU_PLL_CONFIG_PLLPWD_SET(1) - or t8, t8, t5 - sw t8, 0(t7); - -init_ddr_pll: - li t7, KSEG1ADDR(AR934X_DDR_PLL_CONFIG); - li t8, DDR_PLL_CONFIG_PLLPWD_SET(1) - or t8, t8, t6 - sw t8, 0(t7); - -init_ahb_pll: - li t7, KSEG1ADDR(AR934X_CPU_DDR_CLOCK_CONTROL); - li t8, (CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL | \ - CPU_DDR_CLOCK_CONTROL_AHB_CLK_DDR | \ - CPU_DDR_CLOCK_CONTROL_DDR_CLK_DDR | \ - CPU_DDR_CLOCK_CONTROL_CPU_CLK_CPU | \ - CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV | \ - CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV | \ - CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(1) | \ - CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(1) | \ - CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1)); - sw t8, 0(t7); - - /* Use built in values, based on ref clock */ - li t5, KSEG1ADDR(WASP_BOOTSTRAP_REG); - li t6, WASP_REF_CLK_25 - lw t7, 0(t5); - and t6, t7, t6 - beq zero, t6, 1f - nop -#if !defined(CONFIG_AP123) - /* refdiv nint nfrac */ - li t4, ((0x8 << 27) | (112 << 18) | 0);// cpu freq = (40 MHz refclk/refdiv 8) * Nint - li t5, ((0x8 << 27) | (90 << 18) | 0); // ddr freq = (40 MHz refclk/refdiv 8) * Nint - j 2f - nop -1: - li t4, ((0x5 << 27) | (112 << 18) | 0);// cpu freq = (25 MHz refclk/refdiv 5) * Nint - li t5, ((0x5 << 27) | (90 << 18) | 0); // ddr freq = (25 MHz refclk/refdiv 5) * Nint - j 2f - nop -#else /* defined(CONFIG_AP123) */ - /* refdiv nint nfrac */ - li t4, ((0x8 << 27) | (107 << 18) | 0);// cpu freq = (40 MHz refclk/refdiv 8) * Nint - li t5, ((0x8 << 27) | (160 << 18) | 0);// ddr freq = (40 MHz refclk/refdiv 8) * Nint - j 2f - nop -1: - li t4, ((0x5 << 27) | (107 << 18) | 0);// cpu freq = (25 MHz refclk/refdiv 5) * Nint - li t5, ((0x5 << 27) | (160 << 18) | 0);// ddr freq = (25 MHz refclk/refdiv 5) * Nint - j 2f - nop -#endif /* !defined(CONFIG_AP123) */ - -/* CPU */ -2: - clear_loop_count(ATH_CPU_COUNT_LOC); - -cpu_pll_is_not_locked: - inc_loop_count(ATH_CPU_COUNT_LOC); - set_srif_pll(0xb81161c4, (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16)); - set_srif_pll_reg(0xb81161c0, t4); - set_srif_pll(0xb81161c4, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16)); - set_srif_pll(0xb81161c8, (6 << 23)); - set_srif_pll(0xb81161c4, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7)); - -cpu_clear_do_meas1: - li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS) - lw t8, 0(t7) - li t9, ~CPU_DPLL3_DO_MEAS_SET(1) - and t8, t8, t9 - sw t8, 0(t7) - -cpu_set_do_meas: - li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS) - lw t8, 0(t7) - li t9, CPU_DPLL3_DO_MEAS_SET(1) - or t8, t8, t9 - sw t8, 0(t7) - li t7, KSEG1ADDR(CPU_DPLL4_ADDRESS) - -cpu_wait_for_meas_done: - lw t8, 0(t7) - andi t8, t8, CPU_DPLL4_MEAS_DONE_SET(1) - beqz t8, cpu_wait_for_meas_done - nop - -cpu_clear_do_meas2: - li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS) - lw t8, 0(t7) - li t9, ~CPU_DPLL3_DO_MEAS_SET(1) - and t8, t8, t9 - sw t8, 0(t7) - -cpu_read_sqsum_dvc: - li t7, KSEG1ADDR(CPU_DPLL3_ADDRESS) - lw t8, 0(t7) - li t9, CPU_DPLL3_SQSUM_DVC_MASK - and t8, t8, t9 - sra t8, t8, CPU_DPLL3_SQSUM_DVC_LSB - li t9, 0x40000 - subu t8, t8, t9 - bgez t8, cpu_pll_is_not_locked - nop - -/* DDR */ - clear_loop_count(ATH_DDR_COUNT_LOC) - -ddr_pll_is_not_locked: - inc_loop_count(ATH_DDR_COUNT_LOC) -#if !defined(CONFIG_AP123) - set_srif_pll(0xb8116244, (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16)); - set_srif_pll_reg(0xb8116240, t5); - set_srif_pll(0xb8116244, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7) | (1 << 16)); - set_srif_pll(0xb8116248, (6 << 23)); - set_srif_pll(0xb8116244, (0x3 << 30) | (0x4 << 26) | (0x10 << 19) | (0x1e << 7)); -#else /* defined(CONFIG_AP123) */ - /* AP123 uses outdiv = 1 for ddr pll */ - set_srif_pll(0xb8116244, (0x4 << 26) | (0x10 << 19) | (1 << 13) | (0x1e << 7) | (1 << 16)); - set_srif_pll_reg(0xb8116240, t5); - set_srif_pll(0xb8116244, (0x1 << 30) | (0x4 << 26) | (0x10 << 19) | (1 << 13) | (0x1e << 7) | (1 << 16)); - set_srif_pll(0xb8116248, (6 << 23)); - set_srif_pll(0xb8116244, (0x1 << 30) | (0x4 << 26) | (0x10 << 19) | (1 << 13) | (0x1e << 7)); -#endif /* !defined(CONFIG_AP123) */ - -ddr_clear_do_meas1: - li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS) - lw t8, 0(t7) - li t9, ~DDR_DPLL3_DO_MEAS_SET(1) - and t8, t8, t9 - sw t8, 0(t7) - -ddr_set_do_meas: - li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS) - lw t8, 0(t7) - li t9, DDR_DPLL3_DO_MEAS_SET(1) - or t8, t8, t9 - sw t8, 0(t7) - li t7, KSEG1ADDR(DDR_DPLL4_ADDRESS) - -ddr_wait_for_meas_done: - lw t8, 0(t7) - andi t8, t8, DDR_DPLL4_MEAS_DONE_SET(1) - beqz t8, ddr_wait_for_meas_done - nop - -ddr_clear_do_meas2: - li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS) - lw t8, 0(t7) - li t9, ~DDR_DPLL3_DO_MEAS_SET(1) - and t8, t8, t9 - sw t8, 0(t7) - -ddr_read_sqsum_dvc: - li t7, KSEG1ADDR(DDR_DPLL3_ADDRESS) - lw t8, 0(t7) - li t9, DDR_DPLL3_SQSUM_DVC_MASK - and t8, t8, t9 - sra t8, t8, DDR_DPLL3_SQSUM_DVC_LSB - li t9, 0x40000 - subu t8, t8, t9 - bgez t8, ddr_pll_is_not_locked - nop - -pll_bypass_unset: - cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(0)); - cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(0)); - cpu_ddr_control_set (CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK, CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(0)); - -ddr_pll_dither_unset: - li t7, KSEG1ADDR(AR934X_DDR_PLL_DITHER); - sw t3, 0(t7); - -cpu_pll_dither_unset: - li t7, KSEG1ADDR(AR934X_CPU_PLL_DITHER); - sw t4, 0(t7); - - jr ra - nop diff --git a/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S b/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S new file mode 100755 index 0000000..cdab8a7 --- /dev/null +++ b/u-boot/cpu/mips/ar7240/qca95xx_pll_init.S @@ -0,0 +1,471 @@ +/* + * PLL and clocks configurations for + * Qualcomm/Atheros AR934x and QCA95xx WiSoCs + * + * Copyright (C) 2016 Piotr Dymacz + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +#define reg_oc_recovery t0 +#define reg_spi_ctrl_cfg t1 +#define reg_ref_clk_val t2 +#define reg_cpu_pll_cfg t3 +#define reg_ddr_pll_cfg t4 +#define reg_cpu_ddr_clk t5 +#define reg_cpu_pll_dit t6 +#define reg_ddr_pll_dit t7 + +/* Sanity check for O/C recovery button number */ +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN + #if (CONFIG_QCA_GPIO_OC_RECOVERY_BTN >= QCA_GPIO_COUNT) + #error "O/C recovery button number is not correct!" + #endif + + #define CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN \ + (1 << CONFIG_QCA_GPIO_OC_RECOVERY_BTN) +#endif + +.globl lowlevel_init +.type lowlevel_init, @function +.align 4 +.text +.ent lowlevel_init + +lowlevel_init: + +/* + * Get reference clock (XTAL) type, based on BOOTSTRAP register + * and save its value in one register for later use + */ + li reg_ref_clk_val, 25 + li t8, QCA_RST_BOOTSTRAP_REG + lw t9, 0(t8) + li t8, QCA_RST_BOOTSTRAP_REF_CLK_MASK + and t9, t9, t8 + bgtz t9, set_xtal_40mhz + nop + + b rtc_reset + nop + +set_xtal_40mhz: + li reg_ref_clk_val, 40 + +/* + * Reset RTC: + * 1. First reset RTC submodule using RST_RESET register + * 2. Then use RTC_SYNC_RESET register + * 3. And at the end, wait for ON_STATE bit set in RTC_SYNC_STATUS register + * + * TODO: do we need to reset RTC at all? + */ +rtc_reset: + li t8, QCA_RST_RST_REG + lw t9, 0(t8) + or t9, t9, QCA_RST_RESET_RTC_RST_MASK + sw t9, 0(t8) + nop + nop + + lw t9, 0(t8) + and t9, t9, ~QCA_RST_RESET_RTC_RST_MASK + sw t9, 0(t8) + nop + + li t8, QCA_RTC_SYNC_RST_REG + li t9, 0x0 + sw t9, 0(t8) + nop + nop + + li t9, QCA_RTC_SYNC_RST_RESET_MASK + sw t9, 0(t8) + nop + + li t8, QCA_RTC_SYNC_STATUS_REG + +rtc_wait_on: + lw t9, 0(t8) + and t9, t9, QCA_RTC_SYNC_STATUS_ON_MASK + beqz t9, rtc_wait_on + nop + +/* + * O/C recovery mode (start with safe PLL/clocks configuration): + * 1. Check if defined recovery button is pressed + * 2. Indicate recovery mode in predefined register + * 3. If in recovery mode, do not use PLL configuration from FLASH, + * because it is probably the reason why user is using recovery mode + */ +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN +is_oc_recovery_btn_pressed: + li reg_oc_recovery, 0 + li t8, QCA_GPIO_IN_REG + lw t9, 0(t8) + and t9, t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN + + #ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN_ACTIVE_LOW + bne t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN, in_oc_recovery_mode + nop + #else + beq t9, CONFIG_QCA_GPIO_MASK_OC_RECOVERY_BTN, in_oc_recovery_mode + nop + #endif + + #ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET + b is_pll_cfg_in_flash + #else + b xtal_type_check + #endif + nop + +in_oc_recovery_mode: + li reg_oc_recovery, 1 + b xtal_type_check + nop +#endif /* CONFIG_QCA_GPIO_OC_RECOVERY_BTN */ + +/* + * Check if PLL configuration is stored in FLASH: + * 1. Get 32-bit value from defined offset in FLASH + * 2. Compare it with predefined magic value + * 3. If values are not equal, continue default PLL/clocks configuration + * 4. If values are equal it means we should have target PLL/clocks register + * values stored in FLASH, just after magic value, in the following order: + * - SPI_CONTROL (offset 4) + * - CPU_PLL_CONFIG (offset 8) + * - DDR_PLL_CONFIG (offset 12) + * - CPU_DDR_CLOCK_CONTROL (offset 16) + * - CPU_PLL_DITHER (offset 20) + * - DDR_PLL_DITHER (offset 24) + * 5. After loading target values from FLASH, + * jump directly to PLL/clocks configuration + */ +#ifdef CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET +is_pll_cfg_in_flash: + li t8, CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET + lw t9, 0(t8) + bne t9, QCA_PLL_IN_FLASH_MAGIC, xtal_type_check + nop + +pll_cfg_in_flash: + lw reg_spi_ctrl_cfg, 4(t8) + lw reg_cpu_pll_cfg, 8(t8) + lw reg_ddr_pll_cfg, 12(t8) + lw reg_cpu_ddr_clk, 16(t8) + lw reg_cpu_pll_dit, 20(t8) + lw reg_ddr_pll_dit, 24(t8) + b cpu_ddr_clock_control + nop +#endif /* CONFIG_QCA_PLL_IN_FLASH_MAGIC_OFFSET */ + +/* + * Check XTAL type and include dedicated PLL/clocks values, + * predefined in header file, based on selected preset configuration + */ +xtal_type_check: + beq reg_ref_clk_val, 40, xtal_is_40mhz + nop + +xtal_is_25mhz: +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN + beq reg_oc_recovery, 1, xtal_is_25mhz_recovery + nop +#endif + + li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL + li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 + li reg_ddr_pll_cfg, QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 + li reg_cpu_ddr_clk, QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 + li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 + li reg_ddr_pll_dit, QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25 + b cpu_ddr_clock_control + nop + +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN +xtal_is_25mhz_recovery: + li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL_SAFE + li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25 + li reg_ddr_pll_cfg, QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL25 + li reg_cpu_ddr_clk, QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_SAFE_XTAL25 + li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL25 + li reg_ddr_pll_dit, QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL25 + b cpu_ddr_clock_control + nop +#endif + +xtal_is_40mhz: +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN + beq reg_oc_recovery, 1, xtal_is_40mhz_recovery + nop +#endif + + li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL + li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 + li reg_ddr_pll_cfg, QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 + li reg_cpu_ddr_clk, QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 + li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 + li reg_ddr_pll_dit, QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL40 + +#ifdef CONFIG_QCA_GPIO_OC_RECOVERY_BTN + b cpu_ddr_clock_control + nop + +xtal_is_40mhz_recovery: + li reg_spi_ctrl_cfg, QCA_SPI_CTRL_REG_VAL_SAFE + li reg_cpu_pll_cfg, QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40 + li reg_ddr_pll_cfg, QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL40 + li reg_cpu_ddr_clk, QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_SAFE_XTAL40 + li reg_cpu_pll_dit, QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL40 + li reg_ddr_pll_dit, QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL40 +#endif + +/* + * Load target value into CPU_DDR_CLOCK_CONTROL register, + * but for now keep bypass enabled for all clocks (CPU, DDR, AHB) + * (by default, after reset, they should be bypassed, do it just in case) + */ +cpu_ddr_clock_control: + li t8, QCA_PLL_CPU_DDR_CLK_CTRL_REG + move t9, reg_cpu_ddr_clk + or t9, t9, (QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK |\ + QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK |\ + QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK) + sw t9, 0(t8) + +/* + * Load target values into CPU/DDR_PLL_CONFIG registers, but for now keep PLLs down + * (by default, after reset, it should be powered down, do it just in case) + */ +cpu_pll_config: + li t8, QCA_PLL_CPU_PLL_CFG_REG + move t9, reg_cpu_pll_cfg + or t9, t9, QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK + sw t9, 0(t8) + +ddr_pll_config: + li t8, QCA_PLL_DDR_PLL_CFG_REG + move t9, reg_ddr_pll_cfg + or t9, t9, QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK + sw t9, 0(t8) + +/* Load target NFRAC_MIN values into CPU/DDR_PLL_DITHER registers */ +cpu_pll_dither: + li t8, QCA_PLL_CPU_PLL_DITHER_REG + lw t9, 0(t8) + and t9, t9, ~QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK + or t9, t9, reg_cpu_pll_dit + sw t9, 0(t8) + +ddr_pll_dither: + li t8, QCA_PLL_DDR_PLL_DITHER_REG + lw t9, 0(t8) + and t9, t9, ~QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK + or t9, t9, reg_ddr_pll_dit + sw t9, 0(t8) + +/* Disable PLL configuration over SRIF registers (just for sure) */ +cpu_pll_srif_disable: + li t8, QCA_PLL_SRIF_CPU_DPLL2_REG + lw t9, 0(t8) + and t9, t9, ~QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK + sw t9, 0(t8) + +ddr_pll_srif_disable: + li t8, QCA_PLL_SRIF_DDR_DPLL2_REG + lw t9, 0(t8) + and t9, t9, ~QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK + sw t9, 0(t8) + +/* Enable CPU PLL (only if we need it) and wait for update complete */ +cpu_pll_enable: + move t8, reg_cpu_pll_cfg + and t8, t8, QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK + bgtz t8, ddr_pll_enable + nop + li t8, QCA_PLL_CPU_PLL_CFG_REG + lw t9, 0(t8) + and t9, t9, ~QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK + sw t9, 0(t8) + nop + +/* Wait for CPU PLL update complete */ +cpu_pll_wait: + lw t9, 0(t8) + and t9, t9, QCA_PLL_CPU_PLL_CFG_UPDATING_MASK + bgtz t9, cpu_pll_wait + nop + +/* Enable DDR PLL (only if we need it) and wait for update complete */ +ddr_pll_enable: + move t8, reg_ddr_pll_cfg + and t8, t8, QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK + bgtz t8, pll_bypass_disable + nop + li t8, QCA_PLL_DDR_PLL_CFG_REG + lw t9, 0(t8) + and t9, t9, ~QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK + sw t9, 0(t8) + nop + +/* Wait for DDR PLL update complete */ +ddr_pll_wait: + lw t9, 0(t8) + and t9, t9, QCA_PLL_DDR_PLL_CFG_UPDATING_MASK + bgtz t9, ddr_pll_wait + nop + +/* Disable bypassing all clocks */ +pll_bypass_disable: + li t8, QCA_PLL_CPU_DDR_CLK_CTRL_REG + lw t9, 0(t8) + and t9, t9, ~(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK |\ + QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK |\ + QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK) + sw t9, 0(t8) + +/* Setup SPI (clock and other settings) */ +spi_setup: + +#ifdef CONFIG_QCA_PLL_SPI_FLASH_CLK_AUTO + /* + * Configure SPI FLASH and clock: + * 1. Check which PLL is used to drive AHB clock + * 2. Calculate selected PLL output value + * 3. Calculate target AHB clock value + * 4. Find minimum divider for SPI clock + * 5. Setup SPI FLASH clock and other related options (REMAP, etc.) + */ + li t8, QCA_PLL_CPU_DDR_CLK_CTRL_REG + lw t9, 0(t8) + + and t3, t9, QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK + srl t3, t3, QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT + /* t3 = AHB_POST_DIV + 1 */ + addi t3, t3, 1 + + /* Find out where AHB clock come from (CPU or DDR PLL) */ + and t9, t9, QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK + bgtz t9, ahb_clk_from_ddr_pll + nop + +ahb_clk_from_cpu_pll: + li t8, QCA_PLL_CPU_PLL_CFG_REG + lw t9, 0(t8) + + /* Calculate NINT */ + and t8, t9, QCA_PLL_CPU_PLL_CFG_NINT_MASK + srl t8, t8, QCA_PLL_CPU_PLL_CFG_NINT_SHIFT + mul t4, t8, reg_ref_clk_val /* t4 = REFCLK * NINT */ + + /* Calculate OUTDIV */ + and t8, t9, QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK + srl t8, t8, QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT + li t5, 1 + sllv t5, t5, t8 /* t5 = 2 ^ OUTDIV */ + + /* Calculate REFDIV */ + and t8, t9, QCA_PLL_CPU_PLL_CFG_REFDIV_MASK + srl t8, t8, QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT + mul t5, t8, t5 /* t5 = REDIV * (2 ^ OUTDIV) */ + nop + + b ahb_clk_calculation + nop + +ahb_clk_from_ddr_pll: + li t8, QCA_PLL_DDR_PLL_CFG_REG + lw t9, 0(t8) + + /* Calculate NINT */ + and t8, t9, QCA_PLL_DDR_PLL_CFG_NINT_MASK + srl t8, t8, QCA_PLL_DDR_PLL_CFG_NINT_SHIFT + mul t4, t8, reg_ref_clk_val /* t4 = REFCLK * NINT */ + + /* Calculate OUTDIV */ + and t8, t9, QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK + srl t8, t8, QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT + li t5, 1 + sllv t5, t5, t8 /* t5 = 2 ^ OUTDIV */ + + /* Calculate REFDIV */ + and t8, t9, QCA_PLL_DDR_PLL_CFG_REFDIV_MASK + srl t8, t8, QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT + mul t5, t8, t5 /* t5 = REDIV * (2 ^ OUTDIV) */ + nop + nop + +ahb_clk_calculation: + mul t5, t5, t3 /* t5 = REDIV * (2 ^ OUTDIV) * (AHB_POST_DIV + 1) */ + nop + nop + + /* Store AHB CLK in t3 */ + div t3, t4, t5 + + li t9, CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ + li t6, 0 /* t6 = CLOCK_DIVIDER for SPI FLASH clock */ + +/* Maximum SPI clock divider loop */ +spi_clk_calculation: + move t7, t6 + addi t7, t7, 1 + sll t7, t7, 1 /* t7 = 2 * (CLOCK_DIVIDER + 1) */ + div t4, t3, t7 /* t4 = SPI FLASH clock */ + sltu t5, t4, t9 /* t4 < t9 ? t5 = 1 : t5 = 0 */ + + /* SPI clock == target maximum clock? */ + beq t4, t9, spi_clk_setup + nop + + /* SPI clock < target maximum clock? */ + bgtz t5, spi_clk_setup + nop + + addi t6, t6, 1 + b spi_clk_calculation + nop + +spi_clk_setup: + sll t6, t6, QCA_SPI_CTRL_CLK_DIV_SHIFT + and reg_spi_ctrl_cfg, reg_spi_ctrl_cfg, ~QCA_SPI_CTRL_CLK_DIV_MASK + or reg_spi_ctrl_cfg, reg_spi_ctrl_cfg, t6 +#endif /* CONFIG_QCA_PLL_SPI_FLASH_CLK_AUTO */ + + li t8, QCA_SPI_CTRL_REG + sw reg_spi_ctrl_cfg, 0(t8) + and reg_spi_ctrl_cfg, reg_spi_ctrl_cfg, QCA_SPI_CTRL_REMAP_DIS_MASK + beqz reg_spi_ctrl_cfg, end + nop + +/* + * This is a small hack, needed after setting REMAP_DISABLE bit + * in SPI_CONTROL_ADDR register. + * + * Before that, SPI FLASH is mapped to 0x1FC00000, but just after + * setting REMAP_DISABLE bit, aliasing is disabled and SPI FLASH + * is mapped to 0x1F00000, so that the whole 16 MB address space + * could be used. + * + * That means, we need to "fix" return address, stored previously + * in $ra register, subtracting a value 0x00C00000 from it. + * + * Without that, jump would end up somewhere far away on FLASH... + */ + li t8, 0x00C00000 + subu ra, ra, t8 + +end: + jr ra + nop + +.end lowlevel_init diff --git a/u-boot/include/soc/ar933x_pll_init.h b/u-boot/include/soc/ar933x_pll_init.h new file mode 100644 index 0000000..8676999 --- /dev/null +++ b/u-boot/include/soc/ar933x_pll_init.h @@ -0,0 +1,200 @@ +/* + * Helper defines and macros related with + * PLL and clocks configurations for + * Qualcomm/Atheros AR933x WiSoC + * + * Copyright (C) 2016 Piotr Dymacz + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _AR933X_PLL_INIT_H_ +#define _AR933X_PLL_INIT_H_ + +#include + +/* CPU_PLL_CONFIG */ +#define _ar933x_cpu_pll_cfg_reg_val(_nint, \ + _refdiv, \ + _range, \ + _outdiv) \ + \ + ((_nint << QCA_PLL_CPU_PLL_CFG_NINT_SHIFT) & QCA_PLL_CPU_PLL_CFG_NINT_MASK) |\ + ((_refdiv << QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK) |\ + ((_range << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT) & QCA_PLL_CPU_PLL_CFG_RANGE_MASK) |\ + ((_outdiv << QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK) + +/* CPU_CLOCK_CONTROL */ +#define _ar933x_cpu_clk_ctrl_reg_val(_cpudiv, \ + _ddrdiv, \ + _ahbdiv) \ + \ + (((_cpudiv - 1) << QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT) &\ + QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK) |\ + (((_ddrdiv - 1) << QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT) &\ + QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK) |\ + (((_ahbdiv - 1) << QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT) &\ + QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK) + +/* PLL_DITHER_FRAC */ +#define _ar933x_cpu_pll_dither_frac_reg_val(_nfracmin) \ + ((_nfracmin << QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT) &\ + QCA_PLL_CPU_PLL_DITHER_FRAC_NFRAC_MIN_MASK) + +/* SPI_CONTROL_ADDR */ +#define _ar933x_spi_ctrl_addr_reg_val(_clk_div, \ + _remap_dis, \ + _reloc_spi) \ + \ + ((((_clk_div / 2) - 1) << QCA_SPI_CTRL_CLK_DIV_SHIFT) & QCA_SPI_CTRL_CLK_DIV_MASK) |\ + ((_remap_dis << QCA_SPI_CTRL_REMAP_DIS_SHIFT) & QCA_SPI_CTRL_REMAP_DIS_MASK) |\ + ((_reloc_spi << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) & QCA_SPI_CTRL_SPI_RELOCATE_MASK) + +/* + * ============================= + * PLL configuration preset list + * ============================= + */ +#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + + #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(4, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(5, 1, 1, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1) + + #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(7, 1, 1, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(12, 1, 1, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(820) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(8, 1, 1, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + + #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + + #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(6, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 2) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 2) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(24, 1, 0, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(15, 1, 0, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + + #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(10, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(28, 1, 0, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(17, 1, 0, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(512) + + #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(10, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _ar933x_cpu_pll_cfg_reg_val(40, 1, 0, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _ar933x_cpu_pll_cfg_reg_val(25, 1, 0, 1) + #define QCA_PLL_CPU_CLK_CTRL_REG_VAL_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) + + #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(10, 1, 0) + +#else + #error "QCA PLL configuration not supported or not selected!" +#endif + +/* + * Safe configuration, used in "O/C recovery" mode: + * CPU/DDR/AHB/SPI: 400/400/200/20 + */ +#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25 _ar933x_cpu_pll_cfg_reg_val(32, 1, 0, 1) +#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL25 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) +#define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(0) + +#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40 _ar933x_cpu_pll_cfg_reg_val(20, 1, 0, 1) +#define QCA_PLL_CPU_CLK_CTRL_REG_VAL_SAFE_XTAL40 _ar933x_cpu_clk_ctrl_reg_val(1, 1, 2) +#define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_SAFE_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(0) + +#define QCA_SPI_CTRL_REG_VAL_SAFE _ar933x_spi_ctrl_addr_reg_val(10, 1, 0) + +/* + * Default values (if not defined above) + */ + +/* Maximum clock for SPI NOR FLASH */ +#ifndef CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ + #define CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ 30 +#endif + +/* SPI_CONTROL_ADDR register value */ +#ifndef QCA_SPI_CTRL_REG_VAL + #define QCA_SPI_CTRL_REG_VAL _ar933x_spi_ctrl_addr_reg_val(8, 1, 0) +#endif + +/* CPU PLL dither register values */ +#ifndef QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 + #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL25 _ar933x_cpu_pll_dither_frac_reg_val(0) +#endif + +#ifndef QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 + #define QCA_PLL_CPU_PLL_DITHER_FRAC_REG_VAL_XTAL40 _ar933x_cpu_pll_dither_frac_reg_val(0) +#endif + +/* CPU PLL settle time */ +#define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL25 0x550 +#define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_REG_VAL_XTAL40 0x352 + +#endif /* _AR933X_PLL_INIT_H_ */ diff --git a/u-boot/include/soc/qca95xx_pll_init.h b/u-boot/include/soc/qca95xx_pll_init.h new file mode 100644 index 0000000..b8ea1e5 --- /dev/null +++ b/u-boot/include/soc/qca95xx_pll_init.h @@ -0,0 +1,1460 @@ +/* + * Helper defines and macros related with + * PLL and clocks configurations for + * Qualcomm/Atheros AR934x and QCA95xx WiSoCs + * + * Copyright (C) 2016 Piotr Dymacz + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _QCA95XX_PLL_INIT_H_ +#define _QCA95XX_PLL_INIT_H_ + +#include + +/* CPU_PLL_CONFIG */ +#define _qca95xx_cpu_pll_cfg_reg_val(_nint, \ + _refdiv, \ + _range, \ + _outdiv, \ + _dis) \ + \ + ((_nint << QCA_PLL_CPU_PLL_CFG_NINT_SHIFT) & QCA_PLL_CPU_PLL_CFG_NINT_MASK) |\ + ((_refdiv << QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_REFDIV_MASK) |\ + ((_range << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT) & QCA_PLL_CPU_PLL_CFG_RANGE_MASK) |\ + ((_outdiv << QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK) |\ + ((_dis << QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT) & QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK) + +/* DDR_PLL_CONFIG */ +#define _qca95xx_ddr_pll_cfg_reg_val(_nint, \ + _refdiv, \ + _range, \ + _outdiv, \ + _dis) \ + \ + ((_nint << QCA_PLL_DDR_PLL_CFG_NINT_SHIFT) & QCA_PLL_DDR_PLL_CFG_NINT_MASK) |\ + ((_refdiv << QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT) & QCA_PLL_DDR_PLL_CFG_REFDIV_MASK) |\ + ((_range << QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT) & QCA_PLL_DDR_PLL_CFG_RANGE_MASK) |\ + ((_outdiv << QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT) & QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK) |\ + ((_dis << QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT) & QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK) + +/* CPU_DDR_CLOCK_CONTROL */ +#define _qca95xx_cpu_ddr_clk_ctrl_reg_val(_cpudiv, \ + _ddrdiv, \ + _ahbdiv, \ + _cpu_from_cpupll, \ + _ddr_from_ddrpll, \ + _ahb_from_ddrpll) \ + \ + (((_cpudiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &\ + QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) |\ + (((_ddrdiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &\ + QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) |\ + (((_ahbdiv - 1) << QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &\ + QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) |\ + ((_cpu_from_cpupll << QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT) &\ + QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK) |\ + ((_ddr_from_ddrpll << QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT) &\ + QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK) |\ + ((_ahb_from_ddrpll << QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT) &\ + QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) + +/* CPU/DDR_PLL_DITHER */ +#define _qca95xx_cpu_pll_dither_reg_val(_nfracmin) \ + ((_nfracmin << QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT) &\ + QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK) + +#define _qca95xx_ddr_pll_dither_reg_val(_nfracmin) \ + ((_nfracmin << QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT) &\ + QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK) + +/* SPI_CONTROL_ADDR */ +#define _qca95xx_spi_ctrl_addr_reg_val(_clk_div, \ + _remap_dis, \ + _reloc_spi, \ + _tshsl_cnt) \ + \ + ((((_clk_div / 2) - 1) << QCA_SPI_CTRL_CLK_DIV_SHIFT) & QCA_SPI_CTRL_CLK_DIV_MASK) |\ + ((_remap_dis << QCA_SPI_CTRL_REMAP_DIS_SHIFT) & QCA_SPI_CTRL_REMAP_DIS_MASK) |\ + ((_reloc_spi << QCA_SPI_CTRL_SPI_RELOCATE_SHIFT) & QCA_SPI_CTRL_SPI_RELOCATE_MASK) |\ + ((_tshsl_cnt << QCA_SPI_CTRL_TSHSL_CNT_SHIFT) & QCA_SPI_CTRL_TSHSL_CNT_MASK) + +/* + * ============================= + * PLL configuration preset list + * ============================= + */ +#if (CONFIG_QCA_PLL == QCA_PLL_PRESET_25_25_12) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 8, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_25_25_25) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(1, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(1, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(4, 4, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_50_50_25) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_50_50_50) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(2, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_75_75_25) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 6, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_75_75_50) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_75_75_75) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_25) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_50) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_100_100_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_50_25) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_50_50) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_62_25) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 5, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 10, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_62_50) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(2, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 2, 1, 0, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_62_62) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 4, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_25) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_50) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_62) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 4, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_125_100_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 1, 1, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_75) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 3, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_150_150_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_160_160_80) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 1, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(26, 1, 0, 1, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 1, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 1, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_170_170_85) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(34, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(34, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(5, 5, 10, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(17, 1, 0, 1, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(17, 1, 0, 1, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_180_180_90) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 1, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 1, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_200_200_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_200_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_300_300_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_350_350_175) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(14, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(35, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(35, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_360_360_180) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(29, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(29, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(2, 2, 4, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(9, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(9, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_380_380_190) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(46, 3, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(46, 3, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(19, 1, 0, 1, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 1, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(6, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 0, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_200_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_300_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_400_400_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_200_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_250) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_300_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_400_250) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 0, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_250) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_500_500_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_200_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_275) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 2, 1, 1, 0) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_300_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_375_250) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(30, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(19, 1, 0, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_550_400_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_560_450_225) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(26) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(14, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_200_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(4, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_250) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 1, 1, 0, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_300_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_400_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_225) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_450_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_250) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_500_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_275) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_550_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(22, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(55, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 6, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_250) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 0, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_600_600_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 3, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_200_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(8, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(5, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_150) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 2, 3, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_300_300) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(12, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(15, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 1, 1, 1, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_155) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_400_310) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_100) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 5, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_155) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 4, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_166) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 1) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_206) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 3, 1, 1, 0) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_250) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_620_500_310) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(24, 1, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(20, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(52) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(31, 2, 1, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(25, 2, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 0) + + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(12, 1, 0, 2) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_400_200) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_420_210) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_ddr_pll_dither_reg_val(820) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(42, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16) + +#elif (CONFIG_QCA_PLL == QCA_PLL_PRESET_650_450_225) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(26, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(18, 1, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + + #define QCA_PLL_CPU_PLL_CFG_REG_VAL_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 0, 0, 0) + #define QCA_PLL_DDR_PLL_CFG_REG_VAL_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(45, 4, 1, 0, 0) + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(16) + +#else + #error "QCA PLL configuration not supported or not selected!" +#endif + +/* + * Safe configuration, used in "O/C recovery" mode: + * CPU/DDR/AHB/SPI: 400/400/200/20 + */ +#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL25 _qca95xx_cpu_pll_cfg_reg_val(16, 1, 1, 0, 0) +#define QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL25 _qca95xx_ddr_pll_cfg_reg_val(16, 1, 1, 0, 0) +#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_SAFE_XTAL25 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) +#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL25 _qca95xx_cpu_pll_dither_reg_val(0) +#define QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL25 _qca95xx_ddr_pll_dither_reg_val(0) + +#define QCA_PLL_CPU_PLL_CFG_REG_VAL_SAFE_XTAL40 _qca95xx_cpu_pll_cfg_reg_val(10, 1, 1, 0, 0) +#define QCA_PLL_DDR_PLL_CFG_REG_VAL_SAFE_XTAL40 _qca95xx_ddr_pll_cfg_reg_val(10, 1, 1, 0, 0) +#define QCA_PLL_CPU_DDR_CLK_CTRL_REG_VAL_SAFE_XTAL40 _qca95xx_cpu_ddr_clk_ctrl_reg_val(1, 1, 2, 1, 1, 1) +#define QCA_PLL_CPU_PLL_DITHER_REG_VAL_SAFE_XTAL40 _qca95xx_cpu_pll_dither_reg_val(0) +#define QCA_PLL_DDR_PLL_DITHER_REG_VAL_SAFE_XTAL40 _qca95xx_ddr_pll_dither_reg_val(0) + +#define QCA_SPI_CTRL_REG_VAL_SAFE _qca95xx_spi_ctrl_addr_reg_val(10, 1, 0, 2) + +/* + * Default values (if not defined above) + */ + +/* Maximum clock for SPI NOR FLASH */ +#ifndef CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ + #define CONFIG_QCA_SPI_NOR_FLASH_MAX_CLK_MHZ 30 +#endif + +/* SPI_CONTROL_ADDR register value */ +#ifndef QCA_SPI_CTRL_REG_VAL + #define QCA_SPI_CTRL_REG_VAL _qca95xx_spi_ctrl_addr_reg_val(8, 1, 0, 2) +#endif + +/* CPU PLL dither register values */ +#ifndef QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_cpu_pll_dither_reg_val(0) +#endif + +#ifndef QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 + #define QCA_PLL_CPU_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_cpu_pll_dither_reg_val(0) +#endif + +/* DDR PLL dither register values */ +#ifndef QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25 + #define QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL25 _qca95xx_ddr_pll_dither_reg_val(0) +#endif + +#ifndef QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL40 + #define QCA_PLL_DDR_PLL_DITHER_REG_VAL_XTAL40 _qca95xx_ddr_pll_dither_reg_val(0) +#endif + +#endif /* _QCA95XX_PLL_INIT_H_ */ diff --git a/u-boot/include/soc/qca_pll_list.h b/u-boot/include/soc/qca_pll_list.h new file mode 100644 index 0000000..81e7c92 --- /dev/null +++ b/u-boot/include/soc/qca_pll_list.h @@ -0,0 +1,139 @@ +/* + * List of predefined PLL configurations for Qualcomm/Atheros Wireless SOC + * + * Copyright (C) 2016 Piotr Dymacz + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef _QCA_PLL_LIST_H_ +#define _QCA_PLL_LIST_H_ + +#define QCA_PLL_PRESET_25_25_12 1 +#define QCA_PLL_PRESET_25_25_25 2 +#define QCA_PLL_PRESET_50_50_25 3 +#define QCA_PLL_PRESET_50_50_50 4 +#define QCA_PLL_PRESET_75_75_25 5 +#define QCA_PLL_PRESET_75_75_50 6 +#define QCA_PLL_PRESET_75_75_75 7 +#define QCA_PLL_PRESET_100_100_25 8 +#define QCA_PLL_PRESET_100_100_50 9 +#define QCA_PLL_PRESET_100_100_100 10 +#define QCA_PLL_PRESET_125_50_25 11 +#define QCA_PLL_PRESET_125_50_50 12 +#define QCA_PLL_PRESET_125_62_25 13 +#define QCA_PLL_PRESET_125_62_50 14 +#define QCA_PLL_PRESET_125_62_62 15 +#define QCA_PLL_PRESET_125_100_25 16 +#define QCA_PLL_PRESET_125_100_50 17 +#define QCA_PLL_PRESET_125_100_62 18 +#define QCA_PLL_PRESET_125_100_100 19 +#define QCA_PLL_PRESET_150_150_75 20 +#define QCA_PLL_PRESET_150_150_100 21 +#define QCA_PLL_PRESET_150_150_150 22 +#define QCA_PLL_PRESET_160_160_80 23 +#define QCA_PLL_PRESET_170_170_85 24 +#define QCA_PLL_PRESET_180_180_90 25 +#define QCA_PLL_PRESET_200_200_100 26 +#define QCA_PLL_PRESET_200_200_150 27 +#define QCA_PLL_PRESET_200_200_200 28 +#define QCA_PLL_PRESET_300_200_100 29 +#define QCA_PLL_PRESET_300_200_150 30 +#define QCA_PLL_PRESET_300_200_200 31 +#define QCA_PLL_PRESET_300_300_100 32 +#define QCA_PLL_PRESET_300_300_150 33 +#define QCA_PLL_PRESET_300_300_200 34 +#define QCA_PLL_PRESET_350_350_175 35 +#define QCA_PLL_PRESET_360_360_180 36 +#define QCA_PLL_PRESET_380_380_190 37 +#define QCA_PLL_PRESET_400_200_100 38 +#define QCA_PLL_PRESET_400_200_150 39 +#define QCA_PLL_PRESET_400_200_200 40 +#define QCA_PLL_PRESET_400_300_100 41 +#define QCA_PLL_PRESET_400_300_150 42 +#define QCA_PLL_PRESET_400_300_200 43 +#define QCA_PLL_PRESET_400_300_300 44 +#define QCA_PLL_PRESET_400_400_200 45 +#define QCA_PLL_PRESET_400_400_300 46 +#define QCA_PLL_PRESET_500_200_100 47 +#define QCA_PLL_PRESET_500_200_150 48 +#define QCA_PLL_PRESET_500_200_200 49 +#define QCA_PLL_PRESET_500_300_100 50 +#define QCA_PLL_PRESET_500_300_150 51 +#define QCA_PLL_PRESET_500_300_200 52 +#define QCA_PLL_PRESET_500_300_250 53 +#define QCA_PLL_PRESET_500_300_300 54 +#define QCA_PLL_PRESET_500_400_100 55 +#define QCA_PLL_PRESET_500_400_200 56 +#define QCA_PLL_PRESET_500_400_250 57 +#define QCA_PLL_PRESET_500_500_100 58 +#define QCA_PLL_PRESET_500_500_150 59 +#define QCA_PLL_PRESET_500_500_200 60 +#define QCA_PLL_PRESET_500_500_250 61 +#define QCA_PLL_PRESET_500_500_300 62 +#define QCA_PLL_PRESET_550_200_100 63 +#define QCA_PLL_PRESET_550_200_150 64 +#define QCA_PLL_PRESET_550_200_200 65 +#define QCA_PLL_PRESET_550_300_100 66 +#define QCA_PLL_PRESET_550_300_150 67 +#define QCA_PLL_PRESET_550_300_200 68 +#define QCA_PLL_PRESET_550_300_275 69 +#define QCA_PLL_PRESET_550_300_300 70 +#define QCA_PLL_PRESET_550_375_250 71 +#define QCA_PLL_PRESET_550_400_200 72 +#define QCA_PLL_PRESET_560_450_225 73 +#define QCA_PLL_PRESET_600_200_100 74 +#define QCA_PLL_PRESET_600_200_150 75 +#define QCA_PLL_PRESET_600_200_200 76 +#define QCA_PLL_PRESET_600_300_100 77 +#define QCA_PLL_PRESET_600_300_150 78 +#define QCA_PLL_PRESET_600_300_200 79 +#define QCA_PLL_PRESET_600_300_250 80 +#define QCA_PLL_PRESET_600_300_300 81 +#define QCA_PLL_PRESET_600_400_100 82 +#define QCA_PLL_PRESET_600_400_150 83 +#define QCA_PLL_PRESET_600_400_200 84 +#define QCA_PLL_PRESET_600_400_300 85 +#define QCA_PLL_PRESET_600_450_100 86 +#define QCA_PLL_PRESET_600_450_150 87 +#define QCA_PLL_PRESET_600_450_200 88 +#define QCA_PLL_PRESET_600_450_225 89 +#define QCA_PLL_PRESET_600_450_300 90 +#define QCA_PLL_PRESET_600_500_100 91 +#define QCA_PLL_PRESET_600_500_150 92 +#define QCA_PLL_PRESET_600_500_200 93 +#define QCA_PLL_PRESET_600_500_250 94 +#define QCA_PLL_PRESET_600_500_300 95 +#define QCA_PLL_PRESET_600_550_100 96 +#define QCA_PLL_PRESET_600_550_150 97 +#define QCA_PLL_PRESET_600_550_200 98 +#define QCA_PLL_PRESET_600_550_275 99 +#define QCA_PLL_PRESET_600_550_300 100 +#define QCA_PLL_PRESET_600_600_100 101 +#define QCA_PLL_PRESET_600_600_150 102 +#define QCA_PLL_PRESET_600_600_200 103 +#define QCA_PLL_PRESET_600_600_250 104 +#define QCA_PLL_PRESET_600_600_300 105 +#define QCA_PLL_PRESET_620_200_100 106 +#define QCA_PLL_PRESET_620_200_150 107 +#define QCA_PLL_PRESET_620_200_200 108 +#define QCA_PLL_PRESET_620_300_100 109 +#define QCA_PLL_PRESET_620_300_150 110 +#define QCA_PLL_PRESET_620_300_200 111 +#define QCA_PLL_PRESET_620_300_300 112 +#define QCA_PLL_PRESET_620_400_100 113 +#define QCA_PLL_PRESET_620_400_155 114 +#define QCA_PLL_PRESET_620_400_200 115 +#define QCA_PLL_PRESET_620_400_310 116 +#define QCA_PLL_PRESET_620_500_100 117 +#define QCA_PLL_PRESET_620_500_155 118 +#define QCA_PLL_PRESET_620_500_166 119 +#define QCA_PLL_PRESET_620_500_206 120 +#define QCA_PLL_PRESET_620_500_250 121 +#define QCA_PLL_PRESET_620_500_310 122 +#define QCA_PLL_PRESET_650_400_200 123 +#define QCA_PLL_PRESET_650_420_210 124 +#define QCA_PLL_PRESET_650_450_225 125 + + +#endif /* _QCA_PLL_LIST_H_ */ -- 2.25.1