From 2bc1b721807fabccea0dbd89a2d672161a44b095 Mon Sep 17 00:00:00 2001 From: Piotr Dymacz Date: Thu, 12 Nov 2015 22:56:23 +0100 Subject: [PATCH] Introduce new header files for SoC register defines As it turned out, most of QC/A WiSoC are very similar from register structures and addresses point of view. What's more, it seems that even when some registers or fields are slightly different in name, they still mean the same and work in exactly same way. So, instead of using approach from old Atheros SDK, where we have hundreds of different header files, for different chips, we will use only one. And in case of different address for the same register or different fields size/position, etc., we will use preprocessor and SOC_TYPE value. Add also MediaTek/Ralink headers file, we are going to fill it soon. --- u-boot/include/soc/mtk_soc_common.h | 14 + u-boot/include/soc/qca_soc_common.h | 893 ++++++++++++++++++++++++++++ u-boot/include/soc/soc_common.h | 89 +++ 3 files changed, 996 insertions(+) create mode 100644 u-boot/include/soc/mtk_soc_common.h create mode 100644 u-boot/include/soc/qca_soc_common.h create mode 100644 u-boot/include/soc/soc_common.h diff --git a/u-boot/include/soc/mtk_soc_common.h b/u-boot/include/soc/mtk_soc_common.h new file mode 100644 index 0000000..f1806b5 --- /dev/null +++ b/u-boot/include/soc/mtk_soc_common.h @@ -0,0 +1,14 @@ +/* + * MediaTek/Ralink Wireless SOC common registers definitions + * + * Copyright (C) 2014 Piotr Dymacz + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef _MTK_SOC_COMMON_H_ +#define _MTK_SOC_COMMON_H_ + +#include + +#endif /* _MTK_SOC_COMMON_H_ */ diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h new file mode 100644 index 0000000..51c50aa --- /dev/null +++ b/u-boot/include/soc/qca_soc_common.h @@ -0,0 +1,893 @@ +/* + * Qualcomm/Atheros Wireless SOC common registers definitions + * + * Copyright (C) 2014 Piotr Dymacz + * Copyright (C) 2008-2010 Atheros Communications Inc. + * + * Partially based on: + * Linux/arch/mips/include/asm/mach-ath79/ar71xx_regs.h + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef _QCA_SOC_COMMON_H_ +#define _QCA_SOC_COMMON_H_ + +#include + +/* + * Address map + */ +#define QCA_APB_BASE_REG 0x18000000 +#define QCA_FLASH_BASE_REG 0x1F000000 + +/* + * APB block + */ +#define QCA_DDR_CTRL_BASE_REG QCA_APB_BASE_REG + 0x00000000 + +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000 +#else + #define QCA_LSUART_BASE_REG QCA_APB_BASE_REG + 0x00020000 + #define QCA_HSUART_BASE_REG QCA_APB_BASE_REG + 0x00500000 +#endif + +#define QCA_USB_CFG_BASE_REG QCA_APB_BASE_REG + 0x00030000 +#define QCA_GPIO_BASE_REG QCA_APB_BASE_REG + 0x00040000 +#define QCA_PLL_BASE_REG QCA_APB_BASE_REG + 0x00050000 +#define QCA_RST_BASE_REG QCA_APB_BASE_REG + 0x00060000 +#define QCA_GMAC_BASE_REG QCA_APB_BASE_REG + 0x00070000 +#define QCA_RTC_BASE_REG QCA_APB_BASE_REG + 0x00107000 +#define QCA_PLL_SRIF_BASE_REG QCA_APB_BASE_REG + 0x00116000 + +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x00090000 +#elif (SOC_TYPE == QCA_AR9341_SOC || \ + SOC_TYPE == QCA_AR9344_SOC || \ + SOC_TYPE == QCA_AR9558_SOC) + #define QCA_SLIC_BASE_REG QCA_APB_BASE_REG + 0x000A9000 +#endif + +/* + * DDR registers + */ +#define QCA_DDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x000 +#define QCA_DDR_CFG2_REG QCA_DDR_CTRL_BASE_REG + 0x004 +#define QCA_DDR_MODE_REG QCA_DDR_CTRL_BASE_REG + 0x008 +#define QCA_DDR_EXTENDED_MODE_REG QCA_DDR_CTRL_BASE_REG + 0x00C +#define QCA_DDR_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x010 +#define QCA_DDR_REFRESH_REG QCA_DDR_CTRL_BASE_REG + 0x014 +#define QCA_DDR_RD_DATA_THIS_CYCLE_REG QCA_DDR_CTRL_BASE_REG + 0x018 +#define QCA_DDR_TAP_CTRL_0_REG QCA_DDR_CTRL_BASE_REG + 0x01C +#define QCA_DDR_TAP_CTRL_1_REG QCA_DDR_CTRL_BASE_REG + 0x020 + +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x07C + #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x080 + #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x084 +#else + #define QCA_DDR_WB_FLUSH_GE0_REG QCA_DDR_CTRL_BASE_REG + 0x09C + #define QCA_DDR_WB_FLUSH_GE1_REG QCA_DDR_CTRL_BASE_REG + 0x0A0 + #define QCA_DDR_WB_FLUSH_USB_REG QCA_DDR_CTRL_BASE_REG + 0x0A4 + #define QCA_DDR_WB_FLUSH_PCIE_REG QCA_DDR_CTRL_BASE_REG + 0x0A8 + #define QCA_DDR_WB_FLUSH_WMAC_REG QCA_DDR_CTRL_BASE_REG + 0x0AC + #define QCA_DDR_WB_FLUSH_SRC1_REG QCA_DDR_CTRL_BASE_REG + 0x0B0 + #define QCA_DDR_WB_FLUSH_SRC2_REG QCA_DDR_CTRL_BASE_REG + 0x0B4 +#endif + +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x08C + #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x090 + #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x094 + #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x098 + #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x09C + #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0A0 + #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0A4 + #define QCA_SDR_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0D8 +#else + #define QCA_DDR_DDR2_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x0B8 + #define QCA_DDR_EMR2_REG QCA_DDR_CTRL_BASE_REG + 0x0BC + #define QCA_DDR_EMR3_REG QCA_DDR_CTRL_BASE_REG + 0x0C0 + #define QCA_DDR_BURST_REG QCA_DDR_CTRL_BASE_REG + 0x0C4 + #define QCA_DDR_BURST2_REG QCA_DDR_CTRL_BASE_REG + 0x0C8 + #define QCA_AHB_MASTER_TOUT_MAX_REG QCA_DDR_CTRL_BASE_REG + 0x0CC + #define QCA_AHB_MASTER_TOUT_CURR_REG QCA_DDR_CTRL_BASE_REG + 0x0D0 + #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG QCA_DDR_CTRL_BASE_REG + 0x0D4 + #define QCA_DDR_CTRL_CFG_REG QCA_DDR_CTRL_BASE_REG + 0x108 + #define QCA_DDR_SELF_REFRESH_CTRL_REG QCA_DDR_CTRL_BASE_REG + 0x110 + #define QCA_DDR_SELF_REFRESH_TIMER_REG QCA_DDR_CTRL_BASE_REG + 0x114 + #define QCA_DDR_WMAC_FLUSH_REG QCA_DDR_CTRL_BASE_REG + 0x128 + #define QCA_DDR_CFG3_REG QCA_DDR_CTRL_BASE_REG + 0x15C +#endif + +/* + * Low-Speed UART registers + */ +#define QCA_LSUART_RBR_REG QCA_LSUART_BASE_REG + 0x00 +#define QCA_LSUART_THR_REG QCA_LSUART_BASE_REG + 0x00 +#define QCA_LSUART_DLL_REG QCA_LSUART_BASE_REG + 0x00 +#define QCA_LSUART_DLH_REG QCA_LSUART_BASE_REG + 0x04 +#define QCA_LSUART_IER_REG QCA_LSUART_BASE_REG + 0x04 +#define QCA_LSUART_IIR_REG QCA_LSUART_BASE_REG + 0x08 +#define QCA_LSUART_FCR_REG QCA_LSUART_BASE_REG + 0x08 +#define QCA_LSUART_LCR_REG QCA_LSUART_BASE_REG + 0x0C +#define QCA_LSUART_MCR_REG QCA_LSUART_BASE_REG + 0x10 +#define QCA_LSUART_LSR_REG QCA_LSUART_BASE_REG + 0x14 +#define QCA_LSUART_MSR_REG QCA_LSUART_BASE_REG + 0x18 + +/* + * Low-Speed UART registers BIT fields + */ + +/* RBR register (Receive buffer) */ +#define QCA_LSUART_RBR_RBR_SHIFT 0 +#define QCA_LSUART_RBR_RBR_MASK BITS(QCA_LSUART_RBR_RBR_SHIFT, 8) + +/* THR register (Transmit holding) */ +#define QCA_LSUART_THR_THR_SHIFT 0 +#define QCA_LSUART_THR_THR_MASK BITS(QCA_LSUART_THR_THR_SHIFT, 8) + +/* DLL register (Divisor latch low) */ +#define QCA_LSUART_DLL_DLL_SHIFT 0 +#define QCA_LSUART_DLL_DLL_MASK BITS(QCA_LSUART_DLL_DLL_SHIFT, 8) + +/* DLH register (Divisor latch high) */ +#define QCA_LSUART_DLH_DLH_SHIFT 0 +#define QCA_LSUART_DLH_DLH_MASK BITS(QCA_LSUART_DLH_DLH_SHIFT, 8) + +/* IER register (Interrupt enable) */ +#define QCA_LSUART_IER_ERBFI_SHIFT 0 +#define QCA_LSUART_IER_ERBFI_MASK (1 << QCA_LSUART_IER_ERBFI_SHIFT) +#define QCA_LSUART_IER_ETBEI_SHIFT 1 +#define QCA_LSUART_IER_ETBEI_MASK (1 << QCA_LSUART_IER_ETBEI_SHIFT) +#define QCA_LSUART_IER_ELSI_SHIFT 2 +#define QCA_LSUART_IER_ELSI_MASK (1 << QCA_LSUART_IER_ELSI_SHIFT) +#define QCA_LSUART_IER_EDDSI_SHIFT 3 +#define QCA_LSUART_IER_EDDSI_MASK (1 << QCA_LSUART_IER_EDDSI_SHIFT) + +/* IIR register (Interrupt identity) */ +#define QCA_LSUART_IIR_IID_SHIFT 0 +#define QCA_LSUART_IIR_IID_MASK BITS(QCA_LSUART_IIR_IID_SHIFT, 4) +#define QCA_LSUART_IIR_FIFO_STATUS_SHIFT 6 +#define QCA_LSUART_IIR_FIFO_STATUS_MASK BITS(QCA_LSUART_IIR_FIFO_STATUS_SHIFT, 2) + +/* FCR register (FIFO control) */ +#define QCA_LSUART_FCR_FIFO_EN_SHIFT 0 +#define QCA_LSUART_FCR_EDDSI_MASK (1 << QCA_LSUART_FCR_FIFO_EN_SHIFT) +#define QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT 1 +#define QCA_LSUART_FCR_RCVR_FIFO_RST_MASK (1 << QCA_LSUART_FCR_RCVR_FIFO_RST_SHIFT) +#define QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT 2 +#define QCA_LSUART_FCR_XMIT_FIFO_RST_MASK (1 << QCA_LSUART_FCR_XMIT_FIFO_RST_SHIFT) +#define QCA_LSUART_FCR_DMA_MODE_SHIFT 3 +#define QCA_LSUART_FCR_DMA_MODE_MASK (1 << QCA_LSUART_FCR_DMA_MODE_SHIFT) +#define QCA_LSUART_FCR_RCVR_TRIG_SHIFT 6 +#define QCA_LSUART_FCR_RCVR_TRIG_MASK BITS(QCA_LSUART_FCR_RCVR_TRIG_SHIFT, 2) + +/* LCR register (Line control) */ +#define QCA_LSUART_LCR_CLS_SHIFT 0 +#define QCA_LSUART_LCR_CLS_MASK BITS(QCA_LSUART_LCR_CLS_SHIFT, 2) +#define QCA_LSUART_LCR_CLS_5BIT_VAL 0x0 +#define QCA_LSUART_LCR_CLS_6BIT_VAL 0x1 +#define QCA_LSUART_LCR_CLS_7BIT_VAL 0x2 +#define QCA_LSUART_LCR_CLS_8BIT_VAL 0x3 +#define QCA_LSUART_LCR_STOP_SHIFT 2 +#define QCA_LSUART_LCR_STOP_MASK (1 << QCA_LSUART_LCR_STOP_SHIFT) +#define QCA_LSUART_LCR_PEN_SHIFT 3 +#define QCA_LSUART_LCR_PEN_MASK (1 << QCA_LSUART_LCR_PEN_SHIFT) +#define QCA_LSUART_LCR_EPS_SHIFT 4 +#define QCA_LSUART_LCR_EPS_MASK (1 << QCA_LSUART_LCR_EPS_SHIFT) +#define QCA_LSUART_LCR_BREAK_SHIFT 6 +#define QCA_LSUART_LCR_BREAK_MASK (1 << QCA_LSUART_LCR_BREAK_SHIFT) +#define QCA_LSUART_LCR_DLAB_SHIFT 7 +#define QCA_LSUART_LCR_DLAB_MASK (1 << QCA_LSUART_LCR_DLAB_SHIFT) + +/* MCR register (Modem control) */ +#define QCA_LSUART_MCR_DTR_SHIFT 0 +#define QCA_LSUART_MCR_DTR_MASK (1 << QCA_LSUART_MCR_DTR_SHIFT) +#define QCA_LSUART_MCR_RTS_SHIFT 1 +#define QCA_LSUART_MCR_RTS_MASK (1 << QCA_LSUART_MCR_RTS_SHIFT) +#define QCA_LSUART_MCR_OUT1_SHIFT 2 +#define QCA_LSUART_MCR_OUT1_MASK (1 << QCA_LSUART_MCR_OUT1_SHIFT) +#define QCA_LSUART_MCR_OUT2_SHIFT 3 +#define QCA_LSUART_MCR_OUT2_MASK (1 << QCA_LSUART_MCR_OUT2_SHIFT) +#define QCA_LSUART_MCR_LOOPBACK_SHIFT 5 +#define QCA_LSUART_MCR_LOOPBACK_MASK (1 << QCA_LSUART_MCR_LOOPBACK_SHIFT) + +/* LSR register (Line status) */ +#define QCA_LSUART_LSR_DR_SHIFT 0 +#define QCA_LSUART_LSR_DR_MASK (1 << QCA_LSUART_LSR_DR_SHIFT) +#define QCA_LSUART_LSR_OE_SHIFT 1 +#define QCA_LSUART_LSR_OE_MASK (1 << QCA_LSUART_LSR_OE_SHIFT) +#define QCA_LSUART_LSR_PE_SHIFT 2 +#define QCA_LSUART_LSR_PE_MASK (1 << QCA_LSUART_LSR_PE_SHIFT) +#define QCA_LSUART_LSR_FE_SHIFT 3 +#define QCA_LSUART_LSR_FE_MASK (1 << QCA_LSUART_LSR_FE_SHIFT) +#define QCA_LSUART_LSR_BI_SHIFT 4 +#define QCA_LSUART_LSR_BI_MASK (1 << QCA_LSUART_LSR_BI_SHIFT) +#define QCA_LSUART_LSR_THRE_SHIFT 5 +#define QCA_LSUART_LSR_THRE_MASK (1 << QCA_LSUART_LSR_THRE_SHIFT) +#define QCA_LSUART_LSR_TEMT_SHIFT 6 +#define QCA_LSUART_LSR_TEMT_MASK (1 << QCA_LSUART_LSR_TEMT_SHIFT) +#define QCA_LSUART_LSR_FERR_SHIFT 7 +#define QCA_LSUART_LSR_FERR_MASK (1 << QCA_LSUART_LSR_FERR_SHIFT) + +/* MCR register (Modem status) */ +#define QCA_LSUART_MCR_DCTS_SHIFT 0 +#define QCA_LSUART_MCR_DCTS_MASK (1 << QCA_LSUART_MCR_DCTS_SHIFT) +#define QCA_LSUART_MCR_DDSR_SHIFT 1 +#define QCA_LSUART_MCR_DDSR_MASK (1 << QCA_LSUART_MCR_DDSR_SHIFT) +#define QCA_LSUART_MCR_TERI_SHIFT 2 +#define QCA_LSUART_MCR_TERI_MASK (1 << QCA_LSUART_MCR_TERI_SHIFT) +#define QCA_LSUART_MCR_DDCD_SHIFT 3 +#define QCA_LSUART_MCR_DDCD_MASK (1 << QCA_LSUART_MCR_DDCD_SHIFT) +#define QCA_LSUART_MCR_CTS_SHIFT 4 +#define QCA_LSUART_MCR_CTS_MASK (1 << QCA_LSUART_MCR_CTS_SHIFT) +#define QCA_LSUART_MCR_DSR_SHIFT 5 +#define QCA_LSUART_MCR_DSR_MASK (1 << QCA_LSUART_MCR_DSR_SHIFT) +#define QCA_LSUART_MCR_RI_SHIFT 6 +#define QCA_LSUART_MCR_RI_MASK (1 << QCA_LSUART_MCR_RI_SHIFT) +#define QCA_LSUART_MCR_DCD_SHIFT 7 +#define QCA_LSUART_MCR_DCD_MASK (1 << QCA_LSUART_MCR_DCD_SHIFT) + +/* + * High-Speed UART registers + */ +#define QCA_HSUART_DATA_REG QCA_HSUART_BASE_REG + 0x00 +#define QCA_HSUART_CS_REG QCA_HSUART_BASE_REG + 0x04 +#define QCA_HSUART_CLK_REG QCA_HSUART_BASE_REG + 0x08 +#define QCA_HSUART_INT_REG QCA_HSUART_BASE_REG + 0x0C +#define QCA_HSUART_INT_EN_REG QCA_HSUART_BASE_REG + 0x10 + +/* + * High-Speed UART registers BIT fields + */ + +/* UART_DATA register (UART transmit and RX FIFO interface ) */ +#define QCA_HSUART_DATA_TX_RX_DATA_SHIFT 0 +#define QCA_HSUART_DATA_TX_RX_DATA_MASK BITS(QCA_HSUART_DATA_TX_RX_DATA_SHIFT, 8) +#define QCA_HSUART_DATA_RX_CSR_SHIFT 8 +#define QCA_HSUART_DATA_RX_CSR_MASK (1 << QCA_HSUART_DATA_RX_CSR_SHIFT) +#define QCA_HSUART_DATA_TX_CSR_SHIFT 9 +#define QCA_HSUART_DATA_TX_CSR_MASK (1 << QCA_HSUART_DATA_TX_CSR_SHIFT) + +/* UART_CS register (UART configuration and status) */ +#define QCA_HSUART_CS_PAR_MODE_SHIFT 0 +#define QCA_HSUART_CS_PAR_MODE_MASK BITS(QCA_HSUART_CS_PAR_MODE_SHIFT, 2) +#define QCA_HSUART_CS_PAR_MODE_NO_VAL 0x0 +#define QCA_HSUART_CS_PAR_MODE_ODD_VAL 0x2 +#define QCA_HSUART_CS_PAR_MODE_OVEN_VAL 0x3 +#define QCA_HSUART_CS_IFACE_MODE_SHIFT 2 +#define QCA_HSUART_CS_IFACE_MODE_MASK BITS(QCA_HSUART_CS_IFACE_MODE_SHIFT, 2) +#define QCA_HSUART_CS_IFACE_MODE_DISABLE_VAL 0x0 +#define QCA_HSUART_CS_IFACE_MODE_DTE_VAL 0x1 +#define QCA_HSUART_CS_IFACE_MODE_DCE_VAL 0x2 +#define QCA_HSUART_CS_FLOW_MODE_SHIFT 4 +#define QCA_HSUART_CS_FLOW_MODE_MASK BITS(QCA_HSUART_CS_FLOW_MODE_SHIFT, 2) +#define QCA_HSUART_CS_FLOW_MODE_NO_VAL 0x0 +#define QCA_HSUART_CS_FLOW_MODE_HW_VAL 0x2 +#define QCA_HSUART_CS_FLOW_MODE_INV_VAL 0x3 +#define QCA_HSUART_CS_DMA_EN_SHIFT 6 +#define QCA_HSUART_CS_DMA_EN_MASK (1 << QCA_HSUART_CS_DMA_EN_SHIFT) +#define QCA_HSUART_CS_RX_READY_ORIDE_SHIFT 7 +#define QCA_HSUART_CS_RX_READY_ORIDE_MASK (1 << QCA_HSUART_CS_RX_READY_ORIDE_SHIFT) +#define QCA_HSUART_CS_TX_READY_ORIDE_SHIFT 8 +#define QCA_HSUART_CS_TX_READY_ORIDE_MASK (1 << QCA_HSUART_CS_TX_READY_ORIDE_SHIFT) +#define QCA_HSUART_CS_TX_READY_SHIFT 9 +#define QCA_HSUART_CS_TX_READY_MASK (1 << QCA_HSUART_CS_TX_READY_SHIFT) +#define QCA_HSUART_CS_RX_BREAK_SHIFT 10 +#define QCA_HSUART_CS_RX_BREAK_MASK (1 << QCA_HSUART_CS_RX_BREAK_SHIFT) +#define QCA_HSUART_CS_TX_BREAK_SHIFT 11 +#define QCA_HSUART_CS_TX_BREAK_MASK (1 << QCA_HSUART_CS_TX_BREAK_SHIFT) +#define QCA_HSUART_CS_HOST_INT_SHIFT 12 +#define QCA_HSUART_CS_HOST_INT_MASK (1 << QCA_HSUART_CS_HOST_INT_SHIFT) +#define QCA_HSUART_CS_HOST_INT_EN_SHIFT 13 +#define QCA_HSUART_CS_HOST_INT_EN_MASK (1 << QCA_HSUART_CS_HOST_INT_EN_SHIFT) +#define QCA_HSUART_CS_TX_BUSY_SHIFT 14 +#define QCA_HSUART_CS_TX_BUSY_MASK (1 << QCA_HSUART_CS_TX_BUSY_SHIFT) +#define QCA_HSUART_CS_RX_BUSY_SHIFT 15 +#define QCA_HSUART_CS_RX_BUSY_MASK (1 << QCA_HSUART_CS_RX_BUSY_SHIFT) + +/* UART_CLOCK register (UART clock) */ +#define QCA_HSUART_CLK_STEP_SHIFT 0 +#define QCA_HSUART_CLK_STEP_MASK BITS(QCA_HSUART_CLK_STEP_SHIFT, 16) +#define QCA_HSUART_CLK_STEP_MAX_VAL 0x3333 +#define QCA_HSUART_CLK_SCALE_SHIFT 16 +#define QCA_HSUART_CLK_SCALE_MASK BITS(QCA_HSUART_CLK_SCALE_SHIFT, 8) +#define QCA_HSUART_CLK_SCALE_MAX_VAL 0xFF + +/* UART_INT register (UART interrupt/control status) */ +#define QCA_HSUART_INT_RX_VALID_SHIFT 0 +#define QCA_HSUART_INT_RX_VALID_MASK (1 << QCA_HSUART_INT_RX_VALID_SHIFT) +#define QCA_HSUART_INT_TX_READY_SHIFT 1 +#define QCA_HSUART_INT_TX_READY_MASK (1 << QCA_HSUART_INT_TX_READY_SHIFT) +#define QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT 2 +#define QCA_HSUART_INT_RX_FRAMING_ERR_MASK (1 << QCA_HSUART_INT_RX_FRAMING_ERR_SHIFT) +#define QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT 3 +#define QCA_HSUART_INT_RX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_RX_OVERFLOW_ERR_SHIFT) +#define QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT 4 +#define QCA_HSUART_INT_TX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_TX_OVERFLOW_ERR_SHIFT) +#define QCA_HSUART_INT_RX_PARITY_ERR_SHIFT 5 +#define QCA_HSUART_INT_RX_PARITY_ERR_MASK (1 << QCA_HSUART_INT_RX_PARITY_ERR_SHIFT) +#define QCA_HSUART_INT_RX_BREAK_ON_SHIFT 6 +#define QCA_HSUART_INT_RX_BREAK_ON_MASK (1 << QCA_HSUART_INT_RX_BREAK_ON_SHIFT) +#define QCA_HSUART_INT_RX_BREAK_OFF_SHIFT 7 +#define QCA_HSUART_INT_RX_BREAK_OFF_MASK (1 << QCA_HSUART_INT_RX_BREAK_OFF_SHIFT) +#define QCA_HSUART_INT_RX_FULL_SHIFT 8 +#define QCA_HSUART_INT_RX_FULL_MASK (1 << QCA_HSUART_INT_RX_FULL_SHIFT) +#define QCA_HSUART_INT_TX_EMPTY_SHIFT 9 +#define QCA_HSUART_INT_TX_EMPTY_MASK (1 << QCA_HSUART_INT_TX_EMPTY_SHIFT) + +/* UART_INT_EN register (UART interrupt enable) */ +#define QCA_HSUART_INT_EN_RX_VALID_SHIFT 0 +#define QCA_HSUART_INT_EN_RX_VALID_MASK (1 << QCA_HSUART_INT_EN_RX_VALID_SHIFT) +#define QCA_HSUART_INT_EN_TX_READY_SHIFT 1 +#define QCA_HSUART_INT_EN_TX_READY_MASK (1 << QCA_HSUART_INT_EN_TX_READY_SHIFT) +#define QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT 2 +#define QCA_HSUART_INT_EN_RX_FRAMING_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_FRAMING_ERR_SHIFT) +#define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT 3 +#define QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_OVERFLOW_ERR_SHIFT) +#define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT 4 +#define QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_MASK (1 << QCA_HSUART_INT_EN_TX_OVERFLOW_ERR_SHIFT) +#define QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT 5 +#define QCA_HSUART_INT_EN_RX_PARITY_ERR_MASK (1 << QCA_HSUART_INT_EN_RX_PARITY_ERR_SHIFT) +#define QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT 6 +#define QCA_HSUART_INT_EN_RX_BREAK_ON_MASK (1 << QCA_HSUART_INT_EN_RX_BREAK_ON_SHIFT) +#define QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT 7 +#define QCA_HSUART_INT_EN_RX_BREAK_OFF_MASK (1 << QCA_HSUART_INT_EN_RX_BREAK_OFF_SHIFT) +#define QCA_HSUART_INT_EN_RX_FULL_SHIFT 8 +#define QCA_HSUART_INT_EN_RX_FULL_MASK (1 << QCA_HSUART_INT_EN_RX_FULL_SHIFT) +#define QCA_HSUART_INT_EN_TX_EMPTY_SHIFT 9 +#define QCA_HSUART_INT_EN_TX_EMPTY_MASK (1 << QCA_HSUART_INT_EN_TX_EMPTY_SHIFT) + + +/* + * GPIO registers + */ +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_GPIO_COUNT 30 +#elif (SOC_TYPE == QCA_AR9341_SOC || SOC_TYPE == QCA_AR9344_SOC) + #define QCA_GPIO_COUNT 23 +#elif (SOC_TYPE == QCA_QCA9531_SOC || QCA_QCA9533_SOC) + #define QCA_GPIO_COUNT 18 +#elif (SOC_TYPE == QCA_QCA9558_SOC) + #define QCA_GPIO_COUNT 24 +#endif + +#define QCA_GPIO_OE_REG QCA_GPIO_BASE_REG + 0x00 +#define QCA_GPIO_IN_REG QCA_GPIO_BASE_REG + 0x04 +#define QCA_GPIO_OUT_REG QCA_GPIO_BASE_REG + 0x08 +#define QCA_GPIO_SET_REG QCA_GPIO_BASE_REG + 0x0C +#define QCA_GPIO_CLEAR_REG QCA_GPIO_BASE_REG + 0x10 +#define QCA_GPIO_INT_EN_REG QCA_GPIO_BASE_REG + 0x14 +#define QCA_GPIO_INT_TYPE_REG QCA_GPIO_BASE_REG + 0x18 +#define QCA_GPIO_INT_POLARITY_REG QCA_GPIO_BASE_REG + 0x1C +#define QCA_GPIO_INT_PENDING_REG QCA_GPIO_BASE_REG + 0x20 +#define QCA_GPIO_INT_MASK_REG QCA_GPIO_BASE_REG + 0x24 + +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_GPIO_FUNC_1_REG QCA_GPIO_BASE_REG + 0x28 + #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x2C + #define QCA_GPIO_FUNC_2_REG QCA_GPIO_BASE_REG + 0x30 + #define QCA_GPIO_WLAN_MUX_SET0_REG QCA_GPIO_BASE_REG + 0x34 + #define QCA_GPIO_WLAN_MUX_SET1_REG QCA_GPIO_BASE_REG + 0x38 + #define QCA_GPIO_WLAN_MUX_SET2_REG QCA_GPIO_BASE_REG + 0x3C + #define QCA_GPIO_WLAN_MUX_SET3_REG QCA_GPIO_BASE_REG + 0x40 +#else + #if (SOC_TYPE == QCA_QCA9558_SOC) + #define QCA_GPIO_SPARE_BITS_REG QCA_GPIO_BASE_REG + 0x28 + #else + #define QCA_GPIO_IN_ETH_SWITCH_LED_REG QCA_GPIO_BASE_REG + 0x28 + #endif + + #define QCA_GPIO_OUT_FUNC0_REG QCA_GPIO_BASE_REG + 0x2C + #define QCA_GPIO_OUT_FUNC1_REG QCA_GPIO_BASE_REG + 0x30 + #define QCA_GPIO_OUT_FUNC2_REG QCA_GPIO_BASE_REG + 0x34 + #define QCA_GPIO_OUT_FUNC3_REG QCA_GPIO_BASE_REG + 0x38 + #define QCA_GPIO_OUT_FUNC4_REG QCA_GPIO_BASE_REG + 0x3C + #define QCA_GPIO_OUT_FUNC5_REG QCA_GPIO_BASE_REG + 0x40 + #define QCA_GPIO_IN_EN0_REG QCA_GPIO_BASE_REG + 0x44 + #define QCA_GPIO_IN_EN1_REG QCA_GPIO_BASE_REG + 0x48 + #define QCA_GPIO_IN_EN2_REG QCA_GPIO_BASE_REG + 0x4C + #define QCA_GPIO_IN_EN3_REG QCA_GPIO_BASE_REG + 0x50 + #define QCA_GPIO_IN_EN4_REG QCA_GPIO_BASE_REG + 0x54 + #define QCA_GPIO_IN_EN9_REG QCA_GPIO_BASE_REG + 0x68 + #define QCA_GPIO_FUNC_REG QCA_GPIO_BASE_REG + 0x6C +#endif + +/* + * GPIO registers BIT fields + */ + +/* GPIO_FUNCTION_1 register (GPIO function) */ +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_GPIO_FUNC_1_EJTAG_DIS_SHIFT 0 + #define QCA_GPIO_FUNC_1_EJTAG_DIS_MASK (1 << QCA_GPIO_FUNC_1_EJTAG_DIS_SHIFT) + #define QCA_GPIO_FUNC_1_UART_EN_SHIFT 1 + #define QCA_GPIO_FUNC_1_UART_EN_MASK (1 << QCA_GPIO_FUNC_1_UART_EN_SHIFT) + #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT 2 + #define QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_MASK (1 << QCA_GPIO_FUNC_1_UART_RTS_CTS_EN_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT 3 + #define QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED0_EN_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED1_EN_SHIFT 4 + #define QCA_GPIO_FUNC_1_ETH_SW_LED1_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED1_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED2_SHIFT 5 + #define QCA_GPIO_FUNC_1_ETH_SW_LED2_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED2_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED3_SHIFT 6 + #define QCA_GPIO_FUNC_1_ETH_SW_LED3_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED3_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED4_SHIFT 7 + #define QCA_GPIO_FUNC_1_ETH_SW_LED4_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED4_SHIFT) + #define QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT 13 + #define QCA_GPIO_FUNC_1_SPI_CS_EN1_MASK (1 << QCA_GPIO_FUNC_1_SPI_CS_EN1_SHIFT) + #define QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT 14 + #define QCA_GPIO_FUNC_1_SPI_CS_EN2_MASK (1 << QCA_GPIO_FUNC_1_SPI_CS_EN2_SHIFT) + #define QCA_GPIO_FUNC_1_SPI_EN_SHIFT 18 + #define QCA_GPIO_FUNC_1_SPI_EN_MASK (1 << QCA_GPIO_FUNC_1_SPI_EN_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT 23 + #define QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_ACT_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT 24 + #define QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_COLL_SHIFT) + #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT 25 + #define QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_MASK (1 << QCA_GPIO_FUNC_1_ETH_SW_LED_DUPL_SHIFT) + #define QCA_GPIO_FUNC_1_I2S_EN_SHIFT 26 + #define QCA_GPIO_FUNC_1_I2S_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_EN_SHIFT) + #define QCA_GPIO_FUNC_1_I2S_MCK_EN_SHIFT 27 + #define QCA_GPIO_FUNC_1_I2S_MCK_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_MCK_EN_SHIFT) + #define QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT 29 + #define QCA_GPIO_FUNC_1_I2S_22_18_EN_MASK (1 << QCA_GPIO_FUNC_1_I2S_22_18_EN_SHIFT) + #define QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT 30 + #define QCA_GPIO_FUNC_1_SPDIF_EN_MASK (1 << QCA_GPIO_FUNC_1_SPDIF_EN_SHIFT) + #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT 31 + #define QCA_GPIO_FUNC_1_SPDIF_TCK_EN_MASK (1 << QCA_GPIO_FUNC_1_SPDIF_TCK_EN_SHIFT) +#endif + +/* + * PLL control registers + */ +#define QCA_PLL_CPU_PLL_CFG_REG QCA_PLL_BASE_REG + 0x00 + +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_PLL_CPU_PLL_CFG2_REG QCA_PLL_BASE_REG + 0x04 + #define QCA_PLL_CPU_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08 + #define QCA_PLL_PLL_DITHER_FRAC_REG QCA_PLL_BASE_REG + 0x10 + #define QCA_PLL_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x14 + #define QCA_PLL_ETHSW_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24 + #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C + #define QCA_PLL_USB_SUSPEND_REG QCA_PLL_BASE_REG + 0x40 + #define QCA_PLL_WLAN_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x44 +#else + #define QCA_PLL_DDR_PLL_CFG_REG QCA_PLL_BASE_REG + 0x04 + #define QCA_PLL_CPU_DDR_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x08 + + #if (SOC_TYPE == QCA_QCA9558_SOC) + #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x0C + #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x10 + #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x14 + #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x18 + #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x1C + #define QCA_PLL_SWITCH_CLK_SPARE_REG QCA_PLL_BASE_REG + 0x20 + #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x24 + #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x28 + #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x2C + #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x30 + #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x34 + #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x38 + #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x40 + #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44 + #define QCA_PLL_ETH_SGMII_CTRL_REG QCA_PLL_BASE_REG + 0x48 + #define QCA_PLL_ETH_SGMII_SERDES_REG QCA_PLL_BASE_REG + 0x4C + #define QCA_PLL_SLIC_PWM_DIV_REG QCA_PLL_BASE_REG + 0x50 + #else + #define QCA_PLL_CPU_SYNC_REG QCA_PLL_BASE_REG + 0x0C + #define QCA_PLL_PCIE_PLL_CFG_REG QCA_PLL_BASE_REG + 0x10 + #define QCA_PLL_PCIE_PLL_DITHER_DIV_MAX_REG QCA_PLL_BASE_REG + 0x14 + #define QCA_PLL_PCIE_PLL_DITHER_DIV_MIN_REG QCA_PLL_BASE_REG + 0x18 + #define QCA_PLL_PCIE_PLL_DITHER_STEP_REG QCA_PLL_BASE_REG + 0x1C + #define QCA_PLL_LDO_POWER_CTRL_REG QCA_PLL_BASE_REG + 0x20 + #define QCA_PLL_SWITCH_CLK_CTRL_REG QCA_PLL_BASE_REG + 0x24 + + #if (SOC_TYPE == QCA_AR9344_SOC) + #define QCA_PLL_CURR_PCIE_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28 + #else + #define QCA_PLL_CURR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x28 + #endif + + #define QCA_PLL_ETH_XMII_CTRL_REG QCA_PLL_BASE_REG + 0x2C + #define QCA_PLL_AUDIO_PLL_CFG_REG QCA_PLL_BASE_REG + 0x30 + #define QCA_PLL_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x34 + #define QCA_PLL_AUDIO_PLL_MODUL_STEP_REG QCA_PLL_BASE_REG + 0x38 + #define QCA_PLL_CURR_AUDIO_PLL_MODUL_REG QCA_PLL_BASE_REG + 0x3C + #define QCA_PLL_BB_PLL_CFG_REG QCA_PLL_BASE_REG + 0x40 + #define QCA_PLL_DDR_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x44 + #define QCA_PLL_CPU_PLL_DITHER_REG QCA_PLL_BASE_REG + 0x48 + #endif +#endif + + +/* + * PLL control registers BIT fields + */ + +/* CPU_PLL_CONFIG register (CPU phase lock loop configuration) */ +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0 + #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 10) + #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 10 + #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6) + #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 16 + #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5) + #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 21 + #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK (1 << QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT) + #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 23 + #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3) +#else + #define QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT 0 + #define QCA_PLL_CPU_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_CPU_PLL_CFG_NFRAC_SHIFT, 6) + #define QCA_PLL_CPU_PLL_CFG_NINT_SHIFT 6 + #define QCA_PLL_CPU_PLL_CFG_NINT_MASK BITS(QCA_PLL_CPU_PLL_CFG_NINT_SHIFT, 6) + #define QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT 12 + #define QCA_PLL_CPU_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_REFDIV_SHIFT, 5) + #define QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT 17 + #define QCA_PLL_CPU_PLL_CFG_RANGE_MASK BITS(QCA_PLL_CPU_PLL_CFG_RANGE_SHIFT, 2) + #define QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT 19 + #define QCA_PLL_CPU_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_CPU_PLL_CFG_OUTDIV_SHIFT, 3) +#endif + +#define QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT 30 +#define QCA_PLL_CPU_PLL_CFG_PLLPWD_MASK (1 << QCA_PLL_CPU_PLL_CFG_PLLPWD_SHIFT) +#define QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT 31 +#define QCA_PLL_CPU_PLL_CFG_UPDATING_MASK (1 << QCA_PLL_CPU_PLL_CFG_UPDATING_SHIFT) + +/* CPU_PLL_CONFIG2 register (CPU phase lock loop configuration, AR933x only) */ +#define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT 0 +#define QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_MASK BITS(QCA_PLL_CPU_PLL_CFG2_SETTLE_TIME_SHIFT, 12) + +/* CPU_CLOCK_CONTROL register (CPU clock control, AR933x only) */ +#define QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT 2 +#define QCA_PLL_CPU_CLK_CTRL_BYPASS_MASK (1 << QCA_PLL_CPU_CLK_CTRL_BYPASS_SHIFT) +#define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_CPU_POST_DIV_SHIFT, 2) +#define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_DDR_POST_DIV_SHIFT, 2) +#define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_CLK_CTRL_AHB_POST_DIV_SHIFT, 2) + +/* PLL_DITHER_FRAC register (CPU PLL dither FRAC, AR933x only) */ +#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT 0 +#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_MAX_MASK BITS(QCA_PLL_PLL_DITHER_FRAC_NFRAC_MAX_SHIFT, 10) +#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT 10 +#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_MIN_MASK BITS(QCA_PLL_PLL_DITHER_FRAC_NFRAC_MIN_SHIFT, 10) +#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT 10 +#define QCA_PLL_PLL_DITHER_FRAC_NFRAC_STEP_MASK BITS(QCA_PLL_PLL_DITHER_FRAC_NFRAC_STEP_SHIFT, 20) + +/* PLL_DITHER register (CPU PLL dither, AR933x only) */ +#define QCA_PLL_PLL_DITHER_UPDATE_CNT_SHIFT 0 +#define QCA_PLL_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_PLL_DITHER_UPDATE_CNT_SHIFT, 14) +#define QCA_PLL_PLL_DITHER_DITHER_EN_SHIFT 31 +#define QCA_PLL_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_PLL_DITHER_DITHER_EN_SHIFT) + +/* ETHSW_CLOCK_CONTROL register (Ethernet switch clock control, AR933x only) */ +#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLL_PWD_SHIFT 3 +#define QCA_PLL_ETHSW_CLK_CTRL_CORE_PLL_PWD_MASK (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_PLL_PWD_SHIFT) +#define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT 4 +#define QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_MASK (1 << QCA_PLL_ETHSW_CLK_CTRL_CORE_BIAS_EN_SHIFT) + +/* ETH_XMII_CONTROL register (Ethernet XMII control) */ +#define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT 0 +#define QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE0_CNT_SHIFT, 8) +#define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT 8 +#define QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_PHASE1_CNT_SHIFT, 8) +#define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT 16 +#define QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_MASK BITS(QCA_PLL_ETH_XMII_CTRL_OFFSET_CNT_SHIFT, 8) +#define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT 24 +#define QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_MASK (1 << QCA_PLL_ETH_XMII_CTRL_OFFSET_PHASE_SHIFT) +#define QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT 25 +#define QCA_PLL_ETH_XMII_CTRL_GIGE_MASK (1 << QCA_PLL_ETH_XMII_CTRL_GIGE_SHIFT) +#define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT 26 +#define QCA_PLL_ETH_XMII_CTRL_TX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_TX_DELAY_SHIFT, 2) +#define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT 28 +#define QCA_PLL_ETH_XMII_CTRL_RX_DELAY_MASK BITS(QCA_PLL_ETH_XMII_CTRL_RX_DELAY_SHIFT, 2) +#define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT 30 +#define QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_MASK (1 << QCA_PLL_ETH_XMII_CTRL_GIGE_QUAD_SHIFT) +#define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT 31 +#define QCA_PLL_ETH_XMII_CTRL_TX_INVERT_MASK (1 << QCA_PLL_ETH_XMII_CTRL_TX_INVERT_SHIFT) + +/* SUSPEND register (USB suspend, AR933x only) */ +#define QCA_PLL_USB_SUSPEND_EN_SHIFT 0 +#define QCA_PLL_USB_SUSPEND_EN_MASK (1 << QCA_PLL_USB_SUSPEND_EN_SHIFT) +#define QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT 8 +#define QCA_PLL_USB_SUSPEND_RESTART_TIME_MASK BITS(QCA_PLL_USB_SUSPEND_RESTART_TIME_SHIFT, 20) + +/* WLAN_CLOCK_CONTROL register (WLAN clock control, AR933x only) */ +#define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT 0 +#define QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLK_CTL_MASK_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT 1 +#define QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_PWDN_CTL_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT 2 +#define QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLKIN_CTL_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_PLL_PWD_CTL_SHIFT 3 +#define QCA_PLL_WLAN_CLK_CTRL_PLL_PWD_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_PLL_PWD_CTL_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT 4 +#define QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_GLBL_CLK_EN_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT 8 +#define QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_WLANRST_CTL_MASK_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT 9 +#define QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_CLKGEN_COLD_RST_CTL_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT 10 +#define QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_RADIO_COLD_RST_CTL_SHIFT) +#define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT 12 +#define QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_MASK (1 << QCA_PLL_WLAN_CLK_CTRL_UART_CLK88_SHIFT) + +/* DDR_PLL_CONFIG register (DDR PLL configuration) */ +#define QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT 0 +#define QCA_PLL_DDR_PLL_CFG_NFRAC_MASK BITS(QCA_PLL_DDR_PLL_CFG_NFRAC_SHIFT, 10) +#define QCA_PLL_DDR_PLL_CFG_NINT_SHIFT 10 +#define QCA_PLL_DDR_PLL_CFG_NINT_MASK BITS(QCA_PLL_DDR_PLL_CFG_NINT_SHIFT, 6) +#define QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT 16 +#define QCA_PLL_DDR_PLL_CFG_REFDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_REFDIV_SHIFT, 5) +#define QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT 21 +#define QCA_PLL_DDR_PLL_CFG_RANGE_MASK BITS(QCA_PLL_DDR_PLL_CFG_RANGE_SHIFT, 2) +#define QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT 23 +#define QCA_PLL_DDR_PLL_CFG_OUTDIV_MASK BITS(QCA_PLL_DDR_PLL_CFG_OUTDIV_SHIFT, 3) +#define QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT 30 +#define QCA_PLL_DDR_PLL_CFG_PLLPWD_MASK (1 << QCA_PLL_DDR_PLL_CFG_PLLPWD_SHIFT) +#define QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT 31 +#define QCA_PLL_DDR_PLL_CFG_UPDATING_MASK (1 << QCA_PLL_DDR_PLL_CFG_UPDATING_SHIFT) + +/* CPU_DDR_CLOCK_CONTROL register (CPU DDR clock control) */ +#define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT 1 +#define QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_RST_SWITCH_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT 2 +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT 3 +#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT 4 +#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT, 5) +#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT, 5) +#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK BITS(QCA_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT, 5) +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT 20 +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT 21 +#define QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT 22 +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_ASRT_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT 23 +#define QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_CPU_RST_EN_BP_DEASRT_SHIFT) +#define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT 24 +#define QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK (1 << QCA_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SHIFT) + +/* DDR_PLL_DITHER register (DDR PLL dither parameter) */ +#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT 0 +#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MAX_SHIFT, 10) +#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT 10 +#define QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 10) +#define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_SHIFT 20 +#define QCA_PLL_DDR_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_DDR_PLL_DITHER_NFRAC_MIN_SHIFT, 7) +#define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT 27 +#define QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_DDR_PLL_DITHER_UPDATE_CNT_SHIFT, 4) +#define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT 31 +#define QCA_PLL_DDR_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_DDR_PLL_DITHER_DITHER_EN_SHIFT) + +#if (SOC_TYPE == QCA_AR933X_SOC) + /* PLL_DITHER_FRAC register (CPU PLL dither FRAC) */ + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT 0 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 10) + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT 10 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 10) + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 20 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 10) + + /* PLL_DITHER register (CPU PLL dither) */ + #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 0 + #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 14) + #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31 + #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT) +#else + /* CPU_PLL_DITHER register (CPU PLL dither parameter) */ + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT 0 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MAX_SHIFT, 6) + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT 6 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6) + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_SHIFT 12 + #define QCA_PLL_CPU_PLL_DITHER_NFRAC_STEP_MASK BITS(QCA_PLL_CPU_PLL_DITHER_NFRAC_MIN_SHIFT, 6) + #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT 18 + #define QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_MASK BITS(QCA_PLL_CPU_PLL_DITHER_UPDATE_CNT_SHIFT, 6) + #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT 31 + #define QCA_PLL_CPU_PLL_DITHER_DITHER_EN_MASK (1 << QCA_PLL_CPU_PLL_DITHER_DITHER_EN_SHIFT) +#endif + +/* + * PLL SRIF registers (not available in AR933x) + */ +#define QCA_PLL_SRIF_CPU_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x1C0 +#define QCA_PLL_SRIF_CPU_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x1C4 +#define QCA_PLL_SRIF_CPU_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x1C8 +#define QCA_PLL_SRIF_AUD_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x200 +#define QCA_PLL_SRIF_AUD_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x204 +#define QCA_PLL_SRIF_AUD_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x208 +#define QCA_PLL_SRIF_DDR_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0x240 +#define QCA_PLL_SRIF_DDR_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0x244 +#define QCA_PLL_SRIF_DDR_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0x248 +#define QCA_PLL_SRIF_PCIE_DPLL1_REG QCA_PLL_SRIF_BASE_REG + 0xC00 +#define QCA_PLL_SRIF_PCIE_DPLL2_REG QCA_PLL_SRIF_BASE_REG + 0xC04 +#define QCA_PLL_SRIF_PCIE_DPLL3_REG QCA_PLL_SRIF_BASE_REG + 0xC08 + +/* + * PLL SRIF registers BIT fields (not available in AR933x) + */ + +/* DPLL1 (common for CPU, AUD, DDR and PCIE) */ +#define QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT 0 +#define QCA_PLL_SRIF_DPLL1_NFRAC_MASK BITS(QCA_PLL_SRIF_DPLL1_NFRAC_SHIFT, 18) +#define QCA_PLL_SRIF_DPLL1_NINT_SHIFT 18 +#define QCA_PLL_SRIF_DPLL1_NINT_MASK BITS(QCA_PLL_SRIF_DPLL1_NINT_SHIFT, 9) +#define QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT 27 +#define QCA_PLL_SRIF_DPLL1_REFDIV_MASK BITS(QCA_PLL_SRIF_DPLL1_REFDIV_SHIFT, 5) + +/* DPLL2 (common for CPU, AUD, DDR and PCIE) */ +#define QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define QCA_PLL_SRIF_DPLL2_OUTDIV_MASK BITS(QCA_PLL_SRIF_DPLL2_OUTDIV_SHIFT, 2) +#define QCA_PLL_SRIF_DPLL2_PLL_PWD_SHIFT 16 +#define QCA_PLL_SRIF_DPLL2_PLL_PWD_MASK (1 << QCA_PLL_SRIF_DPLL2_PLL_PWD_SHIFT) +#define QCA_PLL_SRIF_DPLL2_KD_SHIFT 19 +#define QCA_PLL_SRIF_DPLL2_KD_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 7) +#define QCA_PLL_SRIF_DPLL2_KI_SHIFT 26 +#define QCA_PLL_SRIF_DPLL2_KI_MASK BITS(QCA_PLL_SRIF_DPLL2_KD_SHIFT, 4) +#define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT 30 +#define QCA_PLL_SRIF_DPLL2_LOCAL_PLL_MASK (1 << QCA_PLL_SRIF_DPLL2_LOCAL_PLL_SHIFT) +#define QCA_PLL_SRIF_DPLL2_RANGE_SHIFT 31 +#define QCA_PLL_SRIF_DPLL2_RANGE_MASK (1 << QCA_PLL_SRIF_DPLL2_RANGE_SHIFT) + +/* DPLL3 (common for CPU, AUD, DDR and PCIE) */ +#define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT 23 +#define QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_MASK BITS(QCA_PLL_SRIF_DPLL3_PHASE_SHIFT_SHIFT, 7) + +/* + * Reset control registers + */ +#define QCA_RST_GENERAL_TIMER1_REG QCA_RST_BASE_REG + 0x00 +#define QCA_RST_GENERAL_TIMER1_RELOAD_REG QCA_RST_BASE_REG + 0x04 +#define QCA_RST_WATCHDOG_TIMER_CTRL_REG QCA_RST_BASE_REG + 0x08 +#define QCA_RST_WATCHDOG_TIMER_REG QCA_RST_BASE_REG + 0x0C +#define QCA_RST_MISC_INTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x10 +#define QCA_RST_MISC_INTERRUPT_MASK_REG QCA_RST_BASE_REG + 0x14 +#define QCA_RST_GLOBALINTERRUPT_STATUS_REG QCA_RST_BASE_REG + 0x18 +#define QCA_RST_RST_REG QCA_RST_BASE_REG + 0x1C +#define QCA_RST_REVISION_ID_REG QCA_RST_BASE_REG + 0x90 +#define QCA_RST_GENERAL_TIMER2_REG QCA_RST_BASE_REG + 0x94 +#define QCA_RST_GENERAL_TIMER2_RELOAD_REG QCA_RST_BASE_REG + 0x98 +#define QCA_RST_GENERAL_TIMER3_REG QCA_RST_BASE_REG + 0x9C +#define QCA_RST_GENERAL_TIMER3_RELOAD_REG QCA_RST_BASE_REG + 0xA0 +#define QCA_RST_GENERAL_TIMER4_REG QCA_RST_BASE_REG + 0xA4 +#define QCA_RST_GENERAL_TIMER4_RELOAD_REG QCA_RST_BASE_REG + 0xA8 + +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xAC +#else + #define QCA_RST_BOOTSTRAP_REG QCA_RST_BASE_REG + 0xB0 +#endif + +/* + * Reset control registers BIT fields + */ + +/* RST_BOOTSTRAP (Reset bootstrap) */ +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 0 +#else + #define QCA_RST_BOOTSTRAP_REF_CLK_SHIFT 4 +#endif +#define QCA_RST_BOOTSTRAP_REF_CLK_MASK (1 << QCA_RST_BOOTSTRAP_REF_CLK_SHIFT) +#define QCA_RST_BOOTSTRAP_REF_CLK_25M_VAL 0x0 +#define QCA_RST_BOOTSTRAP_REF_CLK_40M_VAL 0x1 + +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 12 + #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2) + #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 0 + #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1 + #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 2 +#else + #define QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT 0 + + /* v2 does not support SDR, but we can read reserved bit and make it universal */ + #if (SOC_TYPE == QCA_QCA9531_SOC || QCA_QCA9533_SOC) + #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK BITS(QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT, 2) + #else + #define QCA_RST_BOOTSTRAP_MEM_TYPE_MASK (1 << QCA_RST_BOOTSTRAP_MEM_TYPE_SHIFT) + #endif + + #define QCA_RST_BOOTSTRAP_MEM_TYPE_SDR_VAL 3 + #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR1_VAL 1 + #define QCA_RST_BOOTSTRAP_MEM_TYPE_DDR2_VAL 0 +#endif + +/* RST_REVISION_ID (Chip revision ID) */ +#define QCA_RST_REVISION_ID_MAJOR_SHIFT 4 +#define QCA_RST_REVISION_ID_MAJOR_MASK BITS(QCA_RST_REVISION_ID_MAJOR_SHIFT, 12) + +#if (SOC_TYPE == QCA_AR933X_SOC) + #define QCA_RST_REVISION_ID_REV_SHIFT 0 + #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 2) +#else + #define QCA_RST_REVISION_ID_REV_SHIFT 0 + #define QCA_RST_REVISION_ID_REV_MASK BITS(QCA_RST_REVISION_ID_REV_SHIFT, 4) +#endif + +#define QCA_RST_REVISION_ID_MAJOR_AR9330_VAL 0x0110 +#define QCA_RST_REVISION_ID_MAJOR_AR9331_VAL 0x1110 +#define QCA_RST_REVISION_ID_MAJOR_AR9341_VAL 0x0120 +#define QCA_RST_REVISION_ID_MAJOR_AR9344_VAL 0x2120 +#define QCA_RST_REVISION_ID_MAJOR_QCA9531_VAL 0x0140 +#define QCA_RST_REVISION_ID_MAJOR_QCA9533_VAL 0x0140 +#define QCA_RST_REVISION_ID_MAJOR_QCA9533_V2_VAL 0x0160 +#define QCA_RST_REVISION_ID_MAJOR_QCA9558_VAL 0x1130 + + +/* + * SPI serial flash registers + */ +#define QCA_SPI_FUNC_SEL_REG QCA_FLASH_BASE_REG + 0x00 +#define QCA_SPI_CTRL_REG QCA_FLASH_BASE_REG + 0x04 +#define QCA_SPI_IO_CTRL_REG QCA_FLASH_BASE_REG + 0x08 +#define QCA_SPI_READ_DATA_REG QCA_FLASH_BASE_REG + 0x0C +#define QCA_SPI_SHIFT_DATAOUT_REG QCA_FLASH_BASE_REG + 0x10 +#define QCA_SPI_SHIFT_CNT_REG QCA_FLASH_BASE_REG + 0x14 +#define QCA_SPI_SHIFT_DATAIN_REG QCA_FLASH_BASE_REG + 0x18 + +/* + * SPI serial flash registers BIT fields + */ + +/* SPI_FUNC_SELECT register (SPI function select) */ +#define QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT 0 +#define QCA_SPI_FUNC_SEL_FUNC_SEL_MASK (1 << QCA_SPI_FUNC_SEL_FUNC_SEL_SHIFT) + +/* SPI_CONTROL register (SPI control) */ +#define QCA_SPI_CTRL_CLK_DIV_SHIFT 0 +#define QCA_SPI_CTRL_CLK_DIV_MASK BITS(QCA_SPI_CTRL_CLK_DIV_SHIFT, 6) +#define QCA_SPI_CTRL_REMAP_DIS_SHIFT 6 +#define QCA_SPI_CTRL_REMAP_DIS_MASK (1 << QCA_SPI_CTRL_REMAP_DIS_SHIFT) + +/* SPI_IO_CONTROL register (SPI I/O control) */ +#define QCA_SPI_IO_CTRL_IO_DO_SHIFT 0 +#define QCA_SPI_IO_CTRL_IO_DO_MASK (1 << QCA_SPI_IO_CTRL_IO_DO_SHIFT) +#define QCA_SPI_IO_CTRL_IO_CLK_SHIFT 8 +#define QCA_SPI_IO_CTRL_IO_CLK_MASK (1 << QCA_SPI_IO_CTRL_IO_CLK_SHIFT) +#define QCA_SPI_IO_CTRL_IO_CS0_SHIFT 16 +#define QCA_SPI_IO_CTRL_IO_CS0_MASK (1 << QCA_SPI_IO_CTRL_IO_CS0_SHIFT) +#define QCA_SPI_IO_CTRL_IO_CS1_SHIFT 17 +#define QCA_SPI_IO_CTRL_IO_CS1_MASK (1 << QCA_SPI_IO_CTRL_IO_CS1_SHIFT) +#define QCA_SPI_IO_CTRL_IO_CS2_SHIFT 18 +#define QCA_SPI_IO_CTRL_IO_CS2_MASK (1 << QCA_SPI_IO_CTRL_IO_CS2_SHIFT) + + + +/* + * Functions + */ +#ifndef __ASSEMBLY__ +inline u32 qca_xtal_is_40mhz(void); +inline u32 qca_mem_type(void); +void qca_soc_name_rev(char *buf); +void qca_sys_clocks(u32 *cpu_clk, u32 *ddr_clk, u32 *ahb_clk, u32 *spi_clk, u32 *ref_clk); +void qca_spi_flash_sector_erase(u32 address); +#endif /* !__ASSEMBLY__ */ + +/* + * Read, write, set and clear macros + */ +#define qca_soc_reg_read(_addr) *(volatile unsigned int *)(KSEG1ADDR(_addr)) +#define qca_soc_reg_write(_addr, _val) ((*(volatile unsigned int *)KSEG1ADDR(_addr)) = (_val)) + +#define qca_soc_reg_read_set(_addr, _mask) \ + qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) | (_mask))) + +#define qca_soc_reg_read_clear(_addr, _mask) \ + qca_soc_reg_write((_addr), (qca_soc_reg_read((_addr)) & ~(_mask))) + +#endif /* _QCA_SOC_COMMON_H_ */ diff --git a/u-boot/include/soc/soc_common.h b/u-boot/include/soc/soc_common.h new file mode 100644 index 0000000..17284cf --- /dev/null +++ b/u-boot/include/soc/soc_common.h @@ -0,0 +1,89 @@ +/* + * SOC common registers and helper function/macro definitions + * + * Copyright (C) 2014 Piotr Dymacz + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#ifndef _SOC_COMMON_H_ +#define _SOC_COMMON_H_ + +#include + +#ifndef SOC_TYPE + #error "SOC_TYPE is not defined!" +#endif + +/* + * GPIO registers BIT fields + */ +#define GPIO_X_MASK(_gpio) (1 << _gpio) +#define GPIO0 GPIO_X_MASK(0) +#define GPIO1 GPIO_X_MASK(1) +#define GPIO2 GPIO_X_MASK(2) +#define GPIO3 GPIO_X_MASK(3) +#define GPIO4 GPIO_X_MASK(4) +#define GPIO5 GPIO_X_MASK(5) +#define GPIO6 GPIO_X_MASK(6) +#define GPIO7 GPIO_X_MASK(7) +#define GPIO8 GPIO_X_MASK(8) +#define GPIO9 GPIO_X_MASK(9) +#define GPIO10 GPIO_X_MASK(10) +#define GPIO11 GPIO_X_MASK(11) +#define GPIO12 GPIO_X_MASK(12) +#define GPIO13 GPIO_X_MASK(13) +#define GPIO14 GPIO_X_MASK(14) +#define GPIO15 GPIO_X_MASK(15) +#define GPIO16 GPIO_X_MASK(16) +#define GPIO17 GPIO_X_MASK(17) +#define GPIO18 GPIO_X_MASK(18) +#define GPIO19 GPIO_X_MASK(19) +#define GPIO20 GPIO_X_MASK(20) +#define GPIO21 GPIO_X_MASK(21) +#define GPIO22 GPIO_X_MASK(22) +#define GPIO23 GPIO_X_MASK(23) +#define GPIO24 GPIO_X_MASK(24) +#define GPIO25 GPIO_X_MASK(25) +#define GPIO26 GPIO_X_MASK(26) +#define GPIO27 GPIO_X_MASK(27) +#define GPIO28 GPIO_X_MASK(28) +#define GPIO29 GPIO_X_MASK(29) +#define GPIO30 GPIO_X_MASK(30) +#define GPIO31 GPIO_X_MASK(31) +#define GPIO32 GPIO_X_MASK(32) +#define GPIO33 GPIO_X_MASK(33) +#define GPIO34 GPIO_X_MASK(34) +#define GPIO35 GPIO_X_MASK(35) +#define GPIO36 GPIO_X_MASK(36) +#define GPIO37 GPIO_X_MASK(37) +#define GPIO38 GPIO_X_MASK(38) +#define GPIO39 GPIO_X_MASK(39) +#define GPIO40 GPIO_X_MASK(40) +#define GPIO41 GPIO_X_MASK(41) +#define GPIO42 GPIO_X_MASK(42) +#define GPIO43 GPIO_X_MASK(43) +#define GPIO44 GPIO_X_MASK(44) +#define GPIO45 GPIO_X_MASK(45) +#define GPIO46 GPIO_X_MASK(46) +#define GPIO47 GPIO_X_MASK(47) +#define GPIO48 GPIO_X_MASK(48) +#define GPIO49 GPIO_X_MASK(49) +#define GPIO50 GPIO_X_MASK(50) + +/* + * Memory types + */ +#define RAM_MEMORY_TYPE_DDR1 1 +#define RAM_MEMORY_TYPE_DDR2 2 +#define RAM_MEMORY_TYPE_DDR3 3 +#define RAM_MEMORY_TYPE_SDR 4 +#define RAM_MEMORY_TYPE_UNKNOWN 5 + +/* + * Useful clock variables + */ +#define CLK_40MHz (40 * 1000 * 1000) +#define CLK_25MHz (25 * 1000 * 1000) + +#endif /* _SOC_COMMON_H_ */ -- 2.25.1