From 242b15476c94752494670a3e419e639d2df08dfd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 8 Sep 2015 16:55:42 +0200 Subject: [PATCH] net: zynq: Fix mdc clock division setting for 100Mbit/s Using set and clear macro is incorrect because it is not overwritting origin mdc clock division setup. For example origin setup is 8(0b001) and new setup is 64(0b100) which means 0b101 is setup which is 96 divider. Using writel to rewrite all setting like for 1000Mbit/s case. Signed-off-by: Michal Simek Acked-by: Joe Hershberger --- drivers/net/zynq_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 56651e94bb..9d69c8408d 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -410,8 +410,8 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) clk_rate = ZYNQ_GEM_FREQUENCY_1000; break; case SPEED_100: - clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, - ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); + writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100, + ®s->nwcfg); clk_rate = ZYNQ_GEM_FREQUENCY_100; break; case SPEED_10: -- 2.25.1