From 1ea4fac5a34604e67504ee6537bb01e809528cd4 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Thu, 12 May 2016 12:14:41 +0100
Subject: [PATCH] arm/arm64: Move barrier instructions into separate header

Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory
barrier") broke compilation for the Pine64, as dram_helper.c now
includes <asm/armv7.h>, which does not compile on arm64.

Fix this by moving all barrier instructions into a separate header
file, which can easily be shared between arm and arm64.
Also extend the inline assembly to take the "sy" argument, which is
optional for ARMv7, but mandatory for v8.

This fixes compilation for 64-bit sunxi boards (Pine64).

Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 arch/arm/include/asm/armv7.h       | 21 +-------------
 arch/arm/include/asm/barriers.h    | 44 ++++++++++++++++++++++++++++++
 arch/arm/mach-sunxi/dram_helpers.c |  2 +-
 3 files changed, 46 insertions(+), 21 deletions(-)
 create mode 100644 arch/arm/include/asm/barriers.h

diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 30e7939d8e..423fc70111 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -59,26 +59,7 @@
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
 #include <asm/io.h>
-
-/*
- * CP15 Barrier instructions
- * Please note that we have separate barrier instructions in ARMv7
- * However, we use the CP15 based instructtions because we use
- * -march=armv5 in U-Boot
- */
-#define CP15ISB	asm volatile ("mcr     p15, 0, %0, c7, c5, 4" : : "r" (0))
-#define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
-#define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
-
-#ifdef __ARM_ARCH_7A__
-#define ISB	asm volatile ("isb" : : : "memory")
-#define DSB	asm volatile ("dsb" : : : "memory")
-#define DMB	asm volatile ("dmb" : : : "memory")
-#else
-#define ISB	CP15ISB
-#define DSB	CP15DSB
-#define DMB	CP15DMB
-#endif
+#include <asm/barriers.h>
 
 /*
  * Workaround for ARM errata # 798870
diff --git a/arch/arm/include/asm/barriers.h b/arch/arm/include/asm/barriers.h
new file mode 100644
index 0000000000..37870f9d71
--- /dev/null
+++ b/arch/arm/include/asm/barriers.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2016 ARM Ltd.
+ *
+ * ARM and ARM64 barrier instructions
+ * split from armv7.h to allow sharing between ARM and ARM64
+ *
+ * Original copyright in armv7.h was:
+ * (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com>
+ *
+ * Much of the original barrier code was contributed by:
+ *   Valentine Barshak <valentine.barshak@cogentembedded.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __BARRIERS_H__
+#define __BARRIERS_H__
+
+#ifndef __ASSEMBLY__
+
+#ifndef CONFIG_ARM64
+/*
+ * CP15 Barrier instructions
+ * Please note that we have separate barrier instructions in ARMv7
+ * However, we use the CP15 based instructtions because we use
+ * -march=armv5 in U-Boot
+ */
+#define CP15ISB	asm volatile ("mcr     p15, 0, %0, c7, c5, 4" : : "r" (0))
+#define CP15DSB	asm volatile ("mcr     p15, 0, %0, c7, c10, 4" : : "r" (0))
+#define CP15DMB	asm volatile ("mcr     p15, 0, %0, c7, c10, 5" : : "r" (0))
+
+#endif /* !CONFIG_ARM64 */
+
+#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64)
+#define ISB	asm volatile ("isb sy" : : : "memory")
+#define DSB	asm volatile ("dsb sy" : : : "memory")
+#define DMB	asm volatile ("dmb sy" : : : "memory")
+#else
+#define ISB	CP15ISB
+#define DSB	CP15DSB
+#define DMB	CP15DMB
+#endif
+
+#endif	/* __ASSEMBLY__ */
+#endif	/* __BARRIERS_H__ */
diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index e0c823a4dd..20b430f859 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -7,7 +7,7 @@
  */
 
 #include <common.h>
-#include <asm/armv7.h>
+#include <asm/barriers.h>
 #include <asm/io.h>
 #include <asm/arch/dram.h>
 
-- 
2.25.1