From 19e4a00965f03d5d64af00b7b4258dff43e57d17 Mon Sep 17 00:00:00 2001 From: Liu Gang Date: Sun, 14 Oct 2012 20:55:17 +0000 Subject: [PATCH] powerpc/boot: Change the compile macro for SRIO & PCIE boot master module Currently, the SRIO and PCIE boot master module will be compiled into the u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this macro has been included by all the corenet architecture platform boards. But in fact, it's uncertain whether all corenet platform boards support this feature. So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add a special macro for every board which can support the feature. This special macro will be defined in the header file "arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO and PCIE boot master module should be compiled into the board u-boot image. Signed-off-by: Liu Gang Signed-off-by: Andy Fleming --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc8xxx/srio.c | 4 +++- arch/powerpc/include/asm/config_mpc85xx.h | 4 ++++ drivers/pci/fsl_pci_init.c | 6 +++--- 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index e82c9517fe..736293c41d 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -524,7 +524,7 @@ skip_l2: #ifdef CONFIG_SYS_SRIO srio_init(); -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER char *s = getenv("bootmaster"); if (s) { if (!strcmp(s, "SRIO1")) { diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index d4f8ecee9b..6e6f7dcc3f 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -24,6 +24,7 @@ #include #include +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define SRIO_PORT_ACCEPT_ALL 0x10000001 #define SRIO_IB_ATMU_AR 0x80f55000 #define SRIO_OB_ATMU_AR_MAINT 0x80077000 @@ -32,6 +33,7 @@ #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */ #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */ #define SRIO_LCSBA1CSR 0x60000000 +#endif #if defined(CONFIG_FSL_CORENET) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 @@ -297,7 +299,7 @@ void srio_init(void) } } -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER void srio_boot_master(int port) { struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8a7c81b808..03baaee1b7 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -334,6 +334,7 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -365,6 +366,7 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -405,6 +407,7 @@ #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -436,6 +439,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index e8eb9d6db7..48ae16374d 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -211,7 +211,7 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, return 1; } -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER static void fsl_pcie_boot_master(pit_t *pi) { /* configure inbound window for slave's u-boot image */ @@ -388,7 +388,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) /* see if we are a PCIe or PCI controller */ pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER /* boot from PCIE --master */ char *s = getenv("bootmaster"); char pcie[6]; @@ -602,7 +602,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, if (fsl_is_pci_agent(hose)) { fsl_pci_config_unlock(hose); hose->last_busno = hose->first_busno; -#ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER } else { /* boot from PCIE --master releases slave's core 0 */ char *s = getenv("bootmaster"); -- 2.25.1