From 15bf9eb70d33508475c7bc88f27dc6cf0d53d50e Mon Sep 17 00:00:00 2001
From: Oleksij Rempel <linux@rempel-privat.de>
Date: Fri, 11 Oct 2013 07:47:39 -0700
Subject: [PATCH] Updated usb regs (markdown)

---
 usb-regs.md | 46 ++++++++++++++++++++++++++--------------------
 1 file changed, 26 insertions(+), 20 deletions(-)

diff --git a/usb-regs.md b/usb-regs.md
index 56c5361..837091d 100644
--- a/usb-regs.md
+++ b/usb-regs.md
@@ -15,17 +15,17 @@ Default
 
 
 # 0x00 ZM_MAIN_CTRL_OFFSET
-* BIT7
+* BIT7 - Forced to be Full-Speed Mod?
 * BIT6 - 1 = HighSpeed is set (read only?)
-* BIT5 - chip enable
-* BIT4 - sfrst. soft reset?
-* BIT3 - go suspend
-* BIT2 - 1 = enable global Int
-* BIT1
-* BIT0 - 1 = set Remote Wake Up;
+* BIT5 - Chip Enable
+* BIT4 - Chip Software Rese
+* BIT3 - Enter Suspend Mode
+* BIT2 - Enable global Int
+* BIT1 - Half speed mode for FPGA test
+* BIT0 - Enable remote wake-up;
 
 # 0x01 ZM_DEVICE_ADDRESS_OFFSET
-* BIT7 - usb config? (r/w)
+* BIT7 - SET_CONFIGURATION has been executed
 * BIT6
 * BIT5
 * BIT4
@@ -35,17 +35,23 @@ Default
 * BIT0
 
 # 0x02 ZM_TEST_OFFSET
-* BIT0 - 1 ?? set on usb 2.0 init
+* BIT6 - Do not generate SOF
+* BIT5 - Enter Test Mode
+* BIT4 - Do not toggle sequence
+* BIT3 - Do not append CRC
+* BIT2 - Clear External Side Address
+* BIT1 - EP0 loopback test
+* BIT0 - 1 ?? set on usb 2.0 init. Clear FIFO
 
 # 0x08 ZM_PHY_TEST_SELECT_OFFSET
 * BIT7
 * BIT6
 * BIT5
 * BIT4 - TEST_PKY - Test packed. 
-* BIT3 - TEST_SE0_NAK
-* BIT2 - TEST_K
-* BIT1 - TEST_J
-* BIT0
+* BIT3 - TEST_SE0_NAK. High-Speed quiescent state.
+* BIT2 - TEST_K, High-Speed K state
+* BIT1 - TEST_J, High-Speed J state
+* BIT0 - Enable soft-detachment
 
 According to FUSB200 doc:  
 DM(D-) DP(D+) Description  
@@ -62,13 +68,13 @@ If TEST_PKY is set, the test packet must be filled into FIFO by DMA first.
 
 # 0x0B ZM_CX_CONFIG_STATUS_OFFSET
 * BIT7
-* BIT6 - EP0 tx stall
-* BIT5 - indicator that frame was transmitted.
-* BIT4
-* BIT3 - set to drom the fram?
-* BIT2 - set CX_STL to stall Endpoint0 & will also clear FIFO0
-* BIT1 - 
-* BIT0 - set CX_DONE to indicate the transmistion of control frame
+* BIT6 -
+* BIT5 - CX FIFO empty
+* BIT4 - CX FIFO full
+* BIT3 - CX FIFO clear
+* BIT2 - set CX_STL, CX data stalled
+* BIT1 - Test packet data transfer finished
+* BIT0 - set CX_DONE, CX data transfer finished
 
 # 0x0C ZM_EP0_DATA_OFFSET
 * Write 32bit data to fifo
-- 
2.25.1