From 1416e2d22531c6d4ba9c9c8a4766cbe906ed7ce0 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 25 Jul 2018 00:57:01 +0100 Subject: [PATCH] armv8: make SPL exception vectors optional Even though the exception vector table is a fundamental part of the ARM architecture, U-Boot mostly does not make real use of it, except when crash dumping. But having it in takes up quite some space, partly due to the architectural alignment requirement of 2KB. Since we don't take special care of that, the compiler adds a more or less random amount of padding space, which increases the image size quite a bit, especially for the SPL. On a typical Allwinner build this is around 1.5KB of padding, plus 1KB for the vector table (mostly padding space again), then some extra code to do the actual handling. This amounts to almost 10% of the maximum image size, which is quite a lot for a pure debugging feature. Add a Kconfig symbol to allow the exception vector table to be left out of the build for the SPL. For now this is "default y" for everyone, but specific defconfigs, platforms or .config files can opt out here at will, to mitigate the code size pressure we see for some SPLs. Signed-off-by: Andre Przywara --- arch/arm/cpu/armv8/Kconfig | 11 +++++++++++ arch/arm/cpu/armv8/Makefile | 4 ++++ arch/arm/cpu/armv8/start.S | 19 +++++++++++++++---- 3 files changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 741e15c773..c8bebabdf6 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -1,5 +1,16 @@ if ARM64 +config ARMV8_SPL_EXCEPTION_VECTORS + bool "Install crash dump exception vectors" + depends on SPL + default y + help + The default exception vector table is only used for the crash + dump, but still takes quite a lot of space in the image size. + + Say N here if you are running out of code space in the image + and want to save some space at the cost of less debugging info. + config ARMV8_MULTIENTRY bool "Enable multiple CPUs to enter into U-Boot" diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index d1d4ffecfd..52c8daa049 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -10,7 +10,11 @@ ifndef CONFIG_$(SPL_TPL_)TIMER obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o endif obj-y += cache_v8.o +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o +else obj-y += exceptions.o +endif obj-y += cache.o obj-y += tlb.o obj-y += transition.o diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index d4db4d044f..12a78ee38b 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -86,14 +86,23 @@ pie_fixup_done: #ifdef CONFIG_SYS_RESET_SCTRL bl reset_sctrl +#endif + +#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) +.macro set_vbar, regname, reg + msr \regname, \reg +.endm + adr x0, vectors +#else +.macro set_vbar, regname, reg +.endm #endif /* * Could be EL3/EL2/EL1, Initial State: * Little Endian, MMU Disabled, i/dCache Disabled */ - adr x0, vectors switch_el x1, 3f, 2f, 1f -3: msr vbar_el3, x0 +3: set_vbar vbar_el3, x0 mrs x0, scr_el3 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */ msr scr_el3, x0 @@ -103,11 +112,11 @@ pie_fixup_done: msr cntfrq_el0, x0 /* Initialize CNTFRQ */ #endif b 0f -2: msr vbar_el2, x0 +2: set_vbar vbar_el2, x0 mov x0, #0x33ff msr cptr_el2, x0 /* Enable FP/SIMD */ b 0f -1: msr vbar_el1, x0 +1: set_vbar vbar_el1, x0 mov x0, #3 << 20 msr cpacr_el1, x0 /* Enable FP/SIMD */ 0: @@ -345,6 +354,7 @@ ENDPROC(smp_kick_all_cpus) /*-----------------------------------------------------------------------*/ ENTRY(c_runtime_cpu_setup) +#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD) /* Relocate vBAR */ adr x0, vectors switch_el x1, 3f, 2f, 1f @@ -354,6 +364,7 @@ ENTRY(c_runtime_cpu_setup) b 0f 1: msr vbar_el1, x0 0: +#endif ret ENDPROC(c_runtime_cpu_setup) -- 2.25.1